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ac718b69 | 1 | /* |
c7de7dec | 2 | * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved. |
ac718b69 | 3 | * |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * version 2 as published by the Free Software Foundation. | |
7 | * | |
8 | */ | |
9 | ||
ac718b69 | 10 | #include <linux/signal.h> |
11 | #include <linux/slab.h> | |
12 | #include <linux/module.h> | |
ac718b69 | 13 | #include <linux/netdevice.h> |
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/mii.h> | |
16 | #include <linux/ethtool.h> | |
17 | #include <linux/usb.h> | |
18 | #include <linux/crc32.h> | |
19 | #include <linux/if_vlan.h> | |
20 | #include <linux/uaccess.h> | |
ebc2ec48 | 21 | #include <linux/list.h> |
5bd23881 | 22 | #include <linux/ip.h> |
23 | #include <linux/ipv6.h> | |
ac718b69 | 24 | |
25 | /* Version Information */ | |
c7de7dec | 26 | #define DRIVER_VERSION "v1.04.0 (2014/01/15)" |
ac718b69 | 27 | #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>" |
44d942a9 | 28 | #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters" |
ac718b69 | 29 | #define MODULENAME "r8152" |
30 | ||
31 | #define R8152_PHY_ID 32 | |
32 | ||
33 | #define PLA_IDR 0xc000 | |
34 | #define PLA_RCR 0xc010 | |
35 | #define PLA_RMS 0xc016 | |
36 | #define PLA_RXFIFO_CTRL0 0xc0a0 | |
37 | #define PLA_RXFIFO_CTRL1 0xc0a4 | |
38 | #define PLA_RXFIFO_CTRL2 0xc0a8 | |
39 | #define PLA_FMC 0xc0b4 | |
40 | #define PLA_CFG_WOL 0xc0b6 | |
43779f8d | 41 | #define PLA_TEREDO_CFG 0xc0bc |
ac718b69 | 42 | #define PLA_MAR 0xcd00 |
43779f8d | 43 | #define PLA_BACKUP 0xd000 |
ac718b69 | 44 | #define PAL_BDC_CR 0xd1a0 |
43779f8d | 45 | #define PLA_TEREDO_TIMER 0xd2cc |
46 | #define PLA_REALWOW_TIMER 0xd2e8 | |
ac718b69 | 47 | #define PLA_LEDSEL 0xdd90 |
48 | #define PLA_LED_FEATURE 0xdd92 | |
49 | #define PLA_PHYAR 0xde00 | |
43779f8d | 50 | #define PLA_BOOT_CTRL 0xe004 |
ac718b69 | 51 | #define PLA_GPHY_INTR_IMR 0xe022 |
52 | #define PLA_EEE_CR 0xe040 | |
53 | #define PLA_EEEP_CR 0xe080 | |
54 | #define PLA_MAC_PWR_CTRL 0xe0c0 | |
43779f8d | 55 | #define PLA_MAC_PWR_CTRL2 0xe0ca |
56 | #define PLA_MAC_PWR_CTRL3 0xe0cc | |
57 | #define PLA_MAC_PWR_CTRL4 0xe0ce | |
58 | #define PLA_WDT6_CTRL 0xe428 | |
ac718b69 | 59 | #define PLA_TCR0 0xe610 |
60 | #define PLA_TCR1 0xe612 | |
61 | #define PLA_TXFIFO_CTRL 0xe618 | |
62 | #define PLA_RSTTELLY 0xe800 | |
63 | #define PLA_CR 0xe813 | |
64 | #define PLA_CRWECR 0xe81c | |
65 | #define PLA_CONFIG5 0xe822 | |
66 | #define PLA_PHY_PWR 0xe84c | |
67 | #define PLA_OOB_CTRL 0xe84f | |
68 | #define PLA_CPCR 0xe854 | |
69 | #define PLA_MISC_0 0xe858 | |
70 | #define PLA_MISC_1 0xe85a | |
71 | #define PLA_OCP_GPHY_BASE 0xe86c | |
72 | #define PLA_TELLYCNT 0xe890 | |
73 | #define PLA_SFF_STS_7 0xe8de | |
74 | #define PLA_PHYSTATUS 0xe908 | |
75 | #define PLA_BP_BA 0xfc26 | |
76 | #define PLA_BP_0 0xfc28 | |
77 | #define PLA_BP_1 0xfc2a | |
78 | #define PLA_BP_2 0xfc2c | |
79 | #define PLA_BP_3 0xfc2e | |
80 | #define PLA_BP_4 0xfc30 | |
81 | #define PLA_BP_5 0xfc32 | |
82 | #define PLA_BP_6 0xfc34 | |
83 | #define PLA_BP_7 0xfc36 | |
43779f8d | 84 | #define PLA_BP_EN 0xfc38 |
ac718b69 | 85 | |
43779f8d | 86 | #define USB_U2P3_CTRL 0xb460 |
ac718b69 | 87 | #define USB_DEV_STAT 0xb808 |
88 | #define USB_USB_CTRL 0xd406 | |
89 | #define USB_PHY_CTRL 0xd408 | |
90 | #define USB_TX_AGG 0xd40a | |
91 | #define USB_RX_BUF_TH 0xd40c | |
92 | #define USB_USB_TIMER 0xd428 | |
43779f8d | 93 | #define USB_RX_EARLY_AGG 0xd42c |
ac718b69 | 94 | #define USB_PM_CTRL_STATUS 0xd432 |
95 | #define USB_TX_DMA 0xd434 | |
43779f8d | 96 | #define USB_TOLERANCE 0xd490 |
97 | #define USB_LPM_CTRL 0xd41a | |
ac718b69 | 98 | #define USB_UPS_CTRL 0xd800 |
43779f8d | 99 | #define USB_MISC_0 0xd81a |
100 | #define USB_POWER_CUT 0xd80a | |
101 | #define USB_AFE_CTRL2 0xd824 | |
102 | #define USB_WDT11_CTRL 0xe43c | |
ac718b69 | 103 | #define USB_BP_BA 0xfc26 |
104 | #define USB_BP_0 0xfc28 | |
105 | #define USB_BP_1 0xfc2a | |
106 | #define USB_BP_2 0xfc2c | |
107 | #define USB_BP_3 0xfc2e | |
108 | #define USB_BP_4 0xfc30 | |
109 | #define USB_BP_5 0xfc32 | |
110 | #define USB_BP_6 0xfc34 | |
111 | #define USB_BP_7 0xfc36 | |
43779f8d | 112 | #define USB_BP_EN 0xfc38 |
ac718b69 | 113 | |
114 | /* OCP Registers */ | |
115 | #define OCP_ALDPS_CONFIG 0x2010 | |
116 | #define OCP_EEE_CONFIG1 0x2080 | |
117 | #define OCP_EEE_CONFIG2 0x2092 | |
118 | #define OCP_EEE_CONFIG3 0x2094 | |
ac244d3e | 119 | #define OCP_BASE_MII 0xa400 |
ac718b69 | 120 | #define OCP_EEE_AR 0xa41a |
121 | #define OCP_EEE_DATA 0xa41c | |
43779f8d | 122 | #define OCP_PHY_STATUS 0xa420 |
123 | #define OCP_POWER_CFG 0xa430 | |
124 | #define OCP_EEE_CFG 0xa432 | |
125 | #define OCP_SRAM_ADDR 0xa436 | |
126 | #define OCP_SRAM_DATA 0xa438 | |
127 | #define OCP_DOWN_SPEED 0xa442 | |
128 | #define OCP_EEE_CFG2 0xa5d0 | |
129 | #define OCP_ADC_CFG 0xbc06 | |
130 | ||
131 | /* SRAM Register */ | |
132 | #define SRAM_LPF_CFG 0x8012 | |
133 | #define SRAM_10M_AMP1 0x8080 | |
134 | #define SRAM_10M_AMP2 0x8082 | |
135 | #define SRAM_IMPEDANCE 0x8084 | |
ac718b69 | 136 | |
137 | /* PLA_RCR */ | |
138 | #define RCR_AAP 0x00000001 | |
139 | #define RCR_APM 0x00000002 | |
140 | #define RCR_AM 0x00000004 | |
141 | #define RCR_AB 0x00000008 | |
142 | #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB) | |
143 | ||
144 | /* PLA_RXFIFO_CTRL0 */ | |
145 | #define RXFIFO_THR1_NORMAL 0x00080002 | |
146 | #define RXFIFO_THR1_OOB 0x01800003 | |
147 | ||
148 | /* PLA_RXFIFO_CTRL1 */ | |
149 | #define RXFIFO_THR2_FULL 0x00000060 | |
150 | #define RXFIFO_THR2_HIGH 0x00000038 | |
151 | #define RXFIFO_THR2_OOB 0x0000004a | |
43779f8d | 152 | #define RXFIFO_THR2_NORMAL 0x00a0 |
ac718b69 | 153 | |
154 | /* PLA_RXFIFO_CTRL2 */ | |
155 | #define RXFIFO_THR3_FULL 0x00000078 | |
156 | #define RXFIFO_THR3_HIGH 0x00000048 | |
157 | #define RXFIFO_THR3_OOB 0x0000005a | |
43779f8d | 158 | #define RXFIFO_THR3_NORMAL 0x0110 |
ac718b69 | 159 | |
160 | /* PLA_TXFIFO_CTRL */ | |
161 | #define TXFIFO_THR_NORMAL 0x00400008 | |
43779f8d | 162 | #define TXFIFO_THR_NORMAL2 0x01000008 |
ac718b69 | 163 | |
164 | /* PLA_FMC */ | |
165 | #define FMC_FCR_MCU_EN 0x0001 | |
166 | ||
167 | /* PLA_EEEP_CR */ | |
168 | #define EEEP_CR_EEEP_TX 0x0002 | |
169 | ||
43779f8d | 170 | /* PLA_WDT6_CTRL */ |
171 | #define WDT6_SET_MODE 0x0010 | |
172 | ||
ac718b69 | 173 | /* PLA_TCR0 */ |
174 | #define TCR0_TX_EMPTY 0x0800 | |
175 | #define TCR0_AUTO_FIFO 0x0080 | |
176 | ||
177 | /* PLA_TCR1 */ | |
178 | #define VERSION_MASK 0x7cf0 | |
179 | ||
180 | /* PLA_CR */ | |
181 | #define CR_RST 0x10 | |
182 | #define CR_RE 0x08 | |
183 | #define CR_TE 0x04 | |
184 | ||
185 | /* PLA_CRWECR */ | |
186 | #define CRWECR_NORAML 0x00 | |
187 | #define CRWECR_CONFIG 0xc0 | |
188 | ||
189 | /* PLA_OOB_CTRL */ | |
190 | #define NOW_IS_OOB 0x80 | |
191 | #define TXFIFO_EMPTY 0x20 | |
192 | #define RXFIFO_EMPTY 0x10 | |
193 | #define LINK_LIST_READY 0x02 | |
194 | #define DIS_MCU_CLROOB 0x01 | |
195 | #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY) | |
196 | ||
197 | /* PLA_MISC_1 */ | |
198 | #define RXDY_GATED_EN 0x0008 | |
199 | ||
200 | /* PLA_SFF_STS_7 */ | |
201 | #define RE_INIT_LL 0x8000 | |
202 | #define MCU_BORW_EN 0x4000 | |
203 | ||
204 | /* PLA_CPCR */ | |
205 | #define CPCR_RX_VLAN 0x0040 | |
206 | ||
207 | /* PLA_CFG_WOL */ | |
208 | #define MAGIC_EN 0x0001 | |
209 | ||
43779f8d | 210 | /* PLA_TEREDO_CFG */ |
211 | #define TEREDO_SEL 0x8000 | |
212 | #define TEREDO_WAKE_MASK 0x7f00 | |
213 | #define TEREDO_RS_EVENT_MASK 0x00fe | |
214 | #define OOB_TEREDO_EN 0x0001 | |
215 | ||
ac718b69 | 216 | /* PAL_BDC_CR */ |
217 | #define ALDPS_PROXY_MODE 0x0001 | |
218 | ||
219 | /* PLA_CONFIG5 */ | |
220 | #define LAN_WAKE_EN 0x0002 | |
221 | ||
222 | /* PLA_LED_FEATURE */ | |
223 | #define LED_MODE_MASK 0x0700 | |
224 | ||
225 | /* PLA_PHY_PWR */ | |
226 | #define TX_10M_IDLE_EN 0x0080 | |
227 | #define PFM_PWM_SWITCH 0x0040 | |
228 | ||
229 | /* PLA_MAC_PWR_CTRL */ | |
230 | #define D3_CLK_GATED_EN 0x00004000 | |
231 | #define MCU_CLK_RATIO 0x07010f07 | |
232 | #define MCU_CLK_RATIO_MASK 0x0f0f0f0f | |
43779f8d | 233 | #define ALDPS_SPDWN_RATIO 0x0f87 |
234 | ||
235 | /* PLA_MAC_PWR_CTRL2 */ | |
236 | #define EEE_SPDWN_RATIO 0x8007 | |
237 | ||
238 | /* PLA_MAC_PWR_CTRL3 */ | |
239 | #define PKT_AVAIL_SPDWN_EN 0x0100 | |
240 | #define SUSPEND_SPDWN_EN 0x0004 | |
241 | #define U1U2_SPDWN_EN 0x0002 | |
242 | #define L1_SPDWN_EN 0x0001 | |
243 | ||
244 | /* PLA_MAC_PWR_CTRL4 */ | |
245 | #define PWRSAVE_SPDWN_EN 0x1000 | |
246 | #define RXDV_SPDWN_EN 0x0800 | |
247 | #define TX10MIDLE_EN 0x0100 | |
248 | #define TP100_SPDWN_EN 0x0020 | |
249 | #define TP500_SPDWN_EN 0x0010 | |
250 | #define TP1000_SPDWN_EN 0x0008 | |
251 | #define EEE_SPDWN_EN 0x0001 | |
ac718b69 | 252 | |
253 | /* PLA_GPHY_INTR_IMR */ | |
254 | #define GPHY_STS_MSK 0x0001 | |
255 | #define SPEED_DOWN_MSK 0x0002 | |
256 | #define SPDWN_RXDV_MSK 0x0004 | |
257 | #define SPDWN_LINKCHG_MSK 0x0008 | |
258 | ||
259 | /* PLA_PHYAR */ | |
260 | #define PHYAR_FLAG 0x80000000 | |
261 | ||
262 | /* PLA_EEE_CR */ | |
263 | #define EEE_RX_EN 0x0001 | |
264 | #define EEE_TX_EN 0x0002 | |
265 | ||
43779f8d | 266 | /* PLA_BOOT_CTRL */ |
267 | #define AUTOLOAD_DONE 0x0002 | |
268 | ||
ac718b69 | 269 | /* USB_DEV_STAT */ |
270 | #define STAT_SPEED_MASK 0x0006 | |
271 | #define STAT_SPEED_HIGH 0x0000 | |
272 | #define STAT_SPEED_FULL 0x0001 | |
273 | ||
274 | /* USB_TX_AGG */ | |
275 | #define TX_AGG_MAX_THRESHOLD 0x03 | |
276 | ||
277 | /* USB_RX_BUF_TH */ | |
43779f8d | 278 | #define RX_THR_SUPPER 0x0c350180 |
8e1f51bd | 279 | #define RX_THR_HIGH 0x7a120180 |
43779f8d | 280 | #define RX_THR_SLOW 0xffff0180 |
ac718b69 | 281 | |
282 | /* USB_TX_DMA */ | |
283 | #define TEST_MODE_DISABLE 0x00000001 | |
284 | #define TX_SIZE_ADJUST1 0x00000100 | |
285 | ||
286 | /* USB_UPS_CTRL */ | |
287 | #define POWER_CUT 0x0100 | |
288 | ||
289 | /* USB_PM_CTRL_STATUS */ | |
8e1f51bd | 290 | #define RESUME_INDICATE 0x0001 |
ac718b69 | 291 | |
292 | /* USB_USB_CTRL */ | |
293 | #define RX_AGG_DISABLE 0x0010 | |
294 | ||
43779f8d | 295 | /* USB_U2P3_CTRL */ |
296 | #define U2P3_ENABLE 0x0001 | |
297 | ||
298 | /* USB_POWER_CUT */ | |
299 | #define PWR_EN 0x0001 | |
300 | #define PHASE2_EN 0x0008 | |
301 | ||
302 | /* USB_MISC_0 */ | |
303 | #define PCUT_STATUS 0x0001 | |
304 | ||
305 | /* USB_RX_EARLY_AGG */ | |
306 | #define EARLY_AGG_SUPPER 0x0e832981 | |
307 | #define EARLY_AGG_HIGH 0x0e837a12 | |
308 | #define EARLY_AGG_SLOW 0x0e83ffff | |
309 | ||
310 | /* USB_WDT11_CTRL */ | |
311 | #define TIMER11_EN 0x0001 | |
312 | ||
313 | /* USB_LPM_CTRL */ | |
314 | #define LPM_TIMER_MASK 0x0c | |
315 | #define LPM_TIMER_500MS 0x04 /* 500 ms */ | |
316 | #define LPM_TIMER_500US 0x0c /* 500 us */ | |
317 | ||
318 | /* USB_AFE_CTRL2 */ | |
319 | #define SEN_VAL_MASK 0xf800 | |
320 | #define SEN_VAL_NORMAL 0xa000 | |
321 | #define SEL_RXIDLE 0x0100 | |
322 | ||
ac718b69 | 323 | /* OCP_ALDPS_CONFIG */ |
324 | #define ENPWRSAVE 0x8000 | |
325 | #define ENPDNPS 0x0200 | |
326 | #define LINKENA 0x0100 | |
327 | #define DIS_SDSAVE 0x0010 | |
328 | ||
43779f8d | 329 | /* OCP_PHY_STATUS */ |
330 | #define PHY_STAT_MASK 0x0007 | |
331 | #define PHY_STAT_LAN_ON 3 | |
332 | #define PHY_STAT_PWRDN 5 | |
333 | ||
334 | /* OCP_POWER_CFG */ | |
335 | #define EEE_CLKDIV_EN 0x8000 | |
336 | #define EN_ALDPS 0x0004 | |
337 | #define EN_10M_PLLOFF 0x0001 | |
338 | ||
ac718b69 | 339 | /* OCP_EEE_CONFIG1 */ |
340 | #define RG_TXLPI_MSK_HFDUP 0x8000 | |
341 | #define RG_MATCLR_EN 0x4000 | |
342 | #define EEE_10_CAP 0x2000 | |
343 | #define EEE_NWAY_EN 0x1000 | |
344 | #define TX_QUIET_EN 0x0200 | |
345 | #define RX_QUIET_EN 0x0100 | |
346 | #define SDRISETIME 0x0010 /* bit 4 ~ 6 */ | |
347 | #define RG_RXLPI_MSK_HFDUP 0x0008 | |
348 | #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */ | |
349 | ||
350 | /* OCP_EEE_CONFIG2 */ | |
351 | #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */ | |
352 | #define RG_DACQUIET_EN 0x0400 | |
353 | #define RG_LDVQUIET_EN 0x0200 | |
354 | #define RG_CKRSEL 0x0020 | |
355 | #define RG_EEEPRG_EN 0x0010 | |
356 | ||
357 | /* OCP_EEE_CONFIG3 */ | |
358 | #define FST_SNR_EYE_R 0x1500 /* bit 7 ~ 15 */ | |
359 | #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */ | |
360 | #define MSK_PH 0x0006 /* bit 0 ~ 3 */ | |
361 | ||
362 | /* OCP_EEE_AR */ | |
363 | /* bit[15:14] function */ | |
364 | #define FUN_ADDR 0x0000 | |
365 | #define FUN_DATA 0x4000 | |
366 | /* bit[4:0] device addr */ | |
367 | #define DEVICE_ADDR 0x0007 | |
368 | ||
369 | /* OCP_EEE_DATA */ | |
370 | #define EEE_ADDR 0x003C | |
371 | #define EEE_DATA 0x0002 | |
372 | ||
43779f8d | 373 | /* OCP_EEE_CFG */ |
374 | #define CTAP_SHORT_EN 0x0040 | |
375 | #define EEE10_EN 0x0010 | |
376 | ||
377 | /* OCP_DOWN_SPEED */ | |
378 | #define EN_10M_BGOFF 0x0080 | |
379 | ||
380 | /* OCP_EEE_CFG2 */ | |
381 | #define MY1000_EEE 0x0004 | |
382 | #define MY100_EEE 0x0002 | |
383 | ||
384 | /* OCP_ADC_CFG */ | |
385 | #define CKADSEL_L 0x0100 | |
386 | #define ADC_EN 0x0080 | |
387 | #define EN_EMI_L 0x0040 | |
388 | ||
389 | /* SRAM_LPF_CFG */ | |
390 | #define LPF_AUTO_TUNE 0x8000 | |
391 | ||
392 | /* SRAM_10M_AMP1 */ | |
393 | #define GDAC_IB_UPALL 0x0008 | |
394 | ||
395 | /* SRAM_10M_AMP2 */ | |
396 | #define AMP_DN 0x0200 | |
397 | ||
398 | /* SRAM_IMPEDANCE */ | |
399 | #define RX_DRIVING_MASK 0x6000 | |
400 | ||
ac718b69 | 401 | enum rtl_register_content { |
43779f8d | 402 | _1000bps = 0x10, |
ac718b69 | 403 | _100bps = 0x08, |
404 | _10bps = 0x04, | |
405 | LINK_STATUS = 0x02, | |
406 | FULL_DUP = 0x01, | |
407 | }; | |
408 | ||
ebc2ec48 | 409 | #define RTL8152_MAX_TX 10 |
410 | #define RTL8152_MAX_RX 10 | |
40a82917 | 411 | #define INTBUFSIZE 2 |
8e1f51bd | 412 | #define CRC_SIZE 4 |
413 | #define TX_ALIGN 4 | |
414 | #define RX_ALIGN 8 | |
40a82917 | 415 | |
416 | #define INTR_LINK 0x0004 | |
ebc2ec48 | 417 | |
ac718b69 | 418 | #define RTL8152_REQT_READ 0xc0 |
419 | #define RTL8152_REQT_WRITE 0x40 | |
420 | #define RTL8152_REQ_GET_REGS 0x05 | |
421 | #define RTL8152_REQ_SET_REGS 0x05 | |
422 | ||
423 | #define BYTE_EN_DWORD 0xff | |
424 | #define BYTE_EN_WORD 0x33 | |
425 | #define BYTE_EN_BYTE 0x11 | |
426 | #define BYTE_EN_SIX_BYTES 0x3f | |
427 | #define BYTE_EN_START_MASK 0x0f | |
428 | #define BYTE_EN_END_MASK 0xf0 | |
429 | ||
430 | #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN) | |
431 | #define RTL8152_TX_TIMEOUT (HZ) | |
432 | ||
433 | /* rtl8152 flags */ | |
434 | enum rtl8152_flags { | |
435 | RTL8152_UNPLUG = 0, | |
ac718b69 | 436 | RTL8152_SET_RX_MODE, |
40a82917 | 437 | WORK_ENABLE, |
438 | RTL8152_LINK_CHG, | |
ac718b69 | 439 | }; |
440 | ||
441 | /* Define these values to match your device */ | |
442 | #define VENDOR_ID_REALTEK 0x0bda | |
443 | #define PRODUCT_ID_RTL8152 0x8152 | |
43779f8d | 444 | #define PRODUCT_ID_RTL8153 0x8153 |
445 | ||
446 | #define VENDOR_ID_SAMSUNG 0x04e8 | |
447 | #define PRODUCT_ID_SAMSUNG 0xa101 | |
ac718b69 | 448 | |
449 | #define MCU_TYPE_PLA 0x0100 | |
450 | #define MCU_TYPE_USB 0x0000 | |
451 | ||
c7de7dec | 452 | #define REALTEK_USB_DEVICE(vend, prod) \ |
453 | USB_DEVICE_INTERFACE_CLASS(vend, prod, USB_CLASS_VENDOR_SPEC) | |
454 | ||
ac718b69 | 455 | struct rx_desc { |
500b6d7e | 456 | __le32 opts1; |
ac718b69 | 457 | #define RX_LEN_MASK 0x7fff |
500b6d7e | 458 | __le32 opts2; |
459 | __le32 opts3; | |
460 | __le32 opts4; | |
461 | __le32 opts5; | |
462 | __le32 opts6; | |
ac718b69 | 463 | }; |
464 | ||
465 | struct tx_desc { | |
500b6d7e | 466 | __le32 opts1; |
ac718b69 | 467 | #define TX_FS (1 << 31) /* First segment of a packet */ |
468 | #define TX_LS (1 << 30) /* Final segment of a packet */ | |
5bd23881 | 469 | #define TX_LEN_MASK 0x3ffff |
470 | ||
500b6d7e | 471 | __le32 opts2; |
5bd23881 | 472 | #define UDP_CS (1 << 31) /* Calculate UDP/IP checksum */ |
473 | #define TCP_CS (1 << 30) /* Calculate TCP/IP checksum */ | |
474 | #define IPV4_CS (1 << 29) /* Calculate IPv4 checksum */ | |
475 | #define IPV6_CS (1 << 28) /* Calculate IPv6 checksum */ | |
ac718b69 | 476 | }; |
477 | ||
dff4e8ad | 478 | struct r8152; |
479 | ||
ebc2ec48 | 480 | struct rx_agg { |
481 | struct list_head list; | |
482 | struct urb *urb; | |
dff4e8ad | 483 | struct r8152 *context; |
ebc2ec48 | 484 | void *buffer; |
485 | void *head; | |
486 | }; | |
487 | ||
488 | struct tx_agg { | |
489 | struct list_head list; | |
490 | struct urb *urb; | |
dff4e8ad | 491 | struct r8152 *context; |
ebc2ec48 | 492 | void *buffer; |
493 | void *head; | |
494 | u32 skb_num; | |
495 | u32 skb_len; | |
496 | }; | |
497 | ||
ac718b69 | 498 | struct r8152 { |
499 | unsigned long flags; | |
500 | struct usb_device *udev; | |
501 | struct tasklet_struct tl; | |
40a82917 | 502 | struct usb_interface *intf; |
ac718b69 | 503 | struct net_device *netdev; |
40a82917 | 504 | struct urb *intr_urb; |
ebc2ec48 | 505 | struct tx_agg tx_info[RTL8152_MAX_TX]; |
506 | struct rx_agg rx_info[RTL8152_MAX_RX]; | |
507 | struct list_head rx_done, tx_free; | |
508 | struct sk_buff_head tx_queue; | |
509 | spinlock_t rx_lock, tx_lock; | |
ac718b69 | 510 | struct delayed_work schedule; |
511 | struct mii_if_info mii; | |
c81229c9 | 512 | |
513 | struct rtl_ops { | |
514 | void (*init)(struct r8152 *); | |
515 | int (*enable)(struct r8152 *); | |
516 | void (*disable)(struct r8152 *); | |
517 | void (*down)(struct r8152 *); | |
518 | void (*unload)(struct r8152 *); | |
519 | } rtl_ops; | |
520 | ||
40a82917 | 521 | int intr_interval; |
ac718b69 | 522 | u32 msg_enable; |
dd1b119c | 523 | u32 tx_qlen; |
ac718b69 | 524 | u16 ocp_base; |
40a82917 | 525 | u8 *intr_buff; |
ac718b69 | 526 | u8 version; |
527 | u8 speed; | |
528 | }; | |
529 | ||
530 | enum rtl_version { | |
531 | RTL_VER_UNKNOWN = 0, | |
532 | RTL_VER_01, | |
43779f8d | 533 | RTL_VER_02, |
534 | RTL_VER_03, | |
535 | RTL_VER_04, | |
536 | RTL_VER_05, | |
537 | RTL_VER_MAX | |
ac718b69 | 538 | }; |
539 | ||
540 | /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). | |
541 | * The RTL chips use a 64 element hash table based on the Ethernet CRC. | |
542 | */ | |
543 | static const int multicast_filter_limit = 32; | |
ebc2ec48 | 544 | static unsigned int rx_buf_sz = 16384; |
ac718b69 | 545 | |
546 | static | |
547 | int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) | |
548 | { | |
31787f53 | 549 | int ret; |
550 | void *tmp; | |
551 | ||
552 | tmp = kmalloc(size, GFP_KERNEL); | |
553 | if (!tmp) | |
554 | return -ENOMEM; | |
555 | ||
556 | ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0), | |
ac718b69 | 557 | RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, |
31787f53 | 558 | value, index, tmp, size, 500); |
559 | ||
560 | memcpy(data, tmp, size); | |
561 | kfree(tmp); | |
562 | ||
563 | return ret; | |
ac718b69 | 564 | } |
565 | ||
566 | static | |
567 | int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) | |
568 | { | |
31787f53 | 569 | int ret; |
570 | void *tmp; | |
571 | ||
572 | tmp = kmalloc(size, GFP_KERNEL); | |
573 | if (!tmp) | |
574 | return -ENOMEM; | |
575 | ||
576 | memcpy(tmp, data, size); | |
577 | ||
578 | ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0), | |
ac718b69 | 579 | RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE, |
31787f53 | 580 | value, index, tmp, size, 500); |
581 | ||
582 | kfree(tmp); | |
583 | return ret; | |
ac718b69 | 584 | } |
585 | ||
586 | static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size, | |
587 | void *data, u16 type) | |
588 | { | |
45f4a19f | 589 | u16 limit = 64; |
590 | int ret = 0; | |
ac718b69 | 591 | |
592 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
593 | return -ENODEV; | |
594 | ||
595 | /* both size and indix must be 4 bytes align */ | |
596 | if ((size & 3) || !size || (index & 3) || !data) | |
597 | return -EPERM; | |
598 | ||
599 | if ((u32)index + (u32)size > 0xffff) | |
600 | return -EPERM; | |
601 | ||
602 | while (size) { | |
603 | if (size > limit) { | |
604 | ret = get_registers(tp, index, type, limit, data); | |
605 | if (ret < 0) | |
606 | break; | |
607 | ||
608 | index += limit; | |
609 | data += limit; | |
610 | size -= limit; | |
611 | } else { | |
612 | ret = get_registers(tp, index, type, size, data); | |
613 | if (ret < 0) | |
614 | break; | |
615 | ||
616 | index += size; | |
617 | data += size; | |
618 | size = 0; | |
619 | break; | |
620 | } | |
621 | } | |
622 | ||
623 | return ret; | |
624 | } | |
625 | ||
626 | static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, | |
627 | u16 size, void *data, u16 type) | |
628 | { | |
45f4a19f | 629 | int ret; |
630 | u16 byteen_start, byteen_end, byen; | |
631 | u16 limit = 512; | |
ac718b69 | 632 | |
633 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
634 | return -ENODEV; | |
635 | ||
636 | /* both size and indix must be 4 bytes align */ | |
637 | if ((size & 3) || !size || (index & 3) || !data) | |
638 | return -EPERM; | |
639 | ||
640 | if ((u32)index + (u32)size > 0xffff) | |
641 | return -EPERM; | |
642 | ||
643 | byteen_start = byteen & BYTE_EN_START_MASK; | |
644 | byteen_end = byteen & BYTE_EN_END_MASK; | |
645 | ||
646 | byen = byteen_start | (byteen_start << 4); | |
647 | ret = set_registers(tp, index, type | byen, 4, data); | |
648 | if (ret < 0) | |
649 | goto error1; | |
650 | ||
651 | index += 4; | |
652 | data += 4; | |
653 | size -= 4; | |
654 | ||
655 | if (size) { | |
656 | size -= 4; | |
657 | ||
658 | while (size) { | |
659 | if (size > limit) { | |
660 | ret = set_registers(tp, index, | |
661 | type | BYTE_EN_DWORD, | |
662 | limit, data); | |
663 | if (ret < 0) | |
664 | goto error1; | |
665 | ||
666 | index += limit; | |
667 | data += limit; | |
668 | size -= limit; | |
669 | } else { | |
670 | ret = set_registers(tp, index, | |
671 | type | BYTE_EN_DWORD, | |
672 | size, data); | |
673 | if (ret < 0) | |
674 | goto error1; | |
675 | ||
676 | index += size; | |
677 | data += size; | |
678 | size = 0; | |
679 | break; | |
680 | } | |
681 | } | |
682 | ||
683 | byen = byteen_end | (byteen_end >> 4); | |
684 | ret = set_registers(tp, index, type | byen, 4, data); | |
685 | if (ret < 0) | |
686 | goto error1; | |
687 | } | |
688 | ||
689 | error1: | |
690 | return ret; | |
691 | } | |
692 | ||
693 | static inline | |
694 | int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) | |
695 | { | |
696 | return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA); | |
697 | } | |
698 | ||
699 | static inline | |
700 | int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) | |
701 | { | |
702 | return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA); | |
703 | } | |
704 | ||
705 | static inline | |
706 | int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) | |
707 | { | |
708 | return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB); | |
709 | } | |
710 | ||
711 | static inline | |
712 | int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) | |
713 | { | |
714 | return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB); | |
715 | } | |
716 | ||
717 | static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index) | |
718 | { | |
c8826de8 | 719 | __le32 data; |
ac718b69 | 720 | |
c8826de8 | 721 | generic_ocp_read(tp, index, sizeof(data), &data, type); |
ac718b69 | 722 | |
723 | return __le32_to_cpu(data); | |
724 | } | |
725 | ||
726 | static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data) | |
727 | { | |
c8826de8 | 728 | __le32 tmp = __cpu_to_le32(data); |
729 | ||
730 | generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type); | |
ac718b69 | 731 | } |
732 | ||
733 | static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index) | |
734 | { | |
735 | u32 data; | |
c8826de8 | 736 | __le32 tmp; |
ac718b69 | 737 | u8 shift = index & 2; |
738 | ||
739 | index &= ~3; | |
740 | ||
c8826de8 | 741 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 742 | |
c8826de8 | 743 | data = __le32_to_cpu(tmp); |
ac718b69 | 744 | data >>= (shift * 8); |
745 | data &= 0xffff; | |
746 | ||
747 | return (u16)data; | |
748 | } | |
749 | ||
750 | static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data) | |
751 | { | |
c8826de8 | 752 | u32 mask = 0xffff; |
753 | __le32 tmp; | |
ac718b69 | 754 | u16 byen = BYTE_EN_WORD; |
755 | u8 shift = index & 2; | |
756 | ||
757 | data &= mask; | |
758 | ||
759 | if (index & 2) { | |
760 | byen <<= shift; | |
761 | mask <<= (shift * 8); | |
762 | data <<= (shift * 8); | |
763 | index &= ~3; | |
764 | } | |
765 | ||
c8826de8 | 766 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 767 | |
c8826de8 | 768 | data |= __le32_to_cpu(tmp) & ~mask; |
769 | tmp = __cpu_to_le32(data); | |
ac718b69 | 770 | |
c8826de8 | 771 | generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); |
ac718b69 | 772 | } |
773 | ||
774 | static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index) | |
775 | { | |
776 | u32 data; | |
c8826de8 | 777 | __le32 tmp; |
ac718b69 | 778 | u8 shift = index & 3; |
779 | ||
780 | index &= ~3; | |
781 | ||
c8826de8 | 782 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 783 | |
c8826de8 | 784 | data = __le32_to_cpu(tmp); |
ac718b69 | 785 | data >>= (shift * 8); |
786 | data &= 0xff; | |
787 | ||
788 | return (u8)data; | |
789 | } | |
790 | ||
791 | static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data) | |
792 | { | |
c8826de8 | 793 | u32 mask = 0xff; |
794 | __le32 tmp; | |
ac718b69 | 795 | u16 byen = BYTE_EN_BYTE; |
796 | u8 shift = index & 3; | |
797 | ||
798 | data &= mask; | |
799 | ||
800 | if (index & 3) { | |
801 | byen <<= shift; | |
802 | mask <<= (shift * 8); | |
803 | data <<= (shift * 8); | |
804 | index &= ~3; | |
805 | } | |
806 | ||
c8826de8 | 807 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 808 | |
c8826de8 | 809 | data |= __le32_to_cpu(tmp) & ~mask; |
810 | tmp = __cpu_to_le32(data); | |
ac718b69 | 811 | |
c8826de8 | 812 | generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); |
ac718b69 | 813 | } |
814 | ||
ac244d3e | 815 | static u16 ocp_reg_read(struct r8152 *tp, u16 addr) |
e3fe0b1a | 816 | { |
817 | u16 ocp_base, ocp_index; | |
818 | ||
819 | ocp_base = addr & 0xf000; | |
820 | if (ocp_base != tp->ocp_base) { | |
821 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); | |
822 | tp->ocp_base = ocp_base; | |
823 | } | |
824 | ||
825 | ocp_index = (addr & 0x0fff) | 0xb000; | |
ac244d3e | 826 | return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index); |
e3fe0b1a | 827 | } |
828 | ||
ac244d3e | 829 | static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) |
ac718b69 | 830 | { |
ac244d3e | 831 | u16 ocp_base, ocp_index; |
ac718b69 | 832 | |
ac244d3e | 833 | ocp_base = addr & 0xf000; |
834 | if (ocp_base != tp->ocp_base) { | |
835 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); | |
836 | tp->ocp_base = ocp_base; | |
ac718b69 | 837 | } |
ac244d3e | 838 | |
839 | ocp_index = (addr & 0x0fff) | 0xb000; | |
840 | ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data); | |
ac718b69 | 841 | } |
842 | ||
ac244d3e | 843 | static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value) |
ac718b69 | 844 | { |
ac244d3e | 845 | ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value); |
846 | } | |
ac718b69 | 847 | |
ac244d3e | 848 | static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr) |
849 | { | |
850 | return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2); | |
ac718b69 | 851 | } |
852 | ||
43779f8d | 853 | static void sram_write(struct r8152 *tp, u16 addr, u16 data) |
854 | { | |
855 | ocp_reg_write(tp, OCP_SRAM_ADDR, addr); | |
856 | ocp_reg_write(tp, OCP_SRAM_DATA, data); | |
857 | } | |
858 | ||
859 | static u16 sram_read(struct r8152 *tp, u16 addr) | |
860 | { | |
861 | ocp_reg_write(tp, OCP_SRAM_ADDR, addr); | |
862 | return ocp_reg_read(tp, OCP_SRAM_DATA); | |
863 | } | |
864 | ||
ac718b69 | 865 | static int read_mii_word(struct net_device *netdev, int phy_id, int reg) |
866 | { | |
867 | struct r8152 *tp = netdev_priv(netdev); | |
868 | ||
869 | if (phy_id != R8152_PHY_ID) | |
870 | return -EINVAL; | |
871 | ||
872 | return r8152_mdio_read(tp, reg); | |
873 | } | |
874 | ||
875 | static | |
876 | void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val) | |
877 | { | |
878 | struct r8152 *tp = netdev_priv(netdev); | |
879 | ||
880 | if (phy_id != R8152_PHY_ID) | |
881 | return; | |
882 | ||
883 | r8152_mdio_write(tp, reg, val); | |
884 | } | |
885 | ||
ebc2ec48 | 886 | static |
887 | int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags); | |
888 | ||
ac718b69 | 889 | static inline void set_ethernet_addr(struct r8152 *tp) |
890 | { | |
891 | struct net_device *dev = tp->netdev; | |
31787f53 | 892 | u8 node_id[8] = {0}; |
ac718b69 | 893 | |
31787f53 | 894 | if (pla_ocp_read(tp, PLA_IDR, sizeof(node_id), node_id) < 0) |
ac718b69 | 895 | netif_notice(tp, probe, dev, "inet addr fail\n"); |
896 | else { | |
897 | memcpy(dev->dev_addr, node_id, dev->addr_len); | |
898 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); | |
899 | } | |
ac718b69 | 900 | } |
901 | ||
902 | static int rtl8152_set_mac_address(struct net_device *netdev, void *p) | |
903 | { | |
904 | struct r8152 *tp = netdev_priv(netdev); | |
905 | struct sockaddr *addr = p; | |
906 | ||
907 | if (!is_valid_ether_addr(addr->sa_data)) | |
908 | return -EADDRNOTAVAIL; | |
909 | ||
910 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
911 | ||
912 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
913 | pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data); | |
914 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
915 | ||
916 | return 0; | |
917 | } | |
918 | ||
ac718b69 | 919 | static struct net_device_stats *rtl8152_get_stats(struct net_device *dev) |
920 | { | |
921 | return &dev->stats; | |
922 | } | |
923 | ||
924 | static void read_bulk_callback(struct urb *urb) | |
925 | { | |
ac718b69 | 926 | struct net_device *netdev; |
a5a4f468 | 927 | unsigned long flags; |
ac718b69 | 928 | int status = urb->status; |
ebc2ec48 | 929 | struct rx_agg *agg; |
930 | struct r8152 *tp; | |
ac718b69 | 931 | int result; |
ac718b69 | 932 | |
ebc2ec48 | 933 | agg = urb->context; |
934 | if (!agg) | |
935 | return; | |
936 | ||
937 | tp = agg->context; | |
ac718b69 | 938 | if (!tp) |
939 | return; | |
ebc2ec48 | 940 | |
ac718b69 | 941 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
942 | return; | |
ebc2ec48 | 943 | |
944 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
945 | return; | |
946 | ||
ac718b69 | 947 | netdev = tp->netdev; |
7559fb2f | 948 | |
949 | /* When link down, the driver would cancel all bulks. */ | |
950 | /* This avoid the re-submitting bulk */ | |
ebc2ec48 | 951 | if (!netif_carrier_ok(netdev)) |
ac718b69 | 952 | return; |
953 | ||
ac718b69 | 954 | switch (status) { |
955 | case 0: | |
ebc2ec48 | 956 | if (urb->actual_length < ETH_ZLEN) |
957 | break; | |
958 | ||
a5a4f468 | 959 | spin_lock_irqsave(&tp->rx_lock, flags); |
ebc2ec48 | 960 | list_add_tail(&agg->list, &tp->rx_done); |
a5a4f468 | 961 | spin_unlock_irqrestore(&tp->rx_lock, flags); |
ebc2ec48 | 962 | tasklet_schedule(&tp->tl); |
963 | return; | |
ac718b69 | 964 | case -ESHUTDOWN: |
965 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
966 | netif_device_detach(tp->netdev); | |
ebc2ec48 | 967 | return; |
ac718b69 | 968 | case -ENOENT: |
969 | return; /* the urb is in unlink state */ | |
970 | case -ETIME: | |
4a8deae2 HW |
971 | if (net_ratelimit()) |
972 | netdev_warn(netdev, "maybe reset is needed?\n"); | |
ebc2ec48 | 973 | break; |
ac718b69 | 974 | default: |
4a8deae2 HW |
975 | if (net_ratelimit()) |
976 | netdev_warn(netdev, "Rx status %d\n", status); | |
ebc2ec48 | 977 | break; |
ac718b69 | 978 | } |
979 | ||
ebc2ec48 | 980 | result = r8152_submit_rx(tp, agg, GFP_ATOMIC); |
ac718b69 | 981 | if (result == -ENODEV) { |
982 | netif_device_detach(tp->netdev); | |
983 | } else if (result) { | |
a5a4f468 | 984 | spin_lock_irqsave(&tp->rx_lock, flags); |
ebc2ec48 | 985 | list_add_tail(&agg->list, &tp->rx_done); |
a5a4f468 | 986 | spin_unlock_irqrestore(&tp->rx_lock, flags); |
ebc2ec48 | 987 | tasklet_schedule(&tp->tl); |
ac718b69 | 988 | } |
ac718b69 | 989 | } |
990 | ||
ebc2ec48 | 991 | static void write_bulk_callback(struct urb *urb) |
ac718b69 | 992 | { |
ebc2ec48 | 993 | struct net_device_stats *stats; |
a5a4f468 | 994 | unsigned long flags; |
ebc2ec48 | 995 | struct tx_agg *agg; |
ac718b69 | 996 | struct r8152 *tp; |
ebc2ec48 | 997 | int status = urb->status; |
ac718b69 | 998 | |
ebc2ec48 | 999 | agg = urb->context; |
1000 | if (!agg) | |
ac718b69 | 1001 | return; |
1002 | ||
ebc2ec48 | 1003 | tp = agg->context; |
1004 | if (!tp) | |
1005 | return; | |
1006 | ||
1007 | stats = rtl8152_get_stats(tp->netdev); | |
1008 | if (status) { | |
4a8deae2 HW |
1009 | if (net_ratelimit()) |
1010 | netdev_warn(tp->netdev, "Tx status %d\n", status); | |
ebc2ec48 | 1011 | stats->tx_errors += agg->skb_num; |
ac718b69 | 1012 | } else { |
ebc2ec48 | 1013 | stats->tx_packets += agg->skb_num; |
1014 | stats->tx_bytes += agg->skb_len; | |
ac718b69 | 1015 | } |
1016 | ||
a5a4f468 | 1017 | spin_lock_irqsave(&tp->tx_lock, flags); |
ebc2ec48 | 1018 | list_add_tail(&agg->list, &tp->tx_free); |
a5a4f468 | 1019 | spin_unlock_irqrestore(&tp->tx_lock, flags); |
ebc2ec48 | 1020 | |
1021 | if (!netif_carrier_ok(tp->netdev)) | |
1022 | return; | |
1023 | ||
1024 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
1025 | return; | |
1026 | ||
1027 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
1028 | return; | |
1029 | ||
1030 | if (!skb_queue_empty(&tp->tx_queue)) | |
1031 | tasklet_schedule(&tp->tl); | |
ac718b69 | 1032 | } |
1033 | ||
40a82917 | 1034 | static void intr_callback(struct urb *urb) |
1035 | { | |
1036 | struct r8152 *tp; | |
500b6d7e | 1037 | __le16 *d; |
40a82917 | 1038 | int status = urb->status; |
1039 | int res; | |
1040 | ||
1041 | tp = urb->context; | |
1042 | if (!tp) | |
1043 | return; | |
1044 | ||
1045 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
1046 | return; | |
1047 | ||
1048 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
1049 | return; | |
1050 | ||
1051 | switch (status) { | |
1052 | case 0: /* success */ | |
1053 | break; | |
1054 | case -ECONNRESET: /* unlink */ | |
1055 | case -ESHUTDOWN: | |
1056 | netif_device_detach(tp->netdev); | |
1057 | case -ENOENT: | |
1058 | return; | |
1059 | case -EOVERFLOW: | |
1060 | netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n"); | |
1061 | goto resubmit; | |
1062 | /* -EPIPE: should clear the halt */ | |
1063 | default: | |
1064 | netif_info(tp, intr, tp->netdev, "intr status %d\n", status); | |
1065 | goto resubmit; | |
1066 | } | |
1067 | ||
1068 | d = urb->transfer_buffer; | |
1069 | if (INTR_LINK & __le16_to_cpu(d[0])) { | |
1070 | if (!(tp->speed & LINK_STATUS)) { | |
1071 | set_bit(RTL8152_LINK_CHG, &tp->flags); | |
1072 | schedule_delayed_work(&tp->schedule, 0); | |
1073 | } | |
1074 | } else { | |
1075 | if (tp->speed & LINK_STATUS) { | |
1076 | set_bit(RTL8152_LINK_CHG, &tp->flags); | |
1077 | schedule_delayed_work(&tp->schedule, 0); | |
1078 | } | |
1079 | } | |
1080 | ||
1081 | resubmit: | |
1082 | res = usb_submit_urb(urb, GFP_ATOMIC); | |
1083 | if (res == -ENODEV) | |
1084 | netif_device_detach(tp->netdev); | |
1085 | else if (res) | |
1086 | netif_err(tp, intr, tp->netdev, | |
4a8deae2 | 1087 | "can't resubmit intr, status %d\n", res); |
40a82917 | 1088 | } |
1089 | ||
ebc2ec48 | 1090 | static inline void *rx_agg_align(void *data) |
1091 | { | |
8e1f51bd | 1092 | return (void *)ALIGN((uintptr_t)data, RX_ALIGN); |
ebc2ec48 | 1093 | } |
1094 | ||
1095 | static inline void *tx_agg_align(void *data) | |
1096 | { | |
8e1f51bd | 1097 | return (void *)ALIGN((uintptr_t)data, TX_ALIGN); |
ebc2ec48 | 1098 | } |
1099 | ||
1100 | static void free_all_mem(struct r8152 *tp) | |
1101 | { | |
1102 | int i; | |
1103 | ||
1104 | for (i = 0; i < RTL8152_MAX_RX; i++) { | |
9629e3c0 | 1105 | usb_free_urb(tp->rx_info[i].urb); |
1106 | tp->rx_info[i].urb = NULL; | |
ebc2ec48 | 1107 | |
9629e3c0 | 1108 | kfree(tp->rx_info[i].buffer); |
1109 | tp->rx_info[i].buffer = NULL; | |
1110 | tp->rx_info[i].head = NULL; | |
ebc2ec48 | 1111 | } |
1112 | ||
1113 | for (i = 0; i < RTL8152_MAX_TX; i++) { | |
9629e3c0 | 1114 | usb_free_urb(tp->tx_info[i].urb); |
1115 | tp->tx_info[i].urb = NULL; | |
ebc2ec48 | 1116 | |
9629e3c0 | 1117 | kfree(tp->tx_info[i].buffer); |
1118 | tp->tx_info[i].buffer = NULL; | |
1119 | tp->tx_info[i].head = NULL; | |
ebc2ec48 | 1120 | } |
40a82917 | 1121 | |
9629e3c0 | 1122 | usb_free_urb(tp->intr_urb); |
1123 | tp->intr_urb = NULL; | |
40a82917 | 1124 | |
9629e3c0 | 1125 | kfree(tp->intr_buff); |
1126 | tp->intr_buff = NULL; | |
ebc2ec48 | 1127 | } |
1128 | ||
1129 | static int alloc_all_mem(struct r8152 *tp) | |
1130 | { | |
1131 | struct net_device *netdev = tp->netdev; | |
40a82917 | 1132 | struct usb_interface *intf = tp->intf; |
1133 | struct usb_host_interface *alt = intf->cur_altsetting; | |
1134 | struct usb_host_endpoint *ep_intr = alt->endpoint + 2; | |
ebc2ec48 | 1135 | struct urb *urb; |
1136 | int node, i; | |
1137 | u8 *buf; | |
1138 | ||
1139 | node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; | |
1140 | ||
1141 | spin_lock_init(&tp->rx_lock); | |
1142 | spin_lock_init(&tp->tx_lock); | |
1143 | INIT_LIST_HEAD(&tp->rx_done); | |
1144 | INIT_LIST_HEAD(&tp->tx_free); | |
1145 | skb_queue_head_init(&tp->tx_queue); | |
1146 | ||
1147 | for (i = 0; i < RTL8152_MAX_RX; i++) { | |
1148 | buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node); | |
1149 | if (!buf) | |
1150 | goto err1; | |
1151 | ||
1152 | if (buf != rx_agg_align(buf)) { | |
1153 | kfree(buf); | |
8e1f51bd | 1154 | buf = kmalloc_node(rx_buf_sz + RX_ALIGN, GFP_KERNEL, |
1155 | node); | |
ebc2ec48 | 1156 | if (!buf) |
1157 | goto err1; | |
1158 | } | |
1159 | ||
1160 | urb = usb_alloc_urb(0, GFP_KERNEL); | |
1161 | if (!urb) { | |
1162 | kfree(buf); | |
1163 | goto err1; | |
1164 | } | |
1165 | ||
1166 | INIT_LIST_HEAD(&tp->rx_info[i].list); | |
1167 | tp->rx_info[i].context = tp; | |
1168 | tp->rx_info[i].urb = urb; | |
1169 | tp->rx_info[i].buffer = buf; | |
1170 | tp->rx_info[i].head = rx_agg_align(buf); | |
1171 | } | |
1172 | ||
1173 | for (i = 0; i < RTL8152_MAX_TX; i++) { | |
1174 | buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node); | |
1175 | if (!buf) | |
1176 | goto err1; | |
1177 | ||
1178 | if (buf != tx_agg_align(buf)) { | |
1179 | kfree(buf); | |
8e1f51bd | 1180 | buf = kmalloc_node(rx_buf_sz + TX_ALIGN, GFP_KERNEL, |
1181 | node); | |
ebc2ec48 | 1182 | if (!buf) |
1183 | goto err1; | |
1184 | } | |
1185 | ||
1186 | urb = usb_alloc_urb(0, GFP_KERNEL); | |
1187 | if (!urb) { | |
1188 | kfree(buf); | |
1189 | goto err1; | |
1190 | } | |
1191 | ||
1192 | INIT_LIST_HEAD(&tp->tx_info[i].list); | |
1193 | tp->tx_info[i].context = tp; | |
1194 | tp->tx_info[i].urb = urb; | |
1195 | tp->tx_info[i].buffer = buf; | |
1196 | tp->tx_info[i].head = tx_agg_align(buf); | |
1197 | ||
1198 | list_add_tail(&tp->tx_info[i].list, &tp->tx_free); | |
1199 | } | |
1200 | ||
40a82917 | 1201 | tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL); |
1202 | if (!tp->intr_urb) | |
1203 | goto err1; | |
1204 | ||
1205 | tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL); | |
1206 | if (!tp->intr_buff) | |
1207 | goto err1; | |
1208 | ||
1209 | tp->intr_interval = (int)ep_intr->desc.bInterval; | |
1210 | usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3), | |
1211 | tp->intr_buff, INTBUFSIZE, intr_callback, | |
1212 | tp, tp->intr_interval); | |
1213 | ||
ebc2ec48 | 1214 | return 0; |
1215 | ||
1216 | err1: | |
1217 | free_all_mem(tp); | |
1218 | return -ENOMEM; | |
1219 | } | |
1220 | ||
0de98f6c | 1221 | static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp) |
1222 | { | |
1223 | struct tx_agg *agg = NULL; | |
1224 | unsigned long flags; | |
1225 | ||
1226 | spin_lock_irqsave(&tp->tx_lock, flags); | |
1227 | if (!list_empty(&tp->tx_free)) { | |
1228 | struct list_head *cursor; | |
1229 | ||
1230 | cursor = tp->tx_free.next; | |
1231 | list_del_init(cursor); | |
1232 | agg = list_entry(cursor, struct tx_agg, list); | |
1233 | } | |
1234 | spin_unlock_irqrestore(&tp->tx_lock, flags); | |
1235 | ||
1236 | return agg; | |
1237 | } | |
1238 | ||
5bd23881 | 1239 | static void |
1240 | r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, struct sk_buff *skb) | |
1241 | { | |
1242 | memset(desc, 0, sizeof(*desc)); | |
1243 | ||
1244 | desc->opts1 = cpu_to_le32((skb->len & TX_LEN_MASK) | TX_FS | TX_LS); | |
1245 | ||
1246 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
1247 | __be16 protocol; | |
1248 | u8 ip_protocol; | |
1249 | u32 opts2 = 0; | |
1250 | ||
1251 | if (skb->protocol == htons(ETH_P_8021Q)) | |
1252 | protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto; | |
1253 | else | |
1254 | protocol = skb->protocol; | |
1255 | ||
1256 | switch (protocol) { | |
1257 | case htons(ETH_P_IP): | |
1258 | opts2 |= IPV4_CS; | |
1259 | ip_protocol = ip_hdr(skb)->protocol; | |
1260 | break; | |
1261 | ||
1262 | case htons(ETH_P_IPV6): | |
1263 | opts2 |= IPV6_CS; | |
1264 | ip_protocol = ipv6_hdr(skb)->nexthdr; | |
1265 | break; | |
1266 | ||
1267 | default: | |
1268 | ip_protocol = IPPROTO_RAW; | |
1269 | break; | |
1270 | } | |
1271 | ||
1272 | if (ip_protocol == IPPROTO_TCP) { | |
1273 | opts2 |= TCP_CS; | |
1274 | opts2 |= (skb_transport_offset(skb) & 0x7fff) << 17; | |
1275 | } else if (ip_protocol == IPPROTO_UDP) { | |
1276 | opts2 |= UDP_CS; | |
1277 | } else { | |
1278 | WARN_ON_ONCE(1); | |
1279 | } | |
1280 | ||
1281 | desc->opts2 = cpu_to_le32(opts2); | |
1282 | } | |
1283 | } | |
1284 | ||
b1379d9a | 1285 | static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg) |
1286 | { | |
7937f9e5 | 1287 | int remain; |
b1379d9a | 1288 | u8 *tx_data; |
1289 | ||
1290 | tx_data = agg->head; | |
1291 | agg->skb_num = agg->skb_len = 0; | |
7937f9e5 | 1292 | remain = rx_buf_sz; |
b1379d9a | 1293 | |
7937f9e5 | 1294 | while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) { |
b1379d9a | 1295 | struct tx_desc *tx_desc; |
1296 | struct sk_buff *skb; | |
1297 | unsigned int len; | |
1298 | ||
1299 | skb = skb_dequeue(&tp->tx_queue); | |
1300 | if (!skb) | |
1301 | break; | |
1302 | ||
7937f9e5 | 1303 | remain -= sizeof(*tx_desc); |
b1379d9a | 1304 | len = skb->len; |
1305 | if (remain < len) { | |
1306 | skb_queue_head(&tp->tx_queue, skb); | |
1307 | break; | |
1308 | } | |
1309 | ||
7937f9e5 | 1310 | tx_data = tx_agg_align(tx_data); |
b1379d9a | 1311 | tx_desc = (struct tx_desc *)tx_data; |
1312 | tx_data += sizeof(*tx_desc); | |
1313 | ||
1314 | r8152_tx_csum(tp, tx_desc, skb); | |
1315 | memcpy(tx_data, skb->data, len); | |
1316 | agg->skb_num++; | |
1317 | agg->skb_len += len; | |
1318 | dev_kfree_skb_any(skb); | |
1319 | ||
7937f9e5 | 1320 | tx_data += len; |
1321 | remain = rx_buf_sz - (int)(tx_agg_align(tx_data) - agg->head); | |
b1379d9a | 1322 | } |
1323 | ||
dd1b119c | 1324 | netif_tx_lock(tp->netdev); |
1325 | ||
1326 | if (netif_queue_stopped(tp->netdev) && | |
1327 | skb_queue_len(&tp->tx_queue) < tp->tx_qlen) | |
1328 | netif_wake_queue(tp->netdev); | |
1329 | ||
1330 | netif_tx_unlock(tp->netdev); | |
1331 | ||
b1379d9a | 1332 | usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2), |
1333 | agg->head, (int)(tx_data - (u8 *)agg->head), | |
1334 | (usb_complete_t)write_bulk_callback, agg); | |
1335 | ||
1336 | return usb_submit_urb(agg->urb, GFP_ATOMIC); | |
1337 | } | |
1338 | ||
ebc2ec48 | 1339 | static void rx_bottom(struct r8152 *tp) |
1340 | { | |
a5a4f468 | 1341 | unsigned long flags; |
ebc2ec48 | 1342 | struct list_head *cursor, *next; |
ebc2ec48 | 1343 | |
a5a4f468 | 1344 | spin_lock_irqsave(&tp->rx_lock, flags); |
ebc2ec48 | 1345 | list_for_each_safe(cursor, next, &tp->rx_done) { |
43a4478d | 1346 | struct rx_desc *rx_desc; |
1347 | struct rx_agg *agg; | |
43a4478d | 1348 | int len_used = 0; |
1349 | struct urb *urb; | |
1350 | u8 *rx_data; | |
1351 | int ret; | |
1352 | ||
ebc2ec48 | 1353 | list_del_init(cursor); |
a5a4f468 | 1354 | spin_unlock_irqrestore(&tp->rx_lock, flags); |
ebc2ec48 | 1355 | |
1356 | agg = list_entry(cursor, struct rx_agg, list); | |
1357 | urb = agg->urb; | |
0de98f6c | 1358 | if (urb->actual_length < ETH_ZLEN) |
1359 | goto submit; | |
ebc2ec48 | 1360 | |
ebc2ec48 | 1361 | rx_desc = agg->head; |
1362 | rx_data = agg->head; | |
7937f9e5 | 1363 | len_used += sizeof(struct rx_desc); |
ebc2ec48 | 1364 | |
7937f9e5 | 1365 | while (urb->actual_length > len_used) { |
43a4478d | 1366 | struct net_device *netdev = tp->netdev; |
1367 | struct net_device_stats *stats; | |
7937f9e5 | 1368 | unsigned int pkt_len; |
43a4478d | 1369 | struct sk_buff *skb; |
1370 | ||
7937f9e5 | 1371 | pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; |
ebc2ec48 | 1372 | if (pkt_len < ETH_ZLEN) |
1373 | break; | |
1374 | ||
7937f9e5 | 1375 | len_used += pkt_len; |
1376 | if (urb->actual_length < len_used) | |
1377 | break; | |
1378 | ||
43a4478d | 1379 | stats = rtl8152_get_stats(netdev); |
1380 | ||
8e1f51bd | 1381 | pkt_len -= CRC_SIZE; |
ebc2ec48 | 1382 | rx_data += sizeof(struct rx_desc); |
1383 | ||
1384 | skb = netdev_alloc_skb_ip_align(netdev, pkt_len); | |
1385 | if (!skb) { | |
1386 | stats->rx_dropped++; | |
1387 | break; | |
1388 | } | |
1389 | memcpy(skb->data, rx_data, pkt_len); | |
1390 | skb_put(skb, pkt_len); | |
1391 | skb->protocol = eth_type_trans(skb, netdev); | |
1392 | netif_rx(skb); | |
1393 | stats->rx_packets++; | |
1394 | stats->rx_bytes += pkt_len; | |
1395 | ||
8e1f51bd | 1396 | rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE); |
ebc2ec48 | 1397 | rx_desc = (struct rx_desc *)rx_data; |
ebc2ec48 | 1398 | len_used = (int)(rx_data - (u8 *)agg->head); |
7937f9e5 | 1399 | len_used += sizeof(struct rx_desc); |
ebc2ec48 | 1400 | } |
1401 | ||
0de98f6c | 1402 | submit: |
ebc2ec48 | 1403 | ret = r8152_submit_rx(tp, agg, GFP_ATOMIC); |
a5a4f468 | 1404 | spin_lock_irqsave(&tp->rx_lock, flags); |
ebc2ec48 | 1405 | if (ret && ret != -ENODEV) { |
1406 | list_add_tail(&agg->list, next); | |
1407 | tasklet_schedule(&tp->tl); | |
1408 | } | |
1409 | } | |
a5a4f468 | 1410 | spin_unlock_irqrestore(&tp->rx_lock, flags); |
ebc2ec48 | 1411 | } |
1412 | ||
1413 | static void tx_bottom(struct r8152 *tp) | |
1414 | { | |
ebc2ec48 | 1415 | int res; |
1416 | ||
b1379d9a | 1417 | do { |
1418 | struct tx_agg *agg; | |
ebc2ec48 | 1419 | |
b1379d9a | 1420 | if (skb_queue_empty(&tp->tx_queue)) |
ebc2ec48 | 1421 | break; |
1422 | ||
b1379d9a | 1423 | agg = r8152_get_tx_agg(tp); |
1424 | if (!agg) | |
ebc2ec48 | 1425 | break; |
ebc2ec48 | 1426 | |
b1379d9a | 1427 | res = r8152_tx_agg_fill(tp, agg); |
1428 | if (res) { | |
1429 | struct net_device_stats *stats; | |
1430 | struct net_device *netdev; | |
1431 | unsigned long flags; | |
ebc2ec48 | 1432 | |
b1379d9a | 1433 | netdev = tp->netdev; |
1434 | stats = rtl8152_get_stats(netdev); | |
ebc2ec48 | 1435 | |
b1379d9a | 1436 | if (res == -ENODEV) { |
1437 | netif_device_detach(netdev); | |
1438 | } else { | |
1439 | netif_warn(tp, tx_err, netdev, | |
1440 | "failed tx_urb %d\n", res); | |
1441 | stats->tx_dropped += agg->skb_num; | |
1442 | spin_lock_irqsave(&tp->tx_lock, flags); | |
1443 | list_add_tail(&agg->list, &tp->tx_free); | |
1444 | spin_unlock_irqrestore(&tp->tx_lock, flags); | |
1445 | } | |
ebc2ec48 | 1446 | } |
b1379d9a | 1447 | } while (res == 0); |
ebc2ec48 | 1448 | } |
1449 | ||
1450 | static void bottom_half(unsigned long data) | |
ac718b69 | 1451 | { |
1452 | struct r8152 *tp; | |
ac718b69 | 1453 | |
ebc2ec48 | 1454 | tp = (struct r8152 *)data; |
1455 | ||
1456 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
1457 | return; | |
1458 | ||
1459 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
ac718b69 | 1460 | return; |
ebc2ec48 | 1461 | |
7559fb2f | 1462 | /* When link down, the driver would cancel all bulks. */ |
1463 | /* This avoid the re-submitting bulk */ | |
ebc2ec48 | 1464 | if (!netif_carrier_ok(tp->netdev)) |
ac718b69 | 1465 | return; |
ebc2ec48 | 1466 | |
1467 | rx_bottom(tp); | |
1468 | tx_bottom(tp); | |
1469 | } | |
1470 | ||
1471 | static | |
1472 | int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags) | |
1473 | { | |
1474 | usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1), | |
1475 | agg->head, rx_buf_sz, | |
1476 | (usb_complete_t)read_bulk_callback, agg); | |
1477 | ||
1478 | return usb_submit_urb(agg->urb, mem_flags); | |
ac718b69 | 1479 | } |
1480 | ||
00a5e360 | 1481 | static void rtl_drop_queued_tx(struct r8152 *tp) |
1482 | { | |
1483 | struct net_device_stats *stats = &tp->netdev->stats; | |
1484 | struct sk_buff *skb; | |
1485 | ||
1486 | while ((skb = skb_dequeue(&tp->tx_queue))) { | |
1487 | dev_kfree_skb(skb); | |
1488 | stats->tx_dropped++; | |
1489 | } | |
1490 | } | |
1491 | ||
ac718b69 | 1492 | static void rtl8152_tx_timeout(struct net_device *netdev) |
1493 | { | |
1494 | struct r8152 *tp = netdev_priv(netdev); | |
ebc2ec48 | 1495 | int i; |
1496 | ||
4a8deae2 | 1497 | netif_warn(tp, tx_err, netdev, "Tx timeout\n"); |
ebc2ec48 | 1498 | for (i = 0; i < RTL8152_MAX_TX; i++) |
1499 | usb_unlink_urb(tp->tx_info[i].urb); | |
ac718b69 | 1500 | } |
1501 | ||
1502 | static void rtl8152_set_rx_mode(struct net_device *netdev) | |
1503 | { | |
1504 | struct r8152 *tp = netdev_priv(netdev); | |
1505 | ||
40a82917 | 1506 | if (tp->speed & LINK_STATUS) { |
ac718b69 | 1507 | set_bit(RTL8152_SET_RX_MODE, &tp->flags); |
40a82917 | 1508 | schedule_delayed_work(&tp->schedule, 0); |
1509 | } | |
ac718b69 | 1510 | } |
1511 | ||
1512 | static void _rtl8152_set_rx_mode(struct net_device *netdev) | |
1513 | { | |
1514 | struct r8152 *tp = netdev_priv(netdev); | |
31787f53 | 1515 | u32 mc_filter[2]; /* Multicast hash filter */ |
1516 | __le32 tmp[2]; | |
ac718b69 | 1517 | u32 ocp_data; |
1518 | ||
ac718b69 | 1519 | clear_bit(RTL8152_SET_RX_MODE, &tp->flags); |
1520 | netif_stop_queue(netdev); | |
1521 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
1522 | ocp_data &= ~RCR_ACPT_ALL; | |
1523 | ocp_data |= RCR_AB | RCR_APM; | |
1524 | ||
1525 | if (netdev->flags & IFF_PROMISC) { | |
1526 | /* Unconditionally log net taps. */ | |
1527 | netif_notice(tp, link, netdev, "Promiscuous mode enabled\n"); | |
1528 | ocp_data |= RCR_AM | RCR_AAP; | |
1529 | mc_filter[1] = mc_filter[0] = 0xffffffff; | |
1530 | } else if ((netdev_mc_count(netdev) > multicast_filter_limit) || | |
1531 | (netdev->flags & IFF_ALLMULTI)) { | |
1532 | /* Too many to filter perfectly -- accept all multicasts. */ | |
1533 | ocp_data |= RCR_AM; | |
1534 | mc_filter[1] = mc_filter[0] = 0xffffffff; | |
1535 | } else { | |
1536 | struct netdev_hw_addr *ha; | |
1537 | ||
1538 | mc_filter[1] = mc_filter[0] = 0; | |
1539 | netdev_for_each_mc_addr(ha, netdev) { | |
1540 | int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; | |
1541 | mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); | |
1542 | ocp_data |= RCR_AM; | |
1543 | } | |
1544 | } | |
1545 | ||
31787f53 | 1546 | tmp[0] = __cpu_to_le32(swab32(mc_filter[1])); |
1547 | tmp[1] = __cpu_to_le32(swab32(mc_filter[0])); | |
ac718b69 | 1548 | |
31787f53 | 1549 | pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp); |
ac718b69 | 1550 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); |
1551 | netif_wake_queue(netdev); | |
ac718b69 | 1552 | } |
1553 | ||
1554 | static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb, | |
1555 | struct net_device *netdev) | |
1556 | { | |
1557 | struct r8152 *tp = netdev_priv(netdev); | |
ac718b69 | 1558 | |
ebc2ec48 | 1559 | skb_tx_timestamp(skb); |
ac718b69 | 1560 | |
61598788 | 1561 | skb_queue_tail(&tp->tx_queue, skb); |
ebc2ec48 | 1562 | |
dd1b119c | 1563 | if (list_empty(&tp->tx_free) && |
1564 | skb_queue_len(&tp->tx_queue) > tp->tx_qlen) | |
1565 | netif_stop_queue(netdev); | |
1566 | ||
61598788 | 1567 | if (!list_empty(&tp->tx_free)) |
1568 | tasklet_schedule(&tp->tl); | |
ac718b69 | 1569 | |
1570 | return NETDEV_TX_OK; | |
1571 | } | |
1572 | ||
1573 | static void r8152b_reset_packet_filter(struct r8152 *tp) | |
1574 | { | |
1575 | u32 ocp_data; | |
1576 | ||
1577 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); | |
1578 | ocp_data &= ~FMC_FCR_MCU_EN; | |
1579 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); | |
1580 | ocp_data |= FMC_FCR_MCU_EN; | |
1581 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); | |
1582 | } | |
1583 | ||
1584 | static void rtl8152_nic_reset(struct r8152 *tp) | |
1585 | { | |
1586 | int i; | |
1587 | ||
1588 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST); | |
1589 | ||
1590 | for (i = 0; i < 1000; i++) { | |
1591 | if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST)) | |
1592 | break; | |
1593 | udelay(100); | |
1594 | } | |
1595 | } | |
1596 | ||
dd1b119c | 1597 | static void set_tx_qlen(struct r8152 *tp) |
1598 | { | |
1599 | struct net_device *netdev = tp->netdev; | |
1600 | ||
1601 | tp->tx_qlen = rx_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN + | |
1602 | sizeof(struct tx_desc)); | |
1603 | } | |
1604 | ||
ac718b69 | 1605 | static inline u8 rtl8152_get_speed(struct r8152 *tp) |
1606 | { | |
1607 | return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); | |
1608 | } | |
1609 | ||
507605a8 | 1610 | static void rtl_set_eee_plus(struct r8152 *tp) |
ac718b69 | 1611 | { |
ebc2ec48 | 1612 | u32 ocp_data; |
ac718b69 | 1613 | u8 speed; |
1614 | ||
1615 | speed = rtl8152_get_speed(tp); | |
ebc2ec48 | 1616 | if (speed & _10bps) { |
ac718b69 | 1617 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); |
ebc2ec48 | 1618 | ocp_data |= EEEP_CR_EEEP_TX; |
ac718b69 | 1619 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); |
1620 | } else { | |
1621 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); | |
ebc2ec48 | 1622 | ocp_data &= ~EEEP_CR_EEEP_TX; |
ac718b69 | 1623 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); |
1624 | } | |
507605a8 | 1625 | } |
1626 | ||
00a5e360 | 1627 | static void rxdy_gated_en(struct r8152 *tp, bool enable) |
1628 | { | |
1629 | u32 ocp_data; | |
1630 | ||
1631 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); | |
1632 | if (enable) | |
1633 | ocp_data |= RXDY_GATED_EN; | |
1634 | else | |
1635 | ocp_data &= ~RXDY_GATED_EN; | |
1636 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); | |
1637 | } | |
1638 | ||
507605a8 | 1639 | static int rtl_enable(struct r8152 *tp) |
1640 | { | |
1641 | u32 ocp_data; | |
1642 | int i, ret; | |
ac718b69 | 1643 | |
1644 | r8152b_reset_packet_filter(tp); | |
1645 | ||
1646 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); | |
1647 | ocp_data |= CR_RE | CR_TE; | |
1648 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); | |
1649 | ||
00a5e360 | 1650 | rxdy_gated_en(tp, false); |
ac718b69 | 1651 | |
ebc2ec48 | 1652 | INIT_LIST_HEAD(&tp->rx_done); |
1653 | ret = 0; | |
1654 | for (i = 0; i < RTL8152_MAX_RX; i++) { | |
1655 | INIT_LIST_HEAD(&tp->rx_info[i].list); | |
1656 | ret |= r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL); | |
1657 | } | |
ac718b69 | 1658 | |
ebc2ec48 | 1659 | return ret; |
ac718b69 | 1660 | } |
1661 | ||
507605a8 | 1662 | static int rtl8152_enable(struct r8152 *tp) |
1663 | { | |
1664 | set_tx_qlen(tp); | |
1665 | rtl_set_eee_plus(tp); | |
1666 | ||
1667 | return rtl_enable(tp); | |
1668 | } | |
1669 | ||
43779f8d | 1670 | static void r8153_set_rx_agg(struct r8152 *tp) |
1671 | { | |
1672 | u8 speed; | |
1673 | ||
1674 | speed = rtl8152_get_speed(tp); | |
1675 | if (speed & _1000bps) { | |
1676 | if (tp->udev->speed == USB_SPEED_SUPER) { | |
1677 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, | |
1678 | RX_THR_SUPPER); | |
1679 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG, | |
1680 | EARLY_AGG_SUPPER); | |
1681 | } else { | |
1682 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, | |
1683 | RX_THR_HIGH); | |
1684 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG, | |
1685 | EARLY_AGG_HIGH); | |
1686 | } | |
1687 | } else { | |
1688 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_SLOW); | |
1689 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG, | |
1690 | EARLY_AGG_SLOW); | |
1691 | } | |
1692 | } | |
1693 | ||
1694 | static int rtl8153_enable(struct r8152 *tp) | |
1695 | { | |
1696 | set_tx_qlen(tp); | |
1697 | rtl_set_eee_plus(tp); | |
1698 | r8153_set_rx_agg(tp); | |
1699 | ||
1700 | return rtl_enable(tp); | |
1701 | } | |
1702 | ||
ac718b69 | 1703 | static void rtl8152_disable(struct r8152 *tp) |
1704 | { | |
ebc2ec48 | 1705 | u32 ocp_data; |
1706 | int i; | |
ac718b69 | 1707 | |
1708 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
1709 | ocp_data &= ~RCR_ACPT_ALL; | |
1710 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
1711 | ||
00a5e360 | 1712 | rtl_drop_queued_tx(tp); |
ebc2ec48 | 1713 | |
1714 | for (i = 0; i < RTL8152_MAX_TX; i++) | |
1715 | usb_kill_urb(tp->tx_info[i].urb); | |
ac718b69 | 1716 | |
00a5e360 | 1717 | rxdy_gated_en(tp, true); |
ac718b69 | 1718 | |
1719 | for (i = 0; i < 1000; i++) { | |
1720 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
1721 | if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY) | |
1722 | break; | |
1723 | mdelay(1); | |
1724 | } | |
1725 | ||
1726 | for (i = 0; i < 1000; i++) { | |
1727 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY) | |
1728 | break; | |
1729 | mdelay(1); | |
1730 | } | |
1731 | ||
ebc2ec48 | 1732 | for (i = 0; i < RTL8152_MAX_RX; i++) |
1733 | usb_kill_urb(tp->rx_info[i].urb); | |
ac718b69 | 1734 | |
1735 | rtl8152_nic_reset(tp); | |
1736 | } | |
1737 | ||
00a5e360 | 1738 | static void r8152_power_cut_en(struct r8152 *tp, bool enable) |
1739 | { | |
1740 | u32 ocp_data; | |
1741 | ||
1742 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); | |
1743 | if (enable) | |
1744 | ocp_data |= POWER_CUT; | |
1745 | else | |
1746 | ocp_data &= ~POWER_CUT; | |
1747 | ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); | |
1748 | ||
1749 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); | |
1750 | ocp_data &= ~RESUME_INDICATE; | |
1751 | ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); | |
1752 | ||
1753 | } | |
1754 | ||
4349968a | 1755 | static void rtl_clear_bp(struct r8152 *tp) |
1756 | { | |
1757 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_0, 0); | |
1758 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_2, 0); | |
1759 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_4, 0); | |
1760 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_6, 0); | |
1761 | ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_0, 0); | |
1762 | ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_2, 0); | |
1763 | ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_4, 0); | |
1764 | ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_6, 0); | |
1765 | mdelay(3); | |
1766 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_BA, 0); | |
1767 | ocp_write_word(tp, MCU_TYPE_USB, USB_BP_BA, 0); | |
1768 | } | |
1769 | ||
1770 | static void r8153_clear_bp(struct r8152 *tp) | |
1771 | { | |
1772 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_BP_EN, 0); | |
1773 | ocp_write_byte(tp, MCU_TYPE_USB, USB_BP_EN, 0); | |
1774 | rtl_clear_bp(tp); | |
1775 | } | |
1776 | ||
1777 | static void r8153_teredo_off(struct r8152 *tp) | |
1778 | { | |
1779 | u32 ocp_data; | |
1780 | ||
1781 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); | |
1782 | ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN); | |
1783 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); | |
1784 | ||
1785 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE); | |
1786 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0); | |
1787 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0); | |
1788 | } | |
1789 | ||
1790 | static void r8152b_disable_aldps(struct r8152 *tp) | |
1791 | { | |
1792 | ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE); | |
1793 | msleep(20); | |
1794 | } | |
1795 | ||
1796 | static inline void r8152b_enable_aldps(struct r8152 *tp) | |
1797 | { | |
1798 | ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS | | |
1799 | LINKENA | DIS_SDSAVE); | |
1800 | } | |
1801 | ||
1802 | static void r8152b_hw_phy_cfg(struct r8152 *tp) | |
1803 | { | |
1804 | r8152_mdio_write(tp, MII_BMCR, BMCR_ANENABLE); | |
1805 | r8152b_disable_aldps(tp); | |
1806 | } | |
1807 | ||
ac718b69 | 1808 | static void r8152b_exit_oob(struct r8152 *tp) |
1809 | { | |
1810 | u32 ocp_data; | |
1811 | int i; | |
1812 | ||
1813 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
1814 | ocp_data &= ~RCR_ACPT_ALL; | |
1815 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
1816 | ||
00a5e360 | 1817 | rxdy_gated_en(tp, true); |
ac718b69 | 1818 | |
1819 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
1820 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); | |
1821 | ||
1822 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
1823 | ocp_data &= ~NOW_IS_OOB; | |
1824 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
1825 | ||
1826 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
1827 | ocp_data &= ~MCU_BORW_EN; | |
1828 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
1829 | ||
1830 | for (i = 0; i < 1000; i++) { | |
1831 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
1832 | if (ocp_data & LINK_LIST_READY) | |
1833 | break; | |
1834 | mdelay(1); | |
1835 | } | |
1836 | ||
1837 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
1838 | ocp_data |= RE_INIT_LL; | |
1839 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
1840 | ||
1841 | for (i = 0; i < 1000; i++) { | |
1842 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
1843 | if (ocp_data & LINK_LIST_READY) | |
1844 | break; | |
1845 | mdelay(1); | |
1846 | } | |
1847 | ||
1848 | rtl8152_nic_reset(tp); | |
1849 | ||
1850 | /* rx share fifo credit full threshold */ | |
1851 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); | |
1852 | ||
1853 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_DEV_STAT); | |
1854 | ocp_data &= STAT_SPEED_MASK; | |
1855 | if (ocp_data == STAT_SPEED_FULL) { | |
1856 | /* rx share fifo credit near full threshold */ | |
1857 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, | |
1858 | RXFIFO_THR2_FULL); | |
1859 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, | |
1860 | RXFIFO_THR3_FULL); | |
1861 | } else { | |
1862 | /* rx share fifo credit near full threshold */ | |
1863 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, | |
1864 | RXFIFO_THR2_HIGH); | |
1865 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, | |
1866 | RXFIFO_THR3_HIGH); | |
1867 | } | |
1868 | ||
1869 | /* TX share fifo free credit full threshold */ | |
1870 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL); | |
1871 | ||
1872 | ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD); | |
8e1f51bd | 1873 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH); |
ac718b69 | 1874 | ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA, |
1875 | TEST_MODE_DISABLE | TX_SIZE_ADJUST1); | |
1876 | ||
1877 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); | |
1878 | ocp_data &= ~CPCR_RX_VLAN; | |
1879 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); | |
1880 | ||
1881 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); | |
1882 | ||
1883 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); | |
1884 | ocp_data |= TCR0_AUTO_FIFO; | |
1885 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); | |
1886 | } | |
1887 | ||
1888 | static void r8152b_enter_oob(struct r8152 *tp) | |
1889 | { | |
45f4a19f | 1890 | u32 ocp_data; |
1891 | int i; | |
ac718b69 | 1892 | |
1893 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
1894 | ocp_data &= ~NOW_IS_OOB; | |
1895 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
1896 | ||
1897 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); | |
1898 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); | |
1899 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB); | |
1900 | ||
1901 | rtl8152_disable(tp); | |
1902 | ||
1903 | for (i = 0; i < 1000; i++) { | |
1904 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
1905 | if (ocp_data & LINK_LIST_READY) | |
1906 | break; | |
1907 | mdelay(1); | |
1908 | } | |
1909 | ||
1910 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
1911 | ocp_data |= RE_INIT_LL; | |
1912 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
1913 | ||
1914 | for (i = 0; i < 1000; i++) { | |
1915 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
1916 | if (ocp_data & LINK_LIST_READY) | |
1917 | break; | |
1918 | mdelay(1); | |
1919 | } | |
1920 | ||
1921 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); | |
1922 | ||
1923 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); | |
1924 | ocp_data |= MAGIC_EN; | |
1925 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data); | |
1926 | ||
1927 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); | |
1928 | ocp_data |= CPCR_RX_VLAN; | |
1929 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); | |
1930 | ||
1931 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); | |
1932 | ocp_data |= ALDPS_PROXY_MODE; | |
1933 | ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); | |
1934 | ||
1935 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
1936 | ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; | |
1937 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
1938 | ||
1939 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5, LAN_WAKE_EN); | |
1940 | ||
00a5e360 | 1941 | rxdy_gated_en(tp, false); |
ac718b69 | 1942 | |
1943 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
1944 | ocp_data |= RCR_APM | RCR_AM | RCR_AB; | |
1945 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
1946 | } | |
1947 | ||
43779f8d | 1948 | static void r8153_hw_phy_cfg(struct r8152 *tp) |
1949 | { | |
1950 | u32 ocp_data; | |
1951 | u16 data; | |
1952 | ||
1953 | ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L); | |
1954 | r8152_mdio_write(tp, MII_BMCR, BMCR_ANENABLE); | |
1955 | ||
1956 | if (tp->version == RTL_VER_03) { | |
1957 | data = ocp_reg_read(tp, OCP_EEE_CFG); | |
1958 | data &= ~CTAP_SHORT_EN; | |
1959 | ocp_reg_write(tp, OCP_EEE_CFG, data); | |
1960 | } | |
1961 | ||
1962 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
1963 | data |= EEE_CLKDIV_EN; | |
1964 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
1965 | ||
1966 | data = ocp_reg_read(tp, OCP_DOWN_SPEED); | |
1967 | data |= EN_10M_BGOFF; | |
1968 | ocp_reg_write(tp, OCP_DOWN_SPEED, data); | |
1969 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
1970 | data |= EN_10M_PLLOFF; | |
1971 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
1972 | data = sram_read(tp, SRAM_IMPEDANCE); | |
1973 | data &= ~RX_DRIVING_MASK; | |
1974 | sram_write(tp, SRAM_IMPEDANCE, data); | |
1975 | ||
1976 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); | |
1977 | ocp_data |= PFM_PWM_SWITCH; | |
1978 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); | |
1979 | ||
1980 | data = sram_read(tp, SRAM_LPF_CFG); | |
1981 | data |= LPF_AUTO_TUNE; | |
1982 | sram_write(tp, SRAM_LPF_CFG, data); | |
1983 | ||
1984 | data = sram_read(tp, SRAM_10M_AMP1); | |
1985 | data |= GDAC_IB_UPALL; | |
1986 | sram_write(tp, SRAM_10M_AMP1, data); | |
1987 | data = sram_read(tp, SRAM_10M_AMP2); | |
1988 | data |= AMP_DN; | |
1989 | sram_write(tp, SRAM_10M_AMP2, data); | |
1990 | } | |
1991 | ||
1992 | static void r8153_u1u2en(struct r8152 *tp, int enable) | |
1993 | { | |
1994 | u8 u1u2[8]; | |
1995 | ||
1996 | if (enable) | |
1997 | memset(u1u2, 0xff, sizeof(u1u2)); | |
1998 | else | |
1999 | memset(u1u2, 0x00, sizeof(u1u2)); | |
2000 | ||
2001 | usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2); | |
2002 | } | |
2003 | ||
2004 | static void r8153_u2p3en(struct r8152 *tp, int enable) | |
2005 | { | |
2006 | u32 ocp_data; | |
2007 | ||
2008 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); | |
2009 | if (enable) | |
2010 | ocp_data |= U2P3_ENABLE; | |
2011 | else | |
2012 | ocp_data &= ~U2P3_ENABLE; | |
2013 | ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); | |
2014 | } | |
2015 | ||
2016 | static void r8153_power_cut_en(struct r8152 *tp, int enable) | |
2017 | { | |
2018 | u32 ocp_data; | |
2019 | ||
2020 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); | |
2021 | if (enable) | |
2022 | ocp_data |= PWR_EN | PHASE2_EN; | |
2023 | else | |
2024 | ocp_data &= ~(PWR_EN | PHASE2_EN); | |
2025 | ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); | |
2026 | ||
2027 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); | |
2028 | ocp_data &= ~PCUT_STATUS; | |
2029 | ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); | |
2030 | } | |
2031 | ||
43779f8d | 2032 | static void r8153_first_init(struct r8152 *tp) |
2033 | { | |
2034 | u32 ocp_data; | |
2035 | int i; | |
2036 | ||
00a5e360 | 2037 | rxdy_gated_en(tp, true); |
43779f8d | 2038 | r8153_teredo_off(tp); |
2039 | ||
2040 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2041 | ocp_data &= ~RCR_ACPT_ALL; | |
2042 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2043 | ||
2044 | r8153_hw_phy_cfg(tp); | |
2045 | ||
2046 | rtl8152_nic_reset(tp); | |
2047 | ||
2048 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2049 | ocp_data &= ~NOW_IS_OOB; | |
2050 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2051 | ||
2052 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2053 | ocp_data &= ~MCU_BORW_EN; | |
2054 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2055 | ||
2056 | for (i = 0; i < 1000; i++) { | |
2057 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2058 | if (ocp_data & LINK_LIST_READY) | |
2059 | break; | |
2060 | mdelay(1); | |
2061 | } | |
2062 | ||
2063 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2064 | ocp_data |= RE_INIT_LL; | |
2065 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2066 | ||
2067 | for (i = 0; i < 1000; i++) { | |
2068 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2069 | if (ocp_data & LINK_LIST_READY) | |
2070 | break; | |
2071 | mdelay(1); | |
2072 | } | |
2073 | ||
2074 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); | |
2075 | ocp_data &= ~CPCR_RX_VLAN; | |
2076 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); | |
2077 | ||
2078 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); | |
2079 | ||
2080 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); | |
2081 | ocp_data |= TCR0_AUTO_FIFO; | |
2082 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); | |
2083 | ||
2084 | rtl8152_nic_reset(tp); | |
2085 | ||
2086 | /* rx share fifo credit full threshold */ | |
2087 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); | |
2088 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL); | |
2089 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL); | |
2090 | /* TX share fifo free credit full threshold */ | |
2091 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2); | |
2092 | ||
9629e3c0 | 2093 | /* rx aggregation */ |
43779f8d | 2094 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); |
2095 | ocp_data &= ~RX_AGG_DISABLE; | |
2096 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); | |
2097 | } | |
2098 | ||
2099 | static void r8153_enter_oob(struct r8152 *tp) | |
2100 | { | |
2101 | u32 ocp_data; | |
2102 | int i; | |
2103 | ||
2104 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2105 | ocp_data &= ~NOW_IS_OOB; | |
2106 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2107 | ||
2108 | rtl8152_disable(tp); | |
2109 | ||
2110 | for (i = 0; i < 1000; i++) { | |
2111 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2112 | if (ocp_data & LINK_LIST_READY) | |
2113 | break; | |
2114 | mdelay(1); | |
2115 | } | |
2116 | ||
2117 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2118 | ocp_data |= RE_INIT_LL; | |
2119 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2120 | ||
2121 | for (i = 0; i < 1000; i++) { | |
2122 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2123 | if (ocp_data & LINK_LIST_READY) | |
2124 | break; | |
2125 | mdelay(1); | |
2126 | } | |
2127 | ||
2128 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); | |
2129 | ||
2130 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); | |
2131 | ocp_data |= MAGIC_EN; | |
2132 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data); | |
2133 | ||
2134 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); | |
2135 | ocp_data &= ~TEREDO_WAKE_MASK; | |
2136 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); | |
2137 | ||
2138 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); | |
2139 | ocp_data |= CPCR_RX_VLAN; | |
2140 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); | |
2141 | ||
2142 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); | |
2143 | ocp_data |= ALDPS_PROXY_MODE; | |
2144 | ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); | |
2145 | ||
2146 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2147 | ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; | |
2148 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2149 | ||
2150 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5, LAN_WAKE_EN); | |
2151 | ||
00a5e360 | 2152 | rxdy_gated_en(tp, false); |
43779f8d | 2153 | |
2154 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2155 | ocp_data |= RCR_APM | RCR_AM | RCR_AB; | |
2156 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2157 | } | |
2158 | ||
2159 | static void r8153_disable_aldps(struct r8152 *tp) | |
2160 | { | |
2161 | u16 data; | |
2162 | ||
2163 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
2164 | data &= ~EN_ALDPS; | |
2165 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
2166 | msleep(20); | |
2167 | } | |
2168 | ||
2169 | static void r8153_enable_aldps(struct r8152 *tp) | |
2170 | { | |
2171 | u16 data; | |
2172 | ||
2173 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
2174 | data |= EN_ALDPS; | |
2175 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
2176 | } | |
2177 | ||
ac718b69 | 2178 | static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex) |
2179 | { | |
43779f8d | 2180 | u16 bmcr, anar, gbcr; |
ac718b69 | 2181 | int ret = 0; |
2182 | ||
2183 | cancel_delayed_work_sync(&tp->schedule); | |
2184 | anar = r8152_mdio_read(tp, MII_ADVERTISE); | |
2185 | anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | | |
2186 | ADVERTISE_100HALF | ADVERTISE_100FULL); | |
43779f8d | 2187 | if (tp->mii.supports_gmii) { |
2188 | gbcr = r8152_mdio_read(tp, MII_CTRL1000); | |
2189 | gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); | |
2190 | } else { | |
2191 | gbcr = 0; | |
2192 | } | |
ac718b69 | 2193 | |
2194 | if (autoneg == AUTONEG_DISABLE) { | |
2195 | if (speed == SPEED_10) { | |
2196 | bmcr = 0; | |
2197 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
2198 | } else if (speed == SPEED_100) { | |
2199 | bmcr = BMCR_SPEED100; | |
2200 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; | |
43779f8d | 2201 | } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { |
2202 | bmcr = BMCR_SPEED1000; | |
2203 | gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; | |
ac718b69 | 2204 | } else { |
2205 | ret = -EINVAL; | |
2206 | goto out; | |
2207 | } | |
2208 | ||
2209 | if (duplex == DUPLEX_FULL) | |
2210 | bmcr |= BMCR_FULLDPLX; | |
2211 | } else { | |
2212 | if (speed == SPEED_10) { | |
2213 | if (duplex == DUPLEX_FULL) | |
2214 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
2215 | else | |
2216 | anar |= ADVERTISE_10HALF; | |
2217 | } else if (speed == SPEED_100) { | |
2218 | if (duplex == DUPLEX_FULL) { | |
2219 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
2220 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; | |
2221 | } else { | |
2222 | anar |= ADVERTISE_10HALF; | |
2223 | anar |= ADVERTISE_100HALF; | |
2224 | } | |
43779f8d | 2225 | } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { |
2226 | if (duplex == DUPLEX_FULL) { | |
2227 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
2228 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; | |
2229 | gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; | |
2230 | } else { | |
2231 | anar |= ADVERTISE_10HALF; | |
2232 | anar |= ADVERTISE_100HALF; | |
2233 | gbcr |= ADVERTISE_1000HALF; | |
2234 | } | |
ac718b69 | 2235 | } else { |
2236 | ret = -EINVAL; | |
2237 | goto out; | |
2238 | } | |
2239 | ||
2240 | bmcr = BMCR_ANENABLE | BMCR_ANRESTART; | |
2241 | } | |
2242 | ||
43779f8d | 2243 | if (tp->mii.supports_gmii) |
2244 | r8152_mdio_write(tp, MII_CTRL1000, gbcr); | |
2245 | ||
ac718b69 | 2246 | r8152_mdio_write(tp, MII_ADVERTISE, anar); |
2247 | r8152_mdio_write(tp, MII_BMCR, bmcr); | |
2248 | ||
2249 | out: | |
ac718b69 | 2250 | |
2251 | return ret; | |
2252 | } | |
2253 | ||
2254 | static void rtl8152_down(struct r8152 *tp) | |
2255 | { | |
00a5e360 | 2256 | r8152_power_cut_en(tp, false); |
ac718b69 | 2257 | r8152b_disable_aldps(tp); |
2258 | r8152b_enter_oob(tp); | |
2259 | r8152b_enable_aldps(tp); | |
2260 | } | |
2261 | ||
43779f8d | 2262 | static void rtl8153_down(struct r8152 *tp) |
2263 | { | |
2264 | r8153_u1u2en(tp, 0); | |
2265 | r8153_power_cut_en(tp, 0); | |
2266 | r8153_disable_aldps(tp); | |
2267 | r8153_enter_oob(tp); | |
2268 | r8153_enable_aldps(tp); | |
2269 | } | |
2270 | ||
ac718b69 | 2271 | static void set_carrier(struct r8152 *tp) |
2272 | { | |
2273 | struct net_device *netdev = tp->netdev; | |
2274 | u8 speed; | |
2275 | ||
40a82917 | 2276 | clear_bit(RTL8152_LINK_CHG, &tp->flags); |
ac718b69 | 2277 | speed = rtl8152_get_speed(tp); |
2278 | ||
2279 | if (speed & LINK_STATUS) { | |
2280 | if (!(tp->speed & LINK_STATUS)) { | |
c81229c9 | 2281 | tp->rtl_ops.enable(tp); |
ac718b69 | 2282 | set_bit(RTL8152_SET_RX_MODE, &tp->flags); |
2283 | netif_carrier_on(netdev); | |
2284 | } | |
2285 | } else { | |
2286 | if (tp->speed & LINK_STATUS) { | |
2287 | netif_carrier_off(netdev); | |
ebc2ec48 | 2288 | tasklet_disable(&tp->tl); |
c81229c9 | 2289 | tp->rtl_ops.disable(tp); |
ebc2ec48 | 2290 | tasklet_enable(&tp->tl); |
ac718b69 | 2291 | } |
2292 | } | |
2293 | tp->speed = speed; | |
2294 | } | |
2295 | ||
2296 | static void rtl_work_func_t(struct work_struct *work) | |
2297 | { | |
2298 | struct r8152 *tp = container_of(work, struct r8152, schedule.work); | |
2299 | ||
2300 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
2301 | goto out1; | |
2302 | ||
2303 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
2304 | goto out1; | |
2305 | ||
40a82917 | 2306 | if (test_bit(RTL8152_LINK_CHG, &tp->flags)) |
2307 | set_carrier(tp); | |
ac718b69 | 2308 | |
2309 | if (test_bit(RTL8152_SET_RX_MODE, &tp->flags)) | |
2310 | _rtl8152_set_rx_mode(tp->netdev); | |
2311 | ||
ac718b69 | 2312 | out1: |
2313 | return; | |
2314 | } | |
2315 | ||
2316 | static int rtl8152_open(struct net_device *netdev) | |
2317 | { | |
2318 | struct r8152 *tp = netdev_priv(netdev); | |
2319 | int res = 0; | |
2320 | ||
3d55f44f | 2321 | rtl8152_set_speed(tp, AUTONEG_ENABLE, |
2322 | tp->mii.supports_gmii ? SPEED_1000 : SPEED_100, | |
2323 | DUPLEX_FULL); | |
2324 | tp->speed = 0; | |
2325 | netif_carrier_off(netdev); | |
2326 | netif_start_queue(netdev); | |
2327 | set_bit(WORK_ENABLE, &tp->flags); | |
40a82917 | 2328 | res = usb_submit_urb(tp->intr_urb, GFP_KERNEL); |
2329 | if (res) { | |
2330 | if (res == -ENODEV) | |
2331 | netif_device_detach(tp->netdev); | |
4a8deae2 HW |
2332 | netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n", |
2333 | res); | |
ac718b69 | 2334 | } |
2335 | ||
ac718b69 | 2336 | |
2337 | return res; | |
2338 | } | |
2339 | ||
2340 | static int rtl8152_close(struct net_device *netdev) | |
2341 | { | |
2342 | struct r8152 *tp = netdev_priv(netdev); | |
2343 | int res = 0; | |
2344 | ||
2345 | clear_bit(WORK_ENABLE, &tp->flags); | |
3d55f44f | 2346 | usb_kill_urb(tp->intr_urb); |
ac718b69 | 2347 | cancel_delayed_work_sync(&tp->schedule); |
2348 | netif_stop_queue(netdev); | |
ebc2ec48 | 2349 | tasklet_disable(&tp->tl); |
c81229c9 | 2350 | tp->rtl_ops.disable(tp); |
ebc2ec48 | 2351 | tasklet_enable(&tp->tl); |
ac718b69 | 2352 | |
2353 | return res; | |
2354 | } | |
2355 | ||
ac718b69 | 2356 | static void r8152b_enable_eee(struct r8152 *tp) |
2357 | { | |
45f4a19f | 2358 | u32 ocp_data; |
ac718b69 | 2359 | |
2360 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); | |
2361 | ocp_data |= EEE_RX_EN | EEE_TX_EN; | |
2362 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); | |
2363 | ocp_reg_write(tp, OCP_EEE_CONFIG1, RG_TXLPI_MSK_HFDUP | RG_MATCLR_EN | | |
2364 | EEE_10_CAP | EEE_NWAY_EN | | |
2365 | TX_QUIET_EN | RX_QUIET_EN | | |
2366 | SDRISETIME | RG_RXLPI_MSK_HFDUP | | |
2367 | SDFALLTIME); | |
2368 | ocp_reg_write(tp, OCP_EEE_CONFIG2, RG_LPIHYS_NUM | RG_DACQUIET_EN | | |
2369 | RG_LDVQUIET_EN | RG_CKRSEL | | |
2370 | RG_EEEPRG_EN); | |
2371 | ocp_reg_write(tp, OCP_EEE_CONFIG3, FST_SNR_EYE_R | RG_LFS_SEL | MSK_PH); | |
2372 | ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | DEVICE_ADDR); | |
2373 | ocp_reg_write(tp, OCP_EEE_DATA, EEE_ADDR); | |
2374 | ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | DEVICE_ADDR); | |
2375 | ocp_reg_write(tp, OCP_EEE_DATA, EEE_DATA); | |
2376 | ocp_reg_write(tp, OCP_EEE_AR, 0x0000); | |
2377 | } | |
2378 | ||
43779f8d | 2379 | static void r8153_enable_eee(struct r8152 *tp) |
2380 | { | |
2381 | u32 ocp_data; | |
2382 | u16 data; | |
2383 | ||
2384 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); | |
2385 | ocp_data |= EEE_RX_EN | EEE_TX_EN; | |
2386 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); | |
2387 | data = ocp_reg_read(tp, OCP_EEE_CFG); | |
2388 | data |= EEE10_EN; | |
2389 | ocp_reg_write(tp, OCP_EEE_CFG, data); | |
2390 | data = ocp_reg_read(tp, OCP_EEE_CFG2); | |
2391 | data |= MY1000_EEE | MY100_EEE; | |
2392 | ocp_reg_write(tp, OCP_EEE_CFG2, data); | |
2393 | } | |
2394 | ||
ac718b69 | 2395 | static void r8152b_enable_fc(struct r8152 *tp) |
2396 | { | |
2397 | u16 anar; | |
2398 | ||
2399 | anar = r8152_mdio_read(tp, MII_ADVERTISE); | |
2400 | anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; | |
2401 | r8152_mdio_write(tp, MII_ADVERTISE, anar); | |
2402 | } | |
2403 | ||
ac718b69 | 2404 | static void r8152b_init(struct r8152 *tp) |
2405 | { | |
ebc2ec48 | 2406 | u32 ocp_data; |
2407 | int i; | |
ac718b69 | 2408 | |
2409 | rtl_clear_bp(tp); | |
2410 | ||
2411 | if (tp->version == RTL_VER_01) { | |
2412 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); | |
2413 | ocp_data &= ~LED_MODE_MASK; | |
2414 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); | |
2415 | } | |
2416 | ||
2417 | r8152b_hw_phy_cfg(tp); | |
2418 | ||
00a5e360 | 2419 | r8152_power_cut_en(tp, false); |
ac718b69 | 2420 | |
ac718b69 | 2421 | |
2422 | r8152b_exit_oob(tp); | |
2423 | ||
2424 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); | |
2425 | ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH; | |
2426 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); | |
2427 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL); | |
2428 | ocp_data &= ~MCU_CLK_RATIO_MASK; | |
2429 | ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN; | |
2430 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data); | |
2431 | ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK | | |
2432 | SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK; | |
2433 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data); | |
2434 | ||
2435 | r8152b_enable_eee(tp); | |
2436 | r8152b_enable_aldps(tp); | |
2437 | r8152b_enable_fc(tp); | |
2438 | ||
2439 | r8152_mdio_write(tp, MII_BMCR, BMCR_RESET | BMCR_ANENABLE | | |
2440 | BMCR_ANRESTART); | |
2441 | for (i = 0; i < 100; i++) { | |
2442 | udelay(100); | |
2443 | if (!(r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET)) | |
2444 | break; | |
2445 | } | |
2446 | ||
ebc2ec48 | 2447 | /* enable rx aggregation */ |
ac718b69 | 2448 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); |
ebc2ec48 | 2449 | ocp_data &= ~RX_AGG_DISABLE; |
ac718b69 | 2450 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); |
2451 | } | |
2452 | ||
43779f8d | 2453 | static void r8153_init(struct r8152 *tp) |
2454 | { | |
2455 | u32 ocp_data; | |
2456 | int i; | |
2457 | ||
2458 | r8153_u1u2en(tp, 0); | |
2459 | ||
2460 | for (i = 0; i < 500; i++) { | |
2461 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & | |
2462 | AUTOLOAD_DONE) | |
2463 | break; | |
2464 | msleep(20); | |
2465 | } | |
2466 | ||
2467 | for (i = 0; i < 500; i++) { | |
2468 | ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK; | |
2469 | if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN) | |
2470 | break; | |
2471 | msleep(20); | |
2472 | } | |
2473 | ||
2474 | r8153_u2p3en(tp, 0); | |
2475 | ||
2476 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL); | |
2477 | ocp_data &= ~TIMER11_EN; | |
2478 | ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data); | |
2479 | ||
2480 | r8153_clear_bp(tp); | |
2481 | ||
2482 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); | |
2483 | ocp_data &= ~LED_MODE_MASK; | |
2484 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); | |
2485 | ||
2486 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL); | |
2487 | ocp_data &= ~LPM_TIMER_MASK; | |
2488 | if (tp->udev->speed == USB_SPEED_SUPER) | |
2489 | ocp_data |= LPM_TIMER_500US; | |
2490 | else | |
2491 | ocp_data |= LPM_TIMER_500MS; | |
2492 | ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data); | |
2493 | ||
2494 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2); | |
2495 | ocp_data &= ~SEN_VAL_MASK; | |
2496 | ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE; | |
2497 | ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data); | |
2498 | ||
2499 | r8153_power_cut_en(tp, 0); | |
2500 | r8153_u1u2en(tp, 1); | |
2501 | ||
2502 | r8153_first_init(tp); | |
2503 | ||
2504 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO); | |
2505 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO); | |
2506 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, | |
2507 | PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN | | |
2508 | U1U2_SPDWN_EN | L1_SPDWN_EN); | |
2509 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, | |
2510 | PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN | | |
2511 | TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN | | |
2512 | EEE_SPDWN_EN); | |
2513 | ||
2514 | r8153_enable_eee(tp); | |
2515 | r8153_enable_aldps(tp); | |
2516 | r8152b_enable_fc(tp); | |
2517 | ||
2518 | r8152_mdio_write(tp, MII_BMCR, BMCR_RESET | BMCR_ANENABLE | | |
2519 | BMCR_ANRESTART); | |
2520 | } | |
2521 | ||
ac718b69 | 2522 | static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message) |
2523 | { | |
2524 | struct r8152 *tp = usb_get_intfdata(intf); | |
2525 | ||
2526 | netif_device_detach(tp->netdev); | |
2527 | ||
2528 | if (netif_running(tp->netdev)) { | |
2529 | clear_bit(WORK_ENABLE, &tp->flags); | |
40a82917 | 2530 | usb_kill_urb(tp->intr_urb); |
ac718b69 | 2531 | cancel_delayed_work_sync(&tp->schedule); |
ebc2ec48 | 2532 | tasklet_disable(&tp->tl); |
ac718b69 | 2533 | } |
2534 | ||
c81229c9 | 2535 | tp->rtl_ops.down(tp); |
ac718b69 | 2536 | |
2537 | return 0; | |
2538 | } | |
2539 | ||
2540 | static int rtl8152_resume(struct usb_interface *intf) | |
2541 | { | |
2542 | struct r8152 *tp = usb_get_intfdata(intf); | |
2543 | ||
c81229c9 | 2544 | tp->rtl_ops.init(tp); |
ac718b69 | 2545 | netif_device_attach(tp->netdev); |
2546 | if (netif_running(tp->netdev)) { | |
43779f8d | 2547 | rtl8152_set_speed(tp, AUTONEG_ENABLE, |
2548 | tp->mii.supports_gmii ? SPEED_1000 : SPEED_100, | |
2549 | DUPLEX_FULL); | |
40a82917 | 2550 | tp->speed = 0; |
2551 | netif_carrier_off(tp->netdev); | |
ac718b69 | 2552 | set_bit(WORK_ENABLE, &tp->flags); |
40a82917 | 2553 | usb_submit_urb(tp->intr_urb, GFP_KERNEL); |
ebc2ec48 | 2554 | tasklet_enable(&tp->tl); |
ac718b69 | 2555 | } |
2556 | ||
2557 | return 0; | |
2558 | } | |
2559 | ||
2560 | static void rtl8152_get_drvinfo(struct net_device *netdev, | |
2561 | struct ethtool_drvinfo *info) | |
2562 | { | |
2563 | struct r8152 *tp = netdev_priv(netdev); | |
2564 | ||
2565 | strncpy(info->driver, MODULENAME, ETHTOOL_BUSINFO_LEN); | |
2566 | strncpy(info->version, DRIVER_VERSION, ETHTOOL_BUSINFO_LEN); | |
2567 | usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info)); | |
2568 | } | |
2569 | ||
2570 | static | |
2571 | int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd) | |
2572 | { | |
2573 | struct r8152 *tp = netdev_priv(netdev); | |
2574 | ||
2575 | if (!tp->mii.mdio_read) | |
2576 | return -EOPNOTSUPP; | |
2577 | ||
2578 | return mii_ethtool_gset(&tp->mii, cmd); | |
2579 | } | |
2580 | ||
2581 | static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
2582 | { | |
2583 | struct r8152 *tp = netdev_priv(dev); | |
2584 | ||
2585 | return rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex); | |
2586 | } | |
2587 | ||
2588 | static struct ethtool_ops ops = { | |
2589 | .get_drvinfo = rtl8152_get_drvinfo, | |
2590 | .get_settings = rtl8152_get_settings, | |
2591 | .set_settings = rtl8152_set_settings, | |
2592 | .get_link = ethtool_op_get_link, | |
2593 | }; | |
2594 | ||
2595 | static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) | |
2596 | { | |
2597 | struct r8152 *tp = netdev_priv(netdev); | |
2598 | struct mii_ioctl_data *data = if_mii(rq); | |
2599 | int res = 0; | |
2600 | ||
2601 | switch (cmd) { | |
2602 | case SIOCGMIIPHY: | |
2603 | data->phy_id = R8152_PHY_ID; /* Internal PHY */ | |
2604 | break; | |
2605 | ||
2606 | case SIOCGMIIREG: | |
2607 | data->val_out = r8152_mdio_read(tp, data->reg_num); | |
2608 | break; | |
2609 | ||
2610 | case SIOCSMIIREG: | |
2611 | if (!capable(CAP_NET_ADMIN)) { | |
2612 | res = -EPERM; | |
2613 | break; | |
2614 | } | |
2615 | r8152_mdio_write(tp, data->reg_num, data->val_in); | |
2616 | break; | |
2617 | ||
2618 | default: | |
2619 | res = -EOPNOTSUPP; | |
2620 | } | |
2621 | ||
2622 | return res; | |
2623 | } | |
2624 | ||
2625 | static const struct net_device_ops rtl8152_netdev_ops = { | |
2626 | .ndo_open = rtl8152_open, | |
2627 | .ndo_stop = rtl8152_close, | |
2628 | .ndo_do_ioctl = rtl8152_ioctl, | |
2629 | .ndo_start_xmit = rtl8152_start_xmit, | |
2630 | .ndo_tx_timeout = rtl8152_tx_timeout, | |
2631 | .ndo_set_rx_mode = rtl8152_set_rx_mode, | |
2632 | .ndo_set_mac_address = rtl8152_set_mac_address, | |
2633 | ||
2634 | .ndo_change_mtu = eth_change_mtu, | |
2635 | .ndo_validate_addr = eth_validate_addr, | |
2636 | }; | |
2637 | ||
2638 | static void r8152b_get_version(struct r8152 *tp) | |
2639 | { | |
2640 | u32 ocp_data; | |
2641 | u16 version; | |
2642 | ||
2643 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1); | |
2644 | version = (u16)(ocp_data & VERSION_MASK); | |
2645 | ||
2646 | switch (version) { | |
2647 | case 0x4c00: | |
2648 | tp->version = RTL_VER_01; | |
2649 | break; | |
2650 | case 0x4c10: | |
2651 | tp->version = RTL_VER_02; | |
2652 | break; | |
43779f8d | 2653 | case 0x5c00: |
2654 | tp->version = RTL_VER_03; | |
2655 | tp->mii.supports_gmii = 1; | |
2656 | break; | |
2657 | case 0x5c10: | |
2658 | tp->version = RTL_VER_04; | |
2659 | tp->mii.supports_gmii = 1; | |
2660 | break; | |
2661 | case 0x5c20: | |
2662 | tp->version = RTL_VER_05; | |
2663 | tp->mii.supports_gmii = 1; | |
2664 | break; | |
ac718b69 | 2665 | default: |
2666 | netif_info(tp, probe, tp->netdev, | |
2667 | "Unknown version 0x%04x\n", version); | |
2668 | break; | |
2669 | } | |
2670 | } | |
2671 | ||
e3fe0b1a | 2672 | static void rtl8152_unload(struct r8152 *tp) |
2673 | { | |
00a5e360 | 2674 | if (tp->version != RTL_VER_01) |
2675 | r8152_power_cut_en(tp, true); | |
e3fe0b1a | 2676 | } |
2677 | ||
43779f8d | 2678 | static void rtl8153_unload(struct r8152 *tp) |
2679 | { | |
2680 | r8153_power_cut_en(tp, 1); | |
2681 | } | |
2682 | ||
31ca1dec | 2683 | static int rtl_ops_init(struct r8152 *tp, const struct usb_device_id *id) |
c81229c9 | 2684 | { |
2685 | struct rtl_ops *ops = &tp->rtl_ops; | |
31ca1dec | 2686 | int ret = -ENODEV; |
c81229c9 | 2687 | |
2688 | switch (id->idVendor) { | |
2689 | case VENDOR_ID_REALTEK: | |
2690 | switch (id->idProduct) { | |
2691 | case PRODUCT_ID_RTL8152: | |
2692 | ops->init = r8152b_init; | |
2693 | ops->enable = rtl8152_enable; | |
2694 | ops->disable = rtl8152_disable; | |
2695 | ops->down = rtl8152_down; | |
2696 | ops->unload = rtl8152_unload; | |
31ca1dec | 2697 | ret = 0; |
c81229c9 | 2698 | break; |
43779f8d | 2699 | case PRODUCT_ID_RTL8153: |
2700 | ops->init = r8153_init; | |
2701 | ops->enable = rtl8153_enable; | |
2702 | ops->disable = rtl8152_disable; | |
2703 | ops->down = rtl8153_down; | |
2704 | ops->unload = rtl8153_unload; | |
31ca1dec | 2705 | ret = 0; |
43779f8d | 2706 | break; |
2707 | default: | |
43779f8d | 2708 | break; |
2709 | } | |
2710 | break; | |
2711 | ||
2712 | case VENDOR_ID_SAMSUNG: | |
2713 | switch (id->idProduct) { | |
2714 | case PRODUCT_ID_SAMSUNG: | |
2715 | ops->init = r8153_init; | |
2716 | ops->enable = rtl8153_enable; | |
2717 | ops->disable = rtl8152_disable; | |
2718 | ops->down = rtl8153_down; | |
2719 | ops->unload = rtl8153_unload; | |
31ca1dec | 2720 | ret = 0; |
43779f8d | 2721 | break; |
c81229c9 | 2722 | default: |
c81229c9 | 2723 | break; |
2724 | } | |
2725 | break; | |
2726 | ||
2727 | default: | |
c81229c9 | 2728 | break; |
2729 | } | |
2730 | ||
31ca1dec | 2731 | if (ret) |
2732 | netif_err(tp, probe, tp->netdev, "Unknown Device\n"); | |
2733 | ||
c81229c9 | 2734 | return ret; |
2735 | } | |
2736 | ||
ac718b69 | 2737 | static int rtl8152_probe(struct usb_interface *intf, |
2738 | const struct usb_device_id *id) | |
2739 | { | |
2740 | struct usb_device *udev = interface_to_usbdev(intf); | |
2741 | struct r8152 *tp; | |
2742 | struct net_device *netdev; | |
ebc2ec48 | 2743 | int ret; |
ac718b69 | 2744 | |
ac718b69 | 2745 | netdev = alloc_etherdev(sizeof(struct r8152)); |
2746 | if (!netdev) { | |
4a8deae2 | 2747 | dev_err(&intf->dev, "Out of memory\n"); |
ac718b69 | 2748 | return -ENOMEM; |
2749 | } | |
2750 | ||
ebc2ec48 | 2751 | SET_NETDEV_DEV(netdev, &intf->dev); |
ac718b69 | 2752 | tp = netdev_priv(netdev); |
2753 | tp->msg_enable = 0x7FFF; | |
2754 | ||
e3ad412a | 2755 | tp->udev = udev; |
2756 | tp->netdev = netdev; | |
2757 | tp->intf = intf; | |
2758 | ||
31ca1dec | 2759 | ret = rtl_ops_init(tp, id); |
2760 | if (ret) | |
2761 | goto out; | |
c81229c9 | 2762 | |
ebc2ec48 | 2763 | tasklet_init(&tp->tl, bottom_half, (unsigned long)tp); |
ac718b69 | 2764 | INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t); |
2765 | ||
ac718b69 | 2766 | netdev->netdev_ops = &rtl8152_netdev_ops; |
2767 | netdev->watchdog_timeo = RTL8152_TX_TIMEOUT; | |
5bd23881 | 2768 | |
2769 | netdev->features |= NETIF_F_IP_CSUM; | |
2770 | netdev->hw_features = NETIF_F_IP_CSUM; | |
ac718b69 | 2771 | SET_ETHTOOL_OPS(netdev, &ops); |
ac718b69 | 2772 | |
2773 | tp->mii.dev = netdev; | |
2774 | tp->mii.mdio_read = read_mii_word; | |
2775 | tp->mii.mdio_write = write_mii_word; | |
2776 | tp->mii.phy_id_mask = 0x3f; | |
2777 | tp->mii.reg_num_mask = 0x1f; | |
2778 | tp->mii.phy_id = R8152_PHY_ID; | |
2779 | tp->mii.supports_gmii = 0; | |
2780 | ||
2781 | r8152b_get_version(tp); | |
c81229c9 | 2782 | tp->rtl_ops.init(tp); |
ac718b69 | 2783 | set_ethernet_addr(tp); |
2784 | ||
ebc2ec48 | 2785 | ret = alloc_all_mem(tp); |
2786 | if (ret) | |
ac718b69 | 2787 | goto out; |
ac718b69 | 2788 | |
2789 | usb_set_intfdata(intf, tp); | |
ac718b69 | 2790 | |
ebc2ec48 | 2791 | ret = register_netdev(netdev); |
2792 | if (ret != 0) { | |
4a8deae2 | 2793 | netif_err(tp, probe, netdev, "couldn't register the device\n"); |
ebc2ec48 | 2794 | goto out1; |
ac718b69 | 2795 | } |
2796 | ||
4a8deae2 | 2797 | netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION); |
ac718b69 | 2798 | |
2799 | return 0; | |
2800 | ||
ac718b69 | 2801 | out1: |
ebc2ec48 | 2802 | usb_set_intfdata(intf, NULL); |
ac718b69 | 2803 | out: |
2804 | free_netdev(netdev); | |
ebc2ec48 | 2805 | return ret; |
ac718b69 | 2806 | } |
2807 | ||
ac718b69 | 2808 | static void rtl8152_disconnect(struct usb_interface *intf) |
2809 | { | |
2810 | struct r8152 *tp = usb_get_intfdata(intf); | |
2811 | ||
2812 | usb_set_intfdata(intf, NULL); | |
2813 | if (tp) { | |
2814 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
2815 | tasklet_kill(&tp->tl); | |
2816 | unregister_netdev(tp->netdev); | |
c81229c9 | 2817 | tp->rtl_ops.unload(tp); |
ebc2ec48 | 2818 | free_all_mem(tp); |
ac718b69 | 2819 | free_netdev(tp->netdev); |
2820 | } | |
2821 | } | |
2822 | ||
2823 | /* table of devices that work with this driver */ | |
2824 | static struct usb_device_id rtl8152_table[] = { | |
c7de7dec | 2825 | {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8152)}, |
2826 | {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8153)}, | |
2827 | {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, PRODUCT_ID_SAMSUNG)}, | |
ac718b69 | 2828 | {} |
2829 | }; | |
2830 | ||
2831 | MODULE_DEVICE_TABLE(usb, rtl8152_table); | |
2832 | ||
2833 | static struct usb_driver rtl8152_driver = { | |
2834 | .name = MODULENAME, | |
ebc2ec48 | 2835 | .id_table = rtl8152_table, |
ac718b69 | 2836 | .probe = rtl8152_probe, |
2837 | .disconnect = rtl8152_disconnect, | |
ac718b69 | 2838 | .suspend = rtl8152_suspend, |
ebc2ec48 | 2839 | .resume = rtl8152_resume, |
2840 | .reset_resume = rtl8152_resume, | |
ac718b69 | 2841 | }; |
2842 | ||
b4236daa | 2843 | module_usb_driver(rtl8152_driver); |
ac718b69 | 2844 | |
2845 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
2846 | MODULE_DESCRIPTION(DRIVER_DESC); | |
2847 | MODULE_LICENSE("GPL"); |