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r8152: remove the duplicate init for the list of rx_done
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ac718b69 1/*
c7de7dec 2 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
ac718b69 3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * version 2 as published by the Free Software Foundation.
7 *
8 */
9
ac718b69 10#include <linux/signal.h>
11#include <linux/slab.h>
12#include <linux/module.h>
ac718b69 13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/mii.h>
16#include <linux/ethtool.h>
17#include <linux/usb.h>
18#include <linux/crc32.h>
19#include <linux/if_vlan.h>
20#include <linux/uaccess.h>
ebc2ec48 21#include <linux/list.h>
5bd23881 22#include <linux/ip.h>
23#include <linux/ipv6.h>
6128d1bb 24#include <net/ip6_checksum.h>
4c4a6b1b 25#include <uapi/linux/mdio.h>
26#include <linux/mdio.h>
ac718b69 27
28/* Version Information */
b5403273 29#define DRIVER_VERSION "v1.07.0 (2014/10/09)"
ac718b69 30#define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
44d942a9 31#define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
ac718b69 32#define MODULENAME "r8152"
33
34#define R8152_PHY_ID 32
35
36#define PLA_IDR 0xc000
37#define PLA_RCR 0xc010
38#define PLA_RMS 0xc016
39#define PLA_RXFIFO_CTRL0 0xc0a0
40#define PLA_RXFIFO_CTRL1 0xc0a4
41#define PLA_RXFIFO_CTRL2 0xc0a8
42#define PLA_FMC 0xc0b4
43#define PLA_CFG_WOL 0xc0b6
43779f8d 44#define PLA_TEREDO_CFG 0xc0bc
ac718b69 45#define PLA_MAR 0xcd00
43779f8d 46#define PLA_BACKUP 0xd000
ac718b69 47#define PAL_BDC_CR 0xd1a0
43779f8d 48#define PLA_TEREDO_TIMER 0xd2cc
49#define PLA_REALWOW_TIMER 0xd2e8
ac718b69 50#define PLA_LEDSEL 0xdd90
51#define PLA_LED_FEATURE 0xdd92
52#define PLA_PHYAR 0xde00
43779f8d 53#define PLA_BOOT_CTRL 0xe004
ac718b69 54#define PLA_GPHY_INTR_IMR 0xe022
55#define PLA_EEE_CR 0xe040
56#define PLA_EEEP_CR 0xe080
57#define PLA_MAC_PWR_CTRL 0xe0c0
43779f8d 58#define PLA_MAC_PWR_CTRL2 0xe0ca
59#define PLA_MAC_PWR_CTRL3 0xe0cc
60#define PLA_MAC_PWR_CTRL4 0xe0ce
61#define PLA_WDT6_CTRL 0xe428
ac718b69 62#define PLA_TCR0 0xe610
63#define PLA_TCR1 0xe612
69b4b7a4 64#define PLA_MTPS 0xe615
ac718b69 65#define PLA_TXFIFO_CTRL 0xe618
4f1d4d54 66#define PLA_RSTTALLY 0xe800
ac718b69 67#define PLA_CR 0xe813
68#define PLA_CRWECR 0xe81c
21ff2e89 69#define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
70#define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
ac718b69 71#define PLA_CONFIG5 0xe822
72#define PLA_PHY_PWR 0xe84c
73#define PLA_OOB_CTRL 0xe84f
74#define PLA_CPCR 0xe854
75#define PLA_MISC_0 0xe858
76#define PLA_MISC_1 0xe85a
77#define PLA_OCP_GPHY_BASE 0xe86c
4f1d4d54 78#define PLA_TALLYCNT 0xe890
ac718b69 79#define PLA_SFF_STS_7 0xe8de
80#define PLA_PHYSTATUS 0xe908
81#define PLA_BP_BA 0xfc26
82#define PLA_BP_0 0xfc28
83#define PLA_BP_1 0xfc2a
84#define PLA_BP_2 0xfc2c
85#define PLA_BP_3 0xfc2e
86#define PLA_BP_4 0xfc30
87#define PLA_BP_5 0xfc32
88#define PLA_BP_6 0xfc34
89#define PLA_BP_7 0xfc36
43779f8d 90#define PLA_BP_EN 0xfc38
ac718b69 91
43779f8d 92#define USB_U2P3_CTRL 0xb460
ac718b69 93#define USB_DEV_STAT 0xb808
94#define USB_USB_CTRL 0xd406
95#define USB_PHY_CTRL 0xd408
96#define USB_TX_AGG 0xd40a
97#define USB_RX_BUF_TH 0xd40c
98#define USB_USB_TIMER 0xd428
43779f8d 99#define USB_RX_EARLY_AGG 0xd42c
ac718b69 100#define USB_PM_CTRL_STATUS 0xd432
101#define USB_TX_DMA 0xd434
43779f8d 102#define USB_TOLERANCE 0xd490
103#define USB_LPM_CTRL 0xd41a
ac718b69 104#define USB_UPS_CTRL 0xd800
43779f8d 105#define USB_MISC_0 0xd81a
106#define USB_POWER_CUT 0xd80a
107#define USB_AFE_CTRL2 0xd824
108#define USB_WDT11_CTRL 0xe43c
ac718b69 109#define USB_BP_BA 0xfc26
110#define USB_BP_0 0xfc28
111#define USB_BP_1 0xfc2a
112#define USB_BP_2 0xfc2c
113#define USB_BP_3 0xfc2e
114#define USB_BP_4 0xfc30
115#define USB_BP_5 0xfc32
116#define USB_BP_6 0xfc34
117#define USB_BP_7 0xfc36
43779f8d 118#define USB_BP_EN 0xfc38
ac718b69 119
120/* OCP Registers */
121#define OCP_ALDPS_CONFIG 0x2010
122#define OCP_EEE_CONFIG1 0x2080
123#define OCP_EEE_CONFIG2 0x2092
124#define OCP_EEE_CONFIG3 0x2094
ac244d3e 125#define OCP_BASE_MII 0xa400
ac718b69 126#define OCP_EEE_AR 0xa41a
127#define OCP_EEE_DATA 0xa41c
43779f8d 128#define OCP_PHY_STATUS 0xa420
129#define OCP_POWER_CFG 0xa430
130#define OCP_EEE_CFG 0xa432
131#define OCP_SRAM_ADDR 0xa436
132#define OCP_SRAM_DATA 0xa438
133#define OCP_DOWN_SPEED 0xa442
df35d283 134#define OCP_EEE_ABLE 0xa5c4
4c4a6b1b 135#define OCP_EEE_ADV 0xa5d0
df35d283 136#define OCP_EEE_LPABLE 0xa5d2
43779f8d 137#define OCP_ADC_CFG 0xbc06
138
139/* SRAM Register */
140#define SRAM_LPF_CFG 0x8012
141#define SRAM_10M_AMP1 0x8080
142#define SRAM_10M_AMP2 0x8082
143#define SRAM_IMPEDANCE 0x8084
ac718b69 144
145/* PLA_RCR */
146#define RCR_AAP 0x00000001
147#define RCR_APM 0x00000002
148#define RCR_AM 0x00000004
149#define RCR_AB 0x00000008
150#define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
151
152/* PLA_RXFIFO_CTRL0 */
153#define RXFIFO_THR1_NORMAL 0x00080002
154#define RXFIFO_THR1_OOB 0x01800003
155
156/* PLA_RXFIFO_CTRL1 */
157#define RXFIFO_THR2_FULL 0x00000060
158#define RXFIFO_THR2_HIGH 0x00000038
159#define RXFIFO_THR2_OOB 0x0000004a
43779f8d 160#define RXFIFO_THR2_NORMAL 0x00a0
ac718b69 161
162/* PLA_RXFIFO_CTRL2 */
163#define RXFIFO_THR3_FULL 0x00000078
164#define RXFIFO_THR3_HIGH 0x00000048
165#define RXFIFO_THR3_OOB 0x0000005a
43779f8d 166#define RXFIFO_THR3_NORMAL 0x0110
ac718b69 167
168/* PLA_TXFIFO_CTRL */
169#define TXFIFO_THR_NORMAL 0x00400008
43779f8d 170#define TXFIFO_THR_NORMAL2 0x01000008
ac718b69 171
172/* PLA_FMC */
173#define FMC_FCR_MCU_EN 0x0001
174
175/* PLA_EEEP_CR */
176#define EEEP_CR_EEEP_TX 0x0002
177
43779f8d 178/* PLA_WDT6_CTRL */
179#define WDT6_SET_MODE 0x0010
180
ac718b69 181/* PLA_TCR0 */
182#define TCR0_TX_EMPTY 0x0800
183#define TCR0_AUTO_FIFO 0x0080
184
185/* PLA_TCR1 */
186#define VERSION_MASK 0x7cf0
187
69b4b7a4 188/* PLA_MTPS */
189#define MTPS_JUMBO (12 * 1024 / 64)
190#define MTPS_DEFAULT (6 * 1024 / 64)
191
4f1d4d54 192/* PLA_RSTTALLY */
193#define TALLY_RESET 0x0001
194
ac718b69 195/* PLA_CR */
196#define CR_RST 0x10
197#define CR_RE 0x08
198#define CR_TE 0x04
199
200/* PLA_CRWECR */
201#define CRWECR_NORAML 0x00
202#define CRWECR_CONFIG 0xc0
203
204/* PLA_OOB_CTRL */
205#define NOW_IS_OOB 0x80
206#define TXFIFO_EMPTY 0x20
207#define RXFIFO_EMPTY 0x10
208#define LINK_LIST_READY 0x02
209#define DIS_MCU_CLROOB 0x01
210#define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
211
212/* PLA_MISC_1 */
213#define RXDY_GATED_EN 0x0008
214
215/* PLA_SFF_STS_7 */
216#define RE_INIT_LL 0x8000
217#define MCU_BORW_EN 0x4000
218
219/* PLA_CPCR */
220#define CPCR_RX_VLAN 0x0040
221
222/* PLA_CFG_WOL */
223#define MAGIC_EN 0x0001
224
43779f8d 225/* PLA_TEREDO_CFG */
226#define TEREDO_SEL 0x8000
227#define TEREDO_WAKE_MASK 0x7f00
228#define TEREDO_RS_EVENT_MASK 0x00fe
229#define OOB_TEREDO_EN 0x0001
230
ac718b69 231/* PAL_BDC_CR */
232#define ALDPS_PROXY_MODE 0x0001
233
21ff2e89 234/* PLA_CONFIG34 */
235#define LINK_ON_WAKE_EN 0x0010
236#define LINK_OFF_WAKE_EN 0x0008
237
ac718b69 238/* PLA_CONFIG5 */
21ff2e89 239#define BWF_EN 0x0040
240#define MWF_EN 0x0020
241#define UWF_EN 0x0010
ac718b69 242#define LAN_WAKE_EN 0x0002
243
244/* PLA_LED_FEATURE */
245#define LED_MODE_MASK 0x0700
246
247/* PLA_PHY_PWR */
248#define TX_10M_IDLE_EN 0x0080
249#define PFM_PWM_SWITCH 0x0040
250
251/* PLA_MAC_PWR_CTRL */
252#define D3_CLK_GATED_EN 0x00004000
253#define MCU_CLK_RATIO 0x07010f07
254#define MCU_CLK_RATIO_MASK 0x0f0f0f0f
43779f8d 255#define ALDPS_SPDWN_RATIO 0x0f87
256
257/* PLA_MAC_PWR_CTRL2 */
258#define EEE_SPDWN_RATIO 0x8007
259
260/* PLA_MAC_PWR_CTRL3 */
261#define PKT_AVAIL_SPDWN_EN 0x0100
262#define SUSPEND_SPDWN_EN 0x0004
263#define U1U2_SPDWN_EN 0x0002
264#define L1_SPDWN_EN 0x0001
265
266/* PLA_MAC_PWR_CTRL4 */
267#define PWRSAVE_SPDWN_EN 0x1000
268#define RXDV_SPDWN_EN 0x0800
269#define TX10MIDLE_EN 0x0100
270#define TP100_SPDWN_EN 0x0020
271#define TP500_SPDWN_EN 0x0010
272#define TP1000_SPDWN_EN 0x0008
273#define EEE_SPDWN_EN 0x0001
ac718b69 274
275/* PLA_GPHY_INTR_IMR */
276#define GPHY_STS_MSK 0x0001
277#define SPEED_DOWN_MSK 0x0002
278#define SPDWN_RXDV_MSK 0x0004
279#define SPDWN_LINKCHG_MSK 0x0008
280
281/* PLA_PHYAR */
282#define PHYAR_FLAG 0x80000000
283
284/* PLA_EEE_CR */
285#define EEE_RX_EN 0x0001
286#define EEE_TX_EN 0x0002
287
43779f8d 288/* PLA_BOOT_CTRL */
289#define AUTOLOAD_DONE 0x0002
290
ac718b69 291/* USB_DEV_STAT */
292#define STAT_SPEED_MASK 0x0006
293#define STAT_SPEED_HIGH 0x0000
a3cc465d 294#define STAT_SPEED_FULL 0x0002
ac718b69 295
296/* USB_TX_AGG */
297#define TX_AGG_MAX_THRESHOLD 0x03
298
299/* USB_RX_BUF_TH */
43779f8d 300#define RX_THR_SUPPER 0x0c350180
8e1f51bd 301#define RX_THR_HIGH 0x7a120180
43779f8d 302#define RX_THR_SLOW 0xffff0180
ac718b69 303
304/* USB_TX_DMA */
305#define TEST_MODE_DISABLE 0x00000001
306#define TX_SIZE_ADJUST1 0x00000100
307
308/* USB_UPS_CTRL */
309#define POWER_CUT 0x0100
310
311/* USB_PM_CTRL_STATUS */
8e1f51bd 312#define RESUME_INDICATE 0x0001
ac718b69 313
314/* USB_USB_CTRL */
315#define RX_AGG_DISABLE 0x0010
316
43779f8d 317/* USB_U2P3_CTRL */
318#define U2P3_ENABLE 0x0001
319
320/* USB_POWER_CUT */
321#define PWR_EN 0x0001
322#define PHASE2_EN 0x0008
323
324/* USB_MISC_0 */
325#define PCUT_STATUS 0x0001
326
327/* USB_RX_EARLY_AGG */
328#define EARLY_AGG_SUPPER 0x0e832981
329#define EARLY_AGG_HIGH 0x0e837a12
330#define EARLY_AGG_SLOW 0x0e83ffff
331
332/* USB_WDT11_CTRL */
333#define TIMER11_EN 0x0001
334
335/* USB_LPM_CTRL */
336#define LPM_TIMER_MASK 0x0c
337#define LPM_TIMER_500MS 0x04 /* 500 ms */
338#define LPM_TIMER_500US 0x0c /* 500 us */
339
340/* USB_AFE_CTRL2 */
341#define SEN_VAL_MASK 0xf800
342#define SEN_VAL_NORMAL 0xa000
343#define SEL_RXIDLE 0x0100
344
ac718b69 345/* OCP_ALDPS_CONFIG */
346#define ENPWRSAVE 0x8000
347#define ENPDNPS 0x0200
348#define LINKENA 0x0100
349#define DIS_SDSAVE 0x0010
350
43779f8d 351/* OCP_PHY_STATUS */
352#define PHY_STAT_MASK 0x0007
353#define PHY_STAT_LAN_ON 3
354#define PHY_STAT_PWRDN 5
355
356/* OCP_POWER_CFG */
357#define EEE_CLKDIV_EN 0x8000
358#define EN_ALDPS 0x0004
359#define EN_10M_PLLOFF 0x0001
360
ac718b69 361/* OCP_EEE_CONFIG1 */
362#define RG_TXLPI_MSK_HFDUP 0x8000
363#define RG_MATCLR_EN 0x4000
364#define EEE_10_CAP 0x2000
365#define EEE_NWAY_EN 0x1000
366#define TX_QUIET_EN 0x0200
367#define RX_QUIET_EN 0x0100
d24f6134 368#define sd_rise_time_mask 0x0070
4c4a6b1b 369#define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
ac718b69 370#define RG_RXLPI_MSK_HFDUP 0x0008
371#define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
372
373/* OCP_EEE_CONFIG2 */
374#define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
375#define RG_DACQUIET_EN 0x0400
376#define RG_LDVQUIET_EN 0x0200
377#define RG_CKRSEL 0x0020
378#define RG_EEEPRG_EN 0x0010
379
380/* OCP_EEE_CONFIG3 */
d24f6134 381#define fast_snr_mask 0xff80
4c4a6b1b 382#define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
ac718b69 383#define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
384#define MSK_PH 0x0006 /* bit 0 ~ 3 */
385
386/* OCP_EEE_AR */
387/* bit[15:14] function */
388#define FUN_ADDR 0x0000
389#define FUN_DATA 0x4000
390/* bit[4:0] device addr */
ac718b69 391
43779f8d 392/* OCP_EEE_CFG */
393#define CTAP_SHORT_EN 0x0040
394#define EEE10_EN 0x0010
395
396/* OCP_DOWN_SPEED */
397#define EN_10M_BGOFF 0x0080
398
43779f8d 399/* OCP_ADC_CFG */
400#define CKADSEL_L 0x0100
401#define ADC_EN 0x0080
402#define EN_EMI_L 0x0040
403
404/* SRAM_LPF_CFG */
405#define LPF_AUTO_TUNE 0x8000
406
407/* SRAM_10M_AMP1 */
408#define GDAC_IB_UPALL 0x0008
409
410/* SRAM_10M_AMP2 */
411#define AMP_DN 0x0200
412
413/* SRAM_IMPEDANCE */
414#define RX_DRIVING_MASK 0x6000
415
ac718b69 416enum rtl_register_content {
43779f8d 417 _1000bps = 0x10,
ac718b69 418 _100bps = 0x08,
419 _10bps = 0x04,
420 LINK_STATUS = 0x02,
421 FULL_DUP = 0x01,
422};
423
1764bcd9 424#define RTL8152_MAX_TX 4
ebc2ec48 425#define RTL8152_MAX_RX 10
40a82917 426#define INTBUFSIZE 2
8e1f51bd 427#define CRC_SIZE 4
428#define TX_ALIGN 4
429#define RX_ALIGN 8
40a82917 430
431#define INTR_LINK 0x0004
ebc2ec48 432
ac718b69 433#define RTL8152_REQT_READ 0xc0
434#define RTL8152_REQT_WRITE 0x40
435#define RTL8152_REQ_GET_REGS 0x05
436#define RTL8152_REQ_SET_REGS 0x05
437
438#define BYTE_EN_DWORD 0xff
439#define BYTE_EN_WORD 0x33
440#define BYTE_EN_BYTE 0x11
441#define BYTE_EN_SIX_BYTES 0x3f
442#define BYTE_EN_START_MASK 0x0f
443#define BYTE_EN_END_MASK 0xf0
444
69b4b7a4 445#define RTL8153_MAX_PACKET 9216 /* 9K */
446#define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN)
ac718b69 447#define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
69b4b7a4 448#define RTL8153_RMS RTL8153_MAX_PACKET
b8125404 449#define RTL8152_TX_TIMEOUT (5 * HZ)
ac718b69 450
451/* rtl8152 flags */
452enum rtl8152_flags {
453 RTL8152_UNPLUG = 0,
ac718b69 454 RTL8152_SET_RX_MODE,
40a82917 455 WORK_ENABLE,
456 RTL8152_LINK_CHG,
9a4be1bd 457 SELECTIVE_SUSPEND,
aa66a5f1 458 PHY_RESET,
0c3121fc 459 SCHEDULE_TASKLET,
ac718b69 460};
461
462/* Define these values to match your device */
463#define VENDOR_ID_REALTEK 0x0bda
43779f8d 464#define VENDOR_ID_SAMSUNG 0x04e8
ac718b69 465
466#define MCU_TYPE_PLA 0x0100
467#define MCU_TYPE_USB 0x0000
468
c7de7dec 469#define REALTEK_USB_DEVICE(vend, prod) \
470 USB_DEVICE_INTERFACE_CLASS(vend, prod, USB_CLASS_VENDOR_SPEC)
471
4f1d4d54 472struct tally_counter {
473 __le64 tx_packets;
474 __le64 rx_packets;
475 __le64 tx_errors;
476 __le32 rx_errors;
477 __le16 rx_missed;
478 __le16 align_errors;
479 __le32 tx_one_collision;
480 __le32 tx_multi_collision;
481 __le64 rx_unicast;
482 __le64 rx_broadcast;
483 __le32 rx_multicast;
484 __le16 tx_aborted;
f37119c5 485 __le16 tx_underrun;
4f1d4d54 486};
487
ac718b69 488struct rx_desc {
500b6d7e 489 __le32 opts1;
ac718b69 490#define RX_LEN_MASK 0x7fff
565cab0a 491
500b6d7e 492 __le32 opts2;
565cab0a 493#define RD_UDP_CS (1 << 23)
494#define RD_TCP_CS (1 << 22)
6128d1bb 495#define RD_IPV6_CS (1 << 20)
565cab0a 496#define RD_IPV4_CS (1 << 19)
497
500b6d7e 498 __le32 opts3;
565cab0a 499#define IPF (1 << 23) /* IP checksum fail */
500#define UDPF (1 << 22) /* UDP checksum fail */
501#define TCPF (1 << 21) /* TCP checksum fail */
c5554298 502#define RX_VLAN_TAG (1 << 16)
565cab0a 503
500b6d7e 504 __le32 opts4;
505 __le32 opts5;
506 __le32 opts6;
ac718b69 507};
508
509struct tx_desc {
500b6d7e 510 __le32 opts1;
ac718b69 511#define TX_FS (1 << 31) /* First segment of a packet */
512#define TX_LS (1 << 30) /* Final segment of a packet */
60c89071 513#define GTSENDV4 (1 << 28)
6128d1bb 514#define GTSENDV6 (1 << 27)
60c89071 515#define GTTCPHO_SHIFT 18
6128d1bb 516#define GTTCPHO_MAX 0x7fU
60c89071 517#define TX_LEN_MAX 0x3ffffU
5bd23881 518
500b6d7e 519 __le32 opts2;
5bd23881 520#define UDP_CS (1 << 31) /* Calculate UDP/IP checksum */
521#define TCP_CS (1 << 30) /* Calculate TCP/IP checksum */
522#define IPV4_CS (1 << 29) /* Calculate IPv4 checksum */
523#define IPV6_CS (1 << 28) /* Calculate IPv6 checksum */
60c89071 524#define MSS_SHIFT 17
525#define MSS_MAX 0x7ffU
526#define TCPHO_SHIFT 17
6128d1bb 527#define TCPHO_MAX 0x7ffU
c5554298 528#define TX_VLAN_TAG (1 << 16)
ac718b69 529};
530
dff4e8ad 531struct r8152;
532
ebc2ec48 533struct rx_agg {
534 struct list_head list;
535 struct urb *urb;
dff4e8ad 536 struct r8152 *context;
ebc2ec48 537 void *buffer;
538 void *head;
539};
540
541struct tx_agg {
542 struct list_head list;
543 struct urb *urb;
dff4e8ad 544 struct r8152 *context;
ebc2ec48 545 void *buffer;
546 void *head;
547 u32 skb_num;
548 u32 skb_len;
549};
550
ac718b69 551struct r8152 {
552 unsigned long flags;
553 struct usb_device *udev;
554 struct tasklet_struct tl;
40a82917 555 struct usb_interface *intf;
ac718b69 556 struct net_device *netdev;
40a82917 557 struct urb *intr_urb;
ebc2ec48 558 struct tx_agg tx_info[RTL8152_MAX_TX];
559 struct rx_agg rx_info[RTL8152_MAX_RX];
560 struct list_head rx_done, tx_free;
561 struct sk_buff_head tx_queue;
562 spinlock_t rx_lock, tx_lock;
ac718b69 563 struct delayed_work schedule;
564 struct mii_if_info mii;
b5403273 565 struct mutex control; /* use for hw setting */
c81229c9 566
567 struct rtl_ops {
568 void (*init)(struct r8152 *);
569 int (*enable)(struct r8152 *);
570 void (*disable)(struct r8152 *);
7e9da481 571 void (*up)(struct r8152 *);
c81229c9 572 void (*down)(struct r8152 *);
573 void (*unload)(struct r8152 *);
df35d283 574 int (*eee_get)(struct r8152 *, struct ethtool_eee *);
575 int (*eee_set)(struct r8152 *, struct ethtool_eee *);
c81229c9 576 } rtl_ops;
577
40a82917 578 int intr_interval;
21ff2e89 579 u32 saved_wolopts;
ac718b69 580 u32 msg_enable;
dd1b119c 581 u32 tx_qlen;
ac718b69 582 u16 ocp_base;
40a82917 583 u8 *intr_buff;
ac718b69 584 u8 version;
585 u8 speed;
586};
587
588enum rtl_version {
589 RTL_VER_UNKNOWN = 0,
590 RTL_VER_01,
43779f8d 591 RTL_VER_02,
592 RTL_VER_03,
593 RTL_VER_04,
594 RTL_VER_05,
595 RTL_VER_MAX
ac718b69 596};
597
60c89071 598enum tx_csum_stat {
599 TX_CSUM_SUCCESS = 0,
600 TX_CSUM_TSO,
601 TX_CSUM_NONE
602};
603
ac718b69 604/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
605 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
606 */
607static const int multicast_filter_limit = 32;
52aec126 608static unsigned int agg_buf_sz = 16384;
ac718b69 609
52aec126 610#define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \
60c89071 611 VLAN_ETH_HLEN - VLAN_HLEN)
612
ac718b69 613static
614int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
615{
31787f53 616 int ret;
617 void *tmp;
618
619 tmp = kmalloc(size, GFP_KERNEL);
620 if (!tmp)
621 return -ENOMEM;
622
623 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
b209af99 624 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
625 value, index, tmp, size, 500);
31787f53 626
627 memcpy(data, tmp, size);
628 kfree(tmp);
629
630 return ret;
ac718b69 631}
632
633static
634int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
635{
31787f53 636 int ret;
637 void *tmp;
638
c4438f03 639 tmp = kmemdup(data, size, GFP_KERNEL);
31787f53 640 if (!tmp)
641 return -ENOMEM;
642
31787f53 643 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
b209af99 644 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
645 value, index, tmp, size, 500);
31787f53 646
647 kfree(tmp);
db8515ef 648
31787f53 649 return ret;
ac718b69 650}
651
652static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
b209af99 653 void *data, u16 type)
ac718b69 654{
45f4a19f 655 u16 limit = 64;
656 int ret = 0;
ac718b69 657
658 if (test_bit(RTL8152_UNPLUG, &tp->flags))
659 return -ENODEV;
660
661 /* both size and indix must be 4 bytes align */
662 if ((size & 3) || !size || (index & 3) || !data)
663 return -EPERM;
664
665 if ((u32)index + (u32)size > 0xffff)
666 return -EPERM;
667
668 while (size) {
669 if (size > limit) {
670 ret = get_registers(tp, index, type, limit, data);
671 if (ret < 0)
672 break;
673
674 index += limit;
675 data += limit;
676 size -= limit;
677 } else {
678 ret = get_registers(tp, index, type, size, data);
679 if (ret < 0)
680 break;
681
682 index += size;
683 data += size;
684 size = 0;
685 break;
686 }
687 }
688
67610496 689 if (ret == -ENODEV)
690 set_bit(RTL8152_UNPLUG, &tp->flags);
691
ac718b69 692 return ret;
693}
694
695static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
b209af99 696 u16 size, void *data, u16 type)
ac718b69 697{
45f4a19f 698 int ret;
699 u16 byteen_start, byteen_end, byen;
700 u16 limit = 512;
ac718b69 701
702 if (test_bit(RTL8152_UNPLUG, &tp->flags))
703 return -ENODEV;
704
705 /* both size and indix must be 4 bytes align */
706 if ((size & 3) || !size || (index & 3) || !data)
707 return -EPERM;
708
709 if ((u32)index + (u32)size > 0xffff)
710 return -EPERM;
711
712 byteen_start = byteen & BYTE_EN_START_MASK;
713 byteen_end = byteen & BYTE_EN_END_MASK;
714
715 byen = byteen_start | (byteen_start << 4);
716 ret = set_registers(tp, index, type | byen, 4, data);
717 if (ret < 0)
718 goto error1;
719
720 index += 4;
721 data += 4;
722 size -= 4;
723
724 if (size) {
725 size -= 4;
726
727 while (size) {
728 if (size > limit) {
729 ret = set_registers(tp, index,
b209af99 730 type | BYTE_EN_DWORD,
731 limit, data);
ac718b69 732 if (ret < 0)
733 goto error1;
734
735 index += limit;
736 data += limit;
737 size -= limit;
738 } else {
739 ret = set_registers(tp, index,
b209af99 740 type | BYTE_EN_DWORD,
741 size, data);
ac718b69 742 if (ret < 0)
743 goto error1;
744
745 index += size;
746 data += size;
747 size = 0;
748 break;
749 }
750 }
751
752 byen = byteen_end | (byteen_end >> 4);
753 ret = set_registers(tp, index, type | byen, 4, data);
754 if (ret < 0)
755 goto error1;
756 }
757
758error1:
67610496 759 if (ret == -ENODEV)
760 set_bit(RTL8152_UNPLUG, &tp->flags);
761
ac718b69 762 return ret;
763}
764
765static inline
766int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
767{
768 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
769}
770
771static inline
772int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
773{
774 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
775}
776
777static inline
778int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
779{
780 return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
781}
782
783static inline
784int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
785{
786 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
787}
788
789static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
790{
c8826de8 791 __le32 data;
ac718b69 792
c8826de8 793 generic_ocp_read(tp, index, sizeof(data), &data, type);
ac718b69 794
795 return __le32_to_cpu(data);
796}
797
798static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
799{
c8826de8 800 __le32 tmp = __cpu_to_le32(data);
801
802 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
ac718b69 803}
804
805static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
806{
807 u32 data;
c8826de8 808 __le32 tmp;
ac718b69 809 u8 shift = index & 2;
810
811 index &= ~3;
812
c8826de8 813 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
ac718b69 814
c8826de8 815 data = __le32_to_cpu(tmp);
ac718b69 816 data >>= (shift * 8);
817 data &= 0xffff;
818
819 return (u16)data;
820}
821
822static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
823{
c8826de8 824 u32 mask = 0xffff;
825 __le32 tmp;
ac718b69 826 u16 byen = BYTE_EN_WORD;
827 u8 shift = index & 2;
828
829 data &= mask;
830
831 if (index & 2) {
832 byen <<= shift;
833 mask <<= (shift * 8);
834 data <<= (shift * 8);
835 index &= ~3;
836 }
837
c8826de8 838 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
ac718b69 839
c8826de8 840 data |= __le32_to_cpu(tmp) & ~mask;
841 tmp = __cpu_to_le32(data);
ac718b69 842
c8826de8 843 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
ac718b69 844}
845
846static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
847{
848 u32 data;
c8826de8 849 __le32 tmp;
ac718b69 850 u8 shift = index & 3;
851
852 index &= ~3;
853
c8826de8 854 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
ac718b69 855
c8826de8 856 data = __le32_to_cpu(tmp);
ac718b69 857 data >>= (shift * 8);
858 data &= 0xff;
859
860 return (u8)data;
861}
862
863static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
864{
c8826de8 865 u32 mask = 0xff;
866 __le32 tmp;
ac718b69 867 u16 byen = BYTE_EN_BYTE;
868 u8 shift = index & 3;
869
870 data &= mask;
871
872 if (index & 3) {
873 byen <<= shift;
874 mask <<= (shift * 8);
875 data <<= (shift * 8);
876 index &= ~3;
877 }
878
c8826de8 879 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
ac718b69 880
c8826de8 881 data |= __le32_to_cpu(tmp) & ~mask;
882 tmp = __cpu_to_le32(data);
ac718b69 883
c8826de8 884 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
ac718b69 885}
886
ac244d3e 887static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
e3fe0b1a 888{
889 u16 ocp_base, ocp_index;
890
891 ocp_base = addr & 0xf000;
892 if (ocp_base != tp->ocp_base) {
893 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
894 tp->ocp_base = ocp_base;
895 }
896
897 ocp_index = (addr & 0x0fff) | 0xb000;
ac244d3e 898 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
e3fe0b1a 899}
900
ac244d3e 901static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
ac718b69 902{
ac244d3e 903 u16 ocp_base, ocp_index;
ac718b69 904
ac244d3e 905 ocp_base = addr & 0xf000;
906 if (ocp_base != tp->ocp_base) {
907 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
908 tp->ocp_base = ocp_base;
ac718b69 909 }
ac244d3e 910
911 ocp_index = (addr & 0x0fff) | 0xb000;
912 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
ac718b69 913}
914
ac244d3e 915static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
ac718b69 916{
ac244d3e 917 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
918}
ac718b69 919
ac244d3e 920static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
921{
922 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
ac718b69 923}
924
43779f8d 925static void sram_write(struct r8152 *tp, u16 addr, u16 data)
926{
927 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
928 ocp_reg_write(tp, OCP_SRAM_DATA, data);
929}
930
931static u16 sram_read(struct r8152 *tp, u16 addr)
932{
933 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
934 return ocp_reg_read(tp, OCP_SRAM_DATA);
935}
936
ac718b69 937static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
938{
939 struct r8152 *tp = netdev_priv(netdev);
9a4be1bd 940 int ret;
ac718b69 941
6871438c 942 if (test_bit(RTL8152_UNPLUG, &tp->flags))
943 return -ENODEV;
944
ac718b69 945 if (phy_id != R8152_PHY_ID)
946 return -EINVAL;
947
9a4be1bd 948 ret = r8152_mdio_read(tp, reg);
949
9a4be1bd 950 return ret;
ac718b69 951}
952
953static
954void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
955{
956 struct r8152 *tp = netdev_priv(netdev);
957
6871438c 958 if (test_bit(RTL8152_UNPLUG, &tp->flags))
959 return;
960
ac718b69 961 if (phy_id != R8152_PHY_ID)
962 return;
963
964 r8152_mdio_write(tp, reg, val);
965}
966
b209af99 967static int
968r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
ebc2ec48 969
8ba789ab 970static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
971{
972 struct r8152 *tp = netdev_priv(netdev);
973 struct sockaddr *addr = p;
ea6a7112 974 int ret = -EADDRNOTAVAIL;
8ba789ab 975
976 if (!is_valid_ether_addr(addr->sa_data))
ea6a7112 977 goto out1;
978
979 ret = usb_autopm_get_interface(tp->intf);
980 if (ret < 0)
981 goto out1;
8ba789ab 982
b5403273 983 mutex_lock(&tp->control);
984
8ba789ab 985 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
986
987 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
988 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
989 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
990
b5403273 991 mutex_unlock(&tp->control);
992
ea6a7112 993 usb_autopm_put_interface(tp->intf);
994out1:
995 return ret;
8ba789ab 996}
997
179bb6d7 998static int set_ethernet_addr(struct r8152 *tp)
ac718b69 999{
1000 struct net_device *dev = tp->netdev;
179bb6d7 1001 struct sockaddr sa;
8a91c824 1002 int ret;
ac718b69 1003
8a91c824 1004 if (tp->version == RTL_VER_01)
179bb6d7 1005 ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data);
8a91c824 1006 else
179bb6d7 1007 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data);
8a91c824 1008
1009 if (ret < 0) {
179bb6d7 1010 netif_err(tp, probe, dev, "Get ether addr fail\n");
1011 } else if (!is_valid_ether_addr(sa.sa_data)) {
1012 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1013 sa.sa_data);
1014 eth_hw_addr_random(dev);
1015 ether_addr_copy(sa.sa_data, dev->dev_addr);
1016 ret = rtl8152_set_mac_address(dev, &sa);
1017 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1018 sa.sa_data);
8a91c824 1019 } else {
179bb6d7 1020 if (tp->version == RTL_VER_01)
1021 ether_addr_copy(dev->dev_addr, sa.sa_data);
1022 else
1023 ret = rtl8152_set_mac_address(dev, &sa);
ac718b69 1024 }
179bb6d7 1025
1026 return ret;
ac718b69 1027}
1028
ac718b69 1029static void read_bulk_callback(struct urb *urb)
1030{
ac718b69 1031 struct net_device *netdev;
ac718b69 1032 int status = urb->status;
ebc2ec48 1033 struct rx_agg *agg;
1034 struct r8152 *tp;
ac718b69 1035 int result;
ac718b69 1036
ebc2ec48 1037 agg = urb->context;
1038 if (!agg)
1039 return;
1040
1041 tp = agg->context;
ac718b69 1042 if (!tp)
1043 return;
ebc2ec48 1044
ac718b69 1045 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1046 return;
ebc2ec48 1047
1048 if (!test_bit(WORK_ENABLE, &tp->flags))
1049 return;
1050
ac718b69 1051 netdev = tp->netdev;
7559fb2f 1052
1053 /* When link down, the driver would cancel all bulks. */
1054 /* This avoid the re-submitting bulk */
ebc2ec48 1055 if (!netif_carrier_ok(netdev))
ac718b69 1056 return;
1057
9a4be1bd 1058 usb_mark_last_busy(tp->udev);
1059
ac718b69 1060 switch (status) {
1061 case 0:
ebc2ec48 1062 if (urb->actual_length < ETH_ZLEN)
1063 break;
1064
2685d410 1065 spin_lock(&tp->rx_lock);
ebc2ec48 1066 list_add_tail(&agg->list, &tp->rx_done);
2685d410 1067 spin_unlock(&tp->rx_lock);
ebc2ec48 1068 tasklet_schedule(&tp->tl);
1069 return;
ac718b69 1070 case -ESHUTDOWN:
1071 set_bit(RTL8152_UNPLUG, &tp->flags);
1072 netif_device_detach(tp->netdev);
ebc2ec48 1073 return;
ac718b69 1074 case -ENOENT:
1075 return; /* the urb is in unlink state */
1076 case -ETIME:
4a8deae2
HW
1077 if (net_ratelimit())
1078 netdev_warn(netdev, "maybe reset is needed?\n");
ebc2ec48 1079 break;
ac718b69 1080 default:
4a8deae2
HW
1081 if (net_ratelimit())
1082 netdev_warn(netdev, "Rx status %d\n", status);
ebc2ec48 1083 break;
ac718b69 1084 }
1085
ebc2ec48 1086 result = r8152_submit_rx(tp, agg, GFP_ATOMIC);
ac718b69 1087 if (result == -ENODEV) {
67610496 1088 set_bit(RTL8152_UNPLUG, &tp->flags);
ac718b69 1089 netif_device_detach(tp->netdev);
1090 } else if (result) {
2685d410 1091 spin_lock(&tp->rx_lock);
ebc2ec48 1092 list_add_tail(&agg->list, &tp->rx_done);
2685d410 1093 spin_unlock(&tp->rx_lock);
ebc2ec48 1094 tasklet_schedule(&tp->tl);
ac718b69 1095 }
ac718b69 1096}
1097
ebc2ec48 1098static void write_bulk_callback(struct urb *urb)
ac718b69 1099{
ebc2ec48 1100 struct net_device_stats *stats;
d104eafa 1101 struct net_device *netdev;
ebc2ec48 1102 struct tx_agg *agg;
ac718b69 1103 struct r8152 *tp;
ebc2ec48 1104 int status = urb->status;
ac718b69 1105
ebc2ec48 1106 agg = urb->context;
1107 if (!agg)
ac718b69 1108 return;
1109
ebc2ec48 1110 tp = agg->context;
1111 if (!tp)
1112 return;
1113
d104eafa 1114 netdev = tp->netdev;
05e0f1aa 1115 stats = &netdev->stats;
ebc2ec48 1116 if (status) {
4a8deae2 1117 if (net_ratelimit())
d104eafa 1118 netdev_warn(netdev, "Tx status %d\n", status);
ebc2ec48 1119 stats->tx_errors += agg->skb_num;
ac718b69 1120 } else {
ebc2ec48 1121 stats->tx_packets += agg->skb_num;
1122 stats->tx_bytes += agg->skb_len;
ac718b69 1123 }
1124
2685d410 1125 spin_lock(&tp->tx_lock);
ebc2ec48 1126 list_add_tail(&agg->list, &tp->tx_free);
2685d410 1127 spin_unlock(&tp->tx_lock);
ebc2ec48 1128
9a4be1bd 1129 usb_autopm_put_interface_async(tp->intf);
1130
d104eafa 1131 if (!netif_carrier_ok(netdev))
ebc2ec48 1132 return;
1133
1134 if (!test_bit(WORK_ENABLE, &tp->flags))
1135 return;
1136
1137 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1138 return;
1139
1140 if (!skb_queue_empty(&tp->tx_queue))
0c3121fc 1141 tasklet_schedule(&tp->tl);
ac718b69 1142}
1143
40a82917 1144static void intr_callback(struct urb *urb)
1145{
1146 struct r8152 *tp;
500b6d7e 1147 __le16 *d;
40a82917 1148 int status = urb->status;
1149 int res;
1150
1151 tp = urb->context;
1152 if (!tp)
1153 return;
1154
1155 if (!test_bit(WORK_ENABLE, &tp->flags))
1156 return;
1157
1158 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1159 return;
1160
1161 switch (status) {
1162 case 0: /* success */
1163 break;
1164 case -ECONNRESET: /* unlink */
1165 case -ESHUTDOWN:
1166 netif_device_detach(tp->netdev);
1167 case -ENOENT:
d59c876d 1168 case -EPROTO:
1169 netif_info(tp, intr, tp->netdev,
1170 "Stop submitting intr, status %d\n", status);
40a82917 1171 return;
1172 case -EOVERFLOW:
1173 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1174 goto resubmit;
1175 /* -EPIPE: should clear the halt */
1176 default:
1177 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1178 goto resubmit;
1179 }
1180
1181 d = urb->transfer_buffer;
1182 if (INTR_LINK & __le16_to_cpu(d[0])) {
1183 if (!(tp->speed & LINK_STATUS)) {
1184 set_bit(RTL8152_LINK_CHG, &tp->flags);
1185 schedule_delayed_work(&tp->schedule, 0);
1186 }
1187 } else {
1188 if (tp->speed & LINK_STATUS) {
1189 set_bit(RTL8152_LINK_CHG, &tp->flags);
1190 schedule_delayed_work(&tp->schedule, 0);
1191 }
1192 }
1193
1194resubmit:
1195 res = usb_submit_urb(urb, GFP_ATOMIC);
67610496 1196 if (res == -ENODEV) {
1197 set_bit(RTL8152_UNPLUG, &tp->flags);
40a82917 1198 netif_device_detach(tp->netdev);
67610496 1199 } else if (res) {
40a82917 1200 netif_err(tp, intr, tp->netdev,
4a8deae2 1201 "can't resubmit intr, status %d\n", res);
67610496 1202 }
40a82917 1203}
1204
ebc2ec48 1205static inline void *rx_agg_align(void *data)
1206{
8e1f51bd 1207 return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
ebc2ec48 1208}
1209
1210static inline void *tx_agg_align(void *data)
1211{
8e1f51bd 1212 return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
ebc2ec48 1213}
1214
1215static void free_all_mem(struct r8152 *tp)
1216{
1217 int i;
1218
1219 for (i = 0; i < RTL8152_MAX_RX; i++) {
9629e3c0 1220 usb_free_urb(tp->rx_info[i].urb);
1221 tp->rx_info[i].urb = NULL;
ebc2ec48 1222
9629e3c0 1223 kfree(tp->rx_info[i].buffer);
1224 tp->rx_info[i].buffer = NULL;
1225 tp->rx_info[i].head = NULL;
ebc2ec48 1226 }
1227
1228 for (i = 0; i < RTL8152_MAX_TX; i++) {
9629e3c0 1229 usb_free_urb(tp->tx_info[i].urb);
1230 tp->tx_info[i].urb = NULL;
ebc2ec48 1231
9629e3c0 1232 kfree(tp->tx_info[i].buffer);
1233 tp->tx_info[i].buffer = NULL;
1234 tp->tx_info[i].head = NULL;
ebc2ec48 1235 }
40a82917 1236
9629e3c0 1237 usb_free_urb(tp->intr_urb);
1238 tp->intr_urb = NULL;
40a82917 1239
9629e3c0 1240 kfree(tp->intr_buff);
1241 tp->intr_buff = NULL;
ebc2ec48 1242}
1243
1244static int alloc_all_mem(struct r8152 *tp)
1245{
1246 struct net_device *netdev = tp->netdev;
40a82917 1247 struct usb_interface *intf = tp->intf;
1248 struct usb_host_interface *alt = intf->cur_altsetting;
1249 struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
ebc2ec48 1250 struct urb *urb;
1251 int node, i;
1252 u8 *buf;
1253
1254 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1255
1256 spin_lock_init(&tp->rx_lock);
1257 spin_lock_init(&tp->tx_lock);
ebc2ec48 1258 INIT_LIST_HEAD(&tp->tx_free);
1259 skb_queue_head_init(&tp->tx_queue);
1260
1261 for (i = 0; i < RTL8152_MAX_RX; i++) {
52aec126 1262 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
ebc2ec48 1263 if (!buf)
1264 goto err1;
1265
1266 if (buf != rx_agg_align(buf)) {
1267 kfree(buf);
52aec126 1268 buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL,
8e1f51bd 1269 node);
ebc2ec48 1270 if (!buf)
1271 goto err1;
1272 }
1273
1274 urb = usb_alloc_urb(0, GFP_KERNEL);
1275 if (!urb) {
1276 kfree(buf);
1277 goto err1;
1278 }
1279
1280 INIT_LIST_HEAD(&tp->rx_info[i].list);
1281 tp->rx_info[i].context = tp;
1282 tp->rx_info[i].urb = urb;
1283 tp->rx_info[i].buffer = buf;
1284 tp->rx_info[i].head = rx_agg_align(buf);
1285 }
1286
1287 for (i = 0; i < RTL8152_MAX_TX; i++) {
52aec126 1288 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
ebc2ec48 1289 if (!buf)
1290 goto err1;
1291
1292 if (buf != tx_agg_align(buf)) {
1293 kfree(buf);
52aec126 1294 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
8e1f51bd 1295 node);
ebc2ec48 1296 if (!buf)
1297 goto err1;
1298 }
1299
1300 urb = usb_alloc_urb(0, GFP_KERNEL);
1301 if (!urb) {
1302 kfree(buf);
1303 goto err1;
1304 }
1305
1306 INIT_LIST_HEAD(&tp->tx_info[i].list);
1307 tp->tx_info[i].context = tp;
1308 tp->tx_info[i].urb = urb;
1309 tp->tx_info[i].buffer = buf;
1310 tp->tx_info[i].head = tx_agg_align(buf);
1311
1312 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1313 }
1314
40a82917 1315 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1316 if (!tp->intr_urb)
1317 goto err1;
1318
1319 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1320 if (!tp->intr_buff)
1321 goto err1;
1322
1323 tp->intr_interval = (int)ep_intr->desc.bInterval;
1324 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
b209af99 1325 tp->intr_buff, INTBUFSIZE, intr_callback,
1326 tp, tp->intr_interval);
40a82917 1327
ebc2ec48 1328 return 0;
1329
1330err1:
1331 free_all_mem(tp);
1332 return -ENOMEM;
1333}
1334
0de98f6c 1335static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1336{
1337 struct tx_agg *agg = NULL;
1338 unsigned long flags;
1339
21949ab7 1340 if (list_empty(&tp->tx_free))
1341 return NULL;
1342
0de98f6c 1343 spin_lock_irqsave(&tp->tx_lock, flags);
1344 if (!list_empty(&tp->tx_free)) {
1345 struct list_head *cursor;
1346
1347 cursor = tp->tx_free.next;
1348 list_del_init(cursor);
1349 agg = list_entry(cursor, struct tx_agg, list);
1350 }
1351 spin_unlock_irqrestore(&tp->tx_lock, flags);
1352
1353 return agg;
1354}
1355
60c89071 1356static inline __be16 get_protocol(struct sk_buff *skb)
5bd23881 1357{
60c89071 1358 __be16 protocol;
5bd23881 1359
60c89071 1360 if (skb->protocol == htons(ETH_P_8021Q))
1361 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
1362 else
1363 protocol = skb->protocol;
5bd23881 1364
60c89071 1365 return protocol;
1366}
5bd23881 1367
b209af99 1368/* r8152_csum_workaround()
6128d1bb 1369 * The hw limites the value the transport offset. When the offset is out of the
1370 * range, calculate the checksum by sw.
1371 */
1372static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1373 struct sk_buff_head *list)
1374{
1375 if (skb_shinfo(skb)->gso_size) {
1376 netdev_features_t features = tp->netdev->features;
1377 struct sk_buff_head seg_list;
1378 struct sk_buff *segs, *nskb;
1379
a91d45f1 1380 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6128d1bb 1381 segs = skb_gso_segment(skb, features);
1382 if (IS_ERR(segs) || !segs)
1383 goto drop;
1384
1385 __skb_queue_head_init(&seg_list);
1386
1387 do {
1388 nskb = segs;
1389 segs = segs->next;
1390 nskb->next = NULL;
1391 __skb_queue_tail(&seg_list, nskb);
1392 } while (segs);
1393
1394 skb_queue_splice(&seg_list, list);
1395 dev_kfree_skb(skb);
1396 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1397 if (skb_checksum_help(skb) < 0)
1398 goto drop;
1399
1400 __skb_queue_head(list, skb);
1401 } else {
1402 struct net_device_stats *stats;
1403
1404drop:
1405 stats = &tp->netdev->stats;
1406 stats->tx_dropped++;
1407 dev_kfree_skb(skb);
1408 }
1409}
1410
b209af99 1411/* msdn_giant_send_check()
6128d1bb 1412 * According to the document of microsoft, the TCP Pseudo Header excludes the
1413 * packet length for IPv6 TCP large packets.
1414 */
1415static int msdn_giant_send_check(struct sk_buff *skb)
1416{
1417 const struct ipv6hdr *ipv6h;
1418 struct tcphdr *th;
fcb308d5 1419 int ret;
1420
1421 ret = skb_cow_head(skb, 0);
1422 if (ret)
1423 return ret;
6128d1bb 1424
1425 ipv6h = ipv6_hdr(skb);
1426 th = tcp_hdr(skb);
1427
1428 th->check = 0;
1429 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
1430
fcb308d5 1431 return ret;
6128d1bb 1432}
1433
c5554298 1434static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1435{
1436 if (vlan_tx_tag_present(skb)) {
1437 u32 opts2;
1438
1439 opts2 = TX_VLAN_TAG | swab16(vlan_tx_tag_get(skb));
1440 desc->opts2 |= cpu_to_le32(opts2);
1441 }
1442}
1443
1444static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1445{
1446 u32 opts2 = le32_to_cpu(desc->opts2);
1447
1448 if (opts2 & RX_VLAN_TAG)
1449 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1450 swab16(opts2 & 0xffff));
1451}
1452
60c89071 1453static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1454 struct sk_buff *skb, u32 len, u32 transport_offset)
1455{
1456 u32 mss = skb_shinfo(skb)->gso_size;
1457 u32 opts1, opts2 = 0;
1458 int ret = TX_CSUM_SUCCESS;
1459
1460 WARN_ON_ONCE(len > TX_LEN_MAX);
1461
1462 opts1 = len | TX_FS | TX_LS;
1463
1464 if (mss) {
6128d1bb 1465 if (transport_offset > GTTCPHO_MAX) {
1466 netif_warn(tp, tx_err, tp->netdev,
1467 "Invalid transport offset 0x%x for TSO\n",
1468 transport_offset);
1469 ret = TX_CSUM_TSO;
1470 goto unavailable;
1471 }
1472
60c89071 1473 switch (get_protocol(skb)) {
1474 case htons(ETH_P_IP):
1475 opts1 |= GTSENDV4;
1476 break;
1477
6128d1bb 1478 case htons(ETH_P_IPV6):
fcb308d5 1479 if (msdn_giant_send_check(skb)) {
1480 ret = TX_CSUM_TSO;
1481 goto unavailable;
1482 }
6128d1bb 1483 opts1 |= GTSENDV6;
6128d1bb 1484 break;
1485
60c89071 1486 default:
1487 WARN_ON_ONCE(1);
1488 break;
1489 }
1490
1491 opts1 |= transport_offset << GTTCPHO_SHIFT;
1492 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
1493 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1494 u8 ip_protocol;
5bd23881 1495
6128d1bb 1496 if (transport_offset > TCPHO_MAX) {
1497 netif_warn(tp, tx_err, tp->netdev,
1498 "Invalid transport offset 0x%x\n",
1499 transport_offset);
1500 ret = TX_CSUM_NONE;
1501 goto unavailable;
1502 }
1503
60c89071 1504 switch (get_protocol(skb)) {
5bd23881 1505 case htons(ETH_P_IP):
1506 opts2 |= IPV4_CS;
1507 ip_protocol = ip_hdr(skb)->protocol;
1508 break;
1509
1510 case htons(ETH_P_IPV6):
1511 opts2 |= IPV6_CS;
1512 ip_protocol = ipv6_hdr(skb)->nexthdr;
1513 break;
1514
1515 default:
1516 ip_protocol = IPPROTO_RAW;
1517 break;
1518 }
1519
60c89071 1520 if (ip_protocol == IPPROTO_TCP)
5bd23881 1521 opts2 |= TCP_CS;
60c89071 1522 else if (ip_protocol == IPPROTO_UDP)
5bd23881 1523 opts2 |= UDP_CS;
60c89071 1524 else
5bd23881 1525 WARN_ON_ONCE(1);
5bd23881 1526
60c89071 1527 opts2 |= transport_offset << TCPHO_SHIFT;
5bd23881 1528 }
60c89071 1529
1530 desc->opts2 = cpu_to_le32(opts2);
1531 desc->opts1 = cpu_to_le32(opts1);
1532
6128d1bb 1533unavailable:
60c89071 1534 return ret;
5bd23881 1535}
1536
b1379d9a 1537static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
1538{
d84130a1 1539 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
9a4be1bd 1540 int remain, ret;
b1379d9a 1541 u8 *tx_data;
1542
d84130a1 1543 __skb_queue_head_init(&skb_head);
0c3121fc 1544 spin_lock(&tx_queue->lock);
d84130a1 1545 skb_queue_splice_init(tx_queue, &skb_head);
0c3121fc 1546 spin_unlock(&tx_queue->lock);
d84130a1 1547
b1379d9a 1548 tx_data = agg->head;
b209af99 1549 agg->skb_num = 0;
1550 agg->skb_len = 0;
52aec126 1551 remain = agg_buf_sz;
b1379d9a 1552
7937f9e5 1553 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
b1379d9a 1554 struct tx_desc *tx_desc;
1555 struct sk_buff *skb;
1556 unsigned int len;
60c89071 1557 u32 offset;
b1379d9a 1558
d84130a1 1559 skb = __skb_dequeue(&skb_head);
b1379d9a 1560 if (!skb)
1561 break;
1562
60c89071 1563 len = skb->len + sizeof(*tx_desc);
1564
1565 if (len > remain) {
d84130a1 1566 __skb_queue_head(&skb_head, skb);
b1379d9a 1567 break;
1568 }
1569
7937f9e5 1570 tx_data = tx_agg_align(tx_data);
b1379d9a 1571 tx_desc = (struct tx_desc *)tx_data;
60c89071 1572
1573 offset = (u32)skb_transport_offset(skb);
1574
6128d1bb 1575 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
1576 r8152_csum_workaround(tp, skb, &skb_head);
1577 continue;
1578 }
60c89071 1579
c5554298 1580 rtl_tx_vlan_tag(tx_desc, skb);
1581
b1379d9a 1582 tx_data += sizeof(*tx_desc);
1583
60c89071 1584 len = skb->len;
1585 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
1586 struct net_device_stats *stats = &tp->netdev->stats;
1587
1588 stats->tx_dropped++;
1589 dev_kfree_skb_any(skb);
1590 tx_data -= sizeof(*tx_desc);
1591 continue;
1592 }
1593
1594 tx_data += len;
b1379d9a 1595 agg->skb_len += len;
60c89071 1596 agg->skb_num++;
1597
b1379d9a 1598 dev_kfree_skb_any(skb);
1599
52aec126 1600 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
b1379d9a 1601 }
1602
d84130a1 1603 if (!skb_queue_empty(&skb_head)) {
0c3121fc 1604 spin_lock(&tx_queue->lock);
d84130a1 1605 skb_queue_splice(&skb_head, tx_queue);
0c3121fc 1606 spin_unlock(&tx_queue->lock);
d84130a1 1607 }
1608
0c3121fc 1609 netif_tx_lock(tp->netdev);
dd1b119c 1610
1611 if (netif_queue_stopped(tp->netdev) &&
1612 skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
1613 netif_wake_queue(tp->netdev);
1614
0c3121fc 1615 netif_tx_unlock(tp->netdev);
9a4be1bd 1616
0c3121fc 1617 ret = usb_autopm_get_interface_async(tp->intf);
9a4be1bd 1618 if (ret < 0)
1619 goto out_tx_fill;
dd1b119c 1620
b1379d9a 1621 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1622 agg->head, (int)(tx_data - (u8 *)agg->head),
1623 (usb_complete_t)write_bulk_callback, agg);
1624
0c3121fc 1625 ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
9a4be1bd 1626 if (ret < 0)
0c3121fc 1627 usb_autopm_put_interface_async(tp->intf);
9a4be1bd 1628
1629out_tx_fill:
1630 return ret;
b1379d9a 1631}
1632
565cab0a 1633static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
1634{
1635 u8 checksum = CHECKSUM_NONE;
1636 u32 opts2, opts3;
1637
1638 if (tp->version == RTL_VER_01)
1639 goto return_result;
1640
1641 opts2 = le32_to_cpu(rx_desc->opts2);
1642 opts3 = le32_to_cpu(rx_desc->opts3);
1643
1644 if (opts2 & RD_IPV4_CS) {
1645 if (opts3 & IPF)
1646 checksum = CHECKSUM_NONE;
1647 else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF))
1648 checksum = CHECKSUM_NONE;
1649 else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF))
1650 checksum = CHECKSUM_NONE;
1651 else
1652 checksum = CHECKSUM_UNNECESSARY;
6128d1bb 1653 } else if (RD_IPV6_CS) {
1654 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1655 checksum = CHECKSUM_UNNECESSARY;
1656 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1657 checksum = CHECKSUM_UNNECESSARY;
565cab0a 1658 }
1659
1660return_result:
1661 return checksum;
1662}
1663
ebc2ec48 1664static void rx_bottom(struct r8152 *tp)
1665{
a5a4f468 1666 unsigned long flags;
d84130a1 1667 struct list_head *cursor, *next, rx_queue;
ebc2ec48 1668
d84130a1 1669 if (list_empty(&tp->rx_done))
1670 return;
1671
1672 INIT_LIST_HEAD(&rx_queue);
a5a4f468 1673 spin_lock_irqsave(&tp->rx_lock, flags);
d84130a1 1674 list_splice_init(&tp->rx_done, &rx_queue);
1675 spin_unlock_irqrestore(&tp->rx_lock, flags);
1676
1677 list_for_each_safe(cursor, next, &rx_queue) {
43a4478d 1678 struct rx_desc *rx_desc;
1679 struct rx_agg *agg;
43a4478d 1680 int len_used = 0;
1681 struct urb *urb;
1682 u8 *rx_data;
1683 int ret;
1684
ebc2ec48 1685 list_del_init(cursor);
ebc2ec48 1686
1687 agg = list_entry(cursor, struct rx_agg, list);
1688 urb = agg->urb;
0de98f6c 1689 if (urb->actual_length < ETH_ZLEN)
1690 goto submit;
ebc2ec48 1691
ebc2ec48 1692 rx_desc = agg->head;
1693 rx_data = agg->head;
7937f9e5 1694 len_used += sizeof(struct rx_desc);
ebc2ec48 1695
7937f9e5 1696 while (urb->actual_length > len_used) {
43a4478d 1697 struct net_device *netdev = tp->netdev;
05e0f1aa 1698 struct net_device_stats *stats = &netdev->stats;
7937f9e5 1699 unsigned int pkt_len;
43a4478d 1700 struct sk_buff *skb;
1701
7937f9e5 1702 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
ebc2ec48 1703 if (pkt_len < ETH_ZLEN)
1704 break;
1705
7937f9e5 1706 len_used += pkt_len;
1707 if (urb->actual_length < len_used)
1708 break;
1709
8e1f51bd 1710 pkt_len -= CRC_SIZE;
ebc2ec48 1711 rx_data += sizeof(struct rx_desc);
1712
1713 skb = netdev_alloc_skb_ip_align(netdev, pkt_len);
1714 if (!skb) {
1715 stats->rx_dropped++;
5e2f7485 1716 goto find_next_rx;
ebc2ec48 1717 }
565cab0a 1718
1719 skb->ip_summed = r8152_rx_csum(tp, rx_desc);
ebc2ec48 1720 memcpy(skb->data, rx_data, pkt_len);
1721 skb_put(skb, pkt_len);
1722 skb->protocol = eth_type_trans(skb, netdev);
c5554298 1723 rtl_rx_vlan_tag(rx_desc, skb);
9d9aafa1 1724 netif_receive_skb(skb);
ebc2ec48 1725 stats->rx_packets++;
1726 stats->rx_bytes += pkt_len;
1727
5e2f7485 1728find_next_rx:
8e1f51bd 1729 rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE);
ebc2ec48 1730 rx_desc = (struct rx_desc *)rx_data;
ebc2ec48 1731 len_used = (int)(rx_data - (u8 *)agg->head);
7937f9e5 1732 len_used += sizeof(struct rx_desc);
ebc2ec48 1733 }
1734
0de98f6c 1735submit:
ebc2ec48 1736 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
ebc2ec48 1737 if (ret && ret != -ENODEV) {
d84130a1 1738 spin_lock_irqsave(&tp->rx_lock, flags);
1739 list_add_tail(&agg->list, &tp->rx_done);
1740 spin_unlock_irqrestore(&tp->rx_lock, flags);
ebc2ec48 1741 tasklet_schedule(&tp->tl);
1742 }
1743 }
ebc2ec48 1744}
1745
1746static void tx_bottom(struct r8152 *tp)
1747{
ebc2ec48 1748 int res;
1749
b1379d9a 1750 do {
1751 struct tx_agg *agg;
ebc2ec48 1752
b1379d9a 1753 if (skb_queue_empty(&tp->tx_queue))
ebc2ec48 1754 break;
1755
b1379d9a 1756 agg = r8152_get_tx_agg(tp);
1757 if (!agg)
ebc2ec48 1758 break;
ebc2ec48 1759
b1379d9a 1760 res = r8152_tx_agg_fill(tp, agg);
1761 if (res) {
05e0f1aa 1762 struct net_device *netdev = tp->netdev;
ebc2ec48 1763
b1379d9a 1764 if (res == -ENODEV) {
67610496 1765 set_bit(RTL8152_UNPLUG, &tp->flags);
b1379d9a 1766 netif_device_detach(netdev);
1767 } else {
05e0f1aa 1768 struct net_device_stats *stats = &netdev->stats;
1769 unsigned long flags;
1770
b1379d9a 1771 netif_warn(tp, tx_err, netdev,
1772 "failed tx_urb %d\n", res);
1773 stats->tx_dropped += agg->skb_num;
db8515ef 1774
b1379d9a 1775 spin_lock_irqsave(&tp->tx_lock, flags);
1776 list_add_tail(&agg->list, &tp->tx_free);
1777 spin_unlock_irqrestore(&tp->tx_lock, flags);
1778 }
ebc2ec48 1779 }
b1379d9a 1780 } while (res == 0);
ebc2ec48 1781}
1782
1783static void bottom_half(unsigned long data)
ac718b69 1784{
1785 struct r8152 *tp;
ac718b69 1786
ebc2ec48 1787 tp = (struct r8152 *)data;
1788
1789 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1790 return;
1791
1792 if (!test_bit(WORK_ENABLE, &tp->flags))
ac718b69 1793 return;
ebc2ec48 1794
7559fb2f 1795 /* When link down, the driver would cancel all bulks. */
1796 /* This avoid the re-submitting bulk */
ebc2ec48 1797 if (!netif_carrier_ok(tp->netdev))
ac718b69 1798 return;
ebc2ec48 1799
1800 rx_bottom(tp);
0c3121fc 1801 tx_bottom(tp);
ebc2ec48 1802}
1803
1804static
1805int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
1806{
1807 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
52aec126 1808 agg->head, agg_buf_sz,
b209af99 1809 (usb_complete_t)read_bulk_callback, agg);
ebc2ec48 1810
1811 return usb_submit_urb(agg->urb, mem_flags);
ac718b69 1812}
1813
00a5e360 1814static void rtl_drop_queued_tx(struct r8152 *tp)
1815{
1816 struct net_device_stats *stats = &tp->netdev->stats;
d84130a1 1817 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
00a5e360 1818 struct sk_buff *skb;
1819
d84130a1 1820 if (skb_queue_empty(tx_queue))
1821 return;
1822
1823 __skb_queue_head_init(&skb_head);
2685d410 1824 spin_lock_bh(&tx_queue->lock);
d84130a1 1825 skb_queue_splice_init(tx_queue, &skb_head);
2685d410 1826 spin_unlock_bh(&tx_queue->lock);
d84130a1 1827
1828 while ((skb = __skb_dequeue(&skb_head))) {
00a5e360 1829 dev_kfree_skb(skb);
1830 stats->tx_dropped++;
1831 }
1832}
1833
ac718b69 1834static void rtl8152_tx_timeout(struct net_device *netdev)
1835{
1836 struct r8152 *tp = netdev_priv(netdev);
ebc2ec48 1837 int i;
1838
4a8deae2 1839 netif_warn(tp, tx_err, netdev, "Tx timeout\n");
ebc2ec48 1840 for (i = 0; i < RTL8152_MAX_TX; i++)
1841 usb_unlink_urb(tp->tx_info[i].urb);
ac718b69 1842}
1843
1844static void rtl8152_set_rx_mode(struct net_device *netdev)
1845{
1846 struct r8152 *tp = netdev_priv(netdev);
1847
40a82917 1848 if (tp->speed & LINK_STATUS) {
ac718b69 1849 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
40a82917 1850 schedule_delayed_work(&tp->schedule, 0);
1851 }
ac718b69 1852}
1853
1854static void _rtl8152_set_rx_mode(struct net_device *netdev)
1855{
1856 struct r8152 *tp = netdev_priv(netdev);
31787f53 1857 u32 mc_filter[2]; /* Multicast hash filter */
1858 __le32 tmp[2];
ac718b69 1859 u32 ocp_data;
1860
ac718b69 1861 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
1862 netif_stop_queue(netdev);
1863 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1864 ocp_data &= ~RCR_ACPT_ALL;
1865 ocp_data |= RCR_AB | RCR_APM;
1866
1867 if (netdev->flags & IFF_PROMISC) {
1868 /* Unconditionally log net taps. */
1869 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
1870 ocp_data |= RCR_AM | RCR_AAP;
b209af99 1871 mc_filter[1] = 0xffffffff;
1872 mc_filter[0] = 0xffffffff;
ac718b69 1873 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
1874 (netdev->flags & IFF_ALLMULTI)) {
1875 /* Too many to filter perfectly -- accept all multicasts. */
1876 ocp_data |= RCR_AM;
b209af99 1877 mc_filter[1] = 0xffffffff;
1878 mc_filter[0] = 0xffffffff;
ac718b69 1879 } else {
1880 struct netdev_hw_addr *ha;
1881
b209af99 1882 mc_filter[1] = 0;
1883 mc_filter[0] = 0;
ac718b69 1884 netdev_for_each_mc_addr(ha, netdev) {
1885 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
b209af99 1886
ac718b69 1887 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1888 ocp_data |= RCR_AM;
1889 }
1890 }
1891
31787f53 1892 tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
1893 tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
ac718b69 1894
31787f53 1895 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
ac718b69 1896 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1897 netif_wake_queue(netdev);
ac718b69 1898}
1899
1900static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
b209af99 1901 struct net_device *netdev)
ac718b69 1902{
1903 struct r8152 *tp = netdev_priv(netdev);
ac718b69 1904
ebc2ec48 1905 skb_tx_timestamp(skb);
ac718b69 1906
61598788 1907 skb_queue_tail(&tp->tx_queue, skb);
ebc2ec48 1908
0c3121fc 1909 if (!list_empty(&tp->tx_free)) {
1910 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
1911 set_bit(SCHEDULE_TASKLET, &tp->flags);
1912 schedule_delayed_work(&tp->schedule, 0);
1913 } else {
1914 usb_mark_last_busy(tp->udev);
1915 tasklet_schedule(&tp->tl);
1916 }
b209af99 1917 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
dd1b119c 1918 netif_stop_queue(netdev);
b209af99 1919 }
dd1b119c 1920
ac718b69 1921 return NETDEV_TX_OK;
1922}
1923
1924static void r8152b_reset_packet_filter(struct r8152 *tp)
1925{
1926 u32 ocp_data;
1927
1928 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
1929 ocp_data &= ~FMC_FCR_MCU_EN;
1930 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1931 ocp_data |= FMC_FCR_MCU_EN;
1932 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1933}
1934
1935static void rtl8152_nic_reset(struct r8152 *tp)
1936{
1937 int i;
1938
1939 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
1940
1941 for (i = 0; i < 1000; i++) {
1942 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
1943 break;
b209af99 1944 usleep_range(100, 400);
ac718b69 1945 }
1946}
1947
dd1b119c 1948static void set_tx_qlen(struct r8152 *tp)
1949{
1950 struct net_device *netdev = tp->netdev;
1951
52aec126 1952 tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN +
1953 sizeof(struct tx_desc));
dd1b119c 1954}
1955
ac718b69 1956static inline u8 rtl8152_get_speed(struct r8152 *tp)
1957{
1958 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
1959}
1960
507605a8 1961static void rtl_set_eee_plus(struct r8152 *tp)
ac718b69 1962{
ebc2ec48 1963 u32 ocp_data;
ac718b69 1964 u8 speed;
1965
1966 speed = rtl8152_get_speed(tp);
ebc2ec48 1967 if (speed & _10bps) {
ac718b69 1968 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
ebc2ec48 1969 ocp_data |= EEEP_CR_EEEP_TX;
ac718b69 1970 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
1971 } else {
1972 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
ebc2ec48 1973 ocp_data &= ~EEEP_CR_EEEP_TX;
ac718b69 1974 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
1975 }
507605a8 1976}
1977
00a5e360 1978static void rxdy_gated_en(struct r8152 *tp, bool enable)
1979{
1980 u32 ocp_data;
1981
1982 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
1983 if (enable)
1984 ocp_data |= RXDY_GATED_EN;
1985 else
1986 ocp_data &= ~RXDY_GATED_EN;
1987 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
1988}
1989
445f7f4d 1990static int rtl_start_rx(struct r8152 *tp)
1991{
1992 int i, ret = 0;
1993
1994 INIT_LIST_HEAD(&tp->rx_done);
1995 for (i = 0; i < RTL8152_MAX_RX; i++) {
1996 INIT_LIST_HEAD(&tp->rx_info[i].list);
1997 ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
1998 if (ret)
1999 break;
2000 }
2001
2002 return ret;
2003}
2004
2005static int rtl_stop_rx(struct r8152 *tp)
2006{
2007 int i;
2008
2009 for (i = 0; i < RTL8152_MAX_RX; i++)
2010 usb_kill_urb(tp->rx_info[i].urb);
2011
2012 return 0;
2013}
2014
507605a8 2015static int rtl_enable(struct r8152 *tp)
2016{
2017 u32 ocp_data;
ac718b69 2018
2019 r8152b_reset_packet_filter(tp);
2020
2021 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2022 ocp_data |= CR_RE | CR_TE;
2023 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2024
00a5e360 2025 rxdy_gated_en(tp, false);
ac718b69 2026
445f7f4d 2027 return rtl_start_rx(tp);
ac718b69 2028}
2029
507605a8 2030static int rtl8152_enable(struct r8152 *tp)
2031{
6871438c 2032 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2033 return -ENODEV;
2034
507605a8 2035 set_tx_qlen(tp);
2036 rtl_set_eee_plus(tp);
2037
2038 return rtl_enable(tp);
2039}
2040
43779f8d 2041static void r8153_set_rx_agg(struct r8152 *tp)
2042{
2043 u8 speed;
2044
2045 speed = rtl8152_get_speed(tp);
2046 if (speed & _1000bps) {
2047 if (tp->udev->speed == USB_SPEED_SUPER) {
2048 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
2049 RX_THR_SUPPER);
2050 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
2051 EARLY_AGG_SUPPER);
2052 } else {
2053 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
2054 RX_THR_HIGH);
2055 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
2056 EARLY_AGG_HIGH);
2057 }
2058 } else {
2059 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_SLOW);
2060 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
2061 EARLY_AGG_SLOW);
2062 }
2063}
2064
2065static int rtl8153_enable(struct r8152 *tp)
2066{
6871438c 2067 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2068 return -ENODEV;
2069
43779f8d 2070 set_tx_qlen(tp);
2071 rtl_set_eee_plus(tp);
2072 r8153_set_rx_agg(tp);
2073
2074 return rtl_enable(tp);
2075}
2076
d70b1137 2077static void rtl_disable(struct r8152 *tp)
ac718b69 2078{
ebc2ec48 2079 u32 ocp_data;
2080 int i;
ac718b69 2081
6871438c 2082 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2083 rtl_drop_queued_tx(tp);
2084 return;
2085 }
2086
ac718b69 2087 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2088 ocp_data &= ~RCR_ACPT_ALL;
2089 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2090
00a5e360 2091 rtl_drop_queued_tx(tp);
ebc2ec48 2092
2093 for (i = 0; i < RTL8152_MAX_TX; i++)
2094 usb_kill_urb(tp->tx_info[i].urb);
ac718b69 2095
00a5e360 2096 rxdy_gated_en(tp, true);
ac718b69 2097
2098 for (i = 0; i < 1000; i++) {
2099 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2100 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2101 break;
8ddfa077 2102 usleep_range(1000, 2000);
ac718b69 2103 }
2104
2105 for (i = 0; i < 1000; i++) {
2106 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2107 break;
8ddfa077 2108 usleep_range(1000, 2000);
ac718b69 2109 }
2110
445f7f4d 2111 rtl_stop_rx(tp);
ac718b69 2112
2113 rtl8152_nic_reset(tp);
2114}
2115
00a5e360 2116static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2117{
2118 u32 ocp_data;
2119
2120 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2121 if (enable)
2122 ocp_data |= POWER_CUT;
2123 else
2124 ocp_data &= ~POWER_CUT;
2125 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2126
2127 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2128 ocp_data &= ~RESUME_INDICATE;
2129 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
00a5e360 2130}
2131
c5554298 2132static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2133{
2134 u32 ocp_data;
2135
2136 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2137 if (enable)
2138 ocp_data |= CPCR_RX_VLAN;
2139 else
2140 ocp_data &= ~CPCR_RX_VLAN;
2141 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2142}
2143
2144static int rtl8152_set_features(struct net_device *dev,
2145 netdev_features_t features)
2146{
2147 netdev_features_t changed = features ^ dev->features;
2148 struct r8152 *tp = netdev_priv(dev);
405f8a0e 2149 int ret;
2150
2151 ret = usb_autopm_get_interface(tp->intf);
2152 if (ret < 0)
2153 goto out;
c5554298 2154
b5403273 2155 mutex_lock(&tp->control);
2156
c5554298 2157 if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2158 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2159 rtl_rx_vlan_en(tp, true);
2160 else
2161 rtl_rx_vlan_en(tp, false);
2162 }
2163
b5403273 2164 mutex_unlock(&tp->control);
2165
405f8a0e 2166 usb_autopm_put_interface(tp->intf);
2167
2168out:
2169 return ret;
c5554298 2170}
2171
21ff2e89 2172#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2173
2174static u32 __rtl_get_wol(struct r8152 *tp)
2175{
2176 u32 ocp_data;
2177 u32 wolopts = 0;
2178
2179 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2180 if (!(ocp_data & LAN_WAKE_EN))
2181 return 0;
2182
2183 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2184 if (ocp_data & LINK_ON_WAKE_EN)
2185 wolopts |= WAKE_PHY;
2186
2187 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2188 if (ocp_data & UWF_EN)
2189 wolopts |= WAKE_UCAST;
2190 if (ocp_data & BWF_EN)
2191 wolopts |= WAKE_BCAST;
2192 if (ocp_data & MWF_EN)
2193 wolopts |= WAKE_MCAST;
2194
2195 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2196 if (ocp_data & MAGIC_EN)
2197 wolopts |= WAKE_MAGIC;
2198
2199 return wolopts;
2200}
2201
2202static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
2203{
2204 u32 ocp_data;
2205
2206 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2207
2208 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2209 ocp_data &= ~LINK_ON_WAKE_EN;
2210 if (wolopts & WAKE_PHY)
2211 ocp_data |= LINK_ON_WAKE_EN;
2212 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2213
2214 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2215 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN);
2216 if (wolopts & WAKE_UCAST)
2217 ocp_data |= UWF_EN;
2218 if (wolopts & WAKE_BCAST)
2219 ocp_data |= BWF_EN;
2220 if (wolopts & WAKE_MCAST)
2221 ocp_data |= MWF_EN;
2222 if (wolopts & WAKE_ANY)
2223 ocp_data |= LAN_WAKE_EN;
2224 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
2225
2226 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2227
2228 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2229 ocp_data &= ~MAGIC_EN;
2230 if (wolopts & WAKE_MAGIC)
2231 ocp_data |= MAGIC_EN;
2232 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
2233
2234 if (wolopts & WAKE_ANY)
2235 device_set_wakeup_enable(&tp->udev->dev, true);
2236 else
2237 device_set_wakeup_enable(&tp->udev->dev, false);
2238}
2239
9a4be1bd 2240static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
2241{
2242 if (enable) {
2243 u32 ocp_data;
2244
2245 __rtl_set_wol(tp, WAKE_ANY);
2246
2247 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2248
2249 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2250 ocp_data |= LINK_OFF_WAKE_EN;
2251 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2252
2253 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2254 } else {
2255 __rtl_set_wol(tp, tp->saved_wolopts);
2256 }
2257}
2258
aa66a5f1 2259static void rtl_phy_reset(struct r8152 *tp)
2260{
2261 u16 data;
2262 int i;
2263
2264 clear_bit(PHY_RESET, &tp->flags);
2265
2266 data = r8152_mdio_read(tp, MII_BMCR);
2267
2268 /* don't reset again before the previous one complete */
2269 if (data & BMCR_RESET)
2270 return;
2271
2272 data |= BMCR_RESET;
2273 r8152_mdio_write(tp, MII_BMCR, data);
2274
2275 for (i = 0; i < 50; i++) {
2276 msleep(20);
2277 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
2278 break;
2279 }
2280}
2281
4349968a 2282static void r8153_teredo_off(struct r8152 *tp)
2283{
2284 u32 ocp_data;
2285
2286 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2287 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN);
2288 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2289
2290 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
2291 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
2292 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
2293}
2294
2295static void r8152b_disable_aldps(struct r8152 *tp)
2296{
2297 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
2298 msleep(20);
2299}
2300
2301static inline void r8152b_enable_aldps(struct r8152 *tp)
2302{
2303 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
2304 LINKENA | DIS_SDSAVE);
2305}
2306
d70b1137 2307static void rtl8152_disable(struct r8152 *tp)
2308{
2309 r8152b_disable_aldps(tp);
2310 rtl_disable(tp);
2311 r8152b_enable_aldps(tp);
2312}
2313
4349968a 2314static void r8152b_hw_phy_cfg(struct r8152 *tp)
2315{
f0cbe0ac 2316 u16 data;
2317
2318 data = r8152_mdio_read(tp, MII_BMCR);
2319 if (data & BMCR_PDOWN) {
2320 data &= ~BMCR_PDOWN;
2321 r8152_mdio_write(tp, MII_BMCR, data);
2322 }
2323
aa66a5f1 2324 set_bit(PHY_RESET, &tp->flags);
4349968a 2325}
2326
ac718b69 2327static void r8152b_exit_oob(struct r8152 *tp)
2328{
db8515ef 2329 u32 ocp_data;
2330 int i;
ac718b69 2331
2332 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2333 ocp_data &= ~RCR_ACPT_ALL;
2334 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2335
00a5e360 2336 rxdy_gated_en(tp, true);
da9bd117 2337 r8153_teredo_off(tp);
7e9da481 2338 r8152b_hw_phy_cfg(tp);
ac718b69 2339
2340 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2341 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
2342
2343 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2344 ocp_data &= ~NOW_IS_OOB;
2345 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2346
2347 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2348 ocp_data &= ~MCU_BORW_EN;
2349 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2350
2351 for (i = 0; i < 1000; i++) {
2352 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2353 if (ocp_data & LINK_LIST_READY)
2354 break;
8ddfa077 2355 usleep_range(1000, 2000);
ac718b69 2356 }
2357
2358 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2359 ocp_data |= RE_INIT_LL;
2360 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2361
2362 for (i = 0; i < 1000; i++) {
2363 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2364 if (ocp_data & LINK_LIST_READY)
2365 break;
8ddfa077 2366 usleep_range(1000, 2000);
ac718b69 2367 }
2368
2369 rtl8152_nic_reset(tp);
2370
2371 /* rx share fifo credit full threshold */
2372 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2373
a3cc465d 2374 if (tp->udev->speed == USB_SPEED_FULL ||
2375 tp->udev->speed == USB_SPEED_LOW) {
ac718b69 2376 /* rx share fifo credit near full threshold */
2377 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2378 RXFIFO_THR2_FULL);
2379 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2380 RXFIFO_THR3_FULL);
2381 } else {
2382 /* rx share fifo credit near full threshold */
2383 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2384 RXFIFO_THR2_HIGH);
2385 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2386 RXFIFO_THR3_HIGH);
2387 }
2388
2389 /* TX share fifo free credit full threshold */
2390 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
2391
2392 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
8e1f51bd 2393 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
ac718b69 2394 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
2395 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
2396
c5554298 2397 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
ac718b69 2398
2399 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2400
2401 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2402 ocp_data |= TCR0_AUTO_FIFO;
2403 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2404}
2405
2406static void r8152b_enter_oob(struct r8152 *tp)
2407{
45f4a19f 2408 u32 ocp_data;
2409 int i;
ac718b69 2410
2411 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2412 ocp_data &= ~NOW_IS_OOB;
2413 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2414
2415 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
2416 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
2417 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
2418
d70b1137 2419 rtl_disable(tp);
ac718b69 2420
2421 for (i = 0; i < 1000; i++) {
2422 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2423 if (ocp_data & LINK_LIST_READY)
2424 break;
8ddfa077 2425 usleep_range(1000, 2000);
ac718b69 2426 }
2427
2428 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2429 ocp_data |= RE_INIT_LL;
2430 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2431
2432 for (i = 0; i < 1000; i++) {
2433 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2434 if (ocp_data & LINK_LIST_READY)
2435 break;
8ddfa077 2436 usleep_range(1000, 2000);
ac718b69 2437 }
2438
2439 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2440
c5554298 2441 rtl_rx_vlan_en(tp, true);
ac718b69 2442
2443 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2444 ocp_data |= ALDPS_PROXY_MODE;
2445 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2446
2447 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2448 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2449 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2450
00a5e360 2451 rxdy_gated_en(tp, false);
ac718b69 2452
2453 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2454 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2455 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2456}
2457
43779f8d 2458static void r8153_hw_phy_cfg(struct r8152 *tp)
2459{
2460 u32 ocp_data;
2461 u16 data;
2462
2463 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
f0cbe0ac 2464 data = r8152_mdio_read(tp, MII_BMCR);
2465 if (data & BMCR_PDOWN) {
2466 data &= ~BMCR_PDOWN;
2467 r8152_mdio_write(tp, MII_BMCR, data);
2468 }
43779f8d 2469
2470 if (tp->version == RTL_VER_03) {
2471 data = ocp_reg_read(tp, OCP_EEE_CFG);
2472 data &= ~CTAP_SHORT_EN;
2473 ocp_reg_write(tp, OCP_EEE_CFG, data);
2474 }
2475
2476 data = ocp_reg_read(tp, OCP_POWER_CFG);
2477 data |= EEE_CLKDIV_EN;
2478 ocp_reg_write(tp, OCP_POWER_CFG, data);
2479
2480 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
2481 data |= EN_10M_BGOFF;
2482 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
2483 data = ocp_reg_read(tp, OCP_POWER_CFG);
2484 data |= EN_10M_PLLOFF;
2485 ocp_reg_write(tp, OCP_POWER_CFG, data);
2486 data = sram_read(tp, SRAM_IMPEDANCE);
2487 data &= ~RX_DRIVING_MASK;
2488 sram_write(tp, SRAM_IMPEDANCE, data);
2489
2490 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
2491 ocp_data |= PFM_PWM_SWITCH;
2492 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
2493
2494 data = sram_read(tp, SRAM_LPF_CFG);
2495 data |= LPF_AUTO_TUNE;
2496 sram_write(tp, SRAM_LPF_CFG, data);
2497
2498 data = sram_read(tp, SRAM_10M_AMP1);
2499 data |= GDAC_IB_UPALL;
2500 sram_write(tp, SRAM_10M_AMP1, data);
2501 data = sram_read(tp, SRAM_10M_AMP2);
2502 data |= AMP_DN;
2503 sram_write(tp, SRAM_10M_AMP2, data);
aa66a5f1 2504
2505 set_bit(PHY_RESET, &tp->flags);
43779f8d 2506}
2507
b9702723 2508static void r8153_u1u2en(struct r8152 *tp, bool enable)
43779f8d 2509{
2510 u8 u1u2[8];
2511
2512 if (enable)
2513 memset(u1u2, 0xff, sizeof(u1u2));
2514 else
2515 memset(u1u2, 0x00, sizeof(u1u2));
2516
2517 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
2518}
2519
b9702723 2520static void r8153_u2p3en(struct r8152 *tp, bool enable)
43779f8d 2521{
2522 u32 ocp_data;
2523
2524 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
2525 if (enable)
2526 ocp_data |= U2P3_ENABLE;
2527 else
2528 ocp_data &= ~U2P3_ENABLE;
2529 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
2530}
2531
b9702723 2532static void r8153_power_cut_en(struct r8152 *tp, bool enable)
43779f8d 2533{
2534 u32 ocp_data;
2535
2536 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2537 if (enable)
2538 ocp_data |= PWR_EN | PHASE2_EN;
2539 else
2540 ocp_data &= ~(PWR_EN | PHASE2_EN);
2541 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2542
2543 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2544 ocp_data &= ~PCUT_STATUS;
2545 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2546}
2547
43779f8d 2548static void r8153_first_init(struct r8152 *tp)
2549{
2550 u32 ocp_data;
2551 int i;
2552
00a5e360 2553 rxdy_gated_en(tp, true);
43779f8d 2554 r8153_teredo_off(tp);
2555
2556 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2557 ocp_data &= ~RCR_ACPT_ALL;
2558 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2559
2560 r8153_hw_phy_cfg(tp);
2561
2562 rtl8152_nic_reset(tp);
2563
2564 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2565 ocp_data &= ~NOW_IS_OOB;
2566 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2567
2568 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2569 ocp_data &= ~MCU_BORW_EN;
2570 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2571
2572 for (i = 0; i < 1000; i++) {
2573 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2574 if (ocp_data & LINK_LIST_READY)
2575 break;
8ddfa077 2576 usleep_range(1000, 2000);
43779f8d 2577 }
2578
2579 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2580 ocp_data |= RE_INIT_LL;
2581 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2582
2583 for (i = 0; i < 1000; i++) {
2584 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2585 if (ocp_data & LINK_LIST_READY)
2586 break;
8ddfa077 2587 usleep_range(1000, 2000);
43779f8d 2588 }
2589
c5554298 2590 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
43779f8d 2591
69b4b7a4 2592 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
2593 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
43779f8d 2594
2595 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2596 ocp_data |= TCR0_AUTO_FIFO;
2597 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2598
2599 rtl8152_nic_reset(tp);
2600
2601 /* rx share fifo credit full threshold */
2602 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2603 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
2604 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
2605 /* TX share fifo free credit full threshold */
2606 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
2607
9629e3c0 2608 /* rx aggregation */
43779f8d 2609 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2610 ocp_data &= ~RX_AGG_DISABLE;
2611 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2612}
2613
2614static void r8153_enter_oob(struct r8152 *tp)
2615{
2616 u32 ocp_data;
2617 int i;
2618
2619 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2620 ocp_data &= ~NOW_IS_OOB;
2621 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2622
d70b1137 2623 rtl_disable(tp);
43779f8d 2624
2625 for (i = 0; i < 1000; i++) {
2626 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2627 if (ocp_data & LINK_LIST_READY)
2628 break;
8ddfa077 2629 usleep_range(1000, 2000);
43779f8d 2630 }
2631
2632 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2633 ocp_data |= RE_INIT_LL;
2634 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2635
2636 for (i = 0; i < 1000; i++) {
2637 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2638 if (ocp_data & LINK_LIST_READY)
2639 break;
8ddfa077 2640 usleep_range(1000, 2000);
43779f8d 2641 }
2642
69b4b7a4 2643 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
43779f8d 2644
43779f8d 2645 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2646 ocp_data &= ~TEREDO_WAKE_MASK;
2647 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2648
c5554298 2649 rtl_rx_vlan_en(tp, true);
43779f8d 2650
2651 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2652 ocp_data |= ALDPS_PROXY_MODE;
2653 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2654
2655 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2656 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2657 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2658
00a5e360 2659 rxdy_gated_en(tp, false);
43779f8d 2660
2661 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2662 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2663 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2664}
2665
2666static void r8153_disable_aldps(struct r8152 *tp)
2667{
2668 u16 data;
2669
2670 data = ocp_reg_read(tp, OCP_POWER_CFG);
2671 data &= ~EN_ALDPS;
2672 ocp_reg_write(tp, OCP_POWER_CFG, data);
2673 msleep(20);
2674}
2675
2676static void r8153_enable_aldps(struct r8152 *tp)
2677{
2678 u16 data;
2679
2680 data = ocp_reg_read(tp, OCP_POWER_CFG);
2681 data |= EN_ALDPS;
2682 ocp_reg_write(tp, OCP_POWER_CFG, data);
2683}
2684
d70b1137 2685static void rtl8153_disable(struct r8152 *tp)
2686{
2687 r8153_disable_aldps(tp);
2688 rtl_disable(tp);
2689 r8153_enable_aldps(tp);
2690}
2691
ac718b69 2692static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
2693{
43779f8d 2694 u16 bmcr, anar, gbcr;
ac718b69 2695 int ret = 0;
2696
2697 cancel_delayed_work_sync(&tp->schedule);
2698 anar = r8152_mdio_read(tp, MII_ADVERTISE);
2699 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
2700 ADVERTISE_100HALF | ADVERTISE_100FULL);
43779f8d 2701 if (tp->mii.supports_gmii) {
2702 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
2703 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
2704 } else {
2705 gbcr = 0;
2706 }
ac718b69 2707
2708 if (autoneg == AUTONEG_DISABLE) {
2709 if (speed == SPEED_10) {
2710 bmcr = 0;
2711 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2712 } else if (speed == SPEED_100) {
2713 bmcr = BMCR_SPEED100;
2714 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
43779f8d 2715 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2716 bmcr = BMCR_SPEED1000;
2717 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
ac718b69 2718 } else {
2719 ret = -EINVAL;
2720 goto out;
2721 }
2722
2723 if (duplex == DUPLEX_FULL)
2724 bmcr |= BMCR_FULLDPLX;
2725 } else {
2726 if (speed == SPEED_10) {
2727 if (duplex == DUPLEX_FULL)
2728 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2729 else
2730 anar |= ADVERTISE_10HALF;
2731 } else if (speed == SPEED_100) {
2732 if (duplex == DUPLEX_FULL) {
2733 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2734 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2735 } else {
2736 anar |= ADVERTISE_10HALF;
2737 anar |= ADVERTISE_100HALF;
2738 }
43779f8d 2739 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2740 if (duplex == DUPLEX_FULL) {
2741 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2742 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2743 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
2744 } else {
2745 anar |= ADVERTISE_10HALF;
2746 anar |= ADVERTISE_100HALF;
2747 gbcr |= ADVERTISE_1000HALF;
2748 }
ac718b69 2749 } else {
2750 ret = -EINVAL;
2751 goto out;
2752 }
2753
2754 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
2755 }
2756
aa66a5f1 2757 if (test_bit(PHY_RESET, &tp->flags))
2758 bmcr |= BMCR_RESET;
2759
43779f8d 2760 if (tp->mii.supports_gmii)
2761 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
2762
ac718b69 2763 r8152_mdio_write(tp, MII_ADVERTISE, anar);
2764 r8152_mdio_write(tp, MII_BMCR, bmcr);
2765
aa66a5f1 2766 if (test_bit(PHY_RESET, &tp->flags)) {
2767 int i;
2768
2769 clear_bit(PHY_RESET, &tp->flags);
2770 for (i = 0; i < 50; i++) {
2771 msleep(20);
2772 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
2773 break;
2774 }
2775 }
2776
ac718b69 2777out:
ac718b69 2778
2779 return ret;
2780}
2781
d70b1137 2782static void rtl8152_up(struct r8152 *tp)
2783{
2784 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2785 return;
2786
2787 r8152b_disable_aldps(tp);
2788 r8152b_exit_oob(tp);
2789 r8152b_enable_aldps(tp);
2790}
2791
ac718b69 2792static void rtl8152_down(struct r8152 *tp)
2793{
6871438c 2794 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2795 rtl_drop_queued_tx(tp);
2796 return;
2797 }
2798
00a5e360 2799 r8152_power_cut_en(tp, false);
ac718b69 2800 r8152b_disable_aldps(tp);
2801 r8152b_enter_oob(tp);
2802 r8152b_enable_aldps(tp);
2803}
2804
d70b1137 2805static void rtl8153_up(struct r8152 *tp)
2806{
2807 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2808 return;
2809
2810 r8153_disable_aldps(tp);
2811 r8153_first_init(tp);
2812 r8153_enable_aldps(tp);
2813}
2814
43779f8d 2815static void rtl8153_down(struct r8152 *tp)
2816{
6871438c 2817 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2818 rtl_drop_queued_tx(tp);
2819 return;
2820 }
2821
b9702723 2822 r8153_u1u2en(tp, false);
2823 r8153_power_cut_en(tp, false);
43779f8d 2824 r8153_disable_aldps(tp);
2825 r8153_enter_oob(tp);
2826 r8153_enable_aldps(tp);
2827}
2828
ac718b69 2829static void set_carrier(struct r8152 *tp)
2830{
2831 struct net_device *netdev = tp->netdev;
2832 u8 speed;
2833
40a82917 2834 clear_bit(RTL8152_LINK_CHG, &tp->flags);
ac718b69 2835 speed = rtl8152_get_speed(tp);
2836
2837 if (speed & LINK_STATUS) {
2838 if (!(tp->speed & LINK_STATUS)) {
c81229c9 2839 tp->rtl_ops.enable(tp);
ac718b69 2840 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2841 netif_carrier_on(netdev);
2842 }
2843 } else {
2844 if (tp->speed & LINK_STATUS) {
2845 netif_carrier_off(netdev);
ebc2ec48 2846 tasklet_disable(&tp->tl);
c81229c9 2847 tp->rtl_ops.disable(tp);
ebc2ec48 2848 tasklet_enable(&tp->tl);
ac718b69 2849 }
2850 }
2851 tp->speed = speed;
2852}
2853
2854static void rtl_work_func_t(struct work_struct *work)
2855{
2856 struct r8152 *tp = container_of(work, struct r8152, schedule.work);
2857
9a4be1bd 2858 if (usb_autopm_get_interface(tp->intf) < 0)
2859 return;
2860
ac718b69 2861 if (!test_bit(WORK_ENABLE, &tp->flags))
2862 goto out1;
2863
2864 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2865 goto out1;
2866
b5403273 2867 if (!mutex_trylock(&tp->control)) {
2868 schedule_delayed_work(&tp->schedule, 0);
2869 goto out1;
2870 }
2871
40a82917 2872 if (test_bit(RTL8152_LINK_CHG, &tp->flags))
2873 set_carrier(tp);
ac718b69 2874
2875 if (test_bit(RTL8152_SET_RX_MODE, &tp->flags))
2876 _rtl8152_set_rx_mode(tp->netdev);
2877
0c3121fc 2878 if (test_bit(SCHEDULE_TASKLET, &tp->flags) &&
2879 (tp->speed & LINK_STATUS)) {
2880 clear_bit(SCHEDULE_TASKLET, &tp->flags);
2881 tasklet_schedule(&tp->tl);
2882 }
aa66a5f1 2883
2884 if (test_bit(PHY_RESET, &tp->flags))
2885 rtl_phy_reset(tp);
2886
b5403273 2887 mutex_unlock(&tp->control);
2888
ac718b69 2889out1:
9a4be1bd 2890 usb_autopm_put_interface(tp->intf);
ac718b69 2891}
2892
2893static int rtl8152_open(struct net_device *netdev)
2894{
2895 struct r8152 *tp = netdev_priv(netdev);
2896 int res = 0;
2897
7e9da481 2898 res = alloc_all_mem(tp);
2899 if (res)
2900 goto out;
2901
f4c7476b 2902 /* set speed to 0 to avoid autoresume try to submit rx */
2903 tp->speed = 0;
2904
9a4be1bd 2905 res = usb_autopm_get_interface(tp->intf);
2906 if (res < 0) {
2907 free_all_mem(tp);
2908 goto out;
2909 }
2910
b5403273 2911 mutex_lock(&tp->control);
2912
9a4be1bd 2913 /* The WORK_ENABLE may be set when autoresume occurs */
2914 if (test_bit(WORK_ENABLE, &tp->flags)) {
2915 clear_bit(WORK_ENABLE, &tp->flags);
2916 usb_kill_urb(tp->intr_urb);
2917 cancel_delayed_work_sync(&tp->schedule);
f4c7476b 2918
2919 /* disable the tx/rx, if the workqueue has enabled them. */
9a4be1bd 2920 if (tp->speed & LINK_STATUS)
2921 tp->rtl_ops.disable(tp);
2922 }
2923
7e9da481 2924 tp->rtl_ops.up(tp);
2925
3d55f44f 2926 rtl8152_set_speed(tp, AUTONEG_ENABLE,
2927 tp->mii.supports_gmii ? SPEED_1000 : SPEED_100,
2928 DUPLEX_FULL);
2929 tp->speed = 0;
2930 netif_carrier_off(netdev);
2931 netif_start_queue(netdev);
2932 set_bit(WORK_ENABLE, &tp->flags);
db8515ef 2933
40a82917 2934 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
2935 if (res) {
2936 if (res == -ENODEV)
2937 netif_device_detach(tp->netdev);
4a8deae2
HW
2938 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
2939 res);
7e9da481 2940 free_all_mem(tp);
93ffbeab 2941 } else {
2942 tasklet_enable(&tp->tl);
ac718b69 2943 }
2944
b5403273 2945 mutex_unlock(&tp->control);
2946
9a4be1bd 2947 usb_autopm_put_interface(tp->intf);
ac718b69 2948
7e9da481 2949out:
ac718b69 2950 return res;
2951}
2952
2953static int rtl8152_close(struct net_device *netdev)
2954{
2955 struct r8152 *tp = netdev_priv(netdev);
2956 int res = 0;
2957
93ffbeab 2958 tasklet_disable(&tp->tl);
ac718b69 2959 clear_bit(WORK_ENABLE, &tp->flags);
3d55f44f 2960 usb_kill_urb(tp->intr_urb);
ac718b69 2961 cancel_delayed_work_sync(&tp->schedule);
2962 netif_stop_queue(netdev);
9a4be1bd 2963
2964 res = usb_autopm_get_interface(tp->intf);
2965 if (res < 0) {
2966 rtl_drop_queued_tx(tp);
2967 } else {
b5403273 2968 mutex_lock(&tp->control);
2969
b209af99 2970 /* The autosuspend may have been enabled and wouldn't
9a4be1bd 2971 * be disable when autoresume occurs, because the
2972 * netif_running() would be false.
2973 */
923e1ee3 2974 rtl_runtime_suspend_enable(tp, false);
9a4be1bd 2975
9a4be1bd 2976 tp->rtl_ops.down(tp);
b5403273 2977
2978 mutex_unlock(&tp->control);
2979
9a4be1bd 2980 usb_autopm_put_interface(tp->intf);
2981 }
ac718b69 2982
7e9da481 2983 free_all_mem(tp);
2984
ac718b69 2985 return res;
2986}
2987
d24f6134 2988static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
2989{
2990 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
2991 ocp_reg_write(tp, OCP_EEE_DATA, reg);
2992 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
2993}
2994
2995static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
2996{
2997 u16 data;
2998
2999 r8152_mmd_indirect(tp, dev, reg);
3000 data = ocp_reg_read(tp, OCP_EEE_DATA);
3001 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
3002
3003 return data;
3004}
3005
3006static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
ac718b69 3007{
d24f6134 3008 r8152_mmd_indirect(tp, dev, reg);
3009 ocp_reg_write(tp, OCP_EEE_DATA, data);
3010 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
3011}
3012
3013static void r8152_eee_en(struct r8152 *tp, bool enable)
3014{
3015 u16 config1, config2, config3;
45f4a19f 3016 u32 ocp_data;
ac718b69 3017
3018 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
d24f6134 3019 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
3020 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
3021 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
3022
3023 if (enable) {
3024 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3025 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
3026 config1 |= sd_rise_time(1);
3027 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
3028 config3 |= fast_snr(42);
3029 } else {
3030 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3031 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
3032 RX_QUIET_EN);
3033 config1 |= sd_rise_time(7);
3034 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
3035 config3 |= fast_snr(511);
3036 }
3037
ac718b69 3038 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
d24f6134 3039 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
3040 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
3041 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
ac718b69 3042}
3043
d24f6134 3044static void r8152b_enable_eee(struct r8152 *tp)
3045{
3046 r8152_eee_en(tp, true);
3047 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
3048}
3049
3050static void r8153_eee_en(struct r8152 *tp, bool enable)
43779f8d 3051{
3052 u32 ocp_data;
d24f6134 3053 u16 config;
43779f8d 3054
3055 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
d24f6134 3056 config = ocp_reg_read(tp, OCP_EEE_CFG);
3057
3058 if (enable) {
3059 ocp_data |= EEE_RX_EN | EEE_TX_EN;
3060 config |= EEE10_EN;
3061 } else {
3062 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3063 config &= ~EEE10_EN;
3064 }
3065
43779f8d 3066 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
d24f6134 3067 ocp_reg_write(tp, OCP_EEE_CFG, config);
3068}
3069
3070static void r8153_enable_eee(struct r8152 *tp)
3071{
3072 r8153_eee_en(tp, true);
3073 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
43779f8d 3074}
3075
ac718b69 3076static void r8152b_enable_fc(struct r8152 *tp)
3077{
3078 u16 anar;
3079
3080 anar = r8152_mdio_read(tp, MII_ADVERTISE);
3081 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3082 r8152_mdio_write(tp, MII_ADVERTISE, anar);
3083}
3084
4f1d4d54 3085static void rtl_tally_reset(struct r8152 *tp)
3086{
3087 u32 ocp_data;
3088
3089 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
3090 ocp_data |= TALLY_RESET;
3091 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
3092}
3093
ac718b69 3094static void r8152b_init(struct r8152 *tp)
3095{
ebc2ec48 3096 u32 ocp_data;
ac718b69 3097
6871438c 3098 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3099 return;
3100
d70b1137 3101 r8152b_disable_aldps(tp);
3102
ac718b69 3103 if (tp->version == RTL_VER_01) {
3104 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3105 ocp_data &= ~LED_MODE_MASK;
3106 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3107 }
3108
00a5e360 3109 r8152_power_cut_en(tp, false);
ac718b69 3110
ac718b69 3111 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3112 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
3113 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3114 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
3115 ocp_data &= ~MCU_CLK_RATIO_MASK;
3116 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
3117 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
3118 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
3119 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
3120 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
3121
3122 r8152b_enable_eee(tp);
3123 r8152b_enable_aldps(tp);
3124 r8152b_enable_fc(tp);
4f1d4d54 3125 rtl_tally_reset(tp);
ac718b69 3126
ebc2ec48 3127 /* enable rx aggregation */
ac718b69 3128 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
ebc2ec48 3129 ocp_data &= ~RX_AGG_DISABLE;
ac718b69 3130 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
3131}
3132
43779f8d 3133static void r8153_init(struct r8152 *tp)
3134{
3135 u32 ocp_data;
3136 int i;
3137
6871438c 3138 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3139 return;
3140
d70b1137 3141 r8153_disable_aldps(tp);
b9702723 3142 r8153_u1u2en(tp, false);
43779f8d 3143
3144 for (i = 0; i < 500; i++) {
3145 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3146 AUTOLOAD_DONE)
3147 break;
3148 msleep(20);
3149 }
3150
3151 for (i = 0; i < 500; i++) {
3152 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
3153 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
3154 break;
3155 msleep(20);
3156 }
3157
b9702723 3158 r8153_u2p3en(tp, false);
43779f8d 3159
3160 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
3161 ocp_data &= ~TIMER11_EN;
3162 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
3163
43779f8d 3164 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3165 ocp_data &= ~LED_MODE_MASK;
3166 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3167
3168 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL);
3169 ocp_data &= ~LPM_TIMER_MASK;
3170 if (tp->udev->speed == USB_SPEED_SUPER)
3171 ocp_data |= LPM_TIMER_500US;
3172 else
3173 ocp_data |= LPM_TIMER_500MS;
3174 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
3175
3176 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
3177 ocp_data &= ~SEN_VAL_MASK;
3178 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
3179 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
3180
b9702723 3181 r8153_power_cut_en(tp, false);
3182 r8153_u1u2en(tp, true);
43779f8d 3183
43779f8d 3184 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO);
3185 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO);
3186 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
3187 PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
3188 U1U2_SPDWN_EN | L1_SPDWN_EN);
3189 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
3190 PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
3191 TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN |
3192 EEE_SPDWN_EN);
3193
3194 r8153_enable_eee(tp);
3195 r8153_enable_aldps(tp);
3196 r8152b_enable_fc(tp);
4f1d4d54 3197 rtl_tally_reset(tp);
43779f8d 3198}
3199
ac718b69 3200static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
3201{
3202 struct r8152 *tp = usb_get_intfdata(intf);
6cc69f2a 3203 struct net_device *netdev = tp->netdev;
3204 int ret = 0;
ac718b69 3205
b5403273 3206 mutex_lock(&tp->control);
3207
6cc69f2a 3208 if (PMSG_IS_AUTO(message)) {
3209 if (netif_running(netdev) && work_busy(&tp->schedule.work)) {
3210 ret = -EBUSY;
3211 goto out1;
3212 }
3213
9a4be1bd 3214 set_bit(SELECTIVE_SUSPEND, &tp->flags);
6cc69f2a 3215 } else {
3216 netif_device_detach(netdev);
3217 }
ac718b69 3218
e3bd1a81 3219 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
ac718b69 3220 clear_bit(WORK_ENABLE, &tp->flags);
40a82917 3221 usb_kill_urb(tp->intr_urb);
445f7f4d 3222 tasklet_disable(&tp->tl);
9a4be1bd 3223 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
445f7f4d 3224 rtl_stop_rx(tp);
9a4be1bd 3225 rtl_runtime_suspend_enable(tp, true);
3226 } else {
6cc69f2a 3227 cancel_delayed_work_sync(&tp->schedule);
9a4be1bd 3228 tp->rtl_ops.down(tp);
9a4be1bd 3229 }
445f7f4d 3230 tasklet_enable(&tp->tl);
ac718b69 3231 }
6cc69f2a 3232out1:
b5403273 3233 mutex_unlock(&tp->control);
3234
6cc69f2a 3235 return ret;
ac718b69 3236}
3237
3238static int rtl8152_resume(struct usb_interface *intf)
3239{
3240 struct r8152 *tp = usb_get_intfdata(intf);
3241
b5403273 3242 mutex_lock(&tp->control);
3243
9a4be1bd 3244 if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3245 tp->rtl_ops.init(tp);
3246 netif_device_attach(tp->netdev);
3247 }
3248
ac718b69 3249 if (netif_running(tp->netdev)) {
9a4be1bd 3250 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3251 rtl_runtime_suspend_enable(tp, false);
3252 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
445f7f4d 3253 set_bit(WORK_ENABLE, &tp->flags);
9a4be1bd 3254 if (tp->speed & LINK_STATUS)
445f7f4d 3255 rtl_start_rx(tp);
9a4be1bd 3256 } else {
3257 tp->rtl_ops.up(tp);
3258 rtl8152_set_speed(tp, AUTONEG_ENABLE,
b209af99 3259 tp->mii.supports_gmii ?
3260 SPEED_1000 : SPEED_100,
3261 DUPLEX_FULL);
445f7f4d 3262 tp->speed = 0;
3263 netif_carrier_off(tp->netdev);
3264 set_bit(WORK_ENABLE, &tp->flags);
9a4be1bd 3265 }
40a82917 3266 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
923e1ee3 3267 } else if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3268 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
ac718b69 3269 }
3270
b5403273 3271 mutex_unlock(&tp->control);
3272
ac718b69 3273 return 0;
3274}
3275
21ff2e89 3276static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3277{
3278 struct r8152 *tp = netdev_priv(dev);
3279
9a4be1bd 3280 if (usb_autopm_get_interface(tp->intf) < 0)
3281 return;
3282
b5403273 3283 mutex_lock(&tp->control);
3284
21ff2e89 3285 wol->supported = WAKE_ANY;
3286 wol->wolopts = __rtl_get_wol(tp);
9a4be1bd 3287
b5403273 3288 mutex_unlock(&tp->control);
3289
9a4be1bd 3290 usb_autopm_put_interface(tp->intf);
21ff2e89 3291}
3292
3293static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3294{
3295 struct r8152 *tp = netdev_priv(dev);
9a4be1bd 3296 int ret;
3297
3298 ret = usb_autopm_get_interface(tp->intf);
3299 if (ret < 0)
3300 goto out_set_wol;
21ff2e89 3301
b5403273 3302 mutex_lock(&tp->control);
3303
21ff2e89 3304 __rtl_set_wol(tp, wol->wolopts);
3305 tp->saved_wolopts = wol->wolopts & WAKE_ANY;
3306
b5403273 3307 mutex_unlock(&tp->control);
3308
9a4be1bd 3309 usb_autopm_put_interface(tp->intf);
3310
3311out_set_wol:
3312 return ret;
21ff2e89 3313}
3314
a5ec27c1 3315static u32 rtl8152_get_msglevel(struct net_device *dev)
3316{
3317 struct r8152 *tp = netdev_priv(dev);
3318
3319 return tp->msg_enable;
3320}
3321
3322static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
3323{
3324 struct r8152 *tp = netdev_priv(dev);
3325
3326 tp->msg_enable = value;
3327}
3328
ac718b69 3329static void rtl8152_get_drvinfo(struct net_device *netdev,
3330 struct ethtool_drvinfo *info)
3331{
3332 struct r8152 *tp = netdev_priv(netdev);
3333
b0b46c77 3334 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
3335 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
ac718b69 3336 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
3337}
3338
3339static
3340int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
3341{
3342 struct r8152 *tp = netdev_priv(netdev);
8d4a4d72 3343 int ret;
ac718b69 3344
3345 if (!tp->mii.mdio_read)
3346 return -EOPNOTSUPP;
3347
8d4a4d72 3348 ret = usb_autopm_get_interface(tp->intf);
3349 if (ret < 0)
3350 goto out;
3351
b5403273 3352 mutex_lock(&tp->control);
3353
8d4a4d72 3354 ret = mii_ethtool_gset(&tp->mii, cmd);
3355
b5403273 3356 mutex_unlock(&tp->control);
3357
8d4a4d72 3358 usb_autopm_put_interface(tp->intf);
3359
3360out:
3361 return ret;
ac718b69 3362}
3363
3364static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
3365{
3366 struct r8152 *tp = netdev_priv(dev);
9a4be1bd 3367 int ret;
3368
3369 ret = usb_autopm_get_interface(tp->intf);
3370 if (ret < 0)
3371 goto out;
ac718b69 3372
b5403273 3373 mutex_lock(&tp->control);
3374
9a4be1bd 3375 ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
3376
b5403273 3377 mutex_unlock(&tp->control);
3378
9a4be1bd 3379 usb_autopm_put_interface(tp->intf);
3380
3381out:
3382 return ret;
ac718b69 3383}
3384
4f1d4d54 3385static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
3386 "tx_packets",
3387 "rx_packets",
3388 "tx_errors",
3389 "rx_errors",
3390 "rx_missed",
3391 "align_errors",
3392 "tx_single_collisions",
3393 "tx_multi_collisions",
3394 "rx_unicast",
3395 "rx_broadcast",
3396 "rx_multicast",
3397 "tx_aborted",
3398 "tx_underrun",
3399};
3400
3401static int rtl8152_get_sset_count(struct net_device *dev, int sset)
3402{
3403 switch (sset) {
3404 case ETH_SS_STATS:
3405 return ARRAY_SIZE(rtl8152_gstrings);
3406 default:
3407 return -EOPNOTSUPP;
3408 }
3409}
3410
3411static void rtl8152_get_ethtool_stats(struct net_device *dev,
3412 struct ethtool_stats *stats, u64 *data)
3413{
3414 struct r8152 *tp = netdev_priv(dev);
3415 struct tally_counter tally;
3416
0b030244 3417 if (usb_autopm_get_interface(tp->intf) < 0)
3418 return;
3419
4f1d4d54 3420 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
3421
0b030244 3422 usb_autopm_put_interface(tp->intf);
3423
4f1d4d54 3424 data[0] = le64_to_cpu(tally.tx_packets);
3425 data[1] = le64_to_cpu(tally.rx_packets);
3426 data[2] = le64_to_cpu(tally.tx_errors);
3427 data[3] = le32_to_cpu(tally.rx_errors);
3428 data[4] = le16_to_cpu(tally.rx_missed);
3429 data[5] = le16_to_cpu(tally.align_errors);
3430 data[6] = le32_to_cpu(tally.tx_one_collision);
3431 data[7] = le32_to_cpu(tally.tx_multi_collision);
3432 data[8] = le64_to_cpu(tally.rx_unicast);
3433 data[9] = le64_to_cpu(tally.rx_broadcast);
3434 data[10] = le32_to_cpu(tally.rx_multicast);
3435 data[11] = le16_to_cpu(tally.tx_aborted);
f37119c5 3436 data[12] = le16_to_cpu(tally.tx_underrun);
4f1d4d54 3437}
3438
3439static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
3440{
3441 switch (stringset) {
3442 case ETH_SS_STATS:
3443 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
3444 break;
3445 }
3446}
3447
df35d283 3448static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
3449{
3450 u32 ocp_data, lp, adv, supported = 0;
3451 u16 val;
3452
3453 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
3454 supported = mmd_eee_cap_to_ethtool_sup_t(val);
3455
3456 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
3457 adv = mmd_eee_adv_to_ethtool_adv_t(val);
3458
3459 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
3460 lp = mmd_eee_adv_to_ethtool_adv_t(val);
3461
3462 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3463 ocp_data &= EEE_RX_EN | EEE_TX_EN;
3464
3465 eee->eee_enabled = !!ocp_data;
3466 eee->eee_active = !!(supported & adv & lp);
3467 eee->supported = supported;
3468 eee->advertised = adv;
3469 eee->lp_advertised = lp;
3470
3471 return 0;
3472}
3473
3474static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
3475{
3476 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
3477
3478 r8152_eee_en(tp, eee->eee_enabled);
3479
3480 if (!eee->eee_enabled)
3481 val = 0;
3482
3483 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3484
3485 return 0;
3486}
3487
3488static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
3489{
3490 u32 ocp_data, lp, adv, supported = 0;
3491 u16 val;
3492
3493 val = ocp_reg_read(tp, OCP_EEE_ABLE);
3494 supported = mmd_eee_cap_to_ethtool_sup_t(val);
3495
3496 val = ocp_reg_read(tp, OCP_EEE_ADV);
3497 adv = mmd_eee_adv_to_ethtool_adv_t(val);
3498
3499 val = ocp_reg_read(tp, OCP_EEE_LPABLE);
3500 lp = mmd_eee_adv_to_ethtool_adv_t(val);
3501
3502 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3503 ocp_data &= EEE_RX_EN | EEE_TX_EN;
3504
3505 eee->eee_enabled = !!ocp_data;
3506 eee->eee_active = !!(supported & adv & lp);
3507 eee->supported = supported;
3508 eee->advertised = adv;
3509 eee->lp_advertised = lp;
3510
3511 return 0;
3512}
3513
3514static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
3515{
3516 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
3517
3518 r8153_eee_en(tp, eee->eee_enabled);
3519
3520 if (!eee->eee_enabled)
3521 val = 0;
3522
3523 ocp_reg_write(tp, OCP_EEE_ADV, val);
3524
3525 return 0;
3526}
3527
3528static int
3529rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
3530{
3531 struct r8152 *tp = netdev_priv(net);
3532 int ret;
3533
3534 ret = usb_autopm_get_interface(tp->intf);
3535 if (ret < 0)
3536 goto out;
3537
b5403273 3538 mutex_lock(&tp->control);
3539
df35d283 3540 ret = tp->rtl_ops.eee_get(tp, edata);
3541
b5403273 3542 mutex_unlock(&tp->control);
3543
df35d283 3544 usb_autopm_put_interface(tp->intf);
3545
3546out:
3547 return ret;
3548}
3549
3550static int
3551rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
3552{
3553 struct r8152 *tp = netdev_priv(net);
3554 int ret;
3555
3556 ret = usb_autopm_get_interface(tp->intf);
3557 if (ret < 0)
3558 goto out;
3559
b5403273 3560 mutex_lock(&tp->control);
3561
df35d283 3562 ret = tp->rtl_ops.eee_set(tp, edata);
9d31a7b9 3563 if (!ret)
3564 ret = mii_nway_restart(&tp->mii);
df35d283 3565
b5403273 3566 mutex_unlock(&tp->control);
3567
df35d283 3568 usb_autopm_put_interface(tp->intf);
3569
3570out:
3571 return ret;
3572}
3573
8884f507 3574static int rtl8152_nway_reset(struct net_device *dev)
3575{
3576 struct r8152 *tp = netdev_priv(dev);
3577 int ret;
3578
3579 ret = usb_autopm_get_interface(tp->intf);
3580 if (ret < 0)
3581 goto out;
3582
3583 mutex_lock(&tp->control);
3584
3585 ret = mii_nway_restart(&tp->mii);
3586
3587 mutex_unlock(&tp->control);
3588
3589 usb_autopm_put_interface(tp->intf);
3590
3591out:
3592 return ret;
3593}
3594
ac718b69 3595static struct ethtool_ops ops = {
3596 .get_drvinfo = rtl8152_get_drvinfo,
3597 .get_settings = rtl8152_get_settings,
3598 .set_settings = rtl8152_set_settings,
3599 .get_link = ethtool_op_get_link,
8884f507 3600 .nway_reset = rtl8152_nway_reset,
a5ec27c1 3601 .get_msglevel = rtl8152_get_msglevel,
3602 .set_msglevel = rtl8152_set_msglevel,
21ff2e89 3603 .get_wol = rtl8152_get_wol,
3604 .set_wol = rtl8152_set_wol,
4f1d4d54 3605 .get_strings = rtl8152_get_strings,
3606 .get_sset_count = rtl8152_get_sset_count,
3607 .get_ethtool_stats = rtl8152_get_ethtool_stats,
df35d283 3608 .get_eee = rtl_ethtool_get_eee,
3609 .set_eee = rtl_ethtool_set_eee,
ac718b69 3610};
3611
3612static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
3613{
3614 struct r8152 *tp = netdev_priv(netdev);
3615 struct mii_ioctl_data *data = if_mii(rq);
9a4be1bd 3616 int res;
3617
6871438c 3618 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3619 return -ENODEV;
3620
9a4be1bd 3621 res = usb_autopm_get_interface(tp->intf);
3622 if (res < 0)
3623 goto out;
ac718b69 3624
3625 switch (cmd) {
3626 case SIOCGMIIPHY:
3627 data->phy_id = R8152_PHY_ID; /* Internal PHY */
3628 break;
3629
3630 case SIOCGMIIREG:
b5403273 3631 mutex_lock(&tp->control);
ac718b69 3632 data->val_out = r8152_mdio_read(tp, data->reg_num);
b5403273 3633 mutex_unlock(&tp->control);
ac718b69 3634 break;
3635
3636 case SIOCSMIIREG:
3637 if (!capable(CAP_NET_ADMIN)) {
3638 res = -EPERM;
3639 break;
3640 }
b5403273 3641 mutex_lock(&tp->control);
ac718b69 3642 r8152_mdio_write(tp, data->reg_num, data->val_in);
b5403273 3643 mutex_unlock(&tp->control);
ac718b69 3644 break;
3645
3646 default:
3647 res = -EOPNOTSUPP;
3648 }
3649
9a4be1bd 3650 usb_autopm_put_interface(tp->intf);
3651
3652out:
ac718b69 3653 return res;
3654}
3655
69b4b7a4 3656static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
3657{
3658 struct r8152 *tp = netdev_priv(dev);
3659
3660 switch (tp->version) {
3661 case RTL_VER_01:
3662 case RTL_VER_02:
3663 return eth_change_mtu(dev, new_mtu);
3664 default:
3665 break;
3666 }
3667
3668 if (new_mtu < 68 || new_mtu > RTL8153_MAX_MTU)
3669 return -EINVAL;
3670
3671 dev->mtu = new_mtu;
3672
3673 return 0;
3674}
3675
ac718b69 3676static const struct net_device_ops rtl8152_netdev_ops = {
3677 .ndo_open = rtl8152_open,
3678 .ndo_stop = rtl8152_close,
3679 .ndo_do_ioctl = rtl8152_ioctl,
3680 .ndo_start_xmit = rtl8152_start_xmit,
3681 .ndo_tx_timeout = rtl8152_tx_timeout,
c5554298 3682 .ndo_set_features = rtl8152_set_features,
ac718b69 3683 .ndo_set_rx_mode = rtl8152_set_rx_mode,
3684 .ndo_set_mac_address = rtl8152_set_mac_address,
69b4b7a4 3685 .ndo_change_mtu = rtl8152_change_mtu,
ac718b69 3686 .ndo_validate_addr = eth_validate_addr,
3687};
3688
3689static void r8152b_get_version(struct r8152 *tp)
3690{
3691 u32 ocp_data;
3692 u16 version;
3693
3694 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
3695 version = (u16)(ocp_data & VERSION_MASK);
3696
3697 switch (version) {
3698 case 0x4c00:
3699 tp->version = RTL_VER_01;
3700 break;
3701 case 0x4c10:
3702 tp->version = RTL_VER_02;
3703 break;
43779f8d 3704 case 0x5c00:
3705 tp->version = RTL_VER_03;
3706 tp->mii.supports_gmii = 1;
3707 break;
3708 case 0x5c10:
3709 tp->version = RTL_VER_04;
3710 tp->mii.supports_gmii = 1;
3711 break;
3712 case 0x5c20:
3713 tp->version = RTL_VER_05;
3714 tp->mii.supports_gmii = 1;
3715 break;
ac718b69 3716 default:
3717 netif_info(tp, probe, tp->netdev,
3718 "Unknown version 0x%04x\n", version);
3719 break;
3720 }
3721}
3722
e3fe0b1a 3723static void rtl8152_unload(struct r8152 *tp)
3724{
6871438c 3725 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3726 return;
3727
00a5e360 3728 if (tp->version != RTL_VER_01)
3729 r8152_power_cut_en(tp, true);
e3fe0b1a 3730}
3731
43779f8d 3732static void rtl8153_unload(struct r8152 *tp)
3733{
6871438c 3734 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3735 return;
3736
49be1723 3737 r8153_power_cut_en(tp, false);
43779f8d 3738}
3739
55b65475 3740static int rtl_ops_init(struct r8152 *tp)
c81229c9 3741{
3742 struct rtl_ops *ops = &tp->rtl_ops;
55b65475 3743 int ret = 0;
3744
3745 switch (tp->version) {
3746 case RTL_VER_01:
3747 case RTL_VER_02:
3748 ops->init = r8152b_init;
3749 ops->enable = rtl8152_enable;
3750 ops->disable = rtl8152_disable;
3751 ops->up = rtl8152_up;
3752 ops->down = rtl8152_down;
3753 ops->unload = rtl8152_unload;
3754 ops->eee_get = r8152_get_eee;
3755 ops->eee_set = r8152_set_eee;
43779f8d 3756 break;
3757
55b65475 3758 case RTL_VER_03:
3759 case RTL_VER_04:
3760 case RTL_VER_05:
3761 ops->init = r8153_init;
3762 ops->enable = rtl8153_enable;
3763 ops->disable = rtl8153_disable;
3764 ops->up = rtl8153_up;
3765 ops->down = rtl8153_down;
3766 ops->unload = rtl8153_unload;
3767 ops->eee_get = r8153_get_eee;
3768 ops->eee_set = r8153_set_eee;
c81229c9 3769 break;
3770
3771 default:
55b65475 3772 ret = -ENODEV;
3773 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
c81229c9 3774 break;
3775 }
3776
3777 return ret;
3778}
3779
ac718b69 3780static int rtl8152_probe(struct usb_interface *intf,
3781 const struct usb_device_id *id)
3782{
3783 struct usb_device *udev = interface_to_usbdev(intf);
3784 struct r8152 *tp;
3785 struct net_device *netdev;
ebc2ec48 3786 int ret;
ac718b69 3787
10c32717 3788 if (udev->actconfig->desc.bConfigurationValue != 1) {
3789 usb_driver_set_configuration(udev, 1);
3790 return -ENODEV;
3791 }
3792
3793 usb_reset_device(udev);
ac718b69 3794 netdev = alloc_etherdev(sizeof(struct r8152));
3795 if (!netdev) {
4a8deae2 3796 dev_err(&intf->dev, "Out of memory\n");
ac718b69 3797 return -ENOMEM;
3798 }
3799
ebc2ec48 3800 SET_NETDEV_DEV(netdev, &intf->dev);
ac718b69 3801 tp = netdev_priv(netdev);
3802 tp->msg_enable = 0x7FFF;
3803
e3ad412a 3804 tp->udev = udev;
3805 tp->netdev = netdev;
3806 tp->intf = intf;
3807
82cf94cb 3808 r8152b_get_version(tp);
55b65475 3809 ret = rtl_ops_init(tp);
31ca1dec 3810 if (ret)
3811 goto out;
c81229c9 3812
ebc2ec48 3813 tasklet_init(&tp->tl, bottom_half, (unsigned long)tp);
b5403273 3814 mutex_init(&tp->control);
ac718b69 3815 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
3816
ac718b69 3817 netdev->netdev_ops = &rtl8152_netdev_ops;
3818 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
5bd23881 3819
60c89071 3820 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
6128d1bb 3821 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
c5554298 3822 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
3823 NETIF_F_HW_VLAN_CTAG_TX;
60c89071 3824 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
6128d1bb 3825 NETIF_F_TSO | NETIF_F_FRAGLIST |
c5554298 3826 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
3827 NETIF_F_HW_VLAN_CTAG_RX |
3828 NETIF_F_HW_VLAN_CTAG_TX;
3829 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3830 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
3831 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
db8515ef 3832
7ad24ea4 3833 netdev->ethtool_ops = &ops;
60c89071 3834 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
ac718b69 3835
3836 tp->mii.dev = netdev;
3837 tp->mii.mdio_read = read_mii_word;
3838 tp->mii.mdio_write = write_mii_word;
3839 tp->mii.phy_id_mask = 0x3f;
3840 tp->mii.reg_num_mask = 0x1f;
3841 tp->mii.phy_id = R8152_PHY_ID;
ac718b69 3842
9a4be1bd 3843 intf->needs_remote_wakeup = 1;
3844
c81229c9 3845 tp->rtl_ops.init(tp);
ac718b69 3846 set_ethernet_addr(tp);
3847
ac718b69 3848 usb_set_intfdata(intf, tp);
ac718b69 3849
ebc2ec48 3850 ret = register_netdev(netdev);
3851 if (ret != 0) {
4a8deae2 3852 netif_err(tp, probe, netdev, "couldn't register the device\n");
ebc2ec48 3853 goto out1;
ac718b69 3854 }
3855
21ff2e89 3856 tp->saved_wolopts = __rtl_get_wol(tp);
3857 if (tp->saved_wolopts)
3858 device_set_wakeup_enable(&udev->dev, true);
3859 else
3860 device_set_wakeup_enable(&udev->dev, false);
3861
93ffbeab 3862 tasklet_disable(&tp->tl);
3863
4a8deae2 3864 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
ac718b69 3865
3866 return 0;
3867
ac718b69 3868out1:
ebc2ec48 3869 usb_set_intfdata(intf, NULL);
93ffbeab 3870 tasklet_kill(&tp->tl);
ac718b69 3871out:
3872 free_netdev(netdev);
ebc2ec48 3873 return ret;
ac718b69 3874}
3875
ac718b69 3876static void rtl8152_disconnect(struct usb_interface *intf)
3877{
3878 struct r8152 *tp = usb_get_intfdata(intf);
3879
3880 usb_set_intfdata(intf, NULL);
3881 if (tp) {
f561de33 3882 struct usb_device *udev = tp->udev;
3883
3884 if (udev->state == USB_STATE_NOTATTACHED)
3885 set_bit(RTL8152_UNPLUG, &tp->flags);
3886
ac718b69 3887 tasklet_kill(&tp->tl);
3888 unregister_netdev(tp->netdev);
c81229c9 3889 tp->rtl_ops.unload(tp);
ac718b69 3890 free_netdev(tp->netdev);
3891 }
3892}
3893
3894/* table of devices that work with this driver */
3895static struct usb_device_id rtl8152_table[] = {
662412d1 3896 {USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
3897 {USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
3898 {USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
ac718b69 3899 {}
3900};
3901
3902MODULE_DEVICE_TABLE(usb, rtl8152_table);
3903
3904static struct usb_driver rtl8152_driver = {
3905 .name = MODULENAME,
ebc2ec48 3906 .id_table = rtl8152_table,
ac718b69 3907 .probe = rtl8152_probe,
3908 .disconnect = rtl8152_disconnect,
ac718b69 3909 .suspend = rtl8152_suspend,
ebc2ec48 3910 .resume = rtl8152_resume,
3911 .reset_resume = rtl8152_resume,
9a4be1bd 3912 .supports_autosuspend = 1,
a634782f 3913 .disable_hub_initiated_lpm = 1,
ac718b69 3914};
3915
b4236daa 3916module_usb_driver(rtl8152_driver);
ac718b69 3917
3918MODULE_AUTHOR(DRIVER_AUTHOR);
3919MODULE_DESCRIPTION(DRIVER_DESC);
3920MODULE_LICENSE("GPL");