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ac718b69 | 1 | /* |
c7de7dec | 2 | * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved. |
ac718b69 | 3 | * |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * version 2 as published by the Free Software Foundation. | |
7 | * | |
8 | */ | |
9 | ||
ac718b69 | 10 | #include <linux/signal.h> |
11 | #include <linux/slab.h> | |
12 | #include <linux/module.h> | |
ac718b69 | 13 | #include <linux/netdevice.h> |
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/mii.h> | |
16 | #include <linux/ethtool.h> | |
17 | #include <linux/usb.h> | |
18 | #include <linux/crc32.h> | |
19 | #include <linux/if_vlan.h> | |
20 | #include <linux/uaccess.h> | |
ebc2ec48 | 21 | #include <linux/list.h> |
5bd23881 | 22 | #include <linux/ip.h> |
23 | #include <linux/ipv6.h> | |
6128d1bb | 24 | #include <net/ip6_checksum.h> |
4c4a6b1b | 25 | #include <uapi/linux/mdio.h> |
26 | #include <linux/mdio.h> | |
d9a28c5b | 27 | #include <linux/usb/cdc.h> |
5ee3c60c | 28 | #include <linux/suspend.h> |
34ee32c9 | 29 | #include <linux/acpi.h> |
ac718b69 | 30 | |
d0942473 | 31 | /* Information for net-next */ |
32 | #define NETNEXT_VERSION "08" | |
33 | ||
34 | /* Information for net */ | |
b20cb60e | 35 | #define NET_VERSION "9" |
d0942473 | 36 | |
37 | #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION | |
ac718b69 | 38 | #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>" |
44d942a9 | 39 | #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters" |
ac718b69 | 40 | #define MODULENAME "r8152" |
41 | ||
42 | #define R8152_PHY_ID 32 | |
43 | ||
44 | #define PLA_IDR 0xc000 | |
45 | #define PLA_RCR 0xc010 | |
46 | #define PLA_RMS 0xc016 | |
47 | #define PLA_RXFIFO_CTRL0 0xc0a0 | |
48 | #define PLA_RXFIFO_CTRL1 0xc0a4 | |
49 | #define PLA_RXFIFO_CTRL2 0xc0a8 | |
65bab84c | 50 | #define PLA_DMY_REG0 0xc0b0 |
ac718b69 | 51 | #define PLA_FMC 0xc0b4 |
52 | #define PLA_CFG_WOL 0xc0b6 | |
43779f8d | 53 | #define PLA_TEREDO_CFG 0xc0bc |
ac718b69 | 54 | #define PLA_MAR 0xcd00 |
43779f8d | 55 | #define PLA_BACKUP 0xd000 |
ac718b69 | 56 | #define PAL_BDC_CR 0xd1a0 |
43779f8d | 57 | #define PLA_TEREDO_TIMER 0xd2cc |
58 | #define PLA_REALWOW_TIMER 0xd2e8 | |
ac718b69 | 59 | #define PLA_LEDSEL 0xdd90 |
60 | #define PLA_LED_FEATURE 0xdd92 | |
61 | #define PLA_PHYAR 0xde00 | |
43779f8d | 62 | #define PLA_BOOT_CTRL 0xe004 |
ac718b69 | 63 | #define PLA_GPHY_INTR_IMR 0xe022 |
64 | #define PLA_EEE_CR 0xe040 | |
65 | #define PLA_EEEP_CR 0xe080 | |
66 | #define PLA_MAC_PWR_CTRL 0xe0c0 | |
43779f8d | 67 | #define PLA_MAC_PWR_CTRL2 0xe0ca |
68 | #define PLA_MAC_PWR_CTRL3 0xe0cc | |
69 | #define PLA_MAC_PWR_CTRL4 0xe0ce | |
70 | #define PLA_WDT6_CTRL 0xe428 | |
ac718b69 | 71 | #define PLA_TCR0 0xe610 |
72 | #define PLA_TCR1 0xe612 | |
69b4b7a4 | 73 | #define PLA_MTPS 0xe615 |
ac718b69 | 74 | #define PLA_TXFIFO_CTRL 0xe618 |
4f1d4d54 | 75 | #define PLA_RSTTALLY 0xe800 |
ac718b69 | 76 | #define PLA_CR 0xe813 |
77 | #define PLA_CRWECR 0xe81c | |
21ff2e89 | 78 | #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */ |
79 | #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */ | |
ac718b69 | 80 | #define PLA_CONFIG5 0xe822 |
81 | #define PLA_PHY_PWR 0xe84c | |
82 | #define PLA_OOB_CTRL 0xe84f | |
83 | #define PLA_CPCR 0xe854 | |
84 | #define PLA_MISC_0 0xe858 | |
85 | #define PLA_MISC_1 0xe85a | |
86 | #define PLA_OCP_GPHY_BASE 0xe86c | |
4f1d4d54 | 87 | #define PLA_TALLYCNT 0xe890 |
ac718b69 | 88 | #define PLA_SFF_STS_7 0xe8de |
89 | #define PLA_PHYSTATUS 0xe908 | |
90 | #define PLA_BP_BA 0xfc26 | |
91 | #define PLA_BP_0 0xfc28 | |
92 | #define PLA_BP_1 0xfc2a | |
93 | #define PLA_BP_2 0xfc2c | |
94 | #define PLA_BP_3 0xfc2e | |
95 | #define PLA_BP_4 0xfc30 | |
96 | #define PLA_BP_5 0xfc32 | |
97 | #define PLA_BP_6 0xfc34 | |
98 | #define PLA_BP_7 0xfc36 | |
43779f8d | 99 | #define PLA_BP_EN 0xfc38 |
ac718b69 | 100 | |
65bab84c | 101 | #define USB_USB2PHY 0xb41e |
102 | #define USB_SSPHYLINK2 0xb428 | |
43779f8d | 103 | #define USB_U2P3_CTRL 0xb460 |
65bab84c | 104 | #define USB_CSR_DUMMY1 0xb464 |
105 | #define USB_CSR_DUMMY2 0xb466 | |
ac718b69 | 106 | #define USB_DEV_STAT 0xb808 |
65bab84c | 107 | #define USB_CONNECT_TIMER 0xcbf8 |
108 | #define USB_BURST_SIZE 0xcfc0 | |
ac718b69 | 109 | #define USB_USB_CTRL 0xd406 |
110 | #define USB_PHY_CTRL 0xd408 | |
111 | #define USB_TX_AGG 0xd40a | |
112 | #define USB_RX_BUF_TH 0xd40c | |
113 | #define USB_USB_TIMER 0xd428 | |
464ec10a | 114 | #define USB_RX_EARLY_TIMEOUT 0xd42c |
115 | #define USB_RX_EARLY_SIZE 0xd42e | |
ac718b69 | 116 | #define USB_PM_CTRL_STATUS 0xd432 |
117 | #define USB_TX_DMA 0xd434 | |
43779f8d | 118 | #define USB_TOLERANCE 0xd490 |
119 | #define USB_LPM_CTRL 0xd41a | |
93fe9b18 | 120 | #define USB_BMU_RESET 0xd4b0 |
ac718b69 | 121 | #define USB_UPS_CTRL 0xd800 |
43779f8d | 122 | #define USB_MISC_0 0xd81a |
123 | #define USB_POWER_CUT 0xd80a | |
124 | #define USB_AFE_CTRL2 0xd824 | |
125 | #define USB_WDT11_CTRL 0xe43c | |
ac718b69 | 126 | #define USB_BP_BA 0xfc26 |
127 | #define USB_BP_0 0xfc28 | |
128 | #define USB_BP_1 0xfc2a | |
129 | #define USB_BP_2 0xfc2c | |
130 | #define USB_BP_3 0xfc2e | |
131 | #define USB_BP_4 0xfc30 | |
132 | #define USB_BP_5 0xfc32 | |
133 | #define USB_BP_6 0xfc34 | |
134 | #define USB_BP_7 0xfc36 | |
43779f8d | 135 | #define USB_BP_EN 0xfc38 |
ac718b69 | 136 | |
137 | /* OCP Registers */ | |
138 | #define OCP_ALDPS_CONFIG 0x2010 | |
139 | #define OCP_EEE_CONFIG1 0x2080 | |
140 | #define OCP_EEE_CONFIG2 0x2092 | |
141 | #define OCP_EEE_CONFIG3 0x2094 | |
ac244d3e | 142 | #define OCP_BASE_MII 0xa400 |
ac718b69 | 143 | #define OCP_EEE_AR 0xa41a |
144 | #define OCP_EEE_DATA 0xa41c | |
43779f8d | 145 | #define OCP_PHY_STATUS 0xa420 |
146 | #define OCP_POWER_CFG 0xa430 | |
147 | #define OCP_EEE_CFG 0xa432 | |
148 | #define OCP_SRAM_ADDR 0xa436 | |
149 | #define OCP_SRAM_DATA 0xa438 | |
150 | #define OCP_DOWN_SPEED 0xa442 | |
df35d283 | 151 | #define OCP_EEE_ABLE 0xa5c4 |
4c4a6b1b | 152 | #define OCP_EEE_ADV 0xa5d0 |
df35d283 | 153 | #define OCP_EEE_LPABLE 0xa5d2 |
2dd49e0f | 154 | #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */ |
43779f8d | 155 | #define OCP_ADC_CFG 0xbc06 |
156 | ||
157 | /* SRAM Register */ | |
158 | #define SRAM_LPF_CFG 0x8012 | |
159 | #define SRAM_10M_AMP1 0x8080 | |
160 | #define SRAM_10M_AMP2 0x8082 | |
161 | #define SRAM_IMPEDANCE 0x8084 | |
ac718b69 | 162 | |
163 | /* PLA_RCR */ | |
164 | #define RCR_AAP 0x00000001 | |
165 | #define RCR_APM 0x00000002 | |
166 | #define RCR_AM 0x00000004 | |
167 | #define RCR_AB 0x00000008 | |
168 | #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB) | |
169 | ||
170 | /* PLA_RXFIFO_CTRL0 */ | |
171 | #define RXFIFO_THR1_NORMAL 0x00080002 | |
172 | #define RXFIFO_THR1_OOB 0x01800003 | |
173 | ||
174 | /* PLA_RXFIFO_CTRL1 */ | |
175 | #define RXFIFO_THR2_FULL 0x00000060 | |
176 | #define RXFIFO_THR2_HIGH 0x00000038 | |
177 | #define RXFIFO_THR2_OOB 0x0000004a | |
43779f8d | 178 | #define RXFIFO_THR2_NORMAL 0x00a0 |
ac718b69 | 179 | |
180 | /* PLA_RXFIFO_CTRL2 */ | |
181 | #define RXFIFO_THR3_FULL 0x00000078 | |
182 | #define RXFIFO_THR3_HIGH 0x00000048 | |
183 | #define RXFIFO_THR3_OOB 0x0000005a | |
43779f8d | 184 | #define RXFIFO_THR3_NORMAL 0x0110 |
ac718b69 | 185 | |
186 | /* PLA_TXFIFO_CTRL */ | |
187 | #define TXFIFO_THR_NORMAL 0x00400008 | |
43779f8d | 188 | #define TXFIFO_THR_NORMAL2 0x01000008 |
ac718b69 | 189 | |
65bab84c | 190 | /* PLA_DMY_REG0 */ |
191 | #define ECM_ALDPS 0x0002 | |
192 | ||
ac718b69 | 193 | /* PLA_FMC */ |
194 | #define FMC_FCR_MCU_EN 0x0001 | |
195 | ||
196 | /* PLA_EEEP_CR */ | |
197 | #define EEEP_CR_EEEP_TX 0x0002 | |
198 | ||
43779f8d | 199 | /* PLA_WDT6_CTRL */ |
200 | #define WDT6_SET_MODE 0x0010 | |
201 | ||
ac718b69 | 202 | /* PLA_TCR0 */ |
203 | #define TCR0_TX_EMPTY 0x0800 | |
204 | #define TCR0_AUTO_FIFO 0x0080 | |
205 | ||
206 | /* PLA_TCR1 */ | |
207 | #define VERSION_MASK 0x7cf0 | |
208 | ||
69b4b7a4 | 209 | /* PLA_MTPS */ |
210 | #define MTPS_JUMBO (12 * 1024 / 64) | |
211 | #define MTPS_DEFAULT (6 * 1024 / 64) | |
212 | ||
4f1d4d54 | 213 | /* PLA_RSTTALLY */ |
214 | #define TALLY_RESET 0x0001 | |
215 | ||
ac718b69 | 216 | /* PLA_CR */ |
217 | #define CR_RST 0x10 | |
218 | #define CR_RE 0x08 | |
219 | #define CR_TE 0x04 | |
220 | ||
221 | /* PLA_CRWECR */ | |
222 | #define CRWECR_NORAML 0x00 | |
223 | #define CRWECR_CONFIG 0xc0 | |
224 | ||
225 | /* PLA_OOB_CTRL */ | |
226 | #define NOW_IS_OOB 0x80 | |
227 | #define TXFIFO_EMPTY 0x20 | |
228 | #define RXFIFO_EMPTY 0x10 | |
229 | #define LINK_LIST_READY 0x02 | |
230 | #define DIS_MCU_CLROOB 0x01 | |
231 | #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY) | |
232 | ||
233 | /* PLA_MISC_1 */ | |
234 | #define RXDY_GATED_EN 0x0008 | |
235 | ||
236 | /* PLA_SFF_STS_7 */ | |
237 | #define RE_INIT_LL 0x8000 | |
238 | #define MCU_BORW_EN 0x4000 | |
239 | ||
240 | /* PLA_CPCR */ | |
241 | #define CPCR_RX_VLAN 0x0040 | |
242 | ||
243 | /* PLA_CFG_WOL */ | |
244 | #define MAGIC_EN 0x0001 | |
245 | ||
43779f8d | 246 | /* PLA_TEREDO_CFG */ |
247 | #define TEREDO_SEL 0x8000 | |
248 | #define TEREDO_WAKE_MASK 0x7f00 | |
249 | #define TEREDO_RS_EVENT_MASK 0x00fe | |
250 | #define OOB_TEREDO_EN 0x0001 | |
251 | ||
ac718b69 | 252 | /* PAL_BDC_CR */ |
253 | #define ALDPS_PROXY_MODE 0x0001 | |
254 | ||
21ff2e89 | 255 | /* PLA_CONFIG34 */ |
256 | #define LINK_ON_WAKE_EN 0x0010 | |
257 | #define LINK_OFF_WAKE_EN 0x0008 | |
258 | ||
ac718b69 | 259 | /* PLA_CONFIG5 */ |
21ff2e89 | 260 | #define BWF_EN 0x0040 |
261 | #define MWF_EN 0x0020 | |
262 | #define UWF_EN 0x0010 | |
ac718b69 | 263 | #define LAN_WAKE_EN 0x0002 |
264 | ||
265 | /* PLA_LED_FEATURE */ | |
266 | #define LED_MODE_MASK 0x0700 | |
267 | ||
268 | /* PLA_PHY_PWR */ | |
269 | #define TX_10M_IDLE_EN 0x0080 | |
270 | #define PFM_PWM_SWITCH 0x0040 | |
271 | ||
272 | /* PLA_MAC_PWR_CTRL */ | |
273 | #define D3_CLK_GATED_EN 0x00004000 | |
274 | #define MCU_CLK_RATIO 0x07010f07 | |
275 | #define MCU_CLK_RATIO_MASK 0x0f0f0f0f | |
43779f8d | 276 | #define ALDPS_SPDWN_RATIO 0x0f87 |
277 | ||
278 | /* PLA_MAC_PWR_CTRL2 */ | |
279 | #define EEE_SPDWN_RATIO 0x8007 | |
280 | ||
281 | /* PLA_MAC_PWR_CTRL3 */ | |
282 | #define PKT_AVAIL_SPDWN_EN 0x0100 | |
283 | #define SUSPEND_SPDWN_EN 0x0004 | |
284 | #define U1U2_SPDWN_EN 0x0002 | |
285 | #define L1_SPDWN_EN 0x0001 | |
286 | ||
287 | /* PLA_MAC_PWR_CTRL4 */ | |
288 | #define PWRSAVE_SPDWN_EN 0x1000 | |
289 | #define RXDV_SPDWN_EN 0x0800 | |
290 | #define TX10MIDLE_EN 0x0100 | |
291 | #define TP100_SPDWN_EN 0x0020 | |
292 | #define TP500_SPDWN_EN 0x0010 | |
293 | #define TP1000_SPDWN_EN 0x0008 | |
294 | #define EEE_SPDWN_EN 0x0001 | |
ac718b69 | 295 | |
296 | /* PLA_GPHY_INTR_IMR */ | |
297 | #define GPHY_STS_MSK 0x0001 | |
298 | #define SPEED_DOWN_MSK 0x0002 | |
299 | #define SPDWN_RXDV_MSK 0x0004 | |
300 | #define SPDWN_LINKCHG_MSK 0x0008 | |
301 | ||
302 | /* PLA_PHYAR */ | |
303 | #define PHYAR_FLAG 0x80000000 | |
304 | ||
305 | /* PLA_EEE_CR */ | |
306 | #define EEE_RX_EN 0x0001 | |
307 | #define EEE_TX_EN 0x0002 | |
308 | ||
43779f8d | 309 | /* PLA_BOOT_CTRL */ |
310 | #define AUTOLOAD_DONE 0x0002 | |
311 | ||
65bab84c | 312 | /* USB_USB2PHY */ |
313 | #define USB2PHY_SUSPEND 0x0001 | |
314 | #define USB2PHY_L1 0x0002 | |
315 | ||
316 | /* USB_SSPHYLINK2 */ | |
317 | #define pwd_dn_scale_mask 0x3ffe | |
318 | #define pwd_dn_scale(x) ((x) << 1) | |
319 | ||
320 | /* USB_CSR_DUMMY1 */ | |
321 | #define DYNAMIC_BURST 0x0001 | |
322 | ||
323 | /* USB_CSR_DUMMY2 */ | |
324 | #define EP4_FULL_FC 0x0001 | |
325 | ||
ac718b69 | 326 | /* USB_DEV_STAT */ |
327 | #define STAT_SPEED_MASK 0x0006 | |
328 | #define STAT_SPEED_HIGH 0x0000 | |
a3cc465d | 329 | #define STAT_SPEED_FULL 0x0002 |
ac718b69 | 330 | |
331 | /* USB_TX_AGG */ | |
332 | #define TX_AGG_MAX_THRESHOLD 0x03 | |
333 | ||
334 | /* USB_RX_BUF_TH */ | |
43779f8d | 335 | #define RX_THR_SUPPER 0x0c350180 |
8e1f51bd | 336 | #define RX_THR_HIGH 0x7a120180 |
43779f8d | 337 | #define RX_THR_SLOW 0xffff0180 |
ac718b69 | 338 | |
339 | /* USB_TX_DMA */ | |
340 | #define TEST_MODE_DISABLE 0x00000001 | |
341 | #define TX_SIZE_ADJUST1 0x00000100 | |
342 | ||
93fe9b18 | 343 | /* USB_BMU_RESET */ |
344 | #define BMU_RESET_EP_IN 0x01 | |
345 | #define BMU_RESET_EP_OUT 0x02 | |
346 | ||
ac718b69 | 347 | /* USB_UPS_CTRL */ |
348 | #define POWER_CUT 0x0100 | |
349 | ||
350 | /* USB_PM_CTRL_STATUS */ | |
8e1f51bd | 351 | #define RESUME_INDICATE 0x0001 |
ac718b69 | 352 | |
353 | /* USB_USB_CTRL */ | |
354 | #define RX_AGG_DISABLE 0x0010 | |
e90fba8d | 355 | #define RX_ZERO_EN 0x0080 |
ac718b69 | 356 | |
43779f8d | 357 | /* USB_U2P3_CTRL */ |
358 | #define U2P3_ENABLE 0x0001 | |
359 | ||
360 | /* USB_POWER_CUT */ | |
361 | #define PWR_EN 0x0001 | |
362 | #define PHASE2_EN 0x0008 | |
363 | ||
364 | /* USB_MISC_0 */ | |
365 | #define PCUT_STATUS 0x0001 | |
366 | ||
464ec10a | 367 | /* USB_RX_EARLY_TIMEOUT */ |
368 | #define COALESCE_SUPER 85000U | |
369 | #define COALESCE_HIGH 250000U | |
370 | #define COALESCE_SLOW 524280U | |
43779f8d | 371 | |
372 | /* USB_WDT11_CTRL */ | |
373 | #define TIMER11_EN 0x0001 | |
374 | ||
375 | /* USB_LPM_CTRL */ | |
65bab84c | 376 | /* bit 4 ~ 5: fifo empty boundary */ |
377 | #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */ | |
378 | /* bit 2 ~ 3: LMP timer */ | |
43779f8d | 379 | #define LPM_TIMER_MASK 0x0c |
380 | #define LPM_TIMER_500MS 0x04 /* 500 ms */ | |
381 | #define LPM_TIMER_500US 0x0c /* 500 us */ | |
65bab84c | 382 | #define ROK_EXIT_LPM 0x02 |
43779f8d | 383 | |
384 | /* USB_AFE_CTRL2 */ | |
385 | #define SEN_VAL_MASK 0xf800 | |
386 | #define SEN_VAL_NORMAL 0xa000 | |
387 | #define SEL_RXIDLE 0x0100 | |
388 | ||
ac718b69 | 389 | /* OCP_ALDPS_CONFIG */ |
390 | #define ENPWRSAVE 0x8000 | |
391 | #define ENPDNPS 0x0200 | |
392 | #define LINKENA 0x0100 | |
393 | #define DIS_SDSAVE 0x0010 | |
394 | ||
43779f8d | 395 | /* OCP_PHY_STATUS */ |
396 | #define PHY_STAT_MASK 0x0007 | |
c564b871 | 397 | #define PHY_STAT_EXT_INIT 2 |
43779f8d | 398 | #define PHY_STAT_LAN_ON 3 |
399 | #define PHY_STAT_PWRDN 5 | |
400 | ||
401 | /* OCP_POWER_CFG */ | |
402 | #define EEE_CLKDIV_EN 0x8000 | |
403 | #define EN_ALDPS 0x0004 | |
404 | #define EN_10M_PLLOFF 0x0001 | |
405 | ||
ac718b69 | 406 | /* OCP_EEE_CONFIG1 */ |
407 | #define RG_TXLPI_MSK_HFDUP 0x8000 | |
408 | #define RG_MATCLR_EN 0x4000 | |
409 | #define EEE_10_CAP 0x2000 | |
410 | #define EEE_NWAY_EN 0x1000 | |
411 | #define TX_QUIET_EN 0x0200 | |
412 | #define RX_QUIET_EN 0x0100 | |
d24f6134 | 413 | #define sd_rise_time_mask 0x0070 |
4c4a6b1b | 414 | #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */ |
ac718b69 | 415 | #define RG_RXLPI_MSK_HFDUP 0x0008 |
416 | #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */ | |
417 | ||
418 | /* OCP_EEE_CONFIG2 */ | |
419 | #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */ | |
420 | #define RG_DACQUIET_EN 0x0400 | |
421 | #define RG_LDVQUIET_EN 0x0200 | |
422 | #define RG_CKRSEL 0x0020 | |
423 | #define RG_EEEPRG_EN 0x0010 | |
424 | ||
425 | /* OCP_EEE_CONFIG3 */ | |
d24f6134 | 426 | #define fast_snr_mask 0xff80 |
4c4a6b1b | 427 | #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */ |
ac718b69 | 428 | #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */ |
429 | #define MSK_PH 0x0006 /* bit 0 ~ 3 */ | |
430 | ||
431 | /* OCP_EEE_AR */ | |
432 | /* bit[15:14] function */ | |
433 | #define FUN_ADDR 0x0000 | |
434 | #define FUN_DATA 0x4000 | |
435 | /* bit[4:0] device addr */ | |
ac718b69 | 436 | |
43779f8d | 437 | /* OCP_EEE_CFG */ |
438 | #define CTAP_SHORT_EN 0x0040 | |
439 | #define EEE10_EN 0x0010 | |
440 | ||
441 | /* OCP_DOWN_SPEED */ | |
442 | #define EN_10M_BGOFF 0x0080 | |
443 | ||
2dd49e0f | 444 | /* OCP_PHY_STATE */ |
445 | #define TXDIS_STATE 0x01 | |
446 | #define ABD_STATE 0x02 | |
447 | ||
43779f8d | 448 | /* OCP_ADC_CFG */ |
449 | #define CKADSEL_L 0x0100 | |
450 | #define ADC_EN 0x0080 | |
451 | #define EN_EMI_L 0x0040 | |
452 | ||
453 | /* SRAM_LPF_CFG */ | |
454 | #define LPF_AUTO_TUNE 0x8000 | |
455 | ||
456 | /* SRAM_10M_AMP1 */ | |
457 | #define GDAC_IB_UPALL 0x0008 | |
458 | ||
459 | /* SRAM_10M_AMP2 */ | |
460 | #define AMP_DN 0x0200 | |
461 | ||
462 | /* SRAM_IMPEDANCE */ | |
463 | #define RX_DRIVING_MASK 0x6000 | |
464 | ||
34ee32c9 ML |
465 | /* MAC PASSTHRU */ |
466 | #define AD_MASK 0xfee0 | |
467 | #define EFUSE 0xcfdb | |
468 | #define PASS_THRU_MASK 0x1 | |
469 | ||
ac718b69 | 470 | enum rtl_register_content { |
43779f8d | 471 | _1000bps = 0x10, |
ac718b69 | 472 | _100bps = 0x08, |
473 | _10bps = 0x04, | |
474 | LINK_STATUS = 0x02, | |
475 | FULL_DUP = 0x01, | |
476 | }; | |
477 | ||
1764bcd9 | 478 | #define RTL8152_MAX_TX 4 |
ebc2ec48 | 479 | #define RTL8152_MAX_RX 10 |
40a82917 | 480 | #define INTBUFSIZE 2 |
8e1f51bd | 481 | #define CRC_SIZE 4 |
482 | #define TX_ALIGN 4 | |
483 | #define RX_ALIGN 8 | |
40a82917 | 484 | |
485 | #define INTR_LINK 0x0004 | |
ebc2ec48 | 486 | |
ac718b69 | 487 | #define RTL8152_REQT_READ 0xc0 |
488 | #define RTL8152_REQT_WRITE 0x40 | |
489 | #define RTL8152_REQ_GET_REGS 0x05 | |
490 | #define RTL8152_REQ_SET_REGS 0x05 | |
491 | ||
492 | #define BYTE_EN_DWORD 0xff | |
493 | #define BYTE_EN_WORD 0x33 | |
494 | #define BYTE_EN_BYTE 0x11 | |
495 | #define BYTE_EN_SIX_BYTES 0x3f | |
496 | #define BYTE_EN_START_MASK 0x0f | |
497 | #define BYTE_EN_END_MASK 0xf0 | |
498 | ||
69b4b7a4 | 499 | #define RTL8153_MAX_PACKET 9216 /* 9K */ |
500 | #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN) | |
ac718b69 | 501 | #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN) |
69b4b7a4 | 502 | #define RTL8153_RMS RTL8153_MAX_PACKET |
b8125404 | 503 | #define RTL8152_TX_TIMEOUT (5 * HZ) |
d823ab68 | 504 | #define RTL8152_NAPI_WEIGHT 64 |
b20cb60e | 505 | #define rx_reserved_size(x) ((x) + VLAN_ETH_HLEN + CRC_SIZE + \ |
506 | sizeof(struct rx_desc) + RX_ALIGN) | |
ac718b69 | 507 | |
508 | /* rtl8152 flags */ | |
509 | enum rtl8152_flags { | |
510 | RTL8152_UNPLUG = 0, | |
ac718b69 | 511 | RTL8152_SET_RX_MODE, |
40a82917 | 512 | WORK_ENABLE, |
513 | RTL8152_LINK_CHG, | |
9a4be1bd | 514 | SELECTIVE_SUSPEND, |
aa66a5f1 | 515 | PHY_RESET, |
d823ab68 | 516 | SCHEDULE_NAPI, |
ac718b69 | 517 | }; |
518 | ||
519 | /* Define these values to match your device */ | |
520 | #define VENDOR_ID_REALTEK 0x0bda | |
d5b07ccc | 521 | #define VENDOR_ID_MICROSOFT 0x045e |
43779f8d | 522 | #define VENDOR_ID_SAMSUNG 0x04e8 |
347eec34 | 523 | #define VENDOR_ID_LENOVO 0x17ef |
d065c3c1 | 524 | #define VENDOR_ID_NVIDIA 0x0955 |
ac718b69 | 525 | |
526 | #define MCU_TYPE_PLA 0x0100 | |
527 | #define MCU_TYPE_USB 0x0000 | |
528 | ||
4f1d4d54 | 529 | struct tally_counter { |
530 | __le64 tx_packets; | |
531 | __le64 rx_packets; | |
532 | __le64 tx_errors; | |
533 | __le32 rx_errors; | |
534 | __le16 rx_missed; | |
535 | __le16 align_errors; | |
536 | __le32 tx_one_collision; | |
537 | __le32 tx_multi_collision; | |
538 | __le64 rx_unicast; | |
539 | __le64 rx_broadcast; | |
540 | __le32 rx_multicast; | |
541 | __le16 tx_aborted; | |
f37119c5 | 542 | __le16 tx_underrun; |
4f1d4d54 | 543 | }; |
544 | ||
ac718b69 | 545 | struct rx_desc { |
500b6d7e | 546 | __le32 opts1; |
ac718b69 | 547 | #define RX_LEN_MASK 0x7fff |
565cab0a | 548 | |
500b6d7e | 549 | __le32 opts2; |
f5aaaa6d | 550 | #define RD_UDP_CS BIT(23) |
551 | #define RD_TCP_CS BIT(22) | |
552 | #define RD_IPV6_CS BIT(20) | |
553 | #define RD_IPV4_CS BIT(19) | |
565cab0a | 554 | |
500b6d7e | 555 | __le32 opts3; |
f5aaaa6d | 556 | #define IPF BIT(23) /* IP checksum fail */ |
557 | #define UDPF BIT(22) /* UDP checksum fail */ | |
558 | #define TCPF BIT(21) /* TCP checksum fail */ | |
559 | #define RX_VLAN_TAG BIT(16) | |
565cab0a | 560 | |
500b6d7e | 561 | __le32 opts4; |
562 | __le32 opts5; | |
563 | __le32 opts6; | |
ac718b69 | 564 | }; |
565 | ||
566 | struct tx_desc { | |
500b6d7e | 567 | __le32 opts1; |
f5aaaa6d | 568 | #define TX_FS BIT(31) /* First segment of a packet */ |
569 | #define TX_LS BIT(30) /* Final segment of a packet */ | |
570 | #define GTSENDV4 BIT(28) | |
571 | #define GTSENDV6 BIT(27) | |
60c89071 | 572 | #define GTTCPHO_SHIFT 18 |
6128d1bb | 573 | #define GTTCPHO_MAX 0x7fU |
60c89071 | 574 | #define TX_LEN_MAX 0x3ffffU |
5bd23881 | 575 | |
500b6d7e | 576 | __le32 opts2; |
f5aaaa6d | 577 | #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */ |
578 | #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */ | |
579 | #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */ | |
580 | #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */ | |
60c89071 | 581 | #define MSS_SHIFT 17 |
582 | #define MSS_MAX 0x7ffU | |
583 | #define TCPHO_SHIFT 17 | |
6128d1bb | 584 | #define TCPHO_MAX 0x7ffU |
f5aaaa6d | 585 | #define TX_VLAN_TAG BIT(16) |
ac718b69 | 586 | }; |
587 | ||
dff4e8ad | 588 | struct r8152; |
589 | ||
ebc2ec48 | 590 | struct rx_agg { |
591 | struct list_head list; | |
592 | struct urb *urb; | |
dff4e8ad | 593 | struct r8152 *context; |
ebc2ec48 | 594 | void *buffer; |
595 | void *head; | |
596 | }; | |
597 | ||
598 | struct tx_agg { | |
599 | struct list_head list; | |
600 | struct urb *urb; | |
dff4e8ad | 601 | struct r8152 *context; |
ebc2ec48 | 602 | void *buffer; |
603 | void *head; | |
604 | u32 skb_num; | |
605 | u32 skb_len; | |
606 | }; | |
607 | ||
ac718b69 | 608 | struct r8152 { |
609 | unsigned long flags; | |
610 | struct usb_device *udev; | |
d823ab68 | 611 | struct napi_struct napi; |
40a82917 | 612 | struct usb_interface *intf; |
ac718b69 | 613 | struct net_device *netdev; |
40a82917 | 614 | struct urb *intr_urb; |
ebc2ec48 | 615 | struct tx_agg tx_info[RTL8152_MAX_TX]; |
616 | struct rx_agg rx_info[RTL8152_MAX_RX]; | |
617 | struct list_head rx_done, tx_free; | |
d823ab68 | 618 | struct sk_buff_head tx_queue, rx_queue; |
ebc2ec48 | 619 | spinlock_t rx_lock, tx_lock; |
a028a9e0 | 620 | struct delayed_work schedule, hw_phy_work; |
ac718b69 | 621 | struct mii_if_info mii; |
b5403273 | 622 | struct mutex control; /* use for hw setting */ |
5ee3c60c | 623 | #ifdef CONFIG_PM_SLEEP |
624 | struct notifier_block pm_notifier; | |
625 | #endif | |
c81229c9 | 626 | |
627 | struct rtl_ops { | |
628 | void (*init)(struct r8152 *); | |
629 | int (*enable)(struct r8152 *); | |
630 | void (*disable)(struct r8152 *); | |
7e9da481 | 631 | void (*up)(struct r8152 *); |
c81229c9 | 632 | void (*down)(struct r8152 *); |
633 | void (*unload)(struct r8152 *); | |
df35d283 | 634 | int (*eee_get)(struct r8152 *, struct ethtool_eee *); |
635 | int (*eee_set)(struct r8152 *, struct ethtool_eee *); | |
2dd49e0f | 636 | bool (*in_nway)(struct r8152 *); |
a028a9e0 | 637 | void (*hw_phy_cfg)(struct r8152 *); |
2609af19 | 638 | void (*autosuspend_en)(struct r8152 *tp, bool enable); |
c81229c9 | 639 | } rtl_ops; |
640 | ||
40a82917 | 641 | int intr_interval; |
21ff2e89 | 642 | u32 saved_wolopts; |
ac718b69 | 643 | u32 msg_enable; |
dd1b119c | 644 | u32 tx_qlen; |
464ec10a | 645 | u32 coalesce; |
ac718b69 | 646 | u16 ocp_base; |
aa7e26b6 | 647 | u16 speed; |
40a82917 | 648 | u8 *intr_buff; |
ac718b69 | 649 | u8 version; |
aa7e26b6 | 650 | u8 duplex; |
651 | u8 autoneg; | |
ac718b69 | 652 | }; |
653 | ||
654 | enum rtl_version { | |
655 | RTL_VER_UNKNOWN = 0, | |
656 | RTL_VER_01, | |
43779f8d | 657 | RTL_VER_02, |
658 | RTL_VER_03, | |
659 | RTL_VER_04, | |
660 | RTL_VER_05, | |
fb02eb4a | 661 | RTL_VER_06, |
43779f8d | 662 | RTL_VER_MAX |
ac718b69 | 663 | }; |
664 | ||
60c89071 | 665 | enum tx_csum_stat { |
666 | TX_CSUM_SUCCESS = 0, | |
667 | TX_CSUM_TSO, | |
668 | TX_CSUM_NONE | |
669 | }; | |
670 | ||
ac718b69 | 671 | /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). |
672 | * The RTL chips use a 64 element hash table based on the Ethernet CRC. | |
673 | */ | |
674 | static const int multicast_filter_limit = 32; | |
52aec126 | 675 | static unsigned int agg_buf_sz = 16384; |
ac718b69 | 676 | |
52aec126 | 677 | #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \ |
60c89071 | 678 | VLAN_ETH_HLEN - VLAN_HLEN) |
679 | ||
ac718b69 | 680 | static |
681 | int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) | |
682 | { | |
31787f53 | 683 | int ret; |
684 | void *tmp; | |
685 | ||
686 | tmp = kmalloc(size, GFP_KERNEL); | |
687 | if (!tmp) | |
688 | return -ENOMEM; | |
689 | ||
690 | ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0), | |
b209af99 | 691 | RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, |
692 | value, index, tmp, size, 500); | |
31787f53 | 693 | |
694 | memcpy(data, tmp, size); | |
695 | kfree(tmp); | |
696 | ||
697 | return ret; | |
ac718b69 | 698 | } |
699 | ||
700 | static | |
701 | int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) | |
702 | { | |
31787f53 | 703 | int ret; |
704 | void *tmp; | |
705 | ||
c4438f03 | 706 | tmp = kmemdup(data, size, GFP_KERNEL); |
31787f53 | 707 | if (!tmp) |
708 | return -ENOMEM; | |
709 | ||
31787f53 | 710 | ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0), |
b209af99 | 711 | RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE, |
712 | value, index, tmp, size, 500); | |
31787f53 | 713 | |
714 | kfree(tmp); | |
db8515ef | 715 | |
31787f53 | 716 | return ret; |
ac718b69 | 717 | } |
718 | ||
719 | static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size, | |
b209af99 | 720 | void *data, u16 type) |
ac718b69 | 721 | { |
45f4a19f | 722 | u16 limit = 64; |
723 | int ret = 0; | |
ac718b69 | 724 | |
725 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
726 | return -ENODEV; | |
727 | ||
728 | /* both size and indix must be 4 bytes align */ | |
729 | if ((size & 3) || !size || (index & 3) || !data) | |
730 | return -EPERM; | |
731 | ||
732 | if ((u32)index + (u32)size > 0xffff) | |
733 | return -EPERM; | |
734 | ||
735 | while (size) { | |
736 | if (size > limit) { | |
737 | ret = get_registers(tp, index, type, limit, data); | |
738 | if (ret < 0) | |
739 | break; | |
740 | ||
741 | index += limit; | |
742 | data += limit; | |
743 | size -= limit; | |
744 | } else { | |
745 | ret = get_registers(tp, index, type, size, data); | |
746 | if (ret < 0) | |
747 | break; | |
748 | ||
749 | index += size; | |
750 | data += size; | |
751 | size = 0; | |
752 | break; | |
753 | } | |
754 | } | |
755 | ||
67610496 | 756 | if (ret == -ENODEV) |
757 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
758 | ||
ac718b69 | 759 | return ret; |
760 | } | |
761 | ||
762 | static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, | |
b209af99 | 763 | u16 size, void *data, u16 type) |
ac718b69 | 764 | { |
45f4a19f | 765 | int ret; |
766 | u16 byteen_start, byteen_end, byen; | |
767 | u16 limit = 512; | |
ac718b69 | 768 | |
769 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
770 | return -ENODEV; | |
771 | ||
772 | /* both size and indix must be 4 bytes align */ | |
773 | if ((size & 3) || !size || (index & 3) || !data) | |
774 | return -EPERM; | |
775 | ||
776 | if ((u32)index + (u32)size > 0xffff) | |
777 | return -EPERM; | |
778 | ||
779 | byteen_start = byteen & BYTE_EN_START_MASK; | |
780 | byteen_end = byteen & BYTE_EN_END_MASK; | |
781 | ||
782 | byen = byteen_start | (byteen_start << 4); | |
783 | ret = set_registers(tp, index, type | byen, 4, data); | |
784 | if (ret < 0) | |
785 | goto error1; | |
786 | ||
787 | index += 4; | |
788 | data += 4; | |
789 | size -= 4; | |
790 | ||
791 | if (size) { | |
792 | size -= 4; | |
793 | ||
794 | while (size) { | |
795 | if (size > limit) { | |
796 | ret = set_registers(tp, index, | |
b209af99 | 797 | type | BYTE_EN_DWORD, |
798 | limit, data); | |
ac718b69 | 799 | if (ret < 0) |
800 | goto error1; | |
801 | ||
802 | index += limit; | |
803 | data += limit; | |
804 | size -= limit; | |
805 | } else { | |
806 | ret = set_registers(tp, index, | |
b209af99 | 807 | type | BYTE_EN_DWORD, |
808 | size, data); | |
ac718b69 | 809 | if (ret < 0) |
810 | goto error1; | |
811 | ||
812 | index += size; | |
813 | data += size; | |
814 | size = 0; | |
815 | break; | |
816 | } | |
817 | } | |
818 | ||
819 | byen = byteen_end | (byteen_end >> 4); | |
820 | ret = set_registers(tp, index, type | byen, 4, data); | |
821 | if (ret < 0) | |
822 | goto error1; | |
823 | } | |
824 | ||
825 | error1: | |
67610496 | 826 | if (ret == -ENODEV) |
827 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
828 | ||
ac718b69 | 829 | return ret; |
830 | } | |
831 | ||
832 | static inline | |
833 | int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) | |
834 | { | |
835 | return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA); | |
836 | } | |
837 | ||
838 | static inline | |
839 | int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) | |
840 | { | |
841 | return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA); | |
842 | } | |
843 | ||
ac718b69 | 844 | static inline |
845 | int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) | |
846 | { | |
847 | return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB); | |
848 | } | |
849 | ||
850 | static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index) | |
851 | { | |
c8826de8 | 852 | __le32 data; |
ac718b69 | 853 | |
c8826de8 | 854 | generic_ocp_read(tp, index, sizeof(data), &data, type); |
ac718b69 | 855 | |
856 | return __le32_to_cpu(data); | |
857 | } | |
858 | ||
859 | static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data) | |
860 | { | |
c8826de8 | 861 | __le32 tmp = __cpu_to_le32(data); |
862 | ||
863 | generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type); | |
ac718b69 | 864 | } |
865 | ||
866 | static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index) | |
867 | { | |
868 | u32 data; | |
c8826de8 | 869 | __le32 tmp; |
ac718b69 | 870 | u8 shift = index & 2; |
871 | ||
872 | index &= ~3; | |
873 | ||
c8826de8 | 874 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 875 | |
c8826de8 | 876 | data = __le32_to_cpu(tmp); |
ac718b69 | 877 | data >>= (shift * 8); |
878 | data &= 0xffff; | |
879 | ||
880 | return (u16)data; | |
881 | } | |
882 | ||
883 | static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data) | |
884 | { | |
c8826de8 | 885 | u32 mask = 0xffff; |
886 | __le32 tmp; | |
ac718b69 | 887 | u16 byen = BYTE_EN_WORD; |
888 | u8 shift = index & 2; | |
889 | ||
890 | data &= mask; | |
891 | ||
892 | if (index & 2) { | |
893 | byen <<= shift; | |
894 | mask <<= (shift * 8); | |
895 | data <<= (shift * 8); | |
896 | index &= ~3; | |
897 | } | |
898 | ||
c8826de8 | 899 | tmp = __cpu_to_le32(data); |
ac718b69 | 900 | |
c8826de8 | 901 | generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); |
ac718b69 | 902 | } |
903 | ||
904 | static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index) | |
905 | { | |
906 | u32 data; | |
c8826de8 | 907 | __le32 tmp; |
ac718b69 | 908 | u8 shift = index & 3; |
909 | ||
910 | index &= ~3; | |
911 | ||
c8826de8 | 912 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 913 | |
c8826de8 | 914 | data = __le32_to_cpu(tmp); |
ac718b69 | 915 | data >>= (shift * 8); |
916 | data &= 0xff; | |
917 | ||
918 | return (u8)data; | |
919 | } | |
920 | ||
921 | static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data) | |
922 | { | |
c8826de8 | 923 | u32 mask = 0xff; |
924 | __le32 tmp; | |
ac718b69 | 925 | u16 byen = BYTE_EN_BYTE; |
926 | u8 shift = index & 3; | |
927 | ||
928 | data &= mask; | |
929 | ||
930 | if (index & 3) { | |
931 | byen <<= shift; | |
932 | mask <<= (shift * 8); | |
933 | data <<= (shift * 8); | |
934 | index &= ~3; | |
935 | } | |
936 | ||
c8826de8 | 937 | tmp = __cpu_to_le32(data); |
ac718b69 | 938 | |
c8826de8 | 939 | generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); |
ac718b69 | 940 | } |
941 | ||
ac244d3e | 942 | static u16 ocp_reg_read(struct r8152 *tp, u16 addr) |
e3fe0b1a | 943 | { |
944 | u16 ocp_base, ocp_index; | |
945 | ||
946 | ocp_base = addr & 0xf000; | |
947 | if (ocp_base != tp->ocp_base) { | |
948 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); | |
949 | tp->ocp_base = ocp_base; | |
950 | } | |
951 | ||
952 | ocp_index = (addr & 0x0fff) | 0xb000; | |
ac244d3e | 953 | return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index); |
e3fe0b1a | 954 | } |
955 | ||
ac244d3e | 956 | static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) |
ac718b69 | 957 | { |
ac244d3e | 958 | u16 ocp_base, ocp_index; |
ac718b69 | 959 | |
ac244d3e | 960 | ocp_base = addr & 0xf000; |
961 | if (ocp_base != tp->ocp_base) { | |
962 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); | |
963 | tp->ocp_base = ocp_base; | |
ac718b69 | 964 | } |
ac244d3e | 965 | |
966 | ocp_index = (addr & 0x0fff) | 0xb000; | |
967 | ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data); | |
ac718b69 | 968 | } |
969 | ||
ac244d3e | 970 | static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value) |
ac718b69 | 971 | { |
ac244d3e | 972 | ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value); |
973 | } | |
ac718b69 | 974 | |
ac244d3e | 975 | static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr) |
976 | { | |
977 | return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2); | |
ac718b69 | 978 | } |
979 | ||
43779f8d | 980 | static void sram_write(struct r8152 *tp, u16 addr, u16 data) |
981 | { | |
982 | ocp_reg_write(tp, OCP_SRAM_ADDR, addr); | |
983 | ocp_reg_write(tp, OCP_SRAM_DATA, data); | |
984 | } | |
985 | ||
ac718b69 | 986 | static int read_mii_word(struct net_device *netdev, int phy_id, int reg) |
987 | { | |
988 | struct r8152 *tp = netdev_priv(netdev); | |
9a4be1bd | 989 | int ret; |
ac718b69 | 990 | |
6871438c | 991 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
992 | return -ENODEV; | |
993 | ||
ac718b69 | 994 | if (phy_id != R8152_PHY_ID) |
995 | return -EINVAL; | |
996 | ||
9a4be1bd | 997 | ret = r8152_mdio_read(tp, reg); |
998 | ||
9a4be1bd | 999 | return ret; |
ac718b69 | 1000 | } |
1001 | ||
1002 | static | |
1003 | void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val) | |
1004 | { | |
1005 | struct r8152 *tp = netdev_priv(netdev); | |
1006 | ||
6871438c | 1007 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
1008 | return; | |
1009 | ||
ac718b69 | 1010 | if (phy_id != R8152_PHY_ID) |
1011 | return; | |
1012 | ||
1013 | r8152_mdio_write(tp, reg, val); | |
1014 | } | |
1015 | ||
b209af99 | 1016 | static int |
1017 | r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags); | |
ebc2ec48 | 1018 | |
8ba789ab | 1019 | static int rtl8152_set_mac_address(struct net_device *netdev, void *p) |
1020 | { | |
1021 | struct r8152 *tp = netdev_priv(netdev); | |
1022 | struct sockaddr *addr = p; | |
ea6a7112 | 1023 | int ret = -EADDRNOTAVAIL; |
8ba789ab | 1024 | |
1025 | if (!is_valid_ether_addr(addr->sa_data)) | |
ea6a7112 | 1026 | goto out1; |
1027 | ||
1028 | ret = usb_autopm_get_interface(tp->intf); | |
1029 | if (ret < 0) | |
1030 | goto out1; | |
8ba789ab | 1031 | |
b5403273 | 1032 | mutex_lock(&tp->control); |
1033 | ||
8ba789ab | 1034 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); |
1035 | ||
1036 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
1037 | pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data); | |
1038 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
1039 | ||
b5403273 | 1040 | mutex_unlock(&tp->control); |
1041 | ||
ea6a7112 | 1042 | usb_autopm_put_interface(tp->intf); |
1043 | out1: | |
1044 | return ret; | |
8ba789ab | 1045 | } |
1046 | ||
34ee32c9 ML |
1047 | /* Devices containing RTL8153-AD can support a persistent |
1048 | * host system provided MAC address. | |
1049 | * Examples of this are Dell TB15 and Dell WD15 docks | |
1050 | */ | |
1051 | static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa) | |
1052 | { | |
1053 | acpi_status status; | |
1054 | struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; | |
1055 | union acpi_object *obj; | |
1056 | int ret = -EINVAL; | |
1057 | u32 ocp_data; | |
1058 | unsigned char buf[6]; | |
1059 | ||
1060 | /* test for -AD variant of RTL8153 */ | |
1061 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); | |
1062 | if ((ocp_data & AD_MASK) != 0x1000) | |
1063 | return -ENODEV; | |
1064 | ||
1065 | /* test for MAC address pass-through bit */ | |
1066 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE); | |
1067 | if ((ocp_data & PASS_THRU_MASK) != 1) | |
1068 | return -ENODEV; | |
1069 | ||
1070 | /* returns _AUXMAC_#AABBCCDDEEFF# */ | |
1071 | status = acpi_evaluate_object(NULL, "\\_SB.AMAC", NULL, &buffer); | |
1072 | obj = (union acpi_object *)buffer.pointer; | |
1073 | if (!ACPI_SUCCESS(status)) | |
1074 | return -ENODEV; | |
1075 | if (obj->type != ACPI_TYPE_BUFFER || obj->string.length != 0x17) { | |
1076 | netif_warn(tp, probe, tp->netdev, | |
53700f0c | 1077 | "Invalid buffer for pass-thru MAC addr: (%d, %d)\n", |
34ee32c9 ML |
1078 | obj->type, obj->string.length); |
1079 | goto amacout; | |
1080 | } | |
1081 | if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 || | |
1082 | strncmp(obj->string.pointer + 0x15, "#", 1) != 0) { | |
1083 | netif_warn(tp, probe, tp->netdev, | |
1084 | "Invalid header when reading pass-thru MAC addr\n"); | |
1085 | goto amacout; | |
1086 | } | |
1087 | ret = hex2bin(buf, obj->string.pointer + 9, 6); | |
1088 | if (!(ret == 0 && is_valid_ether_addr(buf))) { | |
1089 | netif_warn(tp, probe, tp->netdev, | |
53700f0c | 1090 | "Invalid MAC for pass-thru MAC addr: %d, %pM\n", |
1091 | ret, buf); | |
34ee32c9 ML |
1092 | ret = -EINVAL; |
1093 | goto amacout; | |
1094 | } | |
1095 | memcpy(sa->sa_data, buf, 6); | |
1096 | ether_addr_copy(tp->netdev->dev_addr, sa->sa_data); | |
1097 | netif_info(tp, probe, tp->netdev, | |
1098 | "Using pass-thru MAC addr %pM\n", sa->sa_data); | |
1099 | ||
1100 | amacout: | |
1101 | kfree(obj); | |
1102 | return ret; | |
1103 | } | |
1104 | ||
179bb6d7 | 1105 | static int set_ethernet_addr(struct r8152 *tp) |
ac718b69 | 1106 | { |
1107 | struct net_device *dev = tp->netdev; | |
179bb6d7 | 1108 | struct sockaddr sa; |
8a91c824 | 1109 | int ret; |
ac718b69 | 1110 | |
53700f0c | 1111 | if (tp->version == RTL_VER_01) { |
179bb6d7 | 1112 | ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data); |
53700f0c | 1113 | } else { |
34ee32c9 ML |
1114 | /* if this is not an RTL8153-AD, no eFuse mac pass thru set, |
1115 | * or system doesn't provide valid _SB.AMAC this will be | |
1116 | * be expected to non-zero | |
1117 | */ | |
1118 | ret = vendor_mac_passthru_addr_read(tp, &sa); | |
1119 | if (ret < 0) | |
1120 | ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data); | |
1121 | } | |
8a91c824 | 1122 | |
1123 | if (ret < 0) { | |
179bb6d7 | 1124 | netif_err(tp, probe, dev, "Get ether addr fail\n"); |
1125 | } else if (!is_valid_ether_addr(sa.sa_data)) { | |
1126 | netif_err(tp, probe, dev, "Invalid ether addr %pM\n", | |
1127 | sa.sa_data); | |
1128 | eth_hw_addr_random(dev); | |
1129 | ether_addr_copy(sa.sa_data, dev->dev_addr); | |
1130 | ret = rtl8152_set_mac_address(dev, &sa); | |
1131 | netif_info(tp, probe, dev, "Random ether addr %pM\n", | |
1132 | sa.sa_data); | |
8a91c824 | 1133 | } else { |
179bb6d7 | 1134 | if (tp->version == RTL_VER_01) |
1135 | ether_addr_copy(dev->dev_addr, sa.sa_data); | |
1136 | else | |
1137 | ret = rtl8152_set_mac_address(dev, &sa); | |
ac718b69 | 1138 | } |
179bb6d7 | 1139 | |
1140 | return ret; | |
ac718b69 | 1141 | } |
1142 | ||
ac718b69 | 1143 | static void read_bulk_callback(struct urb *urb) |
1144 | { | |
ac718b69 | 1145 | struct net_device *netdev; |
ac718b69 | 1146 | int status = urb->status; |
ebc2ec48 | 1147 | struct rx_agg *agg; |
1148 | struct r8152 *tp; | |
ac718b69 | 1149 | |
ebc2ec48 | 1150 | agg = urb->context; |
1151 | if (!agg) | |
1152 | return; | |
1153 | ||
1154 | tp = agg->context; | |
ac718b69 | 1155 | if (!tp) |
1156 | return; | |
ebc2ec48 | 1157 | |
ac718b69 | 1158 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
1159 | return; | |
ebc2ec48 | 1160 | |
1161 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
1162 | return; | |
1163 | ||
ac718b69 | 1164 | netdev = tp->netdev; |
7559fb2f | 1165 | |
1166 | /* When link down, the driver would cancel all bulks. */ | |
1167 | /* This avoid the re-submitting bulk */ | |
ebc2ec48 | 1168 | if (!netif_carrier_ok(netdev)) |
ac718b69 | 1169 | return; |
1170 | ||
9a4be1bd | 1171 | usb_mark_last_busy(tp->udev); |
1172 | ||
ac718b69 | 1173 | switch (status) { |
1174 | case 0: | |
ebc2ec48 | 1175 | if (urb->actual_length < ETH_ZLEN) |
1176 | break; | |
1177 | ||
2685d410 | 1178 | spin_lock(&tp->rx_lock); |
ebc2ec48 | 1179 | list_add_tail(&agg->list, &tp->rx_done); |
2685d410 | 1180 | spin_unlock(&tp->rx_lock); |
d823ab68 | 1181 | napi_schedule(&tp->napi); |
ebc2ec48 | 1182 | return; |
ac718b69 | 1183 | case -ESHUTDOWN: |
1184 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
1185 | netif_device_detach(tp->netdev); | |
ebc2ec48 | 1186 | return; |
ac718b69 | 1187 | case -ENOENT: |
1188 | return; /* the urb is in unlink state */ | |
1189 | case -ETIME: | |
4a8deae2 HW |
1190 | if (net_ratelimit()) |
1191 | netdev_warn(netdev, "maybe reset is needed?\n"); | |
ebc2ec48 | 1192 | break; |
ac718b69 | 1193 | default: |
4a8deae2 HW |
1194 | if (net_ratelimit()) |
1195 | netdev_warn(netdev, "Rx status %d\n", status); | |
ebc2ec48 | 1196 | break; |
ac718b69 | 1197 | } |
1198 | ||
a0fccd48 | 1199 | r8152_submit_rx(tp, agg, GFP_ATOMIC); |
ac718b69 | 1200 | } |
1201 | ||
ebc2ec48 | 1202 | static void write_bulk_callback(struct urb *urb) |
ac718b69 | 1203 | { |
ebc2ec48 | 1204 | struct net_device_stats *stats; |
d104eafa | 1205 | struct net_device *netdev; |
ebc2ec48 | 1206 | struct tx_agg *agg; |
ac718b69 | 1207 | struct r8152 *tp; |
ebc2ec48 | 1208 | int status = urb->status; |
ac718b69 | 1209 | |
ebc2ec48 | 1210 | agg = urb->context; |
1211 | if (!agg) | |
ac718b69 | 1212 | return; |
1213 | ||
ebc2ec48 | 1214 | tp = agg->context; |
1215 | if (!tp) | |
1216 | return; | |
1217 | ||
d104eafa | 1218 | netdev = tp->netdev; |
05e0f1aa | 1219 | stats = &netdev->stats; |
ebc2ec48 | 1220 | if (status) { |
4a8deae2 | 1221 | if (net_ratelimit()) |
d104eafa | 1222 | netdev_warn(netdev, "Tx status %d\n", status); |
ebc2ec48 | 1223 | stats->tx_errors += agg->skb_num; |
ac718b69 | 1224 | } else { |
ebc2ec48 | 1225 | stats->tx_packets += agg->skb_num; |
1226 | stats->tx_bytes += agg->skb_len; | |
ac718b69 | 1227 | } |
1228 | ||
2685d410 | 1229 | spin_lock(&tp->tx_lock); |
ebc2ec48 | 1230 | list_add_tail(&agg->list, &tp->tx_free); |
2685d410 | 1231 | spin_unlock(&tp->tx_lock); |
ebc2ec48 | 1232 | |
9a4be1bd | 1233 | usb_autopm_put_interface_async(tp->intf); |
1234 | ||
d104eafa | 1235 | if (!netif_carrier_ok(netdev)) |
ebc2ec48 | 1236 | return; |
1237 | ||
1238 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
1239 | return; | |
1240 | ||
1241 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
1242 | return; | |
1243 | ||
1244 | if (!skb_queue_empty(&tp->tx_queue)) | |
d823ab68 | 1245 | napi_schedule(&tp->napi); |
ac718b69 | 1246 | } |
1247 | ||
40a82917 | 1248 | static void intr_callback(struct urb *urb) |
1249 | { | |
1250 | struct r8152 *tp; | |
500b6d7e | 1251 | __le16 *d; |
40a82917 | 1252 | int status = urb->status; |
1253 | int res; | |
1254 | ||
1255 | tp = urb->context; | |
1256 | if (!tp) | |
1257 | return; | |
1258 | ||
1259 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
1260 | return; | |
1261 | ||
1262 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
1263 | return; | |
1264 | ||
1265 | switch (status) { | |
1266 | case 0: /* success */ | |
1267 | break; | |
1268 | case -ECONNRESET: /* unlink */ | |
1269 | case -ESHUTDOWN: | |
1270 | netif_device_detach(tp->netdev); | |
1271 | case -ENOENT: | |
d59c876d | 1272 | case -EPROTO: |
1273 | netif_info(tp, intr, tp->netdev, | |
1274 | "Stop submitting intr, status %d\n", status); | |
40a82917 | 1275 | return; |
1276 | case -EOVERFLOW: | |
1277 | netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n"); | |
1278 | goto resubmit; | |
1279 | /* -EPIPE: should clear the halt */ | |
1280 | default: | |
1281 | netif_info(tp, intr, tp->netdev, "intr status %d\n", status); | |
1282 | goto resubmit; | |
1283 | } | |
1284 | ||
1285 | d = urb->transfer_buffer; | |
1286 | if (INTR_LINK & __le16_to_cpu(d[0])) { | |
51d979fa | 1287 | if (!netif_carrier_ok(tp->netdev)) { |
40a82917 | 1288 | set_bit(RTL8152_LINK_CHG, &tp->flags); |
1289 | schedule_delayed_work(&tp->schedule, 0); | |
1290 | } | |
1291 | } else { | |
51d979fa | 1292 | if (netif_carrier_ok(tp->netdev)) { |
2f25abe6 | 1293 | netif_stop_queue(tp->netdev); |
40a82917 | 1294 | set_bit(RTL8152_LINK_CHG, &tp->flags); |
1295 | schedule_delayed_work(&tp->schedule, 0); | |
1296 | } | |
1297 | } | |
1298 | ||
1299 | resubmit: | |
1300 | res = usb_submit_urb(urb, GFP_ATOMIC); | |
67610496 | 1301 | if (res == -ENODEV) { |
1302 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
40a82917 | 1303 | netif_device_detach(tp->netdev); |
67610496 | 1304 | } else if (res) { |
40a82917 | 1305 | netif_err(tp, intr, tp->netdev, |
4a8deae2 | 1306 | "can't resubmit intr, status %d\n", res); |
67610496 | 1307 | } |
40a82917 | 1308 | } |
1309 | ||
ebc2ec48 | 1310 | static inline void *rx_agg_align(void *data) |
1311 | { | |
8e1f51bd | 1312 | return (void *)ALIGN((uintptr_t)data, RX_ALIGN); |
ebc2ec48 | 1313 | } |
1314 | ||
1315 | static inline void *tx_agg_align(void *data) | |
1316 | { | |
8e1f51bd | 1317 | return (void *)ALIGN((uintptr_t)data, TX_ALIGN); |
ebc2ec48 | 1318 | } |
1319 | ||
1320 | static void free_all_mem(struct r8152 *tp) | |
1321 | { | |
1322 | int i; | |
1323 | ||
1324 | for (i = 0; i < RTL8152_MAX_RX; i++) { | |
9629e3c0 | 1325 | usb_free_urb(tp->rx_info[i].urb); |
1326 | tp->rx_info[i].urb = NULL; | |
ebc2ec48 | 1327 | |
9629e3c0 | 1328 | kfree(tp->rx_info[i].buffer); |
1329 | tp->rx_info[i].buffer = NULL; | |
1330 | tp->rx_info[i].head = NULL; | |
ebc2ec48 | 1331 | } |
1332 | ||
1333 | for (i = 0; i < RTL8152_MAX_TX; i++) { | |
9629e3c0 | 1334 | usb_free_urb(tp->tx_info[i].urb); |
1335 | tp->tx_info[i].urb = NULL; | |
ebc2ec48 | 1336 | |
9629e3c0 | 1337 | kfree(tp->tx_info[i].buffer); |
1338 | tp->tx_info[i].buffer = NULL; | |
1339 | tp->tx_info[i].head = NULL; | |
ebc2ec48 | 1340 | } |
40a82917 | 1341 | |
9629e3c0 | 1342 | usb_free_urb(tp->intr_urb); |
1343 | tp->intr_urb = NULL; | |
40a82917 | 1344 | |
9629e3c0 | 1345 | kfree(tp->intr_buff); |
1346 | tp->intr_buff = NULL; | |
ebc2ec48 | 1347 | } |
1348 | ||
1349 | static int alloc_all_mem(struct r8152 *tp) | |
1350 | { | |
1351 | struct net_device *netdev = tp->netdev; | |
40a82917 | 1352 | struct usb_interface *intf = tp->intf; |
1353 | struct usb_host_interface *alt = intf->cur_altsetting; | |
1354 | struct usb_host_endpoint *ep_intr = alt->endpoint + 2; | |
ebc2ec48 | 1355 | struct urb *urb; |
1356 | int node, i; | |
1357 | u8 *buf; | |
1358 | ||
1359 | node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; | |
1360 | ||
1361 | spin_lock_init(&tp->rx_lock); | |
1362 | spin_lock_init(&tp->tx_lock); | |
ebc2ec48 | 1363 | INIT_LIST_HEAD(&tp->tx_free); |
98d068ab | 1364 | INIT_LIST_HEAD(&tp->rx_done); |
ebc2ec48 | 1365 | skb_queue_head_init(&tp->tx_queue); |
d823ab68 | 1366 | skb_queue_head_init(&tp->rx_queue); |
ebc2ec48 | 1367 | |
1368 | for (i = 0; i < RTL8152_MAX_RX; i++) { | |
52aec126 | 1369 | buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); |
ebc2ec48 | 1370 | if (!buf) |
1371 | goto err1; | |
1372 | ||
1373 | if (buf != rx_agg_align(buf)) { | |
1374 | kfree(buf); | |
52aec126 | 1375 | buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL, |
8e1f51bd | 1376 | node); |
ebc2ec48 | 1377 | if (!buf) |
1378 | goto err1; | |
1379 | } | |
1380 | ||
1381 | urb = usb_alloc_urb(0, GFP_KERNEL); | |
1382 | if (!urb) { | |
1383 | kfree(buf); | |
1384 | goto err1; | |
1385 | } | |
1386 | ||
1387 | INIT_LIST_HEAD(&tp->rx_info[i].list); | |
1388 | tp->rx_info[i].context = tp; | |
1389 | tp->rx_info[i].urb = urb; | |
1390 | tp->rx_info[i].buffer = buf; | |
1391 | tp->rx_info[i].head = rx_agg_align(buf); | |
1392 | } | |
1393 | ||
1394 | for (i = 0; i < RTL8152_MAX_TX; i++) { | |
52aec126 | 1395 | buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); |
ebc2ec48 | 1396 | if (!buf) |
1397 | goto err1; | |
1398 | ||
1399 | if (buf != tx_agg_align(buf)) { | |
1400 | kfree(buf); | |
52aec126 | 1401 | buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL, |
8e1f51bd | 1402 | node); |
ebc2ec48 | 1403 | if (!buf) |
1404 | goto err1; | |
1405 | } | |
1406 | ||
1407 | urb = usb_alloc_urb(0, GFP_KERNEL); | |
1408 | if (!urb) { | |
1409 | kfree(buf); | |
1410 | goto err1; | |
1411 | } | |
1412 | ||
1413 | INIT_LIST_HEAD(&tp->tx_info[i].list); | |
1414 | tp->tx_info[i].context = tp; | |
1415 | tp->tx_info[i].urb = urb; | |
1416 | tp->tx_info[i].buffer = buf; | |
1417 | tp->tx_info[i].head = tx_agg_align(buf); | |
1418 | ||
1419 | list_add_tail(&tp->tx_info[i].list, &tp->tx_free); | |
1420 | } | |
1421 | ||
40a82917 | 1422 | tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL); |
1423 | if (!tp->intr_urb) | |
1424 | goto err1; | |
1425 | ||
1426 | tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL); | |
1427 | if (!tp->intr_buff) | |
1428 | goto err1; | |
1429 | ||
1430 | tp->intr_interval = (int)ep_intr->desc.bInterval; | |
1431 | usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3), | |
b209af99 | 1432 | tp->intr_buff, INTBUFSIZE, intr_callback, |
1433 | tp, tp->intr_interval); | |
40a82917 | 1434 | |
ebc2ec48 | 1435 | return 0; |
1436 | ||
1437 | err1: | |
1438 | free_all_mem(tp); | |
1439 | return -ENOMEM; | |
1440 | } | |
1441 | ||
0de98f6c | 1442 | static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp) |
1443 | { | |
1444 | struct tx_agg *agg = NULL; | |
1445 | unsigned long flags; | |
1446 | ||
21949ab7 | 1447 | if (list_empty(&tp->tx_free)) |
1448 | return NULL; | |
1449 | ||
0de98f6c | 1450 | spin_lock_irqsave(&tp->tx_lock, flags); |
1451 | if (!list_empty(&tp->tx_free)) { | |
1452 | struct list_head *cursor; | |
1453 | ||
1454 | cursor = tp->tx_free.next; | |
1455 | list_del_init(cursor); | |
1456 | agg = list_entry(cursor, struct tx_agg, list); | |
1457 | } | |
1458 | spin_unlock_irqrestore(&tp->tx_lock, flags); | |
1459 | ||
1460 | return agg; | |
1461 | } | |
1462 | ||
b209af99 | 1463 | /* r8152_csum_workaround() |
6128d1bb | 1464 | * The hw limites the value the transport offset. When the offset is out of the |
1465 | * range, calculate the checksum by sw. | |
1466 | */ | |
1467 | static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb, | |
1468 | struct sk_buff_head *list) | |
1469 | { | |
1470 | if (skb_shinfo(skb)->gso_size) { | |
1471 | netdev_features_t features = tp->netdev->features; | |
1472 | struct sk_buff_head seg_list; | |
1473 | struct sk_buff *segs, *nskb; | |
1474 | ||
a91d45f1 | 1475 | features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6); |
6128d1bb | 1476 | segs = skb_gso_segment(skb, features); |
1477 | if (IS_ERR(segs) || !segs) | |
1478 | goto drop; | |
1479 | ||
1480 | __skb_queue_head_init(&seg_list); | |
1481 | ||
1482 | do { | |
1483 | nskb = segs; | |
1484 | segs = segs->next; | |
1485 | nskb->next = NULL; | |
1486 | __skb_queue_tail(&seg_list, nskb); | |
1487 | } while (segs); | |
1488 | ||
1489 | skb_queue_splice(&seg_list, list); | |
1490 | dev_kfree_skb(skb); | |
1491 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
1492 | if (skb_checksum_help(skb) < 0) | |
1493 | goto drop; | |
1494 | ||
1495 | __skb_queue_head(list, skb); | |
1496 | } else { | |
1497 | struct net_device_stats *stats; | |
1498 | ||
1499 | drop: | |
1500 | stats = &tp->netdev->stats; | |
1501 | stats->tx_dropped++; | |
1502 | dev_kfree_skb(skb); | |
1503 | } | |
1504 | } | |
1505 | ||
b209af99 | 1506 | /* msdn_giant_send_check() |
6128d1bb | 1507 | * According to the document of microsoft, the TCP Pseudo Header excludes the |
1508 | * packet length for IPv6 TCP large packets. | |
1509 | */ | |
1510 | static int msdn_giant_send_check(struct sk_buff *skb) | |
1511 | { | |
1512 | const struct ipv6hdr *ipv6h; | |
1513 | struct tcphdr *th; | |
fcb308d5 | 1514 | int ret; |
1515 | ||
1516 | ret = skb_cow_head(skb, 0); | |
1517 | if (ret) | |
1518 | return ret; | |
6128d1bb | 1519 | |
1520 | ipv6h = ipv6_hdr(skb); | |
1521 | th = tcp_hdr(skb); | |
1522 | ||
1523 | th->check = 0; | |
1524 | th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0); | |
1525 | ||
fcb308d5 | 1526 | return ret; |
6128d1bb | 1527 | } |
1528 | ||
c5554298 | 1529 | static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb) |
1530 | { | |
df8a39de | 1531 | if (skb_vlan_tag_present(skb)) { |
c5554298 | 1532 | u32 opts2; |
1533 | ||
df8a39de | 1534 | opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb)); |
c5554298 | 1535 | desc->opts2 |= cpu_to_le32(opts2); |
1536 | } | |
1537 | } | |
1538 | ||
1539 | static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb) | |
1540 | { | |
1541 | u32 opts2 = le32_to_cpu(desc->opts2); | |
1542 | ||
1543 | if (opts2 & RX_VLAN_TAG) | |
1544 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), | |
1545 | swab16(opts2 & 0xffff)); | |
1546 | } | |
1547 | ||
60c89071 | 1548 | static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, |
1549 | struct sk_buff *skb, u32 len, u32 transport_offset) | |
1550 | { | |
1551 | u32 mss = skb_shinfo(skb)->gso_size; | |
1552 | u32 opts1, opts2 = 0; | |
1553 | int ret = TX_CSUM_SUCCESS; | |
1554 | ||
1555 | WARN_ON_ONCE(len > TX_LEN_MAX); | |
1556 | ||
1557 | opts1 = len | TX_FS | TX_LS; | |
1558 | ||
1559 | if (mss) { | |
6128d1bb | 1560 | if (transport_offset > GTTCPHO_MAX) { |
1561 | netif_warn(tp, tx_err, tp->netdev, | |
1562 | "Invalid transport offset 0x%x for TSO\n", | |
1563 | transport_offset); | |
1564 | ret = TX_CSUM_TSO; | |
1565 | goto unavailable; | |
1566 | } | |
1567 | ||
6e74d174 | 1568 | switch (vlan_get_protocol(skb)) { |
60c89071 | 1569 | case htons(ETH_P_IP): |
1570 | opts1 |= GTSENDV4; | |
1571 | break; | |
1572 | ||
6128d1bb | 1573 | case htons(ETH_P_IPV6): |
fcb308d5 | 1574 | if (msdn_giant_send_check(skb)) { |
1575 | ret = TX_CSUM_TSO; | |
1576 | goto unavailable; | |
1577 | } | |
6128d1bb | 1578 | opts1 |= GTSENDV6; |
6128d1bb | 1579 | break; |
1580 | ||
60c89071 | 1581 | default: |
1582 | WARN_ON_ONCE(1); | |
1583 | break; | |
1584 | } | |
1585 | ||
1586 | opts1 |= transport_offset << GTTCPHO_SHIFT; | |
1587 | opts2 |= min(mss, MSS_MAX) << MSS_SHIFT; | |
1588 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
1589 | u8 ip_protocol; | |
5bd23881 | 1590 | |
6128d1bb | 1591 | if (transport_offset > TCPHO_MAX) { |
1592 | netif_warn(tp, tx_err, tp->netdev, | |
1593 | "Invalid transport offset 0x%x\n", | |
1594 | transport_offset); | |
1595 | ret = TX_CSUM_NONE; | |
1596 | goto unavailable; | |
1597 | } | |
1598 | ||
6e74d174 | 1599 | switch (vlan_get_protocol(skb)) { |
5bd23881 | 1600 | case htons(ETH_P_IP): |
1601 | opts2 |= IPV4_CS; | |
1602 | ip_protocol = ip_hdr(skb)->protocol; | |
1603 | break; | |
1604 | ||
1605 | case htons(ETH_P_IPV6): | |
1606 | opts2 |= IPV6_CS; | |
1607 | ip_protocol = ipv6_hdr(skb)->nexthdr; | |
1608 | break; | |
1609 | ||
1610 | default: | |
1611 | ip_protocol = IPPROTO_RAW; | |
1612 | break; | |
1613 | } | |
1614 | ||
60c89071 | 1615 | if (ip_protocol == IPPROTO_TCP) |
5bd23881 | 1616 | opts2 |= TCP_CS; |
60c89071 | 1617 | else if (ip_protocol == IPPROTO_UDP) |
5bd23881 | 1618 | opts2 |= UDP_CS; |
60c89071 | 1619 | else |
5bd23881 | 1620 | WARN_ON_ONCE(1); |
5bd23881 | 1621 | |
60c89071 | 1622 | opts2 |= transport_offset << TCPHO_SHIFT; |
5bd23881 | 1623 | } |
60c89071 | 1624 | |
1625 | desc->opts2 = cpu_to_le32(opts2); | |
1626 | desc->opts1 = cpu_to_le32(opts1); | |
1627 | ||
6128d1bb | 1628 | unavailable: |
60c89071 | 1629 | return ret; |
5bd23881 | 1630 | } |
1631 | ||
b1379d9a | 1632 | static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg) |
1633 | { | |
d84130a1 | 1634 | struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; |
9a4be1bd | 1635 | int remain, ret; |
b1379d9a | 1636 | u8 *tx_data; |
1637 | ||
d84130a1 | 1638 | __skb_queue_head_init(&skb_head); |
0c3121fc | 1639 | spin_lock(&tx_queue->lock); |
d84130a1 | 1640 | skb_queue_splice_init(tx_queue, &skb_head); |
0c3121fc | 1641 | spin_unlock(&tx_queue->lock); |
d84130a1 | 1642 | |
b1379d9a | 1643 | tx_data = agg->head; |
b209af99 | 1644 | agg->skb_num = 0; |
1645 | agg->skb_len = 0; | |
52aec126 | 1646 | remain = agg_buf_sz; |
b1379d9a | 1647 | |
7937f9e5 | 1648 | while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) { |
b1379d9a | 1649 | struct tx_desc *tx_desc; |
1650 | struct sk_buff *skb; | |
1651 | unsigned int len; | |
60c89071 | 1652 | u32 offset; |
b1379d9a | 1653 | |
d84130a1 | 1654 | skb = __skb_dequeue(&skb_head); |
b1379d9a | 1655 | if (!skb) |
1656 | break; | |
1657 | ||
60c89071 | 1658 | len = skb->len + sizeof(*tx_desc); |
1659 | ||
1660 | if (len > remain) { | |
d84130a1 | 1661 | __skb_queue_head(&skb_head, skb); |
b1379d9a | 1662 | break; |
1663 | } | |
1664 | ||
7937f9e5 | 1665 | tx_data = tx_agg_align(tx_data); |
b1379d9a | 1666 | tx_desc = (struct tx_desc *)tx_data; |
60c89071 | 1667 | |
1668 | offset = (u32)skb_transport_offset(skb); | |
1669 | ||
6128d1bb | 1670 | if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) { |
1671 | r8152_csum_workaround(tp, skb, &skb_head); | |
1672 | continue; | |
1673 | } | |
60c89071 | 1674 | |
c5554298 | 1675 | rtl_tx_vlan_tag(tx_desc, skb); |
1676 | ||
b1379d9a | 1677 | tx_data += sizeof(*tx_desc); |
1678 | ||
60c89071 | 1679 | len = skb->len; |
1680 | if (skb_copy_bits(skb, 0, tx_data, len) < 0) { | |
1681 | struct net_device_stats *stats = &tp->netdev->stats; | |
1682 | ||
1683 | stats->tx_dropped++; | |
1684 | dev_kfree_skb_any(skb); | |
1685 | tx_data -= sizeof(*tx_desc); | |
1686 | continue; | |
1687 | } | |
1688 | ||
1689 | tx_data += len; | |
b1379d9a | 1690 | agg->skb_len += len; |
60c89071 | 1691 | agg->skb_num++; |
1692 | ||
b1379d9a | 1693 | dev_kfree_skb_any(skb); |
1694 | ||
52aec126 | 1695 | remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head); |
b1379d9a | 1696 | } |
1697 | ||
d84130a1 | 1698 | if (!skb_queue_empty(&skb_head)) { |
0c3121fc | 1699 | spin_lock(&tx_queue->lock); |
d84130a1 | 1700 | skb_queue_splice(&skb_head, tx_queue); |
0c3121fc | 1701 | spin_unlock(&tx_queue->lock); |
d84130a1 | 1702 | } |
1703 | ||
0c3121fc | 1704 | netif_tx_lock(tp->netdev); |
dd1b119c | 1705 | |
1706 | if (netif_queue_stopped(tp->netdev) && | |
1707 | skb_queue_len(&tp->tx_queue) < tp->tx_qlen) | |
1708 | netif_wake_queue(tp->netdev); | |
1709 | ||
0c3121fc | 1710 | netif_tx_unlock(tp->netdev); |
9a4be1bd | 1711 | |
0c3121fc | 1712 | ret = usb_autopm_get_interface_async(tp->intf); |
9a4be1bd | 1713 | if (ret < 0) |
1714 | goto out_tx_fill; | |
dd1b119c | 1715 | |
b1379d9a | 1716 | usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2), |
1717 | agg->head, (int)(tx_data - (u8 *)agg->head), | |
1718 | (usb_complete_t)write_bulk_callback, agg); | |
1719 | ||
0c3121fc | 1720 | ret = usb_submit_urb(agg->urb, GFP_ATOMIC); |
9a4be1bd | 1721 | if (ret < 0) |
0c3121fc | 1722 | usb_autopm_put_interface_async(tp->intf); |
9a4be1bd | 1723 | |
1724 | out_tx_fill: | |
1725 | return ret; | |
b1379d9a | 1726 | } |
1727 | ||
565cab0a | 1728 | static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc) |
1729 | { | |
1730 | u8 checksum = CHECKSUM_NONE; | |
1731 | u32 opts2, opts3; | |
1732 | ||
19c0f40d | 1733 | if (!(tp->netdev->features & NETIF_F_RXCSUM)) |
565cab0a | 1734 | goto return_result; |
1735 | ||
1736 | opts2 = le32_to_cpu(rx_desc->opts2); | |
1737 | opts3 = le32_to_cpu(rx_desc->opts3); | |
1738 | ||
1739 | if (opts2 & RD_IPV4_CS) { | |
1740 | if (opts3 & IPF) | |
1741 | checksum = CHECKSUM_NONE; | |
1742 | else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF)) | |
1743 | checksum = CHECKSUM_NONE; | |
1744 | else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF)) | |
1745 | checksum = CHECKSUM_NONE; | |
1746 | else | |
1747 | checksum = CHECKSUM_UNNECESSARY; | |
b9a321b4 | 1748 | } else if (opts2 & RD_IPV6_CS) { |
6128d1bb | 1749 | if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF)) |
1750 | checksum = CHECKSUM_UNNECESSARY; | |
1751 | else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF)) | |
1752 | checksum = CHECKSUM_UNNECESSARY; | |
565cab0a | 1753 | } |
1754 | ||
1755 | return_result: | |
1756 | return checksum; | |
1757 | } | |
1758 | ||
d823ab68 | 1759 | static int rx_bottom(struct r8152 *tp, int budget) |
ebc2ec48 | 1760 | { |
a5a4f468 | 1761 | unsigned long flags; |
d84130a1 | 1762 | struct list_head *cursor, *next, rx_queue; |
e1a2ca92 | 1763 | int ret = 0, work_done = 0; |
ce594e98 | 1764 | struct napi_struct *napi = &tp->napi; |
d823ab68 | 1765 | |
1766 | if (!skb_queue_empty(&tp->rx_queue)) { | |
1767 | while (work_done < budget) { | |
1768 | struct sk_buff *skb = __skb_dequeue(&tp->rx_queue); | |
1769 | struct net_device *netdev = tp->netdev; | |
1770 | struct net_device_stats *stats = &netdev->stats; | |
1771 | unsigned int pkt_len; | |
1772 | ||
1773 | if (!skb) | |
1774 | break; | |
1775 | ||
1776 | pkt_len = skb->len; | |
ce594e98 | 1777 | napi_gro_receive(napi, skb); |
d823ab68 | 1778 | work_done++; |
1779 | stats->rx_packets++; | |
1780 | stats->rx_bytes += pkt_len; | |
1781 | } | |
1782 | } | |
ebc2ec48 | 1783 | |
d84130a1 | 1784 | if (list_empty(&tp->rx_done)) |
d823ab68 | 1785 | goto out1; |
d84130a1 | 1786 | |
1787 | INIT_LIST_HEAD(&rx_queue); | |
a5a4f468 | 1788 | spin_lock_irqsave(&tp->rx_lock, flags); |
d84130a1 | 1789 | list_splice_init(&tp->rx_done, &rx_queue); |
1790 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
1791 | ||
1792 | list_for_each_safe(cursor, next, &rx_queue) { | |
43a4478d | 1793 | struct rx_desc *rx_desc; |
1794 | struct rx_agg *agg; | |
43a4478d | 1795 | int len_used = 0; |
1796 | struct urb *urb; | |
1797 | u8 *rx_data; | |
43a4478d | 1798 | |
ebc2ec48 | 1799 | list_del_init(cursor); |
ebc2ec48 | 1800 | |
1801 | agg = list_entry(cursor, struct rx_agg, list); | |
1802 | urb = agg->urb; | |
0de98f6c | 1803 | if (urb->actual_length < ETH_ZLEN) |
1804 | goto submit; | |
ebc2ec48 | 1805 | |
ebc2ec48 | 1806 | rx_desc = agg->head; |
1807 | rx_data = agg->head; | |
7937f9e5 | 1808 | len_used += sizeof(struct rx_desc); |
ebc2ec48 | 1809 | |
7937f9e5 | 1810 | while (urb->actual_length > len_used) { |
43a4478d | 1811 | struct net_device *netdev = tp->netdev; |
05e0f1aa | 1812 | struct net_device_stats *stats = &netdev->stats; |
7937f9e5 | 1813 | unsigned int pkt_len; |
43a4478d | 1814 | struct sk_buff *skb; |
1815 | ||
7937f9e5 | 1816 | pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; |
ebc2ec48 | 1817 | if (pkt_len < ETH_ZLEN) |
1818 | break; | |
1819 | ||
7937f9e5 | 1820 | len_used += pkt_len; |
1821 | if (urb->actual_length < len_used) | |
1822 | break; | |
1823 | ||
8e1f51bd | 1824 | pkt_len -= CRC_SIZE; |
ebc2ec48 | 1825 | rx_data += sizeof(struct rx_desc); |
1826 | ||
ce594e98 | 1827 | skb = napi_alloc_skb(napi, pkt_len); |
ebc2ec48 | 1828 | if (!skb) { |
1829 | stats->rx_dropped++; | |
5e2f7485 | 1830 | goto find_next_rx; |
ebc2ec48 | 1831 | } |
565cab0a | 1832 | |
1833 | skb->ip_summed = r8152_rx_csum(tp, rx_desc); | |
ebc2ec48 | 1834 | memcpy(skb->data, rx_data, pkt_len); |
1835 | skb_put(skb, pkt_len); | |
1836 | skb->protocol = eth_type_trans(skb, netdev); | |
c5554298 | 1837 | rtl_rx_vlan_tag(rx_desc, skb); |
d823ab68 | 1838 | if (work_done < budget) { |
ce594e98 | 1839 | napi_gro_receive(napi, skb); |
d823ab68 | 1840 | work_done++; |
1841 | stats->rx_packets++; | |
1842 | stats->rx_bytes += pkt_len; | |
1843 | } else { | |
1844 | __skb_queue_tail(&tp->rx_queue, skb); | |
1845 | } | |
ebc2ec48 | 1846 | |
5e2f7485 | 1847 | find_next_rx: |
8e1f51bd | 1848 | rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE); |
ebc2ec48 | 1849 | rx_desc = (struct rx_desc *)rx_data; |
ebc2ec48 | 1850 | len_used = (int)(rx_data - (u8 *)agg->head); |
7937f9e5 | 1851 | len_used += sizeof(struct rx_desc); |
ebc2ec48 | 1852 | } |
1853 | ||
0de98f6c | 1854 | submit: |
e1a2ca92 | 1855 | if (!ret) { |
1856 | ret = r8152_submit_rx(tp, agg, GFP_ATOMIC); | |
1857 | } else { | |
1858 | urb->actual_length = 0; | |
1859 | list_add_tail(&agg->list, next); | |
1860 | } | |
1861 | } | |
1862 | ||
1863 | if (!list_empty(&rx_queue)) { | |
1864 | spin_lock_irqsave(&tp->rx_lock, flags); | |
1865 | list_splice_tail(&rx_queue, &tp->rx_done); | |
1866 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
ebc2ec48 | 1867 | } |
d823ab68 | 1868 | |
1869 | out1: | |
1870 | return work_done; | |
ebc2ec48 | 1871 | } |
1872 | ||
1873 | static void tx_bottom(struct r8152 *tp) | |
1874 | { | |
ebc2ec48 | 1875 | int res; |
1876 | ||
b1379d9a | 1877 | do { |
1878 | struct tx_agg *agg; | |
ebc2ec48 | 1879 | |
b1379d9a | 1880 | if (skb_queue_empty(&tp->tx_queue)) |
ebc2ec48 | 1881 | break; |
1882 | ||
b1379d9a | 1883 | agg = r8152_get_tx_agg(tp); |
1884 | if (!agg) | |
ebc2ec48 | 1885 | break; |
ebc2ec48 | 1886 | |
b1379d9a | 1887 | res = r8152_tx_agg_fill(tp, agg); |
1888 | if (res) { | |
05e0f1aa | 1889 | struct net_device *netdev = tp->netdev; |
ebc2ec48 | 1890 | |
b1379d9a | 1891 | if (res == -ENODEV) { |
67610496 | 1892 | set_bit(RTL8152_UNPLUG, &tp->flags); |
b1379d9a | 1893 | netif_device_detach(netdev); |
1894 | } else { | |
05e0f1aa | 1895 | struct net_device_stats *stats = &netdev->stats; |
1896 | unsigned long flags; | |
1897 | ||
b1379d9a | 1898 | netif_warn(tp, tx_err, netdev, |
1899 | "failed tx_urb %d\n", res); | |
1900 | stats->tx_dropped += agg->skb_num; | |
db8515ef | 1901 | |
b1379d9a | 1902 | spin_lock_irqsave(&tp->tx_lock, flags); |
1903 | list_add_tail(&agg->list, &tp->tx_free); | |
1904 | spin_unlock_irqrestore(&tp->tx_lock, flags); | |
1905 | } | |
ebc2ec48 | 1906 | } |
b1379d9a | 1907 | } while (res == 0); |
ebc2ec48 | 1908 | } |
1909 | ||
d823ab68 | 1910 | static void bottom_half(struct r8152 *tp) |
ac718b69 | 1911 | { |
ebc2ec48 | 1912 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
1913 | return; | |
1914 | ||
1915 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
ac718b69 | 1916 | return; |
ebc2ec48 | 1917 | |
7559fb2f | 1918 | /* When link down, the driver would cancel all bulks. */ |
1919 | /* This avoid the re-submitting bulk */ | |
ebc2ec48 | 1920 | if (!netif_carrier_ok(tp->netdev)) |
ac718b69 | 1921 | return; |
ebc2ec48 | 1922 | |
d823ab68 | 1923 | clear_bit(SCHEDULE_NAPI, &tp->flags); |
9451a11c | 1924 | |
0c3121fc | 1925 | tx_bottom(tp); |
ebc2ec48 | 1926 | } |
1927 | ||
d823ab68 | 1928 | static int r8152_poll(struct napi_struct *napi, int budget) |
1929 | { | |
1930 | struct r8152 *tp = container_of(napi, struct r8152, napi); | |
1931 | int work_done; | |
1932 | ||
1933 | work_done = rx_bottom(tp, budget); | |
1934 | bottom_half(tp); | |
1935 | ||
1936 | if (work_done < budget) { | |
1937 | napi_complete(napi); | |
1938 | if (!list_empty(&tp->rx_done)) | |
1939 | napi_schedule(napi); | |
248b213a | 1940 | else if (!skb_queue_empty(&tp->tx_queue) && |
1941 | !list_empty(&tp->tx_free)) | |
1942 | napi_schedule(napi); | |
d823ab68 | 1943 | } |
1944 | ||
1945 | return work_done; | |
1946 | } | |
1947 | ||
ebc2ec48 | 1948 | static |
1949 | int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags) | |
1950 | { | |
a0fccd48 | 1951 | int ret; |
1952 | ||
ef827a5b | 1953 | /* The rx would be stopped, so skip submitting */ |
1954 | if (test_bit(RTL8152_UNPLUG, &tp->flags) || | |
1955 | !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev)) | |
1956 | return 0; | |
1957 | ||
ebc2ec48 | 1958 | usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1), |
52aec126 | 1959 | agg->head, agg_buf_sz, |
b209af99 | 1960 | (usb_complete_t)read_bulk_callback, agg); |
ebc2ec48 | 1961 | |
a0fccd48 | 1962 | ret = usb_submit_urb(agg->urb, mem_flags); |
1963 | if (ret == -ENODEV) { | |
1964 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
1965 | netif_device_detach(tp->netdev); | |
1966 | } else if (ret) { | |
1967 | struct urb *urb = agg->urb; | |
1968 | unsigned long flags; | |
1969 | ||
1970 | urb->actual_length = 0; | |
1971 | spin_lock_irqsave(&tp->rx_lock, flags); | |
1972 | list_add_tail(&agg->list, &tp->rx_done); | |
1973 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
d823ab68 | 1974 | |
1975 | netif_err(tp, rx_err, tp->netdev, | |
1976 | "Couldn't submit rx[%p], ret = %d\n", agg, ret); | |
1977 | ||
1978 | napi_schedule(&tp->napi); | |
a0fccd48 | 1979 | } |
1980 | ||
1981 | return ret; | |
ac718b69 | 1982 | } |
1983 | ||
00a5e360 | 1984 | static void rtl_drop_queued_tx(struct r8152 *tp) |
1985 | { | |
1986 | struct net_device_stats *stats = &tp->netdev->stats; | |
d84130a1 | 1987 | struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; |
00a5e360 | 1988 | struct sk_buff *skb; |
1989 | ||
d84130a1 | 1990 | if (skb_queue_empty(tx_queue)) |
1991 | return; | |
1992 | ||
1993 | __skb_queue_head_init(&skb_head); | |
2685d410 | 1994 | spin_lock_bh(&tx_queue->lock); |
d84130a1 | 1995 | skb_queue_splice_init(tx_queue, &skb_head); |
2685d410 | 1996 | spin_unlock_bh(&tx_queue->lock); |
d84130a1 | 1997 | |
1998 | while ((skb = __skb_dequeue(&skb_head))) { | |
00a5e360 | 1999 | dev_kfree_skb(skb); |
2000 | stats->tx_dropped++; | |
2001 | } | |
2002 | } | |
2003 | ||
ac718b69 | 2004 | static void rtl8152_tx_timeout(struct net_device *netdev) |
2005 | { | |
2006 | struct r8152 *tp = netdev_priv(netdev); | |
ebc2ec48 | 2007 | |
4a8deae2 | 2008 | netif_warn(tp, tx_err, netdev, "Tx timeout\n"); |
37608f3e | 2009 | |
2010 | usb_queue_reset_device(tp->intf); | |
ac718b69 | 2011 | } |
2012 | ||
2013 | static void rtl8152_set_rx_mode(struct net_device *netdev) | |
2014 | { | |
2015 | struct r8152 *tp = netdev_priv(netdev); | |
2016 | ||
51d979fa | 2017 | if (netif_carrier_ok(netdev)) { |
ac718b69 | 2018 | set_bit(RTL8152_SET_RX_MODE, &tp->flags); |
40a82917 | 2019 | schedule_delayed_work(&tp->schedule, 0); |
2020 | } | |
ac718b69 | 2021 | } |
2022 | ||
2023 | static void _rtl8152_set_rx_mode(struct net_device *netdev) | |
2024 | { | |
2025 | struct r8152 *tp = netdev_priv(netdev); | |
31787f53 | 2026 | u32 mc_filter[2]; /* Multicast hash filter */ |
2027 | __le32 tmp[2]; | |
ac718b69 | 2028 | u32 ocp_data; |
2029 | ||
ac718b69 | 2030 | netif_stop_queue(netdev); |
2031 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2032 | ocp_data &= ~RCR_ACPT_ALL; | |
2033 | ocp_data |= RCR_AB | RCR_APM; | |
2034 | ||
2035 | if (netdev->flags & IFF_PROMISC) { | |
2036 | /* Unconditionally log net taps. */ | |
2037 | netif_notice(tp, link, netdev, "Promiscuous mode enabled\n"); | |
2038 | ocp_data |= RCR_AM | RCR_AAP; | |
b209af99 | 2039 | mc_filter[1] = 0xffffffff; |
2040 | mc_filter[0] = 0xffffffff; | |
ac718b69 | 2041 | } else if ((netdev_mc_count(netdev) > multicast_filter_limit) || |
2042 | (netdev->flags & IFF_ALLMULTI)) { | |
2043 | /* Too many to filter perfectly -- accept all multicasts. */ | |
2044 | ocp_data |= RCR_AM; | |
b209af99 | 2045 | mc_filter[1] = 0xffffffff; |
2046 | mc_filter[0] = 0xffffffff; | |
ac718b69 | 2047 | } else { |
2048 | struct netdev_hw_addr *ha; | |
2049 | ||
b209af99 | 2050 | mc_filter[1] = 0; |
2051 | mc_filter[0] = 0; | |
ac718b69 | 2052 | netdev_for_each_mc_addr(ha, netdev) { |
2053 | int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; | |
b209af99 | 2054 | |
ac718b69 | 2055 | mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); |
2056 | ocp_data |= RCR_AM; | |
2057 | } | |
2058 | } | |
2059 | ||
31787f53 | 2060 | tmp[0] = __cpu_to_le32(swab32(mc_filter[1])); |
2061 | tmp[1] = __cpu_to_le32(swab32(mc_filter[0])); | |
ac718b69 | 2062 | |
31787f53 | 2063 | pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp); |
ac718b69 | 2064 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); |
2065 | netif_wake_queue(netdev); | |
ac718b69 | 2066 | } |
2067 | ||
a5e31255 | 2068 | static netdev_features_t |
2069 | rtl8152_features_check(struct sk_buff *skb, struct net_device *dev, | |
2070 | netdev_features_t features) | |
2071 | { | |
2072 | u32 mss = skb_shinfo(skb)->gso_size; | |
2073 | int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX; | |
2074 | int offset = skb_transport_offset(skb); | |
2075 | ||
2076 | if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset) | |
a188222b | 2077 | features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); |
a5e31255 | 2078 | else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz) |
2079 | features &= ~NETIF_F_GSO_MASK; | |
2080 | ||
2081 | return features; | |
2082 | } | |
2083 | ||
ac718b69 | 2084 | static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb, |
b209af99 | 2085 | struct net_device *netdev) |
ac718b69 | 2086 | { |
2087 | struct r8152 *tp = netdev_priv(netdev); | |
ac718b69 | 2088 | |
ebc2ec48 | 2089 | skb_tx_timestamp(skb); |
ac718b69 | 2090 | |
61598788 | 2091 | skb_queue_tail(&tp->tx_queue, skb); |
ebc2ec48 | 2092 | |
0c3121fc | 2093 | if (!list_empty(&tp->tx_free)) { |
2094 | if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { | |
d823ab68 | 2095 | set_bit(SCHEDULE_NAPI, &tp->flags); |
0c3121fc | 2096 | schedule_delayed_work(&tp->schedule, 0); |
2097 | } else { | |
2098 | usb_mark_last_busy(tp->udev); | |
d823ab68 | 2099 | napi_schedule(&tp->napi); |
0c3121fc | 2100 | } |
b209af99 | 2101 | } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) { |
dd1b119c | 2102 | netif_stop_queue(netdev); |
b209af99 | 2103 | } |
dd1b119c | 2104 | |
ac718b69 | 2105 | return NETDEV_TX_OK; |
2106 | } | |
2107 | ||
2108 | static void r8152b_reset_packet_filter(struct r8152 *tp) | |
2109 | { | |
2110 | u32 ocp_data; | |
2111 | ||
2112 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); | |
2113 | ocp_data &= ~FMC_FCR_MCU_EN; | |
2114 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); | |
2115 | ocp_data |= FMC_FCR_MCU_EN; | |
2116 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); | |
2117 | } | |
2118 | ||
2119 | static void rtl8152_nic_reset(struct r8152 *tp) | |
2120 | { | |
2121 | int i; | |
2122 | ||
2123 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST); | |
2124 | ||
2125 | for (i = 0; i < 1000; i++) { | |
2126 | if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST)) | |
2127 | break; | |
b209af99 | 2128 | usleep_range(100, 400); |
ac718b69 | 2129 | } |
2130 | } | |
2131 | ||
dd1b119c | 2132 | static void set_tx_qlen(struct r8152 *tp) |
2133 | { | |
2134 | struct net_device *netdev = tp->netdev; | |
2135 | ||
52aec126 | 2136 | tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN + |
2137 | sizeof(struct tx_desc)); | |
dd1b119c | 2138 | } |
2139 | ||
ac718b69 | 2140 | static inline u8 rtl8152_get_speed(struct r8152 *tp) |
2141 | { | |
2142 | return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); | |
2143 | } | |
2144 | ||
507605a8 | 2145 | static void rtl_set_eee_plus(struct r8152 *tp) |
ac718b69 | 2146 | { |
ebc2ec48 | 2147 | u32 ocp_data; |
ac718b69 | 2148 | u8 speed; |
2149 | ||
2150 | speed = rtl8152_get_speed(tp); | |
ebc2ec48 | 2151 | if (speed & _10bps) { |
ac718b69 | 2152 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); |
ebc2ec48 | 2153 | ocp_data |= EEEP_CR_EEEP_TX; |
ac718b69 | 2154 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); |
2155 | } else { | |
2156 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); | |
ebc2ec48 | 2157 | ocp_data &= ~EEEP_CR_EEEP_TX; |
ac718b69 | 2158 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); |
2159 | } | |
507605a8 | 2160 | } |
2161 | ||
00a5e360 | 2162 | static void rxdy_gated_en(struct r8152 *tp, bool enable) |
2163 | { | |
2164 | u32 ocp_data; | |
2165 | ||
2166 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); | |
2167 | if (enable) | |
2168 | ocp_data |= RXDY_GATED_EN; | |
2169 | else | |
2170 | ocp_data &= ~RXDY_GATED_EN; | |
2171 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); | |
2172 | } | |
2173 | ||
445f7f4d | 2174 | static int rtl_start_rx(struct r8152 *tp) |
2175 | { | |
2176 | int i, ret = 0; | |
2177 | ||
2178 | INIT_LIST_HEAD(&tp->rx_done); | |
2179 | for (i = 0; i < RTL8152_MAX_RX; i++) { | |
2180 | INIT_LIST_HEAD(&tp->rx_info[i].list); | |
2181 | ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL); | |
2182 | if (ret) | |
2183 | break; | |
2184 | } | |
2185 | ||
7bcf4f60 | 2186 | if (ret && ++i < RTL8152_MAX_RX) { |
2187 | struct list_head rx_queue; | |
2188 | unsigned long flags; | |
2189 | ||
2190 | INIT_LIST_HEAD(&rx_queue); | |
2191 | ||
2192 | do { | |
2193 | struct rx_agg *agg = &tp->rx_info[i++]; | |
2194 | struct urb *urb = agg->urb; | |
2195 | ||
2196 | urb->actual_length = 0; | |
2197 | list_add_tail(&agg->list, &rx_queue); | |
2198 | } while (i < RTL8152_MAX_RX); | |
2199 | ||
2200 | spin_lock_irqsave(&tp->rx_lock, flags); | |
2201 | list_splice_tail(&rx_queue, &tp->rx_done); | |
2202 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
2203 | } | |
2204 | ||
445f7f4d | 2205 | return ret; |
2206 | } | |
2207 | ||
2208 | static int rtl_stop_rx(struct r8152 *tp) | |
2209 | { | |
2210 | int i; | |
2211 | ||
2212 | for (i = 0; i < RTL8152_MAX_RX; i++) | |
2213 | usb_kill_urb(tp->rx_info[i].urb); | |
2214 | ||
d823ab68 | 2215 | while (!skb_queue_empty(&tp->rx_queue)) |
2216 | dev_kfree_skb(__skb_dequeue(&tp->rx_queue)); | |
2217 | ||
445f7f4d | 2218 | return 0; |
2219 | } | |
2220 | ||
507605a8 | 2221 | static int rtl_enable(struct r8152 *tp) |
2222 | { | |
2223 | u32 ocp_data; | |
ac718b69 | 2224 | |
2225 | r8152b_reset_packet_filter(tp); | |
2226 | ||
2227 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); | |
2228 | ocp_data |= CR_RE | CR_TE; | |
2229 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); | |
2230 | ||
00a5e360 | 2231 | rxdy_gated_en(tp, false); |
ac718b69 | 2232 | |
aa2e0926 | 2233 | return 0; |
ac718b69 | 2234 | } |
2235 | ||
507605a8 | 2236 | static int rtl8152_enable(struct r8152 *tp) |
2237 | { | |
6871438c | 2238 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
2239 | return -ENODEV; | |
2240 | ||
507605a8 | 2241 | set_tx_qlen(tp); |
2242 | rtl_set_eee_plus(tp); | |
2243 | ||
2244 | return rtl_enable(tp); | |
2245 | } | |
2246 | ||
464ec10a | 2247 | static void r8153_set_rx_early_timeout(struct r8152 *tp) |
43779f8d | 2248 | { |
464ec10a | 2249 | u32 ocp_data = tp->coalesce / 8; |
43779f8d | 2250 | |
464ec10a | 2251 | ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, ocp_data); |
2252 | } | |
2253 | ||
2254 | static void r8153_set_rx_early_size(struct r8152 *tp) | |
2255 | { | |
b20cb60e | 2256 | u32 ocp_data = (agg_buf_sz - rx_reserved_size(tp->netdev->mtu)) / 4; |
464ec10a | 2257 | |
2258 | ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, ocp_data); | |
43779f8d | 2259 | } |
2260 | ||
2261 | static int rtl8153_enable(struct r8152 *tp) | |
2262 | { | |
6871438c | 2263 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
2264 | return -ENODEV; | |
2265 | ||
43779f8d | 2266 | set_tx_qlen(tp); |
2267 | rtl_set_eee_plus(tp); | |
464ec10a | 2268 | r8153_set_rx_early_timeout(tp); |
2269 | r8153_set_rx_early_size(tp); | |
43779f8d | 2270 | |
2271 | return rtl_enable(tp); | |
2272 | } | |
2273 | ||
d70b1137 | 2274 | static void rtl_disable(struct r8152 *tp) |
ac718b69 | 2275 | { |
ebc2ec48 | 2276 | u32 ocp_data; |
2277 | int i; | |
ac718b69 | 2278 | |
6871438c | 2279 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) { |
2280 | rtl_drop_queued_tx(tp); | |
2281 | return; | |
2282 | } | |
2283 | ||
ac718b69 | 2284 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); |
2285 | ocp_data &= ~RCR_ACPT_ALL; | |
2286 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2287 | ||
00a5e360 | 2288 | rtl_drop_queued_tx(tp); |
ebc2ec48 | 2289 | |
2290 | for (i = 0; i < RTL8152_MAX_TX; i++) | |
2291 | usb_kill_urb(tp->tx_info[i].urb); | |
ac718b69 | 2292 | |
00a5e360 | 2293 | rxdy_gated_en(tp, true); |
ac718b69 | 2294 | |
2295 | for (i = 0; i < 1000; i++) { | |
2296 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2297 | if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY) | |
2298 | break; | |
8ddfa077 | 2299 | usleep_range(1000, 2000); |
ac718b69 | 2300 | } |
2301 | ||
2302 | for (i = 0; i < 1000; i++) { | |
2303 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY) | |
2304 | break; | |
8ddfa077 | 2305 | usleep_range(1000, 2000); |
ac718b69 | 2306 | } |
2307 | ||
445f7f4d | 2308 | rtl_stop_rx(tp); |
ac718b69 | 2309 | |
2310 | rtl8152_nic_reset(tp); | |
2311 | } | |
2312 | ||
00a5e360 | 2313 | static void r8152_power_cut_en(struct r8152 *tp, bool enable) |
2314 | { | |
2315 | u32 ocp_data; | |
2316 | ||
2317 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); | |
2318 | if (enable) | |
2319 | ocp_data |= POWER_CUT; | |
2320 | else | |
2321 | ocp_data &= ~POWER_CUT; | |
2322 | ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); | |
2323 | ||
2324 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); | |
2325 | ocp_data &= ~RESUME_INDICATE; | |
2326 | ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); | |
00a5e360 | 2327 | } |
2328 | ||
c5554298 | 2329 | static void rtl_rx_vlan_en(struct r8152 *tp, bool enable) |
2330 | { | |
2331 | u32 ocp_data; | |
2332 | ||
2333 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); | |
2334 | if (enable) | |
2335 | ocp_data |= CPCR_RX_VLAN; | |
2336 | else | |
2337 | ocp_data &= ~CPCR_RX_VLAN; | |
2338 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); | |
2339 | } | |
2340 | ||
2341 | static int rtl8152_set_features(struct net_device *dev, | |
2342 | netdev_features_t features) | |
2343 | { | |
2344 | netdev_features_t changed = features ^ dev->features; | |
2345 | struct r8152 *tp = netdev_priv(dev); | |
405f8a0e | 2346 | int ret; |
2347 | ||
2348 | ret = usb_autopm_get_interface(tp->intf); | |
2349 | if (ret < 0) | |
2350 | goto out; | |
c5554298 | 2351 | |
b5403273 | 2352 | mutex_lock(&tp->control); |
2353 | ||
c5554298 | 2354 | if (changed & NETIF_F_HW_VLAN_CTAG_RX) { |
2355 | if (features & NETIF_F_HW_VLAN_CTAG_RX) | |
2356 | rtl_rx_vlan_en(tp, true); | |
2357 | else | |
2358 | rtl_rx_vlan_en(tp, false); | |
2359 | } | |
2360 | ||
b5403273 | 2361 | mutex_unlock(&tp->control); |
2362 | ||
405f8a0e | 2363 | usb_autopm_put_interface(tp->intf); |
2364 | ||
2365 | out: | |
2366 | return ret; | |
c5554298 | 2367 | } |
2368 | ||
21ff2e89 | 2369 | #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) |
2370 | ||
2371 | static u32 __rtl_get_wol(struct r8152 *tp) | |
2372 | { | |
2373 | u32 ocp_data; | |
2374 | u32 wolopts = 0; | |
2375 | ||
21ff2e89 | 2376 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); |
2377 | if (ocp_data & LINK_ON_WAKE_EN) | |
2378 | wolopts |= WAKE_PHY; | |
2379 | ||
2380 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); | |
2381 | if (ocp_data & UWF_EN) | |
2382 | wolopts |= WAKE_UCAST; | |
2383 | if (ocp_data & BWF_EN) | |
2384 | wolopts |= WAKE_BCAST; | |
2385 | if (ocp_data & MWF_EN) | |
2386 | wolopts |= WAKE_MCAST; | |
2387 | ||
2388 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); | |
2389 | if (ocp_data & MAGIC_EN) | |
2390 | wolopts |= WAKE_MAGIC; | |
2391 | ||
2392 | return wolopts; | |
2393 | } | |
2394 | ||
2395 | static void __rtl_set_wol(struct r8152 *tp, u32 wolopts) | |
2396 | { | |
2397 | u32 ocp_data; | |
2398 | ||
2399 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
2400 | ||
2401 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); | |
2402 | ocp_data &= ~LINK_ON_WAKE_EN; | |
2403 | if (wolopts & WAKE_PHY) | |
2404 | ocp_data |= LINK_ON_WAKE_EN; | |
2405 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); | |
2406 | ||
2407 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); | |
92f7d07d | 2408 | ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN); |
21ff2e89 | 2409 | if (wolopts & WAKE_UCAST) |
2410 | ocp_data |= UWF_EN; | |
2411 | if (wolopts & WAKE_BCAST) | |
2412 | ocp_data |= BWF_EN; | |
2413 | if (wolopts & WAKE_MCAST) | |
2414 | ocp_data |= MWF_EN; | |
21ff2e89 | 2415 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data); |
2416 | ||
2417 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
2418 | ||
2419 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); | |
2420 | ocp_data &= ~MAGIC_EN; | |
2421 | if (wolopts & WAKE_MAGIC) | |
2422 | ocp_data |= MAGIC_EN; | |
2423 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data); | |
2424 | ||
2425 | if (wolopts & WAKE_ANY) | |
2426 | device_set_wakeup_enable(&tp->udev->dev, true); | |
2427 | else | |
2428 | device_set_wakeup_enable(&tp->udev->dev, false); | |
2429 | } | |
2430 | ||
134f98bc | 2431 | static void r8153_mac_clk_spd(struct r8152 *tp, bool enable) |
2432 | { | |
2433 | /* MAC clock speed down */ | |
2434 | if (enable) { | |
2435 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, | |
2436 | ALDPS_SPDWN_RATIO); | |
2437 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, | |
2438 | EEE_SPDWN_RATIO); | |
2439 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, | |
2440 | PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN | | |
2441 | U1U2_SPDWN_EN | L1_SPDWN_EN); | |
2442 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, | |
2443 | PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN | | |
2444 | TP100_SPDWN_EN | TP500_SPDWN_EN | EEE_SPDWN_EN | | |
2445 | TP1000_SPDWN_EN); | |
2446 | } else { | |
2447 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0); | |
2448 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0); | |
2449 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0); | |
2450 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0); | |
2451 | } | |
2452 | } | |
2453 | ||
b214396f | 2454 | static void r8153_u1u2en(struct r8152 *tp, bool enable) |
2455 | { | |
2456 | u8 u1u2[8]; | |
2457 | ||
2458 | if (enable) | |
2459 | memset(u1u2, 0xff, sizeof(u1u2)); | |
2460 | else | |
2461 | memset(u1u2, 0x00, sizeof(u1u2)); | |
2462 | ||
2463 | usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2); | |
2464 | } | |
2465 | ||
2466 | static void r8153_u2p3en(struct r8152 *tp, bool enable) | |
2467 | { | |
2468 | u32 ocp_data; | |
2469 | ||
2470 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); | |
2471 | if (enable && tp->version != RTL_VER_03 && tp->version != RTL_VER_04) | |
2472 | ocp_data |= U2P3_ENABLE; | |
2473 | else | |
2474 | ocp_data &= ~U2P3_ENABLE; | |
2475 | ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); | |
2476 | } | |
2477 | ||
c564b871 | 2478 | static u16 r8153_phy_status(struct r8152 *tp, u16 desired) |
2479 | { | |
2480 | u16 data; | |
2481 | int i; | |
2482 | ||
2483 | for (i = 0; i < 500; i++) { | |
2484 | data = ocp_reg_read(tp, OCP_PHY_STATUS); | |
2485 | data &= PHY_STAT_MASK; | |
2486 | if (desired) { | |
2487 | if (data == desired) | |
2488 | break; | |
2489 | } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN || | |
2490 | data == PHY_STAT_EXT_INIT) { | |
2491 | break; | |
2492 | } | |
2493 | ||
2494 | msleep(20); | |
2495 | } | |
2496 | ||
2497 | return data; | |
2498 | } | |
2499 | ||
b214396f | 2500 | static void r8153_power_cut_en(struct r8152 *tp, bool enable) |
2501 | { | |
2502 | u32 ocp_data; | |
2503 | ||
2504 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); | |
2505 | if (enable) | |
2506 | ocp_data |= PWR_EN | PHASE2_EN; | |
2507 | else | |
2508 | ocp_data &= ~(PWR_EN | PHASE2_EN); | |
2509 | ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); | |
2510 | ||
2511 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); | |
2512 | ocp_data &= ~PCUT_STATUS; | |
2513 | ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); | |
2514 | } | |
2515 | ||
7daed8dc | 2516 | static bool rtl_can_wakeup(struct r8152 *tp) |
2517 | { | |
2518 | struct usb_device *udev = tp->udev; | |
2519 | ||
2520 | return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP); | |
2521 | } | |
2522 | ||
9a4be1bd | 2523 | static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable) |
2524 | { | |
2525 | if (enable) { | |
2526 | u32 ocp_data; | |
2527 | ||
2528 | __rtl_set_wol(tp, WAKE_ANY); | |
2529 | ||
2530 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
2531 | ||
2532 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); | |
2533 | ocp_data |= LINK_OFF_WAKE_EN; | |
2534 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); | |
2535 | ||
2536 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
2537 | } else { | |
f95ae8a0 | 2538 | u32 ocp_data; |
2539 | ||
9a4be1bd | 2540 | __rtl_set_wol(tp, tp->saved_wolopts); |
f95ae8a0 | 2541 | |
2542 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
2543 | ||
2544 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); | |
2545 | ocp_data &= ~LINK_OFF_WAKE_EN; | |
2546 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); | |
2547 | ||
2548 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
2609af19 | 2549 | } |
2550 | } | |
f95ae8a0 | 2551 | |
2609af19 | 2552 | static void rtl8153_runtime_enable(struct r8152 *tp, bool enable) |
2553 | { | |
2554 | rtl_runtime_suspend_enable(tp, enable); | |
2555 | ||
2556 | if (enable) { | |
2557 | r8153_u1u2en(tp, false); | |
2558 | r8153_u2p3en(tp, false); | |
134f98bc | 2559 | r8153_mac_clk_spd(tp, true); |
2609af19 | 2560 | } else { |
134f98bc | 2561 | r8153_mac_clk_spd(tp, false); |
b214396f | 2562 | r8153_u2p3en(tp, true); |
2563 | r8153_u1u2en(tp, true); | |
9a4be1bd | 2564 | } |
2565 | } | |
2566 | ||
4349968a | 2567 | static void r8153_teredo_off(struct r8152 *tp) |
2568 | { | |
2569 | u32 ocp_data; | |
2570 | ||
2571 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); | |
2572 | ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN); | |
2573 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); | |
2574 | ||
2575 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE); | |
2576 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0); | |
2577 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0); | |
2578 | } | |
2579 | ||
93fe9b18 | 2580 | static void rtl_reset_bmu(struct r8152 *tp) |
2581 | { | |
2582 | u32 ocp_data; | |
2583 | ||
2584 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET); | |
2585 | ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT); | |
2586 | ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); | |
2587 | ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT; | |
2588 | ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); | |
2589 | } | |
2590 | ||
cda9fb01 | 2591 | static void r8152_aldps_en(struct r8152 *tp, bool enable) |
4349968a | 2592 | { |
cda9fb01 | 2593 | if (enable) { |
2594 | ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS | | |
2595 | LINKENA | DIS_SDSAVE); | |
2596 | } else { | |
2597 | ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | | |
2598 | DIS_SDSAVE); | |
2599 | msleep(20); | |
2600 | } | |
4349968a | 2601 | } |
2602 | ||
e6449539 | 2603 | static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg) |
2604 | { | |
2605 | ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev); | |
2606 | ocp_reg_write(tp, OCP_EEE_DATA, reg); | |
2607 | ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev); | |
2608 | } | |
2609 | ||
2610 | static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg) | |
2611 | { | |
2612 | u16 data; | |
2613 | ||
2614 | r8152_mmd_indirect(tp, dev, reg); | |
2615 | data = ocp_reg_read(tp, OCP_EEE_DATA); | |
2616 | ocp_reg_write(tp, OCP_EEE_AR, 0x0000); | |
2617 | ||
2618 | return data; | |
2619 | } | |
2620 | ||
2621 | static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data) | |
2622 | { | |
2623 | r8152_mmd_indirect(tp, dev, reg); | |
2624 | ocp_reg_write(tp, OCP_EEE_DATA, data); | |
2625 | ocp_reg_write(tp, OCP_EEE_AR, 0x0000); | |
2626 | } | |
2627 | ||
2628 | static void r8152_eee_en(struct r8152 *tp, bool enable) | |
2629 | { | |
2630 | u16 config1, config2, config3; | |
2631 | u32 ocp_data; | |
2632 | ||
2633 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); | |
2634 | config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask; | |
2635 | config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2); | |
2636 | config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask; | |
2637 | ||
2638 | if (enable) { | |
2639 | ocp_data |= EEE_RX_EN | EEE_TX_EN; | |
2640 | config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN; | |
2641 | config1 |= sd_rise_time(1); | |
2642 | config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN; | |
2643 | config3 |= fast_snr(42); | |
2644 | } else { | |
2645 | ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); | |
2646 | config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | | |
2647 | RX_QUIET_EN); | |
2648 | config1 |= sd_rise_time(7); | |
2649 | config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN); | |
2650 | config3 |= fast_snr(511); | |
2651 | } | |
2652 | ||
2653 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); | |
2654 | ocp_reg_write(tp, OCP_EEE_CONFIG1, config1); | |
2655 | ocp_reg_write(tp, OCP_EEE_CONFIG2, config2); | |
2656 | ocp_reg_write(tp, OCP_EEE_CONFIG3, config3); | |
2657 | } | |
2658 | ||
2659 | static void r8152b_enable_eee(struct r8152 *tp) | |
2660 | { | |
2661 | r8152_eee_en(tp, true); | |
2662 | r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX); | |
2663 | } | |
2664 | ||
2665 | static void r8152b_enable_fc(struct r8152 *tp) | |
2666 | { | |
2667 | u16 anar; | |
2668 | ||
2669 | anar = r8152_mdio_read(tp, MII_ADVERTISE); | |
2670 | anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; | |
2671 | r8152_mdio_write(tp, MII_ADVERTISE, anar); | |
2672 | } | |
2673 | ||
d70b1137 | 2674 | static void rtl8152_disable(struct r8152 *tp) |
2675 | { | |
cda9fb01 | 2676 | r8152_aldps_en(tp, false); |
d70b1137 | 2677 | rtl_disable(tp); |
cda9fb01 | 2678 | r8152_aldps_en(tp, true); |
d70b1137 | 2679 | } |
2680 | ||
4349968a | 2681 | static void r8152b_hw_phy_cfg(struct r8152 *tp) |
2682 | { | |
ef39df8e | 2683 | r8152b_enable_eee(tp); |
2684 | r8152_aldps_en(tp, true); | |
2685 | r8152b_enable_fc(tp); | |
f0cbe0ac | 2686 | |
aa66a5f1 | 2687 | set_bit(PHY_RESET, &tp->flags); |
4349968a | 2688 | } |
2689 | ||
ac718b69 | 2690 | static void r8152b_exit_oob(struct r8152 *tp) |
2691 | { | |
db8515ef | 2692 | u32 ocp_data; |
2693 | int i; | |
ac718b69 | 2694 | |
2695 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2696 | ocp_data &= ~RCR_ACPT_ALL; | |
2697 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2698 | ||
00a5e360 | 2699 | rxdy_gated_en(tp, true); |
da9bd117 | 2700 | r8153_teredo_off(tp); |
ac718b69 | 2701 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); |
2702 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); | |
2703 | ||
2704 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2705 | ocp_data &= ~NOW_IS_OOB; | |
2706 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2707 | ||
2708 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2709 | ocp_data &= ~MCU_BORW_EN; | |
2710 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2711 | ||
2712 | for (i = 0; i < 1000; i++) { | |
2713 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2714 | if (ocp_data & LINK_LIST_READY) | |
2715 | break; | |
8ddfa077 | 2716 | usleep_range(1000, 2000); |
ac718b69 | 2717 | } |
2718 | ||
2719 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2720 | ocp_data |= RE_INIT_LL; | |
2721 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2722 | ||
2723 | for (i = 0; i < 1000; i++) { | |
2724 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2725 | if (ocp_data & LINK_LIST_READY) | |
2726 | break; | |
8ddfa077 | 2727 | usleep_range(1000, 2000); |
ac718b69 | 2728 | } |
2729 | ||
2730 | rtl8152_nic_reset(tp); | |
2731 | ||
2732 | /* rx share fifo credit full threshold */ | |
2733 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); | |
2734 | ||
a3cc465d | 2735 | if (tp->udev->speed == USB_SPEED_FULL || |
2736 | tp->udev->speed == USB_SPEED_LOW) { | |
ac718b69 | 2737 | /* rx share fifo credit near full threshold */ |
2738 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, | |
2739 | RXFIFO_THR2_FULL); | |
2740 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, | |
2741 | RXFIFO_THR3_FULL); | |
2742 | } else { | |
2743 | /* rx share fifo credit near full threshold */ | |
2744 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, | |
2745 | RXFIFO_THR2_HIGH); | |
2746 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, | |
2747 | RXFIFO_THR3_HIGH); | |
2748 | } | |
2749 | ||
2750 | /* TX share fifo free credit full threshold */ | |
2751 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL); | |
2752 | ||
2753 | ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD); | |
8e1f51bd | 2754 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH); |
ac718b69 | 2755 | ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA, |
2756 | TEST_MODE_DISABLE | TX_SIZE_ADJUST1); | |
2757 | ||
c5554298 | 2758 | rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); |
ac718b69 | 2759 | |
2760 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); | |
2761 | ||
2762 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); | |
2763 | ocp_data |= TCR0_AUTO_FIFO; | |
2764 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); | |
2765 | } | |
2766 | ||
2767 | static void r8152b_enter_oob(struct r8152 *tp) | |
2768 | { | |
45f4a19f | 2769 | u32 ocp_data; |
2770 | int i; | |
ac718b69 | 2771 | |
2772 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2773 | ocp_data &= ~NOW_IS_OOB; | |
2774 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2775 | ||
2776 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); | |
2777 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); | |
2778 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB); | |
2779 | ||
d70b1137 | 2780 | rtl_disable(tp); |
ac718b69 | 2781 | |
2782 | for (i = 0; i < 1000; i++) { | |
2783 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2784 | if (ocp_data & LINK_LIST_READY) | |
2785 | break; | |
8ddfa077 | 2786 | usleep_range(1000, 2000); |
ac718b69 | 2787 | } |
2788 | ||
2789 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2790 | ocp_data |= RE_INIT_LL; | |
2791 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2792 | ||
2793 | for (i = 0; i < 1000; i++) { | |
2794 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2795 | if (ocp_data & LINK_LIST_READY) | |
2796 | break; | |
8ddfa077 | 2797 | usleep_range(1000, 2000); |
ac718b69 | 2798 | } |
2799 | ||
2800 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); | |
2801 | ||
c5554298 | 2802 | rtl_rx_vlan_en(tp, true); |
ac718b69 | 2803 | |
2804 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); | |
2805 | ocp_data |= ALDPS_PROXY_MODE; | |
2806 | ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); | |
2807 | ||
2808 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2809 | ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; | |
2810 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2811 | ||
00a5e360 | 2812 | rxdy_gated_en(tp, false); |
ac718b69 | 2813 | |
2814 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2815 | ocp_data |= RCR_APM | RCR_AM | RCR_AB; | |
2816 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2817 | } | |
2818 | ||
e6449539 | 2819 | static void r8153_aldps_en(struct r8152 *tp, bool enable) |
2820 | { | |
2821 | u16 data; | |
2822 | ||
2823 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
2824 | if (enable) { | |
2825 | data |= EN_ALDPS; | |
2826 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
2827 | } else { | |
2828 | data &= ~EN_ALDPS; | |
2829 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
2830 | msleep(20); | |
2831 | } | |
2832 | } | |
2833 | ||
2834 | static void r8153_eee_en(struct r8152 *tp, bool enable) | |
2835 | { | |
2836 | u32 ocp_data; | |
2837 | u16 config; | |
2838 | ||
2839 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); | |
2840 | config = ocp_reg_read(tp, OCP_EEE_CFG); | |
2841 | ||
2842 | if (enable) { | |
2843 | ocp_data |= EEE_RX_EN | EEE_TX_EN; | |
2844 | config |= EEE10_EN; | |
2845 | } else { | |
2846 | ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); | |
2847 | config &= ~EEE10_EN; | |
2848 | } | |
2849 | ||
2850 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); | |
2851 | ocp_reg_write(tp, OCP_EEE_CFG, config); | |
2852 | } | |
2853 | ||
43779f8d | 2854 | static void r8153_hw_phy_cfg(struct r8152 *tp) |
2855 | { | |
2856 | u32 ocp_data; | |
2857 | u16 data; | |
2858 | ||
d768c61b | 2859 | /* disable ALDPS before updating the PHY parameters */ |
2860 | r8153_aldps_en(tp, false); | |
fb02eb4a | 2861 | |
d768c61b | 2862 | /* disable EEE before updating the PHY parameters */ |
2863 | r8153_eee_en(tp, false); | |
2864 | ocp_reg_write(tp, OCP_EEE_ADV, 0); | |
43779f8d | 2865 | |
2866 | if (tp->version == RTL_VER_03) { | |
2867 | data = ocp_reg_read(tp, OCP_EEE_CFG); | |
2868 | data &= ~CTAP_SHORT_EN; | |
2869 | ocp_reg_write(tp, OCP_EEE_CFG, data); | |
2870 | } | |
2871 | ||
2872 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
2873 | data |= EEE_CLKDIV_EN; | |
2874 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
2875 | ||
2876 | data = ocp_reg_read(tp, OCP_DOWN_SPEED); | |
2877 | data |= EN_10M_BGOFF; | |
2878 | ocp_reg_write(tp, OCP_DOWN_SPEED, data); | |
2879 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
2880 | data |= EN_10M_PLLOFF; | |
2881 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
b4d99def | 2882 | sram_write(tp, SRAM_IMPEDANCE, 0x0b13); |
43779f8d | 2883 | |
2884 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); | |
2885 | ocp_data |= PFM_PWM_SWITCH; | |
2886 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); | |
2887 | ||
b4d99def | 2888 | /* Enable LPF corner auto tune */ |
2889 | sram_write(tp, SRAM_LPF_CFG, 0xf70f); | |
43779f8d | 2890 | |
b4d99def | 2891 | /* Adjust 10M Amplitude */ |
2892 | sram_write(tp, SRAM_10M_AMP1, 0x00af); | |
2893 | sram_write(tp, SRAM_10M_AMP2, 0x0208); | |
aa66a5f1 | 2894 | |
af0287ec | 2895 | r8153_eee_en(tp, true); |
2896 | ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX); | |
2897 | ||
ef39df8e | 2898 | r8153_aldps_en(tp, true); |
2899 | r8152b_enable_fc(tp); | |
2900 | ||
aa66a5f1 | 2901 | set_bit(PHY_RESET, &tp->flags); |
43779f8d | 2902 | } |
2903 | ||
43779f8d | 2904 | static void r8153_first_init(struct r8152 *tp) |
2905 | { | |
2906 | u32 ocp_data; | |
2907 | int i; | |
2908 | ||
134f98bc | 2909 | r8153_mac_clk_spd(tp, false); |
00a5e360 | 2910 | rxdy_gated_en(tp, true); |
43779f8d | 2911 | r8153_teredo_off(tp); |
2912 | ||
2913 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2914 | ocp_data &= ~RCR_ACPT_ALL; | |
2915 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2916 | ||
43779f8d | 2917 | rtl8152_nic_reset(tp); |
93fe9b18 | 2918 | rtl_reset_bmu(tp); |
43779f8d | 2919 | |
2920 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2921 | ocp_data &= ~NOW_IS_OOB; | |
2922 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2923 | ||
2924 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2925 | ocp_data &= ~MCU_BORW_EN; | |
2926 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2927 | ||
2928 | for (i = 0; i < 1000; i++) { | |
2929 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2930 | if (ocp_data & LINK_LIST_READY) | |
2931 | break; | |
8ddfa077 | 2932 | usleep_range(1000, 2000); |
43779f8d | 2933 | } |
2934 | ||
2935 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2936 | ocp_data |= RE_INIT_LL; | |
2937 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2938 | ||
2939 | for (i = 0; i < 1000; i++) { | |
2940 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2941 | if (ocp_data & LINK_LIST_READY) | |
2942 | break; | |
8ddfa077 | 2943 | usleep_range(1000, 2000); |
43779f8d | 2944 | } |
2945 | ||
c5554298 | 2946 | rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); |
43779f8d | 2947 | |
210c4f70 | 2948 | ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + CRC_SIZE; |
2949 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data); | |
69b4b7a4 | 2950 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO); |
43779f8d | 2951 | |
2952 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); | |
2953 | ocp_data |= TCR0_AUTO_FIFO; | |
2954 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); | |
2955 | ||
2956 | rtl8152_nic_reset(tp); | |
2957 | ||
2958 | /* rx share fifo credit full threshold */ | |
2959 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); | |
2960 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL); | |
2961 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL); | |
2962 | /* TX share fifo free credit full threshold */ | |
2963 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2); | |
2964 | ||
9629e3c0 | 2965 | /* rx aggregation */ |
43779f8d | 2966 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); |
e90fba8d | 2967 | ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); |
43779f8d | 2968 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); |
2969 | } | |
2970 | ||
2971 | static void r8153_enter_oob(struct r8152 *tp) | |
2972 | { | |
2973 | u32 ocp_data; | |
2974 | int i; | |
2975 | ||
134f98bc | 2976 | r8153_mac_clk_spd(tp, true); |
2977 | ||
43779f8d | 2978 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); |
2979 | ocp_data &= ~NOW_IS_OOB; | |
2980 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2981 | ||
d70b1137 | 2982 | rtl_disable(tp); |
93fe9b18 | 2983 | rtl_reset_bmu(tp); |
43779f8d | 2984 | |
2985 | for (i = 0; i < 1000; i++) { | |
2986 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2987 | if (ocp_data & LINK_LIST_READY) | |
2988 | break; | |
8ddfa077 | 2989 | usleep_range(1000, 2000); |
43779f8d | 2990 | } |
2991 | ||
2992 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2993 | ocp_data |= RE_INIT_LL; | |
2994 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2995 | ||
2996 | for (i = 0; i < 1000; i++) { | |
2997 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2998 | if (ocp_data & LINK_LIST_READY) | |
2999 | break; | |
8ddfa077 | 3000 | usleep_range(1000, 2000); |
43779f8d | 3001 | } |
3002 | ||
210c4f70 | 3003 | ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + CRC_SIZE; |
3004 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data); | |
43779f8d | 3005 | |
43779f8d | 3006 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); |
3007 | ocp_data &= ~TEREDO_WAKE_MASK; | |
3008 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); | |
3009 | ||
c5554298 | 3010 | rtl_rx_vlan_en(tp, true); |
43779f8d | 3011 | |
3012 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); | |
3013 | ocp_data |= ALDPS_PROXY_MODE; | |
3014 | ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); | |
3015 | ||
3016 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
3017 | ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; | |
3018 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
3019 | ||
00a5e360 | 3020 | rxdy_gated_en(tp, false); |
43779f8d | 3021 | |
3022 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
3023 | ocp_data |= RCR_APM | RCR_AM | RCR_AB; | |
3024 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
3025 | } | |
3026 | ||
d70b1137 | 3027 | static void rtl8153_disable(struct r8152 *tp) |
3028 | { | |
cda9fb01 | 3029 | r8153_aldps_en(tp, false); |
d70b1137 | 3030 | rtl_disable(tp); |
93fe9b18 | 3031 | rtl_reset_bmu(tp); |
cda9fb01 | 3032 | r8153_aldps_en(tp, true); |
d70b1137 | 3033 | } |
3034 | ||
ac718b69 | 3035 | static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex) |
3036 | { | |
43779f8d | 3037 | u16 bmcr, anar, gbcr; |
ac718b69 | 3038 | int ret = 0; |
3039 | ||
ac718b69 | 3040 | anar = r8152_mdio_read(tp, MII_ADVERTISE); |
3041 | anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | | |
3042 | ADVERTISE_100HALF | ADVERTISE_100FULL); | |
43779f8d | 3043 | if (tp->mii.supports_gmii) { |
3044 | gbcr = r8152_mdio_read(tp, MII_CTRL1000); | |
3045 | gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); | |
3046 | } else { | |
3047 | gbcr = 0; | |
3048 | } | |
ac718b69 | 3049 | |
3050 | if (autoneg == AUTONEG_DISABLE) { | |
3051 | if (speed == SPEED_10) { | |
3052 | bmcr = 0; | |
3053 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
3054 | } else if (speed == SPEED_100) { | |
3055 | bmcr = BMCR_SPEED100; | |
3056 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; | |
43779f8d | 3057 | } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { |
3058 | bmcr = BMCR_SPEED1000; | |
3059 | gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; | |
ac718b69 | 3060 | } else { |
3061 | ret = -EINVAL; | |
3062 | goto out; | |
3063 | } | |
3064 | ||
3065 | if (duplex == DUPLEX_FULL) | |
3066 | bmcr |= BMCR_FULLDPLX; | |
3067 | } else { | |
3068 | if (speed == SPEED_10) { | |
3069 | if (duplex == DUPLEX_FULL) | |
3070 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
3071 | else | |
3072 | anar |= ADVERTISE_10HALF; | |
3073 | } else if (speed == SPEED_100) { | |
3074 | if (duplex == DUPLEX_FULL) { | |
3075 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
3076 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; | |
3077 | } else { | |
3078 | anar |= ADVERTISE_10HALF; | |
3079 | anar |= ADVERTISE_100HALF; | |
3080 | } | |
43779f8d | 3081 | } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { |
3082 | if (duplex == DUPLEX_FULL) { | |
3083 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
3084 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; | |
3085 | gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; | |
3086 | } else { | |
3087 | anar |= ADVERTISE_10HALF; | |
3088 | anar |= ADVERTISE_100HALF; | |
3089 | gbcr |= ADVERTISE_1000HALF; | |
3090 | } | |
ac718b69 | 3091 | } else { |
3092 | ret = -EINVAL; | |
3093 | goto out; | |
3094 | } | |
3095 | ||
3096 | bmcr = BMCR_ANENABLE | BMCR_ANRESTART; | |
3097 | } | |
3098 | ||
fae56178 | 3099 | if (test_and_clear_bit(PHY_RESET, &tp->flags)) |
aa66a5f1 | 3100 | bmcr |= BMCR_RESET; |
3101 | ||
43779f8d | 3102 | if (tp->mii.supports_gmii) |
3103 | r8152_mdio_write(tp, MII_CTRL1000, gbcr); | |
3104 | ||
ac718b69 | 3105 | r8152_mdio_write(tp, MII_ADVERTISE, anar); |
3106 | r8152_mdio_write(tp, MII_BMCR, bmcr); | |
3107 | ||
fae56178 | 3108 | if (bmcr & BMCR_RESET) { |
aa66a5f1 | 3109 | int i; |
3110 | ||
aa66a5f1 | 3111 | for (i = 0; i < 50; i++) { |
3112 | msleep(20); | |
3113 | if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) | |
3114 | break; | |
3115 | } | |
3116 | } | |
3117 | ||
ac718b69 | 3118 | out: |
ac718b69 | 3119 | return ret; |
3120 | } | |
3121 | ||
d70b1137 | 3122 | static void rtl8152_up(struct r8152 *tp) |
3123 | { | |
3124 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
3125 | return; | |
3126 | ||
cda9fb01 | 3127 | r8152_aldps_en(tp, false); |
d70b1137 | 3128 | r8152b_exit_oob(tp); |
cda9fb01 | 3129 | r8152_aldps_en(tp, true); |
d70b1137 | 3130 | } |
3131 | ||
ac718b69 | 3132 | static void rtl8152_down(struct r8152 *tp) |
3133 | { | |
6871438c | 3134 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) { |
3135 | rtl_drop_queued_tx(tp); | |
3136 | return; | |
3137 | } | |
3138 | ||
00a5e360 | 3139 | r8152_power_cut_en(tp, false); |
cda9fb01 | 3140 | r8152_aldps_en(tp, false); |
ac718b69 | 3141 | r8152b_enter_oob(tp); |
cda9fb01 | 3142 | r8152_aldps_en(tp, true); |
ac718b69 | 3143 | } |
3144 | ||
d70b1137 | 3145 | static void rtl8153_up(struct r8152 *tp) |
3146 | { | |
3147 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
3148 | return; | |
3149 | ||
b214396f | 3150 | r8153_u1u2en(tp, false); |
cda9fb01 | 3151 | r8153_aldps_en(tp, false); |
d70b1137 | 3152 | r8153_first_init(tp); |
cda9fb01 | 3153 | r8153_aldps_en(tp, true); |
b214396f | 3154 | r8153_u2p3en(tp, true); |
3155 | r8153_u1u2en(tp, true); | |
d70b1137 | 3156 | } |
3157 | ||
43779f8d | 3158 | static void rtl8153_down(struct r8152 *tp) |
3159 | { | |
6871438c | 3160 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) { |
3161 | rtl_drop_queued_tx(tp); | |
3162 | return; | |
3163 | } | |
3164 | ||
b9702723 | 3165 | r8153_u1u2en(tp, false); |
b214396f | 3166 | r8153_u2p3en(tp, false); |
b9702723 | 3167 | r8153_power_cut_en(tp, false); |
cda9fb01 | 3168 | r8153_aldps_en(tp, false); |
43779f8d | 3169 | r8153_enter_oob(tp); |
cda9fb01 | 3170 | r8153_aldps_en(tp, true); |
43779f8d | 3171 | } |
3172 | ||
2dd49e0f | 3173 | static bool rtl8152_in_nway(struct r8152 *tp) |
3174 | { | |
3175 | u16 nway_state; | |
3176 | ||
3177 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000); | |
3178 | tp->ocp_base = 0x2000; | |
3179 | ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */ | |
3180 | nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a); | |
3181 | ||
3182 | /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */ | |
3183 | if (nway_state & 0xc000) | |
3184 | return false; | |
3185 | else | |
3186 | return true; | |
3187 | } | |
3188 | ||
3189 | static bool rtl8153_in_nway(struct r8152 *tp) | |
3190 | { | |
3191 | u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff; | |
3192 | ||
3193 | if (phy_state == TXDIS_STATE || phy_state == ABD_STATE) | |
3194 | return false; | |
3195 | else | |
3196 | return true; | |
3197 | } | |
3198 | ||
ac718b69 | 3199 | static void set_carrier(struct r8152 *tp) |
3200 | { | |
3201 | struct net_device *netdev = tp->netdev; | |
ce594e98 | 3202 | struct napi_struct *napi = &tp->napi; |
ac718b69 | 3203 | u8 speed; |
3204 | ||
3205 | speed = rtl8152_get_speed(tp); | |
3206 | ||
3207 | if (speed & LINK_STATUS) { | |
51d979fa | 3208 | if (!netif_carrier_ok(netdev)) { |
c81229c9 | 3209 | tp->rtl_ops.enable(tp); |
ac718b69 | 3210 | set_bit(RTL8152_SET_RX_MODE, &tp->flags); |
de9bf29d | 3211 | netif_stop_queue(netdev); |
ce594e98 | 3212 | napi_disable(napi); |
ac718b69 | 3213 | netif_carrier_on(netdev); |
aa2e0926 | 3214 | rtl_start_rx(tp); |
41cec84c | 3215 | napi_enable(&tp->napi); |
de9bf29d | 3216 | netif_wake_queue(netdev); |
3217 | netif_info(tp, link, netdev, "carrier on\n"); | |
2f25abe6 | 3218 | } else if (netif_queue_stopped(netdev) && |
3219 | skb_queue_len(&tp->tx_queue) < tp->tx_qlen) { | |
3220 | netif_wake_queue(netdev); | |
ac718b69 | 3221 | } |
3222 | } else { | |
51d979fa | 3223 | if (netif_carrier_ok(netdev)) { |
ac718b69 | 3224 | netif_carrier_off(netdev); |
ce594e98 | 3225 | napi_disable(napi); |
c81229c9 | 3226 | tp->rtl_ops.disable(tp); |
ce594e98 | 3227 | napi_enable(napi); |
de9bf29d | 3228 | netif_info(tp, link, netdev, "carrier off\n"); |
ac718b69 | 3229 | } |
3230 | } | |
ac718b69 | 3231 | } |
3232 | ||
3233 | static void rtl_work_func_t(struct work_struct *work) | |
3234 | { | |
3235 | struct r8152 *tp = container_of(work, struct r8152, schedule.work); | |
3236 | ||
a1f83fee | 3237 | /* If the device is unplugged or !netif_running(), the workqueue |
3238 | * doesn't need to wake the device, and could return directly. | |
3239 | */ | |
3240 | if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev)) | |
3241 | return; | |
3242 | ||
9a4be1bd | 3243 | if (usb_autopm_get_interface(tp->intf) < 0) |
3244 | return; | |
3245 | ||
ac718b69 | 3246 | if (!test_bit(WORK_ENABLE, &tp->flags)) |
3247 | goto out1; | |
3248 | ||
b5403273 | 3249 | if (!mutex_trylock(&tp->control)) { |
3250 | schedule_delayed_work(&tp->schedule, 0); | |
3251 | goto out1; | |
3252 | } | |
3253 | ||
216a8349 | 3254 | if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags)) |
40a82917 | 3255 | set_carrier(tp); |
ac718b69 | 3256 | |
216a8349 | 3257 | if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags)) |
ac718b69 | 3258 | _rtl8152_set_rx_mode(tp->netdev); |
3259 | ||
d823ab68 | 3260 | /* don't schedule napi before linking */ |
216a8349 | 3261 | if (test_and_clear_bit(SCHEDULE_NAPI, &tp->flags) && |
3262 | netif_carrier_ok(tp->netdev)) | |
d823ab68 | 3263 | napi_schedule(&tp->napi); |
aa66a5f1 | 3264 | |
b5403273 | 3265 | mutex_unlock(&tp->control); |
3266 | ||
ac718b69 | 3267 | out1: |
9a4be1bd | 3268 | usb_autopm_put_interface(tp->intf); |
ac718b69 | 3269 | } |
3270 | ||
a028a9e0 | 3271 | static void rtl_hw_phy_work_func_t(struct work_struct *work) |
3272 | { | |
3273 | struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work); | |
3274 | ||
3275 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
3276 | return; | |
3277 | ||
3278 | if (usb_autopm_get_interface(tp->intf) < 0) | |
3279 | return; | |
3280 | ||
3281 | mutex_lock(&tp->control); | |
3282 | ||
3283 | tp->rtl_ops.hw_phy_cfg(tp); | |
3284 | ||
aa7e26b6 | 3285 | rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex); |
9d21c0d8 | 3286 | |
a028a9e0 | 3287 | mutex_unlock(&tp->control); |
3288 | ||
3289 | usb_autopm_put_interface(tp->intf); | |
3290 | } | |
3291 | ||
5ee3c60c | 3292 | #ifdef CONFIG_PM_SLEEP |
3293 | static int rtl_notifier(struct notifier_block *nb, unsigned long action, | |
3294 | void *data) | |
3295 | { | |
3296 | struct r8152 *tp = container_of(nb, struct r8152, pm_notifier); | |
3297 | ||
3298 | switch (action) { | |
3299 | case PM_HIBERNATION_PREPARE: | |
3300 | case PM_SUSPEND_PREPARE: | |
3301 | usb_autopm_get_interface(tp->intf); | |
3302 | break; | |
3303 | ||
3304 | case PM_POST_HIBERNATION: | |
3305 | case PM_POST_SUSPEND: | |
3306 | usb_autopm_put_interface(tp->intf); | |
3307 | break; | |
3308 | ||
3309 | case PM_POST_RESTORE: | |
3310 | case PM_RESTORE_PREPARE: | |
3311 | default: | |
3312 | break; | |
3313 | } | |
3314 | ||
3315 | return NOTIFY_DONE; | |
3316 | } | |
3317 | #endif | |
3318 | ||
ac718b69 | 3319 | static int rtl8152_open(struct net_device *netdev) |
3320 | { | |
3321 | struct r8152 *tp = netdev_priv(netdev); | |
3322 | int res = 0; | |
3323 | ||
7e9da481 | 3324 | res = alloc_all_mem(tp); |
3325 | if (res) | |
3326 | goto out; | |
3327 | ||
9a4be1bd | 3328 | res = usb_autopm_get_interface(tp->intf); |
ca0a7531 GR |
3329 | if (res < 0) |
3330 | goto out_free; | |
9a4be1bd | 3331 | |
b5403273 | 3332 | mutex_lock(&tp->control); |
3333 | ||
7e9da481 | 3334 | tp->rtl_ops.up(tp); |
3335 | ||
3d55f44f | 3336 | netif_carrier_off(netdev); |
3337 | netif_start_queue(netdev); | |
3338 | set_bit(WORK_ENABLE, &tp->flags); | |
db8515ef | 3339 | |
40a82917 | 3340 | res = usb_submit_urb(tp->intr_urb, GFP_KERNEL); |
3341 | if (res) { | |
3342 | if (res == -ENODEV) | |
3343 | netif_device_detach(tp->netdev); | |
4a8deae2 HW |
3344 | netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n", |
3345 | res); | |
ca0a7531 | 3346 | goto out_unlock; |
ac718b69 | 3347 | } |
ca0a7531 | 3348 | napi_enable(&tp->napi); |
ac718b69 | 3349 | |
b5403273 | 3350 | mutex_unlock(&tp->control); |
3351 | ||
9a4be1bd | 3352 | usb_autopm_put_interface(tp->intf); |
5ee3c60c | 3353 | #ifdef CONFIG_PM_SLEEP |
3354 | tp->pm_notifier.notifier_call = rtl_notifier; | |
3355 | register_pm_notifier(&tp->pm_notifier); | |
3356 | #endif | |
ca0a7531 | 3357 | return 0; |
ac718b69 | 3358 | |
ca0a7531 GR |
3359 | out_unlock: |
3360 | mutex_unlock(&tp->control); | |
3361 | usb_autopm_put_interface(tp->intf); | |
3362 | out_free: | |
3363 | free_all_mem(tp); | |
7e9da481 | 3364 | out: |
ac718b69 | 3365 | return res; |
3366 | } | |
3367 | ||
3368 | static int rtl8152_close(struct net_device *netdev) | |
3369 | { | |
3370 | struct r8152 *tp = netdev_priv(netdev); | |
3371 | int res = 0; | |
3372 | ||
5ee3c60c | 3373 | #ifdef CONFIG_PM_SLEEP |
3374 | unregister_pm_notifier(&tp->pm_notifier); | |
3375 | #endif | |
d823ab68 | 3376 | napi_disable(&tp->napi); |
ac718b69 | 3377 | clear_bit(WORK_ENABLE, &tp->flags); |
3d55f44f | 3378 | usb_kill_urb(tp->intr_urb); |
ac718b69 | 3379 | cancel_delayed_work_sync(&tp->schedule); |
3380 | netif_stop_queue(netdev); | |
9a4be1bd | 3381 | |
3382 | res = usb_autopm_get_interface(tp->intf); | |
53543db5 | 3383 | if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) { |
9a4be1bd | 3384 | rtl_drop_queued_tx(tp); |
d823ab68 | 3385 | rtl_stop_rx(tp); |
9a4be1bd | 3386 | } else { |
b5403273 | 3387 | mutex_lock(&tp->control); |
3388 | ||
9a4be1bd | 3389 | tp->rtl_ops.down(tp); |
b5403273 | 3390 | |
3391 | mutex_unlock(&tp->control); | |
3392 | ||
9a4be1bd | 3393 | usb_autopm_put_interface(tp->intf); |
3394 | } | |
ac718b69 | 3395 | |
7e9da481 | 3396 | free_all_mem(tp); |
3397 | ||
ac718b69 | 3398 | return res; |
3399 | } | |
3400 | ||
4f1d4d54 | 3401 | static void rtl_tally_reset(struct r8152 *tp) |
3402 | { | |
3403 | u32 ocp_data; | |
3404 | ||
3405 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY); | |
3406 | ocp_data |= TALLY_RESET; | |
3407 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data); | |
3408 | } | |
3409 | ||
ac718b69 | 3410 | static void r8152b_init(struct r8152 *tp) |
3411 | { | |
ebc2ec48 | 3412 | u32 ocp_data; |
2dd436da | 3413 | u16 data; |
ac718b69 | 3414 | |
6871438c | 3415 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
3416 | return; | |
3417 | ||
2dd436da | 3418 | data = r8152_mdio_read(tp, MII_BMCR); |
3419 | if (data & BMCR_PDOWN) { | |
3420 | data &= ~BMCR_PDOWN; | |
3421 | r8152_mdio_write(tp, MII_BMCR, data); | |
3422 | } | |
3423 | ||
cda9fb01 | 3424 | r8152_aldps_en(tp, false); |
d70b1137 | 3425 | |
ac718b69 | 3426 | if (tp->version == RTL_VER_01) { |
3427 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); | |
3428 | ocp_data &= ~LED_MODE_MASK; | |
3429 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); | |
3430 | } | |
3431 | ||
00a5e360 | 3432 | r8152_power_cut_en(tp, false); |
ac718b69 | 3433 | |
ac718b69 | 3434 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); |
3435 | ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH; | |
3436 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); | |
3437 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL); | |
3438 | ocp_data &= ~MCU_CLK_RATIO_MASK; | |
3439 | ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN; | |
3440 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data); | |
3441 | ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK | | |
3442 | SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK; | |
3443 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data); | |
3444 | ||
4f1d4d54 | 3445 | rtl_tally_reset(tp); |
ac718b69 | 3446 | |
ebc2ec48 | 3447 | /* enable rx aggregation */ |
ac718b69 | 3448 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); |
e90fba8d | 3449 | ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); |
ac718b69 | 3450 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); |
3451 | } | |
3452 | ||
43779f8d | 3453 | static void r8153_init(struct r8152 *tp) |
3454 | { | |
3455 | u32 ocp_data; | |
2dd436da | 3456 | u16 data; |
43779f8d | 3457 | int i; |
3458 | ||
6871438c | 3459 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
3460 | return; | |
3461 | ||
b9702723 | 3462 | r8153_u1u2en(tp, false); |
43779f8d | 3463 | |
3464 | for (i = 0; i < 500; i++) { | |
3465 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & | |
3466 | AUTOLOAD_DONE) | |
3467 | break; | |
3468 | msleep(20); | |
3469 | } | |
3470 | ||
c564b871 | 3471 | data = r8153_phy_status(tp, 0); |
43779f8d | 3472 | |
2dd436da | 3473 | if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 || |
3474 | tp->version == RTL_VER_05) | |
3475 | ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L); | |
3476 | ||
3477 | data = r8152_mdio_read(tp, MII_BMCR); | |
3478 | if (data & BMCR_PDOWN) { | |
3479 | data &= ~BMCR_PDOWN; | |
3480 | r8152_mdio_write(tp, MII_BMCR, data); | |
3481 | } | |
3482 | ||
c564b871 | 3483 | data = r8153_phy_status(tp, PHY_STAT_LAN_ON); |
2dd436da | 3484 | |
b9702723 | 3485 | r8153_u2p3en(tp, false); |
43779f8d | 3486 | |
65bab84c | 3487 | if (tp->version == RTL_VER_04) { |
3488 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2); | |
3489 | ocp_data &= ~pwd_dn_scale_mask; | |
3490 | ocp_data |= pwd_dn_scale(96); | |
3491 | ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data); | |
3492 | ||
3493 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY); | |
3494 | ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND; | |
3495 | ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data); | |
3496 | } else if (tp->version == RTL_VER_05) { | |
3497 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0); | |
3498 | ocp_data &= ~ECM_ALDPS; | |
3499 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data); | |
3500 | ||
fb02eb4a | 3501 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); |
3502 | if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) | |
3503 | ocp_data &= ~DYNAMIC_BURST; | |
3504 | else | |
3505 | ocp_data |= DYNAMIC_BURST; | |
3506 | ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); | |
3507 | } else if (tp->version == RTL_VER_06) { | |
65bab84c | 3508 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); |
3509 | if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) | |
3510 | ocp_data &= ~DYNAMIC_BURST; | |
3511 | else | |
3512 | ocp_data |= DYNAMIC_BURST; | |
3513 | ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); | |
3514 | } | |
3515 | ||
3516 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2); | |
3517 | ocp_data |= EP4_FULL_FC; | |
3518 | ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data); | |
3519 | ||
43779f8d | 3520 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL); |
3521 | ocp_data &= ~TIMER11_EN; | |
3522 | ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data); | |
3523 | ||
43779f8d | 3524 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); |
3525 | ocp_data &= ~LED_MODE_MASK; | |
3526 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); | |
3527 | ||
65bab84c | 3528 | ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM; |
2b84af94 | 3529 | if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER) |
43779f8d | 3530 | ocp_data |= LPM_TIMER_500MS; |
34203e25 | 3531 | else |
3532 | ocp_data |= LPM_TIMER_500US; | |
43779f8d | 3533 | ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data); |
3534 | ||
3535 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2); | |
3536 | ocp_data &= ~SEN_VAL_MASK; | |
3537 | ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE; | |
3538 | ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data); | |
3539 | ||
65bab84c | 3540 | ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001); |
3541 | ||
b9702723 | 3542 | r8153_power_cut_en(tp, false); |
3543 | r8153_u1u2en(tp, true); | |
134f98bc | 3544 | r8153_mac_clk_spd(tp, false); |
ee4761c1 | 3545 | usb_enable_lpm(tp->udev); |
43779f8d | 3546 | |
43779f8d | 3547 | |
4f1d4d54 | 3548 | rtl_tally_reset(tp); |
b214396f | 3549 | r8153_u2p3en(tp, true); |
43779f8d | 3550 | } |
3551 | ||
e501139a | 3552 | static int rtl8152_pre_reset(struct usb_interface *intf) |
3553 | { | |
3554 | struct r8152 *tp = usb_get_intfdata(intf); | |
3555 | struct net_device *netdev; | |
3556 | ||
3557 | if (!tp) | |
3558 | return 0; | |
3559 | ||
3560 | netdev = tp->netdev; | |
3561 | if (!netif_running(netdev)) | |
3562 | return 0; | |
3563 | ||
de9bf29d | 3564 | netif_stop_queue(netdev); |
e501139a | 3565 | napi_disable(&tp->napi); |
3566 | clear_bit(WORK_ENABLE, &tp->flags); | |
3567 | usb_kill_urb(tp->intr_urb); | |
3568 | cancel_delayed_work_sync(&tp->schedule); | |
3569 | if (netif_carrier_ok(netdev)) { | |
e501139a | 3570 | mutex_lock(&tp->control); |
3571 | tp->rtl_ops.disable(tp); | |
3572 | mutex_unlock(&tp->control); | |
3573 | } | |
3574 | ||
3575 | return 0; | |
3576 | } | |
3577 | ||
3578 | static int rtl8152_post_reset(struct usb_interface *intf) | |
3579 | { | |
3580 | struct r8152 *tp = usb_get_intfdata(intf); | |
3581 | struct net_device *netdev; | |
3582 | ||
3583 | if (!tp) | |
3584 | return 0; | |
3585 | ||
3586 | netdev = tp->netdev; | |
3587 | if (!netif_running(netdev)) | |
3588 | return 0; | |
3589 | ||
3590 | set_bit(WORK_ENABLE, &tp->flags); | |
3591 | if (netif_carrier_ok(netdev)) { | |
3592 | mutex_lock(&tp->control); | |
3593 | tp->rtl_ops.enable(tp); | |
2c561b2b | 3594 | rtl_start_rx(tp); |
e501139a | 3595 | rtl8152_set_rx_mode(netdev); |
3596 | mutex_unlock(&tp->control); | |
e501139a | 3597 | } |
3598 | ||
3599 | napi_enable(&tp->napi); | |
de9bf29d | 3600 | netif_wake_queue(netdev); |
2c561b2b | 3601 | usb_submit_urb(tp->intr_urb, GFP_KERNEL); |
e501139a | 3602 | |
7489bdad | 3603 | if (!list_empty(&tp->rx_done)) |
3604 | napi_schedule(&tp->napi); | |
e501139a | 3605 | |
3606 | return 0; | |
43779f8d | 3607 | } |
3608 | ||
2dd49e0f | 3609 | static bool delay_autosuspend(struct r8152 *tp) |
3610 | { | |
3611 | bool sw_linking = !!netif_carrier_ok(tp->netdev); | |
3612 | bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS); | |
3613 | ||
3614 | /* This means a linking change occurs and the driver doesn't detect it, | |
3615 | * yet. If the driver has disabled tx/rx and hw is linking on, the | |
3616 | * device wouldn't wake up by receiving any packet. | |
3617 | */ | |
3618 | if (work_busy(&tp->schedule.work) || sw_linking != hw_linking) | |
3619 | return true; | |
3620 | ||
3621 | /* If the linking down is occurred by nway, the device may miss the | |
3622 | * linking change event. And it wouldn't wake when linking on. | |
3623 | */ | |
3624 | if (!sw_linking && tp->rtl_ops.in_nway(tp)) | |
3625 | return true; | |
6a0b76c0 | 3626 | else if (!skb_queue_empty(&tp->tx_queue)) |
3627 | return true; | |
2dd49e0f | 3628 | else |
3629 | return false; | |
3630 | } | |
3631 | ||
a9c54ad2 | 3632 | static int rtl8152_runtime_suspend(struct r8152 *tp) |
ac718b69 | 3633 | { |
6cc69f2a | 3634 | struct net_device *netdev = tp->netdev; |
3635 | int ret = 0; | |
ac718b69 | 3636 | |
26afec39 | 3637 | set_bit(SELECTIVE_SUSPEND, &tp->flags); |
3638 | smp_mb__after_atomic(); | |
3639 | ||
8fb28061 | 3640 | if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) { |
75dc692e | 3641 | u32 rcr = 0; |
3642 | ||
8fb28061 | 3643 | if (delay_autosuspend(tp)) { |
26afec39 | 3644 | clear_bit(SELECTIVE_SUSPEND, &tp->flags); |
3645 | smp_mb__after_atomic(); | |
6cc69f2a | 3646 | ret = -EBUSY; |
3647 | goto out1; | |
3648 | } | |
3649 | ||
75dc692e | 3650 | if (netif_carrier_ok(netdev)) { |
3651 | u32 ocp_data; | |
3652 | ||
3653 | rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
3654 | ocp_data = rcr & ~RCR_ACPT_ALL; | |
3655 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
3656 | rxdy_gated_en(tp, true); | |
3657 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, | |
3658 | PLA_OOB_CTRL); | |
3659 | if (!(ocp_data & RXFIFO_EMPTY)) { | |
3660 | rxdy_gated_en(tp, false); | |
3661 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr); | |
26afec39 | 3662 | clear_bit(SELECTIVE_SUSPEND, &tp->flags); |
3663 | smp_mb__after_atomic(); | |
75dc692e | 3664 | ret = -EBUSY; |
3665 | goto out1; | |
3666 | } | |
3667 | } | |
3668 | ||
8fb28061 | 3669 | clear_bit(WORK_ENABLE, &tp->flags); |
3670 | usb_kill_urb(tp->intr_urb); | |
75dc692e | 3671 | |
8fb28061 | 3672 | tp->rtl_ops.autosuspend_en(tp, true); |
75dc692e | 3673 | |
3674 | if (netif_carrier_ok(netdev)) { | |
ce594e98 | 3675 | struct napi_struct *napi = &tp->napi; |
3676 | ||
3677 | napi_disable(napi); | |
75dc692e | 3678 | rtl_stop_rx(tp); |
3679 | rxdy_gated_en(tp, false); | |
3680 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr); | |
ce594e98 | 3681 | napi_enable(napi); |
75dc692e | 3682 | } |
6cc69f2a | 3683 | } |
ac718b69 | 3684 | |
8fb28061 | 3685 | out1: |
3686 | return ret; | |
3687 | } | |
3688 | ||
3689 | static int rtl8152_system_suspend(struct r8152 *tp) | |
3690 | { | |
3691 | struct net_device *netdev = tp->netdev; | |
3692 | int ret = 0; | |
3693 | ||
3694 | netif_device_detach(netdev); | |
3695 | ||
e3bd1a81 | 3696 | if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) { |
ce594e98 | 3697 | struct napi_struct *napi = &tp->napi; |
3698 | ||
ac718b69 | 3699 | clear_bit(WORK_ENABLE, &tp->flags); |
40a82917 | 3700 | usb_kill_urb(tp->intr_urb); |
ce594e98 | 3701 | napi_disable(napi); |
8fb28061 | 3702 | cancel_delayed_work_sync(&tp->schedule); |
3703 | tp->rtl_ops.down(tp); | |
ce594e98 | 3704 | napi_enable(napi); |
ac718b69 | 3705 | } |
8fb28061 | 3706 | |
3707 | return ret; | |
3708 | } | |
3709 | ||
3710 | static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message) | |
3711 | { | |
3712 | struct r8152 *tp = usb_get_intfdata(intf); | |
3713 | int ret; | |
3714 | ||
3715 | mutex_lock(&tp->control); | |
3716 | ||
3717 | if (PMSG_IS_AUTO(message)) | |
a9c54ad2 | 3718 | ret = rtl8152_runtime_suspend(tp); |
8fb28061 | 3719 | else |
3720 | ret = rtl8152_system_suspend(tp); | |
3721 | ||
b5403273 | 3722 | mutex_unlock(&tp->control); |
3723 | ||
6cc69f2a | 3724 | return ret; |
ac718b69 | 3725 | } |
3726 | ||
3727 | static int rtl8152_resume(struct usb_interface *intf) | |
3728 | { | |
3729 | struct r8152 *tp = usb_get_intfdata(intf); | |
ce594e98 | 3730 | struct net_device *netdev = tp->netdev; |
ac718b69 | 3731 | |
b5403273 | 3732 | mutex_lock(&tp->control); |
3733 | ||
9a4be1bd | 3734 | if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) { |
3735 | tp->rtl_ops.init(tp); | |
a028a9e0 | 3736 | queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0); |
ce594e98 | 3737 | netif_device_attach(netdev); |
9a4be1bd | 3738 | } |
3739 | ||
ce594e98 | 3740 | if (netif_running(netdev) && netdev->flags & IFF_UP) { |
9a4be1bd | 3741 | if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { |
ce594e98 | 3742 | struct napi_struct *napi = &tp->napi; |
3743 | ||
2609af19 | 3744 | tp->rtl_ops.autosuspend_en(tp, false); |
ce594e98 | 3745 | napi_disable(napi); |
445f7f4d | 3746 | set_bit(WORK_ENABLE, &tp->flags); |
6f14f443 | 3747 | if (netif_carrier_ok(netdev)) { |
2f25abe6 | 3748 | if (rtl8152_get_speed(tp) & LINK_STATUS) { |
3749 | rtl_start_rx(tp); | |
3750 | } else { | |
6f14f443 | 3751 | netif_carrier_off(netdev); |
2f25abe6 | 3752 | tp->rtl_ops.disable(tp); |
6f14f443 | 3753 | netif_info(tp, link, netdev, |
2f25abe6 | 3754 | "linking down\n"); |
3755 | } | |
3756 | } | |
ce594e98 | 3757 | napi_enable(napi); |
26afec39 | 3758 | clear_bit(SELECTIVE_SUSPEND, &tp->flags); |
3759 | smp_mb__after_atomic(); | |
7489bdad | 3760 | if (!list_empty(&tp->rx_done)) |
3761 | napi_schedule(&tp->napi); | |
9a4be1bd | 3762 | } else { |
3763 | tp->rtl_ops.up(tp); | |
ce594e98 | 3764 | netif_carrier_off(netdev); |
445f7f4d | 3765 | set_bit(WORK_ENABLE, &tp->flags); |
9a4be1bd | 3766 | } |
40a82917 | 3767 | usb_submit_urb(tp->intr_urb, GFP_KERNEL); |
923e1ee3 | 3768 | } else if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { |
ce594e98 | 3769 | if (netdev->flags & IFF_UP) |
2609af19 | 3770 | tp->rtl_ops.autosuspend_en(tp, false); |
923e1ee3 | 3771 | clear_bit(SELECTIVE_SUSPEND, &tp->flags); |
ac718b69 | 3772 | } |
3773 | ||
b5403273 | 3774 | mutex_unlock(&tp->control); |
3775 | ||
ac718b69 | 3776 | return 0; |
3777 | } | |
3778 | ||
7ec2541a | 3779 | static int rtl8152_reset_resume(struct usb_interface *intf) |
3780 | { | |
3781 | struct r8152 *tp = usb_get_intfdata(intf); | |
3782 | ||
3783 | clear_bit(SELECTIVE_SUSPEND, &tp->flags); | |
3784 | return rtl8152_resume(intf); | |
3785 | } | |
3786 | ||
21ff2e89 | 3787 | static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
3788 | { | |
3789 | struct r8152 *tp = netdev_priv(dev); | |
3790 | ||
9a4be1bd | 3791 | if (usb_autopm_get_interface(tp->intf) < 0) |
3792 | return; | |
3793 | ||
7daed8dc | 3794 | if (!rtl_can_wakeup(tp)) { |
3795 | wol->supported = 0; | |
3796 | wol->wolopts = 0; | |
3797 | } else { | |
3798 | mutex_lock(&tp->control); | |
3799 | wol->supported = WAKE_ANY; | |
3800 | wol->wolopts = __rtl_get_wol(tp); | |
3801 | mutex_unlock(&tp->control); | |
3802 | } | |
b5403273 | 3803 | |
9a4be1bd | 3804 | usb_autopm_put_interface(tp->intf); |
21ff2e89 | 3805 | } |
3806 | ||
3807 | static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
3808 | { | |
3809 | struct r8152 *tp = netdev_priv(dev); | |
9a4be1bd | 3810 | int ret; |
3811 | ||
7daed8dc | 3812 | if (!rtl_can_wakeup(tp)) |
3813 | return -EOPNOTSUPP; | |
3814 | ||
9a4be1bd | 3815 | ret = usb_autopm_get_interface(tp->intf); |
3816 | if (ret < 0) | |
3817 | goto out_set_wol; | |
21ff2e89 | 3818 | |
b5403273 | 3819 | mutex_lock(&tp->control); |
3820 | ||
21ff2e89 | 3821 | __rtl_set_wol(tp, wol->wolopts); |
3822 | tp->saved_wolopts = wol->wolopts & WAKE_ANY; | |
3823 | ||
b5403273 | 3824 | mutex_unlock(&tp->control); |
3825 | ||
9a4be1bd | 3826 | usb_autopm_put_interface(tp->intf); |
3827 | ||
3828 | out_set_wol: | |
3829 | return ret; | |
21ff2e89 | 3830 | } |
3831 | ||
a5ec27c1 | 3832 | static u32 rtl8152_get_msglevel(struct net_device *dev) |
3833 | { | |
3834 | struct r8152 *tp = netdev_priv(dev); | |
3835 | ||
3836 | return tp->msg_enable; | |
3837 | } | |
3838 | ||
3839 | static void rtl8152_set_msglevel(struct net_device *dev, u32 value) | |
3840 | { | |
3841 | struct r8152 *tp = netdev_priv(dev); | |
3842 | ||
3843 | tp->msg_enable = value; | |
3844 | } | |
3845 | ||
ac718b69 | 3846 | static void rtl8152_get_drvinfo(struct net_device *netdev, |
3847 | struct ethtool_drvinfo *info) | |
3848 | { | |
3849 | struct r8152 *tp = netdev_priv(netdev); | |
3850 | ||
b0b46c77 | 3851 | strlcpy(info->driver, MODULENAME, sizeof(info->driver)); |
3852 | strlcpy(info->version, DRIVER_VERSION, sizeof(info->version)); | |
ac718b69 | 3853 | usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info)); |
3854 | } | |
3855 | ||
3856 | static | |
06144dcf PR |
3857 | int rtl8152_get_link_ksettings(struct net_device *netdev, |
3858 | struct ethtool_link_ksettings *cmd) | |
ac718b69 | 3859 | { |
3860 | struct r8152 *tp = netdev_priv(netdev); | |
8d4a4d72 | 3861 | int ret; |
ac718b69 | 3862 | |
3863 | if (!tp->mii.mdio_read) | |
3864 | return -EOPNOTSUPP; | |
3865 | ||
8d4a4d72 | 3866 | ret = usb_autopm_get_interface(tp->intf); |
3867 | if (ret < 0) | |
3868 | goto out; | |
3869 | ||
b5403273 | 3870 | mutex_lock(&tp->control); |
3871 | ||
82c01a84 | 3872 | mii_ethtool_get_link_ksettings(&tp->mii, cmd); |
8d4a4d72 | 3873 | |
b5403273 | 3874 | mutex_unlock(&tp->control); |
3875 | ||
8d4a4d72 | 3876 | usb_autopm_put_interface(tp->intf); |
3877 | ||
3878 | out: | |
3879 | return ret; | |
ac718b69 | 3880 | } |
3881 | ||
06144dcf PR |
3882 | static int rtl8152_set_link_ksettings(struct net_device *dev, |
3883 | const struct ethtool_link_ksettings *cmd) | |
ac718b69 | 3884 | { |
3885 | struct r8152 *tp = netdev_priv(dev); | |
9a4be1bd | 3886 | int ret; |
3887 | ||
3888 | ret = usb_autopm_get_interface(tp->intf); | |
3889 | if (ret < 0) | |
3890 | goto out; | |
ac718b69 | 3891 | |
b5403273 | 3892 | mutex_lock(&tp->control); |
3893 | ||
06144dcf PR |
3894 | ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed, |
3895 | cmd->base.duplex); | |
aa7e26b6 | 3896 | if (!ret) { |
06144dcf PR |
3897 | tp->autoneg = cmd->base.autoneg; |
3898 | tp->speed = cmd->base.speed; | |
3899 | tp->duplex = cmd->base.duplex; | |
aa7e26b6 | 3900 | } |
9a4be1bd | 3901 | |
b5403273 | 3902 | mutex_unlock(&tp->control); |
3903 | ||
9a4be1bd | 3904 | usb_autopm_put_interface(tp->intf); |
3905 | ||
3906 | out: | |
3907 | return ret; | |
ac718b69 | 3908 | } |
3909 | ||
4f1d4d54 | 3910 | static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = { |
3911 | "tx_packets", | |
3912 | "rx_packets", | |
3913 | "tx_errors", | |
3914 | "rx_errors", | |
3915 | "rx_missed", | |
3916 | "align_errors", | |
3917 | "tx_single_collisions", | |
3918 | "tx_multi_collisions", | |
3919 | "rx_unicast", | |
3920 | "rx_broadcast", | |
3921 | "rx_multicast", | |
3922 | "tx_aborted", | |
3923 | "tx_underrun", | |
3924 | }; | |
3925 | ||
3926 | static int rtl8152_get_sset_count(struct net_device *dev, int sset) | |
3927 | { | |
3928 | switch (sset) { | |
3929 | case ETH_SS_STATS: | |
3930 | return ARRAY_SIZE(rtl8152_gstrings); | |
3931 | default: | |
3932 | return -EOPNOTSUPP; | |
3933 | } | |
3934 | } | |
3935 | ||
3936 | static void rtl8152_get_ethtool_stats(struct net_device *dev, | |
3937 | struct ethtool_stats *stats, u64 *data) | |
3938 | { | |
3939 | struct r8152 *tp = netdev_priv(dev); | |
3940 | struct tally_counter tally; | |
3941 | ||
0b030244 | 3942 | if (usb_autopm_get_interface(tp->intf) < 0) |
3943 | return; | |
3944 | ||
4f1d4d54 | 3945 | generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA); |
3946 | ||
0b030244 | 3947 | usb_autopm_put_interface(tp->intf); |
3948 | ||
4f1d4d54 | 3949 | data[0] = le64_to_cpu(tally.tx_packets); |
3950 | data[1] = le64_to_cpu(tally.rx_packets); | |
3951 | data[2] = le64_to_cpu(tally.tx_errors); | |
3952 | data[3] = le32_to_cpu(tally.rx_errors); | |
3953 | data[4] = le16_to_cpu(tally.rx_missed); | |
3954 | data[5] = le16_to_cpu(tally.align_errors); | |
3955 | data[6] = le32_to_cpu(tally.tx_one_collision); | |
3956 | data[7] = le32_to_cpu(tally.tx_multi_collision); | |
3957 | data[8] = le64_to_cpu(tally.rx_unicast); | |
3958 | data[9] = le64_to_cpu(tally.rx_broadcast); | |
3959 | data[10] = le32_to_cpu(tally.rx_multicast); | |
3960 | data[11] = le16_to_cpu(tally.tx_aborted); | |
f37119c5 | 3961 | data[12] = le16_to_cpu(tally.tx_underrun); |
4f1d4d54 | 3962 | } |
3963 | ||
3964 | static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data) | |
3965 | { | |
3966 | switch (stringset) { | |
3967 | case ETH_SS_STATS: | |
3968 | memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings)); | |
3969 | break; | |
3970 | } | |
3971 | } | |
3972 | ||
df35d283 | 3973 | static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee) |
3974 | { | |
3975 | u32 ocp_data, lp, adv, supported = 0; | |
3976 | u16 val; | |
3977 | ||
3978 | val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); | |
3979 | supported = mmd_eee_cap_to_ethtool_sup_t(val); | |
3980 | ||
3981 | val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV); | |
3982 | adv = mmd_eee_adv_to_ethtool_adv_t(val); | |
3983 | ||
3984 | val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE); | |
3985 | lp = mmd_eee_adv_to_ethtool_adv_t(val); | |
3986 | ||
3987 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); | |
3988 | ocp_data &= EEE_RX_EN | EEE_TX_EN; | |
3989 | ||
3990 | eee->eee_enabled = !!ocp_data; | |
3991 | eee->eee_active = !!(supported & adv & lp); | |
3992 | eee->supported = supported; | |
3993 | eee->advertised = adv; | |
3994 | eee->lp_advertised = lp; | |
3995 | ||
3996 | return 0; | |
3997 | } | |
3998 | ||
3999 | static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee) | |
4000 | { | |
4001 | u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); | |
4002 | ||
4003 | r8152_eee_en(tp, eee->eee_enabled); | |
4004 | ||
4005 | if (!eee->eee_enabled) | |
4006 | val = 0; | |
4007 | ||
4008 | r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val); | |
4009 | ||
4010 | return 0; | |
4011 | } | |
4012 | ||
4013 | static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee) | |
4014 | { | |
4015 | u32 ocp_data, lp, adv, supported = 0; | |
4016 | u16 val; | |
4017 | ||
4018 | val = ocp_reg_read(tp, OCP_EEE_ABLE); | |
4019 | supported = mmd_eee_cap_to_ethtool_sup_t(val); | |
4020 | ||
4021 | val = ocp_reg_read(tp, OCP_EEE_ADV); | |
4022 | adv = mmd_eee_adv_to_ethtool_adv_t(val); | |
4023 | ||
4024 | val = ocp_reg_read(tp, OCP_EEE_LPABLE); | |
4025 | lp = mmd_eee_adv_to_ethtool_adv_t(val); | |
4026 | ||
4027 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); | |
4028 | ocp_data &= EEE_RX_EN | EEE_TX_EN; | |
4029 | ||
4030 | eee->eee_enabled = !!ocp_data; | |
4031 | eee->eee_active = !!(supported & adv & lp); | |
4032 | eee->supported = supported; | |
4033 | eee->advertised = adv; | |
4034 | eee->lp_advertised = lp; | |
4035 | ||
4036 | return 0; | |
4037 | } | |
4038 | ||
4039 | static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee) | |
4040 | { | |
4041 | u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); | |
4042 | ||
4043 | r8153_eee_en(tp, eee->eee_enabled); | |
4044 | ||
4045 | if (!eee->eee_enabled) | |
4046 | val = 0; | |
4047 | ||
4048 | ocp_reg_write(tp, OCP_EEE_ADV, val); | |
4049 | ||
4050 | return 0; | |
4051 | } | |
4052 | ||
4053 | static int | |
4054 | rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata) | |
4055 | { | |
4056 | struct r8152 *tp = netdev_priv(net); | |
4057 | int ret; | |
4058 | ||
4059 | ret = usb_autopm_get_interface(tp->intf); | |
4060 | if (ret < 0) | |
4061 | goto out; | |
4062 | ||
b5403273 | 4063 | mutex_lock(&tp->control); |
4064 | ||
df35d283 | 4065 | ret = tp->rtl_ops.eee_get(tp, edata); |
4066 | ||
b5403273 | 4067 | mutex_unlock(&tp->control); |
4068 | ||
df35d283 | 4069 | usb_autopm_put_interface(tp->intf); |
4070 | ||
4071 | out: | |
4072 | return ret; | |
4073 | } | |
4074 | ||
4075 | static int | |
4076 | rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata) | |
4077 | { | |
4078 | struct r8152 *tp = netdev_priv(net); | |
4079 | int ret; | |
4080 | ||
4081 | ret = usb_autopm_get_interface(tp->intf); | |
4082 | if (ret < 0) | |
4083 | goto out; | |
4084 | ||
b5403273 | 4085 | mutex_lock(&tp->control); |
4086 | ||
df35d283 | 4087 | ret = tp->rtl_ops.eee_set(tp, edata); |
9d31a7b9 | 4088 | if (!ret) |
4089 | ret = mii_nway_restart(&tp->mii); | |
df35d283 | 4090 | |
b5403273 | 4091 | mutex_unlock(&tp->control); |
4092 | ||
df35d283 | 4093 | usb_autopm_put_interface(tp->intf); |
4094 | ||
4095 | out: | |
4096 | return ret; | |
4097 | } | |
4098 | ||
8884f507 | 4099 | static int rtl8152_nway_reset(struct net_device *dev) |
4100 | { | |
4101 | struct r8152 *tp = netdev_priv(dev); | |
4102 | int ret; | |
4103 | ||
4104 | ret = usb_autopm_get_interface(tp->intf); | |
4105 | if (ret < 0) | |
4106 | goto out; | |
4107 | ||
4108 | mutex_lock(&tp->control); | |
4109 | ||
4110 | ret = mii_nway_restart(&tp->mii); | |
4111 | ||
4112 | mutex_unlock(&tp->control); | |
4113 | ||
4114 | usb_autopm_put_interface(tp->intf); | |
4115 | ||
4116 | out: | |
4117 | return ret; | |
4118 | } | |
4119 | ||
efb3dd88 | 4120 | static int rtl8152_get_coalesce(struct net_device *netdev, |
4121 | struct ethtool_coalesce *coalesce) | |
4122 | { | |
4123 | struct r8152 *tp = netdev_priv(netdev); | |
4124 | ||
4125 | switch (tp->version) { | |
4126 | case RTL_VER_01: | |
4127 | case RTL_VER_02: | |
4128 | return -EOPNOTSUPP; | |
4129 | default: | |
4130 | break; | |
4131 | } | |
4132 | ||
4133 | coalesce->rx_coalesce_usecs = tp->coalesce; | |
4134 | ||
4135 | return 0; | |
4136 | } | |
4137 | ||
4138 | static int rtl8152_set_coalesce(struct net_device *netdev, | |
4139 | struct ethtool_coalesce *coalesce) | |
4140 | { | |
4141 | struct r8152 *tp = netdev_priv(netdev); | |
4142 | int ret; | |
4143 | ||
4144 | switch (tp->version) { | |
4145 | case RTL_VER_01: | |
4146 | case RTL_VER_02: | |
4147 | return -EOPNOTSUPP; | |
4148 | default: | |
4149 | break; | |
4150 | } | |
4151 | ||
4152 | if (coalesce->rx_coalesce_usecs > COALESCE_SLOW) | |
4153 | return -EINVAL; | |
4154 | ||
4155 | ret = usb_autopm_get_interface(tp->intf); | |
4156 | if (ret < 0) | |
4157 | return ret; | |
4158 | ||
4159 | mutex_lock(&tp->control); | |
4160 | ||
4161 | if (tp->coalesce != coalesce->rx_coalesce_usecs) { | |
4162 | tp->coalesce = coalesce->rx_coalesce_usecs; | |
4163 | ||
4164 | if (netif_running(tp->netdev) && netif_carrier_ok(netdev)) | |
4165 | r8153_set_rx_early_timeout(tp); | |
4166 | } | |
4167 | ||
4168 | mutex_unlock(&tp->control); | |
4169 | ||
4170 | usb_autopm_put_interface(tp->intf); | |
4171 | ||
4172 | return ret; | |
4173 | } | |
4174 | ||
407a471d | 4175 | static const struct ethtool_ops ops = { |
ac718b69 | 4176 | .get_drvinfo = rtl8152_get_drvinfo, |
ac718b69 | 4177 | .get_link = ethtool_op_get_link, |
8884f507 | 4178 | .nway_reset = rtl8152_nway_reset, |
a5ec27c1 | 4179 | .get_msglevel = rtl8152_get_msglevel, |
4180 | .set_msglevel = rtl8152_set_msglevel, | |
21ff2e89 | 4181 | .get_wol = rtl8152_get_wol, |
4182 | .set_wol = rtl8152_set_wol, | |
4f1d4d54 | 4183 | .get_strings = rtl8152_get_strings, |
4184 | .get_sset_count = rtl8152_get_sset_count, | |
4185 | .get_ethtool_stats = rtl8152_get_ethtool_stats, | |
efb3dd88 | 4186 | .get_coalesce = rtl8152_get_coalesce, |
4187 | .set_coalesce = rtl8152_set_coalesce, | |
df35d283 | 4188 | .get_eee = rtl_ethtool_get_eee, |
4189 | .set_eee = rtl_ethtool_set_eee, | |
06144dcf PR |
4190 | .get_link_ksettings = rtl8152_get_link_ksettings, |
4191 | .set_link_ksettings = rtl8152_set_link_ksettings, | |
ac718b69 | 4192 | }; |
4193 | ||
4194 | static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) | |
4195 | { | |
4196 | struct r8152 *tp = netdev_priv(netdev); | |
4197 | struct mii_ioctl_data *data = if_mii(rq); | |
9a4be1bd | 4198 | int res; |
4199 | ||
6871438c | 4200 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
4201 | return -ENODEV; | |
4202 | ||
9a4be1bd | 4203 | res = usb_autopm_get_interface(tp->intf); |
4204 | if (res < 0) | |
4205 | goto out; | |
ac718b69 | 4206 | |
4207 | switch (cmd) { | |
4208 | case SIOCGMIIPHY: | |
4209 | data->phy_id = R8152_PHY_ID; /* Internal PHY */ | |
4210 | break; | |
4211 | ||
4212 | case SIOCGMIIREG: | |
b5403273 | 4213 | mutex_lock(&tp->control); |
ac718b69 | 4214 | data->val_out = r8152_mdio_read(tp, data->reg_num); |
b5403273 | 4215 | mutex_unlock(&tp->control); |
ac718b69 | 4216 | break; |
4217 | ||
4218 | case SIOCSMIIREG: | |
4219 | if (!capable(CAP_NET_ADMIN)) { | |
4220 | res = -EPERM; | |
4221 | break; | |
4222 | } | |
b5403273 | 4223 | mutex_lock(&tp->control); |
ac718b69 | 4224 | r8152_mdio_write(tp, data->reg_num, data->val_in); |
b5403273 | 4225 | mutex_unlock(&tp->control); |
ac718b69 | 4226 | break; |
4227 | ||
4228 | default: | |
4229 | res = -EOPNOTSUPP; | |
4230 | } | |
4231 | ||
9a4be1bd | 4232 | usb_autopm_put_interface(tp->intf); |
4233 | ||
4234 | out: | |
ac718b69 | 4235 | return res; |
4236 | } | |
4237 | ||
69b4b7a4 | 4238 | static int rtl8152_change_mtu(struct net_device *dev, int new_mtu) |
4239 | { | |
4240 | struct r8152 *tp = netdev_priv(dev); | |
396e2e23 | 4241 | int ret; |
69b4b7a4 | 4242 | |
4243 | switch (tp->version) { | |
4244 | case RTL_VER_01: | |
4245 | case RTL_VER_02: | |
a52ad514 JW |
4246 | dev->mtu = new_mtu; |
4247 | return 0; | |
69b4b7a4 | 4248 | default: |
4249 | break; | |
4250 | } | |
4251 | ||
396e2e23 | 4252 | ret = usb_autopm_get_interface(tp->intf); |
4253 | if (ret < 0) | |
4254 | return ret; | |
4255 | ||
4256 | mutex_lock(&tp->control); | |
4257 | ||
69b4b7a4 | 4258 | dev->mtu = new_mtu; |
4259 | ||
210c4f70 | 4260 | if (netif_running(dev)) { |
4261 | u32 rms = new_mtu + VLAN_ETH_HLEN + CRC_SIZE; | |
4262 | ||
4263 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rms); | |
4264 | ||
4265 | if (netif_carrier_ok(dev)) | |
4266 | r8153_set_rx_early_size(tp); | |
4267 | } | |
396e2e23 | 4268 | |
4269 | mutex_unlock(&tp->control); | |
4270 | ||
4271 | usb_autopm_put_interface(tp->intf); | |
4272 | ||
4273 | return ret; | |
69b4b7a4 | 4274 | } |
4275 | ||
ac718b69 | 4276 | static const struct net_device_ops rtl8152_netdev_ops = { |
4277 | .ndo_open = rtl8152_open, | |
4278 | .ndo_stop = rtl8152_close, | |
4279 | .ndo_do_ioctl = rtl8152_ioctl, | |
4280 | .ndo_start_xmit = rtl8152_start_xmit, | |
4281 | .ndo_tx_timeout = rtl8152_tx_timeout, | |
c5554298 | 4282 | .ndo_set_features = rtl8152_set_features, |
ac718b69 | 4283 | .ndo_set_rx_mode = rtl8152_set_rx_mode, |
4284 | .ndo_set_mac_address = rtl8152_set_mac_address, | |
69b4b7a4 | 4285 | .ndo_change_mtu = rtl8152_change_mtu, |
ac718b69 | 4286 | .ndo_validate_addr = eth_validate_addr, |
a5e31255 | 4287 | .ndo_features_check = rtl8152_features_check, |
ac718b69 | 4288 | }; |
4289 | ||
e3fe0b1a | 4290 | static void rtl8152_unload(struct r8152 *tp) |
4291 | { | |
6871438c | 4292 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
4293 | return; | |
4294 | ||
00a5e360 | 4295 | if (tp->version != RTL_VER_01) |
4296 | r8152_power_cut_en(tp, true); | |
e3fe0b1a | 4297 | } |
4298 | ||
43779f8d | 4299 | static void rtl8153_unload(struct r8152 *tp) |
4300 | { | |
6871438c | 4301 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
4302 | return; | |
4303 | ||
49be1723 | 4304 | r8153_power_cut_en(tp, false); |
43779f8d | 4305 | } |
4306 | ||
55b65475 | 4307 | static int rtl_ops_init(struct r8152 *tp) |
c81229c9 | 4308 | { |
4309 | struct rtl_ops *ops = &tp->rtl_ops; | |
55b65475 | 4310 | int ret = 0; |
4311 | ||
4312 | switch (tp->version) { | |
4313 | case RTL_VER_01: | |
4314 | case RTL_VER_02: | |
4315 | ops->init = r8152b_init; | |
4316 | ops->enable = rtl8152_enable; | |
4317 | ops->disable = rtl8152_disable; | |
4318 | ops->up = rtl8152_up; | |
4319 | ops->down = rtl8152_down; | |
4320 | ops->unload = rtl8152_unload; | |
4321 | ops->eee_get = r8152_get_eee; | |
4322 | ops->eee_set = r8152_set_eee; | |
2dd49e0f | 4323 | ops->in_nway = rtl8152_in_nway; |
a028a9e0 | 4324 | ops->hw_phy_cfg = r8152b_hw_phy_cfg; |
2609af19 | 4325 | ops->autosuspend_en = rtl_runtime_suspend_enable; |
43779f8d | 4326 | break; |
4327 | ||
55b65475 | 4328 | case RTL_VER_03: |
4329 | case RTL_VER_04: | |
4330 | case RTL_VER_05: | |
fb02eb4a | 4331 | case RTL_VER_06: |
55b65475 | 4332 | ops->init = r8153_init; |
4333 | ops->enable = rtl8153_enable; | |
4334 | ops->disable = rtl8153_disable; | |
4335 | ops->up = rtl8153_up; | |
4336 | ops->down = rtl8153_down; | |
4337 | ops->unload = rtl8153_unload; | |
4338 | ops->eee_get = r8153_get_eee; | |
4339 | ops->eee_set = r8153_set_eee; | |
2dd49e0f | 4340 | ops->in_nway = rtl8153_in_nway; |
a028a9e0 | 4341 | ops->hw_phy_cfg = r8153_hw_phy_cfg; |
2609af19 | 4342 | ops->autosuspend_en = rtl8153_runtime_enable; |
c81229c9 | 4343 | break; |
4344 | ||
4345 | default: | |
55b65475 | 4346 | ret = -ENODEV; |
4347 | netif_err(tp, probe, tp->netdev, "Unknown Device\n"); | |
c81229c9 | 4348 | break; |
4349 | } | |
4350 | ||
4351 | return ret; | |
4352 | } | |
4353 | ||
33928eed | 4354 | static u8 rtl_get_version(struct usb_interface *intf) |
4355 | { | |
4356 | struct usb_device *udev = interface_to_usbdev(intf); | |
4357 | u32 ocp_data = 0; | |
4358 | __le32 *tmp; | |
4359 | u8 version; | |
4360 | int ret; | |
4361 | ||
4362 | tmp = kmalloc(sizeof(*tmp), GFP_KERNEL); | |
4363 | if (!tmp) | |
4364 | return 0; | |
4365 | ||
4366 | ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), | |
4367 | RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, | |
4368 | PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 500); | |
4369 | if (ret > 0) | |
4370 | ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK; | |
4371 | ||
4372 | kfree(tmp); | |
4373 | ||
4374 | switch (ocp_data) { | |
4375 | case 0x4c00: | |
4376 | version = RTL_VER_01; | |
4377 | break; | |
4378 | case 0x4c10: | |
4379 | version = RTL_VER_02; | |
4380 | break; | |
4381 | case 0x5c00: | |
4382 | version = RTL_VER_03; | |
4383 | break; | |
4384 | case 0x5c10: | |
4385 | version = RTL_VER_04; | |
4386 | break; | |
4387 | case 0x5c20: | |
4388 | version = RTL_VER_05; | |
4389 | break; | |
4390 | case 0x5c30: | |
4391 | version = RTL_VER_06; | |
4392 | break; | |
4393 | default: | |
4394 | version = RTL_VER_UNKNOWN; | |
4395 | dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data); | |
4396 | break; | |
4397 | } | |
4398 | ||
4399 | return version; | |
4400 | } | |
4401 | ||
ac718b69 | 4402 | static int rtl8152_probe(struct usb_interface *intf, |
4403 | const struct usb_device_id *id) | |
4404 | { | |
4405 | struct usb_device *udev = interface_to_usbdev(intf); | |
33928eed | 4406 | u8 version = rtl_get_version(intf); |
ac718b69 | 4407 | struct r8152 *tp; |
4408 | struct net_device *netdev; | |
ebc2ec48 | 4409 | int ret; |
ac718b69 | 4410 | |
33928eed | 4411 | if (version == RTL_VER_UNKNOWN) |
4412 | return -ENODEV; | |
4413 | ||
10c32717 | 4414 | if (udev->actconfig->desc.bConfigurationValue != 1) { |
4415 | usb_driver_set_configuration(udev, 1); | |
4416 | return -ENODEV; | |
4417 | } | |
4418 | ||
4419 | usb_reset_device(udev); | |
ac718b69 | 4420 | netdev = alloc_etherdev(sizeof(struct r8152)); |
4421 | if (!netdev) { | |
4a8deae2 | 4422 | dev_err(&intf->dev, "Out of memory\n"); |
ac718b69 | 4423 | return -ENOMEM; |
4424 | } | |
4425 | ||
ebc2ec48 | 4426 | SET_NETDEV_DEV(netdev, &intf->dev); |
ac718b69 | 4427 | tp = netdev_priv(netdev); |
4428 | tp->msg_enable = 0x7FFF; | |
4429 | ||
e3ad412a | 4430 | tp->udev = udev; |
4431 | tp->netdev = netdev; | |
4432 | tp->intf = intf; | |
33928eed | 4433 | tp->version = version; |
4434 | ||
4435 | switch (version) { | |
4436 | case RTL_VER_01: | |
4437 | case RTL_VER_02: | |
4438 | tp->mii.supports_gmii = 0; | |
4439 | break; | |
4440 | default: | |
4441 | tp->mii.supports_gmii = 1; | |
4442 | break; | |
4443 | } | |
e3ad412a | 4444 | |
55b65475 | 4445 | ret = rtl_ops_init(tp); |
31ca1dec | 4446 | if (ret) |
4447 | goto out; | |
c81229c9 | 4448 | |
b5403273 | 4449 | mutex_init(&tp->control); |
ac718b69 | 4450 | INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t); |
a028a9e0 | 4451 | INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t); |
ac718b69 | 4452 | |
ac718b69 | 4453 | netdev->netdev_ops = &rtl8152_netdev_ops; |
4454 | netdev->watchdog_timeo = RTL8152_TX_TIMEOUT; | |
5bd23881 | 4455 | |
60c89071 | 4456 | netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | |
6128d1bb | 4457 | NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM | |
c5554298 | 4458 | NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX | |
4459 | NETIF_F_HW_VLAN_CTAG_TX; | |
60c89071 | 4460 | netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | |
6128d1bb | 4461 | NETIF_F_TSO | NETIF_F_FRAGLIST | |
c5554298 | 4462 | NETIF_F_IPV6_CSUM | NETIF_F_TSO6 | |
ccc39faf | 4463 | NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX; |
c5554298 | 4464 | netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | |
4465 | NETIF_F_HIGHDMA | NETIF_F_FRAGLIST | | |
4466 | NETIF_F_IPV6_CSUM | NETIF_F_TSO6; | |
db8515ef | 4467 | |
19c0f40d | 4468 | if (tp->version == RTL_VER_01) { |
4469 | netdev->features &= ~NETIF_F_RXCSUM; | |
4470 | netdev->hw_features &= ~NETIF_F_RXCSUM; | |
4471 | } | |
4472 | ||
7ad24ea4 | 4473 | netdev->ethtool_ops = &ops; |
60c89071 | 4474 | netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE); |
ac718b69 | 4475 | |
f77f0aee JW |
4476 | /* MTU range: 68 - 1500 or 9194 */ |
4477 | netdev->min_mtu = ETH_MIN_MTU; | |
4478 | switch (tp->version) { | |
4479 | case RTL_VER_01: | |
4480 | case RTL_VER_02: | |
4481 | netdev->max_mtu = ETH_DATA_LEN; | |
4482 | break; | |
4483 | default: | |
4484 | netdev->max_mtu = RTL8153_MAX_MTU; | |
4485 | break; | |
4486 | } | |
4487 | ||
ac718b69 | 4488 | tp->mii.dev = netdev; |
4489 | tp->mii.mdio_read = read_mii_word; | |
4490 | tp->mii.mdio_write = write_mii_word; | |
4491 | tp->mii.phy_id_mask = 0x3f; | |
4492 | tp->mii.reg_num_mask = 0x1f; | |
4493 | tp->mii.phy_id = R8152_PHY_ID; | |
ac718b69 | 4494 | |
464ec10a | 4495 | switch (udev->speed) { |
4496 | case USB_SPEED_SUPER: | |
2b84af94 | 4497 | case USB_SPEED_SUPER_PLUS: |
464ec10a | 4498 | tp->coalesce = COALESCE_SUPER; |
4499 | break; | |
4500 | case USB_SPEED_HIGH: | |
4501 | tp->coalesce = COALESCE_HIGH; | |
4502 | break; | |
4503 | default: | |
4504 | tp->coalesce = COALESCE_SLOW; | |
4505 | break; | |
4506 | } | |
4507 | ||
aa7e26b6 | 4508 | tp->autoneg = AUTONEG_ENABLE; |
4509 | tp->speed = tp->mii.supports_gmii ? SPEED_1000 : SPEED_100; | |
4510 | tp->duplex = DUPLEX_FULL; | |
4511 | ||
9a4be1bd | 4512 | intf->needs_remote_wakeup = 1; |
4513 | ||
c81229c9 | 4514 | tp->rtl_ops.init(tp); |
a028a9e0 | 4515 | queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0); |
ac718b69 | 4516 | set_ethernet_addr(tp); |
4517 | ||
ac718b69 | 4518 | usb_set_intfdata(intf, tp); |
d823ab68 | 4519 | netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT); |
ac718b69 | 4520 | |
ebc2ec48 | 4521 | ret = register_netdev(netdev); |
4522 | if (ret != 0) { | |
4a8deae2 | 4523 | netif_err(tp, probe, netdev, "couldn't register the device\n"); |
ebc2ec48 | 4524 | goto out1; |
ac718b69 | 4525 | } |
4526 | ||
7daed8dc | 4527 | if (!rtl_can_wakeup(tp)) |
4528 | __rtl_set_wol(tp, 0); | |
4529 | ||
21ff2e89 | 4530 | tp->saved_wolopts = __rtl_get_wol(tp); |
4531 | if (tp->saved_wolopts) | |
4532 | device_set_wakeup_enable(&udev->dev, true); | |
4533 | else | |
4534 | device_set_wakeup_enable(&udev->dev, false); | |
4535 | ||
4a8deae2 | 4536 | netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION); |
ac718b69 | 4537 | |
4538 | return 0; | |
4539 | ||
ac718b69 | 4540 | out1: |
d823ab68 | 4541 | netif_napi_del(&tp->napi); |
ebc2ec48 | 4542 | usb_set_intfdata(intf, NULL); |
ac718b69 | 4543 | out: |
4544 | free_netdev(netdev); | |
ebc2ec48 | 4545 | return ret; |
ac718b69 | 4546 | } |
4547 | ||
ac718b69 | 4548 | static void rtl8152_disconnect(struct usb_interface *intf) |
4549 | { | |
4550 | struct r8152 *tp = usb_get_intfdata(intf); | |
4551 | ||
4552 | usb_set_intfdata(intf, NULL); | |
4553 | if (tp) { | |
f561de33 | 4554 | struct usb_device *udev = tp->udev; |
4555 | ||
4556 | if (udev->state == USB_STATE_NOTATTACHED) | |
4557 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
4558 | ||
d823ab68 | 4559 | netif_napi_del(&tp->napi); |
ac718b69 | 4560 | unregister_netdev(tp->netdev); |
a028a9e0 | 4561 | cancel_delayed_work_sync(&tp->hw_phy_work); |
c81229c9 | 4562 | tp->rtl_ops.unload(tp); |
ac718b69 | 4563 | free_netdev(tp->netdev); |
4564 | } | |
4565 | } | |
4566 | ||
d9a28c5b | 4567 | #define REALTEK_USB_DEVICE(vend, prod) \ |
4568 | .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \ | |
4569 | USB_DEVICE_ID_MATCH_INT_CLASS, \ | |
4570 | .idVendor = (vend), \ | |
4571 | .idProduct = (prod), \ | |
4572 | .bInterfaceClass = USB_CLASS_VENDOR_SPEC \ | |
4573 | }, \ | |
4574 | { \ | |
4575 | .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \ | |
4576 | USB_DEVICE_ID_MATCH_DEVICE, \ | |
4577 | .idVendor = (vend), \ | |
4578 | .idProduct = (prod), \ | |
4579 | .bInterfaceClass = USB_CLASS_COMM, \ | |
4580 | .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \ | |
4581 | .bInterfaceProtocol = USB_CDC_PROTO_NONE | |
4582 | ||
ac718b69 | 4583 | /* table of devices that work with this driver */ |
4584 | static struct usb_device_id rtl8152_table[] = { | |
d9a28c5b | 4585 | {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)}, |
4586 | {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)}, | |
d5b07ccc RR |
4587 | {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab)}, |
4588 | {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6)}, | |
d9a28c5b | 4589 | {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)}, |
1006da19 | 4590 | {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)}, |
d248cafc | 4591 | {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3062)}, |
4592 | {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3069)}, | |
4593 | {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)}, | |
4594 | {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x720c)}, | |
4595 | {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7214)}, | |
d065c3c1 | 4596 | {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)}, |
ac718b69 | 4597 | {} |
4598 | }; | |
4599 | ||
4600 | MODULE_DEVICE_TABLE(usb, rtl8152_table); | |
4601 | ||
4602 | static struct usb_driver rtl8152_driver = { | |
4603 | .name = MODULENAME, | |
ebc2ec48 | 4604 | .id_table = rtl8152_table, |
ac718b69 | 4605 | .probe = rtl8152_probe, |
4606 | .disconnect = rtl8152_disconnect, | |
ac718b69 | 4607 | .suspend = rtl8152_suspend, |
ebc2ec48 | 4608 | .resume = rtl8152_resume, |
7ec2541a | 4609 | .reset_resume = rtl8152_reset_resume, |
e501139a | 4610 | .pre_reset = rtl8152_pre_reset, |
4611 | .post_reset = rtl8152_post_reset, | |
9a4be1bd | 4612 | .supports_autosuspend = 1, |
a634782f | 4613 | .disable_hub_initiated_lpm = 1, |
ac718b69 | 4614 | }; |
4615 | ||
b4236daa | 4616 | module_usb_driver(rtl8152_driver); |
ac718b69 | 4617 | |
4618 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
4619 | MODULE_DESCRIPTION(DRIVER_DESC); | |
4620 | MODULE_LICENSE("GPL"); | |
c961e877 | 4621 | MODULE_VERSION(DRIVER_VERSION); |