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ac718b69 | 1 | /* |
c7de7dec | 2 | * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved. |
ac718b69 | 3 | * |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * version 2 as published by the Free Software Foundation. | |
7 | * | |
8 | */ | |
9 | ||
ac718b69 | 10 | #include <linux/signal.h> |
11 | #include <linux/slab.h> | |
12 | #include <linux/module.h> | |
ac718b69 | 13 | #include <linux/netdevice.h> |
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/mii.h> | |
16 | #include <linux/ethtool.h> | |
17 | #include <linux/usb.h> | |
18 | #include <linux/crc32.h> | |
19 | #include <linux/if_vlan.h> | |
20 | #include <linux/uaccess.h> | |
ebc2ec48 | 21 | #include <linux/list.h> |
5bd23881 | 22 | #include <linux/ip.h> |
23 | #include <linux/ipv6.h> | |
6128d1bb | 24 | #include <net/ip6_checksum.h> |
4c4a6b1b | 25 | #include <uapi/linux/mdio.h> |
26 | #include <linux/mdio.h> | |
d9a28c5b | 27 | #include <linux/usb/cdc.h> |
ac718b69 | 28 | |
29 | /* Version Information */ | |
d823ab68 | 30 | #define DRIVER_VERSION "v1.08.0 (2015/01/13)" |
ac718b69 | 31 | #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>" |
44d942a9 | 32 | #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters" |
ac718b69 | 33 | #define MODULENAME "r8152" |
34 | ||
35 | #define R8152_PHY_ID 32 | |
36 | ||
37 | #define PLA_IDR 0xc000 | |
38 | #define PLA_RCR 0xc010 | |
39 | #define PLA_RMS 0xc016 | |
40 | #define PLA_RXFIFO_CTRL0 0xc0a0 | |
41 | #define PLA_RXFIFO_CTRL1 0xc0a4 | |
42 | #define PLA_RXFIFO_CTRL2 0xc0a8 | |
65bab84c | 43 | #define PLA_DMY_REG0 0xc0b0 |
ac718b69 | 44 | #define PLA_FMC 0xc0b4 |
45 | #define PLA_CFG_WOL 0xc0b6 | |
43779f8d | 46 | #define PLA_TEREDO_CFG 0xc0bc |
ac718b69 | 47 | #define PLA_MAR 0xcd00 |
43779f8d | 48 | #define PLA_BACKUP 0xd000 |
ac718b69 | 49 | #define PAL_BDC_CR 0xd1a0 |
43779f8d | 50 | #define PLA_TEREDO_TIMER 0xd2cc |
51 | #define PLA_REALWOW_TIMER 0xd2e8 | |
ac718b69 | 52 | #define PLA_LEDSEL 0xdd90 |
53 | #define PLA_LED_FEATURE 0xdd92 | |
54 | #define PLA_PHYAR 0xde00 | |
43779f8d | 55 | #define PLA_BOOT_CTRL 0xe004 |
ac718b69 | 56 | #define PLA_GPHY_INTR_IMR 0xe022 |
57 | #define PLA_EEE_CR 0xe040 | |
58 | #define PLA_EEEP_CR 0xe080 | |
59 | #define PLA_MAC_PWR_CTRL 0xe0c0 | |
43779f8d | 60 | #define PLA_MAC_PWR_CTRL2 0xe0ca |
61 | #define PLA_MAC_PWR_CTRL3 0xe0cc | |
62 | #define PLA_MAC_PWR_CTRL4 0xe0ce | |
63 | #define PLA_WDT6_CTRL 0xe428 | |
ac718b69 | 64 | #define PLA_TCR0 0xe610 |
65 | #define PLA_TCR1 0xe612 | |
69b4b7a4 | 66 | #define PLA_MTPS 0xe615 |
ac718b69 | 67 | #define PLA_TXFIFO_CTRL 0xe618 |
4f1d4d54 | 68 | #define PLA_RSTTALLY 0xe800 |
ac718b69 | 69 | #define PLA_CR 0xe813 |
70 | #define PLA_CRWECR 0xe81c | |
21ff2e89 | 71 | #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */ |
72 | #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */ | |
ac718b69 | 73 | #define PLA_CONFIG5 0xe822 |
74 | #define PLA_PHY_PWR 0xe84c | |
75 | #define PLA_OOB_CTRL 0xe84f | |
76 | #define PLA_CPCR 0xe854 | |
77 | #define PLA_MISC_0 0xe858 | |
78 | #define PLA_MISC_1 0xe85a | |
79 | #define PLA_OCP_GPHY_BASE 0xe86c | |
4f1d4d54 | 80 | #define PLA_TALLYCNT 0xe890 |
ac718b69 | 81 | #define PLA_SFF_STS_7 0xe8de |
82 | #define PLA_PHYSTATUS 0xe908 | |
83 | #define PLA_BP_BA 0xfc26 | |
84 | #define PLA_BP_0 0xfc28 | |
85 | #define PLA_BP_1 0xfc2a | |
86 | #define PLA_BP_2 0xfc2c | |
87 | #define PLA_BP_3 0xfc2e | |
88 | #define PLA_BP_4 0xfc30 | |
89 | #define PLA_BP_5 0xfc32 | |
90 | #define PLA_BP_6 0xfc34 | |
91 | #define PLA_BP_7 0xfc36 | |
43779f8d | 92 | #define PLA_BP_EN 0xfc38 |
ac718b69 | 93 | |
65bab84c | 94 | #define USB_USB2PHY 0xb41e |
95 | #define USB_SSPHYLINK2 0xb428 | |
43779f8d | 96 | #define USB_U2P3_CTRL 0xb460 |
65bab84c | 97 | #define USB_CSR_DUMMY1 0xb464 |
98 | #define USB_CSR_DUMMY2 0xb466 | |
ac718b69 | 99 | #define USB_DEV_STAT 0xb808 |
65bab84c | 100 | #define USB_CONNECT_TIMER 0xcbf8 |
101 | #define USB_BURST_SIZE 0xcfc0 | |
ac718b69 | 102 | #define USB_USB_CTRL 0xd406 |
103 | #define USB_PHY_CTRL 0xd408 | |
104 | #define USB_TX_AGG 0xd40a | |
105 | #define USB_RX_BUF_TH 0xd40c | |
106 | #define USB_USB_TIMER 0xd428 | |
464ec10a | 107 | #define USB_RX_EARLY_TIMEOUT 0xd42c |
108 | #define USB_RX_EARLY_SIZE 0xd42e | |
ac718b69 | 109 | #define USB_PM_CTRL_STATUS 0xd432 |
110 | #define USB_TX_DMA 0xd434 | |
43779f8d | 111 | #define USB_TOLERANCE 0xd490 |
112 | #define USB_LPM_CTRL 0xd41a | |
ac718b69 | 113 | #define USB_UPS_CTRL 0xd800 |
43779f8d | 114 | #define USB_MISC_0 0xd81a |
115 | #define USB_POWER_CUT 0xd80a | |
116 | #define USB_AFE_CTRL2 0xd824 | |
117 | #define USB_WDT11_CTRL 0xe43c | |
ac718b69 | 118 | #define USB_BP_BA 0xfc26 |
119 | #define USB_BP_0 0xfc28 | |
120 | #define USB_BP_1 0xfc2a | |
121 | #define USB_BP_2 0xfc2c | |
122 | #define USB_BP_3 0xfc2e | |
123 | #define USB_BP_4 0xfc30 | |
124 | #define USB_BP_5 0xfc32 | |
125 | #define USB_BP_6 0xfc34 | |
126 | #define USB_BP_7 0xfc36 | |
43779f8d | 127 | #define USB_BP_EN 0xfc38 |
ac718b69 | 128 | |
129 | /* OCP Registers */ | |
130 | #define OCP_ALDPS_CONFIG 0x2010 | |
131 | #define OCP_EEE_CONFIG1 0x2080 | |
132 | #define OCP_EEE_CONFIG2 0x2092 | |
133 | #define OCP_EEE_CONFIG3 0x2094 | |
ac244d3e | 134 | #define OCP_BASE_MII 0xa400 |
ac718b69 | 135 | #define OCP_EEE_AR 0xa41a |
136 | #define OCP_EEE_DATA 0xa41c | |
43779f8d | 137 | #define OCP_PHY_STATUS 0xa420 |
138 | #define OCP_POWER_CFG 0xa430 | |
139 | #define OCP_EEE_CFG 0xa432 | |
140 | #define OCP_SRAM_ADDR 0xa436 | |
141 | #define OCP_SRAM_DATA 0xa438 | |
142 | #define OCP_DOWN_SPEED 0xa442 | |
df35d283 | 143 | #define OCP_EEE_ABLE 0xa5c4 |
4c4a6b1b | 144 | #define OCP_EEE_ADV 0xa5d0 |
df35d283 | 145 | #define OCP_EEE_LPABLE 0xa5d2 |
43779f8d | 146 | #define OCP_ADC_CFG 0xbc06 |
147 | ||
148 | /* SRAM Register */ | |
149 | #define SRAM_LPF_CFG 0x8012 | |
150 | #define SRAM_10M_AMP1 0x8080 | |
151 | #define SRAM_10M_AMP2 0x8082 | |
152 | #define SRAM_IMPEDANCE 0x8084 | |
ac718b69 | 153 | |
154 | /* PLA_RCR */ | |
155 | #define RCR_AAP 0x00000001 | |
156 | #define RCR_APM 0x00000002 | |
157 | #define RCR_AM 0x00000004 | |
158 | #define RCR_AB 0x00000008 | |
159 | #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB) | |
160 | ||
161 | /* PLA_RXFIFO_CTRL0 */ | |
162 | #define RXFIFO_THR1_NORMAL 0x00080002 | |
163 | #define RXFIFO_THR1_OOB 0x01800003 | |
164 | ||
165 | /* PLA_RXFIFO_CTRL1 */ | |
166 | #define RXFIFO_THR2_FULL 0x00000060 | |
167 | #define RXFIFO_THR2_HIGH 0x00000038 | |
168 | #define RXFIFO_THR2_OOB 0x0000004a | |
43779f8d | 169 | #define RXFIFO_THR2_NORMAL 0x00a0 |
ac718b69 | 170 | |
171 | /* PLA_RXFIFO_CTRL2 */ | |
172 | #define RXFIFO_THR3_FULL 0x00000078 | |
173 | #define RXFIFO_THR3_HIGH 0x00000048 | |
174 | #define RXFIFO_THR3_OOB 0x0000005a | |
43779f8d | 175 | #define RXFIFO_THR3_NORMAL 0x0110 |
ac718b69 | 176 | |
177 | /* PLA_TXFIFO_CTRL */ | |
178 | #define TXFIFO_THR_NORMAL 0x00400008 | |
43779f8d | 179 | #define TXFIFO_THR_NORMAL2 0x01000008 |
ac718b69 | 180 | |
65bab84c | 181 | /* PLA_DMY_REG0 */ |
182 | #define ECM_ALDPS 0x0002 | |
183 | ||
ac718b69 | 184 | /* PLA_FMC */ |
185 | #define FMC_FCR_MCU_EN 0x0001 | |
186 | ||
187 | /* PLA_EEEP_CR */ | |
188 | #define EEEP_CR_EEEP_TX 0x0002 | |
189 | ||
43779f8d | 190 | /* PLA_WDT6_CTRL */ |
191 | #define WDT6_SET_MODE 0x0010 | |
192 | ||
ac718b69 | 193 | /* PLA_TCR0 */ |
194 | #define TCR0_TX_EMPTY 0x0800 | |
195 | #define TCR0_AUTO_FIFO 0x0080 | |
196 | ||
197 | /* PLA_TCR1 */ | |
198 | #define VERSION_MASK 0x7cf0 | |
199 | ||
69b4b7a4 | 200 | /* PLA_MTPS */ |
201 | #define MTPS_JUMBO (12 * 1024 / 64) | |
202 | #define MTPS_DEFAULT (6 * 1024 / 64) | |
203 | ||
4f1d4d54 | 204 | /* PLA_RSTTALLY */ |
205 | #define TALLY_RESET 0x0001 | |
206 | ||
ac718b69 | 207 | /* PLA_CR */ |
208 | #define CR_RST 0x10 | |
209 | #define CR_RE 0x08 | |
210 | #define CR_TE 0x04 | |
211 | ||
212 | /* PLA_CRWECR */ | |
213 | #define CRWECR_NORAML 0x00 | |
214 | #define CRWECR_CONFIG 0xc0 | |
215 | ||
216 | /* PLA_OOB_CTRL */ | |
217 | #define NOW_IS_OOB 0x80 | |
218 | #define TXFIFO_EMPTY 0x20 | |
219 | #define RXFIFO_EMPTY 0x10 | |
220 | #define LINK_LIST_READY 0x02 | |
221 | #define DIS_MCU_CLROOB 0x01 | |
222 | #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY) | |
223 | ||
224 | /* PLA_MISC_1 */ | |
225 | #define RXDY_GATED_EN 0x0008 | |
226 | ||
227 | /* PLA_SFF_STS_7 */ | |
228 | #define RE_INIT_LL 0x8000 | |
229 | #define MCU_BORW_EN 0x4000 | |
230 | ||
231 | /* PLA_CPCR */ | |
232 | #define CPCR_RX_VLAN 0x0040 | |
233 | ||
234 | /* PLA_CFG_WOL */ | |
235 | #define MAGIC_EN 0x0001 | |
236 | ||
43779f8d | 237 | /* PLA_TEREDO_CFG */ |
238 | #define TEREDO_SEL 0x8000 | |
239 | #define TEREDO_WAKE_MASK 0x7f00 | |
240 | #define TEREDO_RS_EVENT_MASK 0x00fe | |
241 | #define OOB_TEREDO_EN 0x0001 | |
242 | ||
ac718b69 | 243 | /* PAL_BDC_CR */ |
244 | #define ALDPS_PROXY_MODE 0x0001 | |
245 | ||
21ff2e89 | 246 | /* PLA_CONFIG34 */ |
247 | #define LINK_ON_WAKE_EN 0x0010 | |
248 | #define LINK_OFF_WAKE_EN 0x0008 | |
249 | ||
ac718b69 | 250 | /* PLA_CONFIG5 */ |
21ff2e89 | 251 | #define BWF_EN 0x0040 |
252 | #define MWF_EN 0x0020 | |
253 | #define UWF_EN 0x0010 | |
ac718b69 | 254 | #define LAN_WAKE_EN 0x0002 |
255 | ||
256 | /* PLA_LED_FEATURE */ | |
257 | #define LED_MODE_MASK 0x0700 | |
258 | ||
259 | /* PLA_PHY_PWR */ | |
260 | #define TX_10M_IDLE_EN 0x0080 | |
261 | #define PFM_PWM_SWITCH 0x0040 | |
262 | ||
263 | /* PLA_MAC_PWR_CTRL */ | |
264 | #define D3_CLK_GATED_EN 0x00004000 | |
265 | #define MCU_CLK_RATIO 0x07010f07 | |
266 | #define MCU_CLK_RATIO_MASK 0x0f0f0f0f | |
43779f8d | 267 | #define ALDPS_SPDWN_RATIO 0x0f87 |
268 | ||
269 | /* PLA_MAC_PWR_CTRL2 */ | |
270 | #define EEE_SPDWN_RATIO 0x8007 | |
271 | ||
272 | /* PLA_MAC_PWR_CTRL3 */ | |
273 | #define PKT_AVAIL_SPDWN_EN 0x0100 | |
274 | #define SUSPEND_SPDWN_EN 0x0004 | |
275 | #define U1U2_SPDWN_EN 0x0002 | |
276 | #define L1_SPDWN_EN 0x0001 | |
277 | ||
278 | /* PLA_MAC_PWR_CTRL4 */ | |
279 | #define PWRSAVE_SPDWN_EN 0x1000 | |
280 | #define RXDV_SPDWN_EN 0x0800 | |
281 | #define TX10MIDLE_EN 0x0100 | |
282 | #define TP100_SPDWN_EN 0x0020 | |
283 | #define TP500_SPDWN_EN 0x0010 | |
284 | #define TP1000_SPDWN_EN 0x0008 | |
285 | #define EEE_SPDWN_EN 0x0001 | |
ac718b69 | 286 | |
287 | /* PLA_GPHY_INTR_IMR */ | |
288 | #define GPHY_STS_MSK 0x0001 | |
289 | #define SPEED_DOWN_MSK 0x0002 | |
290 | #define SPDWN_RXDV_MSK 0x0004 | |
291 | #define SPDWN_LINKCHG_MSK 0x0008 | |
292 | ||
293 | /* PLA_PHYAR */ | |
294 | #define PHYAR_FLAG 0x80000000 | |
295 | ||
296 | /* PLA_EEE_CR */ | |
297 | #define EEE_RX_EN 0x0001 | |
298 | #define EEE_TX_EN 0x0002 | |
299 | ||
43779f8d | 300 | /* PLA_BOOT_CTRL */ |
301 | #define AUTOLOAD_DONE 0x0002 | |
302 | ||
65bab84c | 303 | /* USB_USB2PHY */ |
304 | #define USB2PHY_SUSPEND 0x0001 | |
305 | #define USB2PHY_L1 0x0002 | |
306 | ||
307 | /* USB_SSPHYLINK2 */ | |
308 | #define pwd_dn_scale_mask 0x3ffe | |
309 | #define pwd_dn_scale(x) ((x) << 1) | |
310 | ||
311 | /* USB_CSR_DUMMY1 */ | |
312 | #define DYNAMIC_BURST 0x0001 | |
313 | ||
314 | /* USB_CSR_DUMMY2 */ | |
315 | #define EP4_FULL_FC 0x0001 | |
316 | ||
ac718b69 | 317 | /* USB_DEV_STAT */ |
318 | #define STAT_SPEED_MASK 0x0006 | |
319 | #define STAT_SPEED_HIGH 0x0000 | |
a3cc465d | 320 | #define STAT_SPEED_FULL 0x0002 |
ac718b69 | 321 | |
322 | /* USB_TX_AGG */ | |
323 | #define TX_AGG_MAX_THRESHOLD 0x03 | |
324 | ||
325 | /* USB_RX_BUF_TH */ | |
43779f8d | 326 | #define RX_THR_SUPPER 0x0c350180 |
8e1f51bd | 327 | #define RX_THR_HIGH 0x7a120180 |
43779f8d | 328 | #define RX_THR_SLOW 0xffff0180 |
ac718b69 | 329 | |
330 | /* USB_TX_DMA */ | |
331 | #define TEST_MODE_DISABLE 0x00000001 | |
332 | #define TX_SIZE_ADJUST1 0x00000100 | |
333 | ||
334 | /* USB_UPS_CTRL */ | |
335 | #define POWER_CUT 0x0100 | |
336 | ||
337 | /* USB_PM_CTRL_STATUS */ | |
8e1f51bd | 338 | #define RESUME_INDICATE 0x0001 |
ac718b69 | 339 | |
340 | /* USB_USB_CTRL */ | |
341 | #define RX_AGG_DISABLE 0x0010 | |
342 | ||
43779f8d | 343 | /* USB_U2P3_CTRL */ |
344 | #define U2P3_ENABLE 0x0001 | |
345 | ||
346 | /* USB_POWER_CUT */ | |
347 | #define PWR_EN 0x0001 | |
348 | #define PHASE2_EN 0x0008 | |
349 | ||
350 | /* USB_MISC_0 */ | |
351 | #define PCUT_STATUS 0x0001 | |
352 | ||
464ec10a | 353 | /* USB_RX_EARLY_TIMEOUT */ |
354 | #define COALESCE_SUPER 85000U | |
355 | #define COALESCE_HIGH 250000U | |
356 | #define COALESCE_SLOW 524280U | |
43779f8d | 357 | |
358 | /* USB_WDT11_CTRL */ | |
359 | #define TIMER11_EN 0x0001 | |
360 | ||
361 | /* USB_LPM_CTRL */ | |
65bab84c | 362 | /* bit 4 ~ 5: fifo empty boundary */ |
363 | #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */ | |
364 | /* bit 2 ~ 3: LMP timer */ | |
43779f8d | 365 | #define LPM_TIMER_MASK 0x0c |
366 | #define LPM_TIMER_500MS 0x04 /* 500 ms */ | |
367 | #define LPM_TIMER_500US 0x0c /* 500 us */ | |
65bab84c | 368 | #define ROK_EXIT_LPM 0x02 |
43779f8d | 369 | |
370 | /* USB_AFE_CTRL2 */ | |
371 | #define SEN_VAL_MASK 0xf800 | |
372 | #define SEN_VAL_NORMAL 0xa000 | |
373 | #define SEL_RXIDLE 0x0100 | |
374 | ||
ac718b69 | 375 | /* OCP_ALDPS_CONFIG */ |
376 | #define ENPWRSAVE 0x8000 | |
377 | #define ENPDNPS 0x0200 | |
378 | #define LINKENA 0x0100 | |
379 | #define DIS_SDSAVE 0x0010 | |
380 | ||
43779f8d | 381 | /* OCP_PHY_STATUS */ |
382 | #define PHY_STAT_MASK 0x0007 | |
383 | #define PHY_STAT_LAN_ON 3 | |
384 | #define PHY_STAT_PWRDN 5 | |
385 | ||
386 | /* OCP_POWER_CFG */ | |
387 | #define EEE_CLKDIV_EN 0x8000 | |
388 | #define EN_ALDPS 0x0004 | |
389 | #define EN_10M_PLLOFF 0x0001 | |
390 | ||
ac718b69 | 391 | /* OCP_EEE_CONFIG1 */ |
392 | #define RG_TXLPI_MSK_HFDUP 0x8000 | |
393 | #define RG_MATCLR_EN 0x4000 | |
394 | #define EEE_10_CAP 0x2000 | |
395 | #define EEE_NWAY_EN 0x1000 | |
396 | #define TX_QUIET_EN 0x0200 | |
397 | #define RX_QUIET_EN 0x0100 | |
d24f6134 | 398 | #define sd_rise_time_mask 0x0070 |
4c4a6b1b | 399 | #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */ |
ac718b69 | 400 | #define RG_RXLPI_MSK_HFDUP 0x0008 |
401 | #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */ | |
402 | ||
403 | /* OCP_EEE_CONFIG2 */ | |
404 | #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */ | |
405 | #define RG_DACQUIET_EN 0x0400 | |
406 | #define RG_LDVQUIET_EN 0x0200 | |
407 | #define RG_CKRSEL 0x0020 | |
408 | #define RG_EEEPRG_EN 0x0010 | |
409 | ||
410 | /* OCP_EEE_CONFIG3 */ | |
d24f6134 | 411 | #define fast_snr_mask 0xff80 |
4c4a6b1b | 412 | #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */ |
ac718b69 | 413 | #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */ |
414 | #define MSK_PH 0x0006 /* bit 0 ~ 3 */ | |
415 | ||
416 | /* OCP_EEE_AR */ | |
417 | /* bit[15:14] function */ | |
418 | #define FUN_ADDR 0x0000 | |
419 | #define FUN_DATA 0x4000 | |
420 | /* bit[4:0] device addr */ | |
ac718b69 | 421 | |
43779f8d | 422 | /* OCP_EEE_CFG */ |
423 | #define CTAP_SHORT_EN 0x0040 | |
424 | #define EEE10_EN 0x0010 | |
425 | ||
426 | /* OCP_DOWN_SPEED */ | |
427 | #define EN_10M_BGOFF 0x0080 | |
428 | ||
43779f8d | 429 | /* OCP_ADC_CFG */ |
430 | #define CKADSEL_L 0x0100 | |
431 | #define ADC_EN 0x0080 | |
432 | #define EN_EMI_L 0x0040 | |
433 | ||
434 | /* SRAM_LPF_CFG */ | |
435 | #define LPF_AUTO_TUNE 0x8000 | |
436 | ||
437 | /* SRAM_10M_AMP1 */ | |
438 | #define GDAC_IB_UPALL 0x0008 | |
439 | ||
440 | /* SRAM_10M_AMP2 */ | |
441 | #define AMP_DN 0x0200 | |
442 | ||
443 | /* SRAM_IMPEDANCE */ | |
444 | #define RX_DRIVING_MASK 0x6000 | |
445 | ||
ac718b69 | 446 | enum rtl_register_content { |
43779f8d | 447 | _1000bps = 0x10, |
ac718b69 | 448 | _100bps = 0x08, |
449 | _10bps = 0x04, | |
450 | LINK_STATUS = 0x02, | |
451 | FULL_DUP = 0x01, | |
452 | }; | |
453 | ||
1764bcd9 | 454 | #define RTL8152_MAX_TX 4 |
ebc2ec48 | 455 | #define RTL8152_MAX_RX 10 |
40a82917 | 456 | #define INTBUFSIZE 2 |
8e1f51bd | 457 | #define CRC_SIZE 4 |
458 | #define TX_ALIGN 4 | |
459 | #define RX_ALIGN 8 | |
40a82917 | 460 | |
461 | #define INTR_LINK 0x0004 | |
ebc2ec48 | 462 | |
ac718b69 | 463 | #define RTL8152_REQT_READ 0xc0 |
464 | #define RTL8152_REQT_WRITE 0x40 | |
465 | #define RTL8152_REQ_GET_REGS 0x05 | |
466 | #define RTL8152_REQ_SET_REGS 0x05 | |
467 | ||
468 | #define BYTE_EN_DWORD 0xff | |
469 | #define BYTE_EN_WORD 0x33 | |
470 | #define BYTE_EN_BYTE 0x11 | |
471 | #define BYTE_EN_SIX_BYTES 0x3f | |
472 | #define BYTE_EN_START_MASK 0x0f | |
473 | #define BYTE_EN_END_MASK 0xf0 | |
474 | ||
69b4b7a4 | 475 | #define RTL8153_MAX_PACKET 9216 /* 9K */ |
476 | #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN) | |
ac718b69 | 477 | #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN) |
69b4b7a4 | 478 | #define RTL8153_RMS RTL8153_MAX_PACKET |
b8125404 | 479 | #define RTL8152_TX_TIMEOUT (5 * HZ) |
d823ab68 | 480 | #define RTL8152_NAPI_WEIGHT 64 |
ac718b69 | 481 | |
482 | /* rtl8152 flags */ | |
483 | enum rtl8152_flags { | |
484 | RTL8152_UNPLUG = 0, | |
ac718b69 | 485 | RTL8152_SET_RX_MODE, |
40a82917 | 486 | WORK_ENABLE, |
487 | RTL8152_LINK_CHG, | |
9a4be1bd | 488 | SELECTIVE_SUSPEND, |
aa66a5f1 | 489 | PHY_RESET, |
d823ab68 | 490 | SCHEDULE_NAPI, |
ac718b69 | 491 | }; |
492 | ||
493 | /* Define these values to match your device */ | |
494 | #define VENDOR_ID_REALTEK 0x0bda | |
43779f8d | 495 | #define VENDOR_ID_SAMSUNG 0x04e8 |
347eec34 | 496 | #define VENDOR_ID_LENOVO 0x17ef |
d065c3c1 | 497 | #define VENDOR_ID_NVIDIA 0x0955 |
ac718b69 | 498 | |
499 | #define MCU_TYPE_PLA 0x0100 | |
500 | #define MCU_TYPE_USB 0x0000 | |
501 | ||
4f1d4d54 | 502 | struct tally_counter { |
503 | __le64 tx_packets; | |
504 | __le64 rx_packets; | |
505 | __le64 tx_errors; | |
506 | __le32 rx_errors; | |
507 | __le16 rx_missed; | |
508 | __le16 align_errors; | |
509 | __le32 tx_one_collision; | |
510 | __le32 tx_multi_collision; | |
511 | __le64 rx_unicast; | |
512 | __le64 rx_broadcast; | |
513 | __le32 rx_multicast; | |
514 | __le16 tx_aborted; | |
f37119c5 | 515 | __le16 tx_underrun; |
4f1d4d54 | 516 | }; |
517 | ||
ac718b69 | 518 | struct rx_desc { |
500b6d7e | 519 | __le32 opts1; |
ac718b69 | 520 | #define RX_LEN_MASK 0x7fff |
565cab0a | 521 | |
500b6d7e | 522 | __le32 opts2; |
f5aaaa6d | 523 | #define RD_UDP_CS BIT(23) |
524 | #define RD_TCP_CS BIT(22) | |
525 | #define RD_IPV6_CS BIT(20) | |
526 | #define RD_IPV4_CS BIT(19) | |
565cab0a | 527 | |
500b6d7e | 528 | __le32 opts3; |
f5aaaa6d | 529 | #define IPF BIT(23) /* IP checksum fail */ |
530 | #define UDPF BIT(22) /* UDP checksum fail */ | |
531 | #define TCPF BIT(21) /* TCP checksum fail */ | |
532 | #define RX_VLAN_TAG BIT(16) | |
565cab0a | 533 | |
500b6d7e | 534 | __le32 opts4; |
535 | __le32 opts5; | |
536 | __le32 opts6; | |
ac718b69 | 537 | }; |
538 | ||
539 | struct tx_desc { | |
500b6d7e | 540 | __le32 opts1; |
f5aaaa6d | 541 | #define TX_FS BIT(31) /* First segment of a packet */ |
542 | #define TX_LS BIT(30) /* Final segment of a packet */ | |
543 | #define GTSENDV4 BIT(28) | |
544 | #define GTSENDV6 BIT(27) | |
60c89071 | 545 | #define GTTCPHO_SHIFT 18 |
6128d1bb | 546 | #define GTTCPHO_MAX 0x7fU |
60c89071 | 547 | #define TX_LEN_MAX 0x3ffffU |
5bd23881 | 548 | |
500b6d7e | 549 | __le32 opts2; |
f5aaaa6d | 550 | #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */ |
551 | #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */ | |
552 | #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */ | |
553 | #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */ | |
60c89071 | 554 | #define MSS_SHIFT 17 |
555 | #define MSS_MAX 0x7ffU | |
556 | #define TCPHO_SHIFT 17 | |
6128d1bb | 557 | #define TCPHO_MAX 0x7ffU |
f5aaaa6d | 558 | #define TX_VLAN_TAG BIT(16) |
ac718b69 | 559 | }; |
560 | ||
dff4e8ad | 561 | struct r8152; |
562 | ||
ebc2ec48 | 563 | struct rx_agg { |
564 | struct list_head list; | |
565 | struct urb *urb; | |
dff4e8ad | 566 | struct r8152 *context; |
ebc2ec48 | 567 | void *buffer; |
568 | void *head; | |
569 | }; | |
570 | ||
571 | struct tx_agg { | |
572 | struct list_head list; | |
573 | struct urb *urb; | |
dff4e8ad | 574 | struct r8152 *context; |
ebc2ec48 | 575 | void *buffer; |
576 | void *head; | |
577 | u32 skb_num; | |
578 | u32 skb_len; | |
579 | }; | |
580 | ||
ac718b69 | 581 | struct r8152 { |
582 | unsigned long flags; | |
583 | struct usb_device *udev; | |
d823ab68 | 584 | struct napi_struct napi; |
40a82917 | 585 | struct usb_interface *intf; |
ac718b69 | 586 | struct net_device *netdev; |
40a82917 | 587 | struct urb *intr_urb; |
ebc2ec48 | 588 | struct tx_agg tx_info[RTL8152_MAX_TX]; |
589 | struct rx_agg rx_info[RTL8152_MAX_RX]; | |
590 | struct list_head rx_done, tx_free; | |
d823ab68 | 591 | struct sk_buff_head tx_queue, rx_queue; |
ebc2ec48 | 592 | spinlock_t rx_lock, tx_lock; |
ac718b69 | 593 | struct delayed_work schedule; |
594 | struct mii_if_info mii; | |
b5403273 | 595 | struct mutex control; /* use for hw setting */ |
c81229c9 | 596 | |
597 | struct rtl_ops { | |
598 | void (*init)(struct r8152 *); | |
599 | int (*enable)(struct r8152 *); | |
600 | void (*disable)(struct r8152 *); | |
7e9da481 | 601 | void (*up)(struct r8152 *); |
c81229c9 | 602 | void (*down)(struct r8152 *); |
603 | void (*unload)(struct r8152 *); | |
df35d283 | 604 | int (*eee_get)(struct r8152 *, struct ethtool_eee *); |
605 | int (*eee_set)(struct r8152 *, struct ethtool_eee *); | |
c81229c9 | 606 | } rtl_ops; |
607 | ||
40a82917 | 608 | int intr_interval; |
21ff2e89 | 609 | u32 saved_wolopts; |
ac718b69 | 610 | u32 msg_enable; |
dd1b119c | 611 | u32 tx_qlen; |
464ec10a | 612 | u32 coalesce; |
ac718b69 | 613 | u16 ocp_base; |
40a82917 | 614 | u8 *intr_buff; |
ac718b69 | 615 | u8 version; |
ac718b69 | 616 | }; |
617 | ||
618 | enum rtl_version { | |
619 | RTL_VER_UNKNOWN = 0, | |
620 | RTL_VER_01, | |
43779f8d | 621 | RTL_VER_02, |
622 | RTL_VER_03, | |
623 | RTL_VER_04, | |
624 | RTL_VER_05, | |
625 | RTL_VER_MAX | |
ac718b69 | 626 | }; |
627 | ||
60c89071 | 628 | enum tx_csum_stat { |
629 | TX_CSUM_SUCCESS = 0, | |
630 | TX_CSUM_TSO, | |
631 | TX_CSUM_NONE | |
632 | }; | |
633 | ||
ac718b69 | 634 | /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). |
635 | * The RTL chips use a 64 element hash table based on the Ethernet CRC. | |
636 | */ | |
637 | static const int multicast_filter_limit = 32; | |
52aec126 | 638 | static unsigned int agg_buf_sz = 16384; |
ac718b69 | 639 | |
52aec126 | 640 | #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \ |
60c89071 | 641 | VLAN_ETH_HLEN - VLAN_HLEN) |
642 | ||
ac718b69 | 643 | static |
644 | int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) | |
645 | { | |
31787f53 | 646 | int ret; |
647 | void *tmp; | |
648 | ||
649 | tmp = kmalloc(size, GFP_KERNEL); | |
650 | if (!tmp) | |
651 | return -ENOMEM; | |
652 | ||
653 | ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0), | |
b209af99 | 654 | RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, |
655 | value, index, tmp, size, 500); | |
31787f53 | 656 | |
657 | memcpy(data, tmp, size); | |
658 | kfree(tmp); | |
659 | ||
660 | return ret; | |
ac718b69 | 661 | } |
662 | ||
663 | static | |
664 | int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) | |
665 | { | |
31787f53 | 666 | int ret; |
667 | void *tmp; | |
668 | ||
c4438f03 | 669 | tmp = kmemdup(data, size, GFP_KERNEL); |
31787f53 | 670 | if (!tmp) |
671 | return -ENOMEM; | |
672 | ||
31787f53 | 673 | ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0), |
b209af99 | 674 | RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE, |
675 | value, index, tmp, size, 500); | |
31787f53 | 676 | |
677 | kfree(tmp); | |
db8515ef | 678 | |
31787f53 | 679 | return ret; |
ac718b69 | 680 | } |
681 | ||
682 | static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size, | |
b209af99 | 683 | void *data, u16 type) |
ac718b69 | 684 | { |
45f4a19f | 685 | u16 limit = 64; |
686 | int ret = 0; | |
ac718b69 | 687 | |
688 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
689 | return -ENODEV; | |
690 | ||
691 | /* both size and indix must be 4 bytes align */ | |
692 | if ((size & 3) || !size || (index & 3) || !data) | |
693 | return -EPERM; | |
694 | ||
695 | if ((u32)index + (u32)size > 0xffff) | |
696 | return -EPERM; | |
697 | ||
698 | while (size) { | |
699 | if (size > limit) { | |
700 | ret = get_registers(tp, index, type, limit, data); | |
701 | if (ret < 0) | |
702 | break; | |
703 | ||
704 | index += limit; | |
705 | data += limit; | |
706 | size -= limit; | |
707 | } else { | |
708 | ret = get_registers(tp, index, type, size, data); | |
709 | if (ret < 0) | |
710 | break; | |
711 | ||
712 | index += size; | |
713 | data += size; | |
714 | size = 0; | |
715 | break; | |
716 | } | |
717 | } | |
718 | ||
67610496 | 719 | if (ret == -ENODEV) |
720 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
721 | ||
ac718b69 | 722 | return ret; |
723 | } | |
724 | ||
725 | static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, | |
b209af99 | 726 | u16 size, void *data, u16 type) |
ac718b69 | 727 | { |
45f4a19f | 728 | int ret; |
729 | u16 byteen_start, byteen_end, byen; | |
730 | u16 limit = 512; | |
ac718b69 | 731 | |
732 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
733 | return -ENODEV; | |
734 | ||
735 | /* both size and indix must be 4 bytes align */ | |
736 | if ((size & 3) || !size || (index & 3) || !data) | |
737 | return -EPERM; | |
738 | ||
739 | if ((u32)index + (u32)size > 0xffff) | |
740 | return -EPERM; | |
741 | ||
742 | byteen_start = byteen & BYTE_EN_START_MASK; | |
743 | byteen_end = byteen & BYTE_EN_END_MASK; | |
744 | ||
745 | byen = byteen_start | (byteen_start << 4); | |
746 | ret = set_registers(tp, index, type | byen, 4, data); | |
747 | if (ret < 0) | |
748 | goto error1; | |
749 | ||
750 | index += 4; | |
751 | data += 4; | |
752 | size -= 4; | |
753 | ||
754 | if (size) { | |
755 | size -= 4; | |
756 | ||
757 | while (size) { | |
758 | if (size > limit) { | |
759 | ret = set_registers(tp, index, | |
b209af99 | 760 | type | BYTE_EN_DWORD, |
761 | limit, data); | |
ac718b69 | 762 | if (ret < 0) |
763 | goto error1; | |
764 | ||
765 | index += limit; | |
766 | data += limit; | |
767 | size -= limit; | |
768 | } else { | |
769 | ret = set_registers(tp, index, | |
b209af99 | 770 | type | BYTE_EN_DWORD, |
771 | size, data); | |
ac718b69 | 772 | if (ret < 0) |
773 | goto error1; | |
774 | ||
775 | index += size; | |
776 | data += size; | |
777 | size = 0; | |
778 | break; | |
779 | } | |
780 | } | |
781 | ||
782 | byen = byteen_end | (byteen_end >> 4); | |
783 | ret = set_registers(tp, index, type | byen, 4, data); | |
784 | if (ret < 0) | |
785 | goto error1; | |
786 | } | |
787 | ||
788 | error1: | |
67610496 | 789 | if (ret == -ENODEV) |
790 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
791 | ||
ac718b69 | 792 | return ret; |
793 | } | |
794 | ||
795 | static inline | |
796 | int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) | |
797 | { | |
798 | return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA); | |
799 | } | |
800 | ||
801 | static inline | |
802 | int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) | |
803 | { | |
804 | return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA); | |
805 | } | |
806 | ||
807 | static inline | |
808 | int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) | |
809 | { | |
810 | return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB); | |
811 | } | |
812 | ||
813 | static inline | |
814 | int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) | |
815 | { | |
816 | return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB); | |
817 | } | |
818 | ||
819 | static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index) | |
820 | { | |
c8826de8 | 821 | __le32 data; |
ac718b69 | 822 | |
c8826de8 | 823 | generic_ocp_read(tp, index, sizeof(data), &data, type); |
ac718b69 | 824 | |
825 | return __le32_to_cpu(data); | |
826 | } | |
827 | ||
828 | static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data) | |
829 | { | |
c8826de8 | 830 | __le32 tmp = __cpu_to_le32(data); |
831 | ||
832 | generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type); | |
ac718b69 | 833 | } |
834 | ||
835 | static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index) | |
836 | { | |
837 | u32 data; | |
c8826de8 | 838 | __le32 tmp; |
ac718b69 | 839 | u8 shift = index & 2; |
840 | ||
841 | index &= ~3; | |
842 | ||
c8826de8 | 843 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 844 | |
c8826de8 | 845 | data = __le32_to_cpu(tmp); |
ac718b69 | 846 | data >>= (shift * 8); |
847 | data &= 0xffff; | |
848 | ||
849 | return (u16)data; | |
850 | } | |
851 | ||
852 | static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data) | |
853 | { | |
c8826de8 | 854 | u32 mask = 0xffff; |
855 | __le32 tmp; | |
ac718b69 | 856 | u16 byen = BYTE_EN_WORD; |
857 | u8 shift = index & 2; | |
858 | ||
859 | data &= mask; | |
860 | ||
861 | if (index & 2) { | |
862 | byen <<= shift; | |
863 | mask <<= (shift * 8); | |
864 | data <<= (shift * 8); | |
865 | index &= ~3; | |
866 | } | |
867 | ||
c8826de8 | 868 | tmp = __cpu_to_le32(data); |
ac718b69 | 869 | |
c8826de8 | 870 | generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); |
ac718b69 | 871 | } |
872 | ||
873 | static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index) | |
874 | { | |
875 | u32 data; | |
c8826de8 | 876 | __le32 tmp; |
ac718b69 | 877 | u8 shift = index & 3; |
878 | ||
879 | index &= ~3; | |
880 | ||
c8826de8 | 881 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 882 | |
c8826de8 | 883 | data = __le32_to_cpu(tmp); |
ac718b69 | 884 | data >>= (shift * 8); |
885 | data &= 0xff; | |
886 | ||
887 | return (u8)data; | |
888 | } | |
889 | ||
890 | static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data) | |
891 | { | |
c8826de8 | 892 | u32 mask = 0xff; |
893 | __le32 tmp; | |
ac718b69 | 894 | u16 byen = BYTE_EN_BYTE; |
895 | u8 shift = index & 3; | |
896 | ||
897 | data &= mask; | |
898 | ||
899 | if (index & 3) { | |
900 | byen <<= shift; | |
901 | mask <<= (shift * 8); | |
902 | data <<= (shift * 8); | |
903 | index &= ~3; | |
904 | } | |
905 | ||
c8826de8 | 906 | tmp = __cpu_to_le32(data); |
ac718b69 | 907 | |
c8826de8 | 908 | generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); |
ac718b69 | 909 | } |
910 | ||
ac244d3e | 911 | static u16 ocp_reg_read(struct r8152 *tp, u16 addr) |
e3fe0b1a | 912 | { |
913 | u16 ocp_base, ocp_index; | |
914 | ||
915 | ocp_base = addr & 0xf000; | |
916 | if (ocp_base != tp->ocp_base) { | |
917 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); | |
918 | tp->ocp_base = ocp_base; | |
919 | } | |
920 | ||
921 | ocp_index = (addr & 0x0fff) | 0xb000; | |
ac244d3e | 922 | return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index); |
e3fe0b1a | 923 | } |
924 | ||
ac244d3e | 925 | static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) |
ac718b69 | 926 | { |
ac244d3e | 927 | u16 ocp_base, ocp_index; |
ac718b69 | 928 | |
ac244d3e | 929 | ocp_base = addr & 0xf000; |
930 | if (ocp_base != tp->ocp_base) { | |
931 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); | |
932 | tp->ocp_base = ocp_base; | |
ac718b69 | 933 | } |
ac244d3e | 934 | |
935 | ocp_index = (addr & 0x0fff) | 0xb000; | |
936 | ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data); | |
ac718b69 | 937 | } |
938 | ||
ac244d3e | 939 | static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value) |
ac718b69 | 940 | { |
ac244d3e | 941 | ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value); |
942 | } | |
ac718b69 | 943 | |
ac244d3e | 944 | static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr) |
945 | { | |
946 | return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2); | |
ac718b69 | 947 | } |
948 | ||
43779f8d | 949 | static void sram_write(struct r8152 *tp, u16 addr, u16 data) |
950 | { | |
951 | ocp_reg_write(tp, OCP_SRAM_ADDR, addr); | |
952 | ocp_reg_write(tp, OCP_SRAM_DATA, data); | |
953 | } | |
954 | ||
ac718b69 | 955 | static int read_mii_word(struct net_device *netdev, int phy_id, int reg) |
956 | { | |
957 | struct r8152 *tp = netdev_priv(netdev); | |
9a4be1bd | 958 | int ret; |
ac718b69 | 959 | |
6871438c | 960 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
961 | return -ENODEV; | |
962 | ||
ac718b69 | 963 | if (phy_id != R8152_PHY_ID) |
964 | return -EINVAL; | |
965 | ||
9a4be1bd | 966 | ret = r8152_mdio_read(tp, reg); |
967 | ||
9a4be1bd | 968 | return ret; |
ac718b69 | 969 | } |
970 | ||
971 | static | |
972 | void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val) | |
973 | { | |
974 | struct r8152 *tp = netdev_priv(netdev); | |
975 | ||
6871438c | 976 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
977 | return; | |
978 | ||
ac718b69 | 979 | if (phy_id != R8152_PHY_ID) |
980 | return; | |
981 | ||
982 | r8152_mdio_write(tp, reg, val); | |
983 | } | |
984 | ||
b209af99 | 985 | static int |
986 | r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags); | |
ebc2ec48 | 987 | |
8ba789ab | 988 | static int rtl8152_set_mac_address(struct net_device *netdev, void *p) |
989 | { | |
990 | struct r8152 *tp = netdev_priv(netdev); | |
991 | struct sockaddr *addr = p; | |
ea6a7112 | 992 | int ret = -EADDRNOTAVAIL; |
8ba789ab | 993 | |
994 | if (!is_valid_ether_addr(addr->sa_data)) | |
ea6a7112 | 995 | goto out1; |
996 | ||
997 | ret = usb_autopm_get_interface(tp->intf); | |
998 | if (ret < 0) | |
999 | goto out1; | |
8ba789ab | 1000 | |
b5403273 | 1001 | mutex_lock(&tp->control); |
1002 | ||
8ba789ab | 1003 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); |
1004 | ||
1005 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
1006 | pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data); | |
1007 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
1008 | ||
b5403273 | 1009 | mutex_unlock(&tp->control); |
1010 | ||
ea6a7112 | 1011 | usb_autopm_put_interface(tp->intf); |
1012 | out1: | |
1013 | return ret; | |
8ba789ab | 1014 | } |
1015 | ||
179bb6d7 | 1016 | static int set_ethernet_addr(struct r8152 *tp) |
ac718b69 | 1017 | { |
1018 | struct net_device *dev = tp->netdev; | |
179bb6d7 | 1019 | struct sockaddr sa; |
8a91c824 | 1020 | int ret; |
ac718b69 | 1021 | |
8a91c824 | 1022 | if (tp->version == RTL_VER_01) |
179bb6d7 | 1023 | ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data); |
8a91c824 | 1024 | else |
179bb6d7 | 1025 | ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data); |
8a91c824 | 1026 | |
1027 | if (ret < 0) { | |
179bb6d7 | 1028 | netif_err(tp, probe, dev, "Get ether addr fail\n"); |
1029 | } else if (!is_valid_ether_addr(sa.sa_data)) { | |
1030 | netif_err(tp, probe, dev, "Invalid ether addr %pM\n", | |
1031 | sa.sa_data); | |
1032 | eth_hw_addr_random(dev); | |
1033 | ether_addr_copy(sa.sa_data, dev->dev_addr); | |
1034 | ret = rtl8152_set_mac_address(dev, &sa); | |
1035 | netif_info(tp, probe, dev, "Random ether addr %pM\n", | |
1036 | sa.sa_data); | |
8a91c824 | 1037 | } else { |
179bb6d7 | 1038 | if (tp->version == RTL_VER_01) |
1039 | ether_addr_copy(dev->dev_addr, sa.sa_data); | |
1040 | else | |
1041 | ret = rtl8152_set_mac_address(dev, &sa); | |
ac718b69 | 1042 | } |
179bb6d7 | 1043 | |
1044 | return ret; | |
ac718b69 | 1045 | } |
1046 | ||
ac718b69 | 1047 | static void read_bulk_callback(struct urb *urb) |
1048 | { | |
ac718b69 | 1049 | struct net_device *netdev; |
ac718b69 | 1050 | int status = urb->status; |
ebc2ec48 | 1051 | struct rx_agg *agg; |
1052 | struct r8152 *tp; | |
ac718b69 | 1053 | |
ebc2ec48 | 1054 | agg = urb->context; |
1055 | if (!agg) | |
1056 | return; | |
1057 | ||
1058 | tp = agg->context; | |
ac718b69 | 1059 | if (!tp) |
1060 | return; | |
ebc2ec48 | 1061 | |
ac718b69 | 1062 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
1063 | return; | |
ebc2ec48 | 1064 | |
1065 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
1066 | return; | |
1067 | ||
ac718b69 | 1068 | netdev = tp->netdev; |
7559fb2f | 1069 | |
1070 | /* When link down, the driver would cancel all bulks. */ | |
1071 | /* This avoid the re-submitting bulk */ | |
ebc2ec48 | 1072 | if (!netif_carrier_ok(netdev)) |
ac718b69 | 1073 | return; |
1074 | ||
9a4be1bd | 1075 | usb_mark_last_busy(tp->udev); |
1076 | ||
ac718b69 | 1077 | switch (status) { |
1078 | case 0: | |
ebc2ec48 | 1079 | if (urb->actual_length < ETH_ZLEN) |
1080 | break; | |
1081 | ||
2685d410 | 1082 | spin_lock(&tp->rx_lock); |
ebc2ec48 | 1083 | list_add_tail(&agg->list, &tp->rx_done); |
2685d410 | 1084 | spin_unlock(&tp->rx_lock); |
d823ab68 | 1085 | napi_schedule(&tp->napi); |
ebc2ec48 | 1086 | return; |
ac718b69 | 1087 | case -ESHUTDOWN: |
1088 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
1089 | netif_device_detach(tp->netdev); | |
ebc2ec48 | 1090 | return; |
ac718b69 | 1091 | case -ENOENT: |
1092 | return; /* the urb is in unlink state */ | |
1093 | case -ETIME: | |
4a8deae2 HW |
1094 | if (net_ratelimit()) |
1095 | netdev_warn(netdev, "maybe reset is needed?\n"); | |
ebc2ec48 | 1096 | break; |
ac718b69 | 1097 | default: |
4a8deae2 HW |
1098 | if (net_ratelimit()) |
1099 | netdev_warn(netdev, "Rx status %d\n", status); | |
ebc2ec48 | 1100 | break; |
ac718b69 | 1101 | } |
1102 | ||
a0fccd48 | 1103 | r8152_submit_rx(tp, agg, GFP_ATOMIC); |
ac718b69 | 1104 | } |
1105 | ||
ebc2ec48 | 1106 | static void write_bulk_callback(struct urb *urb) |
ac718b69 | 1107 | { |
ebc2ec48 | 1108 | struct net_device_stats *stats; |
d104eafa | 1109 | struct net_device *netdev; |
ebc2ec48 | 1110 | struct tx_agg *agg; |
ac718b69 | 1111 | struct r8152 *tp; |
ebc2ec48 | 1112 | int status = urb->status; |
ac718b69 | 1113 | |
ebc2ec48 | 1114 | agg = urb->context; |
1115 | if (!agg) | |
ac718b69 | 1116 | return; |
1117 | ||
ebc2ec48 | 1118 | tp = agg->context; |
1119 | if (!tp) | |
1120 | return; | |
1121 | ||
d104eafa | 1122 | netdev = tp->netdev; |
05e0f1aa | 1123 | stats = &netdev->stats; |
ebc2ec48 | 1124 | if (status) { |
4a8deae2 | 1125 | if (net_ratelimit()) |
d104eafa | 1126 | netdev_warn(netdev, "Tx status %d\n", status); |
ebc2ec48 | 1127 | stats->tx_errors += agg->skb_num; |
ac718b69 | 1128 | } else { |
ebc2ec48 | 1129 | stats->tx_packets += agg->skb_num; |
1130 | stats->tx_bytes += agg->skb_len; | |
ac718b69 | 1131 | } |
1132 | ||
2685d410 | 1133 | spin_lock(&tp->tx_lock); |
ebc2ec48 | 1134 | list_add_tail(&agg->list, &tp->tx_free); |
2685d410 | 1135 | spin_unlock(&tp->tx_lock); |
ebc2ec48 | 1136 | |
9a4be1bd | 1137 | usb_autopm_put_interface_async(tp->intf); |
1138 | ||
d104eafa | 1139 | if (!netif_carrier_ok(netdev)) |
ebc2ec48 | 1140 | return; |
1141 | ||
1142 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
1143 | return; | |
1144 | ||
1145 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
1146 | return; | |
1147 | ||
1148 | if (!skb_queue_empty(&tp->tx_queue)) | |
d823ab68 | 1149 | napi_schedule(&tp->napi); |
ac718b69 | 1150 | } |
1151 | ||
40a82917 | 1152 | static void intr_callback(struct urb *urb) |
1153 | { | |
1154 | struct r8152 *tp; | |
500b6d7e | 1155 | __le16 *d; |
40a82917 | 1156 | int status = urb->status; |
1157 | int res; | |
1158 | ||
1159 | tp = urb->context; | |
1160 | if (!tp) | |
1161 | return; | |
1162 | ||
1163 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
1164 | return; | |
1165 | ||
1166 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
1167 | return; | |
1168 | ||
1169 | switch (status) { | |
1170 | case 0: /* success */ | |
1171 | break; | |
1172 | case -ECONNRESET: /* unlink */ | |
1173 | case -ESHUTDOWN: | |
1174 | netif_device_detach(tp->netdev); | |
1175 | case -ENOENT: | |
d59c876d | 1176 | case -EPROTO: |
1177 | netif_info(tp, intr, tp->netdev, | |
1178 | "Stop submitting intr, status %d\n", status); | |
40a82917 | 1179 | return; |
1180 | case -EOVERFLOW: | |
1181 | netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n"); | |
1182 | goto resubmit; | |
1183 | /* -EPIPE: should clear the halt */ | |
1184 | default: | |
1185 | netif_info(tp, intr, tp->netdev, "intr status %d\n", status); | |
1186 | goto resubmit; | |
1187 | } | |
1188 | ||
1189 | d = urb->transfer_buffer; | |
1190 | if (INTR_LINK & __le16_to_cpu(d[0])) { | |
51d979fa | 1191 | if (!netif_carrier_ok(tp->netdev)) { |
40a82917 | 1192 | set_bit(RTL8152_LINK_CHG, &tp->flags); |
1193 | schedule_delayed_work(&tp->schedule, 0); | |
1194 | } | |
1195 | } else { | |
51d979fa | 1196 | if (netif_carrier_ok(tp->netdev)) { |
40a82917 | 1197 | set_bit(RTL8152_LINK_CHG, &tp->flags); |
1198 | schedule_delayed_work(&tp->schedule, 0); | |
1199 | } | |
1200 | } | |
1201 | ||
1202 | resubmit: | |
1203 | res = usb_submit_urb(urb, GFP_ATOMIC); | |
67610496 | 1204 | if (res == -ENODEV) { |
1205 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
40a82917 | 1206 | netif_device_detach(tp->netdev); |
67610496 | 1207 | } else if (res) { |
40a82917 | 1208 | netif_err(tp, intr, tp->netdev, |
4a8deae2 | 1209 | "can't resubmit intr, status %d\n", res); |
67610496 | 1210 | } |
40a82917 | 1211 | } |
1212 | ||
ebc2ec48 | 1213 | static inline void *rx_agg_align(void *data) |
1214 | { | |
8e1f51bd | 1215 | return (void *)ALIGN((uintptr_t)data, RX_ALIGN); |
ebc2ec48 | 1216 | } |
1217 | ||
1218 | static inline void *tx_agg_align(void *data) | |
1219 | { | |
8e1f51bd | 1220 | return (void *)ALIGN((uintptr_t)data, TX_ALIGN); |
ebc2ec48 | 1221 | } |
1222 | ||
1223 | static void free_all_mem(struct r8152 *tp) | |
1224 | { | |
1225 | int i; | |
1226 | ||
1227 | for (i = 0; i < RTL8152_MAX_RX; i++) { | |
9629e3c0 | 1228 | usb_free_urb(tp->rx_info[i].urb); |
1229 | tp->rx_info[i].urb = NULL; | |
ebc2ec48 | 1230 | |
9629e3c0 | 1231 | kfree(tp->rx_info[i].buffer); |
1232 | tp->rx_info[i].buffer = NULL; | |
1233 | tp->rx_info[i].head = NULL; | |
ebc2ec48 | 1234 | } |
1235 | ||
1236 | for (i = 0; i < RTL8152_MAX_TX; i++) { | |
9629e3c0 | 1237 | usb_free_urb(tp->tx_info[i].urb); |
1238 | tp->tx_info[i].urb = NULL; | |
ebc2ec48 | 1239 | |
9629e3c0 | 1240 | kfree(tp->tx_info[i].buffer); |
1241 | tp->tx_info[i].buffer = NULL; | |
1242 | tp->tx_info[i].head = NULL; | |
ebc2ec48 | 1243 | } |
40a82917 | 1244 | |
9629e3c0 | 1245 | usb_free_urb(tp->intr_urb); |
1246 | tp->intr_urb = NULL; | |
40a82917 | 1247 | |
9629e3c0 | 1248 | kfree(tp->intr_buff); |
1249 | tp->intr_buff = NULL; | |
ebc2ec48 | 1250 | } |
1251 | ||
1252 | static int alloc_all_mem(struct r8152 *tp) | |
1253 | { | |
1254 | struct net_device *netdev = tp->netdev; | |
40a82917 | 1255 | struct usb_interface *intf = tp->intf; |
1256 | struct usb_host_interface *alt = intf->cur_altsetting; | |
1257 | struct usb_host_endpoint *ep_intr = alt->endpoint + 2; | |
ebc2ec48 | 1258 | struct urb *urb; |
1259 | int node, i; | |
1260 | u8 *buf; | |
1261 | ||
1262 | node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; | |
1263 | ||
1264 | spin_lock_init(&tp->rx_lock); | |
1265 | spin_lock_init(&tp->tx_lock); | |
ebc2ec48 | 1266 | INIT_LIST_HEAD(&tp->tx_free); |
1267 | skb_queue_head_init(&tp->tx_queue); | |
d823ab68 | 1268 | skb_queue_head_init(&tp->rx_queue); |
ebc2ec48 | 1269 | |
1270 | for (i = 0; i < RTL8152_MAX_RX; i++) { | |
52aec126 | 1271 | buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); |
ebc2ec48 | 1272 | if (!buf) |
1273 | goto err1; | |
1274 | ||
1275 | if (buf != rx_agg_align(buf)) { | |
1276 | kfree(buf); | |
52aec126 | 1277 | buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL, |
8e1f51bd | 1278 | node); |
ebc2ec48 | 1279 | if (!buf) |
1280 | goto err1; | |
1281 | } | |
1282 | ||
1283 | urb = usb_alloc_urb(0, GFP_KERNEL); | |
1284 | if (!urb) { | |
1285 | kfree(buf); | |
1286 | goto err1; | |
1287 | } | |
1288 | ||
1289 | INIT_LIST_HEAD(&tp->rx_info[i].list); | |
1290 | tp->rx_info[i].context = tp; | |
1291 | tp->rx_info[i].urb = urb; | |
1292 | tp->rx_info[i].buffer = buf; | |
1293 | tp->rx_info[i].head = rx_agg_align(buf); | |
1294 | } | |
1295 | ||
1296 | for (i = 0; i < RTL8152_MAX_TX; i++) { | |
52aec126 | 1297 | buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); |
ebc2ec48 | 1298 | if (!buf) |
1299 | goto err1; | |
1300 | ||
1301 | if (buf != tx_agg_align(buf)) { | |
1302 | kfree(buf); | |
52aec126 | 1303 | buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL, |
8e1f51bd | 1304 | node); |
ebc2ec48 | 1305 | if (!buf) |
1306 | goto err1; | |
1307 | } | |
1308 | ||
1309 | urb = usb_alloc_urb(0, GFP_KERNEL); | |
1310 | if (!urb) { | |
1311 | kfree(buf); | |
1312 | goto err1; | |
1313 | } | |
1314 | ||
1315 | INIT_LIST_HEAD(&tp->tx_info[i].list); | |
1316 | tp->tx_info[i].context = tp; | |
1317 | tp->tx_info[i].urb = urb; | |
1318 | tp->tx_info[i].buffer = buf; | |
1319 | tp->tx_info[i].head = tx_agg_align(buf); | |
1320 | ||
1321 | list_add_tail(&tp->tx_info[i].list, &tp->tx_free); | |
1322 | } | |
1323 | ||
40a82917 | 1324 | tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL); |
1325 | if (!tp->intr_urb) | |
1326 | goto err1; | |
1327 | ||
1328 | tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL); | |
1329 | if (!tp->intr_buff) | |
1330 | goto err1; | |
1331 | ||
1332 | tp->intr_interval = (int)ep_intr->desc.bInterval; | |
1333 | usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3), | |
b209af99 | 1334 | tp->intr_buff, INTBUFSIZE, intr_callback, |
1335 | tp, tp->intr_interval); | |
40a82917 | 1336 | |
ebc2ec48 | 1337 | return 0; |
1338 | ||
1339 | err1: | |
1340 | free_all_mem(tp); | |
1341 | return -ENOMEM; | |
1342 | } | |
1343 | ||
0de98f6c | 1344 | static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp) |
1345 | { | |
1346 | struct tx_agg *agg = NULL; | |
1347 | unsigned long flags; | |
1348 | ||
21949ab7 | 1349 | if (list_empty(&tp->tx_free)) |
1350 | return NULL; | |
1351 | ||
0de98f6c | 1352 | spin_lock_irqsave(&tp->tx_lock, flags); |
1353 | if (!list_empty(&tp->tx_free)) { | |
1354 | struct list_head *cursor; | |
1355 | ||
1356 | cursor = tp->tx_free.next; | |
1357 | list_del_init(cursor); | |
1358 | agg = list_entry(cursor, struct tx_agg, list); | |
1359 | } | |
1360 | spin_unlock_irqrestore(&tp->tx_lock, flags); | |
1361 | ||
1362 | return agg; | |
1363 | } | |
1364 | ||
b209af99 | 1365 | /* r8152_csum_workaround() |
6128d1bb | 1366 | * The hw limites the value the transport offset. When the offset is out of the |
1367 | * range, calculate the checksum by sw. | |
1368 | */ | |
1369 | static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb, | |
1370 | struct sk_buff_head *list) | |
1371 | { | |
1372 | if (skb_shinfo(skb)->gso_size) { | |
1373 | netdev_features_t features = tp->netdev->features; | |
1374 | struct sk_buff_head seg_list; | |
1375 | struct sk_buff *segs, *nskb; | |
1376 | ||
a91d45f1 | 1377 | features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6); |
6128d1bb | 1378 | segs = skb_gso_segment(skb, features); |
1379 | if (IS_ERR(segs) || !segs) | |
1380 | goto drop; | |
1381 | ||
1382 | __skb_queue_head_init(&seg_list); | |
1383 | ||
1384 | do { | |
1385 | nskb = segs; | |
1386 | segs = segs->next; | |
1387 | nskb->next = NULL; | |
1388 | __skb_queue_tail(&seg_list, nskb); | |
1389 | } while (segs); | |
1390 | ||
1391 | skb_queue_splice(&seg_list, list); | |
1392 | dev_kfree_skb(skb); | |
1393 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
1394 | if (skb_checksum_help(skb) < 0) | |
1395 | goto drop; | |
1396 | ||
1397 | __skb_queue_head(list, skb); | |
1398 | } else { | |
1399 | struct net_device_stats *stats; | |
1400 | ||
1401 | drop: | |
1402 | stats = &tp->netdev->stats; | |
1403 | stats->tx_dropped++; | |
1404 | dev_kfree_skb(skb); | |
1405 | } | |
1406 | } | |
1407 | ||
b209af99 | 1408 | /* msdn_giant_send_check() |
6128d1bb | 1409 | * According to the document of microsoft, the TCP Pseudo Header excludes the |
1410 | * packet length for IPv6 TCP large packets. | |
1411 | */ | |
1412 | static int msdn_giant_send_check(struct sk_buff *skb) | |
1413 | { | |
1414 | const struct ipv6hdr *ipv6h; | |
1415 | struct tcphdr *th; | |
fcb308d5 | 1416 | int ret; |
1417 | ||
1418 | ret = skb_cow_head(skb, 0); | |
1419 | if (ret) | |
1420 | return ret; | |
6128d1bb | 1421 | |
1422 | ipv6h = ipv6_hdr(skb); | |
1423 | th = tcp_hdr(skb); | |
1424 | ||
1425 | th->check = 0; | |
1426 | th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0); | |
1427 | ||
fcb308d5 | 1428 | return ret; |
6128d1bb | 1429 | } |
1430 | ||
c5554298 | 1431 | static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb) |
1432 | { | |
df8a39de | 1433 | if (skb_vlan_tag_present(skb)) { |
c5554298 | 1434 | u32 opts2; |
1435 | ||
df8a39de | 1436 | opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb)); |
c5554298 | 1437 | desc->opts2 |= cpu_to_le32(opts2); |
1438 | } | |
1439 | } | |
1440 | ||
1441 | static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb) | |
1442 | { | |
1443 | u32 opts2 = le32_to_cpu(desc->opts2); | |
1444 | ||
1445 | if (opts2 & RX_VLAN_TAG) | |
1446 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), | |
1447 | swab16(opts2 & 0xffff)); | |
1448 | } | |
1449 | ||
60c89071 | 1450 | static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, |
1451 | struct sk_buff *skb, u32 len, u32 transport_offset) | |
1452 | { | |
1453 | u32 mss = skb_shinfo(skb)->gso_size; | |
1454 | u32 opts1, opts2 = 0; | |
1455 | int ret = TX_CSUM_SUCCESS; | |
1456 | ||
1457 | WARN_ON_ONCE(len > TX_LEN_MAX); | |
1458 | ||
1459 | opts1 = len | TX_FS | TX_LS; | |
1460 | ||
1461 | if (mss) { | |
6128d1bb | 1462 | if (transport_offset > GTTCPHO_MAX) { |
1463 | netif_warn(tp, tx_err, tp->netdev, | |
1464 | "Invalid transport offset 0x%x for TSO\n", | |
1465 | transport_offset); | |
1466 | ret = TX_CSUM_TSO; | |
1467 | goto unavailable; | |
1468 | } | |
1469 | ||
6e74d174 | 1470 | switch (vlan_get_protocol(skb)) { |
60c89071 | 1471 | case htons(ETH_P_IP): |
1472 | opts1 |= GTSENDV4; | |
1473 | break; | |
1474 | ||
6128d1bb | 1475 | case htons(ETH_P_IPV6): |
fcb308d5 | 1476 | if (msdn_giant_send_check(skb)) { |
1477 | ret = TX_CSUM_TSO; | |
1478 | goto unavailable; | |
1479 | } | |
6128d1bb | 1480 | opts1 |= GTSENDV6; |
6128d1bb | 1481 | break; |
1482 | ||
60c89071 | 1483 | default: |
1484 | WARN_ON_ONCE(1); | |
1485 | break; | |
1486 | } | |
1487 | ||
1488 | opts1 |= transport_offset << GTTCPHO_SHIFT; | |
1489 | opts2 |= min(mss, MSS_MAX) << MSS_SHIFT; | |
1490 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
1491 | u8 ip_protocol; | |
5bd23881 | 1492 | |
6128d1bb | 1493 | if (transport_offset > TCPHO_MAX) { |
1494 | netif_warn(tp, tx_err, tp->netdev, | |
1495 | "Invalid transport offset 0x%x\n", | |
1496 | transport_offset); | |
1497 | ret = TX_CSUM_NONE; | |
1498 | goto unavailable; | |
1499 | } | |
1500 | ||
6e74d174 | 1501 | switch (vlan_get_protocol(skb)) { |
5bd23881 | 1502 | case htons(ETH_P_IP): |
1503 | opts2 |= IPV4_CS; | |
1504 | ip_protocol = ip_hdr(skb)->protocol; | |
1505 | break; | |
1506 | ||
1507 | case htons(ETH_P_IPV6): | |
1508 | opts2 |= IPV6_CS; | |
1509 | ip_protocol = ipv6_hdr(skb)->nexthdr; | |
1510 | break; | |
1511 | ||
1512 | default: | |
1513 | ip_protocol = IPPROTO_RAW; | |
1514 | break; | |
1515 | } | |
1516 | ||
60c89071 | 1517 | if (ip_protocol == IPPROTO_TCP) |
5bd23881 | 1518 | opts2 |= TCP_CS; |
60c89071 | 1519 | else if (ip_protocol == IPPROTO_UDP) |
5bd23881 | 1520 | opts2 |= UDP_CS; |
60c89071 | 1521 | else |
5bd23881 | 1522 | WARN_ON_ONCE(1); |
5bd23881 | 1523 | |
60c89071 | 1524 | opts2 |= transport_offset << TCPHO_SHIFT; |
5bd23881 | 1525 | } |
60c89071 | 1526 | |
1527 | desc->opts2 = cpu_to_le32(opts2); | |
1528 | desc->opts1 = cpu_to_le32(opts1); | |
1529 | ||
6128d1bb | 1530 | unavailable: |
60c89071 | 1531 | return ret; |
5bd23881 | 1532 | } |
1533 | ||
b1379d9a | 1534 | static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg) |
1535 | { | |
d84130a1 | 1536 | struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; |
9a4be1bd | 1537 | int remain, ret; |
b1379d9a | 1538 | u8 *tx_data; |
1539 | ||
d84130a1 | 1540 | __skb_queue_head_init(&skb_head); |
0c3121fc | 1541 | spin_lock(&tx_queue->lock); |
d84130a1 | 1542 | skb_queue_splice_init(tx_queue, &skb_head); |
0c3121fc | 1543 | spin_unlock(&tx_queue->lock); |
d84130a1 | 1544 | |
b1379d9a | 1545 | tx_data = agg->head; |
b209af99 | 1546 | agg->skb_num = 0; |
1547 | agg->skb_len = 0; | |
52aec126 | 1548 | remain = agg_buf_sz; |
b1379d9a | 1549 | |
7937f9e5 | 1550 | while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) { |
b1379d9a | 1551 | struct tx_desc *tx_desc; |
1552 | struct sk_buff *skb; | |
1553 | unsigned int len; | |
60c89071 | 1554 | u32 offset; |
b1379d9a | 1555 | |
d84130a1 | 1556 | skb = __skb_dequeue(&skb_head); |
b1379d9a | 1557 | if (!skb) |
1558 | break; | |
1559 | ||
60c89071 | 1560 | len = skb->len + sizeof(*tx_desc); |
1561 | ||
1562 | if (len > remain) { | |
d84130a1 | 1563 | __skb_queue_head(&skb_head, skb); |
b1379d9a | 1564 | break; |
1565 | } | |
1566 | ||
7937f9e5 | 1567 | tx_data = tx_agg_align(tx_data); |
b1379d9a | 1568 | tx_desc = (struct tx_desc *)tx_data; |
60c89071 | 1569 | |
1570 | offset = (u32)skb_transport_offset(skb); | |
1571 | ||
6128d1bb | 1572 | if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) { |
1573 | r8152_csum_workaround(tp, skb, &skb_head); | |
1574 | continue; | |
1575 | } | |
60c89071 | 1576 | |
c5554298 | 1577 | rtl_tx_vlan_tag(tx_desc, skb); |
1578 | ||
b1379d9a | 1579 | tx_data += sizeof(*tx_desc); |
1580 | ||
60c89071 | 1581 | len = skb->len; |
1582 | if (skb_copy_bits(skb, 0, tx_data, len) < 0) { | |
1583 | struct net_device_stats *stats = &tp->netdev->stats; | |
1584 | ||
1585 | stats->tx_dropped++; | |
1586 | dev_kfree_skb_any(skb); | |
1587 | tx_data -= sizeof(*tx_desc); | |
1588 | continue; | |
1589 | } | |
1590 | ||
1591 | tx_data += len; | |
b1379d9a | 1592 | agg->skb_len += len; |
60c89071 | 1593 | agg->skb_num++; |
1594 | ||
b1379d9a | 1595 | dev_kfree_skb_any(skb); |
1596 | ||
52aec126 | 1597 | remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head); |
b1379d9a | 1598 | } |
1599 | ||
d84130a1 | 1600 | if (!skb_queue_empty(&skb_head)) { |
0c3121fc | 1601 | spin_lock(&tx_queue->lock); |
d84130a1 | 1602 | skb_queue_splice(&skb_head, tx_queue); |
0c3121fc | 1603 | spin_unlock(&tx_queue->lock); |
d84130a1 | 1604 | } |
1605 | ||
0c3121fc | 1606 | netif_tx_lock(tp->netdev); |
dd1b119c | 1607 | |
1608 | if (netif_queue_stopped(tp->netdev) && | |
1609 | skb_queue_len(&tp->tx_queue) < tp->tx_qlen) | |
1610 | netif_wake_queue(tp->netdev); | |
1611 | ||
0c3121fc | 1612 | netif_tx_unlock(tp->netdev); |
9a4be1bd | 1613 | |
0c3121fc | 1614 | ret = usb_autopm_get_interface_async(tp->intf); |
9a4be1bd | 1615 | if (ret < 0) |
1616 | goto out_tx_fill; | |
dd1b119c | 1617 | |
b1379d9a | 1618 | usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2), |
1619 | agg->head, (int)(tx_data - (u8 *)agg->head), | |
1620 | (usb_complete_t)write_bulk_callback, agg); | |
1621 | ||
0c3121fc | 1622 | ret = usb_submit_urb(agg->urb, GFP_ATOMIC); |
9a4be1bd | 1623 | if (ret < 0) |
0c3121fc | 1624 | usb_autopm_put_interface_async(tp->intf); |
9a4be1bd | 1625 | |
1626 | out_tx_fill: | |
1627 | return ret; | |
b1379d9a | 1628 | } |
1629 | ||
565cab0a | 1630 | static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc) |
1631 | { | |
1632 | u8 checksum = CHECKSUM_NONE; | |
1633 | u32 opts2, opts3; | |
1634 | ||
1635 | if (tp->version == RTL_VER_01) | |
1636 | goto return_result; | |
1637 | ||
1638 | opts2 = le32_to_cpu(rx_desc->opts2); | |
1639 | opts3 = le32_to_cpu(rx_desc->opts3); | |
1640 | ||
1641 | if (opts2 & RD_IPV4_CS) { | |
1642 | if (opts3 & IPF) | |
1643 | checksum = CHECKSUM_NONE; | |
1644 | else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF)) | |
1645 | checksum = CHECKSUM_NONE; | |
1646 | else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF)) | |
1647 | checksum = CHECKSUM_NONE; | |
1648 | else | |
1649 | checksum = CHECKSUM_UNNECESSARY; | |
6128d1bb | 1650 | } else if (RD_IPV6_CS) { |
1651 | if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF)) | |
1652 | checksum = CHECKSUM_UNNECESSARY; | |
1653 | else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF)) | |
1654 | checksum = CHECKSUM_UNNECESSARY; | |
565cab0a | 1655 | } |
1656 | ||
1657 | return_result: | |
1658 | return checksum; | |
1659 | } | |
1660 | ||
d823ab68 | 1661 | static int rx_bottom(struct r8152 *tp, int budget) |
ebc2ec48 | 1662 | { |
a5a4f468 | 1663 | unsigned long flags; |
d84130a1 | 1664 | struct list_head *cursor, *next, rx_queue; |
e1a2ca92 | 1665 | int ret = 0, work_done = 0; |
d823ab68 | 1666 | |
1667 | if (!skb_queue_empty(&tp->rx_queue)) { | |
1668 | while (work_done < budget) { | |
1669 | struct sk_buff *skb = __skb_dequeue(&tp->rx_queue); | |
1670 | struct net_device *netdev = tp->netdev; | |
1671 | struct net_device_stats *stats = &netdev->stats; | |
1672 | unsigned int pkt_len; | |
1673 | ||
1674 | if (!skb) | |
1675 | break; | |
1676 | ||
1677 | pkt_len = skb->len; | |
1678 | napi_gro_receive(&tp->napi, skb); | |
1679 | work_done++; | |
1680 | stats->rx_packets++; | |
1681 | stats->rx_bytes += pkt_len; | |
1682 | } | |
1683 | } | |
ebc2ec48 | 1684 | |
d84130a1 | 1685 | if (list_empty(&tp->rx_done)) |
d823ab68 | 1686 | goto out1; |
d84130a1 | 1687 | |
1688 | INIT_LIST_HEAD(&rx_queue); | |
a5a4f468 | 1689 | spin_lock_irqsave(&tp->rx_lock, flags); |
d84130a1 | 1690 | list_splice_init(&tp->rx_done, &rx_queue); |
1691 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
1692 | ||
1693 | list_for_each_safe(cursor, next, &rx_queue) { | |
43a4478d | 1694 | struct rx_desc *rx_desc; |
1695 | struct rx_agg *agg; | |
43a4478d | 1696 | int len_used = 0; |
1697 | struct urb *urb; | |
1698 | u8 *rx_data; | |
43a4478d | 1699 | |
ebc2ec48 | 1700 | list_del_init(cursor); |
ebc2ec48 | 1701 | |
1702 | agg = list_entry(cursor, struct rx_agg, list); | |
1703 | urb = agg->urb; | |
0de98f6c | 1704 | if (urb->actual_length < ETH_ZLEN) |
1705 | goto submit; | |
ebc2ec48 | 1706 | |
ebc2ec48 | 1707 | rx_desc = agg->head; |
1708 | rx_data = agg->head; | |
7937f9e5 | 1709 | len_used += sizeof(struct rx_desc); |
ebc2ec48 | 1710 | |
7937f9e5 | 1711 | while (urb->actual_length > len_used) { |
43a4478d | 1712 | struct net_device *netdev = tp->netdev; |
05e0f1aa | 1713 | struct net_device_stats *stats = &netdev->stats; |
7937f9e5 | 1714 | unsigned int pkt_len; |
43a4478d | 1715 | struct sk_buff *skb; |
1716 | ||
7937f9e5 | 1717 | pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; |
ebc2ec48 | 1718 | if (pkt_len < ETH_ZLEN) |
1719 | break; | |
1720 | ||
7937f9e5 | 1721 | len_used += pkt_len; |
1722 | if (urb->actual_length < len_used) | |
1723 | break; | |
1724 | ||
8e1f51bd | 1725 | pkt_len -= CRC_SIZE; |
ebc2ec48 | 1726 | rx_data += sizeof(struct rx_desc); |
1727 | ||
1728 | skb = netdev_alloc_skb_ip_align(netdev, pkt_len); | |
1729 | if (!skb) { | |
1730 | stats->rx_dropped++; | |
5e2f7485 | 1731 | goto find_next_rx; |
ebc2ec48 | 1732 | } |
565cab0a | 1733 | |
1734 | skb->ip_summed = r8152_rx_csum(tp, rx_desc); | |
ebc2ec48 | 1735 | memcpy(skb->data, rx_data, pkt_len); |
1736 | skb_put(skb, pkt_len); | |
1737 | skb->protocol = eth_type_trans(skb, netdev); | |
c5554298 | 1738 | rtl_rx_vlan_tag(rx_desc, skb); |
d823ab68 | 1739 | if (work_done < budget) { |
1740 | napi_gro_receive(&tp->napi, skb); | |
1741 | work_done++; | |
1742 | stats->rx_packets++; | |
1743 | stats->rx_bytes += pkt_len; | |
1744 | } else { | |
1745 | __skb_queue_tail(&tp->rx_queue, skb); | |
1746 | } | |
ebc2ec48 | 1747 | |
5e2f7485 | 1748 | find_next_rx: |
8e1f51bd | 1749 | rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE); |
ebc2ec48 | 1750 | rx_desc = (struct rx_desc *)rx_data; |
ebc2ec48 | 1751 | len_used = (int)(rx_data - (u8 *)agg->head); |
7937f9e5 | 1752 | len_used += sizeof(struct rx_desc); |
ebc2ec48 | 1753 | } |
1754 | ||
0de98f6c | 1755 | submit: |
e1a2ca92 | 1756 | if (!ret) { |
1757 | ret = r8152_submit_rx(tp, agg, GFP_ATOMIC); | |
1758 | } else { | |
1759 | urb->actual_length = 0; | |
1760 | list_add_tail(&agg->list, next); | |
1761 | } | |
1762 | } | |
1763 | ||
1764 | if (!list_empty(&rx_queue)) { | |
1765 | spin_lock_irqsave(&tp->rx_lock, flags); | |
1766 | list_splice_tail(&rx_queue, &tp->rx_done); | |
1767 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
ebc2ec48 | 1768 | } |
d823ab68 | 1769 | |
1770 | out1: | |
1771 | return work_done; | |
ebc2ec48 | 1772 | } |
1773 | ||
1774 | static void tx_bottom(struct r8152 *tp) | |
1775 | { | |
ebc2ec48 | 1776 | int res; |
1777 | ||
b1379d9a | 1778 | do { |
1779 | struct tx_agg *agg; | |
ebc2ec48 | 1780 | |
b1379d9a | 1781 | if (skb_queue_empty(&tp->tx_queue)) |
ebc2ec48 | 1782 | break; |
1783 | ||
b1379d9a | 1784 | agg = r8152_get_tx_agg(tp); |
1785 | if (!agg) | |
ebc2ec48 | 1786 | break; |
ebc2ec48 | 1787 | |
b1379d9a | 1788 | res = r8152_tx_agg_fill(tp, agg); |
1789 | if (res) { | |
05e0f1aa | 1790 | struct net_device *netdev = tp->netdev; |
ebc2ec48 | 1791 | |
b1379d9a | 1792 | if (res == -ENODEV) { |
67610496 | 1793 | set_bit(RTL8152_UNPLUG, &tp->flags); |
b1379d9a | 1794 | netif_device_detach(netdev); |
1795 | } else { | |
05e0f1aa | 1796 | struct net_device_stats *stats = &netdev->stats; |
1797 | unsigned long flags; | |
1798 | ||
b1379d9a | 1799 | netif_warn(tp, tx_err, netdev, |
1800 | "failed tx_urb %d\n", res); | |
1801 | stats->tx_dropped += agg->skb_num; | |
db8515ef | 1802 | |
b1379d9a | 1803 | spin_lock_irqsave(&tp->tx_lock, flags); |
1804 | list_add_tail(&agg->list, &tp->tx_free); | |
1805 | spin_unlock_irqrestore(&tp->tx_lock, flags); | |
1806 | } | |
ebc2ec48 | 1807 | } |
b1379d9a | 1808 | } while (res == 0); |
ebc2ec48 | 1809 | } |
1810 | ||
d823ab68 | 1811 | static void bottom_half(struct r8152 *tp) |
ac718b69 | 1812 | { |
ebc2ec48 | 1813 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
1814 | return; | |
1815 | ||
1816 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
ac718b69 | 1817 | return; |
ebc2ec48 | 1818 | |
7559fb2f | 1819 | /* When link down, the driver would cancel all bulks. */ |
1820 | /* This avoid the re-submitting bulk */ | |
ebc2ec48 | 1821 | if (!netif_carrier_ok(tp->netdev)) |
ac718b69 | 1822 | return; |
ebc2ec48 | 1823 | |
d823ab68 | 1824 | clear_bit(SCHEDULE_NAPI, &tp->flags); |
9451a11c | 1825 | |
0c3121fc | 1826 | tx_bottom(tp); |
ebc2ec48 | 1827 | } |
1828 | ||
d823ab68 | 1829 | static int r8152_poll(struct napi_struct *napi, int budget) |
1830 | { | |
1831 | struct r8152 *tp = container_of(napi, struct r8152, napi); | |
1832 | int work_done; | |
1833 | ||
1834 | work_done = rx_bottom(tp, budget); | |
1835 | bottom_half(tp); | |
1836 | ||
1837 | if (work_done < budget) { | |
1838 | napi_complete(napi); | |
1839 | if (!list_empty(&tp->rx_done)) | |
1840 | napi_schedule(napi); | |
1841 | } | |
1842 | ||
1843 | return work_done; | |
1844 | } | |
1845 | ||
ebc2ec48 | 1846 | static |
1847 | int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags) | |
1848 | { | |
a0fccd48 | 1849 | int ret; |
1850 | ||
ef827a5b | 1851 | /* The rx would be stopped, so skip submitting */ |
1852 | if (test_bit(RTL8152_UNPLUG, &tp->flags) || | |
1853 | !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev)) | |
1854 | return 0; | |
1855 | ||
ebc2ec48 | 1856 | usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1), |
52aec126 | 1857 | agg->head, agg_buf_sz, |
b209af99 | 1858 | (usb_complete_t)read_bulk_callback, agg); |
ebc2ec48 | 1859 | |
a0fccd48 | 1860 | ret = usb_submit_urb(agg->urb, mem_flags); |
1861 | if (ret == -ENODEV) { | |
1862 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
1863 | netif_device_detach(tp->netdev); | |
1864 | } else if (ret) { | |
1865 | struct urb *urb = agg->urb; | |
1866 | unsigned long flags; | |
1867 | ||
1868 | urb->actual_length = 0; | |
1869 | spin_lock_irqsave(&tp->rx_lock, flags); | |
1870 | list_add_tail(&agg->list, &tp->rx_done); | |
1871 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
d823ab68 | 1872 | |
1873 | netif_err(tp, rx_err, tp->netdev, | |
1874 | "Couldn't submit rx[%p], ret = %d\n", agg, ret); | |
1875 | ||
1876 | napi_schedule(&tp->napi); | |
a0fccd48 | 1877 | } |
1878 | ||
1879 | return ret; | |
ac718b69 | 1880 | } |
1881 | ||
00a5e360 | 1882 | static void rtl_drop_queued_tx(struct r8152 *tp) |
1883 | { | |
1884 | struct net_device_stats *stats = &tp->netdev->stats; | |
d84130a1 | 1885 | struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; |
00a5e360 | 1886 | struct sk_buff *skb; |
1887 | ||
d84130a1 | 1888 | if (skb_queue_empty(tx_queue)) |
1889 | return; | |
1890 | ||
1891 | __skb_queue_head_init(&skb_head); | |
2685d410 | 1892 | spin_lock_bh(&tx_queue->lock); |
d84130a1 | 1893 | skb_queue_splice_init(tx_queue, &skb_head); |
2685d410 | 1894 | spin_unlock_bh(&tx_queue->lock); |
d84130a1 | 1895 | |
1896 | while ((skb = __skb_dequeue(&skb_head))) { | |
00a5e360 | 1897 | dev_kfree_skb(skb); |
1898 | stats->tx_dropped++; | |
1899 | } | |
1900 | } | |
1901 | ||
ac718b69 | 1902 | static void rtl8152_tx_timeout(struct net_device *netdev) |
1903 | { | |
1904 | struct r8152 *tp = netdev_priv(netdev); | |
ebc2ec48 | 1905 | int i; |
1906 | ||
4a8deae2 | 1907 | netif_warn(tp, tx_err, netdev, "Tx timeout\n"); |
ebc2ec48 | 1908 | for (i = 0; i < RTL8152_MAX_TX; i++) |
1909 | usb_unlink_urb(tp->tx_info[i].urb); | |
ac718b69 | 1910 | } |
1911 | ||
1912 | static void rtl8152_set_rx_mode(struct net_device *netdev) | |
1913 | { | |
1914 | struct r8152 *tp = netdev_priv(netdev); | |
1915 | ||
51d979fa | 1916 | if (netif_carrier_ok(netdev)) { |
ac718b69 | 1917 | set_bit(RTL8152_SET_RX_MODE, &tp->flags); |
40a82917 | 1918 | schedule_delayed_work(&tp->schedule, 0); |
1919 | } | |
ac718b69 | 1920 | } |
1921 | ||
1922 | static void _rtl8152_set_rx_mode(struct net_device *netdev) | |
1923 | { | |
1924 | struct r8152 *tp = netdev_priv(netdev); | |
31787f53 | 1925 | u32 mc_filter[2]; /* Multicast hash filter */ |
1926 | __le32 tmp[2]; | |
ac718b69 | 1927 | u32 ocp_data; |
1928 | ||
ac718b69 | 1929 | clear_bit(RTL8152_SET_RX_MODE, &tp->flags); |
1930 | netif_stop_queue(netdev); | |
1931 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
1932 | ocp_data &= ~RCR_ACPT_ALL; | |
1933 | ocp_data |= RCR_AB | RCR_APM; | |
1934 | ||
1935 | if (netdev->flags & IFF_PROMISC) { | |
1936 | /* Unconditionally log net taps. */ | |
1937 | netif_notice(tp, link, netdev, "Promiscuous mode enabled\n"); | |
1938 | ocp_data |= RCR_AM | RCR_AAP; | |
b209af99 | 1939 | mc_filter[1] = 0xffffffff; |
1940 | mc_filter[0] = 0xffffffff; | |
ac718b69 | 1941 | } else if ((netdev_mc_count(netdev) > multicast_filter_limit) || |
1942 | (netdev->flags & IFF_ALLMULTI)) { | |
1943 | /* Too many to filter perfectly -- accept all multicasts. */ | |
1944 | ocp_data |= RCR_AM; | |
b209af99 | 1945 | mc_filter[1] = 0xffffffff; |
1946 | mc_filter[0] = 0xffffffff; | |
ac718b69 | 1947 | } else { |
1948 | struct netdev_hw_addr *ha; | |
1949 | ||
b209af99 | 1950 | mc_filter[1] = 0; |
1951 | mc_filter[0] = 0; | |
ac718b69 | 1952 | netdev_for_each_mc_addr(ha, netdev) { |
1953 | int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; | |
b209af99 | 1954 | |
ac718b69 | 1955 | mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); |
1956 | ocp_data |= RCR_AM; | |
1957 | } | |
1958 | } | |
1959 | ||
31787f53 | 1960 | tmp[0] = __cpu_to_le32(swab32(mc_filter[1])); |
1961 | tmp[1] = __cpu_to_le32(swab32(mc_filter[0])); | |
ac718b69 | 1962 | |
31787f53 | 1963 | pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp); |
ac718b69 | 1964 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); |
1965 | netif_wake_queue(netdev); | |
ac718b69 | 1966 | } |
1967 | ||
a5e31255 | 1968 | static netdev_features_t |
1969 | rtl8152_features_check(struct sk_buff *skb, struct net_device *dev, | |
1970 | netdev_features_t features) | |
1971 | { | |
1972 | u32 mss = skb_shinfo(skb)->gso_size; | |
1973 | int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX; | |
1974 | int offset = skb_transport_offset(skb); | |
1975 | ||
1976 | if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset) | |
1977 | features &= ~(NETIF_F_ALL_CSUM | NETIF_F_GSO_MASK); | |
1978 | else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz) | |
1979 | features &= ~NETIF_F_GSO_MASK; | |
1980 | ||
1981 | return features; | |
1982 | } | |
1983 | ||
ac718b69 | 1984 | static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb, |
b209af99 | 1985 | struct net_device *netdev) |
ac718b69 | 1986 | { |
1987 | struct r8152 *tp = netdev_priv(netdev); | |
ac718b69 | 1988 | |
ebc2ec48 | 1989 | skb_tx_timestamp(skb); |
ac718b69 | 1990 | |
61598788 | 1991 | skb_queue_tail(&tp->tx_queue, skb); |
ebc2ec48 | 1992 | |
0c3121fc | 1993 | if (!list_empty(&tp->tx_free)) { |
1994 | if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { | |
d823ab68 | 1995 | set_bit(SCHEDULE_NAPI, &tp->flags); |
0c3121fc | 1996 | schedule_delayed_work(&tp->schedule, 0); |
1997 | } else { | |
1998 | usb_mark_last_busy(tp->udev); | |
d823ab68 | 1999 | napi_schedule(&tp->napi); |
0c3121fc | 2000 | } |
b209af99 | 2001 | } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) { |
dd1b119c | 2002 | netif_stop_queue(netdev); |
b209af99 | 2003 | } |
dd1b119c | 2004 | |
ac718b69 | 2005 | return NETDEV_TX_OK; |
2006 | } | |
2007 | ||
2008 | static void r8152b_reset_packet_filter(struct r8152 *tp) | |
2009 | { | |
2010 | u32 ocp_data; | |
2011 | ||
2012 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); | |
2013 | ocp_data &= ~FMC_FCR_MCU_EN; | |
2014 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); | |
2015 | ocp_data |= FMC_FCR_MCU_EN; | |
2016 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); | |
2017 | } | |
2018 | ||
2019 | static void rtl8152_nic_reset(struct r8152 *tp) | |
2020 | { | |
2021 | int i; | |
2022 | ||
2023 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST); | |
2024 | ||
2025 | for (i = 0; i < 1000; i++) { | |
2026 | if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST)) | |
2027 | break; | |
b209af99 | 2028 | usleep_range(100, 400); |
ac718b69 | 2029 | } |
2030 | } | |
2031 | ||
dd1b119c | 2032 | static void set_tx_qlen(struct r8152 *tp) |
2033 | { | |
2034 | struct net_device *netdev = tp->netdev; | |
2035 | ||
52aec126 | 2036 | tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN + |
2037 | sizeof(struct tx_desc)); | |
dd1b119c | 2038 | } |
2039 | ||
ac718b69 | 2040 | static inline u8 rtl8152_get_speed(struct r8152 *tp) |
2041 | { | |
2042 | return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); | |
2043 | } | |
2044 | ||
507605a8 | 2045 | static void rtl_set_eee_plus(struct r8152 *tp) |
ac718b69 | 2046 | { |
ebc2ec48 | 2047 | u32 ocp_data; |
ac718b69 | 2048 | u8 speed; |
2049 | ||
2050 | speed = rtl8152_get_speed(tp); | |
ebc2ec48 | 2051 | if (speed & _10bps) { |
ac718b69 | 2052 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); |
ebc2ec48 | 2053 | ocp_data |= EEEP_CR_EEEP_TX; |
ac718b69 | 2054 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); |
2055 | } else { | |
2056 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); | |
ebc2ec48 | 2057 | ocp_data &= ~EEEP_CR_EEEP_TX; |
ac718b69 | 2058 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); |
2059 | } | |
507605a8 | 2060 | } |
2061 | ||
00a5e360 | 2062 | static void rxdy_gated_en(struct r8152 *tp, bool enable) |
2063 | { | |
2064 | u32 ocp_data; | |
2065 | ||
2066 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); | |
2067 | if (enable) | |
2068 | ocp_data |= RXDY_GATED_EN; | |
2069 | else | |
2070 | ocp_data &= ~RXDY_GATED_EN; | |
2071 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); | |
2072 | } | |
2073 | ||
445f7f4d | 2074 | static int rtl_start_rx(struct r8152 *tp) |
2075 | { | |
2076 | int i, ret = 0; | |
2077 | ||
2078 | INIT_LIST_HEAD(&tp->rx_done); | |
2079 | for (i = 0; i < RTL8152_MAX_RX; i++) { | |
2080 | INIT_LIST_HEAD(&tp->rx_info[i].list); | |
2081 | ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL); | |
2082 | if (ret) | |
2083 | break; | |
2084 | } | |
2085 | ||
7bcf4f60 | 2086 | if (ret && ++i < RTL8152_MAX_RX) { |
2087 | struct list_head rx_queue; | |
2088 | unsigned long flags; | |
2089 | ||
2090 | INIT_LIST_HEAD(&rx_queue); | |
2091 | ||
2092 | do { | |
2093 | struct rx_agg *agg = &tp->rx_info[i++]; | |
2094 | struct urb *urb = agg->urb; | |
2095 | ||
2096 | urb->actual_length = 0; | |
2097 | list_add_tail(&agg->list, &rx_queue); | |
2098 | } while (i < RTL8152_MAX_RX); | |
2099 | ||
2100 | spin_lock_irqsave(&tp->rx_lock, flags); | |
2101 | list_splice_tail(&rx_queue, &tp->rx_done); | |
2102 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
2103 | } | |
2104 | ||
445f7f4d | 2105 | return ret; |
2106 | } | |
2107 | ||
2108 | static int rtl_stop_rx(struct r8152 *tp) | |
2109 | { | |
2110 | int i; | |
2111 | ||
2112 | for (i = 0; i < RTL8152_MAX_RX; i++) | |
2113 | usb_kill_urb(tp->rx_info[i].urb); | |
2114 | ||
d823ab68 | 2115 | while (!skb_queue_empty(&tp->rx_queue)) |
2116 | dev_kfree_skb(__skb_dequeue(&tp->rx_queue)); | |
2117 | ||
445f7f4d | 2118 | return 0; |
2119 | } | |
2120 | ||
507605a8 | 2121 | static int rtl_enable(struct r8152 *tp) |
2122 | { | |
2123 | u32 ocp_data; | |
ac718b69 | 2124 | |
2125 | r8152b_reset_packet_filter(tp); | |
2126 | ||
2127 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); | |
2128 | ocp_data |= CR_RE | CR_TE; | |
2129 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); | |
2130 | ||
00a5e360 | 2131 | rxdy_gated_en(tp, false); |
ac718b69 | 2132 | |
aa2e0926 | 2133 | return 0; |
ac718b69 | 2134 | } |
2135 | ||
507605a8 | 2136 | static int rtl8152_enable(struct r8152 *tp) |
2137 | { | |
6871438c | 2138 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
2139 | return -ENODEV; | |
2140 | ||
507605a8 | 2141 | set_tx_qlen(tp); |
2142 | rtl_set_eee_plus(tp); | |
2143 | ||
2144 | return rtl_enable(tp); | |
2145 | } | |
2146 | ||
464ec10a | 2147 | static void r8153_set_rx_early_timeout(struct r8152 *tp) |
43779f8d | 2148 | { |
464ec10a | 2149 | u32 ocp_data = tp->coalesce / 8; |
43779f8d | 2150 | |
464ec10a | 2151 | ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, ocp_data); |
2152 | } | |
2153 | ||
2154 | static void r8153_set_rx_early_size(struct r8152 *tp) | |
2155 | { | |
2156 | u32 mtu = tp->netdev->mtu; | |
2157 | u32 ocp_data = (agg_buf_sz - mtu - VLAN_ETH_HLEN - VLAN_HLEN) / 4; | |
2158 | ||
2159 | ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, ocp_data); | |
43779f8d | 2160 | } |
2161 | ||
2162 | static int rtl8153_enable(struct r8152 *tp) | |
2163 | { | |
6871438c | 2164 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
2165 | return -ENODEV; | |
2166 | ||
b214396f | 2167 | usb_disable_lpm(tp->udev); |
43779f8d | 2168 | set_tx_qlen(tp); |
2169 | rtl_set_eee_plus(tp); | |
464ec10a | 2170 | r8153_set_rx_early_timeout(tp); |
2171 | r8153_set_rx_early_size(tp); | |
43779f8d | 2172 | |
2173 | return rtl_enable(tp); | |
2174 | } | |
2175 | ||
d70b1137 | 2176 | static void rtl_disable(struct r8152 *tp) |
ac718b69 | 2177 | { |
ebc2ec48 | 2178 | u32 ocp_data; |
2179 | int i; | |
ac718b69 | 2180 | |
6871438c | 2181 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) { |
2182 | rtl_drop_queued_tx(tp); | |
2183 | return; | |
2184 | } | |
2185 | ||
ac718b69 | 2186 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); |
2187 | ocp_data &= ~RCR_ACPT_ALL; | |
2188 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2189 | ||
00a5e360 | 2190 | rtl_drop_queued_tx(tp); |
ebc2ec48 | 2191 | |
2192 | for (i = 0; i < RTL8152_MAX_TX; i++) | |
2193 | usb_kill_urb(tp->tx_info[i].urb); | |
ac718b69 | 2194 | |
00a5e360 | 2195 | rxdy_gated_en(tp, true); |
ac718b69 | 2196 | |
2197 | for (i = 0; i < 1000; i++) { | |
2198 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2199 | if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY) | |
2200 | break; | |
8ddfa077 | 2201 | usleep_range(1000, 2000); |
ac718b69 | 2202 | } |
2203 | ||
2204 | for (i = 0; i < 1000; i++) { | |
2205 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY) | |
2206 | break; | |
8ddfa077 | 2207 | usleep_range(1000, 2000); |
ac718b69 | 2208 | } |
2209 | ||
445f7f4d | 2210 | rtl_stop_rx(tp); |
ac718b69 | 2211 | |
2212 | rtl8152_nic_reset(tp); | |
2213 | } | |
2214 | ||
00a5e360 | 2215 | static void r8152_power_cut_en(struct r8152 *tp, bool enable) |
2216 | { | |
2217 | u32 ocp_data; | |
2218 | ||
2219 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); | |
2220 | if (enable) | |
2221 | ocp_data |= POWER_CUT; | |
2222 | else | |
2223 | ocp_data &= ~POWER_CUT; | |
2224 | ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); | |
2225 | ||
2226 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); | |
2227 | ocp_data &= ~RESUME_INDICATE; | |
2228 | ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); | |
00a5e360 | 2229 | } |
2230 | ||
c5554298 | 2231 | static void rtl_rx_vlan_en(struct r8152 *tp, bool enable) |
2232 | { | |
2233 | u32 ocp_data; | |
2234 | ||
2235 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); | |
2236 | if (enable) | |
2237 | ocp_data |= CPCR_RX_VLAN; | |
2238 | else | |
2239 | ocp_data &= ~CPCR_RX_VLAN; | |
2240 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); | |
2241 | } | |
2242 | ||
2243 | static int rtl8152_set_features(struct net_device *dev, | |
2244 | netdev_features_t features) | |
2245 | { | |
2246 | netdev_features_t changed = features ^ dev->features; | |
2247 | struct r8152 *tp = netdev_priv(dev); | |
405f8a0e | 2248 | int ret; |
2249 | ||
2250 | ret = usb_autopm_get_interface(tp->intf); | |
2251 | if (ret < 0) | |
2252 | goto out; | |
c5554298 | 2253 | |
b5403273 | 2254 | mutex_lock(&tp->control); |
2255 | ||
c5554298 | 2256 | if (changed & NETIF_F_HW_VLAN_CTAG_RX) { |
2257 | if (features & NETIF_F_HW_VLAN_CTAG_RX) | |
2258 | rtl_rx_vlan_en(tp, true); | |
2259 | else | |
2260 | rtl_rx_vlan_en(tp, false); | |
2261 | } | |
2262 | ||
b5403273 | 2263 | mutex_unlock(&tp->control); |
2264 | ||
405f8a0e | 2265 | usb_autopm_put_interface(tp->intf); |
2266 | ||
2267 | out: | |
2268 | return ret; | |
c5554298 | 2269 | } |
2270 | ||
21ff2e89 | 2271 | #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) |
2272 | ||
2273 | static u32 __rtl_get_wol(struct r8152 *tp) | |
2274 | { | |
2275 | u32 ocp_data; | |
2276 | u32 wolopts = 0; | |
2277 | ||
2278 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5); | |
2279 | if (!(ocp_data & LAN_WAKE_EN)) | |
2280 | return 0; | |
2281 | ||
2282 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); | |
2283 | if (ocp_data & LINK_ON_WAKE_EN) | |
2284 | wolopts |= WAKE_PHY; | |
2285 | ||
2286 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); | |
2287 | if (ocp_data & UWF_EN) | |
2288 | wolopts |= WAKE_UCAST; | |
2289 | if (ocp_data & BWF_EN) | |
2290 | wolopts |= WAKE_BCAST; | |
2291 | if (ocp_data & MWF_EN) | |
2292 | wolopts |= WAKE_MCAST; | |
2293 | ||
2294 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); | |
2295 | if (ocp_data & MAGIC_EN) | |
2296 | wolopts |= WAKE_MAGIC; | |
2297 | ||
2298 | return wolopts; | |
2299 | } | |
2300 | ||
2301 | static void __rtl_set_wol(struct r8152 *tp, u32 wolopts) | |
2302 | { | |
2303 | u32 ocp_data; | |
2304 | ||
2305 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
2306 | ||
2307 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); | |
2308 | ocp_data &= ~LINK_ON_WAKE_EN; | |
2309 | if (wolopts & WAKE_PHY) | |
2310 | ocp_data |= LINK_ON_WAKE_EN; | |
2311 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); | |
2312 | ||
2313 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); | |
2314 | ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN); | |
2315 | if (wolopts & WAKE_UCAST) | |
2316 | ocp_data |= UWF_EN; | |
2317 | if (wolopts & WAKE_BCAST) | |
2318 | ocp_data |= BWF_EN; | |
2319 | if (wolopts & WAKE_MCAST) | |
2320 | ocp_data |= MWF_EN; | |
2321 | if (wolopts & WAKE_ANY) | |
2322 | ocp_data |= LAN_WAKE_EN; | |
2323 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data); | |
2324 | ||
2325 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
2326 | ||
2327 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); | |
2328 | ocp_data &= ~MAGIC_EN; | |
2329 | if (wolopts & WAKE_MAGIC) | |
2330 | ocp_data |= MAGIC_EN; | |
2331 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data); | |
2332 | ||
2333 | if (wolopts & WAKE_ANY) | |
2334 | device_set_wakeup_enable(&tp->udev->dev, true); | |
2335 | else | |
2336 | device_set_wakeup_enable(&tp->udev->dev, false); | |
2337 | } | |
2338 | ||
b214396f | 2339 | static void r8153_u1u2en(struct r8152 *tp, bool enable) |
2340 | { | |
2341 | u8 u1u2[8]; | |
2342 | ||
2343 | if (enable) | |
2344 | memset(u1u2, 0xff, sizeof(u1u2)); | |
2345 | else | |
2346 | memset(u1u2, 0x00, sizeof(u1u2)); | |
2347 | ||
2348 | usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2); | |
2349 | } | |
2350 | ||
2351 | static void r8153_u2p3en(struct r8152 *tp, bool enable) | |
2352 | { | |
2353 | u32 ocp_data; | |
2354 | ||
2355 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); | |
2356 | if (enable && tp->version != RTL_VER_03 && tp->version != RTL_VER_04) | |
2357 | ocp_data |= U2P3_ENABLE; | |
2358 | else | |
2359 | ocp_data &= ~U2P3_ENABLE; | |
2360 | ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); | |
2361 | } | |
2362 | ||
2363 | static void r8153_power_cut_en(struct r8152 *tp, bool enable) | |
2364 | { | |
2365 | u32 ocp_data; | |
2366 | ||
2367 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); | |
2368 | if (enable) | |
2369 | ocp_data |= PWR_EN | PHASE2_EN; | |
2370 | else | |
2371 | ocp_data &= ~(PWR_EN | PHASE2_EN); | |
2372 | ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); | |
2373 | ||
2374 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); | |
2375 | ocp_data &= ~PCUT_STATUS; | |
2376 | ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); | |
2377 | } | |
2378 | ||
7daed8dc | 2379 | static bool rtl_can_wakeup(struct r8152 *tp) |
2380 | { | |
2381 | struct usb_device *udev = tp->udev; | |
2382 | ||
2383 | return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP); | |
2384 | } | |
2385 | ||
9a4be1bd | 2386 | static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable) |
2387 | { | |
2388 | if (enable) { | |
2389 | u32 ocp_data; | |
2390 | ||
b214396f | 2391 | r8153_u1u2en(tp, false); |
2392 | r8153_u2p3en(tp, false); | |
2393 | ||
9a4be1bd | 2394 | __rtl_set_wol(tp, WAKE_ANY); |
2395 | ||
2396 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
2397 | ||
2398 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); | |
2399 | ocp_data |= LINK_OFF_WAKE_EN; | |
2400 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); | |
2401 | ||
2402 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
2403 | } else { | |
2404 | __rtl_set_wol(tp, tp->saved_wolopts); | |
b214396f | 2405 | r8153_u2p3en(tp, true); |
2406 | r8153_u1u2en(tp, true); | |
9a4be1bd | 2407 | } |
2408 | } | |
2409 | ||
aa66a5f1 | 2410 | static void rtl_phy_reset(struct r8152 *tp) |
2411 | { | |
2412 | u16 data; | |
2413 | int i; | |
2414 | ||
2415 | clear_bit(PHY_RESET, &tp->flags); | |
2416 | ||
2417 | data = r8152_mdio_read(tp, MII_BMCR); | |
2418 | ||
2419 | /* don't reset again before the previous one complete */ | |
2420 | if (data & BMCR_RESET) | |
2421 | return; | |
2422 | ||
2423 | data |= BMCR_RESET; | |
2424 | r8152_mdio_write(tp, MII_BMCR, data); | |
2425 | ||
2426 | for (i = 0; i < 50; i++) { | |
2427 | msleep(20); | |
2428 | if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) | |
2429 | break; | |
2430 | } | |
2431 | } | |
2432 | ||
4349968a | 2433 | static void r8153_teredo_off(struct r8152 *tp) |
2434 | { | |
2435 | u32 ocp_data; | |
2436 | ||
2437 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); | |
2438 | ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN); | |
2439 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); | |
2440 | ||
2441 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE); | |
2442 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0); | |
2443 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0); | |
2444 | } | |
2445 | ||
2446 | static void r8152b_disable_aldps(struct r8152 *tp) | |
2447 | { | |
2448 | ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE); | |
2449 | msleep(20); | |
2450 | } | |
2451 | ||
2452 | static inline void r8152b_enable_aldps(struct r8152 *tp) | |
2453 | { | |
2454 | ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS | | |
2455 | LINKENA | DIS_SDSAVE); | |
2456 | } | |
2457 | ||
d70b1137 | 2458 | static void rtl8152_disable(struct r8152 *tp) |
2459 | { | |
2460 | r8152b_disable_aldps(tp); | |
2461 | rtl_disable(tp); | |
2462 | r8152b_enable_aldps(tp); | |
2463 | } | |
2464 | ||
4349968a | 2465 | static void r8152b_hw_phy_cfg(struct r8152 *tp) |
2466 | { | |
f0cbe0ac | 2467 | u16 data; |
2468 | ||
2469 | data = r8152_mdio_read(tp, MII_BMCR); | |
2470 | if (data & BMCR_PDOWN) { | |
2471 | data &= ~BMCR_PDOWN; | |
2472 | r8152_mdio_write(tp, MII_BMCR, data); | |
2473 | } | |
2474 | ||
aa66a5f1 | 2475 | set_bit(PHY_RESET, &tp->flags); |
4349968a | 2476 | } |
2477 | ||
ac718b69 | 2478 | static void r8152b_exit_oob(struct r8152 *tp) |
2479 | { | |
db8515ef | 2480 | u32 ocp_data; |
2481 | int i; | |
ac718b69 | 2482 | |
2483 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2484 | ocp_data &= ~RCR_ACPT_ALL; | |
2485 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2486 | ||
00a5e360 | 2487 | rxdy_gated_en(tp, true); |
da9bd117 | 2488 | r8153_teredo_off(tp); |
7e9da481 | 2489 | r8152b_hw_phy_cfg(tp); |
ac718b69 | 2490 | |
2491 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
2492 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); | |
2493 | ||
2494 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2495 | ocp_data &= ~NOW_IS_OOB; | |
2496 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2497 | ||
2498 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2499 | ocp_data &= ~MCU_BORW_EN; | |
2500 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2501 | ||
2502 | for (i = 0; i < 1000; i++) { | |
2503 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2504 | if (ocp_data & LINK_LIST_READY) | |
2505 | break; | |
8ddfa077 | 2506 | usleep_range(1000, 2000); |
ac718b69 | 2507 | } |
2508 | ||
2509 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2510 | ocp_data |= RE_INIT_LL; | |
2511 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2512 | ||
2513 | for (i = 0; i < 1000; i++) { | |
2514 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2515 | if (ocp_data & LINK_LIST_READY) | |
2516 | break; | |
8ddfa077 | 2517 | usleep_range(1000, 2000); |
ac718b69 | 2518 | } |
2519 | ||
2520 | rtl8152_nic_reset(tp); | |
2521 | ||
2522 | /* rx share fifo credit full threshold */ | |
2523 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); | |
2524 | ||
a3cc465d | 2525 | if (tp->udev->speed == USB_SPEED_FULL || |
2526 | tp->udev->speed == USB_SPEED_LOW) { | |
ac718b69 | 2527 | /* rx share fifo credit near full threshold */ |
2528 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, | |
2529 | RXFIFO_THR2_FULL); | |
2530 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, | |
2531 | RXFIFO_THR3_FULL); | |
2532 | } else { | |
2533 | /* rx share fifo credit near full threshold */ | |
2534 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, | |
2535 | RXFIFO_THR2_HIGH); | |
2536 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, | |
2537 | RXFIFO_THR3_HIGH); | |
2538 | } | |
2539 | ||
2540 | /* TX share fifo free credit full threshold */ | |
2541 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL); | |
2542 | ||
2543 | ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD); | |
8e1f51bd | 2544 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH); |
ac718b69 | 2545 | ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA, |
2546 | TEST_MODE_DISABLE | TX_SIZE_ADJUST1); | |
2547 | ||
c5554298 | 2548 | rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); |
ac718b69 | 2549 | |
2550 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); | |
2551 | ||
2552 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); | |
2553 | ocp_data |= TCR0_AUTO_FIFO; | |
2554 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); | |
2555 | } | |
2556 | ||
2557 | static void r8152b_enter_oob(struct r8152 *tp) | |
2558 | { | |
45f4a19f | 2559 | u32 ocp_data; |
2560 | int i; | |
ac718b69 | 2561 | |
2562 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2563 | ocp_data &= ~NOW_IS_OOB; | |
2564 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2565 | ||
2566 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); | |
2567 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); | |
2568 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB); | |
2569 | ||
d70b1137 | 2570 | rtl_disable(tp); |
ac718b69 | 2571 | |
2572 | for (i = 0; i < 1000; i++) { | |
2573 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2574 | if (ocp_data & LINK_LIST_READY) | |
2575 | break; | |
8ddfa077 | 2576 | usleep_range(1000, 2000); |
ac718b69 | 2577 | } |
2578 | ||
2579 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2580 | ocp_data |= RE_INIT_LL; | |
2581 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2582 | ||
2583 | for (i = 0; i < 1000; i++) { | |
2584 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2585 | if (ocp_data & LINK_LIST_READY) | |
2586 | break; | |
8ddfa077 | 2587 | usleep_range(1000, 2000); |
ac718b69 | 2588 | } |
2589 | ||
2590 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); | |
2591 | ||
c5554298 | 2592 | rtl_rx_vlan_en(tp, true); |
ac718b69 | 2593 | |
2594 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); | |
2595 | ocp_data |= ALDPS_PROXY_MODE; | |
2596 | ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); | |
2597 | ||
2598 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2599 | ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; | |
2600 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2601 | ||
00a5e360 | 2602 | rxdy_gated_en(tp, false); |
ac718b69 | 2603 | |
2604 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2605 | ocp_data |= RCR_APM | RCR_AM | RCR_AB; | |
2606 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2607 | } | |
2608 | ||
43779f8d | 2609 | static void r8153_hw_phy_cfg(struct r8152 *tp) |
2610 | { | |
2611 | u32 ocp_data; | |
2612 | u16 data; | |
2613 | ||
2614 | ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L); | |
f0cbe0ac | 2615 | data = r8152_mdio_read(tp, MII_BMCR); |
2616 | if (data & BMCR_PDOWN) { | |
2617 | data &= ~BMCR_PDOWN; | |
2618 | r8152_mdio_write(tp, MII_BMCR, data); | |
2619 | } | |
43779f8d | 2620 | |
2621 | if (tp->version == RTL_VER_03) { | |
2622 | data = ocp_reg_read(tp, OCP_EEE_CFG); | |
2623 | data &= ~CTAP_SHORT_EN; | |
2624 | ocp_reg_write(tp, OCP_EEE_CFG, data); | |
2625 | } | |
2626 | ||
2627 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
2628 | data |= EEE_CLKDIV_EN; | |
2629 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
2630 | ||
2631 | data = ocp_reg_read(tp, OCP_DOWN_SPEED); | |
2632 | data |= EN_10M_BGOFF; | |
2633 | ocp_reg_write(tp, OCP_DOWN_SPEED, data); | |
2634 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
2635 | data |= EN_10M_PLLOFF; | |
2636 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
b4d99def | 2637 | sram_write(tp, SRAM_IMPEDANCE, 0x0b13); |
43779f8d | 2638 | |
2639 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); | |
2640 | ocp_data |= PFM_PWM_SWITCH; | |
2641 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); | |
2642 | ||
b4d99def | 2643 | /* Enable LPF corner auto tune */ |
2644 | sram_write(tp, SRAM_LPF_CFG, 0xf70f); | |
43779f8d | 2645 | |
b4d99def | 2646 | /* Adjust 10M Amplitude */ |
2647 | sram_write(tp, SRAM_10M_AMP1, 0x00af); | |
2648 | sram_write(tp, SRAM_10M_AMP2, 0x0208); | |
aa66a5f1 | 2649 | |
2650 | set_bit(PHY_RESET, &tp->flags); | |
43779f8d | 2651 | } |
2652 | ||
43779f8d | 2653 | static void r8153_first_init(struct r8152 *tp) |
2654 | { | |
2655 | u32 ocp_data; | |
2656 | int i; | |
2657 | ||
00a5e360 | 2658 | rxdy_gated_en(tp, true); |
43779f8d | 2659 | r8153_teredo_off(tp); |
2660 | ||
2661 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2662 | ocp_data &= ~RCR_ACPT_ALL; | |
2663 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2664 | ||
2665 | r8153_hw_phy_cfg(tp); | |
2666 | ||
2667 | rtl8152_nic_reset(tp); | |
2668 | ||
2669 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2670 | ocp_data &= ~NOW_IS_OOB; | |
2671 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2672 | ||
2673 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2674 | ocp_data &= ~MCU_BORW_EN; | |
2675 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2676 | ||
2677 | for (i = 0; i < 1000; i++) { | |
2678 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2679 | if (ocp_data & LINK_LIST_READY) | |
2680 | break; | |
8ddfa077 | 2681 | usleep_range(1000, 2000); |
43779f8d | 2682 | } |
2683 | ||
2684 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2685 | ocp_data |= RE_INIT_LL; | |
2686 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2687 | ||
2688 | for (i = 0; i < 1000; i++) { | |
2689 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2690 | if (ocp_data & LINK_LIST_READY) | |
2691 | break; | |
8ddfa077 | 2692 | usleep_range(1000, 2000); |
43779f8d | 2693 | } |
2694 | ||
c5554298 | 2695 | rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); |
43779f8d | 2696 | |
69b4b7a4 | 2697 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS); |
2698 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO); | |
43779f8d | 2699 | |
2700 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); | |
2701 | ocp_data |= TCR0_AUTO_FIFO; | |
2702 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); | |
2703 | ||
2704 | rtl8152_nic_reset(tp); | |
2705 | ||
2706 | /* rx share fifo credit full threshold */ | |
2707 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); | |
2708 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL); | |
2709 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL); | |
2710 | /* TX share fifo free credit full threshold */ | |
2711 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2); | |
2712 | ||
9629e3c0 | 2713 | /* rx aggregation */ |
43779f8d | 2714 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); |
2715 | ocp_data &= ~RX_AGG_DISABLE; | |
2716 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); | |
2717 | } | |
2718 | ||
2719 | static void r8153_enter_oob(struct r8152 *tp) | |
2720 | { | |
2721 | u32 ocp_data; | |
2722 | int i; | |
2723 | ||
2724 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2725 | ocp_data &= ~NOW_IS_OOB; | |
2726 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2727 | ||
d70b1137 | 2728 | rtl_disable(tp); |
43779f8d | 2729 | |
2730 | for (i = 0; i < 1000; i++) { | |
2731 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2732 | if (ocp_data & LINK_LIST_READY) | |
2733 | break; | |
8ddfa077 | 2734 | usleep_range(1000, 2000); |
43779f8d | 2735 | } |
2736 | ||
2737 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2738 | ocp_data |= RE_INIT_LL; | |
2739 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2740 | ||
2741 | for (i = 0; i < 1000; i++) { | |
2742 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2743 | if (ocp_data & LINK_LIST_READY) | |
2744 | break; | |
8ddfa077 | 2745 | usleep_range(1000, 2000); |
43779f8d | 2746 | } |
2747 | ||
69b4b7a4 | 2748 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS); |
43779f8d | 2749 | |
43779f8d | 2750 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); |
2751 | ocp_data &= ~TEREDO_WAKE_MASK; | |
2752 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); | |
2753 | ||
c5554298 | 2754 | rtl_rx_vlan_en(tp, true); |
43779f8d | 2755 | |
2756 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); | |
2757 | ocp_data |= ALDPS_PROXY_MODE; | |
2758 | ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); | |
2759 | ||
2760 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2761 | ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; | |
2762 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2763 | ||
00a5e360 | 2764 | rxdy_gated_en(tp, false); |
43779f8d | 2765 | |
2766 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2767 | ocp_data |= RCR_APM | RCR_AM | RCR_AB; | |
2768 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2769 | } | |
2770 | ||
2771 | static void r8153_disable_aldps(struct r8152 *tp) | |
2772 | { | |
2773 | u16 data; | |
2774 | ||
2775 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
2776 | data &= ~EN_ALDPS; | |
2777 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
2778 | msleep(20); | |
2779 | } | |
2780 | ||
2781 | static void r8153_enable_aldps(struct r8152 *tp) | |
2782 | { | |
2783 | u16 data; | |
2784 | ||
2785 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
2786 | data |= EN_ALDPS; | |
2787 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
2788 | } | |
2789 | ||
d70b1137 | 2790 | static void rtl8153_disable(struct r8152 *tp) |
2791 | { | |
2792 | r8153_disable_aldps(tp); | |
2793 | rtl_disable(tp); | |
2794 | r8153_enable_aldps(tp); | |
b214396f | 2795 | usb_enable_lpm(tp->udev); |
d70b1137 | 2796 | } |
2797 | ||
ac718b69 | 2798 | static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex) |
2799 | { | |
43779f8d | 2800 | u16 bmcr, anar, gbcr; |
ac718b69 | 2801 | int ret = 0; |
2802 | ||
2803 | cancel_delayed_work_sync(&tp->schedule); | |
2804 | anar = r8152_mdio_read(tp, MII_ADVERTISE); | |
2805 | anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | | |
2806 | ADVERTISE_100HALF | ADVERTISE_100FULL); | |
43779f8d | 2807 | if (tp->mii.supports_gmii) { |
2808 | gbcr = r8152_mdio_read(tp, MII_CTRL1000); | |
2809 | gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); | |
2810 | } else { | |
2811 | gbcr = 0; | |
2812 | } | |
ac718b69 | 2813 | |
2814 | if (autoneg == AUTONEG_DISABLE) { | |
2815 | if (speed == SPEED_10) { | |
2816 | bmcr = 0; | |
2817 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
2818 | } else if (speed == SPEED_100) { | |
2819 | bmcr = BMCR_SPEED100; | |
2820 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; | |
43779f8d | 2821 | } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { |
2822 | bmcr = BMCR_SPEED1000; | |
2823 | gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; | |
ac718b69 | 2824 | } else { |
2825 | ret = -EINVAL; | |
2826 | goto out; | |
2827 | } | |
2828 | ||
2829 | if (duplex == DUPLEX_FULL) | |
2830 | bmcr |= BMCR_FULLDPLX; | |
2831 | } else { | |
2832 | if (speed == SPEED_10) { | |
2833 | if (duplex == DUPLEX_FULL) | |
2834 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
2835 | else | |
2836 | anar |= ADVERTISE_10HALF; | |
2837 | } else if (speed == SPEED_100) { | |
2838 | if (duplex == DUPLEX_FULL) { | |
2839 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
2840 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; | |
2841 | } else { | |
2842 | anar |= ADVERTISE_10HALF; | |
2843 | anar |= ADVERTISE_100HALF; | |
2844 | } | |
43779f8d | 2845 | } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { |
2846 | if (duplex == DUPLEX_FULL) { | |
2847 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
2848 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; | |
2849 | gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; | |
2850 | } else { | |
2851 | anar |= ADVERTISE_10HALF; | |
2852 | anar |= ADVERTISE_100HALF; | |
2853 | gbcr |= ADVERTISE_1000HALF; | |
2854 | } | |
ac718b69 | 2855 | } else { |
2856 | ret = -EINVAL; | |
2857 | goto out; | |
2858 | } | |
2859 | ||
2860 | bmcr = BMCR_ANENABLE | BMCR_ANRESTART; | |
2861 | } | |
2862 | ||
aa66a5f1 | 2863 | if (test_bit(PHY_RESET, &tp->flags)) |
2864 | bmcr |= BMCR_RESET; | |
2865 | ||
43779f8d | 2866 | if (tp->mii.supports_gmii) |
2867 | r8152_mdio_write(tp, MII_CTRL1000, gbcr); | |
2868 | ||
ac718b69 | 2869 | r8152_mdio_write(tp, MII_ADVERTISE, anar); |
2870 | r8152_mdio_write(tp, MII_BMCR, bmcr); | |
2871 | ||
aa66a5f1 | 2872 | if (test_bit(PHY_RESET, &tp->flags)) { |
2873 | int i; | |
2874 | ||
2875 | clear_bit(PHY_RESET, &tp->flags); | |
2876 | for (i = 0; i < 50; i++) { | |
2877 | msleep(20); | |
2878 | if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) | |
2879 | break; | |
2880 | } | |
2881 | } | |
2882 | ||
ac718b69 | 2883 | out: |
ac718b69 | 2884 | |
2885 | return ret; | |
2886 | } | |
2887 | ||
d70b1137 | 2888 | static void rtl8152_up(struct r8152 *tp) |
2889 | { | |
2890 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
2891 | return; | |
2892 | ||
2893 | r8152b_disable_aldps(tp); | |
2894 | r8152b_exit_oob(tp); | |
2895 | r8152b_enable_aldps(tp); | |
2896 | } | |
2897 | ||
ac718b69 | 2898 | static void rtl8152_down(struct r8152 *tp) |
2899 | { | |
6871438c | 2900 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) { |
2901 | rtl_drop_queued_tx(tp); | |
2902 | return; | |
2903 | } | |
2904 | ||
00a5e360 | 2905 | r8152_power_cut_en(tp, false); |
ac718b69 | 2906 | r8152b_disable_aldps(tp); |
2907 | r8152b_enter_oob(tp); | |
2908 | r8152b_enable_aldps(tp); | |
2909 | } | |
2910 | ||
d70b1137 | 2911 | static void rtl8153_up(struct r8152 *tp) |
2912 | { | |
2913 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
2914 | return; | |
2915 | ||
b214396f | 2916 | r8153_u1u2en(tp, false); |
d70b1137 | 2917 | r8153_disable_aldps(tp); |
2918 | r8153_first_init(tp); | |
2919 | r8153_enable_aldps(tp); | |
b214396f | 2920 | r8153_u2p3en(tp, true); |
2921 | r8153_u1u2en(tp, true); | |
2922 | usb_enable_lpm(tp->udev); | |
d70b1137 | 2923 | } |
2924 | ||
43779f8d | 2925 | static void rtl8153_down(struct r8152 *tp) |
2926 | { | |
6871438c | 2927 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) { |
2928 | rtl_drop_queued_tx(tp); | |
2929 | return; | |
2930 | } | |
2931 | ||
b9702723 | 2932 | r8153_u1u2en(tp, false); |
b214396f | 2933 | r8153_u2p3en(tp, false); |
b9702723 | 2934 | r8153_power_cut_en(tp, false); |
43779f8d | 2935 | r8153_disable_aldps(tp); |
2936 | r8153_enter_oob(tp); | |
2937 | r8153_enable_aldps(tp); | |
2938 | } | |
2939 | ||
ac718b69 | 2940 | static void set_carrier(struct r8152 *tp) |
2941 | { | |
2942 | struct net_device *netdev = tp->netdev; | |
2943 | u8 speed; | |
2944 | ||
40a82917 | 2945 | clear_bit(RTL8152_LINK_CHG, &tp->flags); |
ac718b69 | 2946 | speed = rtl8152_get_speed(tp); |
2947 | ||
2948 | if (speed & LINK_STATUS) { | |
51d979fa | 2949 | if (!netif_carrier_ok(netdev)) { |
c81229c9 | 2950 | tp->rtl_ops.enable(tp); |
ac718b69 | 2951 | set_bit(RTL8152_SET_RX_MODE, &tp->flags); |
41cec84c | 2952 | napi_disable(&tp->napi); |
ac718b69 | 2953 | netif_carrier_on(netdev); |
aa2e0926 | 2954 | rtl_start_rx(tp); |
41cec84c | 2955 | napi_enable(&tp->napi); |
ac718b69 | 2956 | } |
2957 | } else { | |
51d979fa | 2958 | if (netif_carrier_ok(netdev)) { |
ac718b69 | 2959 | netif_carrier_off(netdev); |
d823ab68 | 2960 | napi_disable(&tp->napi); |
c81229c9 | 2961 | tp->rtl_ops.disable(tp); |
d823ab68 | 2962 | napi_enable(&tp->napi); |
ac718b69 | 2963 | } |
2964 | } | |
ac718b69 | 2965 | } |
2966 | ||
2967 | static void rtl_work_func_t(struct work_struct *work) | |
2968 | { | |
2969 | struct r8152 *tp = container_of(work, struct r8152, schedule.work); | |
2970 | ||
a1f83fee | 2971 | /* If the device is unplugged or !netif_running(), the workqueue |
2972 | * doesn't need to wake the device, and could return directly. | |
2973 | */ | |
2974 | if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev)) | |
2975 | return; | |
2976 | ||
9a4be1bd | 2977 | if (usb_autopm_get_interface(tp->intf) < 0) |
2978 | return; | |
2979 | ||
ac718b69 | 2980 | if (!test_bit(WORK_ENABLE, &tp->flags)) |
2981 | goto out1; | |
2982 | ||
b5403273 | 2983 | if (!mutex_trylock(&tp->control)) { |
2984 | schedule_delayed_work(&tp->schedule, 0); | |
2985 | goto out1; | |
2986 | } | |
2987 | ||
40a82917 | 2988 | if (test_bit(RTL8152_LINK_CHG, &tp->flags)) |
2989 | set_carrier(tp); | |
ac718b69 | 2990 | |
2991 | if (test_bit(RTL8152_SET_RX_MODE, &tp->flags)) | |
2992 | _rtl8152_set_rx_mode(tp->netdev); | |
2993 | ||
d823ab68 | 2994 | /* don't schedule napi before linking */ |
2995 | if (test_bit(SCHEDULE_NAPI, &tp->flags) && | |
51d979fa | 2996 | netif_carrier_ok(tp->netdev)) { |
d823ab68 | 2997 | clear_bit(SCHEDULE_NAPI, &tp->flags); |
2998 | napi_schedule(&tp->napi); | |
0c3121fc | 2999 | } |
aa66a5f1 | 3000 | |
3001 | if (test_bit(PHY_RESET, &tp->flags)) | |
3002 | rtl_phy_reset(tp); | |
3003 | ||
b5403273 | 3004 | mutex_unlock(&tp->control); |
3005 | ||
ac718b69 | 3006 | out1: |
9a4be1bd | 3007 | usb_autopm_put_interface(tp->intf); |
ac718b69 | 3008 | } |
3009 | ||
3010 | static int rtl8152_open(struct net_device *netdev) | |
3011 | { | |
3012 | struct r8152 *tp = netdev_priv(netdev); | |
3013 | int res = 0; | |
3014 | ||
7e9da481 | 3015 | res = alloc_all_mem(tp); |
3016 | if (res) | |
3017 | goto out; | |
3018 | ||
51d979fa | 3019 | netif_carrier_off(netdev); |
f4c7476b | 3020 | |
9a4be1bd | 3021 | res = usb_autopm_get_interface(tp->intf); |
3022 | if (res < 0) { | |
3023 | free_all_mem(tp); | |
3024 | goto out; | |
3025 | } | |
3026 | ||
b5403273 | 3027 | mutex_lock(&tp->control); |
3028 | ||
9a4be1bd | 3029 | /* The WORK_ENABLE may be set when autoresume occurs */ |
3030 | if (test_bit(WORK_ENABLE, &tp->flags)) { | |
3031 | clear_bit(WORK_ENABLE, &tp->flags); | |
3032 | usb_kill_urb(tp->intr_urb); | |
3033 | cancel_delayed_work_sync(&tp->schedule); | |
f4c7476b | 3034 | |
3035 | /* disable the tx/rx, if the workqueue has enabled them. */ | |
51d979fa | 3036 | if (netif_carrier_ok(netdev)) |
9a4be1bd | 3037 | tp->rtl_ops.disable(tp); |
3038 | } | |
3039 | ||
7e9da481 | 3040 | tp->rtl_ops.up(tp); |
3041 | ||
3d55f44f | 3042 | rtl8152_set_speed(tp, AUTONEG_ENABLE, |
3043 | tp->mii.supports_gmii ? SPEED_1000 : SPEED_100, | |
3044 | DUPLEX_FULL); | |
3d55f44f | 3045 | netif_carrier_off(netdev); |
3046 | netif_start_queue(netdev); | |
3047 | set_bit(WORK_ENABLE, &tp->flags); | |
db8515ef | 3048 | |
40a82917 | 3049 | res = usb_submit_urb(tp->intr_urb, GFP_KERNEL); |
3050 | if (res) { | |
3051 | if (res == -ENODEV) | |
3052 | netif_device_detach(tp->netdev); | |
4a8deae2 HW |
3053 | netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n", |
3054 | res); | |
7e9da481 | 3055 | free_all_mem(tp); |
93ffbeab | 3056 | } else { |
d823ab68 | 3057 | napi_enable(&tp->napi); |
ac718b69 | 3058 | } |
3059 | ||
b5403273 | 3060 | mutex_unlock(&tp->control); |
3061 | ||
9a4be1bd | 3062 | usb_autopm_put_interface(tp->intf); |
ac718b69 | 3063 | |
7e9da481 | 3064 | out: |
ac718b69 | 3065 | return res; |
3066 | } | |
3067 | ||
3068 | static int rtl8152_close(struct net_device *netdev) | |
3069 | { | |
3070 | struct r8152 *tp = netdev_priv(netdev); | |
3071 | int res = 0; | |
3072 | ||
d823ab68 | 3073 | napi_disable(&tp->napi); |
ac718b69 | 3074 | clear_bit(WORK_ENABLE, &tp->flags); |
3d55f44f | 3075 | usb_kill_urb(tp->intr_urb); |
ac718b69 | 3076 | cancel_delayed_work_sync(&tp->schedule); |
3077 | netif_stop_queue(netdev); | |
9a4be1bd | 3078 | |
3079 | res = usb_autopm_get_interface(tp->intf); | |
53543db5 | 3080 | if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) { |
9a4be1bd | 3081 | rtl_drop_queued_tx(tp); |
d823ab68 | 3082 | rtl_stop_rx(tp); |
9a4be1bd | 3083 | } else { |
b5403273 | 3084 | mutex_lock(&tp->control); |
3085 | ||
b209af99 | 3086 | /* The autosuspend may have been enabled and wouldn't |
9a4be1bd | 3087 | * be disable when autoresume occurs, because the |
3088 | * netif_running() would be false. | |
3089 | */ | |
923e1ee3 | 3090 | rtl_runtime_suspend_enable(tp, false); |
9a4be1bd | 3091 | |
9a4be1bd | 3092 | tp->rtl_ops.down(tp); |
b5403273 | 3093 | |
3094 | mutex_unlock(&tp->control); | |
3095 | ||
9a4be1bd | 3096 | usb_autopm_put_interface(tp->intf); |
3097 | } | |
ac718b69 | 3098 | |
7e9da481 | 3099 | free_all_mem(tp); |
3100 | ||
ac718b69 | 3101 | return res; |
3102 | } | |
3103 | ||
d24f6134 | 3104 | static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg) |
3105 | { | |
3106 | ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev); | |
3107 | ocp_reg_write(tp, OCP_EEE_DATA, reg); | |
3108 | ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev); | |
3109 | } | |
3110 | ||
3111 | static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg) | |
3112 | { | |
3113 | u16 data; | |
3114 | ||
3115 | r8152_mmd_indirect(tp, dev, reg); | |
3116 | data = ocp_reg_read(tp, OCP_EEE_DATA); | |
3117 | ocp_reg_write(tp, OCP_EEE_AR, 0x0000); | |
3118 | ||
3119 | return data; | |
3120 | } | |
3121 | ||
3122 | static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data) | |
ac718b69 | 3123 | { |
d24f6134 | 3124 | r8152_mmd_indirect(tp, dev, reg); |
3125 | ocp_reg_write(tp, OCP_EEE_DATA, data); | |
3126 | ocp_reg_write(tp, OCP_EEE_AR, 0x0000); | |
3127 | } | |
3128 | ||
3129 | static void r8152_eee_en(struct r8152 *tp, bool enable) | |
3130 | { | |
3131 | u16 config1, config2, config3; | |
45f4a19f | 3132 | u32 ocp_data; |
ac718b69 | 3133 | |
3134 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); | |
d24f6134 | 3135 | config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask; |
3136 | config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2); | |
3137 | config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask; | |
3138 | ||
3139 | if (enable) { | |
3140 | ocp_data |= EEE_RX_EN | EEE_TX_EN; | |
3141 | config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN; | |
3142 | config1 |= sd_rise_time(1); | |
3143 | config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN; | |
3144 | config3 |= fast_snr(42); | |
3145 | } else { | |
3146 | ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); | |
3147 | config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | | |
3148 | RX_QUIET_EN); | |
3149 | config1 |= sd_rise_time(7); | |
3150 | config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN); | |
3151 | config3 |= fast_snr(511); | |
3152 | } | |
3153 | ||
ac718b69 | 3154 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); |
d24f6134 | 3155 | ocp_reg_write(tp, OCP_EEE_CONFIG1, config1); |
3156 | ocp_reg_write(tp, OCP_EEE_CONFIG2, config2); | |
3157 | ocp_reg_write(tp, OCP_EEE_CONFIG3, config3); | |
ac718b69 | 3158 | } |
3159 | ||
d24f6134 | 3160 | static void r8152b_enable_eee(struct r8152 *tp) |
3161 | { | |
3162 | r8152_eee_en(tp, true); | |
3163 | r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX); | |
3164 | } | |
3165 | ||
3166 | static void r8153_eee_en(struct r8152 *tp, bool enable) | |
43779f8d | 3167 | { |
3168 | u32 ocp_data; | |
d24f6134 | 3169 | u16 config; |
43779f8d | 3170 | |
3171 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); | |
d24f6134 | 3172 | config = ocp_reg_read(tp, OCP_EEE_CFG); |
3173 | ||
3174 | if (enable) { | |
3175 | ocp_data |= EEE_RX_EN | EEE_TX_EN; | |
3176 | config |= EEE10_EN; | |
3177 | } else { | |
3178 | ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); | |
3179 | config &= ~EEE10_EN; | |
3180 | } | |
3181 | ||
43779f8d | 3182 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); |
d24f6134 | 3183 | ocp_reg_write(tp, OCP_EEE_CFG, config); |
3184 | } | |
3185 | ||
3186 | static void r8153_enable_eee(struct r8152 *tp) | |
3187 | { | |
3188 | r8153_eee_en(tp, true); | |
3189 | ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX); | |
43779f8d | 3190 | } |
3191 | ||
ac718b69 | 3192 | static void r8152b_enable_fc(struct r8152 *tp) |
3193 | { | |
3194 | u16 anar; | |
3195 | ||
3196 | anar = r8152_mdio_read(tp, MII_ADVERTISE); | |
3197 | anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; | |
3198 | r8152_mdio_write(tp, MII_ADVERTISE, anar); | |
3199 | } | |
3200 | ||
4f1d4d54 | 3201 | static void rtl_tally_reset(struct r8152 *tp) |
3202 | { | |
3203 | u32 ocp_data; | |
3204 | ||
3205 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY); | |
3206 | ocp_data |= TALLY_RESET; | |
3207 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data); | |
3208 | } | |
3209 | ||
ac718b69 | 3210 | static void r8152b_init(struct r8152 *tp) |
3211 | { | |
ebc2ec48 | 3212 | u32 ocp_data; |
ac718b69 | 3213 | |
6871438c | 3214 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
3215 | return; | |
3216 | ||
d70b1137 | 3217 | r8152b_disable_aldps(tp); |
3218 | ||
ac718b69 | 3219 | if (tp->version == RTL_VER_01) { |
3220 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); | |
3221 | ocp_data &= ~LED_MODE_MASK; | |
3222 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); | |
3223 | } | |
3224 | ||
00a5e360 | 3225 | r8152_power_cut_en(tp, false); |
ac718b69 | 3226 | |
ac718b69 | 3227 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); |
3228 | ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH; | |
3229 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); | |
3230 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL); | |
3231 | ocp_data &= ~MCU_CLK_RATIO_MASK; | |
3232 | ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN; | |
3233 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data); | |
3234 | ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK | | |
3235 | SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK; | |
3236 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data); | |
3237 | ||
3238 | r8152b_enable_eee(tp); | |
3239 | r8152b_enable_aldps(tp); | |
3240 | r8152b_enable_fc(tp); | |
4f1d4d54 | 3241 | rtl_tally_reset(tp); |
ac718b69 | 3242 | |
ebc2ec48 | 3243 | /* enable rx aggregation */ |
ac718b69 | 3244 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); |
ebc2ec48 | 3245 | ocp_data &= ~RX_AGG_DISABLE; |
ac718b69 | 3246 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); |
3247 | } | |
3248 | ||
43779f8d | 3249 | static void r8153_init(struct r8152 *tp) |
3250 | { | |
3251 | u32 ocp_data; | |
3252 | int i; | |
3253 | ||
6871438c | 3254 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
3255 | return; | |
3256 | ||
d70b1137 | 3257 | r8153_disable_aldps(tp); |
b9702723 | 3258 | r8153_u1u2en(tp, false); |
43779f8d | 3259 | |
3260 | for (i = 0; i < 500; i++) { | |
3261 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & | |
3262 | AUTOLOAD_DONE) | |
3263 | break; | |
3264 | msleep(20); | |
3265 | } | |
3266 | ||
3267 | for (i = 0; i < 500; i++) { | |
3268 | ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK; | |
3269 | if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN) | |
3270 | break; | |
3271 | msleep(20); | |
3272 | } | |
3273 | ||
b214396f | 3274 | usb_disable_lpm(tp->udev); |
b9702723 | 3275 | r8153_u2p3en(tp, false); |
43779f8d | 3276 | |
65bab84c | 3277 | if (tp->version == RTL_VER_04) { |
3278 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2); | |
3279 | ocp_data &= ~pwd_dn_scale_mask; | |
3280 | ocp_data |= pwd_dn_scale(96); | |
3281 | ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data); | |
3282 | ||
3283 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY); | |
3284 | ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND; | |
3285 | ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data); | |
3286 | } else if (tp->version == RTL_VER_05) { | |
3287 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0); | |
3288 | ocp_data &= ~ECM_ALDPS; | |
3289 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data); | |
3290 | ||
3291 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); | |
3292 | if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) | |
3293 | ocp_data &= ~DYNAMIC_BURST; | |
3294 | else | |
3295 | ocp_data |= DYNAMIC_BURST; | |
3296 | ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); | |
3297 | } | |
3298 | ||
3299 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2); | |
3300 | ocp_data |= EP4_FULL_FC; | |
3301 | ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data); | |
3302 | ||
43779f8d | 3303 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL); |
3304 | ocp_data &= ~TIMER11_EN; | |
3305 | ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data); | |
3306 | ||
43779f8d | 3307 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); |
3308 | ocp_data &= ~LED_MODE_MASK; | |
3309 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); | |
3310 | ||
65bab84c | 3311 | ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM; |
34203e25 | 3312 | if (tp->version == RTL_VER_04 && tp->udev->speed != USB_SPEED_SUPER) |
43779f8d | 3313 | ocp_data |= LPM_TIMER_500MS; |
34203e25 | 3314 | else |
3315 | ocp_data |= LPM_TIMER_500US; | |
43779f8d | 3316 | ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data); |
3317 | ||
3318 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2); | |
3319 | ocp_data &= ~SEN_VAL_MASK; | |
3320 | ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE; | |
3321 | ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data); | |
3322 | ||
65bab84c | 3323 | ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001); |
3324 | ||
b9702723 | 3325 | r8153_power_cut_en(tp, false); |
3326 | r8153_u1u2en(tp, true); | |
43779f8d | 3327 | |
43779f8d | 3328 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO); |
3329 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO); | |
3330 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, | |
3331 | PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN | | |
3332 | U1U2_SPDWN_EN | L1_SPDWN_EN); | |
3333 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, | |
3334 | PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN | | |
3335 | TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN | | |
3336 | EEE_SPDWN_EN); | |
3337 | ||
3338 | r8153_enable_eee(tp); | |
3339 | r8153_enable_aldps(tp); | |
3340 | r8152b_enable_fc(tp); | |
4f1d4d54 | 3341 | rtl_tally_reset(tp); |
b214396f | 3342 | r8153_u2p3en(tp, true); |
43779f8d | 3343 | } |
3344 | ||
ac718b69 | 3345 | static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message) |
3346 | { | |
3347 | struct r8152 *tp = usb_get_intfdata(intf); | |
6cc69f2a | 3348 | struct net_device *netdev = tp->netdev; |
3349 | int ret = 0; | |
ac718b69 | 3350 | |
b5403273 | 3351 | mutex_lock(&tp->control); |
3352 | ||
6cc69f2a | 3353 | if (PMSG_IS_AUTO(message)) { |
3354 | if (netif_running(netdev) && work_busy(&tp->schedule.work)) { | |
3355 | ret = -EBUSY; | |
3356 | goto out1; | |
3357 | } | |
3358 | ||
9a4be1bd | 3359 | set_bit(SELECTIVE_SUSPEND, &tp->flags); |
6cc69f2a | 3360 | } else { |
3361 | netif_device_detach(netdev); | |
3362 | } | |
ac718b69 | 3363 | |
e3bd1a81 | 3364 | if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) { |
ac718b69 | 3365 | clear_bit(WORK_ENABLE, &tp->flags); |
40a82917 | 3366 | usb_kill_urb(tp->intr_urb); |
d823ab68 | 3367 | napi_disable(&tp->napi); |
9a4be1bd | 3368 | if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { |
445f7f4d | 3369 | rtl_stop_rx(tp); |
9a4be1bd | 3370 | rtl_runtime_suspend_enable(tp, true); |
3371 | } else { | |
6cc69f2a | 3372 | cancel_delayed_work_sync(&tp->schedule); |
9a4be1bd | 3373 | tp->rtl_ops.down(tp); |
9a4be1bd | 3374 | } |
d823ab68 | 3375 | napi_enable(&tp->napi); |
ac718b69 | 3376 | } |
6cc69f2a | 3377 | out1: |
b5403273 | 3378 | mutex_unlock(&tp->control); |
3379 | ||
6cc69f2a | 3380 | return ret; |
ac718b69 | 3381 | } |
3382 | ||
3383 | static int rtl8152_resume(struct usb_interface *intf) | |
3384 | { | |
3385 | struct r8152 *tp = usb_get_intfdata(intf); | |
3386 | ||
b5403273 | 3387 | mutex_lock(&tp->control); |
3388 | ||
9a4be1bd | 3389 | if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) { |
3390 | tp->rtl_ops.init(tp); | |
3391 | netif_device_attach(tp->netdev); | |
3392 | } | |
3393 | ||
ac718b69 | 3394 | if (netif_running(tp->netdev)) { |
9a4be1bd | 3395 | if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { |
3396 | rtl_runtime_suspend_enable(tp, false); | |
3397 | clear_bit(SELECTIVE_SUSPEND, &tp->flags); | |
41cec84c | 3398 | napi_disable(&tp->napi); |
445f7f4d | 3399 | set_bit(WORK_ENABLE, &tp->flags); |
51d979fa | 3400 | if (netif_carrier_ok(tp->netdev)) |
445f7f4d | 3401 | rtl_start_rx(tp); |
41cec84c | 3402 | napi_enable(&tp->napi); |
9a4be1bd | 3403 | } else { |
3404 | tp->rtl_ops.up(tp); | |
3405 | rtl8152_set_speed(tp, AUTONEG_ENABLE, | |
b209af99 | 3406 | tp->mii.supports_gmii ? |
3407 | SPEED_1000 : SPEED_100, | |
3408 | DUPLEX_FULL); | |
445f7f4d | 3409 | netif_carrier_off(tp->netdev); |
3410 | set_bit(WORK_ENABLE, &tp->flags); | |
9a4be1bd | 3411 | } |
40a82917 | 3412 | usb_submit_urb(tp->intr_urb, GFP_KERNEL); |
923e1ee3 | 3413 | } else if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { |
3414 | clear_bit(SELECTIVE_SUSPEND, &tp->flags); | |
ac718b69 | 3415 | } |
3416 | ||
b5403273 | 3417 | mutex_unlock(&tp->control); |
3418 | ||
ac718b69 | 3419 | return 0; |
3420 | } | |
3421 | ||
21ff2e89 | 3422 | static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
3423 | { | |
3424 | struct r8152 *tp = netdev_priv(dev); | |
3425 | ||
9a4be1bd | 3426 | if (usb_autopm_get_interface(tp->intf) < 0) |
3427 | return; | |
3428 | ||
7daed8dc | 3429 | if (!rtl_can_wakeup(tp)) { |
3430 | wol->supported = 0; | |
3431 | wol->wolopts = 0; | |
3432 | } else { | |
3433 | mutex_lock(&tp->control); | |
3434 | wol->supported = WAKE_ANY; | |
3435 | wol->wolopts = __rtl_get_wol(tp); | |
3436 | mutex_unlock(&tp->control); | |
3437 | } | |
b5403273 | 3438 | |
9a4be1bd | 3439 | usb_autopm_put_interface(tp->intf); |
21ff2e89 | 3440 | } |
3441 | ||
3442 | static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
3443 | { | |
3444 | struct r8152 *tp = netdev_priv(dev); | |
9a4be1bd | 3445 | int ret; |
3446 | ||
7daed8dc | 3447 | if (!rtl_can_wakeup(tp)) |
3448 | return -EOPNOTSUPP; | |
3449 | ||
9a4be1bd | 3450 | ret = usb_autopm_get_interface(tp->intf); |
3451 | if (ret < 0) | |
3452 | goto out_set_wol; | |
21ff2e89 | 3453 | |
b5403273 | 3454 | mutex_lock(&tp->control); |
3455 | ||
21ff2e89 | 3456 | __rtl_set_wol(tp, wol->wolopts); |
3457 | tp->saved_wolopts = wol->wolopts & WAKE_ANY; | |
3458 | ||
b5403273 | 3459 | mutex_unlock(&tp->control); |
3460 | ||
9a4be1bd | 3461 | usb_autopm_put_interface(tp->intf); |
3462 | ||
3463 | out_set_wol: | |
3464 | return ret; | |
21ff2e89 | 3465 | } |
3466 | ||
a5ec27c1 | 3467 | static u32 rtl8152_get_msglevel(struct net_device *dev) |
3468 | { | |
3469 | struct r8152 *tp = netdev_priv(dev); | |
3470 | ||
3471 | return tp->msg_enable; | |
3472 | } | |
3473 | ||
3474 | static void rtl8152_set_msglevel(struct net_device *dev, u32 value) | |
3475 | { | |
3476 | struct r8152 *tp = netdev_priv(dev); | |
3477 | ||
3478 | tp->msg_enable = value; | |
3479 | } | |
3480 | ||
ac718b69 | 3481 | static void rtl8152_get_drvinfo(struct net_device *netdev, |
3482 | struct ethtool_drvinfo *info) | |
3483 | { | |
3484 | struct r8152 *tp = netdev_priv(netdev); | |
3485 | ||
b0b46c77 | 3486 | strlcpy(info->driver, MODULENAME, sizeof(info->driver)); |
3487 | strlcpy(info->version, DRIVER_VERSION, sizeof(info->version)); | |
ac718b69 | 3488 | usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info)); |
3489 | } | |
3490 | ||
3491 | static | |
3492 | int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd) | |
3493 | { | |
3494 | struct r8152 *tp = netdev_priv(netdev); | |
8d4a4d72 | 3495 | int ret; |
ac718b69 | 3496 | |
3497 | if (!tp->mii.mdio_read) | |
3498 | return -EOPNOTSUPP; | |
3499 | ||
8d4a4d72 | 3500 | ret = usb_autopm_get_interface(tp->intf); |
3501 | if (ret < 0) | |
3502 | goto out; | |
3503 | ||
b5403273 | 3504 | mutex_lock(&tp->control); |
3505 | ||
8d4a4d72 | 3506 | ret = mii_ethtool_gset(&tp->mii, cmd); |
3507 | ||
b5403273 | 3508 | mutex_unlock(&tp->control); |
3509 | ||
8d4a4d72 | 3510 | usb_autopm_put_interface(tp->intf); |
3511 | ||
3512 | out: | |
3513 | return ret; | |
ac718b69 | 3514 | } |
3515 | ||
3516 | static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
3517 | { | |
3518 | struct r8152 *tp = netdev_priv(dev); | |
9a4be1bd | 3519 | int ret; |
3520 | ||
3521 | ret = usb_autopm_get_interface(tp->intf); | |
3522 | if (ret < 0) | |
3523 | goto out; | |
ac718b69 | 3524 | |
b5403273 | 3525 | mutex_lock(&tp->control); |
3526 | ||
9a4be1bd | 3527 | ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex); |
3528 | ||
b5403273 | 3529 | mutex_unlock(&tp->control); |
3530 | ||
9a4be1bd | 3531 | usb_autopm_put_interface(tp->intf); |
3532 | ||
3533 | out: | |
3534 | return ret; | |
ac718b69 | 3535 | } |
3536 | ||
4f1d4d54 | 3537 | static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = { |
3538 | "tx_packets", | |
3539 | "rx_packets", | |
3540 | "tx_errors", | |
3541 | "rx_errors", | |
3542 | "rx_missed", | |
3543 | "align_errors", | |
3544 | "tx_single_collisions", | |
3545 | "tx_multi_collisions", | |
3546 | "rx_unicast", | |
3547 | "rx_broadcast", | |
3548 | "rx_multicast", | |
3549 | "tx_aborted", | |
3550 | "tx_underrun", | |
3551 | }; | |
3552 | ||
3553 | static int rtl8152_get_sset_count(struct net_device *dev, int sset) | |
3554 | { | |
3555 | switch (sset) { | |
3556 | case ETH_SS_STATS: | |
3557 | return ARRAY_SIZE(rtl8152_gstrings); | |
3558 | default: | |
3559 | return -EOPNOTSUPP; | |
3560 | } | |
3561 | } | |
3562 | ||
3563 | static void rtl8152_get_ethtool_stats(struct net_device *dev, | |
3564 | struct ethtool_stats *stats, u64 *data) | |
3565 | { | |
3566 | struct r8152 *tp = netdev_priv(dev); | |
3567 | struct tally_counter tally; | |
3568 | ||
0b030244 | 3569 | if (usb_autopm_get_interface(tp->intf) < 0) |
3570 | return; | |
3571 | ||
4f1d4d54 | 3572 | generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA); |
3573 | ||
0b030244 | 3574 | usb_autopm_put_interface(tp->intf); |
3575 | ||
4f1d4d54 | 3576 | data[0] = le64_to_cpu(tally.tx_packets); |
3577 | data[1] = le64_to_cpu(tally.rx_packets); | |
3578 | data[2] = le64_to_cpu(tally.tx_errors); | |
3579 | data[3] = le32_to_cpu(tally.rx_errors); | |
3580 | data[4] = le16_to_cpu(tally.rx_missed); | |
3581 | data[5] = le16_to_cpu(tally.align_errors); | |
3582 | data[6] = le32_to_cpu(tally.tx_one_collision); | |
3583 | data[7] = le32_to_cpu(tally.tx_multi_collision); | |
3584 | data[8] = le64_to_cpu(tally.rx_unicast); | |
3585 | data[9] = le64_to_cpu(tally.rx_broadcast); | |
3586 | data[10] = le32_to_cpu(tally.rx_multicast); | |
3587 | data[11] = le16_to_cpu(tally.tx_aborted); | |
f37119c5 | 3588 | data[12] = le16_to_cpu(tally.tx_underrun); |
4f1d4d54 | 3589 | } |
3590 | ||
3591 | static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data) | |
3592 | { | |
3593 | switch (stringset) { | |
3594 | case ETH_SS_STATS: | |
3595 | memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings)); | |
3596 | break; | |
3597 | } | |
3598 | } | |
3599 | ||
df35d283 | 3600 | static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee) |
3601 | { | |
3602 | u32 ocp_data, lp, adv, supported = 0; | |
3603 | u16 val; | |
3604 | ||
3605 | val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); | |
3606 | supported = mmd_eee_cap_to_ethtool_sup_t(val); | |
3607 | ||
3608 | val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV); | |
3609 | adv = mmd_eee_adv_to_ethtool_adv_t(val); | |
3610 | ||
3611 | val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE); | |
3612 | lp = mmd_eee_adv_to_ethtool_adv_t(val); | |
3613 | ||
3614 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); | |
3615 | ocp_data &= EEE_RX_EN | EEE_TX_EN; | |
3616 | ||
3617 | eee->eee_enabled = !!ocp_data; | |
3618 | eee->eee_active = !!(supported & adv & lp); | |
3619 | eee->supported = supported; | |
3620 | eee->advertised = adv; | |
3621 | eee->lp_advertised = lp; | |
3622 | ||
3623 | return 0; | |
3624 | } | |
3625 | ||
3626 | static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee) | |
3627 | { | |
3628 | u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); | |
3629 | ||
3630 | r8152_eee_en(tp, eee->eee_enabled); | |
3631 | ||
3632 | if (!eee->eee_enabled) | |
3633 | val = 0; | |
3634 | ||
3635 | r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val); | |
3636 | ||
3637 | return 0; | |
3638 | } | |
3639 | ||
3640 | static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee) | |
3641 | { | |
3642 | u32 ocp_data, lp, adv, supported = 0; | |
3643 | u16 val; | |
3644 | ||
3645 | val = ocp_reg_read(tp, OCP_EEE_ABLE); | |
3646 | supported = mmd_eee_cap_to_ethtool_sup_t(val); | |
3647 | ||
3648 | val = ocp_reg_read(tp, OCP_EEE_ADV); | |
3649 | adv = mmd_eee_adv_to_ethtool_adv_t(val); | |
3650 | ||
3651 | val = ocp_reg_read(tp, OCP_EEE_LPABLE); | |
3652 | lp = mmd_eee_adv_to_ethtool_adv_t(val); | |
3653 | ||
3654 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); | |
3655 | ocp_data &= EEE_RX_EN | EEE_TX_EN; | |
3656 | ||
3657 | eee->eee_enabled = !!ocp_data; | |
3658 | eee->eee_active = !!(supported & adv & lp); | |
3659 | eee->supported = supported; | |
3660 | eee->advertised = adv; | |
3661 | eee->lp_advertised = lp; | |
3662 | ||
3663 | return 0; | |
3664 | } | |
3665 | ||
3666 | static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee) | |
3667 | { | |
3668 | u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); | |
3669 | ||
3670 | r8153_eee_en(tp, eee->eee_enabled); | |
3671 | ||
3672 | if (!eee->eee_enabled) | |
3673 | val = 0; | |
3674 | ||
3675 | ocp_reg_write(tp, OCP_EEE_ADV, val); | |
3676 | ||
3677 | return 0; | |
3678 | } | |
3679 | ||
3680 | static int | |
3681 | rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata) | |
3682 | { | |
3683 | struct r8152 *tp = netdev_priv(net); | |
3684 | int ret; | |
3685 | ||
3686 | ret = usb_autopm_get_interface(tp->intf); | |
3687 | if (ret < 0) | |
3688 | goto out; | |
3689 | ||
b5403273 | 3690 | mutex_lock(&tp->control); |
3691 | ||
df35d283 | 3692 | ret = tp->rtl_ops.eee_get(tp, edata); |
3693 | ||
b5403273 | 3694 | mutex_unlock(&tp->control); |
3695 | ||
df35d283 | 3696 | usb_autopm_put_interface(tp->intf); |
3697 | ||
3698 | out: | |
3699 | return ret; | |
3700 | } | |
3701 | ||
3702 | static int | |
3703 | rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata) | |
3704 | { | |
3705 | struct r8152 *tp = netdev_priv(net); | |
3706 | int ret; | |
3707 | ||
3708 | ret = usb_autopm_get_interface(tp->intf); | |
3709 | if (ret < 0) | |
3710 | goto out; | |
3711 | ||
b5403273 | 3712 | mutex_lock(&tp->control); |
3713 | ||
df35d283 | 3714 | ret = tp->rtl_ops.eee_set(tp, edata); |
9d31a7b9 | 3715 | if (!ret) |
3716 | ret = mii_nway_restart(&tp->mii); | |
df35d283 | 3717 | |
b5403273 | 3718 | mutex_unlock(&tp->control); |
3719 | ||
df35d283 | 3720 | usb_autopm_put_interface(tp->intf); |
3721 | ||
3722 | out: | |
3723 | return ret; | |
3724 | } | |
3725 | ||
8884f507 | 3726 | static int rtl8152_nway_reset(struct net_device *dev) |
3727 | { | |
3728 | struct r8152 *tp = netdev_priv(dev); | |
3729 | int ret; | |
3730 | ||
3731 | ret = usb_autopm_get_interface(tp->intf); | |
3732 | if (ret < 0) | |
3733 | goto out; | |
3734 | ||
3735 | mutex_lock(&tp->control); | |
3736 | ||
3737 | ret = mii_nway_restart(&tp->mii); | |
3738 | ||
3739 | mutex_unlock(&tp->control); | |
3740 | ||
3741 | usb_autopm_put_interface(tp->intf); | |
3742 | ||
3743 | out: | |
3744 | return ret; | |
3745 | } | |
3746 | ||
efb3dd88 | 3747 | static int rtl8152_get_coalesce(struct net_device *netdev, |
3748 | struct ethtool_coalesce *coalesce) | |
3749 | { | |
3750 | struct r8152 *tp = netdev_priv(netdev); | |
3751 | ||
3752 | switch (tp->version) { | |
3753 | case RTL_VER_01: | |
3754 | case RTL_VER_02: | |
3755 | return -EOPNOTSUPP; | |
3756 | default: | |
3757 | break; | |
3758 | } | |
3759 | ||
3760 | coalesce->rx_coalesce_usecs = tp->coalesce; | |
3761 | ||
3762 | return 0; | |
3763 | } | |
3764 | ||
3765 | static int rtl8152_set_coalesce(struct net_device *netdev, | |
3766 | struct ethtool_coalesce *coalesce) | |
3767 | { | |
3768 | struct r8152 *tp = netdev_priv(netdev); | |
3769 | int ret; | |
3770 | ||
3771 | switch (tp->version) { | |
3772 | case RTL_VER_01: | |
3773 | case RTL_VER_02: | |
3774 | return -EOPNOTSUPP; | |
3775 | default: | |
3776 | break; | |
3777 | } | |
3778 | ||
3779 | if (coalesce->rx_coalesce_usecs > COALESCE_SLOW) | |
3780 | return -EINVAL; | |
3781 | ||
3782 | ret = usb_autopm_get_interface(tp->intf); | |
3783 | if (ret < 0) | |
3784 | return ret; | |
3785 | ||
3786 | mutex_lock(&tp->control); | |
3787 | ||
3788 | if (tp->coalesce != coalesce->rx_coalesce_usecs) { | |
3789 | tp->coalesce = coalesce->rx_coalesce_usecs; | |
3790 | ||
3791 | if (netif_running(tp->netdev) && netif_carrier_ok(netdev)) | |
3792 | r8153_set_rx_early_timeout(tp); | |
3793 | } | |
3794 | ||
3795 | mutex_unlock(&tp->control); | |
3796 | ||
3797 | usb_autopm_put_interface(tp->intf); | |
3798 | ||
3799 | return ret; | |
3800 | } | |
3801 | ||
ac718b69 | 3802 | static struct ethtool_ops ops = { |
3803 | .get_drvinfo = rtl8152_get_drvinfo, | |
3804 | .get_settings = rtl8152_get_settings, | |
3805 | .set_settings = rtl8152_set_settings, | |
3806 | .get_link = ethtool_op_get_link, | |
8884f507 | 3807 | .nway_reset = rtl8152_nway_reset, |
a5ec27c1 | 3808 | .get_msglevel = rtl8152_get_msglevel, |
3809 | .set_msglevel = rtl8152_set_msglevel, | |
21ff2e89 | 3810 | .get_wol = rtl8152_get_wol, |
3811 | .set_wol = rtl8152_set_wol, | |
4f1d4d54 | 3812 | .get_strings = rtl8152_get_strings, |
3813 | .get_sset_count = rtl8152_get_sset_count, | |
3814 | .get_ethtool_stats = rtl8152_get_ethtool_stats, | |
efb3dd88 | 3815 | .get_coalesce = rtl8152_get_coalesce, |
3816 | .set_coalesce = rtl8152_set_coalesce, | |
df35d283 | 3817 | .get_eee = rtl_ethtool_get_eee, |
3818 | .set_eee = rtl_ethtool_set_eee, | |
ac718b69 | 3819 | }; |
3820 | ||
3821 | static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) | |
3822 | { | |
3823 | struct r8152 *tp = netdev_priv(netdev); | |
3824 | struct mii_ioctl_data *data = if_mii(rq); | |
9a4be1bd | 3825 | int res; |
3826 | ||
6871438c | 3827 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
3828 | return -ENODEV; | |
3829 | ||
9a4be1bd | 3830 | res = usb_autopm_get_interface(tp->intf); |
3831 | if (res < 0) | |
3832 | goto out; | |
ac718b69 | 3833 | |
3834 | switch (cmd) { | |
3835 | case SIOCGMIIPHY: | |
3836 | data->phy_id = R8152_PHY_ID; /* Internal PHY */ | |
3837 | break; | |
3838 | ||
3839 | case SIOCGMIIREG: | |
b5403273 | 3840 | mutex_lock(&tp->control); |
ac718b69 | 3841 | data->val_out = r8152_mdio_read(tp, data->reg_num); |
b5403273 | 3842 | mutex_unlock(&tp->control); |
ac718b69 | 3843 | break; |
3844 | ||
3845 | case SIOCSMIIREG: | |
3846 | if (!capable(CAP_NET_ADMIN)) { | |
3847 | res = -EPERM; | |
3848 | break; | |
3849 | } | |
b5403273 | 3850 | mutex_lock(&tp->control); |
ac718b69 | 3851 | r8152_mdio_write(tp, data->reg_num, data->val_in); |
b5403273 | 3852 | mutex_unlock(&tp->control); |
ac718b69 | 3853 | break; |
3854 | ||
3855 | default: | |
3856 | res = -EOPNOTSUPP; | |
3857 | } | |
3858 | ||
9a4be1bd | 3859 | usb_autopm_put_interface(tp->intf); |
3860 | ||
3861 | out: | |
ac718b69 | 3862 | return res; |
3863 | } | |
3864 | ||
69b4b7a4 | 3865 | static int rtl8152_change_mtu(struct net_device *dev, int new_mtu) |
3866 | { | |
3867 | struct r8152 *tp = netdev_priv(dev); | |
396e2e23 | 3868 | int ret; |
69b4b7a4 | 3869 | |
3870 | switch (tp->version) { | |
3871 | case RTL_VER_01: | |
3872 | case RTL_VER_02: | |
3873 | return eth_change_mtu(dev, new_mtu); | |
3874 | default: | |
3875 | break; | |
3876 | } | |
3877 | ||
3878 | if (new_mtu < 68 || new_mtu > RTL8153_MAX_MTU) | |
3879 | return -EINVAL; | |
3880 | ||
396e2e23 | 3881 | ret = usb_autopm_get_interface(tp->intf); |
3882 | if (ret < 0) | |
3883 | return ret; | |
3884 | ||
3885 | mutex_lock(&tp->control); | |
3886 | ||
69b4b7a4 | 3887 | dev->mtu = new_mtu; |
3888 | ||
396e2e23 | 3889 | if (netif_running(dev) && netif_carrier_ok(dev)) |
3890 | r8153_set_rx_early_size(tp); | |
3891 | ||
3892 | mutex_unlock(&tp->control); | |
3893 | ||
3894 | usb_autopm_put_interface(tp->intf); | |
3895 | ||
3896 | return ret; | |
69b4b7a4 | 3897 | } |
3898 | ||
ac718b69 | 3899 | static const struct net_device_ops rtl8152_netdev_ops = { |
3900 | .ndo_open = rtl8152_open, | |
3901 | .ndo_stop = rtl8152_close, | |
3902 | .ndo_do_ioctl = rtl8152_ioctl, | |
3903 | .ndo_start_xmit = rtl8152_start_xmit, | |
3904 | .ndo_tx_timeout = rtl8152_tx_timeout, | |
c5554298 | 3905 | .ndo_set_features = rtl8152_set_features, |
ac718b69 | 3906 | .ndo_set_rx_mode = rtl8152_set_rx_mode, |
3907 | .ndo_set_mac_address = rtl8152_set_mac_address, | |
69b4b7a4 | 3908 | .ndo_change_mtu = rtl8152_change_mtu, |
ac718b69 | 3909 | .ndo_validate_addr = eth_validate_addr, |
a5e31255 | 3910 | .ndo_features_check = rtl8152_features_check, |
ac718b69 | 3911 | }; |
3912 | ||
3913 | static void r8152b_get_version(struct r8152 *tp) | |
3914 | { | |
3915 | u32 ocp_data; | |
3916 | u16 version; | |
3917 | ||
3918 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1); | |
3919 | version = (u16)(ocp_data & VERSION_MASK); | |
3920 | ||
3921 | switch (version) { | |
3922 | case 0x4c00: | |
3923 | tp->version = RTL_VER_01; | |
3924 | break; | |
3925 | case 0x4c10: | |
3926 | tp->version = RTL_VER_02; | |
3927 | break; | |
43779f8d | 3928 | case 0x5c00: |
3929 | tp->version = RTL_VER_03; | |
3930 | tp->mii.supports_gmii = 1; | |
3931 | break; | |
3932 | case 0x5c10: | |
3933 | tp->version = RTL_VER_04; | |
3934 | tp->mii.supports_gmii = 1; | |
3935 | break; | |
3936 | case 0x5c20: | |
3937 | tp->version = RTL_VER_05; | |
3938 | tp->mii.supports_gmii = 1; | |
3939 | break; | |
ac718b69 | 3940 | default: |
3941 | netif_info(tp, probe, tp->netdev, | |
3942 | "Unknown version 0x%04x\n", version); | |
3943 | break; | |
3944 | } | |
3945 | } | |
3946 | ||
e3fe0b1a | 3947 | static void rtl8152_unload(struct r8152 *tp) |
3948 | { | |
6871438c | 3949 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
3950 | return; | |
3951 | ||
00a5e360 | 3952 | if (tp->version != RTL_VER_01) |
3953 | r8152_power_cut_en(tp, true); | |
e3fe0b1a | 3954 | } |
3955 | ||
43779f8d | 3956 | static void rtl8153_unload(struct r8152 *tp) |
3957 | { | |
6871438c | 3958 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
3959 | return; | |
3960 | ||
49be1723 | 3961 | r8153_power_cut_en(tp, false); |
43779f8d | 3962 | } |
3963 | ||
55b65475 | 3964 | static int rtl_ops_init(struct r8152 *tp) |
c81229c9 | 3965 | { |
3966 | struct rtl_ops *ops = &tp->rtl_ops; | |
55b65475 | 3967 | int ret = 0; |
3968 | ||
3969 | switch (tp->version) { | |
3970 | case RTL_VER_01: | |
3971 | case RTL_VER_02: | |
3972 | ops->init = r8152b_init; | |
3973 | ops->enable = rtl8152_enable; | |
3974 | ops->disable = rtl8152_disable; | |
3975 | ops->up = rtl8152_up; | |
3976 | ops->down = rtl8152_down; | |
3977 | ops->unload = rtl8152_unload; | |
3978 | ops->eee_get = r8152_get_eee; | |
3979 | ops->eee_set = r8152_set_eee; | |
43779f8d | 3980 | break; |
3981 | ||
55b65475 | 3982 | case RTL_VER_03: |
3983 | case RTL_VER_04: | |
3984 | case RTL_VER_05: | |
3985 | ops->init = r8153_init; | |
3986 | ops->enable = rtl8153_enable; | |
3987 | ops->disable = rtl8153_disable; | |
3988 | ops->up = rtl8153_up; | |
3989 | ops->down = rtl8153_down; | |
3990 | ops->unload = rtl8153_unload; | |
3991 | ops->eee_get = r8153_get_eee; | |
3992 | ops->eee_set = r8153_set_eee; | |
c81229c9 | 3993 | break; |
3994 | ||
3995 | default: | |
55b65475 | 3996 | ret = -ENODEV; |
3997 | netif_err(tp, probe, tp->netdev, "Unknown Device\n"); | |
c81229c9 | 3998 | break; |
3999 | } | |
4000 | ||
4001 | return ret; | |
4002 | } | |
4003 | ||
ac718b69 | 4004 | static int rtl8152_probe(struct usb_interface *intf, |
4005 | const struct usb_device_id *id) | |
4006 | { | |
4007 | struct usb_device *udev = interface_to_usbdev(intf); | |
4008 | struct r8152 *tp; | |
4009 | struct net_device *netdev; | |
ebc2ec48 | 4010 | int ret; |
ac718b69 | 4011 | |
10c32717 | 4012 | if (udev->actconfig->desc.bConfigurationValue != 1) { |
4013 | usb_driver_set_configuration(udev, 1); | |
4014 | return -ENODEV; | |
4015 | } | |
4016 | ||
4017 | usb_reset_device(udev); | |
ac718b69 | 4018 | netdev = alloc_etherdev(sizeof(struct r8152)); |
4019 | if (!netdev) { | |
4a8deae2 | 4020 | dev_err(&intf->dev, "Out of memory\n"); |
ac718b69 | 4021 | return -ENOMEM; |
4022 | } | |
4023 | ||
ebc2ec48 | 4024 | SET_NETDEV_DEV(netdev, &intf->dev); |
ac718b69 | 4025 | tp = netdev_priv(netdev); |
4026 | tp->msg_enable = 0x7FFF; | |
4027 | ||
e3ad412a | 4028 | tp->udev = udev; |
4029 | tp->netdev = netdev; | |
4030 | tp->intf = intf; | |
4031 | ||
82cf94cb | 4032 | r8152b_get_version(tp); |
55b65475 | 4033 | ret = rtl_ops_init(tp); |
31ca1dec | 4034 | if (ret) |
4035 | goto out; | |
c81229c9 | 4036 | |
b5403273 | 4037 | mutex_init(&tp->control); |
ac718b69 | 4038 | INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t); |
4039 | ||
ac718b69 | 4040 | netdev->netdev_ops = &rtl8152_netdev_ops; |
4041 | netdev->watchdog_timeo = RTL8152_TX_TIMEOUT; | |
5bd23881 | 4042 | |
60c89071 | 4043 | netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | |
6128d1bb | 4044 | NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM | |
c5554298 | 4045 | NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX | |
4046 | NETIF_F_HW_VLAN_CTAG_TX; | |
60c89071 | 4047 | netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | |
6128d1bb | 4048 | NETIF_F_TSO | NETIF_F_FRAGLIST | |
c5554298 | 4049 | NETIF_F_IPV6_CSUM | NETIF_F_TSO6 | |
ccc39faf | 4050 | NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX; |
c5554298 | 4051 | netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | |
4052 | NETIF_F_HIGHDMA | NETIF_F_FRAGLIST | | |
4053 | NETIF_F_IPV6_CSUM | NETIF_F_TSO6; | |
db8515ef | 4054 | |
7ad24ea4 | 4055 | netdev->ethtool_ops = &ops; |
60c89071 | 4056 | netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE); |
ac718b69 | 4057 | |
4058 | tp->mii.dev = netdev; | |
4059 | tp->mii.mdio_read = read_mii_word; | |
4060 | tp->mii.mdio_write = write_mii_word; | |
4061 | tp->mii.phy_id_mask = 0x3f; | |
4062 | tp->mii.reg_num_mask = 0x1f; | |
4063 | tp->mii.phy_id = R8152_PHY_ID; | |
ac718b69 | 4064 | |
464ec10a | 4065 | switch (udev->speed) { |
4066 | case USB_SPEED_SUPER: | |
4067 | tp->coalesce = COALESCE_SUPER; | |
4068 | break; | |
4069 | case USB_SPEED_HIGH: | |
4070 | tp->coalesce = COALESCE_HIGH; | |
4071 | break; | |
4072 | default: | |
4073 | tp->coalesce = COALESCE_SLOW; | |
4074 | break; | |
4075 | } | |
4076 | ||
9a4be1bd | 4077 | intf->needs_remote_wakeup = 1; |
4078 | ||
c81229c9 | 4079 | tp->rtl_ops.init(tp); |
ac718b69 | 4080 | set_ethernet_addr(tp); |
4081 | ||
ac718b69 | 4082 | usb_set_intfdata(intf, tp); |
d823ab68 | 4083 | netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT); |
ac718b69 | 4084 | |
ebc2ec48 | 4085 | ret = register_netdev(netdev); |
4086 | if (ret != 0) { | |
4a8deae2 | 4087 | netif_err(tp, probe, netdev, "couldn't register the device\n"); |
ebc2ec48 | 4088 | goto out1; |
ac718b69 | 4089 | } |
4090 | ||
7daed8dc | 4091 | if (!rtl_can_wakeup(tp)) |
4092 | __rtl_set_wol(tp, 0); | |
4093 | ||
21ff2e89 | 4094 | tp->saved_wolopts = __rtl_get_wol(tp); |
4095 | if (tp->saved_wolopts) | |
4096 | device_set_wakeup_enable(&udev->dev, true); | |
4097 | else | |
4098 | device_set_wakeup_enable(&udev->dev, false); | |
4099 | ||
4a8deae2 | 4100 | netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION); |
ac718b69 | 4101 | |
4102 | return 0; | |
4103 | ||
ac718b69 | 4104 | out1: |
d823ab68 | 4105 | netif_napi_del(&tp->napi); |
ebc2ec48 | 4106 | usb_set_intfdata(intf, NULL); |
ac718b69 | 4107 | out: |
4108 | free_netdev(netdev); | |
ebc2ec48 | 4109 | return ret; |
ac718b69 | 4110 | } |
4111 | ||
ac718b69 | 4112 | static void rtl8152_disconnect(struct usb_interface *intf) |
4113 | { | |
4114 | struct r8152 *tp = usb_get_intfdata(intf); | |
4115 | ||
4116 | usb_set_intfdata(intf, NULL); | |
4117 | if (tp) { | |
f561de33 | 4118 | struct usb_device *udev = tp->udev; |
4119 | ||
4120 | if (udev->state == USB_STATE_NOTATTACHED) | |
4121 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
4122 | ||
d823ab68 | 4123 | netif_napi_del(&tp->napi); |
ac718b69 | 4124 | unregister_netdev(tp->netdev); |
c81229c9 | 4125 | tp->rtl_ops.unload(tp); |
ac718b69 | 4126 | free_netdev(tp->netdev); |
4127 | } | |
4128 | } | |
4129 | ||
d9a28c5b | 4130 | #define REALTEK_USB_DEVICE(vend, prod) \ |
4131 | .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \ | |
4132 | USB_DEVICE_ID_MATCH_INT_CLASS, \ | |
4133 | .idVendor = (vend), \ | |
4134 | .idProduct = (prod), \ | |
4135 | .bInterfaceClass = USB_CLASS_VENDOR_SPEC \ | |
4136 | }, \ | |
4137 | { \ | |
4138 | .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \ | |
4139 | USB_DEVICE_ID_MATCH_DEVICE, \ | |
4140 | .idVendor = (vend), \ | |
4141 | .idProduct = (prod), \ | |
4142 | .bInterfaceClass = USB_CLASS_COMM, \ | |
4143 | .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \ | |
4144 | .bInterfaceProtocol = USB_CDC_PROTO_NONE | |
4145 | ||
ac718b69 | 4146 | /* table of devices that work with this driver */ |
4147 | static struct usb_device_id rtl8152_table[] = { | |
d9a28c5b | 4148 | {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)}, |
4149 | {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)}, | |
4150 | {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)}, | |
347eec34 | 4151 | {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)}, |
1006da19 | 4152 | {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)}, |
d065c3c1 | 4153 | {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)}, |
ac718b69 | 4154 | {} |
4155 | }; | |
4156 | ||
4157 | MODULE_DEVICE_TABLE(usb, rtl8152_table); | |
4158 | ||
4159 | static struct usb_driver rtl8152_driver = { | |
4160 | .name = MODULENAME, | |
ebc2ec48 | 4161 | .id_table = rtl8152_table, |
ac718b69 | 4162 | .probe = rtl8152_probe, |
4163 | .disconnect = rtl8152_disconnect, | |
ac718b69 | 4164 | .suspend = rtl8152_suspend, |
ebc2ec48 | 4165 | .resume = rtl8152_resume, |
4166 | .reset_resume = rtl8152_resume, | |
9a4be1bd | 4167 | .supports_autosuspend = 1, |
a634782f | 4168 | .disable_hub_initiated_lpm = 1, |
ac718b69 | 4169 | }; |
4170 | ||
b4236daa | 4171 | module_usb_driver(rtl8152_driver); |
ac718b69 | 4172 | |
4173 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
4174 | MODULE_DESCRIPTION(DRIVER_DESC); | |
4175 | MODULE_LICENSE("GPL"); |