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Merge branch 'ibmvnic-LPM-bug-fixes'
[mirror_ubuntu-bionic-kernel.git] / drivers / net / usb / r8152.c
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ac718b69 1/*
c7de7dec 2 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
ac718b69 3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * version 2 as published by the Free Software Foundation.
7 *
8 */
9
ac718b69 10#include <linux/signal.h>
11#include <linux/slab.h>
12#include <linux/module.h>
ac718b69 13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/mii.h>
16#include <linux/ethtool.h>
17#include <linux/usb.h>
18#include <linux/crc32.h>
19#include <linux/if_vlan.h>
20#include <linux/uaccess.h>
ebc2ec48 21#include <linux/list.h>
5bd23881 22#include <linux/ip.h>
23#include <linux/ipv6.h>
6128d1bb 24#include <net/ip6_checksum.h>
4c4a6b1b 25#include <uapi/linux/mdio.h>
26#include <linux/mdio.h>
d9a28c5b 27#include <linux/usb/cdc.h>
5ee3c60c 28#include <linux/suspend.h>
34ee32c9 29#include <linux/acpi.h>
ac718b69 30
d0942473 31/* Information for net-next */
32#define NETNEXT_VERSION "08"
33
34/* Information for net */
b20cb60e 35#define NET_VERSION "9"
d0942473 36
37#define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION
ac718b69 38#define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
44d942a9 39#define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
ac718b69 40#define MODULENAME "r8152"
41
42#define R8152_PHY_ID 32
43
44#define PLA_IDR 0xc000
45#define PLA_RCR 0xc010
46#define PLA_RMS 0xc016
47#define PLA_RXFIFO_CTRL0 0xc0a0
48#define PLA_RXFIFO_CTRL1 0xc0a4
49#define PLA_RXFIFO_CTRL2 0xc0a8
65bab84c 50#define PLA_DMY_REG0 0xc0b0
ac718b69 51#define PLA_FMC 0xc0b4
52#define PLA_CFG_WOL 0xc0b6
43779f8d 53#define PLA_TEREDO_CFG 0xc0bc
ac718b69 54#define PLA_MAR 0xcd00
43779f8d 55#define PLA_BACKUP 0xd000
ac718b69 56#define PAL_BDC_CR 0xd1a0
43779f8d 57#define PLA_TEREDO_TIMER 0xd2cc
58#define PLA_REALWOW_TIMER 0xd2e8
ac718b69 59#define PLA_LEDSEL 0xdd90
60#define PLA_LED_FEATURE 0xdd92
61#define PLA_PHYAR 0xde00
43779f8d 62#define PLA_BOOT_CTRL 0xe004
ac718b69 63#define PLA_GPHY_INTR_IMR 0xe022
64#define PLA_EEE_CR 0xe040
65#define PLA_EEEP_CR 0xe080
66#define PLA_MAC_PWR_CTRL 0xe0c0
43779f8d 67#define PLA_MAC_PWR_CTRL2 0xe0ca
68#define PLA_MAC_PWR_CTRL3 0xe0cc
69#define PLA_MAC_PWR_CTRL4 0xe0ce
70#define PLA_WDT6_CTRL 0xe428
ac718b69 71#define PLA_TCR0 0xe610
72#define PLA_TCR1 0xe612
69b4b7a4 73#define PLA_MTPS 0xe615
ac718b69 74#define PLA_TXFIFO_CTRL 0xe618
4f1d4d54 75#define PLA_RSTTALLY 0xe800
ac718b69 76#define PLA_CR 0xe813
77#define PLA_CRWECR 0xe81c
21ff2e89 78#define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
79#define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
ac718b69 80#define PLA_CONFIG5 0xe822
81#define PLA_PHY_PWR 0xe84c
82#define PLA_OOB_CTRL 0xe84f
83#define PLA_CPCR 0xe854
84#define PLA_MISC_0 0xe858
85#define PLA_MISC_1 0xe85a
86#define PLA_OCP_GPHY_BASE 0xe86c
4f1d4d54 87#define PLA_TALLYCNT 0xe890
ac718b69 88#define PLA_SFF_STS_7 0xe8de
89#define PLA_PHYSTATUS 0xe908
90#define PLA_BP_BA 0xfc26
91#define PLA_BP_0 0xfc28
92#define PLA_BP_1 0xfc2a
93#define PLA_BP_2 0xfc2c
94#define PLA_BP_3 0xfc2e
95#define PLA_BP_4 0xfc30
96#define PLA_BP_5 0xfc32
97#define PLA_BP_6 0xfc34
98#define PLA_BP_7 0xfc36
43779f8d 99#define PLA_BP_EN 0xfc38
ac718b69 100
65bab84c 101#define USB_USB2PHY 0xb41e
102#define USB_SSPHYLINK2 0xb428
43779f8d 103#define USB_U2P3_CTRL 0xb460
65bab84c 104#define USB_CSR_DUMMY1 0xb464
105#define USB_CSR_DUMMY2 0xb466
ac718b69 106#define USB_DEV_STAT 0xb808
65bab84c 107#define USB_CONNECT_TIMER 0xcbf8
108#define USB_BURST_SIZE 0xcfc0
ac718b69 109#define USB_USB_CTRL 0xd406
110#define USB_PHY_CTRL 0xd408
111#define USB_TX_AGG 0xd40a
112#define USB_RX_BUF_TH 0xd40c
113#define USB_USB_TIMER 0xd428
464ec10a 114#define USB_RX_EARLY_TIMEOUT 0xd42c
115#define USB_RX_EARLY_SIZE 0xd42e
ac718b69 116#define USB_PM_CTRL_STATUS 0xd432
117#define USB_TX_DMA 0xd434
43779f8d 118#define USB_TOLERANCE 0xd490
119#define USB_LPM_CTRL 0xd41a
93fe9b18 120#define USB_BMU_RESET 0xd4b0
ac718b69 121#define USB_UPS_CTRL 0xd800
43779f8d 122#define USB_MISC_0 0xd81a
123#define USB_POWER_CUT 0xd80a
124#define USB_AFE_CTRL2 0xd824
125#define USB_WDT11_CTRL 0xe43c
ac718b69 126#define USB_BP_BA 0xfc26
127#define USB_BP_0 0xfc28
128#define USB_BP_1 0xfc2a
129#define USB_BP_2 0xfc2c
130#define USB_BP_3 0xfc2e
131#define USB_BP_4 0xfc30
132#define USB_BP_5 0xfc32
133#define USB_BP_6 0xfc34
134#define USB_BP_7 0xfc36
43779f8d 135#define USB_BP_EN 0xfc38
ac718b69 136
137/* OCP Registers */
138#define OCP_ALDPS_CONFIG 0x2010
139#define OCP_EEE_CONFIG1 0x2080
140#define OCP_EEE_CONFIG2 0x2092
141#define OCP_EEE_CONFIG3 0x2094
ac244d3e 142#define OCP_BASE_MII 0xa400
ac718b69 143#define OCP_EEE_AR 0xa41a
144#define OCP_EEE_DATA 0xa41c
43779f8d 145#define OCP_PHY_STATUS 0xa420
146#define OCP_POWER_CFG 0xa430
147#define OCP_EEE_CFG 0xa432
148#define OCP_SRAM_ADDR 0xa436
149#define OCP_SRAM_DATA 0xa438
150#define OCP_DOWN_SPEED 0xa442
df35d283 151#define OCP_EEE_ABLE 0xa5c4
4c4a6b1b 152#define OCP_EEE_ADV 0xa5d0
df35d283 153#define OCP_EEE_LPABLE 0xa5d2
2dd49e0f 154#define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
43779f8d 155#define OCP_ADC_CFG 0xbc06
156
157/* SRAM Register */
158#define SRAM_LPF_CFG 0x8012
159#define SRAM_10M_AMP1 0x8080
160#define SRAM_10M_AMP2 0x8082
161#define SRAM_IMPEDANCE 0x8084
ac718b69 162
163/* PLA_RCR */
164#define RCR_AAP 0x00000001
165#define RCR_APM 0x00000002
166#define RCR_AM 0x00000004
167#define RCR_AB 0x00000008
168#define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
169
170/* PLA_RXFIFO_CTRL0 */
171#define RXFIFO_THR1_NORMAL 0x00080002
172#define RXFIFO_THR1_OOB 0x01800003
173
174/* PLA_RXFIFO_CTRL1 */
175#define RXFIFO_THR2_FULL 0x00000060
176#define RXFIFO_THR2_HIGH 0x00000038
177#define RXFIFO_THR2_OOB 0x0000004a
43779f8d 178#define RXFIFO_THR2_NORMAL 0x00a0
ac718b69 179
180/* PLA_RXFIFO_CTRL2 */
181#define RXFIFO_THR3_FULL 0x00000078
182#define RXFIFO_THR3_HIGH 0x00000048
183#define RXFIFO_THR3_OOB 0x0000005a
43779f8d 184#define RXFIFO_THR3_NORMAL 0x0110
ac718b69 185
186/* PLA_TXFIFO_CTRL */
187#define TXFIFO_THR_NORMAL 0x00400008
43779f8d 188#define TXFIFO_THR_NORMAL2 0x01000008
ac718b69 189
65bab84c 190/* PLA_DMY_REG0 */
191#define ECM_ALDPS 0x0002
192
ac718b69 193/* PLA_FMC */
194#define FMC_FCR_MCU_EN 0x0001
195
196/* PLA_EEEP_CR */
197#define EEEP_CR_EEEP_TX 0x0002
198
43779f8d 199/* PLA_WDT6_CTRL */
200#define WDT6_SET_MODE 0x0010
201
ac718b69 202/* PLA_TCR0 */
203#define TCR0_TX_EMPTY 0x0800
204#define TCR0_AUTO_FIFO 0x0080
205
206/* PLA_TCR1 */
207#define VERSION_MASK 0x7cf0
208
69b4b7a4 209/* PLA_MTPS */
210#define MTPS_JUMBO (12 * 1024 / 64)
211#define MTPS_DEFAULT (6 * 1024 / 64)
212
4f1d4d54 213/* PLA_RSTTALLY */
214#define TALLY_RESET 0x0001
215
ac718b69 216/* PLA_CR */
217#define CR_RST 0x10
218#define CR_RE 0x08
219#define CR_TE 0x04
220
221/* PLA_CRWECR */
222#define CRWECR_NORAML 0x00
223#define CRWECR_CONFIG 0xc0
224
225/* PLA_OOB_CTRL */
226#define NOW_IS_OOB 0x80
227#define TXFIFO_EMPTY 0x20
228#define RXFIFO_EMPTY 0x10
229#define LINK_LIST_READY 0x02
230#define DIS_MCU_CLROOB 0x01
231#define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
232
233/* PLA_MISC_1 */
234#define RXDY_GATED_EN 0x0008
235
236/* PLA_SFF_STS_7 */
237#define RE_INIT_LL 0x8000
238#define MCU_BORW_EN 0x4000
239
240/* PLA_CPCR */
241#define CPCR_RX_VLAN 0x0040
242
243/* PLA_CFG_WOL */
244#define MAGIC_EN 0x0001
245
43779f8d 246/* PLA_TEREDO_CFG */
247#define TEREDO_SEL 0x8000
248#define TEREDO_WAKE_MASK 0x7f00
249#define TEREDO_RS_EVENT_MASK 0x00fe
250#define OOB_TEREDO_EN 0x0001
251
ac718b69 252/* PAL_BDC_CR */
253#define ALDPS_PROXY_MODE 0x0001
254
21ff2e89 255/* PLA_CONFIG34 */
256#define LINK_ON_WAKE_EN 0x0010
257#define LINK_OFF_WAKE_EN 0x0008
258
ac718b69 259/* PLA_CONFIG5 */
21ff2e89 260#define BWF_EN 0x0040
261#define MWF_EN 0x0020
262#define UWF_EN 0x0010
ac718b69 263#define LAN_WAKE_EN 0x0002
264
265/* PLA_LED_FEATURE */
266#define LED_MODE_MASK 0x0700
267
268/* PLA_PHY_PWR */
269#define TX_10M_IDLE_EN 0x0080
270#define PFM_PWM_SWITCH 0x0040
271
272/* PLA_MAC_PWR_CTRL */
273#define D3_CLK_GATED_EN 0x00004000
274#define MCU_CLK_RATIO 0x07010f07
275#define MCU_CLK_RATIO_MASK 0x0f0f0f0f
43779f8d 276#define ALDPS_SPDWN_RATIO 0x0f87
277
278/* PLA_MAC_PWR_CTRL2 */
279#define EEE_SPDWN_RATIO 0x8007
280
281/* PLA_MAC_PWR_CTRL3 */
282#define PKT_AVAIL_SPDWN_EN 0x0100
283#define SUSPEND_SPDWN_EN 0x0004
284#define U1U2_SPDWN_EN 0x0002
285#define L1_SPDWN_EN 0x0001
286
287/* PLA_MAC_PWR_CTRL4 */
288#define PWRSAVE_SPDWN_EN 0x1000
289#define RXDV_SPDWN_EN 0x0800
290#define TX10MIDLE_EN 0x0100
291#define TP100_SPDWN_EN 0x0020
292#define TP500_SPDWN_EN 0x0010
293#define TP1000_SPDWN_EN 0x0008
294#define EEE_SPDWN_EN 0x0001
ac718b69 295
296/* PLA_GPHY_INTR_IMR */
297#define GPHY_STS_MSK 0x0001
298#define SPEED_DOWN_MSK 0x0002
299#define SPDWN_RXDV_MSK 0x0004
300#define SPDWN_LINKCHG_MSK 0x0008
301
302/* PLA_PHYAR */
303#define PHYAR_FLAG 0x80000000
304
305/* PLA_EEE_CR */
306#define EEE_RX_EN 0x0001
307#define EEE_TX_EN 0x0002
308
43779f8d 309/* PLA_BOOT_CTRL */
310#define AUTOLOAD_DONE 0x0002
311
65bab84c 312/* USB_USB2PHY */
313#define USB2PHY_SUSPEND 0x0001
314#define USB2PHY_L1 0x0002
315
316/* USB_SSPHYLINK2 */
317#define pwd_dn_scale_mask 0x3ffe
318#define pwd_dn_scale(x) ((x) << 1)
319
320/* USB_CSR_DUMMY1 */
321#define DYNAMIC_BURST 0x0001
322
323/* USB_CSR_DUMMY2 */
324#define EP4_FULL_FC 0x0001
325
ac718b69 326/* USB_DEV_STAT */
327#define STAT_SPEED_MASK 0x0006
328#define STAT_SPEED_HIGH 0x0000
a3cc465d 329#define STAT_SPEED_FULL 0x0002
ac718b69 330
331/* USB_TX_AGG */
332#define TX_AGG_MAX_THRESHOLD 0x03
333
334/* USB_RX_BUF_TH */
43779f8d 335#define RX_THR_SUPPER 0x0c350180
8e1f51bd 336#define RX_THR_HIGH 0x7a120180
43779f8d 337#define RX_THR_SLOW 0xffff0180
ac718b69 338
339/* USB_TX_DMA */
340#define TEST_MODE_DISABLE 0x00000001
341#define TX_SIZE_ADJUST1 0x00000100
342
93fe9b18 343/* USB_BMU_RESET */
344#define BMU_RESET_EP_IN 0x01
345#define BMU_RESET_EP_OUT 0x02
346
ac718b69 347/* USB_UPS_CTRL */
348#define POWER_CUT 0x0100
349
350/* USB_PM_CTRL_STATUS */
8e1f51bd 351#define RESUME_INDICATE 0x0001
ac718b69 352
353/* USB_USB_CTRL */
354#define RX_AGG_DISABLE 0x0010
e90fba8d 355#define RX_ZERO_EN 0x0080
ac718b69 356
43779f8d 357/* USB_U2P3_CTRL */
358#define U2P3_ENABLE 0x0001
359
360/* USB_POWER_CUT */
361#define PWR_EN 0x0001
362#define PHASE2_EN 0x0008
363
364/* USB_MISC_0 */
365#define PCUT_STATUS 0x0001
366
464ec10a 367/* USB_RX_EARLY_TIMEOUT */
368#define COALESCE_SUPER 85000U
369#define COALESCE_HIGH 250000U
370#define COALESCE_SLOW 524280U
43779f8d 371
372/* USB_WDT11_CTRL */
373#define TIMER11_EN 0x0001
374
375/* USB_LPM_CTRL */
65bab84c 376/* bit 4 ~ 5: fifo empty boundary */
377#define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
378/* bit 2 ~ 3: LMP timer */
43779f8d 379#define LPM_TIMER_MASK 0x0c
380#define LPM_TIMER_500MS 0x04 /* 500 ms */
381#define LPM_TIMER_500US 0x0c /* 500 us */
65bab84c 382#define ROK_EXIT_LPM 0x02
43779f8d 383
384/* USB_AFE_CTRL2 */
385#define SEN_VAL_MASK 0xf800
386#define SEN_VAL_NORMAL 0xa000
387#define SEL_RXIDLE 0x0100
388
ac718b69 389/* OCP_ALDPS_CONFIG */
390#define ENPWRSAVE 0x8000
391#define ENPDNPS 0x0200
392#define LINKENA 0x0100
393#define DIS_SDSAVE 0x0010
394
43779f8d 395/* OCP_PHY_STATUS */
396#define PHY_STAT_MASK 0x0007
c564b871 397#define PHY_STAT_EXT_INIT 2
43779f8d 398#define PHY_STAT_LAN_ON 3
399#define PHY_STAT_PWRDN 5
400
401/* OCP_POWER_CFG */
402#define EEE_CLKDIV_EN 0x8000
403#define EN_ALDPS 0x0004
404#define EN_10M_PLLOFF 0x0001
405
ac718b69 406/* OCP_EEE_CONFIG1 */
407#define RG_TXLPI_MSK_HFDUP 0x8000
408#define RG_MATCLR_EN 0x4000
409#define EEE_10_CAP 0x2000
410#define EEE_NWAY_EN 0x1000
411#define TX_QUIET_EN 0x0200
412#define RX_QUIET_EN 0x0100
d24f6134 413#define sd_rise_time_mask 0x0070
4c4a6b1b 414#define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
ac718b69 415#define RG_RXLPI_MSK_HFDUP 0x0008
416#define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
417
418/* OCP_EEE_CONFIG2 */
419#define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
420#define RG_DACQUIET_EN 0x0400
421#define RG_LDVQUIET_EN 0x0200
422#define RG_CKRSEL 0x0020
423#define RG_EEEPRG_EN 0x0010
424
425/* OCP_EEE_CONFIG3 */
d24f6134 426#define fast_snr_mask 0xff80
4c4a6b1b 427#define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
ac718b69 428#define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
429#define MSK_PH 0x0006 /* bit 0 ~ 3 */
430
431/* OCP_EEE_AR */
432/* bit[15:14] function */
433#define FUN_ADDR 0x0000
434#define FUN_DATA 0x4000
435/* bit[4:0] device addr */
ac718b69 436
43779f8d 437/* OCP_EEE_CFG */
438#define CTAP_SHORT_EN 0x0040
439#define EEE10_EN 0x0010
440
441/* OCP_DOWN_SPEED */
442#define EN_10M_BGOFF 0x0080
443
2dd49e0f 444/* OCP_PHY_STATE */
445#define TXDIS_STATE 0x01
446#define ABD_STATE 0x02
447
43779f8d 448/* OCP_ADC_CFG */
449#define CKADSEL_L 0x0100
450#define ADC_EN 0x0080
451#define EN_EMI_L 0x0040
452
453/* SRAM_LPF_CFG */
454#define LPF_AUTO_TUNE 0x8000
455
456/* SRAM_10M_AMP1 */
457#define GDAC_IB_UPALL 0x0008
458
459/* SRAM_10M_AMP2 */
460#define AMP_DN 0x0200
461
462/* SRAM_IMPEDANCE */
463#define RX_DRIVING_MASK 0x6000
464
34ee32c9
ML
465/* MAC PASSTHRU */
466#define AD_MASK 0xfee0
467#define EFUSE 0xcfdb
468#define PASS_THRU_MASK 0x1
469
ac718b69 470enum rtl_register_content {
43779f8d 471 _1000bps = 0x10,
ac718b69 472 _100bps = 0x08,
473 _10bps = 0x04,
474 LINK_STATUS = 0x02,
475 FULL_DUP = 0x01,
476};
477
1764bcd9 478#define RTL8152_MAX_TX 4
ebc2ec48 479#define RTL8152_MAX_RX 10
40a82917 480#define INTBUFSIZE 2
8e1f51bd 481#define CRC_SIZE 4
482#define TX_ALIGN 4
483#define RX_ALIGN 8
40a82917 484
485#define INTR_LINK 0x0004
ebc2ec48 486
ac718b69 487#define RTL8152_REQT_READ 0xc0
488#define RTL8152_REQT_WRITE 0x40
489#define RTL8152_REQ_GET_REGS 0x05
490#define RTL8152_REQ_SET_REGS 0x05
491
492#define BYTE_EN_DWORD 0xff
493#define BYTE_EN_WORD 0x33
494#define BYTE_EN_BYTE 0x11
495#define BYTE_EN_SIX_BYTES 0x3f
496#define BYTE_EN_START_MASK 0x0f
497#define BYTE_EN_END_MASK 0xf0
498
69b4b7a4 499#define RTL8153_MAX_PACKET 9216 /* 9K */
500#define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN)
ac718b69 501#define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
69b4b7a4 502#define RTL8153_RMS RTL8153_MAX_PACKET
b8125404 503#define RTL8152_TX_TIMEOUT (5 * HZ)
d823ab68 504#define RTL8152_NAPI_WEIGHT 64
b20cb60e 505#define rx_reserved_size(x) ((x) + VLAN_ETH_HLEN + CRC_SIZE + \
506 sizeof(struct rx_desc) + RX_ALIGN)
ac718b69 507
508/* rtl8152 flags */
509enum rtl8152_flags {
510 RTL8152_UNPLUG = 0,
ac718b69 511 RTL8152_SET_RX_MODE,
40a82917 512 WORK_ENABLE,
513 RTL8152_LINK_CHG,
9a4be1bd 514 SELECTIVE_SUSPEND,
aa66a5f1 515 PHY_RESET,
d823ab68 516 SCHEDULE_NAPI,
ac718b69 517};
518
519/* Define these values to match your device */
520#define VENDOR_ID_REALTEK 0x0bda
d5b07ccc 521#define VENDOR_ID_MICROSOFT 0x045e
43779f8d 522#define VENDOR_ID_SAMSUNG 0x04e8
347eec34 523#define VENDOR_ID_LENOVO 0x17ef
d065c3c1 524#define VENDOR_ID_NVIDIA 0x0955
ac718b69 525
526#define MCU_TYPE_PLA 0x0100
527#define MCU_TYPE_USB 0x0000
528
4f1d4d54 529struct tally_counter {
530 __le64 tx_packets;
531 __le64 rx_packets;
532 __le64 tx_errors;
533 __le32 rx_errors;
534 __le16 rx_missed;
535 __le16 align_errors;
536 __le32 tx_one_collision;
537 __le32 tx_multi_collision;
538 __le64 rx_unicast;
539 __le64 rx_broadcast;
540 __le32 rx_multicast;
541 __le16 tx_aborted;
f37119c5 542 __le16 tx_underrun;
4f1d4d54 543};
544
ac718b69 545struct rx_desc {
500b6d7e 546 __le32 opts1;
ac718b69 547#define RX_LEN_MASK 0x7fff
565cab0a 548
500b6d7e 549 __le32 opts2;
f5aaaa6d 550#define RD_UDP_CS BIT(23)
551#define RD_TCP_CS BIT(22)
552#define RD_IPV6_CS BIT(20)
553#define RD_IPV4_CS BIT(19)
565cab0a 554
500b6d7e 555 __le32 opts3;
f5aaaa6d 556#define IPF BIT(23) /* IP checksum fail */
557#define UDPF BIT(22) /* UDP checksum fail */
558#define TCPF BIT(21) /* TCP checksum fail */
559#define RX_VLAN_TAG BIT(16)
565cab0a 560
500b6d7e 561 __le32 opts4;
562 __le32 opts5;
563 __le32 opts6;
ac718b69 564};
565
566struct tx_desc {
500b6d7e 567 __le32 opts1;
f5aaaa6d 568#define TX_FS BIT(31) /* First segment of a packet */
569#define TX_LS BIT(30) /* Final segment of a packet */
570#define GTSENDV4 BIT(28)
571#define GTSENDV6 BIT(27)
60c89071 572#define GTTCPHO_SHIFT 18
6128d1bb 573#define GTTCPHO_MAX 0x7fU
60c89071 574#define TX_LEN_MAX 0x3ffffU
5bd23881 575
500b6d7e 576 __le32 opts2;
f5aaaa6d 577#define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
578#define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
579#define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
580#define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
60c89071 581#define MSS_SHIFT 17
582#define MSS_MAX 0x7ffU
583#define TCPHO_SHIFT 17
6128d1bb 584#define TCPHO_MAX 0x7ffU
f5aaaa6d 585#define TX_VLAN_TAG BIT(16)
ac718b69 586};
587
dff4e8ad 588struct r8152;
589
ebc2ec48 590struct rx_agg {
591 struct list_head list;
592 struct urb *urb;
dff4e8ad 593 struct r8152 *context;
ebc2ec48 594 void *buffer;
595 void *head;
596};
597
598struct tx_agg {
599 struct list_head list;
600 struct urb *urb;
dff4e8ad 601 struct r8152 *context;
ebc2ec48 602 void *buffer;
603 void *head;
604 u32 skb_num;
605 u32 skb_len;
606};
607
ac718b69 608struct r8152 {
609 unsigned long flags;
610 struct usb_device *udev;
d823ab68 611 struct napi_struct napi;
40a82917 612 struct usb_interface *intf;
ac718b69 613 struct net_device *netdev;
40a82917 614 struct urb *intr_urb;
ebc2ec48 615 struct tx_agg tx_info[RTL8152_MAX_TX];
616 struct rx_agg rx_info[RTL8152_MAX_RX];
617 struct list_head rx_done, tx_free;
d823ab68 618 struct sk_buff_head tx_queue, rx_queue;
ebc2ec48 619 spinlock_t rx_lock, tx_lock;
a028a9e0 620 struct delayed_work schedule, hw_phy_work;
ac718b69 621 struct mii_if_info mii;
b5403273 622 struct mutex control; /* use for hw setting */
5ee3c60c 623#ifdef CONFIG_PM_SLEEP
624 struct notifier_block pm_notifier;
625#endif
c81229c9 626
627 struct rtl_ops {
628 void (*init)(struct r8152 *);
629 int (*enable)(struct r8152 *);
630 void (*disable)(struct r8152 *);
7e9da481 631 void (*up)(struct r8152 *);
c81229c9 632 void (*down)(struct r8152 *);
633 void (*unload)(struct r8152 *);
df35d283 634 int (*eee_get)(struct r8152 *, struct ethtool_eee *);
635 int (*eee_set)(struct r8152 *, struct ethtool_eee *);
2dd49e0f 636 bool (*in_nway)(struct r8152 *);
a028a9e0 637 void (*hw_phy_cfg)(struct r8152 *);
2609af19 638 void (*autosuspend_en)(struct r8152 *tp, bool enable);
c81229c9 639 } rtl_ops;
640
40a82917 641 int intr_interval;
21ff2e89 642 u32 saved_wolopts;
ac718b69 643 u32 msg_enable;
dd1b119c 644 u32 tx_qlen;
464ec10a 645 u32 coalesce;
ac718b69 646 u16 ocp_base;
aa7e26b6 647 u16 speed;
40a82917 648 u8 *intr_buff;
ac718b69 649 u8 version;
aa7e26b6 650 u8 duplex;
651 u8 autoneg;
ac718b69 652};
653
654enum rtl_version {
655 RTL_VER_UNKNOWN = 0,
656 RTL_VER_01,
43779f8d 657 RTL_VER_02,
658 RTL_VER_03,
659 RTL_VER_04,
660 RTL_VER_05,
fb02eb4a 661 RTL_VER_06,
43779f8d 662 RTL_VER_MAX
ac718b69 663};
664
60c89071 665enum tx_csum_stat {
666 TX_CSUM_SUCCESS = 0,
667 TX_CSUM_TSO,
668 TX_CSUM_NONE
669};
670
ac718b69 671/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
672 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
673 */
674static const int multicast_filter_limit = 32;
52aec126 675static unsigned int agg_buf_sz = 16384;
ac718b69 676
52aec126 677#define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \
60c89071 678 VLAN_ETH_HLEN - VLAN_HLEN)
679
ac718b69 680static
681int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
682{
31787f53 683 int ret;
684 void *tmp;
685
686 tmp = kmalloc(size, GFP_KERNEL);
687 if (!tmp)
688 return -ENOMEM;
689
690 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
b209af99 691 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
692 value, index, tmp, size, 500);
31787f53 693
694 memcpy(data, tmp, size);
695 kfree(tmp);
696
697 return ret;
ac718b69 698}
699
700static
701int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
702{
31787f53 703 int ret;
704 void *tmp;
705
c4438f03 706 tmp = kmemdup(data, size, GFP_KERNEL);
31787f53 707 if (!tmp)
708 return -ENOMEM;
709
31787f53 710 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
b209af99 711 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
712 value, index, tmp, size, 500);
31787f53 713
714 kfree(tmp);
db8515ef 715
31787f53 716 return ret;
ac718b69 717}
718
719static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
b209af99 720 void *data, u16 type)
ac718b69 721{
45f4a19f 722 u16 limit = 64;
723 int ret = 0;
ac718b69 724
725 if (test_bit(RTL8152_UNPLUG, &tp->flags))
726 return -ENODEV;
727
728 /* both size and indix must be 4 bytes align */
729 if ((size & 3) || !size || (index & 3) || !data)
730 return -EPERM;
731
732 if ((u32)index + (u32)size > 0xffff)
733 return -EPERM;
734
735 while (size) {
736 if (size > limit) {
737 ret = get_registers(tp, index, type, limit, data);
738 if (ret < 0)
739 break;
740
741 index += limit;
742 data += limit;
743 size -= limit;
744 } else {
745 ret = get_registers(tp, index, type, size, data);
746 if (ret < 0)
747 break;
748
749 index += size;
750 data += size;
751 size = 0;
752 break;
753 }
754 }
755
67610496 756 if (ret == -ENODEV)
757 set_bit(RTL8152_UNPLUG, &tp->flags);
758
ac718b69 759 return ret;
760}
761
762static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
b209af99 763 u16 size, void *data, u16 type)
ac718b69 764{
45f4a19f 765 int ret;
766 u16 byteen_start, byteen_end, byen;
767 u16 limit = 512;
ac718b69 768
769 if (test_bit(RTL8152_UNPLUG, &tp->flags))
770 return -ENODEV;
771
772 /* both size and indix must be 4 bytes align */
773 if ((size & 3) || !size || (index & 3) || !data)
774 return -EPERM;
775
776 if ((u32)index + (u32)size > 0xffff)
777 return -EPERM;
778
779 byteen_start = byteen & BYTE_EN_START_MASK;
780 byteen_end = byteen & BYTE_EN_END_MASK;
781
782 byen = byteen_start | (byteen_start << 4);
783 ret = set_registers(tp, index, type | byen, 4, data);
784 if (ret < 0)
785 goto error1;
786
787 index += 4;
788 data += 4;
789 size -= 4;
790
791 if (size) {
792 size -= 4;
793
794 while (size) {
795 if (size > limit) {
796 ret = set_registers(tp, index,
b209af99 797 type | BYTE_EN_DWORD,
798 limit, data);
ac718b69 799 if (ret < 0)
800 goto error1;
801
802 index += limit;
803 data += limit;
804 size -= limit;
805 } else {
806 ret = set_registers(tp, index,
b209af99 807 type | BYTE_EN_DWORD,
808 size, data);
ac718b69 809 if (ret < 0)
810 goto error1;
811
812 index += size;
813 data += size;
814 size = 0;
815 break;
816 }
817 }
818
819 byen = byteen_end | (byteen_end >> 4);
820 ret = set_registers(tp, index, type | byen, 4, data);
821 if (ret < 0)
822 goto error1;
823 }
824
825error1:
67610496 826 if (ret == -ENODEV)
827 set_bit(RTL8152_UNPLUG, &tp->flags);
828
ac718b69 829 return ret;
830}
831
832static inline
833int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
834{
835 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
836}
837
838static inline
839int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
840{
841 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
842}
843
ac718b69 844static inline
845int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
846{
847 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
848}
849
850static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
851{
c8826de8 852 __le32 data;
ac718b69 853
c8826de8 854 generic_ocp_read(tp, index, sizeof(data), &data, type);
ac718b69 855
856 return __le32_to_cpu(data);
857}
858
859static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
860{
c8826de8 861 __le32 tmp = __cpu_to_le32(data);
862
863 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
ac718b69 864}
865
866static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
867{
868 u32 data;
c8826de8 869 __le32 tmp;
ac718b69 870 u8 shift = index & 2;
871
872 index &= ~3;
873
c8826de8 874 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
ac718b69 875
c8826de8 876 data = __le32_to_cpu(tmp);
ac718b69 877 data >>= (shift * 8);
878 data &= 0xffff;
879
880 return (u16)data;
881}
882
883static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
884{
c8826de8 885 u32 mask = 0xffff;
886 __le32 tmp;
ac718b69 887 u16 byen = BYTE_EN_WORD;
888 u8 shift = index & 2;
889
890 data &= mask;
891
892 if (index & 2) {
893 byen <<= shift;
894 mask <<= (shift * 8);
895 data <<= (shift * 8);
896 index &= ~3;
897 }
898
c8826de8 899 tmp = __cpu_to_le32(data);
ac718b69 900
c8826de8 901 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
ac718b69 902}
903
904static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
905{
906 u32 data;
c8826de8 907 __le32 tmp;
ac718b69 908 u8 shift = index & 3;
909
910 index &= ~3;
911
c8826de8 912 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
ac718b69 913
c8826de8 914 data = __le32_to_cpu(tmp);
ac718b69 915 data >>= (shift * 8);
916 data &= 0xff;
917
918 return (u8)data;
919}
920
921static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
922{
c8826de8 923 u32 mask = 0xff;
924 __le32 tmp;
ac718b69 925 u16 byen = BYTE_EN_BYTE;
926 u8 shift = index & 3;
927
928 data &= mask;
929
930 if (index & 3) {
931 byen <<= shift;
932 mask <<= (shift * 8);
933 data <<= (shift * 8);
934 index &= ~3;
935 }
936
c8826de8 937 tmp = __cpu_to_le32(data);
ac718b69 938
c8826de8 939 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
ac718b69 940}
941
ac244d3e 942static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
e3fe0b1a 943{
944 u16 ocp_base, ocp_index;
945
946 ocp_base = addr & 0xf000;
947 if (ocp_base != tp->ocp_base) {
948 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
949 tp->ocp_base = ocp_base;
950 }
951
952 ocp_index = (addr & 0x0fff) | 0xb000;
ac244d3e 953 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
e3fe0b1a 954}
955
ac244d3e 956static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
ac718b69 957{
ac244d3e 958 u16 ocp_base, ocp_index;
ac718b69 959
ac244d3e 960 ocp_base = addr & 0xf000;
961 if (ocp_base != tp->ocp_base) {
962 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
963 tp->ocp_base = ocp_base;
ac718b69 964 }
ac244d3e 965
966 ocp_index = (addr & 0x0fff) | 0xb000;
967 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
ac718b69 968}
969
ac244d3e 970static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
ac718b69 971{
ac244d3e 972 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
973}
ac718b69 974
ac244d3e 975static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
976{
977 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
ac718b69 978}
979
43779f8d 980static void sram_write(struct r8152 *tp, u16 addr, u16 data)
981{
982 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
983 ocp_reg_write(tp, OCP_SRAM_DATA, data);
984}
985
ac718b69 986static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
987{
988 struct r8152 *tp = netdev_priv(netdev);
9a4be1bd 989 int ret;
ac718b69 990
6871438c 991 if (test_bit(RTL8152_UNPLUG, &tp->flags))
992 return -ENODEV;
993
ac718b69 994 if (phy_id != R8152_PHY_ID)
995 return -EINVAL;
996
9a4be1bd 997 ret = r8152_mdio_read(tp, reg);
998
9a4be1bd 999 return ret;
ac718b69 1000}
1001
1002static
1003void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
1004{
1005 struct r8152 *tp = netdev_priv(netdev);
1006
6871438c 1007 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1008 return;
1009
ac718b69 1010 if (phy_id != R8152_PHY_ID)
1011 return;
1012
1013 r8152_mdio_write(tp, reg, val);
1014}
1015
b209af99 1016static int
1017r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
ebc2ec48 1018
8ba789ab 1019static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
1020{
1021 struct r8152 *tp = netdev_priv(netdev);
1022 struct sockaddr *addr = p;
ea6a7112 1023 int ret = -EADDRNOTAVAIL;
8ba789ab 1024
1025 if (!is_valid_ether_addr(addr->sa_data))
ea6a7112 1026 goto out1;
1027
1028 ret = usb_autopm_get_interface(tp->intf);
1029 if (ret < 0)
1030 goto out1;
8ba789ab 1031
b5403273 1032 mutex_lock(&tp->control);
1033
8ba789ab 1034 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1035
1036 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1037 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1038 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1039
b5403273 1040 mutex_unlock(&tp->control);
1041
ea6a7112 1042 usb_autopm_put_interface(tp->intf);
1043out1:
1044 return ret;
8ba789ab 1045}
1046
34ee32c9
ML
1047/* Devices containing RTL8153-AD can support a persistent
1048 * host system provided MAC address.
1049 * Examples of this are Dell TB15 and Dell WD15 docks
1050 */
1051static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa)
1052{
1053 acpi_status status;
1054 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
1055 union acpi_object *obj;
1056 int ret = -EINVAL;
1057 u32 ocp_data;
1058 unsigned char buf[6];
1059
1060 /* test for -AD variant of RTL8153 */
1061 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
1062 if ((ocp_data & AD_MASK) != 0x1000)
1063 return -ENODEV;
1064
1065 /* test for MAC address pass-through bit */
1066 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);
1067 if ((ocp_data & PASS_THRU_MASK) != 1)
1068 return -ENODEV;
1069
1070 /* returns _AUXMAC_#AABBCCDDEEFF# */
1071 status = acpi_evaluate_object(NULL, "\\_SB.AMAC", NULL, &buffer);
1072 obj = (union acpi_object *)buffer.pointer;
1073 if (!ACPI_SUCCESS(status))
1074 return -ENODEV;
1075 if (obj->type != ACPI_TYPE_BUFFER || obj->string.length != 0x17) {
1076 netif_warn(tp, probe, tp->netdev,
53700f0c 1077 "Invalid buffer for pass-thru MAC addr: (%d, %d)\n",
34ee32c9
ML
1078 obj->type, obj->string.length);
1079 goto amacout;
1080 }
1081 if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||
1082 strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {
1083 netif_warn(tp, probe, tp->netdev,
1084 "Invalid header when reading pass-thru MAC addr\n");
1085 goto amacout;
1086 }
1087 ret = hex2bin(buf, obj->string.pointer + 9, 6);
1088 if (!(ret == 0 && is_valid_ether_addr(buf))) {
1089 netif_warn(tp, probe, tp->netdev,
53700f0c 1090 "Invalid MAC for pass-thru MAC addr: %d, %pM\n",
1091 ret, buf);
34ee32c9
ML
1092 ret = -EINVAL;
1093 goto amacout;
1094 }
1095 memcpy(sa->sa_data, buf, 6);
1096 ether_addr_copy(tp->netdev->dev_addr, sa->sa_data);
1097 netif_info(tp, probe, tp->netdev,
1098 "Using pass-thru MAC addr %pM\n", sa->sa_data);
1099
1100amacout:
1101 kfree(obj);
1102 return ret;
1103}
1104
179bb6d7 1105static int set_ethernet_addr(struct r8152 *tp)
ac718b69 1106{
1107 struct net_device *dev = tp->netdev;
179bb6d7 1108 struct sockaddr sa;
8a91c824 1109 int ret;
ac718b69 1110
53700f0c 1111 if (tp->version == RTL_VER_01) {
179bb6d7 1112 ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data);
53700f0c 1113 } else {
34ee32c9
ML
1114 /* if this is not an RTL8153-AD, no eFuse mac pass thru set,
1115 * or system doesn't provide valid _SB.AMAC this will be
1116 * be expected to non-zero
1117 */
1118 ret = vendor_mac_passthru_addr_read(tp, &sa);
1119 if (ret < 0)
1120 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data);
1121 }
8a91c824 1122
1123 if (ret < 0) {
179bb6d7 1124 netif_err(tp, probe, dev, "Get ether addr fail\n");
1125 } else if (!is_valid_ether_addr(sa.sa_data)) {
1126 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1127 sa.sa_data);
1128 eth_hw_addr_random(dev);
1129 ether_addr_copy(sa.sa_data, dev->dev_addr);
1130 ret = rtl8152_set_mac_address(dev, &sa);
1131 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1132 sa.sa_data);
8a91c824 1133 } else {
179bb6d7 1134 if (tp->version == RTL_VER_01)
1135 ether_addr_copy(dev->dev_addr, sa.sa_data);
1136 else
1137 ret = rtl8152_set_mac_address(dev, &sa);
ac718b69 1138 }
179bb6d7 1139
1140 return ret;
ac718b69 1141}
1142
ac718b69 1143static void read_bulk_callback(struct urb *urb)
1144{
ac718b69 1145 struct net_device *netdev;
ac718b69 1146 int status = urb->status;
ebc2ec48 1147 struct rx_agg *agg;
1148 struct r8152 *tp;
ac718b69 1149
ebc2ec48 1150 agg = urb->context;
1151 if (!agg)
1152 return;
1153
1154 tp = agg->context;
ac718b69 1155 if (!tp)
1156 return;
ebc2ec48 1157
ac718b69 1158 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1159 return;
ebc2ec48 1160
1161 if (!test_bit(WORK_ENABLE, &tp->flags))
1162 return;
1163
ac718b69 1164 netdev = tp->netdev;
7559fb2f 1165
1166 /* When link down, the driver would cancel all bulks. */
1167 /* This avoid the re-submitting bulk */
ebc2ec48 1168 if (!netif_carrier_ok(netdev))
ac718b69 1169 return;
1170
9a4be1bd 1171 usb_mark_last_busy(tp->udev);
1172
ac718b69 1173 switch (status) {
1174 case 0:
ebc2ec48 1175 if (urb->actual_length < ETH_ZLEN)
1176 break;
1177
2685d410 1178 spin_lock(&tp->rx_lock);
ebc2ec48 1179 list_add_tail(&agg->list, &tp->rx_done);
2685d410 1180 spin_unlock(&tp->rx_lock);
d823ab68 1181 napi_schedule(&tp->napi);
ebc2ec48 1182 return;
ac718b69 1183 case -ESHUTDOWN:
1184 set_bit(RTL8152_UNPLUG, &tp->flags);
1185 netif_device_detach(tp->netdev);
ebc2ec48 1186 return;
ac718b69 1187 case -ENOENT:
1188 return; /* the urb is in unlink state */
1189 case -ETIME:
4a8deae2
HW
1190 if (net_ratelimit())
1191 netdev_warn(netdev, "maybe reset is needed?\n");
ebc2ec48 1192 break;
ac718b69 1193 default:
4a8deae2
HW
1194 if (net_ratelimit())
1195 netdev_warn(netdev, "Rx status %d\n", status);
ebc2ec48 1196 break;
ac718b69 1197 }
1198
a0fccd48 1199 r8152_submit_rx(tp, agg, GFP_ATOMIC);
ac718b69 1200}
1201
ebc2ec48 1202static void write_bulk_callback(struct urb *urb)
ac718b69 1203{
ebc2ec48 1204 struct net_device_stats *stats;
d104eafa 1205 struct net_device *netdev;
ebc2ec48 1206 struct tx_agg *agg;
ac718b69 1207 struct r8152 *tp;
ebc2ec48 1208 int status = urb->status;
ac718b69 1209
ebc2ec48 1210 agg = urb->context;
1211 if (!agg)
ac718b69 1212 return;
1213
ebc2ec48 1214 tp = agg->context;
1215 if (!tp)
1216 return;
1217
d104eafa 1218 netdev = tp->netdev;
05e0f1aa 1219 stats = &netdev->stats;
ebc2ec48 1220 if (status) {
4a8deae2 1221 if (net_ratelimit())
d104eafa 1222 netdev_warn(netdev, "Tx status %d\n", status);
ebc2ec48 1223 stats->tx_errors += agg->skb_num;
ac718b69 1224 } else {
ebc2ec48 1225 stats->tx_packets += agg->skb_num;
1226 stats->tx_bytes += agg->skb_len;
ac718b69 1227 }
1228
2685d410 1229 spin_lock(&tp->tx_lock);
ebc2ec48 1230 list_add_tail(&agg->list, &tp->tx_free);
2685d410 1231 spin_unlock(&tp->tx_lock);
ebc2ec48 1232
9a4be1bd 1233 usb_autopm_put_interface_async(tp->intf);
1234
d104eafa 1235 if (!netif_carrier_ok(netdev))
ebc2ec48 1236 return;
1237
1238 if (!test_bit(WORK_ENABLE, &tp->flags))
1239 return;
1240
1241 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1242 return;
1243
1244 if (!skb_queue_empty(&tp->tx_queue))
d823ab68 1245 napi_schedule(&tp->napi);
ac718b69 1246}
1247
40a82917 1248static void intr_callback(struct urb *urb)
1249{
1250 struct r8152 *tp;
500b6d7e 1251 __le16 *d;
40a82917 1252 int status = urb->status;
1253 int res;
1254
1255 tp = urb->context;
1256 if (!tp)
1257 return;
1258
1259 if (!test_bit(WORK_ENABLE, &tp->flags))
1260 return;
1261
1262 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1263 return;
1264
1265 switch (status) {
1266 case 0: /* success */
1267 break;
1268 case -ECONNRESET: /* unlink */
1269 case -ESHUTDOWN:
1270 netif_device_detach(tp->netdev);
1271 case -ENOENT:
d59c876d 1272 case -EPROTO:
1273 netif_info(tp, intr, tp->netdev,
1274 "Stop submitting intr, status %d\n", status);
40a82917 1275 return;
1276 case -EOVERFLOW:
1277 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1278 goto resubmit;
1279 /* -EPIPE: should clear the halt */
1280 default:
1281 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1282 goto resubmit;
1283 }
1284
1285 d = urb->transfer_buffer;
1286 if (INTR_LINK & __le16_to_cpu(d[0])) {
51d979fa 1287 if (!netif_carrier_ok(tp->netdev)) {
40a82917 1288 set_bit(RTL8152_LINK_CHG, &tp->flags);
1289 schedule_delayed_work(&tp->schedule, 0);
1290 }
1291 } else {
51d979fa 1292 if (netif_carrier_ok(tp->netdev)) {
2f25abe6 1293 netif_stop_queue(tp->netdev);
40a82917 1294 set_bit(RTL8152_LINK_CHG, &tp->flags);
1295 schedule_delayed_work(&tp->schedule, 0);
1296 }
1297 }
1298
1299resubmit:
1300 res = usb_submit_urb(urb, GFP_ATOMIC);
67610496 1301 if (res == -ENODEV) {
1302 set_bit(RTL8152_UNPLUG, &tp->flags);
40a82917 1303 netif_device_detach(tp->netdev);
67610496 1304 } else if (res) {
40a82917 1305 netif_err(tp, intr, tp->netdev,
4a8deae2 1306 "can't resubmit intr, status %d\n", res);
67610496 1307 }
40a82917 1308}
1309
ebc2ec48 1310static inline void *rx_agg_align(void *data)
1311{
8e1f51bd 1312 return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
ebc2ec48 1313}
1314
1315static inline void *tx_agg_align(void *data)
1316{
8e1f51bd 1317 return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
ebc2ec48 1318}
1319
1320static void free_all_mem(struct r8152 *tp)
1321{
1322 int i;
1323
1324 for (i = 0; i < RTL8152_MAX_RX; i++) {
9629e3c0 1325 usb_free_urb(tp->rx_info[i].urb);
1326 tp->rx_info[i].urb = NULL;
ebc2ec48 1327
9629e3c0 1328 kfree(tp->rx_info[i].buffer);
1329 tp->rx_info[i].buffer = NULL;
1330 tp->rx_info[i].head = NULL;
ebc2ec48 1331 }
1332
1333 for (i = 0; i < RTL8152_MAX_TX; i++) {
9629e3c0 1334 usb_free_urb(tp->tx_info[i].urb);
1335 tp->tx_info[i].urb = NULL;
ebc2ec48 1336
9629e3c0 1337 kfree(tp->tx_info[i].buffer);
1338 tp->tx_info[i].buffer = NULL;
1339 tp->tx_info[i].head = NULL;
ebc2ec48 1340 }
40a82917 1341
9629e3c0 1342 usb_free_urb(tp->intr_urb);
1343 tp->intr_urb = NULL;
40a82917 1344
9629e3c0 1345 kfree(tp->intr_buff);
1346 tp->intr_buff = NULL;
ebc2ec48 1347}
1348
1349static int alloc_all_mem(struct r8152 *tp)
1350{
1351 struct net_device *netdev = tp->netdev;
40a82917 1352 struct usb_interface *intf = tp->intf;
1353 struct usb_host_interface *alt = intf->cur_altsetting;
1354 struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
ebc2ec48 1355 struct urb *urb;
1356 int node, i;
1357 u8 *buf;
1358
1359 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1360
1361 spin_lock_init(&tp->rx_lock);
1362 spin_lock_init(&tp->tx_lock);
ebc2ec48 1363 INIT_LIST_HEAD(&tp->tx_free);
98d068ab 1364 INIT_LIST_HEAD(&tp->rx_done);
ebc2ec48 1365 skb_queue_head_init(&tp->tx_queue);
d823ab68 1366 skb_queue_head_init(&tp->rx_queue);
ebc2ec48 1367
1368 for (i = 0; i < RTL8152_MAX_RX; i++) {
52aec126 1369 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
ebc2ec48 1370 if (!buf)
1371 goto err1;
1372
1373 if (buf != rx_agg_align(buf)) {
1374 kfree(buf);
52aec126 1375 buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL,
8e1f51bd 1376 node);
ebc2ec48 1377 if (!buf)
1378 goto err1;
1379 }
1380
1381 urb = usb_alloc_urb(0, GFP_KERNEL);
1382 if (!urb) {
1383 kfree(buf);
1384 goto err1;
1385 }
1386
1387 INIT_LIST_HEAD(&tp->rx_info[i].list);
1388 tp->rx_info[i].context = tp;
1389 tp->rx_info[i].urb = urb;
1390 tp->rx_info[i].buffer = buf;
1391 tp->rx_info[i].head = rx_agg_align(buf);
1392 }
1393
1394 for (i = 0; i < RTL8152_MAX_TX; i++) {
52aec126 1395 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
ebc2ec48 1396 if (!buf)
1397 goto err1;
1398
1399 if (buf != tx_agg_align(buf)) {
1400 kfree(buf);
52aec126 1401 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
8e1f51bd 1402 node);
ebc2ec48 1403 if (!buf)
1404 goto err1;
1405 }
1406
1407 urb = usb_alloc_urb(0, GFP_KERNEL);
1408 if (!urb) {
1409 kfree(buf);
1410 goto err1;
1411 }
1412
1413 INIT_LIST_HEAD(&tp->tx_info[i].list);
1414 tp->tx_info[i].context = tp;
1415 tp->tx_info[i].urb = urb;
1416 tp->tx_info[i].buffer = buf;
1417 tp->tx_info[i].head = tx_agg_align(buf);
1418
1419 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1420 }
1421
40a82917 1422 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1423 if (!tp->intr_urb)
1424 goto err1;
1425
1426 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1427 if (!tp->intr_buff)
1428 goto err1;
1429
1430 tp->intr_interval = (int)ep_intr->desc.bInterval;
1431 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
b209af99 1432 tp->intr_buff, INTBUFSIZE, intr_callback,
1433 tp, tp->intr_interval);
40a82917 1434
ebc2ec48 1435 return 0;
1436
1437err1:
1438 free_all_mem(tp);
1439 return -ENOMEM;
1440}
1441
0de98f6c 1442static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1443{
1444 struct tx_agg *agg = NULL;
1445 unsigned long flags;
1446
21949ab7 1447 if (list_empty(&tp->tx_free))
1448 return NULL;
1449
0de98f6c 1450 spin_lock_irqsave(&tp->tx_lock, flags);
1451 if (!list_empty(&tp->tx_free)) {
1452 struct list_head *cursor;
1453
1454 cursor = tp->tx_free.next;
1455 list_del_init(cursor);
1456 agg = list_entry(cursor, struct tx_agg, list);
1457 }
1458 spin_unlock_irqrestore(&tp->tx_lock, flags);
1459
1460 return agg;
1461}
1462
b209af99 1463/* r8152_csum_workaround()
6128d1bb 1464 * The hw limites the value the transport offset. When the offset is out of the
1465 * range, calculate the checksum by sw.
1466 */
1467static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1468 struct sk_buff_head *list)
1469{
1470 if (skb_shinfo(skb)->gso_size) {
1471 netdev_features_t features = tp->netdev->features;
1472 struct sk_buff_head seg_list;
1473 struct sk_buff *segs, *nskb;
1474
a91d45f1 1475 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6128d1bb 1476 segs = skb_gso_segment(skb, features);
1477 if (IS_ERR(segs) || !segs)
1478 goto drop;
1479
1480 __skb_queue_head_init(&seg_list);
1481
1482 do {
1483 nskb = segs;
1484 segs = segs->next;
1485 nskb->next = NULL;
1486 __skb_queue_tail(&seg_list, nskb);
1487 } while (segs);
1488
1489 skb_queue_splice(&seg_list, list);
1490 dev_kfree_skb(skb);
1491 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1492 if (skb_checksum_help(skb) < 0)
1493 goto drop;
1494
1495 __skb_queue_head(list, skb);
1496 } else {
1497 struct net_device_stats *stats;
1498
1499drop:
1500 stats = &tp->netdev->stats;
1501 stats->tx_dropped++;
1502 dev_kfree_skb(skb);
1503 }
1504}
1505
b209af99 1506/* msdn_giant_send_check()
6128d1bb 1507 * According to the document of microsoft, the TCP Pseudo Header excludes the
1508 * packet length for IPv6 TCP large packets.
1509 */
1510static int msdn_giant_send_check(struct sk_buff *skb)
1511{
1512 const struct ipv6hdr *ipv6h;
1513 struct tcphdr *th;
fcb308d5 1514 int ret;
1515
1516 ret = skb_cow_head(skb, 0);
1517 if (ret)
1518 return ret;
6128d1bb 1519
1520 ipv6h = ipv6_hdr(skb);
1521 th = tcp_hdr(skb);
1522
1523 th->check = 0;
1524 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
1525
fcb308d5 1526 return ret;
6128d1bb 1527}
1528
c5554298 1529static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1530{
df8a39de 1531 if (skb_vlan_tag_present(skb)) {
c5554298 1532 u32 opts2;
1533
df8a39de 1534 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
c5554298 1535 desc->opts2 |= cpu_to_le32(opts2);
1536 }
1537}
1538
1539static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1540{
1541 u32 opts2 = le32_to_cpu(desc->opts2);
1542
1543 if (opts2 & RX_VLAN_TAG)
1544 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1545 swab16(opts2 & 0xffff));
1546}
1547
60c89071 1548static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1549 struct sk_buff *skb, u32 len, u32 transport_offset)
1550{
1551 u32 mss = skb_shinfo(skb)->gso_size;
1552 u32 opts1, opts2 = 0;
1553 int ret = TX_CSUM_SUCCESS;
1554
1555 WARN_ON_ONCE(len > TX_LEN_MAX);
1556
1557 opts1 = len | TX_FS | TX_LS;
1558
1559 if (mss) {
6128d1bb 1560 if (transport_offset > GTTCPHO_MAX) {
1561 netif_warn(tp, tx_err, tp->netdev,
1562 "Invalid transport offset 0x%x for TSO\n",
1563 transport_offset);
1564 ret = TX_CSUM_TSO;
1565 goto unavailable;
1566 }
1567
6e74d174 1568 switch (vlan_get_protocol(skb)) {
60c89071 1569 case htons(ETH_P_IP):
1570 opts1 |= GTSENDV4;
1571 break;
1572
6128d1bb 1573 case htons(ETH_P_IPV6):
fcb308d5 1574 if (msdn_giant_send_check(skb)) {
1575 ret = TX_CSUM_TSO;
1576 goto unavailable;
1577 }
6128d1bb 1578 opts1 |= GTSENDV6;
6128d1bb 1579 break;
1580
60c89071 1581 default:
1582 WARN_ON_ONCE(1);
1583 break;
1584 }
1585
1586 opts1 |= transport_offset << GTTCPHO_SHIFT;
1587 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
1588 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1589 u8 ip_protocol;
5bd23881 1590
6128d1bb 1591 if (transport_offset > TCPHO_MAX) {
1592 netif_warn(tp, tx_err, tp->netdev,
1593 "Invalid transport offset 0x%x\n",
1594 transport_offset);
1595 ret = TX_CSUM_NONE;
1596 goto unavailable;
1597 }
1598
6e74d174 1599 switch (vlan_get_protocol(skb)) {
5bd23881 1600 case htons(ETH_P_IP):
1601 opts2 |= IPV4_CS;
1602 ip_protocol = ip_hdr(skb)->protocol;
1603 break;
1604
1605 case htons(ETH_P_IPV6):
1606 opts2 |= IPV6_CS;
1607 ip_protocol = ipv6_hdr(skb)->nexthdr;
1608 break;
1609
1610 default:
1611 ip_protocol = IPPROTO_RAW;
1612 break;
1613 }
1614
60c89071 1615 if (ip_protocol == IPPROTO_TCP)
5bd23881 1616 opts2 |= TCP_CS;
60c89071 1617 else if (ip_protocol == IPPROTO_UDP)
5bd23881 1618 opts2 |= UDP_CS;
60c89071 1619 else
5bd23881 1620 WARN_ON_ONCE(1);
5bd23881 1621
60c89071 1622 opts2 |= transport_offset << TCPHO_SHIFT;
5bd23881 1623 }
60c89071 1624
1625 desc->opts2 = cpu_to_le32(opts2);
1626 desc->opts1 = cpu_to_le32(opts1);
1627
6128d1bb 1628unavailable:
60c89071 1629 return ret;
5bd23881 1630}
1631
b1379d9a 1632static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
1633{
d84130a1 1634 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
9a4be1bd 1635 int remain, ret;
b1379d9a 1636 u8 *tx_data;
1637
d84130a1 1638 __skb_queue_head_init(&skb_head);
0c3121fc 1639 spin_lock(&tx_queue->lock);
d84130a1 1640 skb_queue_splice_init(tx_queue, &skb_head);
0c3121fc 1641 spin_unlock(&tx_queue->lock);
d84130a1 1642
b1379d9a 1643 tx_data = agg->head;
b209af99 1644 agg->skb_num = 0;
1645 agg->skb_len = 0;
52aec126 1646 remain = agg_buf_sz;
b1379d9a 1647
7937f9e5 1648 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
b1379d9a 1649 struct tx_desc *tx_desc;
1650 struct sk_buff *skb;
1651 unsigned int len;
60c89071 1652 u32 offset;
b1379d9a 1653
d84130a1 1654 skb = __skb_dequeue(&skb_head);
b1379d9a 1655 if (!skb)
1656 break;
1657
60c89071 1658 len = skb->len + sizeof(*tx_desc);
1659
1660 if (len > remain) {
d84130a1 1661 __skb_queue_head(&skb_head, skb);
b1379d9a 1662 break;
1663 }
1664
7937f9e5 1665 tx_data = tx_agg_align(tx_data);
b1379d9a 1666 tx_desc = (struct tx_desc *)tx_data;
60c89071 1667
1668 offset = (u32)skb_transport_offset(skb);
1669
6128d1bb 1670 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
1671 r8152_csum_workaround(tp, skb, &skb_head);
1672 continue;
1673 }
60c89071 1674
c5554298 1675 rtl_tx_vlan_tag(tx_desc, skb);
1676
b1379d9a 1677 tx_data += sizeof(*tx_desc);
1678
60c89071 1679 len = skb->len;
1680 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
1681 struct net_device_stats *stats = &tp->netdev->stats;
1682
1683 stats->tx_dropped++;
1684 dev_kfree_skb_any(skb);
1685 tx_data -= sizeof(*tx_desc);
1686 continue;
1687 }
1688
1689 tx_data += len;
b1379d9a 1690 agg->skb_len += len;
60c89071 1691 agg->skb_num++;
1692
b1379d9a 1693 dev_kfree_skb_any(skb);
1694
52aec126 1695 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
b1379d9a 1696 }
1697
d84130a1 1698 if (!skb_queue_empty(&skb_head)) {
0c3121fc 1699 spin_lock(&tx_queue->lock);
d84130a1 1700 skb_queue_splice(&skb_head, tx_queue);
0c3121fc 1701 spin_unlock(&tx_queue->lock);
d84130a1 1702 }
1703
0c3121fc 1704 netif_tx_lock(tp->netdev);
dd1b119c 1705
1706 if (netif_queue_stopped(tp->netdev) &&
1707 skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
1708 netif_wake_queue(tp->netdev);
1709
0c3121fc 1710 netif_tx_unlock(tp->netdev);
9a4be1bd 1711
0c3121fc 1712 ret = usb_autopm_get_interface_async(tp->intf);
9a4be1bd 1713 if (ret < 0)
1714 goto out_tx_fill;
dd1b119c 1715
b1379d9a 1716 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1717 agg->head, (int)(tx_data - (u8 *)agg->head),
1718 (usb_complete_t)write_bulk_callback, agg);
1719
0c3121fc 1720 ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
9a4be1bd 1721 if (ret < 0)
0c3121fc 1722 usb_autopm_put_interface_async(tp->intf);
9a4be1bd 1723
1724out_tx_fill:
1725 return ret;
b1379d9a 1726}
1727
565cab0a 1728static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
1729{
1730 u8 checksum = CHECKSUM_NONE;
1731 u32 opts2, opts3;
1732
19c0f40d 1733 if (!(tp->netdev->features & NETIF_F_RXCSUM))
565cab0a 1734 goto return_result;
1735
1736 opts2 = le32_to_cpu(rx_desc->opts2);
1737 opts3 = le32_to_cpu(rx_desc->opts3);
1738
1739 if (opts2 & RD_IPV4_CS) {
1740 if (opts3 & IPF)
1741 checksum = CHECKSUM_NONE;
1742 else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF))
1743 checksum = CHECKSUM_NONE;
1744 else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF))
1745 checksum = CHECKSUM_NONE;
1746 else
1747 checksum = CHECKSUM_UNNECESSARY;
b9a321b4 1748 } else if (opts2 & RD_IPV6_CS) {
6128d1bb 1749 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1750 checksum = CHECKSUM_UNNECESSARY;
1751 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1752 checksum = CHECKSUM_UNNECESSARY;
565cab0a 1753 }
1754
1755return_result:
1756 return checksum;
1757}
1758
d823ab68 1759static int rx_bottom(struct r8152 *tp, int budget)
ebc2ec48 1760{
a5a4f468 1761 unsigned long flags;
d84130a1 1762 struct list_head *cursor, *next, rx_queue;
e1a2ca92 1763 int ret = 0, work_done = 0;
ce594e98 1764 struct napi_struct *napi = &tp->napi;
d823ab68 1765
1766 if (!skb_queue_empty(&tp->rx_queue)) {
1767 while (work_done < budget) {
1768 struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
1769 struct net_device *netdev = tp->netdev;
1770 struct net_device_stats *stats = &netdev->stats;
1771 unsigned int pkt_len;
1772
1773 if (!skb)
1774 break;
1775
1776 pkt_len = skb->len;
ce594e98 1777 napi_gro_receive(napi, skb);
d823ab68 1778 work_done++;
1779 stats->rx_packets++;
1780 stats->rx_bytes += pkt_len;
1781 }
1782 }
ebc2ec48 1783
d84130a1 1784 if (list_empty(&tp->rx_done))
d823ab68 1785 goto out1;
d84130a1 1786
1787 INIT_LIST_HEAD(&rx_queue);
a5a4f468 1788 spin_lock_irqsave(&tp->rx_lock, flags);
d84130a1 1789 list_splice_init(&tp->rx_done, &rx_queue);
1790 spin_unlock_irqrestore(&tp->rx_lock, flags);
1791
1792 list_for_each_safe(cursor, next, &rx_queue) {
43a4478d 1793 struct rx_desc *rx_desc;
1794 struct rx_agg *agg;
43a4478d 1795 int len_used = 0;
1796 struct urb *urb;
1797 u8 *rx_data;
43a4478d 1798
ebc2ec48 1799 list_del_init(cursor);
ebc2ec48 1800
1801 agg = list_entry(cursor, struct rx_agg, list);
1802 urb = agg->urb;
0de98f6c 1803 if (urb->actual_length < ETH_ZLEN)
1804 goto submit;
ebc2ec48 1805
ebc2ec48 1806 rx_desc = agg->head;
1807 rx_data = agg->head;
7937f9e5 1808 len_used += sizeof(struct rx_desc);
ebc2ec48 1809
7937f9e5 1810 while (urb->actual_length > len_used) {
43a4478d 1811 struct net_device *netdev = tp->netdev;
05e0f1aa 1812 struct net_device_stats *stats = &netdev->stats;
7937f9e5 1813 unsigned int pkt_len;
43a4478d 1814 struct sk_buff *skb;
1815
74544458 1816 /* limite the skb numbers for rx_queue */
1817 if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000))
1818 break;
1819
7937f9e5 1820 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
ebc2ec48 1821 if (pkt_len < ETH_ZLEN)
1822 break;
1823
7937f9e5 1824 len_used += pkt_len;
1825 if (urb->actual_length < len_used)
1826 break;
1827
8e1f51bd 1828 pkt_len -= CRC_SIZE;
ebc2ec48 1829 rx_data += sizeof(struct rx_desc);
1830
ce594e98 1831 skb = napi_alloc_skb(napi, pkt_len);
ebc2ec48 1832 if (!skb) {
1833 stats->rx_dropped++;
5e2f7485 1834 goto find_next_rx;
ebc2ec48 1835 }
565cab0a 1836
1837 skb->ip_summed = r8152_rx_csum(tp, rx_desc);
ebc2ec48 1838 memcpy(skb->data, rx_data, pkt_len);
1839 skb_put(skb, pkt_len);
1840 skb->protocol = eth_type_trans(skb, netdev);
c5554298 1841 rtl_rx_vlan_tag(rx_desc, skb);
d823ab68 1842 if (work_done < budget) {
ce594e98 1843 napi_gro_receive(napi, skb);
d823ab68 1844 work_done++;
1845 stats->rx_packets++;
1846 stats->rx_bytes += pkt_len;
1847 } else {
1848 __skb_queue_tail(&tp->rx_queue, skb);
1849 }
ebc2ec48 1850
5e2f7485 1851find_next_rx:
8e1f51bd 1852 rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE);
ebc2ec48 1853 rx_desc = (struct rx_desc *)rx_data;
ebc2ec48 1854 len_used = (int)(rx_data - (u8 *)agg->head);
7937f9e5 1855 len_used += sizeof(struct rx_desc);
ebc2ec48 1856 }
1857
0de98f6c 1858submit:
e1a2ca92 1859 if (!ret) {
1860 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
1861 } else {
1862 urb->actual_length = 0;
1863 list_add_tail(&agg->list, next);
1864 }
1865 }
1866
1867 if (!list_empty(&rx_queue)) {
1868 spin_lock_irqsave(&tp->rx_lock, flags);
1869 list_splice_tail(&rx_queue, &tp->rx_done);
1870 spin_unlock_irqrestore(&tp->rx_lock, flags);
ebc2ec48 1871 }
d823ab68 1872
1873out1:
1874 return work_done;
ebc2ec48 1875}
1876
1877static void tx_bottom(struct r8152 *tp)
1878{
ebc2ec48 1879 int res;
1880
b1379d9a 1881 do {
1882 struct tx_agg *agg;
ebc2ec48 1883
b1379d9a 1884 if (skb_queue_empty(&tp->tx_queue))
ebc2ec48 1885 break;
1886
b1379d9a 1887 agg = r8152_get_tx_agg(tp);
1888 if (!agg)
ebc2ec48 1889 break;
ebc2ec48 1890
b1379d9a 1891 res = r8152_tx_agg_fill(tp, agg);
1892 if (res) {
05e0f1aa 1893 struct net_device *netdev = tp->netdev;
ebc2ec48 1894
b1379d9a 1895 if (res == -ENODEV) {
67610496 1896 set_bit(RTL8152_UNPLUG, &tp->flags);
b1379d9a 1897 netif_device_detach(netdev);
1898 } else {
05e0f1aa 1899 struct net_device_stats *stats = &netdev->stats;
1900 unsigned long flags;
1901
b1379d9a 1902 netif_warn(tp, tx_err, netdev,
1903 "failed tx_urb %d\n", res);
1904 stats->tx_dropped += agg->skb_num;
db8515ef 1905
b1379d9a 1906 spin_lock_irqsave(&tp->tx_lock, flags);
1907 list_add_tail(&agg->list, &tp->tx_free);
1908 spin_unlock_irqrestore(&tp->tx_lock, flags);
1909 }
ebc2ec48 1910 }
b1379d9a 1911 } while (res == 0);
ebc2ec48 1912}
1913
d823ab68 1914static void bottom_half(struct r8152 *tp)
ac718b69 1915{
ebc2ec48 1916 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1917 return;
1918
1919 if (!test_bit(WORK_ENABLE, &tp->flags))
ac718b69 1920 return;
ebc2ec48 1921
7559fb2f 1922 /* When link down, the driver would cancel all bulks. */
1923 /* This avoid the re-submitting bulk */
ebc2ec48 1924 if (!netif_carrier_ok(tp->netdev))
ac718b69 1925 return;
ebc2ec48 1926
d823ab68 1927 clear_bit(SCHEDULE_NAPI, &tp->flags);
9451a11c 1928
0c3121fc 1929 tx_bottom(tp);
ebc2ec48 1930}
1931
d823ab68 1932static int r8152_poll(struct napi_struct *napi, int budget)
1933{
1934 struct r8152 *tp = container_of(napi, struct r8152, napi);
1935 int work_done;
1936
1937 work_done = rx_bottom(tp, budget);
1938 bottom_half(tp);
1939
1940 if (work_done < budget) {
a3307f9b 1941 if (!napi_complete_done(napi, work_done))
1942 goto out;
d823ab68 1943 if (!list_empty(&tp->rx_done))
1944 napi_schedule(napi);
248b213a 1945 else if (!skb_queue_empty(&tp->tx_queue) &&
1946 !list_empty(&tp->tx_free))
1947 napi_schedule(napi);
d823ab68 1948 }
1949
a3307f9b 1950out:
d823ab68 1951 return work_done;
1952}
1953
ebc2ec48 1954static
1955int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
1956{
a0fccd48 1957 int ret;
1958
ef827a5b 1959 /* The rx would be stopped, so skip submitting */
1960 if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
1961 !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
1962 return 0;
1963
ebc2ec48 1964 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
52aec126 1965 agg->head, agg_buf_sz,
b209af99 1966 (usb_complete_t)read_bulk_callback, agg);
ebc2ec48 1967
a0fccd48 1968 ret = usb_submit_urb(agg->urb, mem_flags);
1969 if (ret == -ENODEV) {
1970 set_bit(RTL8152_UNPLUG, &tp->flags);
1971 netif_device_detach(tp->netdev);
1972 } else if (ret) {
1973 struct urb *urb = agg->urb;
1974 unsigned long flags;
1975
1976 urb->actual_length = 0;
1977 spin_lock_irqsave(&tp->rx_lock, flags);
1978 list_add_tail(&agg->list, &tp->rx_done);
1979 spin_unlock_irqrestore(&tp->rx_lock, flags);
d823ab68 1980
1981 netif_err(tp, rx_err, tp->netdev,
1982 "Couldn't submit rx[%p], ret = %d\n", agg, ret);
1983
1984 napi_schedule(&tp->napi);
a0fccd48 1985 }
1986
1987 return ret;
ac718b69 1988}
1989
00a5e360 1990static void rtl_drop_queued_tx(struct r8152 *tp)
1991{
1992 struct net_device_stats *stats = &tp->netdev->stats;
d84130a1 1993 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
00a5e360 1994 struct sk_buff *skb;
1995
d84130a1 1996 if (skb_queue_empty(tx_queue))
1997 return;
1998
1999 __skb_queue_head_init(&skb_head);
2685d410 2000 spin_lock_bh(&tx_queue->lock);
d84130a1 2001 skb_queue_splice_init(tx_queue, &skb_head);
2685d410 2002 spin_unlock_bh(&tx_queue->lock);
d84130a1 2003
2004 while ((skb = __skb_dequeue(&skb_head))) {
00a5e360 2005 dev_kfree_skb(skb);
2006 stats->tx_dropped++;
2007 }
2008}
2009
ac718b69 2010static void rtl8152_tx_timeout(struct net_device *netdev)
2011{
2012 struct r8152 *tp = netdev_priv(netdev);
ebc2ec48 2013
4a8deae2 2014 netif_warn(tp, tx_err, netdev, "Tx timeout\n");
37608f3e 2015
2016 usb_queue_reset_device(tp->intf);
ac718b69 2017}
2018
2019static void rtl8152_set_rx_mode(struct net_device *netdev)
2020{
2021 struct r8152 *tp = netdev_priv(netdev);
2022
51d979fa 2023 if (netif_carrier_ok(netdev)) {
ac718b69 2024 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
40a82917 2025 schedule_delayed_work(&tp->schedule, 0);
2026 }
ac718b69 2027}
2028
2029static void _rtl8152_set_rx_mode(struct net_device *netdev)
2030{
2031 struct r8152 *tp = netdev_priv(netdev);
31787f53 2032 u32 mc_filter[2]; /* Multicast hash filter */
2033 __le32 tmp[2];
ac718b69 2034 u32 ocp_data;
2035
ac718b69 2036 netif_stop_queue(netdev);
2037 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2038 ocp_data &= ~RCR_ACPT_ALL;
2039 ocp_data |= RCR_AB | RCR_APM;
2040
2041 if (netdev->flags & IFF_PROMISC) {
2042 /* Unconditionally log net taps. */
2043 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
2044 ocp_data |= RCR_AM | RCR_AAP;
b209af99 2045 mc_filter[1] = 0xffffffff;
2046 mc_filter[0] = 0xffffffff;
ac718b69 2047 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
2048 (netdev->flags & IFF_ALLMULTI)) {
2049 /* Too many to filter perfectly -- accept all multicasts. */
2050 ocp_data |= RCR_AM;
b209af99 2051 mc_filter[1] = 0xffffffff;
2052 mc_filter[0] = 0xffffffff;
ac718b69 2053 } else {
2054 struct netdev_hw_addr *ha;
2055
b209af99 2056 mc_filter[1] = 0;
2057 mc_filter[0] = 0;
ac718b69 2058 netdev_for_each_mc_addr(ha, netdev) {
2059 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
b209af99 2060
ac718b69 2061 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2062 ocp_data |= RCR_AM;
2063 }
2064 }
2065
31787f53 2066 tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
2067 tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
ac718b69 2068
31787f53 2069 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
ac718b69 2070 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2071 netif_wake_queue(netdev);
ac718b69 2072}
2073
a5e31255 2074static netdev_features_t
2075rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
2076 netdev_features_t features)
2077{
2078 u32 mss = skb_shinfo(skb)->gso_size;
2079 int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
2080 int offset = skb_transport_offset(skb);
2081
2082 if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
a188222b 2083 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
a5e31255 2084 else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
2085 features &= ~NETIF_F_GSO_MASK;
2086
2087 return features;
2088}
2089
ac718b69 2090static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
b209af99 2091 struct net_device *netdev)
ac718b69 2092{
2093 struct r8152 *tp = netdev_priv(netdev);
ac718b69 2094
ebc2ec48 2095 skb_tx_timestamp(skb);
ac718b69 2096
61598788 2097 skb_queue_tail(&tp->tx_queue, skb);
ebc2ec48 2098
0c3121fc 2099 if (!list_empty(&tp->tx_free)) {
2100 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
d823ab68 2101 set_bit(SCHEDULE_NAPI, &tp->flags);
0c3121fc 2102 schedule_delayed_work(&tp->schedule, 0);
2103 } else {
2104 usb_mark_last_busy(tp->udev);
d823ab68 2105 napi_schedule(&tp->napi);
0c3121fc 2106 }
b209af99 2107 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
dd1b119c 2108 netif_stop_queue(netdev);
b209af99 2109 }
dd1b119c 2110
ac718b69 2111 return NETDEV_TX_OK;
2112}
2113
2114static void r8152b_reset_packet_filter(struct r8152 *tp)
2115{
2116 u32 ocp_data;
2117
2118 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
2119 ocp_data &= ~FMC_FCR_MCU_EN;
2120 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2121 ocp_data |= FMC_FCR_MCU_EN;
2122 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2123}
2124
2125static void rtl8152_nic_reset(struct r8152 *tp)
2126{
2127 int i;
2128
2129 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
2130
2131 for (i = 0; i < 1000; i++) {
2132 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
2133 break;
b209af99 2134 usleep_range(100, 400);
ac718b69 2135 }
2136}
2137
dd1b119c 2138static void set_tx_qlen(struct r8152 *tp)
2139{
2140 struct net_device *netdev = tp->netdev;
2141
52aec126 2142 tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN +
2143 sizeof(struct tx_desc));
dd1b119c 2144}
2145
ac718b69 2146static inline u8 rtl8152_get_speed(struct r8152 *tp)
2147{
2148 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
2149}
2150
507605a8 2151static void rtl_set_eee_plus(struct r8152 *tp)
ac718b69 2152{
ebc2ec48 2153 u32 ocp_data;
ac718b69 2154 u8 speed;
2155
2156 speed = rtl8152_get_speed(tp);
ebc2ec48 2157 if (speed & _10bps) {
ac718b69 2158 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
ebc2ec48 2159 ocp_data |= EEEP_CR_EEEP_TX;
ac718b69 2160 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2161 } else {
2162 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
ebc2ec48 2163 ocp_data &= ~EEEP_CR_EEEP_TX;
ac718b69 2164 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2165 }
507605a8 2166}
2167
00a5e360 2168static void rxdy_gated_en(struct r8152 *tp, bool enable)
2169{
2170 u32 ocp_data;
2171
2172 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
2173 if (enable)
2174 ocp_data |= RXDY_GATED_EN;
2175 else
2176 ocp_data &= ~RXDY_GATED_EN;
2177 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2178}
2179
445f7f4d 2180static int rtl_start_rx(struct r8152 *tp)
2181{
2182 int i, ret = 0;
2183
2184 INIT_LIST_HEAD(&tp->rx_done);
2185 for (i = 0; i < RTL8152_MAX_RX; i++) {
2186 INIT_LIST_HEAD(&tp->rx_info[i].list);
2187 ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
2188 if (ret)
2189 break;
2190 }
2191
7bcf4f60 2192 if (ret && ++i < RTL8152_MAX_RX) {
2193 struct list_head rx_queue;
2194 unsigned long flags;
2195
2196 INIT_LIST_HEAD(&rx_queue);
2197
2198 do {
2199 struct rx_agg *agg = &tp->rx_info[i++];
2200 struct urb *urb = agg->urb;
2201
2202 urb->actual_length = 0;
2203 list_add_tail(&agg->list, &rx_queue);
2204 } while (i < RTL8152_MAX_RX);
2205
2206 spin_lock_irqsave(&tp->rx_lock, flags);
2207 list_splice_tail(&rx_queue, &tp->rx_done);
2208 spin_unlock_irqrestore(&tp->rx_lock, flags);
2209 }
2210
445f7f4d 2211 return ret;
2212}
2213
2214static int rtl_stop_rx(struct r8152 *tp)
2215{
2216 int i;
2217
2218 for (i = 0; i < RTL8152_MAX_RX; i++)
2219 usb_kill_urb(tp->rx_info[i].urb);
2220
d823ab68 2221 while (!skb_queue_empty(&tp->rx_queue))
2222 dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
2223
445f7f4d 2224 return 0;
2225}
2226
507605a8 2227static int rtl_enable(struct r8152 *tp)
2228{
2229 u32 ocp_data;
ac718b69 2230
2231 r8152b_reset_packet_filter(tp);
2232
2233 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2234 ocp_data |= CR_RE | CR_TE;
2235 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2236
00a5e360 2237 rxdy_gated_en(tp, false);
ac718b69 2238
aa2e0926 2239 return 0;
ac718b69 2240}
2241
507605a8 2242static int rtl8152_enable(struct r8152 *tp)
2243{
6871438c 2244 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2245 return -ENODEV;
2246
507605a8 2247 set_tx_qlen(tp);
2248 rtl_set_eee_plus(tp);
2249
2250 return rtl_enable(tp);
2251}
2252
464ec10a 2253static void r8153_set_rx_early_timeout(struct r8152 *tp)
43779f8d 2254{
464ec10a 2255 u32 ocp_data = tp->coalesce / 8;
43779f8d 2256
464ec10a 2257 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, ocp_data);
2258}
2259
2260static void r8153_set_rx_early_size(struct r8152 *tp)
2261{
b20cb60e 2262 u32 ocp_data = (agg_buf_sz - rx_reserved_size(tp->netdev->mtu)) / 4;
464ec10a 2263
2264 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, ocp_data);
43779f8d 2265}
2266
2267static int rtl8153_enable(struct r8152 *tp)
2268{
6871438c 2269 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2270 return -ENODEV;
2271
43779f8d 2272 set_tx_qlen(tp);
2273 rtl_set_eee_plus(tp);
464ec10a 2274 r8153_set_rx_early_timeout(tp);
2275 r8153_set_rx_early_size(tp);
43779f8d 2276
2277 return rtl_enable(tp);
2278}
2279
d70b1137 2280static void rtl_disable(struct r8152 *tp)
ac718b69 2281{
ebc2ec48 2282 u32 ocp_data;
2283 int i;
ac718b69 2284
6871438c 2285 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2286 rtl_drop_queued_tx(tp);
2287 return;
2288 }
2289
ac718b69 2290 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2291 ocp_data &= ~RCR_ACPT_ALL;
2292 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2293
00a5e360 2294 rtl_drop_queued_tx(tp);
ebc2ec48 2295
2296 for (i = 0; i < RTL8152_MAX_TX; i++)
2297 usb_kill_urb(tp->tx_info[i].urb);
ac718b69 2298
00a5e360 2299 rxdy_gated_en(tp, true);
ac718b69 2300
2301 for (i = 0; i < 1000; i++) {
2302 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2303 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2304 break;
8ddfa077 2305 usleep_range(1000, 2000);
ac718b69 2306 }
2307
2308 for (i = 0; i < 1000; i++) {
2309 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2310 break;
8ddfa077 2311 usleep_range(1000, 2000);
ac718b69 2312 }
2313
445f7f4d 2314 rtl_stop_rx(tp);
ac718b69 2315
2316 rtl8152_nic_reset(tp);
2317}
2318
00a5e360 2319static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2320{
2321 u32 ocp_data;
2322
2323 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2324 if (enable)
2325 ocp_data |= POWER_CUT;
2326 else
2327 ocp_data &= ~POWER_CUT;
2328 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2329
2330 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2331 ocp_data &= ~RESUME_INDICATE;
2332 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
00a5e360 2333}
2334
c5554298 2335static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2336{
2337 u32 ocp_data;
2338
2339 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2340 if (enable)
2341 ocp_data |= CPCR_RX_VLAN;
2342 else
2343 ocp_data &= ~CPCR_RX_VLAN;
2344 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2345}
2346
2347static int rtl8152_set_features(struct net_device *dev,
2348 netdev_features_t features)
2349{
2350 netdev_features_t changed = features ^ dev->features;
2351 struct r8152 *tp = netdev_priv(dev);
405f8a0e 2352 int ret;
2353
2354 ret = usb_autopm_get_interface(tp->intf);
2355 if (ret < 0)
2356 goto out;
c5554298 2357
b5403273 2358 mutex_lock(&tp->control);
2359
c5554298 2360 if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2361 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2362 rtl_rx_vlan_en(tp, true);
2363 else
2364 rtl_rx_vlan_en(tp, false);
2365 }
2366
b5403273 2367 mutex_unlock(&tp->control);
2368
405f8a0e 2369 usb_autopm_put_interface(tp->intf);
2370
2371out:
2372 return ret;
c5554298 2373}
2374
21ff2e89 2375#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2376
2377static u32 __rtl_get_wol(struct r8152 *tp)
2378{
2379 u32 ocp_data;
2380 u32 wolopts = 0;
2381
21ff2e89 2382 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2383 if (ocp_data & LINK_ON_WAKE_EN)
2384 wolopts |= WAKE_PHY;
2385
2386 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2387 if (ocp_data & UWF_EN)
2388 wolopts |= WAKE_UCAST;
2389 if (ocp_data & BWF_EN)
2390 wolopts |= WAKE_BCAST;
2391 if (ocp_data & MWF_EN)
2392 wolopts |= WAKE_MCAST;
2393
2394 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2395 if (ocp_data & MAGIC_EN)
2396 wolopts |= WAKE_MAGIC;
2397
2398 return wolopts;
2399}
2400
2401static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
2402{
2403 u32 ocp_data;
2404
2405 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2406
2407 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2408 ocp_data &= ~LINK_ON_WAKE_EN;
2409 if (wolopts & WAKE_PHY)
2410 ocp_data |= LINK_ON_WAKE_EN;
2411 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2412
2413 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
92f7d07d 2414 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);
21ff2e89 2415 if (wolopts & WAKE_UCAST)
2416 ocp_data |= UWF_EN;
2417 if (wolopts & WAKE_BCAST)
2418 ocp_data |= BWF_EN;
2419 if (wolopts & WAKE_MCAST)
2420 ocp_data |= MWF_EN;
21ff2e89 2421 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
2422
2423 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2424
2425 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2426 ocp_data &= ~MAGIC_EN;
2427 if (wolopts & WAKE_MAGIC)
2428 ocp_data |= MAGIC_EN;
2429 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
2430
2431 if (wolopts & WAKE_ANY)
2432 device_set_wakeup_enable(&tp->udev->dev, true);
2433 else
2434 device_set_wakeup_enable(&tp->udev->dev, false);
2435}
2436
134f98bc 2437static void r8153_mac_clk_spd(struct r8152 *tp, bool enable)
2438{
2439 /* MAC clock speed down */
2440 if (enable) {
2441 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL,
2442 ALDPS_SPDWN_RATIO);
2443 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2,
2444 EEE_SPDWN_RATIO);
2445 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
2446 PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
2447 U1U2_SPDWN_EN | L1_SPDWN_EN);
2448 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
2449 PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
2450 TP100_SPDWN_EN | TP500_SPDWN_EN | EEE_SPDWN_EN |
2451 TP1000_SPDWN_EN);
2452 } else {
2453 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0);
2454 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0);
2455 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0);
2456 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0);
2457 }
2458}
2459
b214396f 2460static void r8153_u1u2en(struct r8152 *tp, bool enable)
2461{
2462 u8 u1u2[8];
2463
2464 if (enable)
2465 memset(u1u2, 0xff, sizeof(u1u2));
2466 else
2467 memset(u1u2, 0x00, sizeof(u1u2));
2468
2469 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
2470}
2471
2472static void r8153_u2p3en(struct r8152 *tp, bool enable)
2473{
2474 u32 ocp_data;
2475
2476 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
3cb3234e 2477 if (enable)
b214396f 2478 ocp_data |= U2P3_ENABLE;
2479 else
2480 ocp_data &= ~U2P3_ENABLE;
2481 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
2482}
2483
c564b871 2484static u16 r8153_phy_status(struct r8152 *tp, u16 desired)
2485{
2486 u16 data;
2487 int i;
2488
2489 for (i = 0; i < 500; i++) {
2490 data = ocp_reg_read(tp, OCP_PHY_STATUS);
2491 data &= PHY_STAT_MASK;
2492 if (desired) {
2493 if (data == desired)
2494 break;
2495 } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN ||
2496 data == PHY_STAT_EXT_INIT) {
2497 break;
2498 }
2499
2500 msleep(20);
2501 }
2502
2503 return data;
2504}
2505
b214396f 2506static void r8153_power_cut_en(struct r8152 *tp, bool enable)
2507{
2508 u32 ocp_data;
2509
2510 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2511 if (enable)
2512 ocp_data |= PWR_EN | PHASE2_EN;
2513 else
2514 ocp_data &= ~(PWR_EN | PHASE2_EN);
2515 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2516
2517 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2518 ocp_data &= ~PCUT_STATUS;
2519 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2520}
2521
7daed8dc 2522static bool rtl_can_wakeup(struct r8152 *tp)
2523{
2524 struct usb_device *udev = tp->udev;
2525
2526 return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
2527}
2528
9a4be1bd 2529static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
2530{
2531 if (enable) {
2532 u32 ocp_data;
2533
2534 __rtl_set_wol(tp, WAKE_ANY);
2535
2536 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2537
2538 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2539 ocp_data |= LINK_OFF_WAKE_EN;
2540 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2541
2542 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2543 } else {
f95ae8a0 2544 u32 ocp_data;
2545
9a4be1bd 2546 __rtl_set_wol(tp, tp->saved_wolopts);
f95ae8a0 2547
2548 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2549
2550 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2551 ocp_data &= ~LINK_OFF_WAKE_EN;
2552 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2553
2554 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2609af19 2555 }
2556}
f95ae8a0 2557
2609af19 2558static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
2559{
2609af19 2560 if (enable) {
2561 r8153_u1u2en(tp, false);
2562 r8153_u2p3en(tp, false);
134f98bc 2563 r8153_mac_clk_spd(tp, true);
02552754 2564 rtl_runtime_suspend_enable(tp, true);
2609af19 2565 } else {
02552754 2566 rtl_runtime_suspend_enable(tp, false);
134f98bc 2567 r8153_mac_clk_spd(tp, false);
3cb3234e 2568
2569 switch (tp->version) {
2570 case RTL_VER_03:
2571 case RTL_VER_04:
2572 break;
2573 case RTL_VER_05:
2574 case RTL_VER_06:
2575 default:
2576 r8153_u2p3en(tp, true);
2577 break;
2578 }
2579
b214396f 2580 r8153_u1u2en(tp, true);
9a4be1bd 2581 }
2582}
2583
4349968a 2584static void r8153_teredo_off(struct r8152 *tp)
2585{
2586 u32 ocp_data;
2587
2588 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2589 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN);
2590 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2591
2592 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
2593 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
2594 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
2595}
2596
93fe9b18 2597static void rtl_reset_bmu(struct r8152 *tp)
2598{
2599 u32 ocp_data;
2600
2601 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
2602 ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
2603 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2604 ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
2605 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2606}
2607
cda9fb01 2608static void r8152_aldps_en(struct r8152 *tp, bool enable)
4349968a 2609{
cda9fb01 2610 if (enable) {
2611 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
2612 LINKENA | DIS_SDSAVE);
2613 } else {
2614 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
2615 DIS_SDSAVE);
2616 msleep(20);
2617 }
4349968a 2618}
2619
e6449539 2620static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
2621{
2622 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
2623 ocp_reg_write(tp, OCP_EEE_DATA, reg);
2624 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
2625}
2626
2627static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
2628{
2629 u16 data;
2630
2631 r8152_mmd_indirect(tp, dev, reg);
2632 data = ocp_reg_read(tp, OCP_EEE_DATA);
2633 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
2634
2635 return data;
2636}
2637
2638static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
2639{
2640 r8152_mmd_indirect(tp, dev, reg);
2641 ocp_reg_write(tp, OCP_EEE_DATA, data);
2642 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
2643}
2644
2645static void r8152_eee_en(struct r8152 *tp, bool enable)
2646{
2647 u16 config1, config2, config3;
2648 u32 ocp_data;
2649
2650 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
2651 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
2652 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
2653 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
2654
2655 if (enable) {
2656 ocp_data |= EEE_RX_EN | EEE_TX_EN;
2657 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
2658 config1 |= sd_rise_time(1);
2659 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
2660 config3 |= fast_snr(42);
2661 } else {
2662 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
2663 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
2664 RX_QUIET_EN);
2665 config1 |= sd_rise_time(7);
2666 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
2667 config3 |= fast_snr(511);
2668 }
2669
2670 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
2671 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
2672 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
2673 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
2674}
2675
2676static void r8152b_enable_eee(struct r8152 *tp)
2677{
2678 r8152_eee_en(tp, true);
2679 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
2680}
2681
2682static void r8152b_enable_fc(struct r8152 *tp)
2683{
2684 u16 anar;
2685
2686 anar = r8152_mdio_read(tp, MII_ADVERTISE);
2687 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
2688 r8152_mdio_write(tp, MII_ADVERTISE, anar);
2689}
2690
d70b1137 2691static void rtl8152_disable(struct r8152 *tp)
2692{
cda9fb01 2693 r8152_aldps_en(tp, false);
d70b1137 2694 rtl_disable(tp);
cda9fb01 2695 r8152_aldps_en(tp, true);
d70b1137 2696}
2697
4349968a 2698static void r8152b_hw_phy_cfg(struct r8152 *tp)
2699{
ef39df8e 2700 r8152b_enable_eee(tp);
2701 r8152_aldps_en(tp, true);
2702 r8152b_enable_fc(tp);
f0cbe0ac 2703
aa66a5f1 2704 set_bit(PHY_RESET, &tp->flags);
4349968a 2705}
2706
ac718b69 2707static void r8152b_exit_oob(struct r8152 *tp)
2708{
db8515ef 2709 u32 ocp_data;
2710 int i;
ac718b69 2711
2712 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2713 ocp_data &= ~RCR_ACPT_ALL;
2714 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2715
00a5e360 2716 rxdy_gated_en(tp, true);
da9bd117 2717 r8153_teredo_off(tp);
ac718b69 2718 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2719 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
2720
2721 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2722 ocp_data &= ~NOW_IS_OOB;
2723 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2724
2725 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2726 ocp_data &= ~MCU_BORW_EN;
2727 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2728
2729 for (i = 0; i < 1000; i++) {
2730 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2731 if (ocp_data & LINK_LIST_READY)
2732 break;
8ddfa077 2733 usleep_range(1000, 2000);
ac718b69 2734 }
2735
2736 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2737 ocp_data |= RE_INIT_LL;
2738 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2739
2740 for (i = 0; i < 1000; i++) {
2741 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2742 if (ocp_data & LINK_LIST_READY)
2743 break;
8ddfa077 2744 usleep_range(1000, 2000);
ac718b69 2745 }
2746
2747 rtl8152_nic_reset(tp);
2748
2749 /* rx share fifo credit full threshold */
2750 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2751
a3cc465d 2752 if (tp->udev->speed == USB_SPEED_FULL ||
2753 tp->udev->speed == USB_SPEED_LOW) {
ac718b69 2754 /* rx share fifo credit near full threshold */
2755 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2756 RXFIFO_THR2_FULL);
2757 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2758 RXFIFO_THR3_FULL);
2759 } else {
2760 /* rx share fifo credit near full threshold */
2761 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2762 RXFIFO_THR2_HIGH);
2763 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2764 RXFIFO_THR3_HIGH);
2765 }
2766
2767 /* TX share fifo free credit full threshold */
2768 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
2769
2770 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
8e1f51bd 2771 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
ac718b69 2772 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
2773 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
2774
c5554298 2775 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
ac718b69 2776
2777 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2778
2779 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2780 ocp_data |= TCR0_AUTO_FIFO;
2781 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2782}
2783
2784static void r8152b_enter_oob(struct r8152 *tp)
2785{
45f4a19f 2786 u32 ocp_data;
2787 int i;
ac718b69 2788
2789 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2790 ocp_data &= ~NOW_IS_OOB;
2791 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2792
2793 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
2794 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
2795 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
2796
d70b1137 2797 rtl_disable(tp);
ac718b69 2798
2799 for (i = 0; i < 1000; i++) {
2800 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2801 if (ocp_data & LINK_LIST_READY)
2802 break;
8ddfa077 2803 usleep_range(1000, 2000);
ac718b69 2804 }
2805
2806 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2807 ocp_data |= RE_INIT_LL;
2808 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2809
2810 for (i = 0; i < 1000; i++) {
2811 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2812 if (ocp_data & LINK_LIST_READY)
2813 break;
8ddfa077 2814 usleep_range(1000, 2000);
ac718b69 2815 }
2816
2817 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2818
c5554298 2819 rtl_rx_vlan_en(tp, true);
ac718b69 2820
2821 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2822 ocp_data |= ALDPS_PROXY_MODE;
2823 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2824
2825 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2826 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2827 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2828
00a5e360 2829 rxdy_gated_en(tp, false);
ac718b69 2830
2831 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2832 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2833 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2834}
2835
e6449539 2836static void r8153_aldps_en(struct r8152 *tp, bool enable)
2837{
2838 u16 data;
2839
2840 data = ocp_reg_read(tp, OCP_POWER_CFG);
2841 if (enable) {
2842 data |= EN_ALDPS;
2843 ocp_reg_write(tp, OCP_POWER_CFG, data);
2844 } else {
4214cc55 2845 int i;
2846
e6449539 2847 data &= ~EN_ALDPS;
2848 ocp_reg_write(tp, OCP_POWER_CFG, data);
4214cc55 2849 for (i = 0; i < 20; i++) {
2850 usleep_range(1000, 2000);
2851 if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100)
2852 break;
2853 }
e6449539 2854 }
2855}
2856
2857static void r8153_eee_en(struct r8152 *tp, bool enable)
2858{
2859 u32 ocp_data;
2860 u16 config;
2861
2862 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
2863 config = ocp_reg_read(tp, OCP_EEE_CFG);
2864
2865 if (enable) {
2866 ocp_data |= EEE_RX_EN | EEE_TX_EN;
2867 config |= EEE10_EN;
2868 } else {
2869 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
2870 config &= ~EEE10_EN;
2871 }
2872
2873 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
2874 ocp_reg_write(tp, OCP_EEE_CFG, config);
2875}
2876
43779f8d 2877static void r8153_hw_phy_cfg(struct r8152 *tp)
2878{
2879 u32 ocp_data;
2880 u16 data;
2881
d768c61b 2882 /* disable ALDPS before updating the PHY parameters */
2883 r8153_aldps_en(tp, false);
fb02eb4a 2884
d768c61b 2885 /* disable EEE before updating the PHY parameters */
2886 r8153_eee_en(tp, false);
2887 ocp_reg_write(tp, OCP_EEE_ADV, 0);
43779f8d 2888
2889 if (tp->version == RTL_VER_03) {
2890 data = ocp_reg_read(tp, OCP_EEE_CFG);
2891 data &= ~CTAP_SHORT_EN;
2892 ocp_reg_write(tp, OCP_EEE_CFG, data);
2893 }
2894
2895 data = ocp_reg_read(tp, OCP_POWER_CFG);
2896 data |= EEE_CLKDIV_EN;
2897 ocp_reg_write(tp, OCP_POWER_CFG, data);
2898
2899 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
2900 data |= EN_10M_BGOFF;
2901 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
2902 data = ocp_reg_read(tp, OCP_POWER_CFG);
2903 data |= EN_10M_PLLOFF;
2904 ocp_reg_write(tp, OCP_POWER_CFG, data);
b4d99def 2905 sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
43779f8d 2906
2907 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
2908 ocp_data |= PFM_PWM_SWITCH;
2909 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
2910
b4d99def 2911 /* Enable LPF corner auto tune */
2912 sram_write(tp, SRAM_LPF_CFG, 0xf70f);
43779f8d 2913
b4d99def 2914 /* Adjust 10M Amplitude */
2915 sram_write(tp, SRAM_10M_AMP1, 0x00af);
2916 sram_write(tp, SRAM_10M_AMP2, 0x0208);
aa66a5f1 2917
af0287ec 2918 r8153_eee_en(tp, true);
2919 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
2920
ef39df8e 2921 r8153_aldps_en(tp, true);
2922 r8152b_enable_fc(tp);
2923
3cb3234e 2924 switch (tp->version) {
2925 case RTL_VER_03:
2926 case RTL_VER_04:
2927 break;
2928 case RTL_VER_05:
2929 case RTL_VER_06:
2930 default:
2931 r8153_u2p3en(tp, true);
2932 break;
2933 }
2934
aa66a5f1 2935 set_bit(PHY_RESET, &tp->flags);
43779f8d 2936}
2937
43779f8d 2938static void r8153_first_init(struct r8152 *tp)
2939{
2940 u32 ocp_data;
2941 int i;
2942
134f98bc 2943 r8153_mac_clk_spd(tp, false);
00a5e360 2944 rxdy_gated_en(tp, true);
43779f8d 2945 r8153_teredo_off(tp);
2946
2947 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2948 ocp_data &= ~RCR_ACPT_ALL;
2949 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2950
43779f8d 2951 rtl8152_nic_reset(tp);
93fe9b18 2952 rtl_reset_bmu(tp);
43779f8d 2953
2954 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2955 ocp_data &= ~NOW_IS_OOB;
2956 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2957
2958 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2959 ocp_data &= ~MCU_BORW_EN;
2960 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2961
2962 for (i = 0; i < 1000; i++) {
2963 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2964 if (ocp_data & LINK_LIST_READY)
2965 break;
8ddfa077 2966 usleep_range(1000, 2000);
43779f8d 2967 }
2968
2969 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2970 ocp_data |= RE_INIT_LL;
2971 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2972
2973 for (i = 0; i < 1000; i++) {
2974 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2975 if (ocp_data & LINK_LIST_READY)
2976 break;
8ddfa077 2977 usleep_range(1000, 2000);
43779f8d 2978 }
2979
c5554298 2980 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
43779f8d 2981
210c4f70 2982 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + CRC_SIZE;
2983 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
69b4b7a4 2984 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
43779f8d 2985
2986 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2987 ocp_data |= TCR0_AUTO_FIFO;
2988 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2989
2990 rtl8152_nic_reset(tp);
2991
2992 /* rx share fifo credit full threshold */
2993 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2994 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
2995 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
2996 /* TX share fifo free credit full threshold */
2997 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
43779f8d 2998}
2999
3000static void r8153_enter_oob(struct r8152 *tp)
3001{
3002 u32 ocp_data;
3003 int i;
3004
134f98bc 3005 r8153_mac_clk_spd(tp, true);
3006
43779f8d 3007 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3008 ocp_data &= ~NOW_IS_OOB;
3009 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3010
d70b1137 3011 rtl_disable(tp);
93fe9b18 3012 rtl_reset_bmu(tp);
43779f8d 3013
3014 for (i = 0; i < 1000; i++) {
3015 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3016 if (ocp_data & LINK_LIST_READY)
3017 break;
8ddfa077 3018 usleep_range(1000, 2000);
43779f8d 3019 }
3020
3021 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3022 ocp_data |= RE_INIT_LL;
3023 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3024
3025 for (i = 0; i < 1000; i++) {
3026 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3027 if (ocp_data & LINK_LIST_READY)
3028 break;
8ddfa077 3029 usleep_range(1000, 2000);
43779f8d 3030 }
3031
210c4f70 3032 ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + CRC_SIZE;
3033 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
43779f8d 3034
43779f8d 3035 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
3036 ocp_data &= ~TEREDO_WAKE_MASK;
3037 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
3038
c5554298 3039 rtl_rx_vlan_en(tp, true);
43779f8d 3040
3041 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
3042 ocp_data |= ALDPS_PROXY_MODE;
3043 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
3044
3045 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3046 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
3047 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3048
00a5e360 3049 rxdy_gated_en(tp, false);
43779f8d 3050
3051 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3052 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
3053 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3054}
3055
d70b1137 3056static void rtl8153_disable(struct r8152 *tp)
3057{
cda9fb01 3058 r8153_aldps_en(tp, false);
d70b1137 3059 rtl_disable(tp);
93fe9b18 3060 rtl_reset_bmu(tp);
cda9fb01 3061 r8153_aldps_en(tp, true);
d70b1137 3062}
3063
ac718b69 3064static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
3065{
43779f8d 3066 u16 bmcr, anar, gbcr;
ac718b69 3067 int ret = 0;
3068
ac718b69 3069 anar = r8152_mdio_read(tp, MII_ADVERTISE);
3070 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
3071 ADVERTISE_100HALF | ADVERTISE_100FULL);
43779f8d 3072 if (tp->mii.supports_gmii) {
3073 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
3074 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
3075 } else {
3076 gbcr = 0;
3077 }
ac718b69 3078
3079 if (autoneg == AUTONEG_DISABLE) {
3080 if (speed == SPEED_10) {
3081 bmcr = 0;
3082 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3083 } else if (speed == SPEED_100) {
3084 bmcr = BMCR_SPEED100;
3085 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
43779f8d 3086 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
3087 bmcr = BMCR_SPEED1000;
3088 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
ac718b69 3089 } else {
3090 ret = -EINVAL;
3091 goto out;
3092 }
3093
3094 if (duplex == DUPLEX_FULL)
3095 bmcr |= BMCR_FULLDPLX;
3096 } else {
3097 if (speed == SPEED_10) {
3098 if (duplex == DUPLEX_FULL)
3099 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3100 else
3101 anar |= ADVERTISE_10HALF;
3102 } else if (speed == SPEED_100) {
3103 if (duplex == DUPLEX_FULL) {
3104 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3105 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
3106 } else {
3107 anar |= ADVERTISE_10HALF;
3108 anar |= ADVERTISE_100HALF;
3109 }
43779f8d 3110 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
3111 if (duplex == DUPLEX_FULL) {
3112 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3113 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
3114 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
3115 } else {
3116 anar |= ADVERTISE_10HALF;
3117 anar |= ADVERTISE_100HALF;
3118 gbcr |= ADVERTISE_1000HALF;
3119 }
ac718b69 3120 } else {
3121 ret = -EINVAL;
3122 goto out;
3123 }
3124
3125 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
3126 }
3127
fae56178 3128 if (test_and_clear_bit(PHY_RESET, &tp->flags))
aa66a5f1 3129 bmcr |= BMCR_RESET;
3130
43779f8d 3131 if (tp->mii.supports_gmii)
3132 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
3133
ac718b69 3134 r8152_mdio_write(tp, MII_ADVERTISE, anar);
3135 r8152_mdio_write(tp, MII_BMCR, bmcr);
3136
fae56178 3137 if (bmcr & BMCR_RESET) {
aa66a5f1 3138 int i;
3139
aa66a5f1 3140 for (i = 0; i < 50; i++) {
3141 msleep(20);
3142 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
3143 break;
3144 }
3145 }
3146
ac718b69 3147out:
ac718b69 3148 return ret;
3149}
3150
d70b1137 3151static void rtl8152_up(struct r8152 *tp)
3152{
3153 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3154 return;
3155
cda9fb01 3156 r8152_aldps_en(tp, false);
d70b1137 3157 r8152b_exit_oob(tp);
cda9fb01 3158 r8152_aldps_en(tp, true);
d70b1137 3159}
3160
ac718b69 3161static void rtl8152_down(struct r8152 *tp)
3162{
6871438c 3163 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3164 rtl_drop_queued_tx(tp);
3165 return;
3166 }
3167
00a5e360 3168 r8152_power_cut_en(tp, false);
cda9fb01 3169 r8152_aldps_en(tp, false);
ac718b69 3170 r8152b_enter_oob(tp);
cda9fb01 3171 r8152_aldps_en(tp, true);
ac718b69 3172}
3173
d70b1137 3174static void rtl8153_up(struct r8152 *tp)
3175{
3176 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3177 return;
3178
b214396f 3179 r8153_u1u2en(tp, false);
3cb3234e 3180 r8153_u2p3en(tp, false);
cda9fb01 3181 r8153_aldps_en(tp, false);
d70b1137 3182 r8153_first_init(tp);
cda9fb01 3183 r8153_aldps_en(tp, true);
3cb3234e 3184
3185 switch (tp->version) {
3186 case RTL_VER_03:
3187 case RTL_VER_04:
3188 break;
3189 case RTL_VER_05:
3190 case RTL_VER_06:
3191 default:
3192 r8153_u2p3en(tp, true);
3193 break;
3194 }
3195
b214396f 3196 r8153_u1u2en(tp, true);
d70b1137 3197}
3198
43779f8d 3199static void rtl8153_down(struct r8152 *tp)
3200{
6871438c 3201 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3202 rtl_drop_queued_tx(tp);
3203 return;
3204 }
3205
b9702723 3206 r8153_u1u2en(tp, false);
b214396f 3207 r8153_u2p3en(tp, false);
b9702723 3208 r8153_power_cut_en(tp, false);
cda9fb01 3209 r8153_aldps_en(tp, false);
43779f8d 3210 r8153_enter_oob(tp);
cda9fb01 3211 r8153_aldps_en(tp, true);
43779f8d 3212}
3213
2dd49e0f 3214static bool rtl8152_in_nway(struct r8152 *tp)
3215{
3216 u16 nway_state;
3217
3218 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
3219 tp->ocp_base = 0x2000;
3220 ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */
3221 nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
3222
3223 /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
3224 if (nway_state & 0xc000)
3225 return false;
3226 else
3227 return true;
3228}
3229
3230static bool rtl8153_in_nway(struct r8152 *tp)
3231{
3232 u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
3233
3234 if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
3235 return false;
3236 else
3237 return true;
3238}
3239
ac718b69 3240static void set_carrier(struct r8152 *tp)
3241{
3242 struct net_device *netdev = tp->netdev;
ce594e98 3243 struct napi_struct *napi = &tp->napi;
ac718b69 3244 u8 speed;
3245
3246 speed = rtl8152_get_speed(tp);
3247
3248 if (speed & LINK_STATUS) {
51d979fa 3249 if (!netif_carrier_ok(netdev)) {
c81229c9 3250 tp->rtl_ops.enable(tp);
ac718b69 3251 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
de9bf29d 3252 netif_stop_queue(netdev);
ce594e98 3253 napi_disable(napi);
ac718b69 3254 netif_carrier_on(netdev);
aa2e0926 3255 rtl_start_rx(tp);
41cec84c 3256 napi_enable(&tp->napi);
de9bf29d 3257 netif_wake_queue(netdev);
3258 netif_info(tp, link, netdev, "carrier on\n");
2f25abe6 3259 } else if (netif_queue_stopped(netdev) &&
3260 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) {
3261 netif_wake_queue(netdev);
ac718b69 3262 }
3263 } else {
51d979fa 3264 if (netif_carrier_ok(netdev)) {
ac718b69 3265 netif_carrier_off(netdev);
ce594e98 3266 napi_disable(napi);
c81229c9 3267 tp->rtl_ops.disable(tp);
ce594e98 3268 napi_enable(napi);
de9bf29d 3269 netif_info(tp, link, netdev, "carrier off\n");
ac718b69 3270 }
3271 }
ac718b69 3272}
3273
3274static void rtl_work_func_t(struct work_struct *work)
3275{
3276 struct r8152 *tp = container_of(work, struct r8152, schedule.work);
3277
a1f83fee 3278 /* If the device is unplugged or !netif_running(), the workqueue
3279 * doesn't need to wake the device, and could return directly.
3280 */
3281 if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
3282 return;
3283
9a4be1bd 3284 if (usb_autopm_get_interface(tp->intf) < 0)
3285 return;
3286
ac718b69 3287 if (!test_bit(WORK_ENABLE, &tp->flags))
3288 goto out1;
3289
b5403273 3290 if (!mutex_trylock(&tp->control)) {
3291 schedule_delayed_work(&tp->schedule, 0);
3292 goto out1;
3293 }
3294
216a8349 3295 if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
40a82917 3296 set_carrier(tp);
ac718b69 3297
216a8349 3298 if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
ac718b69 3299 _rtl8152_set_rx_mode(tp->netdev);
3300
d823ab68 3301 /* don't schedule napi before linking */
216a8349 3302 if (test_and_clear_bit(SCHEDULE_NAPI, &tp->flags) &&
3303 netif_carrier_ok(tp->netdev))
d823ab68 3304 napi_schedule(&tp->napi);
aa66a5f1 3305
b5403273 3306 mutex_unlock(&tp->control);
3307
ac718b69 3308out1:
9a4be1bd 3309 usb_autopm_put_interface(tp->intf);
ac718b69 3310}
3311
a028a9e0 3312static void rtl_hw_phy_work_func_t(struct work_struct *work)
3313{
3314 struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
3315
3316 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3317 return;
3318
3319 if (usb_autopm_get_interface(tp->intf) < 0)
3320 return;
3321
3322 mutex_lock(&tp->control);
3323
3324 tp->rtl_ops.hw_phy_cfg(tp);
3325
aa7e26b6 3326 rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex);
9d21c0d8 3327
a028a9e0 3328 mutex_unlock(&tp->control);
3329
3330 usb_autopm_put_interface(tp->intf);
3331}
3332
5ee3c60c 3333#ifdef CONFIG_PM_SLEEP
3334static int rtl_notifier(struct notifier_block *nb, unsigned long action,
3335 void *data)
3336{
3337 struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
3338
3339 switch (action) {
3340 case PM_HIBERNATION_PREPARE:
3341 case PM_SUSPEND_PREPARE:
3342 usb_autopm_get_interface(tp->intf);
3343 break;
3344
3345 case PM_POST_HIBERNATION:
3346 case PM_POST_SUSPEND:
3347 usb_autopm_put_interface(tp->intf);
3348 break;
3349
3350 case PM_POST_RESTORE:
3351 case PM_RESTORE_PREPARE:
3352 default:
3353 break;
3354 }
3355
3356 return NOTIFY_DONE;
3357}
3358#endif
3359
ac718b69 3360static int rtl8152_open(struct net_device *netdev)
3361{
3362 struct r8152 *tp = netdev_priv(netdev);
3363 int res = 0;
3364
7e9da481 3365 res = alloc_all_mem(tp);
3366 if (res)
3367 goto out;
3368
9a4be1bd 3369 res = usb_autopm_get_interface(tp->intf);
ca0a7531
GR
3370 if (res < 0)
3371 goto out_free;
9a4be1bd 3372
b5403273 3373 mutex_lock(&tp->control);
3374
7e9da481 3375 tp->rtl_ops.up(tp);
3376
3d55f44f 3377 netif_carrier_off(netdev);
3378 netif_start_queue(netdev);
3379 set_bit(WORK_ENABLE, &tp->flags);
db8515ef 3380
40a82917 3381 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
3382 if (res) {
3383 if (res == -ENODEV)
3384 netif_device_detach(tp->netdev);
4a8deae2
HW
3385 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
3386 res);
ca0a7531 3387 goto out_unlock;
ac718b69 3388 }
ca0a7531 3389 napi_enable(&tp->napi);
ac718b69 3390
b5403273 3391 mutex_unlock(&tp->control);
3392
9a4be1bd 3393 usb_autopm_put_interface(tp->intf);
5ee3c60c 3394#ifdef CONFIG_PM_SLEEP
3395 tp->pm_notifier.notifier_call = rtl_notifier;
3396 register_pm_notifier(&tp->pm_notifier);
3397#endif
ca0a7531 3398 return 0;
ac718b69 3399
ca0a7531
GR
3400out_unlock:
3401 mutex_unlock(&tp->control);
3402 usb_autopm_put_interface(tp->intf);
3403out_free:
3404 free_all_mem(tp);
7e9da481 3405out:
ac718b69 3406 return res;
3407}
3408
3409static int rtl8152_close(struct net_device *netdev)
3410{
3411 struct r8152 *tp = netdev_priv(netdev);
3412 int res = 0;
3413
5ee3c60c 3414#ifdef CONFIG_PM_SLEEP
3415 unregister_pm_notifier(&tp->pm_notifier);
3416#endif
d823ab68 3417 napi_disable(&tp->napi);
ac718b69 3418 clear_bit(WORK_ENABLE, &tp->flags);
3d55f44f 3419 usb_kill_urb(tp->intr_urb);
ac718b69 3420 cancel_delayed_work_sync(&tp->schedule);
3421 netif_stop_queue(netdev);
9a4be1bd 3422
3423 res = usb_autopm_get_interface(tp->intf);
53543db5 3424 if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
9a4be1bd 3425 rtl_drop_queued_tx(tp);
d823ab68 3426 rtl_stop_rx(tp);
9a4be1bd 3427 } else {
b5403273 3428 mutex_lock(&tp->control);
3429
9a4be1bd 3430 tp->rtl_ops.down(tp);
b5403273 3431
3432 mutex_unlock(&tp->control);
3433
9a4be1bd 3434 usb_autopm_put_interface(tp->intf);
3435 }
ac718b69 3436
7e9da481 3437 free_all_mem(tp);
3438
ac718b69 3439 return res;
3440}
3441
4f1d4d54 3442static void rtl_tally_reset(struct r8152 *tp)
3443{
3444 u32 ocp_data;
3445
3446 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
3447 ocp_data |= TALLY_RESET;
3448 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
3449}
3450
ac718b69 3451static void r8152b_init(struct r8152 *tp)
3452{
ebc2ec48 3453 u32 ocp_data;
2dd436da 3454 u16 data;
ac718b69 3455
6871438c 3456 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3457 return;
3458
2dd436da 3459 data = r8152_mdio_read(tp, MII_BMCR);
3460 if (data & BMCR_PDOWN) {
3461 data &= ~BMCR_PDOWN;
3462 r8152_mdio_write(tp, MII_BMCR, data);
3463 }
3464
cda9fb01 3465 r8152_aldps_en(tp, false);
d70b1137 3466
ac718b69 3467 if (tp->version == RTL_VER_01) {
3468 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3469 ocp_data &= ~LED_MODE_MASK;
3470 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3471 }
3472
00a5e360 3473 r8152_power_cut_en(tp, false);
ac718b69 3474
ac718b69 3475 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3476 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
3477 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3478 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
3479 ocp_data &= ~MCU_CLK_RATIO_MASK;
3480 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
3481 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
3482 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
3483 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
3484 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
3485
4f1d4d54 3486 rtl_tally_reset(tp);
ac718b69 3487
ebc2ec48 3488 /* enable rx aggregation */
ac718b69 3489 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
e90fba8d 3490 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
ac718b69 3491 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
3492}
3493
43779f8d 3494static void r8153_init(struct r8152 *tp)
3495{
3496 u32 ocp_data;
2dd436da 3497 u16 data;
43779f8d 3498 int i;
3499
6871438c 3500 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3501 return;
3502
b9702723 3503 r8153_u1u2en(tp, false);
43779f8d 3504
3505 for (i = 0; i < 500; i++) {
3506 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3507 AUTOLOAD_DONE)
3508 break;
3509 msleep(20);
3510 }
3511
c564b871 3512 data = r8153_phy_status(tp, 0);
43779f8d 3513
2dd436da 3514 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
3515 tp->version == RTL_VER_05)
3516 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
3517
3518 data = r8152_mdio_read(tp, MII_BMCR);
3519 if (data & BMCR_PDOWN) {
3520 data &= ~BMCR_PDOWN;
3521 r8152_mdio_write(tp, MII_BMCR, data);
3522 }
3523
c564b871 3524 data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
2dd436da 3525
b9702723 3526 r8153_u2p3en(tp, false);
43779f8d 3527
65bab84c 3528 if (tp->version == RTL_VER_04) {
3529 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
3530 ocp_data &= ~pwd_dn_scale_mask;
3531 ocp_data |= pwd_dn_scale(96);
3532 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
3533
3534 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
3535 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
3536 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
3537 } else if (tp->version == RTL_VER_05) {
3538 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
3539 ocp_data &= ~ECM_ALDPS;
3540 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
3541
fb02eb4a 3542 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
3543 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
3544 ocp_data &= ~DYNAMIC_BURST;
3545 else
3546 ocp_data |= DYNAMIC_BURST;
3547 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
3548 } else if (tp->version == RTL_VER_06) {
65bab84c 3549 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
3550 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
3551 ocp_data &= ~DYNAMIC_BURST;
3552 else
3553 ocp_data |= DYNAMIC_BURST;
3554 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
3555 }
3556
3557 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
3558 ocp_data |= EP4_FULL_FC;
3559 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
3560
43779f8d 3561 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
3562 ocp_data &= ~TIMER11_EN;
3563 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
3564
43779f8d 3565 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3566 ocp_data &= ~LED_MODE_MASK;
3567 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3568
65bab84c 3569 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
2b84af94 3570 if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
43779f8d 3571 ocp_data |= LPM_TIMER_500MS;
34203e25 3572 else
3573 ocp_data |= LPM_TIMER_500US;
43779f8d 3574 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
3575
3576 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
3577 ocp_data &= ~SEN_VAL_MASK;
3578 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
3579 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
3580
65bab84c 3581 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
3582
b9702723 3583 r8153_power_cut_en(tp, false);
3584 r8153_u1u2en(tp, true);
134f98bc 3585 r8153_mac_clk_spd(tp, false);
ee4761c1 3586 usb_enable_lpm(tp->udev);
43779f8d 3587
e31f6367 3588 /* rx aggregation */
3589 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
3590 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
3591 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
43779f8d 3592
4f1d4d54 3593 rtl_tally_reset(tp);
49d10347 3594
3595 switch (tp->udev->speed) {
3596 case USB_SPEED_SUPER:
3597 case USB_SPEED_SUPER_PLUS:
3598 tp->coalesce = COALESCE_SUPER;
3599 break;
3600 case USB_SPEED_HIGH:
3601 tp->coalesce = COALESCE_HIGH;
3602 break;
3603 default:
3604 tp->coalesce = COALESCE_SLOW;
3605 break;
3606 }
43779f8d 3607}
3608
e501139a 3609static int rtl8152_pre_reset(struct usb_interface *intf)
3610{
3611 struct r8152 *tp = usb_get_intfdata(intf);
3612 struct net_device *netdev;
3613
3614 if (!tp)
3615 return 0;
3616
3617 netdev = tp->netdev;
3618 if (!netif_running(netdev))
3619 return 0;
3620
de9bf29d 3621 netif_stop_queue(netdev);
e501139a 3622 napi_disable(&tp->napi);
3623 clear_bit(WORK_ENABLE, &tp->flags);
3624 usb_kill_urb(tp->intr_urb);
3625 cancel_delayed_work_sync(&tp->schedule);
3626 if (netif_carrier_ok(netdev)) {
e501139a 3627 mutex_lock(&tp->control);
3628 tp->rtl_ops.disable(tp);
3629 mutex_unlock(&tp->control);
3630 }
3631
3632 return 0;
3633}
3634
3635static int rtl8152_post_reset(struct usb_interface *intf)
3636{
3637 struct r8152 *tp = usb_get_intfdata(intf);
3638 struct net_device *netdev;
3639
3640 if (!tp)
3641 return 0;
3642
3643 netdev = tp->netdev;
3644 if (!netif_running(netdev))
3645 return 0;
3646
3647 set_bit(WORK_ENABLE, &tp->flags);
3648 if (netif_carrier_ok(netdev)) {
3649 mutex_lock(&tp->control);
3650 tp->rtl_ops.enable(tp);
2c561b2b 3651 rtl_start_rx(tp);
e501139a 3652 rtl8152_set_rx_mode(netdev);
3653 mutex_unlock(&tp->control);
e501139a 3654 }
3655
3656 napi_enable(&tp->napi);
de9bf29d 3657 netif_wake_queue(netdev);
2c561b2b 3658 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
e501139a 3659
7489bdad 3660 if (!list_empty(&tp->rx_done))
3661 napi_schedule(&tp->napi);
e501139a 3662
3663 return 0;
43779f8d 3664}
3665
2dd49e0f 3666static bool delay_autosuspend(struct r8152 *tp)
3667{
3668 bool sw_linking = !!netif_carrier_ok(tp->netdev);
3669 bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
3670
3671 /* This means a linking change occurs and the driver doesn't detect it,
3672 * yet. If the driver has disabled tx/rx and hw is linking on, the
3673 * device wouldn't wake up by receiving any packet.
3674 */
3675 if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
3676 return true;
3677
3678 /* If the linking down is occurred by nway, the device may miss the
3679 * linking change event. And it wouldn't wake when linking on.
3680 */
3681 if (!sw_linking && tp->rtl_ops.in_nway(tp))
3682 return true;
6a0b76c0 3683 else if (!skb_queue_empty(&tp->tx_queue))
3684 return true;
2dd49e0f 3685 else
3686 return false;
3687}
3688
a9c54ad2 3689static int rtl8152_runtime_suspend(struct r8152 *tp)
ac718b69 3690{
6cc69f2a 3691 struct net_device *netdev = tp->netdev;
3692 int ret = 0;
ac718b69 3693
26afec39 3694 set_bit(SELECTIVE_SUSPEND, &tp->flags);
3695 smp_mb__after_atomic();
3696
8fb28061 3697 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
75dc692e 3698 u32 rcr = 0;
3699
8fb28061 3700 if (delay_autosuspend(tp)) {
26afec39 3701 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
3702 smp_mb__after_atomic();
6cc69f2a 3703 ret = -EBUSY;
3704 goto out1;
3705 }
3706
75dc692e 3707 if (netif_carrier_ok(netdev)) {
3708 u32 ocp_data;
3709
3710 rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3711 ocp_data = rcr & ~RCR_ACPT_ALL;
3712 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3713 rxdy_gated_en(tp, true);
3714 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA,
3715 PLA_OOB_CTRL);
3716 if (!(ocp_data & RXFIFO_EMPTY)) {
3717 rxdy_gated_en(tp, false);
3718 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
26afec39 3719 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
3720 smp_mb__after_atomic();
75dc692e 3721 ret = -EBUSY;
3722 goto out1;
3723 }
3724 }
3725
8fb28061 3726 clear_bit(WORK_ENABLE, &tp->flags);
3727 usb_kill_urb(tp->intr_urb);
75dc692e 3728
8fb28061 3729 tp->rtl_ops.autosuspend_en(tp, true);
75dc692e 3730
3731 if (netif_carrier_ok(netdev)) {
ce594e98 3732 struct napi_struct *napi = &tp->napi;
3733
3734 napi_disable(napi);
75dc692e 3735 rtl_stop_rx(tp);
3736 rxdy_gated_en(tp, false);
3737 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
ce594e98 3738 napi_enable(napi);
75dc692e 3739 }
6cc69f2a 3740 }
ac718b69 3741
8fb28061 3742out1:
3743 return ret;
3744}
3745
3746static int rtl8152_system_suspend(struct r8152 *tp)
3747{
3748 struct net_device *netdev = tp->netdev;
3749 int ret = 0;
3750
3751 netif_device_detach(netdev);
3752
e3bd1a81 3753 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
ce594e98 3754 struct napi_struct *napi = &tp->napi;
3755
ac718b69 3756 clear_bit(WORK_ENABLE, &tp->flags);
40a82917 3757 usb_kill_urb(tp->intr_urb);
ce594e98 3758 napi_disable(napi);
8fb28061 3759 cancel_delayed_work_sync(&tp->schedule);
3760 tp->rtl_ops.down(tp);
ce594e98 3761 napi_enable(napi);
ac718b69 3762 }
8fb28061 3763
3764 return ret;
3765}
3766
3767static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
3768{
3769 struct r8152 *tp = usb_get_intfdata(intf);
3770 int ret;
3771
3772 mutex_lock(&tp->control);
3773
3774 if (PMSG_IS_AUTO(message))
a9c54ad2 3775 ret = rtl8152_runtime_suspend(tp);
8fb28061 3776 else
3777 ret = rtl8152_system_suspend(tp);
3778
b5403273 3779 mutex_unlock(&tp->control);
3780
6cc69f2a 3781 return ret;
ac718b69 3782}
3783
3784static int rtl8152_resume(struct usb_interface *intf)
3785{
3786 struct r8152 *tp = usb_get_intfdata(intf);
ce594e98 3787 struct net_device *netdev = tp->netdev;
ac718b69 3788
b5403273 3789 mutex_lock(&tp->control);
3790
befb2de1 3791 if (!test_bit(SELECTIVE_SUSPEND, &tp->flags))
ce594e98 3792 netif_device_attach(netdev);
9a4be1bd 3793
ce594e98 3794 if (netif_running(netdev) && netdev->flags & IFF_UP) {
9a4be1bd 3795 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
ce594e98 3796 struct napi_struct *napi = &tp->napi;
3797
2609af19 3798 tp->rtl_ops.autosuspend_en(tp, false);
ce594e98 3799 napi_disable(napi);
445f7f4d 3800 set_bit(WORK_ENABLE, &tp->flags);
6f14f443 3801 if (netif_carrier_ok(netdev)) {
2f25abe6 3802 if (rtl8152_get_speed(tp) & LINK_STATUS) {
3803 rtl_start_rx(tp);
3804 } else {
6f14f443 3805 netif_carrier_off(netdev);
2f25abe6 3806 tp->rtl_ops.disable(tp);
6f14f443 3807 netif_info(tp, link, netdev,
2f25abe6 3808 "linking down\n");
3809 }
3810 }
ce594e98 3811 napi_enable(napi);
26afec39 3812 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
3813 smp_mb__after_atomic();
7489bdad 3814 if (!list_empty(&tp->rx_done))
3815 napi_schedule(&tp->napi);
9a4be1bd 3816 } else {
3817 tp->rtl_ops.up(tp);
ce594e98 3818 netif_carrier_off(netdev);
445f7f4d 3819 set_bit(WORK_ENABLE, &tp->flags);
9a4be1bd 3820 }
40a82917 3821 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
923e1ee3 3822 } else if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
ce594e98 3823 if (netdev->flags & IFF_UP)
2609af19 3824 tp->rtl_ops.autosuspend_en(tp, false);
923e1ee3 3825 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
ac718b69 3826 }
3827
b5403273 3828 mutex_unlock(&tp->control);
3829
ac718b69 3830 return 0;
3831}
3832
7ec2541a 3833static int rtl8152_reset_resume(struct usb_interface *intf)
3834{
3835 struct r8152 *tp = usb_get_intfdata(intf);
3836
3837 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
befb2de1 3838 mutex_lock(&tp->control);
3839 tp->rtl_ops.init(tp);
3840 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
3841 mutex_unlock(&tp->control);
7ec2541a 3842 return rtl8152_resume(intf);
3843}
3844
21ff2e89 3845static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3846{
3847 struct r8152 *tp = netdev_priv(dev);
3848
9a4be1bd 3849 if (usb_autopm_get_interface(tp->intf) < 0)
3850 return;
3851
7daed8dc 3852 if (!rtl_can_wakeup(tp)) {
3853 wol->supported = 0;
3854 wol->wolopts = 0;
3855 } else {
3856 mutex_lock(&tp->control);
3857 wol->supported = WAKE_ANY;
3858 wol->wolopts = __rtl_get_wol(tp);
3859 mutex_unlock(&tp->control);
3860 }
b5403273 3861
9a4be1bd 3862 usb_autopm_put_interface(tp->intf);
21ff2e89 3863}
3864
3865static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3866{
3867 struct r8152 *tp = netdev_priv(dev);
9a4be1bd 3868 int ret;
3869
7daed8dc 3870 if (!rtl_can_wakeup(tp))
3871 return -EOPNOTSUPP;
3872
9a4be1bd 3873 ret = usb_autopm_get_interface(tp->intf);
3874 if (ret < 0)
3875 goto out_set_wol;
21ff2e89 3876
b5403273 3877 mutex_lock(&tp->control);
3878
21ff2e89 3879 __rtl_set_wol(tp, wol->wolopts);
3880 tp->saved_wolopts = wol->wolopts & WAKE_ANY;
3881
b5403273 3882 mutex_unlock(&tp->control);
3883
9a4be1bd 3884 usb_autopm_put_interface(tp->intf);
3885
3886out_set_wol:
3887 return ret;
21ff2e89 3888}
3889
a5ec27c1 3890static u32 rtl8152_get_msglevel(struct net_device *dev)
3891{
3892 struct r8152 *tp = netdev_priv(dev);
3893
3894 return tp->msg_enable;
3895}
3896
3897static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
3898{
3899 struct r8152 *tp = netdev_priv(dev);
3900
3901 tp->msg_enable = value;
3902}
3903
ac718b69 3904static void rtl8152_get_drvinfo(struct net_device *netdev,
3905 struct ethtool_drvinfo *info)
3906{
3907 struct r8152 *tp = netdev_priv(netdev);
3908
b0b46c77 3909 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
3910 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
ac718b69 3911 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
3912}
3913
3914static
06144dcf
PR
3915int rtl8152_get_link_ksettings(struct net_device *netdev,
3916 struct ethtool_link_ksettings *cmd)
ac718b69 3917{
3918 struct r8152 *tp = netdev_priv(netdev);
8d4a4d72 3919 int ret;
ac718b69 3920
3921 if (!tp->mii.mdio_read)
3922 return -EOPNOTSUPP;
3923
8d4a4d72 3924 ret = usb_autopm_get_interface(tp->intf);
3925 if (ret < 0)
3926 goto out;
3927
b5403273 3928 mutex_lock(&tp->control);
3929
82c01a84 3930 mii_ethtool_get_link_ksettings(&tp->mii, cmd);
8d4a4d72 3931
b5403273 3932 mutex_unlock(&tp->control);
3933
8d4a4d72 3934 usb_autopm_put_interface(tp->intf);
3935
3936out:
3937 return ret;
ac718b69 3938}
3939
06144dcf
PR
3940static int rtl8152_set_link_ksettings(struct net_device *dev,
3941 const struct ethtool_link_ksettings *cmd)
ac718b69 3942{
3943 struct r8152 *tp = netdev_priv(dev);
9a4be1bd 3944 int ret;
3945
3946 ret = usb_autopm_get_interface(tp->intf);
3947 if (ret < 0)
3948 goto out;
ac718b69 3949
b5403273 3950 mutex_lock(&tp->control);
3951
06144dcf
PR
3952 ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed,
3953 cmd->base.duplex);
aa7e26b6 3954 if (!ret) {
06144dcf
PR
3955 tp->autoneg = cmd->base.autoneg;
3956 tp->speed = cmd->base.speed;
3957 tp->duplex = cmd->base.duplex;
aa7e26b6 3958 }
9a4be1bd 3959
b5403273 3960 mutex_unlock(&tp->control);
3961
9a4be1bd 3962 usb_autopm_put_interface(tp->intf);
3963
3964out:
3965 return ret;
ac718b69 3966}
3967
4f1d4d54 3968static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
3969 "tx_packets",
3970 "rx_packets",
3971 "tx_errors",
3972 "rx_errors",
3973 "rx_missed",
3974 "align_errors",
3975 "tx_single_collisions",
3976 "tx_multi_collisions",
3977 "rx_unicast",
3978 "rx_broadcast",
3979 "rx_multicast",
3980 "tx_aborted",
3981 "tx_underrun",
3982};
3983
3984static int rtl8152_get_sset_count(struct net_device *dev, int sset)
3985{
3986 switch (sset) {
3987 case ETH_SS_STATS:
3988 return ARRAY_SIZE(rtl8152_gstrings);
3989 default:
3990 return -EOPNOTSUPP;
3991 }
3992}
3993
3994static void rtl8152_get_ethtool_stats(struct net_device *dev,
3995 struct ethtool_stats *stats, u64 *data)
3996{
3997 struct r8152 *tp = netdev_priv(dev);
3998 struct tally_counter tally;
3999
0b030244 4000 if (usb_autopm_get_interface(tp->intf) < 0)
4001 return;
4002
4f1d4d54 4003 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
4004
0b030244 4005 usb_autopm_put_interface(tp->intf);
4006
4f1d4d54 4007 data[0] = le64_to_cpu(tally.tx_packets);
4008 data[1] = le64_to_cpu(tally.rx_packets);
4009 data[2] = le64_to_cpu(tally.tx_errors);
4010 data[3] = le32_to_cpu(tally.rx_errors);
4011 data[4] = le16_to_cpu(tally.rx_missed);
4012 data[5] = le16_to_cpu(tally.align_errors);
4013 data[6] = le32_to_cpu(tally.tx_one_collision);
4014 data[7] = le32_to_cpu(tally.tx_multi_collision);
4015 data[8] = le64_to_cpu(tally.rx_unicast);
4016 data[9] = le64_to_cpu(tally.rx_broadcast);
4017 data[10] = le32_to_cpu(tally.rx_multicast);
4018 data[11] = le16_to_cpu(tally.tx_aborted);
f37119c5 4019 data[12] = le16_to_cpu(tally.tx_underrun);
4f1d4d54 4020}
4021
4022static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
4023{
4024 switch (stringset) {
4025 case ETH_SS_STATS:
4026 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
4027 break;
4028 }
4029}
4030
df35d283 4031static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
4032{
4033 u32 ocp_data, lp, adv, supported = 0;
4034 u16 val;
4035
4036 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
4037 supported = mmd_eee_cap_to_ethtool_sup_t(val);
4038
4039 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
4040 adv = mmd_eee_adv_to_ethtool_adv_t(val);
4041
4042 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
4043 lp = mmd_eee_adv_to_ethtool_adv_t(val);
4044
4045 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4046 ocp_data &= EEE_RX_EN | EEE_TX_EN;
4047
4048 eee->eee_enabled = !!ocp_data;
4049 eee->eee_active = !!(supported & adv & lp);
4050 eee->supported = supported;
4051 eee->advertised = adv;
4052 eee->lp_advertised = lp;
4053
4054 return 0;
4055}
4056
4057static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
4058{
4059 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
4060
4061 r8152_eee_en(tp, eee->eee_enabled);
4062
4063 if (!eee->eee_enabled)
4064 val = 0;
4065
4066 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
4067
4068 return 0;
4069}
4070
4071static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
4072{
4073 u32 ocp_data, lp, adv, supported = 0;
4074 u16 val;
4075
4076 val = ocp_reg_read(tp, OCP_EEE_ABLE);
4077 supported = mmd_eee_cap_to_ethtool_sup_t(val);
4078
4079 val = ocp_reg_read(tp, OCP_EEE_ADV);
4080 adv = mmd_eee_adv_to_ethtool_adv_t(val);
4081
4082 val = ocp_reg_read(tp, OCP_EEE_LPABLE);
4083 lp = mmd_eee_adv_to_ethtool_adv_t(val);
4084
4085 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4086 ocp_data &= EEE_RX_EN | EEE_TX_EN;
4087
4088 eee->eee_enabled = !!ocp_data;
4089 eee->eee_active = !!(supported & adv & lp);
4090 eee->supported = supported;
4091 eee->advertised = adv;
4092 eee->lp_advertised = lp;
4093
4094 return 0;
4095}
4096
4097static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
4098{
4099 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
4100
4101 r8153_eee_en(tp, eee->eee_enabled);
4102
4103 if (!eee->eee_enabled)
4104 val = 0;
4105
4106 ocp_reg_write(tp, OCP_EEE_ADV, val);
4107
4108 return 0;
4109}
4110
4111static int
4112rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
4113{
4114 struct r8152 *tp = netdev_priv(net);
4115 int ret;
4116
4117 ret = usb_autopm_get_interface(tp->intf);
4118 if (ret < 0)
4119 goto out;
4120
b5403273 4121 mutex_lock(&tp->control);
4122
df35d283 4123 ret = tp->rtl_ops.eee_get(tp, edata);
4124
b5403273 4125 mutex_unlock(&tp->control);
4126
df35d283 4127 usb_autopm_put_interface(tp->intf);
4128
4129out:
4130 return ret;
4131}
4132
4133static int
4134rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
4135{
4136 struct r8152 *tp = netdev_priv(net);
4137 int ret;
4138
4139 ret = usb_autopm_get_interface(tp->intf);
4140 if (ret < 0)
4141 goto out;
4142
b5403273 4143 mutex_lock(&tp->control);
4144
df35d283 4145 ret = tp->rtl_ops.eee_set(tp, edata);
9d31a7b9 4146 if (!ret)
4147 ret = mii_nway_restart(&tp->mii);
df35d283 4148
b5403273 4149 mutex_unlock(&tp->control);
4150
df35d283 4151 usb_autopm_put_interface(tp->intf);
4152
4153out:
4154 return ret;
4155}
4156
8884f507 4157static int rtl8152_nway_reset(struct net_device *dev)
4158{
4159 struct r8152 *tp = netdev_priv(dev);
4160 int ret;
4161
4162 ret = usb_autopm_get_interface(tp->intf);
4163 if (ret < 0)
4164 goto out;
4165
4166 mutex_lock(&tp->control);
4167
4168 ret = mii_nway_restart(&tp->mii);
4169
4170 mutex_unlock(&tp->control);
4171
4172 usb_autopm_put_interface(tp->intf);
4173
4174out:
4175 return ret;
4176}
4177
efb3dd88 4178static int rtl8152_get_coalesce(struct net_device *netdev,
4179 struct ethtool_coalesce *coalesce)
4180{
4181 struct r8152 *tp = netdev_priv(netdev);
4182
4183 switch (tp->version) {
4184 case RTL_VER_01:
4185 case RTL_VER_02:
4186 return -EOPNOTSUPP;
4187 default:
4188 break;
4189 }
4190
4191 coalesce->rx_coalesce_usecs = tp->coalesce;
4192
4193 return 0;
4194}
4195
4196static int rtl8152_set_coalesce(struct net_device *netdev,
4197 struct ethtool_coalesce *coalesce)
4198{
4199 struct r8152 *tp = netdev_priv(netdev);
4200 int ret;
4201
4202 switch (tp->version) {
4203 case RTL_VER_01:
4204 case RTL_VER_02:
4205 return -EOPNOTSUPP;
4206 default:
4207 break;
4208 }
4209
4210 if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
4211 return -EINVAL;
4212
4213 ret = usb_autopm_get_interface(tp->intf);
4214 if (ret < 0)
4215 return ret;
4216
4217 mutex_lock(&tp->control);
4218
4219 if (tp->coalesce != coalesce->rx_coalesce_usecs) {
4220 tp->coalesce = coalesce->rx_coalesce_usecs;
4221
4222 if (netif_running(tp->netdev) && netif_carrier_ok(netdev))
4223 r8153_set_rx_early_timeout(tp);
4224 }
4225
4226 mutex_unlock(&tp->control);
4227
4228 usb_autopm_put_interface(tp->intf);
4229
4230 return ret;
4231}
4232
407a471d 4233static const struct ethtool_ops ops = {
ac718b69 4234 .get_drvinfo = rtl8152_get_drvinfo,
ac718b69 4235 .get_link = ethtool_op_get_link,
8884f507 4236 .nway_reset = rtl8152_nway_reset,
a5ec27c1 4237 .get_msglevel = rtl8152_get_msglevel,
4238 .set_msglevel = rtl8152_set_msglevel,
21ff2e89 4239 .get_wol = rtl8152_get_wol,
4240 .set_wol = rtl8152_set_wol,
4f1d4d54 4241 .get_strings = rtl8152_get_strings,
4242 .get_sset_count = rtl8152_get_sset_count,
4243 .get_ethtool_stats = rtl8152_get_ethtool_stats,
efb3dd88 4244 .get_coalesce = rtl8152_get_coalesce,
4245 .set_coalesce = rtl8152_set_coalesce,
df35d283 4246 .get_eee = rtl_ethtool_get_eee,
4247 .set_eee = rtl_ethtool_set_eee,
06144dcf
PR
4248 .get_link_ksettings = rtl8152_get_link_ksettings,
4249 .set_link_ksettings = rtl8152_set_link_ksettings,
ac718b69 4250};
4251
4252static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
4253{
4254 struct r8152 *tp = netdev_priv(netdev);
4255 struct mii_ioctl_data *data = if_mii(rq);
9a4be1bd 4256 int res;
4257
6871438c 4258 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4259 return -ENODEV;
4260
9a4be1bd 4261 res = usb_autopm_get_interface(tp->intf);
4262 if (res < 0)
4263 goto out;
ac718b69 4264
4265 switch (cmd) {
4266 case SIOCGMIIPHY:
4267 data->phy_id = R8152_PHY_ID; /* Internal PHY */
4268 break;
4269
4270 case SIOCGMIIREG:
b5403273 4271 mutex_lock(&tp->control);
ac718b69 4272 data->val_out = r8152_mdio_read(tp, data->reg_num);
b5403273 4273 mutex_unlock(&tp->control);
ac718b69 4274 break;
4275
4276 case SIOCSMIIREG:
4277 if (!capable(CAP_NET_ADMIN)) {
4278 res = -EPERM;
4279 break;
4280 }
b5403273 4281 mutex_lock(&tp->control);
ac718b69 4282 r8152_mdio_write(tp, data->reg_num, data->val_in);
b5403273 4283 mutex_unlock(&tp->control);
ac718b69 4284 break;
4285
4286 default:
4287 res = -EOPNOTSUPP;
4288 }
4289
9a4be1bd 4290 usb_autopm_put_interface(tp->intf);
4291
4292out:
ac718b69 4293 return res;
4294}
4295
69b4b7a4 4296static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
4297{
4298 struct r8152 *tp = netdev_priv(dev);
396e2e23 4299 int ret;
69b4b7a4 4300
4301 switch (tp->version) {
4302 case RTL_VER_01:
4303 case RTL_VER_02:
a52ad514
JW
4304 dev->mtu = new_mtu;
4305 return 0;
69b4b7a4 4306 default:
4307 break;
4308 }
4309
396e2e23 4310 ret = usb_autopm_get_interface(tp->intf);
4311 if (ret < 0)
4312 return ret;
4313
4314 mutex_lock(&tp->control);
4315
69b4b7a4 4316 dev->mtu = new_mtu;
4317
210c4f70 4318 if (netif_running(dev)) {
4319 u32 rms = new_mtu + VLAN_ETH_HLEN + CRC_SIZE;
4320
4321 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rms);
4322
4323 if (netif_carrier_ok(dev))
4324 r8153_set_rx_early_size(tp);
4325 }
396e2e23 4326
4327 mutex_unlock(&tp->control);
4328
4329 usb_autopm_put_interface(tp->intf);
4330
4331 return ret;
69b4b7a4 4332}
4333
ac718b69 4334static const struct net_device_ops rtl8152_netdev_ops = {
4335 .ndo_open = rtl8152_open,
4336 .ndo_stop = rtl8152_close,
4337 .ndo_do_ioctl = rtl8152_ioctl,
4338 .ndo_start_xmit = rtl8152_start_xmit,
4339 .ndo_tx_timeout = rtl8152_tx_timeout,
c5554298 4340 .ndo_set_features = rtl8152_set_features,
ac718b69 4341 .ndo_set_rx_mode = rtl8152_set_rx_mode,
4342 .ndo_set_mac_address = rtl8152_set_mac_address,
69b4b7a4 4343 .ndo_change_mtu = rtl8152_change_mtu,
ac718b69 4344 .ndo_validate_addr = eth_validate_addr,
a5e31255 4345 .ndo_features_check = rtl8152_features_check,
ac718b69 4346};
4347
e3fe0b1a 4348static void rtl8152_unload(struct r8152 *tp)
4349{
6871438c 4350 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4351 return;
4352
00a5e360 4353 if (tp->version != RTL_VER_01)
4354 r8152_power_cut_en(tp, true);
e3fe0b1a 4355}
4356
43779f8d 4357static void rtl8153_unload(struct r8152 *tp)
4358{
6871438c 4359 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4360 return;
4361
49be1723 4362 r8153_power_cut_en(tp, false);
43779f8d 4363}
4364
55b65475 4365static int rtl_ops_init(struct r8152 *tp)
c81229c9 4366{
4367 struct rtl_ops *ops = &tp->rtl_ops;
55b65475 4368 int ret = 0;
4369
4370 switch (tp->version) {
4371 case RTL_VER_01:
4372 case RTL_VER_02:
4373 ops->init = r8152b_init;
4374 ops->enable = rtl8152_enable;
4375 ops->disable = rtl8152_disable;
4376 ops->up = rtl8152_up;
4377 ops->down = rtl8152_down;
4378 ops->unload = rtl8152_unload;
4379 ops->eee_get = r8152_get_eee;
4380 ops->eee_set = r8152_set_eee;
2dd49e0f 4381 ops->in_nway = rtl8152_in_nway;
a028a9e0 4382 ops->hw_phy_cfg = r8152b_hw_phy_cfg;
2609af19 4383 ops->autosuspend_en = rtl_runtime_suspend_enable;
43779f8d 4384 break;
4385
55b65475 4386 case RTL_VER_03:
4387 case RTL_VER_04:
4388 case RTL_VER_05:
fb02eb4a 4389 case RTL_VER_06:
55b65475 4390 ops->init = r8153_init;
4391 ops->enable = rtl8153_enable;
4392 ops->disable = rtl8153_disable;
4393 ops->up = rtl8153_up;
4394 ops->down = rtl8153_down;
4395 ops->unload = rtl8153_unload;
4396 ops->eee_get = r8153_get_eee;
4397 ops->eee_set = r8153_set_eee;
2dd49e0f 4398 ops->in_nway = rtl8153_in_nway;
a028a9e0 4399 ops->hw_phy_cfg = r8153_hw_phy_cfg;
2609af19 4400 ops->autosuspend_en = rtl8153_runtime_enable;
c81229c9 4401 break;
4402
4403 default:
55b65475 4404 ret = -ENODEV;
4405 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
c81229c9 4406 break;
4407 }
4408
4409 return ret;
4410}
4411
33928eed 4412static u8 rtl_get_version(struct usb_interface *intf)
4413{
4414 struct usb_device *udev = interface_to_usbdev(intf);
4415 u32 ocp_data = 0;
4416 __le32 *tmp;
4417 u8 version;
4418 int ret;
4419
4420 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
4421 if (!tmp)
4422 return 0;
4423
4424 ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
4425 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
4426 PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 500);
4427 if (ret > 0)
4428 ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK;
4429
4430 kfree(tmp);
4431
4432 switch (ocp_data) {
4433 case 0x4c00:
4434 version = RTL_VER_01;
4435 break;
4436 case 0x4c10:
4437 version = RTL_VER_02;
4438 break;
4439 case 0x5c00:
4440 version = RTL_VER_03;
4441 break;
4442 case 0x5c10:
4443 version = RTL_VER_04;
4444 break;
4445 case 0x5c20:
4446 version = RTL_VER_05;
4447 break;
4448 case 0x5c30:
4449 version = RTL_VER_06;
4450 break;
4451 default:
4452 version = RTL_VER_UNKNOWN;
4453 dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data);
4454 break;
4455 }
4456
eb3c28c1
ON
4457 dev_dbg(&intf->dev, "Detected version 0x%04x\n", version);
4458
33928eed 4459 return version;
4460}
4461
ac718b69 4462static int rtl8152_probe(struct usb_interface *intf,
4463 const struct usb_device_id *id)
4464{
4465 struct usb_device *udev = interface_to_usbdev(intf);
33928eed 4466 u8 version = rtl_get_version(intf);
ac718b69 4467 struct r8152 *tp;
4468 struct net_device *netdev;
ebc2ec48 4469 int ret;
ac718b69 4470
33928eed 4471 if (version == RTL_VER_UNKNOWN)
4472 return -ENODEV;
4473
10c32717 4474 if (udev->actconfig->desc.bConfigurationValue != 1) {
4475 usb_driver_set_configuration(udev, 1);
4476 return -ENODEV;
4477 }
4478
4479 usb_reset_device(udev);
ac718b69 4480 netdev = alloc_etherdev(sizeof(struct r8152));
4481 if (!netdev) {
4a8deae2 4482 dev_err(&intf->dev, "Out of memory\n");
ac718b69 4483 return -ENOMEM;
4484 }
4485
ebc2ec48 4486 SET_NETDEV_DEV(netdev, &intf->dev);
ac718b69 4487 tp = netdev_priv(netdev);
4488 tp->msg_enable = 0x7FFF;
4489
e3ad412a 4490 tp->udev = udev;
4491 tp->netdev = netdev;
4492 tp->intf = intf;
33928eed 4493 tp->version = version;
4494
4495 switch (version) {
4496 case RTL_VER_01:
4497 case RTL_VER_02:
4498 tp->mii.supports_gmii = 0;
4499 break;
4500 default:
4501 tp->mii.supports_gmii = 1;
4502 break;
4503 }
e3ad412a 4504
55b65475 4505 ret = rtl_ops_init(tp);
31ca1dec 4506 if (ret)
4507 goto out;
c81229c9 4508
b5403273 4509 mutex_init(&tp->control);
ac718b69 4510 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
a028a9e0 4511 INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
ac718b69 4512
ac718b69 4513 netdev->netdev_ops = &rtl8152_netdev_ops;
4514 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
5bd23881 4515
60c89071 4516 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
6128d1bb 4517 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
c5554298 4518 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
4519 NETIF_F_HW_VLAN_CTAG_TX;
60c89071 4520 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
6128d1bb 4521 NETIF_F_TSO | NETIF_F_FRAGLIST |
c5554298 4522 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
ccc39faf 4523 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
c5554298 4524 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
4525 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
4526 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
db8515ef 4527
19c0f40d 4528 if (tp->version == RTL_VER_01) {
4529 netdev->features &= ~NETIF_F_RXCSUM;
4530 netdev->hw_features &= ~NETIF_F_RXCSUM;
4531 }
4532
7ad24ea4 4533 netdev->ethtool_ops = &ops;
60c89071 4534 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
ac718b69 4535
f77f0aee
JW
4536 /* MTU range: 68 - 1500 or 9194 */
4537 netdev->min_mtu = ETH_MIN_MTU;
4538 switch (tp->version) {
4539 case RTL_VER_01:
4540 case RTL_VER_02:
4541 netdev->max_mtu = ETH_DATA_LEN;
4542 break;
4543 default:
4544 netdev->max_mtu = RTL8153_MAX_MTU;
4545 break;
4546 }
4547
ac718b69 4548 tp->mii.dev = netdev;
4549 tp->mii.mdio_read = read_mii_word;
4550 tp->mii.mdio_write = write_mii_word;
4551 tp->mii.phy_id_mask = 0x3f;
4552 tp->mii.reg_num_mask = 0x1f;
4553 tp->mii.phy_id = R8152_PHY_ID;
ac718b69 4554
aa7e26b6 4555 tp->autoneg = AUTONEG_ENABLE;
4556 tp->speed = tp->mii.supports_gmii ? SPEED_1000 : SPEED_100;
4557 tp->duplex = DUPLEX_FULL;
4558
9a4be1bd 4559 intf->needs_remote_wakeup = 1;
4560
c81229c9 4561 tp->rtl_ops.init(tp);
a028a9e0 4562 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
ac718b69 4563 set_ethernet_addr(tp);
4564
ac718b69 4565 usb_set_intfdata(intf, tp);
d823ab68 4566 netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
ac718b69 4567
ebc2ec48 4568 ret = register_netdev(netdev);
4569 if (ret != 0) {
4a8deae2 4570 netif_err(tp, probe, netdev, "couldn't register the device\n");
ebc2ec48 4571 goto out1;
ac718b69 4572 }
4573
7daed8dc 4574 if (!rtl_can_wakeup(tp))
4575 __rtl_set_wol(tp, 0);
4576
21ff2e89 4577 tp->saved_wolopts = __rtl_get_wol(tp);
4578 if (tp->saved_wolopts)
4579 device_set_wakeup_enable(&udev->dev, true);
4580 else
4581 device_set_wakeup_enable(&udev->dev, false);
4582
4a8deae2 4583 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
ac718b69 4584
4585 return 0;
4586
ac718b69 4587out1:
d823ab68 4588 netif_napi_del(&tp->napi);
ebc2ec48 4589 usb_set_intfdata(intf, NULL);
ac718b69 4590out:
4591 free_netdev(netdev);
ebc2ec48 4592 return ret;
ac718b69 4593}
4594
ac718b69 4595static void rtl8152_disconnect(struct usb_interface *intf)
4596{
4597 struct r8152 *tp = usb_get_intfdata(intf);
4598
4599 usb_set_intfdata(intf, NULL);
4600 if (tp) {
f561de33 4601 struct usb_device *udev = tp->udev;
4602
4603 if (udev->state == USB_STATE_NOTATTACHED)
4604 set_bit(RTL8152_UNPLUG, &tp->flags);
4605
d823ab68 4606 netif_napi_del(&tp->napi);
ac718b69 4607 unregister_netdev(tp->netdev);
a028a9e0 4608 cancel_delayed_work_sync(&tp->hw_phy_work);
c81229c9 4609 tp->rtl_ops.unload(tp);
ac718b69 4610 free_netdev(tp->netdev);
4611 }
4612}
4613
d9a28c5b 4614#define REALTEK_USB_DEVICE(vend, prod) \
4615 .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
4616 USB_DEVICE_ID_MATCH_INT_CLASS, \
4617 .idVendor = (vend), \
4618 .idProduct = (prod), \
4619 .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
4620}, \
4621{ \
4622 .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
4623 USB_DEVICE_ID_MATCH_DEVICE, \
4624 .idVendor = (vend), \
4625 .idProduct = (prod), \
4626 .bInterfaceClass = USB_CLASS_COMM, \
4627 .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
4628 .bInterfaceProtocol = USB_CDC_PROTO_NONE
4629
ac718b69 4630/* table of devices that work with this driver */
4631static struct usb_device_id rtl8152_table[] = {
d9a28c5b 4632 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
4633 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
d5b07ccc
RR
4634 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab)},
4635 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6)},
d9a28c5b 4636 {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
1006da19 4637 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)},
d248cafc 4638 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3062)},
4639 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3069)},
4640 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)},
4641 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x720c)},
4642 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7214)},
d065c3c1 4643 {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)},
ac718b69 4644 {}
4645};
4646
4647MODULE_DEVICE_TABLE(usb, rtl8152_table);
4648
4649static struct usb_driver rtl8152_driver = {
4650 .name = MODULENAME,
ebc2ec48 4651 .id_table = rtl8152_table,
ac718b69 4652 .probe = rtl8152_probe,
4653 .disconnect = rtl8152_disconnect,
ac718b69 4654 .suspend = rtl8152_suspend,
ebc2ec48 4655 .resume = rtl8152_resume,
7ec2541a 4656 .reset_resume = rtl8152_reset_resume,
e501139a 4657 .pre_reset = rtl8152_pre_reset,
4658 .post_reset = rtl8152_post_reset,
9a4be1bd 4659 .supports_autosuspend = 1,
a634782f 4660 .disable_hub_initiated_lpm = 1,
ac718b69 4661};
4662
b4236daa 4663module_usb_driver(rtl8152_driver);
ac718b69 4664
4665MODULE_AUTHOR(DRIVER_AUTHOR);
4666MODULE_DESCRIPTION(DRIVER_DESC);
4667MODULE_LICENSE("GPL");
c961e877 4668MODULE_VERSION(DRIVER_VERSION);