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ac718b69 | 1 | /* |
c7de7dec | 2 | * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved. |
ac718b69 | 3 | * |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * version 2 as published by the Free Software Foundation. | |
7 | * | |
8 | */ | |
9 | ||
ac718b69 | 10 | #include <linux/signal.h> |
11 | #include <linux/slab.h> | |
12 | #include <linux/module.h> | |
ac718b69 | 13 | #include <linux/netdevice.h> |
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/mii.h> | |
16 | #include <linux/ethtool.h> | |
17 | #include <linux/usb.h> | |
18 | #include <linux/crc32.h> | |
19 | #include <linux/if_vlan.h> | |
20 | #include <linux/uaccess.h> | |
ebc2ec48 | 21 | #include <linux/list.h> |
5bd23881 | 22 | #include <linux/ip.h> |
23 | #include <linux/ipv6.h> | |
6128d1bb | 24 | #include <net/ip6_checksum.h> |
ac718b69 | 25 | |
26 | /* Version Information */ | |
204c8704 | 27 | #define DRIVER_VERSION "v1.06.1 (2014/10/01)" |
ac718b69 | 28 | #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>" |
44d942a9 | 29 | #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters" |
ac718b69 | 30 | #define MODULENAME "r8152" |
31 | ||
32 | #define R8152_PHY_ID 32 | |
33 | ||
34 | #define PLA_IDR 0xc000 | |
35 | #define PLA_RCR 0xc010 | |
36 | #define PLA_RMS 0xc016 | |
37 | #define PLA_RXFIFO_CTRL0 0xc0a0 | |
38 | #define PLA_RXFIFO_CTRL1 0xc0a4 | |
39 | #define PLA_RXFIFO_CTRL2 0xc0a8 | |
40 | #define PLA_FMC 0xc0b4 | |
41 | #define PLA_CFG_WOL 0xc0b6 | |
43779f8d | 42 | #define PLA_TEREDO_CFG 0xc0bc |
ac718b69 | 43 | #define PLA_MAR 0xcd00 |
43779f8d | 44 | #define PLA_BACKUP 0xd000 |
ac718b69 | 45 | #define PAL_BDC_CR 0xd1a0 |
43779f8d | 46 | #define PLA_TEREDO_TIMER 0xd2cc |
47 | #define PLA_REALWOW_TIMER 0xd2e8 | |
ac718b69 | 48 | #define PLA_LEDSEL 0xdd90 |
49 | #define PLA_LED_FEATURE 0xdd92 | |
50 | #define PLA_PHYAR 0xde00 | |
43779f8d | 51 | #define PLA_BOOT_CTRL 0xe004 |
ac718b69 | 52 | #define PLA_GPHY_INTR_IMR 0xe022 |
53 | #define PLA_EEE_CR 0xe040 | |
54 | #define PLA_EEEP_CR 0xe080 | |
55 | #define PLA_MAC_PWR_CTRL 0xe0c0 | |
43779f8d | 56 | #define PLA_MAC_PWR_CTRL2 0xe0ca |
57 | #define PLA_MAC_PWR_CTRL3 0xe0cc | |
58 | #define PLA_MAC_PWR_CTRL4 0xe0ce | |
59 | #define PLA_WDT6_CTRL 0xe428 | |
ac718b69 | 60 | #define PLA_TCR0 0xe610 |
61 | #define PLA_TCR1 0xe612 | |
69b4b7a4 | 62 | #define PLA_MTPS 0xe615 |
ac718b69 | 63 | #define PLA_TXFIFO_CTRL 0xe618 |
4f1d4d54 | 64 | #define PLA_RSTTALLY 0xe800 |
ac718b69 | 65 | #define PLA_CR 0xe813 |
66 | #define PLA_CRWECR 0xe81c | |
21ff2e89 | 67 | #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */ |
68 | #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */ | |
ac718b69 | 69 | #define PLA_CONFIG5 0xe822 |
70 | #define PLA_PHY_PWR 0xe84c | |
71 | #define PLA_OOB_CTRL 0xe84f | |
72 | #define PLA_CPCR 0xe854 | |
73 | #define PLA_MISC_0 0xe858 | |
74 | #define PLA_MISC_1 0xe85a | |
75 | #define PLA_OCP_GPHY_BASE 0xe86c | |
4f1d4d54 | 76 | #define PLA_TALLYCNT 0xe890 |
ac718b69 | 77 | #define PLA_SFF_STS_7 0xe8de |
78 | #define PLA_PHYSTATUS 0xe908 | |
79 | #define PLA_BP_BA 0xfc26 | |
80 | #define PLA_BP_0 0xfc28 | |
81 | #define PLA_BP_1 0xfc2a | |
82 | #define PLA_BP_2 0xfc2c | |
83 | #define PLA_BP_3 0xfc2e | |
84 | #define PLA_BP_4 0xfc30 | |
85 | #define PLA_BP_5 0xfc32 | |
86 | #define PLA_BP_6 0xfc34 | |
87 | #define PLA_BP_7 0xfc36 | |
43779f8d | 88 | #define PLA_BP_EN 0xfc38 |
ac718b69 | 89 | |
43779f8d | 90 | #define USB_U2P3_CTRL 0xb460 |
ac718b69 | 91 | #define USB_DEV_STAT 0xb808 |
92 | #define USB_USB_CTRL 0xd406 | |
93 | #define USB_PHY_CTRL 0xd408 | |
94 | #define USB_TX_AGG 0xd40a | |
95 | #define USB_RX_BUF_TH 0xd40c | |
96 | #define USB_USB_TIMER 0xd428 | |
43779f8d | 97 | #define USB_RX_EARLY_AGG 0xd42c |
ac718b69 | 98 | #define USB_PM_CTRL_STATUS 0xd432 |
99 | #define USB_TX_DMA 0xd434 | |
43779f8d | 100 | #define USB_TOLERANCE 0xd490 |
101 | #define USB_LPM_CTRL 0xd41a | |
ac718b69 | 102 | #define USB_UPS_CTRL 0xd800 |
43779f8d | 103 | #define USB_MISC_0 0xd81a |
104 | #define USB_POWER_CUT 0xd80a | |
105 | #define USB_AFE_CTRL2 0xd824 | |
106 | #define USB_WDT11_CTRL 0xe43c | |
ac718b69 | 107 | #define USB_BP_BA 0xfc26 |
108 | #define USB_BP_0 0xfc28 | |
109 | #define USB_BP_1 0xfc2a | |
110 | #define USB_BP_2 0xfc2c | |
111 | #define USB_BP_3 0xfc2e | |
112 | #define USB_BP_4 0xfc30 | |
113 | #define USB_BP_5 0xfc32 | |
114 | #define USB_BP_6 0xfc34 | |
115 | #define USB_BP_7 0xfc36 | |
43779f8d | 116 | #define USB_BP_EN 0xfc38 |
ac718b69 | 117 | |
118 | /* OCP Registers */ | |
119 | #define OCP_ALDPS_CONFIG 0x2010 | |
120 | #define OCP_EEE_CONFIG1 0x2080 | |
121 | #define OCP_EEE_CONFIG2 0x2092 | |
122 | #define OCP_EEE_CONFIG3 0x2094 | |
ac244d3e | 123 | #define OCP_BASE_MII 0xa400 |
ac718b69 | 124 | #define OCP_EEE_AR 0xa41a |
125 | #define OCP_EEE_DATA 0xa41c | |
43779f8d | 126 | #define OCP_PHY_STATUS 0xa420 |
127 | #define OCP_POWER_CFG 0xa430 | |
128 | #define OCP_EEE_CFG 0xa432 | |
129 | #define OCP_SRAM_ADDR 0xa436 | |
130 | #define OCP_SRAM_DATA 0xa438 | |
131 | #define OCP_DOWN_SPEED 0xa442 | |
132 | #define OCP_EEE_CFG2 0xa5d0 | |
133 | #define OCP_ADC_CFG 0xbc06 | |
134 | ||
135 | /* SRAM Register */ | |
136 | #define SRAM_LPF_CFG 0x8012 | |
137 | #define SRAM_10M_AMP1 0x8080 | |
138 | #define SRAM_10M_AMP2 0x8082 | |
139 | #define SRAM_IMPEDANCE 0x8084 | |
ac718b69 | 140 | |
141 | /* PLA_RCR */ | |
142 | #define RCR_AAP 0x00000001 | |
143 | #define RCR_APM 0x00000002 | |
144 | #define RCR_AM 0x00000004 | |
145 | #define RCR_AB 0x00000008 | |
146 | #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB) | |
147 | ||
148 | /* PLA_RXFIFO_CTRL0 */ | |
149 | #define RXFIFO_THR1_NORMAL 0x00080002 | |
150 | #define RXFIFO_THR1_OOB 0x01800003 | |
151 | ||
152 | /* PLA_RXFIFO_CTRL1 */ | |
153 | #define RXFIFO_THR2_FULL 0x00000060 | |
154 | #define RXFIFO_THR2_HIGH 0x00000038 | |
155 | #define RXFIFO_THR2_OOB 0x0000004a | |
43779f8d | 156 | #define RXFIFO_THR2_NORMAL 0x00a0 |
ac718b69 | 157 | |
158 | /* PLA_RXFIFO_CTRL2 */ | |
159 | #define RXFIFO_THR3_FULL 0x00000078 | |
160 | #define RXFIFO_THR3_HIGH 0x00000048 | |
161 | #define RXFIFO_THR3_OOB 0x0000005a | |
43779f8d | 162 | #define RXFIFO_THR3_NORMAL 0x0110 |
ac718b69 | 163 | |
164 | /* PLA_TXFIFO_CTRL */ | |
165 | #define TXFIFO_THR_NORMAL 0x00400008 | |
43779f8d | 166 | #define TXFIFO_THR_NORMAL2 0x01000008 |
ac718b69 | 167 | |
168 | /* PLA_FMC */ | |
169 | #define FMC_FCR_MCU_EN 0x0001 | |
170 | ||
171 | /* PLA_EEEP_CR */ | |
172 | #define EEEP_CR_EEEP_TX 0x0002 | |
173 | ||
43779f8d | 174 | /* PLA_WDT6_CTRL */ |
175 | #define WDT6_SET_MODE 0x0010 | |
176 | ||
ac718b69 | 177 | /* PLA_TCR0 */ |
178 | #define TCR0_TX_EMPTY 0x0800 | |
179 | #define TCR0_AUTO_FIFO 0x0080 | |
180 | ||
181 | /* PLA_TCR1 */ | |
182 | #define VERSION_MASK 0x7cf0 | |
183 | ||
69b4b7a4 | 184 | /* PLA_MTPS */ |
185 | #define MTPS_JUMBO (12 * 1024 / 64) | |
186 | #define MTPS_DEFAULT (6 * 1024 / 64) | |
187 | ||
4f1d4d54 | 188 | /* PLA_RSTTALLY */ |
189 | #define TALLY_RESET 0x0001 | |
190 | ||
ac718b69 | 191 | /* PLA_CR */ |
192 | #define CR_RST 0x10 | |
193 | #define CR_RE 0x08 | |
194 | #define CR_TE 0x04 | |
195 | ||
196 | /* PLA_CRWECR */ | |
197 | #define CRWECR_NORAML 0x00 | |
198 | #define CRWECR_CONFIG 0xc0 | |
199 | ||
200 | /* PLA_OOB_CTRL */ | |
201 | #define NOW_IS_OOB 0x80 | |
202 | #define TXFIFO_EMPTY 0x20 | |
203 | #define RXFIFO_EMPTY 0x10 | |
204 | #define LINK_LIST_READY 0x02 | |
205 | #define DIS_MCU_CLROOB 0x01 | |
206 | #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY) | |
207 | ||
208 | /* PLA_MISC_1 */ | |
209 | #define RXDY_GATED_EN 0x0008 | |
210 | ||
211 | /* PLA_SFF_STS_7 */ | |
212 | #define RE_INIT_LL 0x8000 | |
213 | #define MCU_BORW_EN 0x4000 | |
214 | ||
215 | /* PLA_CPCR */ | |
216 | #define CPCR_RX_VLAN 0x0040 | |
217 | ||
218 | /* PLA_CFG_WOL */ | |
219 | #define MAGIC_EN 0x0001 | |
220 | ||
43779f8d | 221 | /* PLA_TEREDO_CFG */ |
222 | #define TEREDO_SEL 0x8000 | |
223 | #define TEREDO_WAKE_MASK 0x7f00 | |
224 | #define TEREDO_RS_EVENT_MASK 0x00fe | |
225 | #define OOB_TEREDO_EN 0x0001 | |
226 | ||
ac718b69 | 227 | /* PAL_BDC_CR */ |
228 | #define ALDPS_PROXY_MODE 0x0001 | |
229 | ||
21ff2e89 | 230 | /* PLA_CONFIG34 */ |
231 | #define LINK_ON_WAKE_EN 0x0010 | |
232 | #define LINK_OFF_WAKE_EN 0x0008 | |
233 | ||
ac718b69 | 234 | /* PLA_CONFIG5 */ |
21ff2e89 | 235 | #define BWF_EN 0x0040 |
236 | #define MWF_EN 0x0020 | |
237 | #define UWF_EN 0x0010 | |
ac718b69 | 238 | #define LAN_WAKE_EN 0x0002 |
239 | ||
240 | /* PLA_LED_FEATURE */ | |
241 | #define LED_MODE_MASK 0x0700 | |
242 | ||
243 | /* PLA_PHY_PWR */ | |
244 | #define TX_10M_IDLE_EN 0x0080 | |
245 | #define PFM_PWM_SWITCH 0x0040 | |
246 | ||
247 | /* PLA_MAC_PWR_CTRL */ | |
248 | #define D3_CLK_GATED_EN 0x00004000 | |
249 | #define MCU_CLK_RATIO 0x07010f07 | |
250 | #define MCU_CLK_RATIO_MASK 0x0f0f0f0f | |
43779f8d | 251 | #define ALDPS_SPDWN_RATIO 0x0f87 |
252 | ||
253 | /* PLA_MAC_PWR_CTRL2 */ | |
254 | #define EEE_SPDWN_RATIO 0x8007 | |
255 | ||
256 | /* PLA_MAC_PWR_CTRL3 */ | |
257 | #define PKT_AVAIL_SPDWN_EN 0x0100 | |
258 | #define SUSPEND_SPDWN_EN 0x0004 | |
259 | #define U1U2_SPDWN_EN 0x0002 | |
260 | #define L1_SPDWN_EN 0x0001 | |
261 | ||
262 | /* PLA_MAC_PWR_CTRL4 */ | |
263 | #define PWRSAVE_SPDWN_EN 0x1000 | |
264 | #define RXDV_SPDWN_EN 0x0800 | |
265 | #define TX10MIDLE_EN 0x0100 | |
266 | #define TP100_SPDWN_EN 0x0020 | |
267 | #define TP500_SPDWN_EN 0x0010 | |
268 | #define TP1000_SPDWN_EN 0x0008 | |
269 | #define EEE_SPDWN_EN 0x0001 | |
ac718b69 | 270 | |
271 | /* PLA_GPHY_INTR_IMR */ | |
272 | #define GPHY_STS_MSK 0x0001 | |
273 | #define SPEED_DOWN_MSK 0x0002 | |
274 | #define SPDWN_RXDV_MSK 0x0004 | |
275 | #define SPDWN_LINKCHG_MSK 0x0008 | |
276 | ||
277 | /* PLA_PHYAR */ | |
278 | #define PHYAR_FLAG 0x80000000 | |
279 | ||
280 | /* PLA_EEE_CR */ | |
281 | #define EEE_RX_EN 0x0001 | |
282 | #define EEE_TX_EN 0x0002 | |
283 | ||
43779f8d | 284 | /* PLA_BOOT_CTRL */ |
285 | #define AUTOLOAD_DONE 0x0002 | |
286 | ||
ac718b69 | 287 | /* USB_DEV_STAT */ |
288 | #define STAT_SPEED_MASK 0x0006 | |
289 | #define STAT_SPEED_HIGH 0x0000 | |
a3cc465d | 290 | #define STAT_SPEED_FULL 0x0002 |
ac718b69 | 291 | |
292 | /* USB_TX_AGG */ | |
293 | #define TX_AGG_MAX_THRESHOLD 0x03 | |
294 | ||
295 | /* USB_RX_BUF_TH */ | |
43779f8d | 296 | #define RX_THR_SUPPER 0x0c350180 |
8e1f51bd | 297 | #define RX_THR_HIGH 0x7a120180 |
43779f8d | 298 | #define RX_THR_SLOW 0xffff0180 |
ac718b69 | 299 | |
300 | /* USB_TX_DMA */ | |
301 | #define TEST_MODE_DISABLE 0x00000001 | |
302 | #define TX_SIZE_ADJUST1 0x00000100 | |
303 | ||
304 | /* USB_UPS_CTRL */ | |
305 | #define POWER_CUT 0x0100 | |
306 | ||
307 | /* USB_PM_CTRL_STATUS */ | |
8e1f51bd | 308 | #define RESUME_INDICATE 0x0001 |
ac718b69 | 309 | |
310 | /* USB_USB_CTRL */ | |
311 | #define RX_AGG_DISABLE 0x0010 | |
312 | ||
43779f8d | 313 | /* USB_U2P3_CTRL */ |
314 | #define U2P3_ENABLE 0x0001 | |
315 | ||
316 | /* USB_POWER_CUT */ | |
317 | #define PWR_EN 0x0001 | |
318 | #define PHASE2_EN 0x0008 | |
319 | ||
320 | /* USB_MISC_0 */ | |
321 | #define PCUT_STATUS 0x0001 | |
322 | ||
323 | /* USB_RX_EARLY_AGG */ | |
324 | #define EARLY_AGG_SUPPER 0x0e832981 | |
325 | #define EARLY_AGG_HIGH 0x0e837a12 | |
326 | #define EARLY_AGG_SLOW 0x0e83ffff | |
327 | ||
328 | /* USB_WDT11_CTRL */ | |
329 | #define TIMER11_EN 0x0001 | |
330 | ||
331 | /* USB_LPM_CTRL */ | |
332 | #define LPM_TIMER_MASK 0x0c | |
333 | #define LPM_TIMER_500MS 0x04 /* 500 ms */ | |
334 | #define LPM_TIMER_500US 0x0c /* 500 us */ | |
335 | ||
336 | /* USB_AFE_CTRL2 */ | |
337 | #define SEN_VAL_MASK 0xf800 | |
338 | #define SEN_VAL_NORMAL 0xa000 | |
339 | #define SEL_RXIDLE 0x0100 | |
340 | ||
ac718b69 | 341 | /* OCP_ALDPS_CONFIG */ |
342 | #define ENPWRSAVE 0x8000 | |
343 | #define ENPDNPS 0x0200 | |
344 | #define LINKENA 0x0100 | |
345 | #define DIS_SDSAVE 0x0010 | |
346 | ||
43779f8d | 347 | /* OCP_PHY_STATUS */ |
348 | #define PHY_STAT_MASK 0x0007 | |
349 | #define PHY_STAT_LAN_ON 3 | |
350 | #define PHY_STAT_PWRDN 5 | |
351 | ||
352 | /* OCP_POWER_CFG */ | |
353 | #define EEE_CLKDIV_EN 0x8000 | |
354 | #define EN_ALDPS 0x0004 | |
355 | #define EN_10M_PLLOFF 0x0001 | |
356 | ||
ac718b69 | 357 | /* OCP_EEE_CONFIG1 */ |
358 | #define RG_TXLPI_MSK_HFDUP 0x8000 | |
359 | #define RG_MATCLR_EN 0x4000 | |
360 | #define EEE_10_CAP 0x2000 | |
361 | #define EEE_NWAY_EN 0x1000 | |
362 | #define TX_QUIET_EN 0x0200 | |
363 | #define RX_QUIET_EN 0x0100 | |
364 | #define SDRISETIME 0x0010 /* bit 4 ~ 6 */ | |
365 | #define RG_RXLPI_MSK_HFDUP 0x0008 | |
366 | #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */ | |
367 | ||
368 | /* OCP_EEE_CONFIG2 */ | |
369 | #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */ | |
370 | #define RG_DACQUIET_EN 0x0400 | |
371 | #define RG_LDVQUIET_EN 0x0200 | |
372 | #define RG_CKRSEL 0x0020 | |
373 | #define RG_EEEPRG_EN 0x0010 | |
374 | ||
375 | /* OCP_EEE_CONFIG3 */ | |
376 | #define FST_SNR_EYE_R 0x1500 /* bit 7 ~ 15 */ | |
377 | #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */ | |
378 | #define MSK_PH 0x0006 /* bit 0 ~ 3 */ | |
379 | ||
380 | /* OCP_EEE_AR */ | |
381 | /* bit[15:14] function */ | |
382 | #define FUN_ADDR 0x0000 | |
383 | #define FUN_DATA 0x4000 | |
384 | /* bit[4:0] device addr */ | |
385 | #define DEVICE_ADDR 0x0007 | |
386 | ||
387 | /* OCP_EEE_DATA */ | |
388 | #define EEE_ADDR 0x003C | |
389 | #define EEE_DATA 0x0002 | |
390 | ||
43779f8d | 391 | /* OCP_EEE_CFG */ |
392 | #define CTAP_SHORT_EN 0x0040 | |
393 | #define EEE10_EN 0x0010 | |
394 | ||
395 | /* OCP_DOWN_SPEED */ | |
396 | #define EN_10M_BGOFF 0x0080 | |
397 | ||
398 | /* OCP_EEE_CFG2 */ | |
399 | #define MY1000_EEE 0x0004 | |
400 | #define MY100_EEE 0x0002 | |
401 | ||
402 | /* OCP_ADC_CFG */ | |
403 | #define CKADSEL_L 0x0100 | |
404 | #define ADC_EN 0x0080 | |
405 | #define EN_EMI_L 0x0040 | |
406 | ||
407 | /* SRAM_LPF_CFG */ | |
408 | #define LPF_AUTO_TUNE 0x8000 | |
409 | ||
410 | /* SRAM_10M_AMP1 */ | |
411 | #define GDAC_IB_UPALL 0x0008 | |
412 | ||
413 | /* SRAM_10M_AMP2 */ | |
414 | #define AMP_DN 0x0200 | |
415 | ||
416 | /* SRAM_IMPEDANCE */ | |
417 | #define RX_DRIVING_MASK 0x6000 | |
418 | ||
ac718b69 | 419 | enum rtl_register_content { |
43779f8d | 420 | _1000bps = 0x10, |
ac718b69 | 421 | _100bps = 0x08, |
422 | _10bps = 0x04, | |
423 | LINK_STATUS = 0x02, | |
424 | FULL_DUP = 0x01, | |
425 | }; | |
426 | ||
ebc2ec48 | 427 | #define RTL8152_MAX_TX 10 |
428 | #define RTL8152_MAX_RX 10 | |
40a82917 | 429 | #define INTBUFSIZE 2 |
8e1f51bd | 430 | #define CRC_SIZE 4 |
431 | #define TX_ALIGN 4 | |
432 | #define RX_ALIGN 8 | |
40a82917 | 433 | |
434 | #define INTR_LINK 0x0004 | |
ebc2ec48 | 435 | |
ac718b69 | 436 | #define RTL8152_REQT_READ 0xc0 |
437 | #define RTL8152_REQT_WRITE 0x40 | |
438 | #define RTL8152_REQ_GET_REGS 0x05 | |
439 | #define RTL8152_REQ_SET_REGS 0x05 | |
440 | ||
441 | #define BYTE_EN_DWORD 0xff | |
442 | #define BYTE_EN_WORD 0x33 | |
443 | #define BYTE_EN_BYTE 0x11 | |
444 | #define BYTE_EN_SIX_BYTES 0x3f | |
445 | #define BYTE_EN_START_MASK 0x0f | |
446 | #define BYTE_EN_END_MASK 0xf0 | |
447 | ||
69b4b7a4 | 448 | #define RTL8153_MAX_PACKET 9216 /* 9K */ |
449 | #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN) | |
ac718b69 | 450 | #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN) |
69b4b7a4 | 451 | #define RTL8153_RMS RTL8153_MAX_PACKET |
b8125404 | 452 | #define RTL8152_TX_TIMEOUT (5 * HZ) |
ac718b69 | 453 | |
454 | /* rtl8152 flags */ | |
455 | enum rtl8152_flags { | |
456 | RTL8152_UNPLUG = 0, | |
ac718b69 | 457 | RTL8152_SET_RX_MODE, |
40a82917 | 458 | WORK_ENABLE, |
459 | RTL8152_LINK_CHG, | |
9a4be1bd | 460 | SELECTIVE_SUSPEND, |
aa66a5f1 | 461 | PHY_RESET, |
0c3121fc | 462 | SCHEDULE_TASKLET, |
ac718b69 | 463 | }; |
464 | ||
465 | /* Define these values to match your device */ | |
466 | #define VENDOR_ID_REALTEK 0x0bda | |
467 | #define PRODUCT_ID_RTL8152 0x8152 | |
43779f8d | 468 | #define PRODUCT_ID_RTL8153 0x8153 |
469 | ||
470 | #define VENDOR_ID_SAMSUNG 0x04e8 | |
471 | #define PRODUCT_ID_SAMSUNG 0xa101 | |
ac718b69 | 472 | |
473 | #define MCU_TYPE_PLA 0x0100 | |
474 | #define MCU_TYPE_USB 0x0000 | |
475 | ||
c7de7dec | 476 | #define REALTEK_USB_DEVICE(vend, prod) \ |
477 | USB_DEVICE_INTERFACE_CLASS(vend, prod, USB_CLASS_VENDOR_SPEC) | |
478 | ||
4f1d4d54 | 479 | struct tally_counter { |
480 | __le64 tx_packets; | |
481 | __le64 rx_packets; | |
482 | __le64 tx_errors; | |
483 | __le32 rx_errors; | |
484 | __le16 rx_missed; | |
485 | __le16 align_errors; | |
486 | __le32 tx_one_collision; | |
487 | __le32 tx_multi_collision; | |
488 | __le64 rx_unicast; | |
489 | __le64 rx_broadcast; | |
490 | __le32 rx_multicast; | |
491 | __le16 tx_aborted; | |
492 | __le16 tx_underun; | |
493 | }; | |
494 | ||
ac718b69 | 495 | struct rx_desc { |
500b6d7e | 496 | __le32 opts1; |
ac718b69 | 497 | #define RX_LEN_MASK 0x7fff |
565cab0a | 498 | |
500b6d7e | 499 | __le32 opts2; |
565cab0a | 500 | #define RD_UDP_CS (1 << 23) |
501 | #define RD_TCP_CS (1 << 22) | |
6128d1bb | 502 | #define RD_IPV6_CS (1 << 20) |
565cab0a | 503 | #define RD_IPV4_CS (1 << 19) |
504 | ||
500b6d7e | 505 | __le32 opts3; |
565cab0a | 506 | #define IPF (1 << 23) /* IP checksum fail */ |
507 | #define UDPF (1 << 22) /* UDP checksum fail */ | |
508 | #define TCPF (1 << 21) /* TCP checksum fail */ | |
509 | ||
500b6d7e | 510 | __le32 opts4; |
511 | __le32 opts5; | |
512 | __le32 opts6; | |
ac718b69 | 513 | }; |
514 | ||
515 | struct tx_desc { | |
500b6d7e | 516 | __le32 opts1; |
ac718b69 | 517 | #define TX_FS (1 << 31) /* First segment of a packet */ |
518 | #define TX_LS (1 << 30) /* Final segment of a packet */ | |
60c89071 | 519 | #define GTSENDV4 (1 << 28) |
6128d1bb | 520 | #define GTSENDV6 (1 << 27) |
60c89071 | 521 | #define GTTCPHO_SHIFT 18 |
6128d1bb | 522 | #define GTTCPHO_MAX 0x7fU |
60c89071 | 523 | #define TX_LEN_MAX 0x3ffffU |
5bd23881 | 524 | |
500b6d7e | 525 | __le32 opts2; |
5bd23881 | 526 | #define UDP_CS (1 << 31) /* Calculate UDP/IP checksum */ |
527 | #define TCP_CS (1 << 30) /* Calculate TCP/IP checksum */ | |
528 | #define IPV4_CS (1 << 29) /* Calculate IPv4 checksum */ | |
529 | #define IPV6_CS (1 << 28) /* Calculate IPv6 checksum */ | |
60c89071 | 530 | #define MSS_SHIFT 17 |
531 | #define MSS_MAX 0x7ffU | |
532 | #define TCPHO_SHIFT 17 | |
6128d1bb | 533 | #define TCPHO_MAX 0x7ffU |
ac718b69 | 534 | }; |
535 | ||
dff4e8ad | 536 | struct r8152; |
537 | ||
ebc2ec48 | 538 | struct rx_agg { |
539 | struct list_head list; | |
540 | struct urb *urb; | |
dff4e8ad | 541 | struct r8152 *context; |
ebc2ec48 | 542 | void *buffer; |
543 | void *head; | |
544 | }; | |
545 | ||
546 | struct tx_agg { | |
547 | struct list_head list; | |
548 | struct urb *urb; | |
dff4e8ad | 549 | struct r8152 *context; |
ebc2ec48 | 550 | void *buffer; |
551 | void *head; | |
552 | u32 skb_num; | |
553 | u32 skb_len; | |
554 | }; | |
555 | ||
ac718b69 | 556 | struct r8152 { |
557 | unsigned long flags; | |
558 | struct usb_device *udev; | |
559 | struct tasklet_struct tl; | |
40a82917 | 560 | struct usb_interface *intf; |
ac718b69 | 561 | struct net_device *netdev; |
40a82917 | 562 | struct urb *intr_urb; |
ebc2ec48 | 563 | struct tx_agg tx_info[RTL8152_MAX_TX]; |
564 | struct rx_agg rx_info[RTL8152_MAX_RX]; | |
565 | struct list_head rx_done, tx_free; | |
566 | struct sk_buff_head tx_queue; | |
567 | spinlock_t rx_lock, tx_lock; | |
ac718b69 | 568 | struct delayed_work schedule; |
569 | struct mii_if_info mii; | |
c81229c9 | 570 | |
571 | struct rtl_ops { | |
572 | void (*init)(struct r8152 *); | |
573 | int (*enable)(struct r8152 *); | |
574 | void (*disable)(struct r8152 *); | |
7e9da481 | 575 | void (*up)(struct r8152 *); |
c81229c9 | 576 | void (*down)(struct r8152 *); |
577 | void (*unload)(struct r8152 *); | |
578 | } rtl_ops; | |
579 | ||
40a82917 | 580 | int intr_interval; |
21ff2e89 | 581 | u32 saved_wolopts; |
ac718b69 | 582 | u32 msg_enable; |
dd1b119c | 583 | u32 tx_qlen; |
ac718b69 | 584 | u16 ocp_base; |
40a82917 | 585 | u8 *intr_buff; |
ac718b69 | 586 | u8 version; |
587 | u8 speed; | |
588 | }; | |
589 | ||
590 | enum rtl_version { | |
591 | RTL_VER_UNKNOWN = 0, | |
592 | RTL_VER_01, | |
43779f8d | 593 | RTL_VER_02, |
594 | RTL_VER_03, | |
595 | RTL_VER_04, | |
596 | RTL_VER_05, | |
597 | RTL_VER_MAX | |
ac718b69 | 598 | }; |
599 | ||
60c89071 | 600 | enum tx_csum_stat { |
601 | TX_CSUM_SUCCESS = 0, | |
602 | TX_CSUM_TSO, | |
603 | TX_CSUM_NONE | |
604 | }; | |
605 | ||
ac718b69 | 606 | /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). |
607 | * The RTL chips use a 64 element hash table based on the Ethernet CRC. | |
608 | */ | |
609 | static const int multicast_filter_limit = 32; | |
ebc2ec48 | 610 | static unsigned int rx_buf_sz = 16384; |
ac718b69 | 611 | |
60c89071 | 612 | #define RTL_LIMITED_TSO_SIZE (rx_buf_sz - sizeof(struct tx_desc) - \ |
613 | VLAN_ETH_HLEN - VLAN_HLEN) | |
614 | ||
ac718b69 | 615 | static |
616 | int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) | |
617 | { | |
31787f53 | 618 | int ret; |
619 | void *tmp; | |
620 | ||
621 | tmp = kmalloc(size, GFP_KERNEL); | |
622 | if (!tmp) | |
623 | return -ENOMEM; | |
624 | ||
625 | ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0), | |
ac718b69 | 626 | RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, |
31787f53 | 627 | value, index, tmp, size, 500); |
628 | ||
629 | memcpy(data, tmp, size); | |
630 | kfree(tmp); | |
631 | ||
632 | return ret; | |
ac718b69 | 633 | } |
634 | ||
635 | static | |
636 | int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) | |
637 | { | |
31787f53 | 638 | int ret; |
639 | void *tmp; | |
640 | ||
c4438f03 | 641 | tmp = kmemdup(data, size, GFP_KERNEL); |
31787f53 | 642 | if (!tmp) |
643 | return -ENOMEM; | |
644 | ||
31787f53 | 645 | ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0), |
ac718b69 | 646 | RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE, |
31787f53 | 647 | value, index, tmp, size, 500); |
648 | ||
649 | kfree(tmp); | |
db8515ef | 650 | |
31787f53 | 651 | return ret; |
ac718b69 | 652 | } |
653 | ||
654 | static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size, | |
655 | void *data, u16 type) | |
656 | { | |
45f4a19f | 657 | u16 limit = 64; |
658 | int ret = 0; | |
ac718b69 | 659 | |
660 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
661 | return -ENODEV; | |
662 | ||
663 | /* both size and indix must be 4 bytes align */ | |
664 | if ((size & 3) || !size || (index & 3) || !data) | |
665 | return -EPERM; | |
666 | ||
667 | if ((u32)index + (u32)size > 0xffff) | |
668 | return -EPERM; | |
669 | ||
670 | while (size) { | |
671 | if (size > limit) { | |
672 | ret = get_registers(tp, index, type, limit, data); | |
673 | if (ret < 0) | |
674 | break; | |
675 | ||
676 | index += limit; | |
677 | data += limit; | |
678 | size -= limit; | |
679 | } else { | |
680 | ret = get_registers(tp, index, type, size, data); | |
681 | if (ret < 0) | |
682 | break; | |
683 | ||
684 | index += size; | |
685 | data += size; | |
686 | size = 0; | |
687 | break; | |
688 | } | |
689 | } | |
690 | ||
691 | return ret; | |
692 | } | |
693 | ||
694 | static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, | |
695 | u16 size, void *data, u16 type) | |
696 | { | |
45f4a19f | 697 | int ret; |
698 | u16 byteen_start, byteen_end, byen; | |
699 | u16 limit = 512; | |
ac718b69 | 700 | |
701 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
702 | return -ENODEV; | |
703 | ||
704 | /* both size and indix must be 4 bytes align */ | |
705 | if ((size & 3) || !size || (index & 3) || !data) | |
706 | return -EPERM; | |
707 | ||
708 | if ((u32)index + (u32)size > 0xffff) | |
709 | return -EPERM; | |
710 | ||
711 | byteen_start = byteen & BYTE_EN_START_MASK; | |
712 | byteen_end = byteen & BYTE_EN_END_MASK; | |
713 | ||
714 | byen = byteen_start | (byteen_start << 4); | |
715 | ret = set_registers(tp, index, type | byen, 4, data); | |
716 | if (ret < 0) | |
717 | goto error1; | |
718 | ||
719 | index += 4; | |
720 | data += 4; | |
721 | size -= 4; | |
722 | ||
723 | if (size) { | |
724 | size -= 4; | |
725 | ||
726 | while (size) { | |
727 | if (size > limit) { | |
728 | ret = set_registers(tp, index, | |
729 | type | BYTE_EN_DWORD, | |
730 | limit, data); | |
731 | if (ret < 0) | |
732 | goto error1; | |
733 | ||
734 | index += limit; | |
735 | data += limit; | |
736 | size -= limit; | |
737 | } else { | |
738 | ret = set_registers(tp, index, | |
739 | type | BYTE_EN_DWORD, | |
740 | size, data); | |
741 | if (ret < 0) | |
742 | goto error1; | |
743 | ||
744 | index += size; | |
745 | data += size; | |
746 | size = 0; | |
747 | break; | |
748 | } | |
749 | } | |
750 | ||
751 | byen = byteen_end | (byteen_end >> 4); | |
752 | ret = set_registers(tp, index, type | byen, 4, data); | |
753 | if (ret < 0) | |
754 | goto error1; | |
755 | } | |
756 | ||
757 | error1: | |
758 | return ret; | |
759 | } | |
760 | ||
761 | static inline | |
762 | int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) | |
763 | { | |
764 | return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA); | |
765 | } | |
766 | ||
767 | static inline | |
768 | int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) | |
769 | { | |
770 | return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA); | |
771 | } | |
772 | ||
773 | static inline | |
774 | int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) | |
775 | { | |
776 | return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB); | |
777 | } | |
778 | ||
779 | static inline | |
780 | int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) | |
781 | { | |
782 | return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB); | |
783 | } | |
784 | ||
785 | static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index) | |
786 | { | |
c8826de8 | 787 | __le32 data; |
ac718b69 | 788 | |
c8826de8 | 789 | generic_ocp_read(tp, index, sizeof(data), &data, type); |
ac718b69 | 790 | |
791 | return __le32_to_cpu(data); | |
792 | } | |
793 | ||
794 | static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data) | |
795 | { | |
c8826de8 | 796 | __le32 tmp = __cpu_to_le32(data); |
797 | ||
798 | generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type); | |
ac718b69 | 799 | } |
800 | ||
801 | static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index) | |
802 | { | |
803 | u32 data; | |
c8826de8 | 804 | __le32 tmp; |
ac718b69 | 805 | u8 shift = index & 2; |
806 | ||
807 | index &= ~3; | |
808 | ||
c8826de8 | 809 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 810 | |
c8826de8 | 811 | data = __le32_to_cpu(tmp); |
ac718b69 | 812 | data >>= (shift * 8); |
813 | data &= 0xffff; | |
814 | ||
815 | return (u16)data; | |
816 | } | |
817 | ||
818 | static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data) | |
819 | { | |
c8826de8 | 820 | u32 mask = 0xffff; |
821 | __le32 tmp; | |
ac718b69 | 822 | u16 byen = BYTE_EN_WORD; |
823 | u8 shift = index & 2; | |
824 | ||
825 | data &= mask; | |
826 | ||
827 | if (index & 2) { | |
828 | byen <<= shift; | |
829 | mask <<= (shift * 8); | |
830 | data <<= (shift * 8); | |
831 | index &= ~3; | |
832 | } | |
833 | ||
c8826de8 | 834 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 835 | |
c8826de8 | 836 | data |= __le32_to_cpu(tmp) & ~mask; |
837 | tmp = __cpu_to_le32(data); | |
ac718b69 | 838 | |
c8826de8 | 839 | generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); |
ac718b69 | 840 | } |
841 | ||
842 | static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index) | |
843 | { | |
844 | u32 data; | |
c8826de8 | 845 | __le32 tmp; |
ac718b69 | 846 | u8 shift = index & 3; |
847 | ||
848 | index &= ~3; | |
849 | ||
c8826de8 | 850 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 851 | |
c8826de8 | 852 | data = __le32_to_cpu(tmp); |
ac718b69 | 853 | data >>= (shift * 8); |
854 | data &= 0xff; | |
855 | ||
856 | return (u8)data; | |
857 | } | |
858 | ||
859 | static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data) | |
860 | { | |
c8826de8 | 861 | u32 mask = 0xff; |
862 | __le32 tmp; | |
ac718b69 | 863 | u16 byen = BYTE_EN_BYTE; |
864 | u8 shift = index & 3; | |
865 | ||
866 | data &= mask; | |
867 | ||
868 | if (index & 3) { | |
869 | byen <<= shift; | |
870 | mask <<= (shift * 8); | |
871 | data <<= (shift * 8); | |
872 | index &= ~3; | |
873 | } | |
874 | ||
c8826de8 | 875 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 876 | |
c8826de8 | 877 | data |= __le32_to_cpu(tmp) & ~mask; |
878 | tmp = __cpu_to_le32(data); | |
ac718b69 | 879 | |
c8826de8 | 880 | generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); |
ac718b69 | 881 | } |
882 | ||
ac244d3e | 883 | static u16 ocp_reg_read(struct r8152 *tp, u16 addr) |
e3fe0b1a | 884 | { |
885 | u16 ocp_base, ocp_index; | |
886 | ||
887 | ocp_base = addr & 0xf000; | |
888 | if (ocp_base != tp->ocp_base) { | |
889 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); | |
890 | tp->ocp_base = ocp_base; | |
891 | } | |
892 | ||
893 | ocp_index = (addr & 0x0fff) | 0xb000; | |
ac244d3e | 894 | return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index); |
e3fe0b1a | 895 | } |
896 | ||
ac244d3e | 897 | static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) |
ac718b69 | 898 | { |
ac244d3e | 899 | u16 ocp_base, ocp_index; |
ac718b69 | 900 | |
ac244d3e | 901 | ocp_base = addr & 0xf000; |
902 | if (ocp_base != tp->ocp_base) { | |
903 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); | |
904 | tp->ocp_base = ocp_base; | |
ac718b69 | 905 | } |
ac244d3e | 906 | |
907 | ocp_index = (addr & 0x0fff) | 0xb000; | |
908 | ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data); | |
ac718b69 | 909 | } |
910 | ||
ac244d3e | 911 | static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value) |
ac718b69 | 912 | { |
ac244d3e | 913 | ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value); |
914 | } | |
ac718b69 | 915 | |
ac244d3e | 916 | static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr) |
917 | { | |
918 | return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2); | |
ac718b69 | 919 | } |
920 | ||
43779f8d | 921 | static void sram_write(struct r8152 *tp, u16 addr, u16 data) |
922 | { | |
923 | ocp_reg_write(tp, OCP_SRAM_ADDR, addr); | |
924 | ocp_reg_write(tp, OCP_SRAM_DATA, data); | |
925 | } | |
926 | ||
927 | static u16 sram_read(struct r8152 *tp, u16 addr) | |
928 | { | |
929 | ocp_reg_write(tp, OCP_SRAM_ADDR, addr); | |
930 | return ocp_reg_read(tp, OCP_SRAM_DATA); | |
931 | } | |
932 | ||
ac718b69 | 933 | static int read_mii_word(struct net_device *netdev, int phy_id, int reg) |
934 | { | |
935 | struct r8152 *tp = netdev_priv(netdev); | |
9a4be1bd | 936 | int ret; |
ac718b69 | 937 | |
6871438c | 938 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
939 | return -ENODEV; | |
940 | ||
ac718b69 | 941 | if (phy_id != R8152_PHY_ID) |
942 | return -EINVAL; | |
943 | ||
9a4be1bd | 944 | ret = usb_autopm_get_interface(tp->intf); |
945 | if (ret < 0) | |
946 | goto out; | |
947 | ||
948 | ret = r8152_mdio_read(tp, reg); | |
949 | ||
950 | usb_autopm_put_interface(tp->intf); | |
951 | ||
952 | out: | |
953 | return ret; | |
ac718b69 | 954 | } |
955 | ||
956 | static | |
957 | void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val) | |
958 | { | |
959 | struct r8152 *tp = netdev_priv(netdev); | |
960 | ||
6871438c | 961 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
962 | return; | |
963 | ||
ac718b69 | 964 | if (phy_id != R8152_PHY_ID) |
965 | return; | |
966 | ||
9a4be1bd | 967 | if (usb_autopm_get_interface(tp->intf) < 0) |
968 | return; | |
969 | ||
ac718b69 | 970 | r8152_mdio_write(tp, reg, val); |
9a4be1bd | 971 | |
972 | usb_autopm_put_interface(tp->intf); | |
ac718b69 | 973 | } |
974 | ||
ebc2ec48 | 975 | static |
976 | int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags); | |
977 | ||
ac718b69 | 978 | static inline void set_ethernet_addr(struct r8152 *tp) |
979 | { | |
980 | struct net_device *dev = tp->netdev; | |
8a91c824 | 981 | int ret; |
31787f53 | 982 | u8 node_id[8] = {0}; |
ac718b69 | 983 | |
8a91c824 | 984 | if (tp->version == RTL_VER_01) |
985 | ret = pla_ocp_read(tp, PLA_IDR, sizeof(node_id), node_id); | |
986 | else | |
987 | ret = pla_ocp_read(tp, PLA_BACKUP, sizeof(node_id), node_id); | |
988 | ||
989 | if (ret < 0) { | |
ac718b69 | 990 | netif_notice(tp, probe, dev, "inet addr fail\n"); |
8a91c824 | 991 | } else { |
992 | if (tp->version != RTL_VER_01) { | |
993 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, | |
994 | CRWECR_CONFIG); | |
995 | pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, | |
996 | sizeof(node_id), node_id); | |
997 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, | |
998 | CRWECR_NORAML); | |
999 | } | |
1000 | ||
ac718b69 | 1001 | memcpy(dev->dev_addr, node_id, dev->addr_len); |
1002 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); | |
1003 | } | |
ac718b69 | 1004 | } |
1005 | ||
1006 | static int rtl8152_set_mac_address(struct net_device *netdev, void *p) | |
1007 | { | |
1008 | struct r8152 *tp = netdev_priv(netdev); | |
1009 | struct sockaddr *addr = p; | |
1010 | ||
1011 | if (!is_valid_ether_addr(addr->sa_data)) | |
1012 | return -EADDRNOTAVAIL; | |
1013 | ||
1014 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
1015 | ||
1016 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
1017 | pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data); | |
1018 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
1019 | ||
1020 | return 0; | |
1021 | } | |
1022 | ||
ac718b69 | 1023 | static void read_bulk_callback(struct urb *urb) |
1024 | { | |
ac718b69 | 1025 | struct net_device *netdev; |
ac718b69 | 1026 | int status = urb->status; |
ebc2ec48 | 1027 | struct rx_agg *agg; |
1028 | struct r8152 *tp; | |
ac718b69 | 1029 | int result; |
ac718b69 | 1030 | |
ebc2ec48 | 1031 | agg = urb->context; |
1032 | if (!agg) | |
1033 | return; | |
1034 | ||
1035 | tp = agg->context; | |
ac718b69 | 1036 | if (!tp) |
1037 | return; | |
ebc2ec48 | 1038 | |
ac718b69 | 1039 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
1040 | return; | |
ebc2ec48 | 1041 | |
1042 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
1043 | return; | |
1044 | ||
ac718b69 | 1045 | netdev = tp->netdev; |
7559fb2f | 1046 | |
1047 | /* When link down, the driver would cancel all bulks. */ | |
1048 | /* This avoid the re-submitting bulk */ | |
ebc2ec48 | 1049 | if (!netif_carrier_ok(netdev)) |
ac718b69 | 1050 | return; |
1051 | ||
9a4be1bd | 1052 | usb_mark_last_busy(tp->udev); |
1053 | ||
ac718b69 | 1054 | switch (status) { |
1055 | case 0: | |
ebc2ec48 | 1056 | if (urb->actual_length < ETH_ZLEN) |
1057 | break; | |
1058 | ||
2685d410 | 1059 | spin_lock(&tp->rx_lock); |
ebc2ec48 | 1060 | list_add_tail(&agg->list, &tp->rx_done); |
2685d410 | 1061 | spin_unlock(&tp->rx_lock); |
ebc2ec48 | 1062 | tasklet_schedule(&tp->tl); |
1063 | return; | |
ac718b69 | 1064 | case -ESHUTDOWN: |
1065 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
1066 | netif_device_detach(tp->netdev); | |
ebc2ec48 | 1067 | return; |
ac718b69 | 1068 | case -ENOENT: |
1069 | return; /* the urb is in unlink state */ | |
1070 | case -ETIME: | |
4a8deae2 HW |
1071 | if (net_ratelimit()) |
1072 | netdev_warn(netdev, "maybe reset is needed?\n"); | |
ebc2ec48 | 1073 | break; |
ac718b69 | 1074 | default: |
4a8deae2 HW |
1075 | if (net_ratelimit()) |
1076 | netdev_warn(netdev, "Rx status %d\n", status); | |
ebc2ec48 | 1077 | break; |
ac718b69 | 1078 | } |
1079 | ||
ebc2ec48 | 1080 | result = r8152_submit_rx(tp, agg, GFP_ATOMIC); |
ac718b69 | 1081 | if (result == -ENODEV) { |
1082 | netif_device_detach(tp->netdev); | |
1083 | } else if (result) { | |
2685d410 | 1084 | spin_lock(&tp->rx_lock); |
ebc2ec48 | 1085 | list_add_tail(&agg->list, &tp->rx_done); |
2685d410 | 1086 | spin_unlock(&tp->rx_lock); |
ebc2ec48 | 1087 | tasklet_schedule(&tp->tl); |
ac718b69 | 1088 | } |
ac718b69 | 1089 | } |
1090 | ||
ebc2ec48 | 1091 | static void write_bulk_callback(struct urb *urb) |
ac718b69 | 1092 | { |
ebc2ec48 | 1093 | struct net_device_stats *stats; |
d104eafa | 1094 | struct net_device *netdev; |
ebc2ec48 | 1095 | struct tx_agg *agg; |
ac718b69 | 1096 | struct r8152 *tp; |
ebc2ec48 | 1097 | int status = urb->status; |
ac718b69 | 1098 | |
ebc2ec48 | 1099 | agg = urb->context; |
1100 | if (!agg) | |
ac718b69 | 1101 | return; |
1102 | ||
ebc2ec48 | 1103 | tp = agg->context; |
1104 | if (!tp) | |
1105 | return; | |
1106 | ||
d104eafa | 1107 | netdev = tp->netdev; |
05e0f1aa | 1108 | stats = &netdev->stats; |
ebc2ec48 | 1109 | if (status) { |
4a8deae2 | 1110 | if (net_ratelimit()) |
d104eafa | 1111 | netdev_warn(netdev, "Tx status %d\n", status); |
ebc2ec48 | 1112 | stats->tx_errors += agg->skb_num; |
ac718b69 | 1113 | } else { |
ebc2ec48 | 1114 | stats->tx_packets += agg->skb_num; |
1115 | stats->tx_bytes += agg->skb_len; | |
ac718b69 | 1116 | } |
1117 | ||
2685d410 | 1118 | spin_lock(&tp->tx_lock); |
ebc2ec48 | 1119 | list_add_tail(&agg->list, &tp->tx_free); |
2685d410 | 1120 | spin_unlock(&tp->tx_lock); |
ebc2ec48 | 1121 | |
9a4be1bd | 1122 | usb_autopm_put_interface_async(tp->intf); |
1123 | ||
d104eafa | 1124 | if (!netif_carrier_ok(netdev)) |
ebc2ec48 | 1125 | return; |
1126 | ||
1127 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
1128 | return; | |
1129 | ||
1130 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
1131 | return; | |
1132 | ||
1133 | if (!skb_queue_empty(&tp->tx_queue)) | |
0c3121fc | 1134 | tasklet_schedule(&tp->tl); |
ac718b69 | 1135 | } |
1136 | ||
40a82917 | 1137 | static void intr_callback(struct urb *urb) |
1138 | { | |
1139 | struct r8152 *tp; | |
500b6d7e | 1140 | __le16 *d; |
40a82917 | 1141 | int status = urb->status; |
1142 | int res; | |
1143 | ||
1144 | tp = urb->context; | |
1145 | if (!tp) | |
1146 | return; | |
1147 | ||
1148 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
1149 | return; | |
1150 | ||
1151 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
1152 | return; | |
1153 | ||
1154 | switch (status) { | |
1155 | case 0: /* success */ | |
1156 | break; | |
1157 | case -ECONNRESET: /* unlink */ | |
1158 | case -ESHUTDOWN: | |
1159 | netif_device_detach(tp->netdev); | |
1160 | case -ENOENT: | |
1161 | return; | |
1162 | case -EOVERFLOW: | |
1163 | netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n"); | |
1164 | goto resubmit; | |
1165 | /* -EPIPE: should clear the halt */ | |
1166 | default: | |
1167 | netif_info(tp, intr, tp->netdev, "intr status %d\n", status); | |
1168 | goto resubmit; | |
1169 | } | |
1170 | ||
1171 | d = urb->transfer_buffer; | |
1172 | if (INTR_LINK & __le16_to_cpu(d[0])) { | |
1173 | if (!(tp->speed & LINK_STATUS)) { | |
1174 | set_bit(RTL8152_LINK_CHG, &tp->flags); | |
1175 | schedule_delayed_work(&tp->schedule, 0); | |
1176 | } | |
1177 | } else { | |
1178 | if (tp->speed & LINK_STATUS) { | |
1179 | set_bit(RTL8152_LINK_CHG, &tp->flags); | |
1180 | schedule_delayed_work(&tp->schedule, 0); | |
1181 | } | |
1182 | } | |
1183 | ||
1184 | resubmit: | |
1185 | res = usb_submit_urb(urb, GFP_ATOMIC); | |
1186 | if (res == -ENODEV) | |
1187 | netif_device_detach(tp->netdev); | |
1188 | else if (res) | |
1189 | netif_err(tp, intr, tp->netdev, | |
4a8deae2 | 1190 | "can't resubmit intr, status %d\n", res); |
40a82917 | 1191 | } |
1192 | ||
ebc2ec48 | 1193 | static inline void *rx_agg_align(void *data) |
1194 | { | |
8e1f51bd | 1195 | return (void *)ALIGN((uintptr_t)data, RX_ALIGN); |
ebc2ec48 | 1196 | } |
1197 | ||
1198 | static inline void *tx_agg_align(void *data) | |
1199 | { | |
8e1f51bd | 1200 | return (void *)ALIGN((uintptr_t)data, TX_ALIGN); |
ebc2ec48 | 1201 | } |
1202 | ||
1203 | static void free_all_mem(struct r8152 *tp) | |
1204 | { | |
1205 | int i; | |
1206 | ||
1207 | for (i = 0; i < RTL8152_MAX_RX; i++) { | |
9629e3c0 | 1208 | usb_free_urb(tp->rx_info[i].urb); |
1209 | tp->rx_info[i].urb = NULL; | |
ebc2ec48 | 1210 | |
9629e3c0 | 1211 | kfree(tp->rx_info[i].buffer); |
1212 | tp->rx_info[i].buffer = NULL; | |
1213 | tp->rx_info[i].head = NULL; | |
ebc2ec48 | 1214 | } |
1215 | ||
1216 | for (i = 0; i < RTL8152_MAX_TX; i++) { | |
9629e3c0 | 1217 | usb_free_urb(tp->tx_info[i].urb); |
1218 | tp->tx_info[i].urb = NULL; | |
ebc2ec48 | 1219 | |
9629e3c0 | 1220 | kfree(tp->tx_info[i].buffer); |
1221 | tp->tx_info[i].buffer = NULL; | |
1222 | tp->tx_info[i].head = NULL; | |
ebc2ec48 | 1223 | } |
40a82917 | 1224 | |
9629e3c0 | 1225 | usb_free_urb(tp->intr_urb); |
1226 | tp->intr_urb = NULL; | |
40a82917 | 1227 | |
9629e3c0 | 1228 | kfree(tp->intr_buff); |
1229 | tp->intr_buff = NULL; | |
ebc2ec48 | 1230 | } |
1231 | ||
1232 | static int alloc_all_mem(struct r8152 *tp) | |
1233 | { | |
1234 | struct net_device *netdev = tp->netdev; | |
40a82917 | 1235 | struct usb_interface *intf = tp->intf; |
1236 | struct usb_host_interface *alt = intf->cur_altsetting; | |
1237 | struct usb_host_endpoint *ep_intr = alt->endpoint + 2; | |
ebc2ec48 | 1238 | struct urb *urb; |
1239 | int node, i; | |
1240 | u8 *buf; | |
1241 | ||
1242 | node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; | |
1243 | ||
1244 | spin_lock_init(&tp->rx_lock); | |
1245 | spin_lock_init(&tp->tx_lock); | |
1246 | INIT_LIST_HEAD(&tp->rx_done); | |
1247 | INIT_LIST_HEAD(&tp->tx_free); | |
1248 | skb_queue_head_init(&tp->tx_queue); | |
1249 | ||
1250 | for (i = 0; i < RTL8152_MAX_RX; i++) { | |
1251 | buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node); | |
1252 | if (!buf) | |
1253 | goto err1; | |
1254 | ||
1255 | if (buf != rx_agg_align(buf)) { | |
1256 | kfree(buf); | |
8e1f51bd | 1257 | buf = kmalloc_node(rx_buf_sz + RX_ALIGN, GFP_KERNEL, |
1258 | node); | |
ebc2ec48 | 1259 | if (!buf) |
1260 | goto err1; | |
1261 | } | |
1262 | ||
1263 | urb = usb_alloc_urb(0, GFP_KERNEL); | |
1264 | if (!urb) { | |
1265 | kfree(buf); | |
1266 | goto err1; | |
1267 | } | |
1268 | ||
1269 | INIT_LIST_HEAD(&tp->rx_info[i].list); | |
1270 | tp->rx_info[i].context = tp; | |
1271 | tp->rx_info[i].urb = urb; | |
1272 | tp->rx_info[i].buffer = buf; | |
1273 | tp->rx_info[i].head = rx_agg_align(buf); | |
1274 | } | |
1275 | ||
1276 | for (i = 0; i < RTL8152_MAX_TX; i++) { | |
1277 | buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node); | |
1278 | if (!buf) | |
1279 | goto err1; | |
1280 | ||
1281 | if (buf != tx_agg_align(buf)) { | |
1282 | kfree(buf); | |
8e1f51bd | 1283 | buf = kmalloc_node(rx_buf_sz + TX_ALIGN, GFP_KERNEL, |
1284 | node); | |
ebc2ec48 | 1285 | if (!buf) |
1286 | goto err1; | |
1287 | } | |
1288 | ||
1289 | urb = usb_alloc_urb(0, GFP_KERNEL); | |
1290 | if (!urb) { | |
1291 | kfree(buf); | |
1292 | goto err1; | |
1293 | } | |
1294 | ||
1295 | INIT_LIST_HEAD(&tp->tx_info[i].list); | |
1296 | tp->tx_info[i].context = tp; | |
1297 | tp->tx_info[i].urb = urb; | |
1298 | tp->tx_info[i].buffer = buf; | |
1299 | tp->tx_info[i].head = tx_agg_align(buf); | |
1300 | ||
1301 | list_add_tail(&tp->tx_info[i].list, &tp->tx_free); | |
1302 | } | |
1303 | ||
40a82917 | 1304 | tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL); |
1305 | if (!tp->intr_urb) | |
1306 | goto err1; | |
1307 | ||
1308 | tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL); | |
1309 | if (!tp->intr_buff) | |
1310 | goto err1; | |
1311 | ||
1312 | tp->intr_interval = (int)ep_intr->desc.bInterval; | |
1313 | usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3), | |
1314 | tp->intr_buff, INTBUFSIZE, intr_callback, | |
1315 | tp, tp->intr_interval); | |
1316 | ||
ebc2ec48 | 1317 | return 0; |
1318 | ||
1319 | err1: | |
1320 | free_all_mem(tp); | |
1321 | return -ENOMEM; | |
1322 | } | |
1323 | ||
0de98f6c | 1324 | static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp) |
1325 | { | |
1326 | struct tx_agg *agg = NULL; | |
1327 | unsigned long flags; | |
1328 | ||
21949ab7 | 1329 | if (list_empty(&tp->tx_free)) |
1330 | return NULL; | |
1331 | ||
0de98f6c | 1332 | spin_lock_irqsave(&tp->tx_lock, flags); |
1333 | if (!list_empty(&tp->tx_free)) { | |
1334 | struct list_head *cursor; | |
1335 | ||
1336 | cursor = tp->tx_free.next; | |
1337 | list_del_init(cursor); | |
1338 | agg = list_entry(cursor, struct tx_agg, list); | |
1339 | } | |
1340 | spin_unlock_irqrestore(&tp->tx_lock, flags); | |
1341 | ||
1342 | return agg; | |
1343 | } | |
1344 | ||
60c89071 | 1345 | static inline __be16 get_protocol(struct sk_buff *skb) |
5bd23881 | 1346 | { |
60c89071 | 1347 | __be16 protocol; |
5bd23881 | 1348 | |
60c89071 | 1349 | if (skb->protocol == htons(ETH_P_8021Q)) |
1350 | protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto; | |
1351 | else | |
1352 | protocol = skb->protocol; | |
5bd23881 | 1353 | |
60c89071 | 1354 | return protocol; |
1355 | } | |
5bd23881 | 1356 | |
6128d1bb | 1357 | /* |
1358 | * r8152_csum_workaround() | |
1359 | * The hw limites the value the transport offset. When the offset is out of the | |
1360 | * range, calculate the checksum by sw. | |
1361 | */ | |
1362 | static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb, | |
1363 | struct sk_buff_head *list) | |
1364 | { | |
1365 | if (skb_shinfo(skb)->gso_size) { | |
1366 | netdev_features_t features = tp->netdev->features; | |
1367 | struct sk_buff_head seg_list; | |
1368 | struct sk_buff *segs, *nskb; | |
1369 | ||
a91d45f1 | 1370 | features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6); |
6128d1bb | 1371 | segs = skb_gso_segment(skb, features); |
1372 | if (IS_ERR(segs) || !segs) | |
1373 | goto drop; | |
1374 | ||
1375 | __skb_queue_head_init(&seg_list); | |
1376 | ||
1377 | do { | |
1378 | nskb = segs; | |
1379 | segs = segs->next; | |
1380 | nskb->next = NULL; | |
1381 | __skb_queue_tail(&seg_list, nskb); | |
1382 | } while (segs); | |
1383 | ||
1384 | skb_queue_splice(&seg_list, list); | |
1385 | dev_kfree_skb(skb); | |
1386 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
1387 | if (skb_checksum_help(skb) < 0) | |
1388 | goto drop; | |
1389 | ||
1390 | __skb_queue_head(list, skb); | |
1391 | } else { | |
1392 | struct net_device_stats *stats; | |
1393 | ||
1394 | drop: | |
1395 | stats = &tp->netdev->stats; | |
1396 | stats->tx_dropped++; | |
1397 | dev_kfree_skb(skb); | |
1398 | } | |
1399 | } | |
1400 | ||
1401 | /* | |
1402 | * msdn_giant_send_check() | |
1403 | * According to the document of microsoft, the TCP Pseudo Header excludes the | |
1404 | * packet length for IPv6 TCP large packets. | |
1405 | */ | |
1406 | static int msdn_giant_send_check(struct sk_buff *skb) | |
1407 | { | |
1408 | const struct ipv6hdr *ipv6h; | |
1409 | struct tcphdr *th; | |
fcb308d5 | 1410 | int ret; |
1411 | ||
1412 | ret = skb_cow_head(skb, 0); | |
1413 | if (ret) | |
1414 | return ret; | |
6128d1bb | 1415 | |
1416 | ipv6h = ipv6_hdr(skb); | |
1417 | th = tcp_hdr(skb); | |
1418 | ||
1419 | th->check = 0; | |
1420 | th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0); | |
1421 | ||
fcb308d5 | 1422 | return ret; |
6128d1bb | 1423 | } |
1424 | ||
60c89071 | 1425 | static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, |
1426 | struct sk_buff *skb, u32 len, u32 transport_offset) | |
1427 | { | |
1428 | u32 mss = skb_shinfo(skb)->gso_size; | |
1429 | u32 opts1, opts2 = 0; | |
1430 | int ret = TX_CSUM_SUCCESS; | |
1431 | ||
1432 | WARN_ON_ONCE(len > TX_LEN_MAX); | |
1433 | ||
1434 | opts1 = len | TX_FS | TX_LS; | |
1435 | ||
1436 | if (mss) { | |
6128d1bb | 1437 | if (transport_offset > GTTCPHO_MAX) { |
1438 | netif_warn(tp, tx_err, tp->netdev, | |
1439 | "Invalid transport offset 0x%x for TSO\n", | |
1440 | transport_offset); | |
1441 | ret = TX_CSUM_TSO; | |
1442 | goto unavailable; | |
1443 | } | |
1444 | ||
60c89071 | 1445 | switch (get_protocol(skb)) { |
1446 | case htons(ETH_P_IP): | |
1447 | opts1 |= GTSENDV4; | |
1448 | break; | |
1449 | ||
6128d1bb | 1450 | case htons(ETH_P_IPV6): |
fcb308d5 | 1451 | if (msdn_giant_send_check(skb)) { |
1452 | ret = TX_CSUM_TSO; | |
1453 | goto unavailable; | |
1454 | } | |
6128d1bb | 1455 | opts1 |= GTSENDV6; |
6128d1bb | 1456 | break; |
1457 | ||
60c89071 | 1458 | default: |
1459 | WARN_ON_ONCE(1); | |
1460 | break; | |
1461 | } | |
1462 | ||
1463 | opts1 |= transport_offset << GTTCPHO_SHIFT; | |
1464 | opts2 |= min(mss, MSS_MAX) << MSS_SHIFT; | |
1465 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
1466 | u8 ip_protocol; | |
5bd23881 | 1467 | |
6128d1bb | 1468 | if (transport_offset > TCPHO_MAX) { |
1469 | netif_warn(tp, tx_err, tp->netdev, | |
1470 | "Invalid transport offset 0x%x\n", | |
1471 | transport_offset); | |
1472 | ret = TX_CSUM_NONE; | |
1473 | goto unavailable; | |
1474 | } | |
1475 | ||
60c89071 | 1476 | switch (get_protocol(skb)) { |
5bd23881 | 1477 | case htons(ETH_P_IP): |
1478 | opts2 |= IPV4_CS; | |
1479 | ip_protocol = ip_hdr(skb)->protocol; | |
1480 | break; | |
1481 | ||
1482 | case htons(ETH_P_IPV6): | |
1483 | opts2 |= IPV6_CS; | |
1484 | ip_protocol = ipv6_hdr(skb)->nexthdr; | |
1485 | break; | |
1486 | ||
1487 | default: | |
1488 | ip_protocol = IPPROTO_RAW; | |
1489 | break; | |
1490 | } | |
1491 | ||
60c89071 | 1492 | if (ip_protocol == IPPROTO_TCP) |
5bd23881 | 1493 | opts2 |= TCP_CS; |
60c89071 | 1494 | else if (ip_protocol == IPPROTO_UDP) |
5bd23881 | 1495 | opts2 |= UDP_CS; |
60c89071 | 1496 | else |
5bd23881 | 1497 | WARN_ON_ONCE(1); |
5bd23881 | 1498 | |
60c89071 | 1499 | opts2 |= transport_offset << TCPHO_SHIFT; |
5bd23881 | 1500 | } |
60c89071 | 1501 | |
1502 | desc->opts2 = cpu_to_le32(opts2); | |
1503 | desc->opts1 = cpu_to_le32(opts1); | |
1504 | ||
6128d1bb | 1505 | unavailable: |
60c89071 | 1506 | return ret; |
5bd23881 | 1507 | } |
1508 | ||
b1379d9a | 1509 | static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg) |
1510 | { | |
d84130a1 | 1511 | struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; |
9a4be1bd | 1512 | int remain, ret; |
b1379d9a | 1513 | u8 *tx_data; |
1514 | ||
d84130a1 | 1515 | __skb_queue_head_init(&skb_head); |
0c3121fc | 1516 | spin_lock(&tx_queue->lock); |
d84130a1 | 1517 | skb_queue_splice_init(tx_queue, &skb_head); |
0c3121fc | 1518 | spin_unlock(&tx_queue->lock); |
d84130a1 | 1519 | |
b1379d9a | 1520 | tx_data = agg->head; |
1521 | agg->skb_num = agg->skb_len = 0; | |
7937f9e5 | 1522 | remain = rx_buf_sz; |
b1379d9a | 1523 | |
7937f9e5 | 1524 | while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) { |
b1379d9a | 1525 | struct tx_desc *tx_desc; |
1526 | struct sk_buff *skb; | |
1527 | unsigned int len; | |
60c89071 | 1528 | u32 offset; |
b1379d9a | 1529 | |
d84130a1 | 1530 | skb = __skb_dequeue(&skb_head); |
b1379d9a | 1531 | if (!skb) |
1532 | break; | |
1533 | ||
60c89071 | 1534 | len = skb->len + sizeof(*tx_desc); |
1535 | ||
1536 | if (len > remain) { | |
d84130a1 | 1537 | __skb_queue_head(&skb_head, skb); |
b1379d9a | 1538 | break; |
1539 | } | |
1540 | ||
7937f9e5 | 1541 | tx_data = tx_agg_align(tx_data); |
b1379d9a | 1542 | tx_desc = (struct tx_desc *)tx_data; |
60c89071 | 1543 | |
1544 | offset = (u32)skb_transport_offset(skb); | |
1545 | ||
6128d1bb | 1546 | if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) { |
1547 | r8152_csum_workaround(tp, skb, &skb_head); | |
1548 | continue; | |
1549 | } | |
60c89071 | 1550 | |
b1379d9a | 1551 | tx_data += sizeof(*tx_desc); |
1552 | ||
60c89071 | 1553 | len = skb->len; |
1554 | if (skb_copy_bits(skb, 0, tx_data, len) < 0) { | |
1555 | struct net_device_stats *stats = &tp->netdev->stats; | |
1556 | ||
1557 | stats->tx_dropped++; | |
1558 | dev_kfree_skb_any(skb); | |
1559 | tx_data -= sizeof(*tx_desc); | |
1560 | continue; | |
1561 | } | |
1562 | ||
1563 | tx_data += len; | |
b1379d9a | 1564 | agg->skb_len += len; |
60c89071 | 1565 | agg->skb_num++; |
1566 | ||
b1379d9a | 1567 | dev_kfree_skb_any(skb); |
1568 | ||
7937f9e5 | 1569 | remain = rx_buf_sz - (int)(tx_agg_align(tx_data) - agg->head); |
b1379d9a | 1570 | } |
1571 | ||
d84130a1 | 1572 | if (!skb_queue_empty(&skb_head)) { |
0c3121fc | 1573 | spin_lock(&tx_queue->lock); |
d84130a1 | 1574 | skb_queue_splice(&skb_head, tx_queue); |
0c3121fc | 1575 | spin_unlock(&tx_queue->lock); |
d84130a1 | 1576 | } |
1577 | ||
0c3121fc | 1578 | netif_tx_lock(tp->netdev); |
dd1b119c | 1579 | |
1580 | if (netif_queue_stopped(tp->netdev) && | |
1581 | skb_queue_len(&tp->tx_queue) < tp->tx_qlen) | |
1582 | netif_wake_queue(tp->netdev); | |
1583 | ||
0c3121fc | 1584 | netif_tx_unlock(tp->netdev); |
9a4be1bd | 1585 | |
0c3121fc | 1586 | ret = usb_autopm_get_interface_async(tp->intf); |
9a4be1bd | 1587 | if (ret < 0) |
1588 | goto out_tx_fill; | |
dd1b119c | 1589 | |
b1379d9a | 1590 | usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2), |
1591 | agg->head, (int)(tx_data - (u8 *)agg->head), | |
1592 | (usb_complete_t)write_bulk_callback, agg); | |
1593 | ||
0c3121fc | 1594 | ret = usb_submit_urb(agg->urb, GFP_ATOMIC); |
9a4be1bd | 1595 | if (ret < 0) |
0c3121fc | 1596 | usb_autopm_put_interface_async(tp->intf); |
9a4be1bd | 1597 | |
1598 | out_tx_fill: | |
1599 | return ret; | |
b1379d9a | 1600 | } |
1601 | ||
565cab0a | 1602 | static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc) |
1603 | { | |
1604 | u8 checksum = CHECKSUM_NONE; | |
1605 | u32 opts2, opts3; | |
1606 | ||
1607 | if (tp->version == RTL_VER_01) | |
1608 | goto return_result; | |
1609 | ||
1610 | opts2 = le32_to_cpu(rx_desc->opts2); | |
1611 | opts3 = le32_to_cpu(rx_desc->opts3); | |
1612 | ||
1613 | if (opts2 & RD_IPV4_CS) { | |
1614 | if (opts3 & IPF) | |
1615 | checksum = CHECKSUM_NONE; | |
1616 | else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF)) | |
1617 | checksum = CHECKSUM_NONE; | |
1618 | else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF)) | |
1619 | checksum = CHECKSUM_NONE; | |
1620 | else | |
1621 | checksum = CHECKSUM_UNNECESSARY; | |
6128d1bb | 1622 | } else if (RD_IPV6_CS) { |
1623 | if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF)) | |
1624 | checksum = CHECKSUM_UNNECESSARY; | |
1625 | else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF)) | |
1626 | checksum = CHECKSUM_UNNECESSARY; | |
565cab0a | 1627 | } |
1628 | ||
1629 | return_result: | |
1630 | return checksum; | |
1631 | } | |
1632 | ||
ebc2ec48 | 1633 | static void rx_bottom(struct r8152 *tp) |
1634 | { | |
a5a4f468 | 1635 | unsigned long flags; |
d84130a1 | 1636 | struct list_head *cursor, *next, rx_queue; |
ebc2ec48 | 1637 | |
d84130a1 | 1638 | if (list_empty(&tp->rx_done)) |
1639 | return; | |
1640 | ||
1641 | INIT_LIST_HEAD(&rx_queue); | |
a5a4f468 | 1642 | spin_lock_irqsave(&tp->rx_lock, flags); |
d84130a1 | 1643 | list_splice_init(&tp->rx_done, &rx_queue); |
1644 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
1645 | ||
1646 | list_for_each_safe(cursor, next, &rx_queue) { | |
43a4478d | 1647 | struct rx_desc *rx_desc; |
1648 | struct rx_agg *agg; | |
43a4478d | 1649 | int len_used = 0; |
1650 | struct urb *urb; | |
1651 | u8 *rx_data; | |
1652 | int ret; | |
1653 | ||
ebc2ec48 | 1654 | list_del_init(cursor); |
ebc2ec48 | 1655 | |
1656 | agg = list_entry(cursor, struct rx_agg, list); | |
1657 | urb = agg->urb; | |
0de98f6c | 1658 | if (urb->actual_length < ETH_ZLEN) |
1659 | goto submit; | |
ebc2ec48 | 1660 | |
ebc2ec48 | 1661 | rx_desc = agg->head; |
1662 | rx_data = agg->head; | |
7937f9e5 | 1663 | len_used += sizeof(struct rx_desc); |
ebc2ec48 | 1664 | |
7937f9e5 | 1665 | while (urb->actual_length > len_used) { |
43a4478d | 1666 | struct net_device *netdev = tp->netdev; |
05e0f1aa | 1667 | struct net_device_stats *stats = &netdev->stats; |
7937f9e5 | 1668 | unsigned int pkt_len; |
43a4478d | 1669 | struct sk_buff *skb; |
1670 | ||
7937f9e5 | 1671 | pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; |
ebc2ec48 | 1672 | if (pkt_len < ETH_ZLEN) |
1673 | break; | |
1674 | ||
7937f9e5 | 1675 | len_used += pkt_len; |
1676 | if (urb->actual_length < len_used) | |
1677 | break; | |
1678 | ||
8e1f51bd | 1679 | pkt_len -= CRC_SIZE; |
ebc2ec48 | 1680 | rx_data += sizeof(struct rx_desc); |
1681 | ||
1682 | skb = netdev_alloc_skb_ip_align(netdev, pkt_len); | |
1683 | if (!skb) { | |
1684 | stats->rx_dropped++; | |
5e2f7485 | 1685 | goto find_next_rx; |
ebc2ec48 | 1686 | } |
565cab0a | 1687 | |
1688 | skb->ip_summed = r8152_rx_csum(tp, rx_desc); | |
ebc2ec48 | 1689 | memcpy(skb->data, rx_data, pkt_len); |
1690 | skb_put(skb, pkt_len); | |
1691 | skb->protocol = eth_type_trans(skb, netdev); | |
9d9aafa1 | 1692 | netif_receive_skb(skb); |
ebc2ec48 | 1693 | stats->rx_packets++; |
1694 | stats->rx_bytes += pkt_len; | |
1695 | ||
5e2f7485 | 1696 | find_next_rx: |
8e1f51bd | 1697 | rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE); |
ebc2ec48 | 1698 | rx_desc = (struct rx_desc *)rx_data; |
ebc2ec48 | 1699 | len_used = (int)(rx_data - (u8 *)agg->head); |
7937f9e5 | 1700 | len_used += sizeof(struct rx_desc); |
ebc2ec48 | 1701 | } |
1702 | ||
0de98f6c | 1703 | submit: |
ebc2ec48 | 1704 | ret = r8152_submit_rx(tp, agg, GFP_ATOMIC); |
ebc2ec48 | 1705 | if (ret && ret != -ENODEV) { |
d84130a1 | 1706 | spin_lock_irqsave(&tp->rx_lock, flags); |
1707 | list_add_tail(&agg->list, &tp->rx_done); | |
1708 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
ebc2ec48 | 1709 | tasklet_schedule(&tp->tl); |
1710 | } | |
1711 | } | |
ebc2ec48 | 1712 | } |
1713 | ||
1714 | static void tx_bottom(struct r8152 *tp) | |
1715 | { | |
ebc2ec48 | 1716 | int res; |
1717 | ||
b1379d9a | 1718 | do { |
1719 | struct tx_agg *agg; | |
ebc2ec48 | 1720 | |
b1379d9a | 1721 | if (skb_queue_empty(&tp->tx_queue)) |
ebc2ec48 | 1722 | break; |
1723 | ||
b1379d9a | 1724 | agg = r8152_get_tx_agg(tp); |
1725 | if (!agg) | |
ebc2ec48 | 1726 | break; |
ebc2ec48 | 1727 | |
b1379d9a | 1728 | res = r8152_tx_agg_fill(tp, agg); |
1729 | if (res) { | |
05e0f1aa | 1730 | struct net_device *netdev = tp->netdev; |
ebc2ec48 | 1731 | |
b1379d9a | 1732 | if (res == -ENODEV) { |
1733 | netif_device_detach(netdev); | |
1734 | } else { | |
05e0f1aa | 1735 | struct net_device_stats *stats = &netdev->stats; |
1736 | unsigned long flags; | |
1737 | ||
b1379d9a | 1738 | netif_warn(tp, tx_err, netdev, |
1739 | "failed tx_urb %d\n", res); | |
1740 | stats->tx_dropped += agg->skb_num; | |
db8515ef | 1741 | |
b1379d9a | 1742 | spin_lock_irqsave(&tp->tx_lock, flags); |
1743 | list_add_tail(&agg->list, &tp->tx_free); | |
1744 | spin_unlock_irqrestore(&tp->tx_lock, flags); | |
1745 | } | |
ebc2ec48 | 1746 | } |
b1379d9a | 1747 | } while (res == 0); |
ebc2ec48 | 1748 | } |
1749 | ||
1750 | static void bottom_half(unsigned long data) | |
ac718b69 | 1751 | { |
1752 | struct r8152 *tp; | |
ac718b69 | 1753 | |
ebc2ec48 | 1754 | tp = (struct r8152 *)data; |
1755 | ||
1756 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
1757 | return; | |
1758 | ||
1759 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
ac718b69 | 1760 | return; |
ebc2ec48 | 1761 | |
7559fb2f | 1762 | /* When link down, the driver would cancel all bulks. */ |
1763 | /* This avoid the re-submitting bulk */ | |
ebc2ec48 | 1764 | if (!netif_carrier_ok(tp->netdev)) |
ac718b69 | 1765 | return; |
ebc2ec48 | 1766 | |
1767 | rx_bottom(tp); | |
0c3121fc | 1768 | tx_bottom(tp); |
ebc2ec48 | 1769 | } |
1770 | ||
1771 | static | |
1772 | int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags) | |
1773 | { | |
1774 | usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1), | |
1775 | agg->head, rx_buf_sz, | |
1776 | (usb_complete_t)read_bulk_callback, agg); | |
1777 | ||
1778 | return usb_submit_urb(agg->urb, mem_flags); | |
ac718b69 | 1779 | } |
1780 | ||
00a5e360 | 1781 | static void rtl_drop_queued_tx(struct r8152 *tp) |
1782 | { | |
1783 | struct net_device_stats *stats = &tp->netdev->stats; | |
d84130a1 | 1784 | struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; |
00a5e360 | 1785 | struct sk_buff *skb; |
1786 | ||
d84130a1 | 1787 | if (skb_queue_empty(tx_queue)) |
1788 | return; | |
1789 | ||
1790 | __skb_queue_head_init(&skb_head); | |
2685d410 | 1791 | spin_lock_bh(&tx_queue->lock); |
d84130a1 | 1792 | skb_queue_splice_init(tx_queue, &skb_head); |
2685d410 | 1793 | spin_unlock_bh(&tx_queue->lock); |
d84130a1 | 1794 | |
1795 | while ((skb = __skb_dequeue(&skb_head))) { | |
00a5e360 | 1796 | dev_kfree_skb(skb); |
1797 | stats->tx_dropped++; | |
1798 | } | |
1799 | } | |
1800 | ||
ac718b69 | 1801 | static void rtl8152_tx_timeout(struct net_device *netdev) |
1802 | { | |
1803 | struct r8152 *tp = netdev_priv(netdev); | |
ebc2ec48 | 1804 | int i; |
1805 | ||
4a8deae2 | 1806 | netif_warn(tp, tx_err, netdev, "Tx timeout\n"); |
ebc2ec48 | 1807 | for (i = 0; i < RTL8152_MAX_TX; i++) |
1808 | usb_unlink_urb(tp->tx_info[i].urb); | |
ac718b69 | 1809 | } |
1810 | ||
1811 | static void rtl8152_set_rx_mode(struct net_device *netdev) | |
1812 | { | |
1813 | struct r8152 *tp = netdev_priv(netdev); | |
1814 | ||
40a82917 | 1815 | if (tp->speed & LINK_STATUS) { |
ac718b69 | 1816 | set_bit(RTL8152_SET_RX_MODE, &tp->flags); |
40a82917 | 1817 | schedule_delayed_work(&tp->schedule, 0); |
1818 | } | |
ac718b69 | 1819 | } |
1820 | ||
1821 | static void _rtl8152_set_rx_mode(struct net_device *netdev) | |
1822 | { | |
1823 | struct r8152 *tp = netdev_priv(netdev); | |
31787f53 | 1824 | u32 mc_filter[2]; /* Multicast hash filter */ |
1825 | __le32 tmp[2]; | |
ac718b69 | 1826 | u32 ocp_data; |
1827 | ||
ac718b69 | 1828 | clear_bit(RTL8152_SET_RX_MODE, &tp->flags); |
1829 | netif_stop_queue(netdev); | |
1830 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
1831 | ocp_data &= ~RCR_ACPT_ALL; | |
1832 | ocp_data |= RCR_AB | RCR_APM; | |
1833 | ||
1834 | if (netdev->flags & IFF_PROMISC) { | |
1835 | /* Unconditionally log net taps. */ | |
1836 | netif_notice(tp, link, netdev, "Promiscuous mode enabled\n"); | |
1837 | ocp_data |= RCR_AM | RCR_AAP; | |
1838 | mc_filter[1] = mc_filter[0] = 0xffffffff; | |
1839 | } else if ((netdev_mc_count(netdev) > multicast_filter_limit) || | |
1840 | (netdev->flags & IFF_ALLMULTI)) { | |
1841 | /* Too many to filter perfectly -- accept all multicasts. */ | |
1842 | ocp_data |= RCR_AM; | |
1843 | mc_filter[1] = mc_filter[0] = 0xffffffff; | |
1844 | } else { | |
1845 | struct netdev_hw_addr *ha; | |
1846 | ||
1847 | mc_filter[1] = mc_filter[0] = 0; | |
1848 | netdev_for_each_mc_addr(ha, netdev) { | |
1849 | int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; | |
1850 | mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); | |
1851 | ocp_data |= RCR_AM; | |
1852 | } | |
1853 | } | |
1854 | ||
31787f53 | 1855 | tmp[0] = __cpu_to_le32(swab32(mc_filter[1])); |
1856 | tmp[1] = __cpu_to_le32(swab32(mc_filter[0])); | |
ac718b69 | 1857 | |
31787f53 | 1858 | pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp); |
ac718b69 | 1859 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); |
1860 | netif_wake_queue(netdev); | |
ac718b69 | 1861 | } |
1862 | ||
1863 | static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb, | |
0c3121fc | 1864 | struct net_device *netdev) |
ac718b69 | 1865 | { |
1866 | struct r8152 *tp = netdev_priv(netdev); | |
ac718b69 | 1867 | |
ebc2ec48 | 1868 | skb_tx_timestamp(skb); |
ac718b69 | 1869 | |
61598788 | 1870 | skb_queue_tail(&tp->tx_queue, skb); |
ebc2ec48 | 1871 | |
0c3121fc | 1872 | if (!list_empty(&tp->tx_free)) { |
1873 | if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { | |
1874 | set_bit(SCHEDULE_TASKLET, &tp->flags); | |
1875 | schedule_delayed_work(&tp->schedule, 0); | |
1876 | } else { | |
1877 | usb_mark_last_busy(tp->udev); | |
1878 | tasklet_schedule(&tp->tl); | |
1879 | } | |
1880 | } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) | |
dd1b119c | 1881 | netif_stop_queue(netdev); |
1882 | ||
ac718b69 | 1883 | return NETDEV_TX_OK; |
1884 | } | |
1885 | ||
1886 | static void r8152b_reset_packet_filter(struct r8152 *tp) | |
1887 | { | |
1888 | u32 ocp_data; | |
1889 | ||
1890 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); | |
1891 | ocp_data &= ~FMC_FCR_MCU_EN; | |
1892 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); | |
1893 | ocp_data |= FMC_FCR_MCU_EN; | |
1894 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); | |
1895 | } | |
1896 | ||
1897 | static void rtl8152_nic_reset(struct r8152 *tp) | |
1898 | { | |
1899 | int i; | |
1900 | ||
1901 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST); | |
1902 | ||
1903 | for (i = 0; i < 1000; i++) { | |
1904 | if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST)) | |
1905 | break; | |
1906 | udelay(100); | |
1907 | } | |
1908 | } | |
1909 | ||
dd1b119c | 1910 | static void set_tx_qlen(struct r8152 *tp) |
1911 | { | |
1912 | struct net_device *netdev = tp->netdev; | |
1913 | ||
1914 | tp->tx_qlen = rx_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN + | |
1915 | sizeof(struct tx_desc)); | |
1916 | } | |
1917 | ||
ac718b69 | 1918 | static inline u8 rtl8152_get_speed(struct r8152 *tp) |
1919 | { | |
1920 | return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); | |
1921 | } | |
1922 | ||
507605a8 | 1923 | static void rtl_set_eee_plus(struct r8152 *tp) |
ac718b69 | 1924 | { |
ebc2ec48 | 1925 | u32 ocp_data; |
ac718b69 | 1926 | u8 speed; |
1927 | ||
1928 | speed = rtl8152_get_speed(tp); | |
ebc2ec48 | 1929 | if (speed & _10bps) { |
ac718b69 | 1930 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); |
ebc2ec48 | 1931 | ocp_data |= EEEP_CR_EEEP_TX; |
ac718b69 | 1932 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); |
1933 | } else { | |
1934 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); | |
ebc2ec48 | 1935 | ocp_data &= ~EEEP_CR_EEEP_TX; |
ac718b69 | 1936 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); |
1937 | } | |
507605a8 | 1938 | } |
1939 | ||
00a5e360 | 1940 | static void rxdy_gated_en(struct r8152 *tp, bool enable) |
1941 | { | |
1942 | u32 ocp_data; | |
1943 | ||
1944 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); | |
1945 | if (enable) | |
1946 | ocp_data |= RXDY_GATED_EN; | |
1947 | else | |
1948 | ocp_data &= ~RXDY_GATED_EN; | |
1949 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); | |
1950 | } | |
1951 | ||
445f7f4d | 1952 | static int rtl_start_rx(struct r8152 *tp) |
1953 | { | |
1954 | int i, ret = 0; | |
1955 | ||
1956 | INIT_LIST_HEAD(&tp->rx_done); | |
1957 | for (i = 0; i < RTL8152_MAX_RX; i++) { | |
1958 | INIT_LIST_HEAD(&tp->rx_info[i].list); | |
1959 | ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL); | |
1960 | if (ret) | |
1961 | break; | |
1962 | } | |
1963 | ||
1964 | return ret; | |
1965 | } | |
1966 | ||
1967 | static int rtl_stop_rx(struct r8152 *tp) | |
1968 | { | |
1969 | int i; | |
1970 | ||
1971 | for (i = 0; i < RTL8152_MAX_RX; i++) | |
1972 | usb_kill_urb(tp->rx_info[i].urb); | |
1973 | ||
1974 | return 0; | |
1975 | } | |
1976 | ||
507605a8 | 1977 | static int rtl_enable(struct r8152 *tp) |
1978 | { | |
1979 | u32 ocp_data; | |
ac718b69 | 1980 | |
1981 | r8152b_reset_packet_filter(tp); | |
1982 | ||
1983 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); | |
1984 | ocp_data |= CR_RE | CR_TE; | |
1985 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); | |
1986 | ||
00a5e360 | 1987 | rxdy_gated_en(tp, false); |
ac718b69 | 1988 | |
445f7f4d | 1989 | return rtl_start_rx(tp); |
ac718b69 | 1990 | } |
1991 | ||
507605a8 | 1992 | static int rtl8152_enable(struct r8152 *tp) |
1993 | { | |
6871438c | 1994 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
1995 | return -ENODEV; | |
1996 | ||
507605a8 | 1997 | set_tx_qlen(tp); |
1998 | rtl_set_eee_plus(tp); | |
1999 | ||
2000 | return rtl_enable(tp); | |
2001 | } | |
2002 | ||
43779f8d | 2003 | static void r8153_set_rx_agg(struct r8152 *tp) |
2004 | { | |
2005 | u8 speed; | |
2006 | ||
2007 | speed = rtl8152_get_speed(tp); | |
2008 | if (speed & _1000bps) { | |
2009 | if (tp->udev->speed == USB_SPEED_SUPER) { | |
2010 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, | |
2011 | RX_THR_SUPPER); | |
2012 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG, | |
2013 | EARLY_AGG_SUPPER); | |
2014 | } else { | |
2015 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, | |
2016 | RX_THR_HIGH); | |
2017 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG, | |
2018 | EARLY_AGG_HIGH); | |
2019 | } | |
2020 | } else { | |
2021 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_SLOW); | |
2022 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG, | |
2023 | EARLY_AGG_SLOW); | |
2024 | } | |
2025 | } | |
2026 | ||
2027 | static int rtl8153_enable(struct r8152 *tp) | |
2028 | { | |
6871438c | 2029 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
2030 | return -ENODEV; | |
2031 | ||
43779f8d | 2032 | set_tx_qlen(tp); |
2033 | rtl_set_eee_plus(tp); | |
2034 | r8153_set_rx_agg(tp); | |
2035 | ||
2036 | return rtl_enable(tp); | |
2037 | } | |
2038 | ||
d70b1137 | 2039 | static void rtl_disable(struct r8152 *tp) |
ac718b69 | 2040 | { |
ebc2ec48 | 2041 | u32 ocp_data; |
2042 | int i; | |
ac718b69 | 2043 | |
6871438c | 2044 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) { |
2045 | rtl_drop_queued_tx(tp); | |
2046 | return; | |
2047 | } | |
2048 | ||
ac718b69 | 2049 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); |
2050 | ocp_data &= ~RCR_ACPT_ALL; | |
2051 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2052 | ||
00a5e360 | 2053 | rtl_drop_queued_tx(tp); |
ebc2ec48 | 2054 | |
2055 | for (i = 0; i < RTL8152_MAX_TX; i++) | |
2056 | usb_kill_urb(tp->tx_info[i].urb); | |
ac718b69 | 2057 | |
00a5e360 | 2058 | rxdy_gated_en(tp, true); |
ac718b69 | 2059 | |
2060 | for (i = 0; i < 1000; i++) { | |
2061 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2062 | if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY) | |
2063 | break; | |
2064 | mdelay(1); | |
2065 | } | |
2066 | ||
2067 | for (i = 0; i < 1000; i++) { | |
2068 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY) | |
2069 | break; | |
2070 | mdelay(1); | |
2071 | } | |
2072 | ||
445f7f4d | 2073 | rtl_stop_rx(tp); |
ac718b69 | 2074 | |
2075 | rtl8152_nic_reset(tp); | |
2076 | } | |
2077 | ||
00a5e360 | 2078 | static void r8152_power_cut_en(struct r8152 *tp, bool enable) |
2079 | { | |
2080 | u32 ocp_data; | |
2081 | ||
2082 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); | |
2083 | if (enable) | |
2084 | ocp_data |= POWER_CUT; | |
2085 | else | |
2086 | ocp_data &= ~POWER_CUT; | |
2087 | ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); | |
2088 | ||
2089 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); | |
2090 | ocp_data &= ~RESUME_INDICATE; | |
2091 | ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); | |
00a5e360 | 2092 | } |
2093 | ||
21ff2e89 | 2094 | #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) |
2095 | ||
2096 | static u32 __rtl_get_wol(struct r8152 *tp) | |
2097 | { | |
2098 | u32 ocp_data; | |
2099 | u32 wolopts = 0; | |
2100 | ||
2101 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5); | |
2102 | if (!(ocp_data & LAN_WAKE_EN)) | |
2103 | return 0; | |
2104 | ||
2105 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); | |
2106 | if (ocp_data & LINK_ON_WAKE_EN) | |
2107 | wolopts |= WAKE_PHY; | |
2108 | ||
2109 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); | |
2110 | if (ocp_data & UWF_EN) | |
2111 | wolopts |= WAKE_UCAST; | |
2112 | if (ocp_data & BWF_EN) | |
2113 | wolopts |= WAKE_BCAST; | |
2114 | if (ocp_data & MWF_EN) | |
2115 | wolopts |= WAKE_MCAST; | |
2116 | ||
2117 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); | |
2118 | if (ocp_data & MAGIC_EN) | |
2119 | wolopts |= WAKE_MAGIC; | |
2120 | ||
2121 | return wolopts; | |
2122 | } | |
2123 | ||
2124 | static void __rtl_set_wol(struct r8152 *tp, u32 wolopts) | |
2125 | { | |
2126 | u32 ocp_data; | |
2127 | ||
2128 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
2129 | ||
2130 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); | |
2131 | ocp_data &= ~LINK_ON_WAKE_EN; | |
2132 | if (wolopts & WAKE_PHY) | |
2133 | ocp_data |= LINK_ON_WAKE_EN; | |
2134 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); | |
2135 | ||
2136 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); | |
2137 | ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN); | |
2138 | if (wolopts & WAKE_UCAST) | |
2139 | ocp_data |= UWF_EN; | |
2140 | if (wolopts & WAKE_BCAST) | |
2141 | ocp_data |= BWF_EN; | |
2142 | if (wolopts & WAKE_MCAST) | |
2143 | ocp_data |= MWF_EN; | |
2144 | if (wolopts & WAKE_ANY) | |
2145 | ocp_data |= LAN_WAKE_EN; | |
2146 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data); | |
2147 | ||
2148 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
2149 | ||
2150 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); | |
2151 | ocp_data &= ~MAGIC_EN; | |
2152 | if (wolopts & WAKE_MAGIC) | |
2153 | ocp_data |= MAGIC_EN; | |
2154 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data); | |
2155 | ||
2156 | if (wolopts & WAKE_ANY) | |
2157 | device_set_wakeup_enable(&tp->udev->dev, true); | |
2158 | else | |
2159 | device_set_wakeup_enable(&tp->udev->dev, false); | |
2160 | } | |
2161 | ||
9a4be1bd | 2162 | static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable) |
2163 | { | |
2164 | if (enable) { | |
2165 | u32 ocp_data; | |
2166 | ||
2167 | __rtl_set_wol(tp, WAKE_ANY); | |
2168 | ||
2169 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
2170 | ||
2171 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); | |
2172 | ocp_data |= LINK_OFF_WAKE_EN; | |
2173 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); | |
2174 | ||
2175 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
2176 | } else { | |
2177 | __rtl_set_wol(tp, tp->saved_wolopts); | |
2178 | } | |
2179 | } | |
2180 | ||
aa66a5f1 | 2181 | static void rtl_phy_reset(struct r8152 *tp) |
2182 | { | |
2183 | u16 data; | |
2184 | int i; | |
2185 | ||
2186 | clear_bit(PHY_RESET, &tp->flags); | |
2187 | ||
2188 | data = r8152_mdio_read(tp, MII_BMCR); | |
2189 | ||
2190 | /* don't reset again before the previous one complete */ | |
2191 | if (data & BMCR_RESET) | |
2192 | return; | |
2193 | ||
2194 | data |= BMCR_RESET; | |
2195 | r8152_mdio_write(tp, MII_BMCR, data); | |
2196 | ||
2197 | for (i = 0; i < 50; i++) { | |
2198 | msleep(20); | |
2199 | if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) | |
2200 | break; | |
2201 | } | |
2202 | } | |
2203 | ||
4349968a | 2204 | static void r8153_teredo_off(struct r8152 *tp) |
2205 | { | |
2206 | u32 ocp_data; | |
2207 | ||
2208 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); | |
2209 | ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN); | |
2210 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); | |
2211 | ||
2212 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE); | |
2213 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0); | |
2214 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0); | |
2215 | } | |
2216 | ||
2217 | static void r8152b_disable_aldps(struct r8152 *tp) | |
2218 | { | |
2219 | ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE); | |
2220 | msleep(20); | |
2221 | } | |
2222 | ||
2223 | static inline void r8152b_enable_aldps(struct r8152 *tp) | |
2224 | { | |
2225 | ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS | | |
2226 | LINKENA | DIS_SDSAVE); | |
2227 | } | |
2228 | ||
d70b1137 | 2229 | static void rtl8152_disable(struct r8152 *tp) |
2230 | { | |
2231 | r8152b_disable_aldps(tp); | |
2232 | rtl_disable(tp); | |
2233 | r8152b_enable_aldps(tp); | |
2234 | } | |
2235 | ||
4349968a | 2236 | static void r8152b_hw_phy_cfg(struct r8152 *tp) |
2237 | { | |
f0cbe0ac | 2238 | u16 data; |
2239 | ||
2240 | data = r8152_mdio_read(tp, MII_BMCR); | |
2241 | if (data & BMCR_PDOWN) { | |
2242 | data &= ~BMCR_PDOWN; | |
2243 | r8152_mdio_write(tp, MII_BMCR, data); | |
2244 | } | |
2245 | ||
aa66a5f1 | 2246 | set_bit(PHY_RESET, &tp->flags); |
4349968a | 2247 | } |
2248 | ||
ac718b69 | 2249 | static void r8152b_exit_oob(struct r8152 *tp) |
2250 | { | |
db8515ef | 2251 | u32 ocp_data; |
2252 | int i; | |
ac718b69 | 2253 | |
2254 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2255 | ocp_data &= ~RCR_ACPT_ALL; | |
2256 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2257 | ||
00a5e360 | 2258 | rxdy_gated_en(tp, true); |
da9bd117 | 2259 | r8153_teredo_off(tp); |
7e9da481 | 2260 | r8152b_hw_phy_cfg(tp); |
ac718b69 | 2261 | |
2262 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
2263 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); | |
2264 | ||
2265 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2266 | ocp_data &= ~NOW_IS_OOB; | |
2267 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2268 | ||
2269 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2270 | ocp_data &= ~MCU_BORW_EN; | |
2271 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2272 | ||
2273 | for (i = 0; i < 1000; i++) { | |
2274 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2275 | if (ocp_data & LINK_LIST_READY) | |
2276 | break; | |
2277 | mdelay(1); | |
2278 | } | |
2279 | ||
2280 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2281 | ocp_data |= RE_INIT_LL; | |
2282 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2283 | ||
2284 | for (i = 0; i < 1000; i++) { | |
2285 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2286 | if (ocp_data & LINK_LIST_READY) | |
2287 | break; | |
2288 | mdelay(1); | |
2289 | } | |
2290 | ||
2291 | rtl8152_nic_reset(tp); | |
2292 | ||
2293 | /* rx share fifo credit full threshold */ | |
2294 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); | |
2295 | ||
a3cc465d | 2296 | if (tp->udev->speed == USB_SPEED_FULL || |
2297 | tp->udev->speed == USB_SPEED_LOW) { | |
ac718b69 | 2298 | /* rx share fifo credit near full threshold */ |
2299 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, | |
2300 | RXFIFO_THR2_FULL); | |
2301 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, | |
2302 | RXFIFO_THR3_FULL); | |
2303 | } else { | |
2304 | /* rx share fifo credit near full threshold */ | |
2305 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, | |
2306 | RXFIFO_THR2_HIGH); | |
2307 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, | |
2308 | RXFIFO_THR3_HIGH); | |
2309 | } | |
2310 | ||
2311 | /* TX share fifo free credit full threshold */ | |
2312 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL); | |
2313 | ||
2314 | ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD); | |
8e1f51bd | 2315 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH); |
ac718b69 | 2316 | ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA, |
2317 | TEST_MODE_DISABLE | TX_SIZE_ADJUST1); | |
2318 | ||
2319 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); | |
2320 | ocp_data &= ~CPCR_RX_VLAN; | |
2321 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); | |
2322 | ||
2323 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); | |
2324 | ||
2325 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); | |
2326 | ocp_data |= TCR0_AUTO_FIFO; | |
2327 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); | |
2328 | } | |
2329 | ||
2330 | static void r8152b_enter_oob(struct r8152 *tp) | |
2331 | { | |
45f4a19f | 2332 | u32 ocp_data; |
2333 | int i; | |
ac718b69 | 2334 | |
2335 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2336 | ocp_data &= ~NOW_IS_OOB; | |
2337 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2338 | ||
2339 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); | |
2340 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); | |
2341 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB); | |
2342 | ||
d70b1137 | 2343 | rtl_disable(tp); |
ac718b69 | 2344 | |
2345 | for (i = 0; i < 1000; i++) { | |
2346 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2347 | if (ocp_data & LINK_LIST_READY) | |
2348 | break; | |
2349 | mdelay(1); | |
2350 | } | |
2351 | ||
2352 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2353 | ocp_data |= RE_INIT_LL; | |
2354 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2355 | ||
2356 | for (i = 0; i < 1000; i++) { | |
2357 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2358 | if (ocp_data & LINK_LIST_READY) | |
2359 | break; | |
2360 | mdelay(1); | |
2361 | } | |
2362 | ||
2363 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); | |
2364 | ||
ac718b69 | 2365 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); |
2366 | ocp_data |= CPCR_RX_VLAN; | |
2367 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); | |
2368 | ||
2369 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); | |
2370 | ocp_data |= ALDPS_PROXY_MODE; | |
2371 | ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); | |
2372 | ||
2373 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2374 | ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; | |
2375 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2376 | ||
00a5e360 | 2377 | rxdy_gated_en(tp, false); |
ac718b69 | 2378 | |
2379 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2380 | ocp_data |= RCR_APM | RCR_AM | RCR_AB; | |
2381 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2382 | } | |
2383 | ||
43779f8d | 2384 | static void r8153_hw_phy_cfg(struct r8152 *tp) |
2385 | { | |
2386 | u32 ocp_data; | |
2387 | u16 data; | |
2388 | ||
2389 | ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L); | |
f0cbe0ac | 2390 | data = r8152_mdio_read(tp, MII_BMCR); |
2391 | if (data & BMCR_PDOWN) { | |
2392 | data &= ~BMCR_PDOWN; | |
2393 | r8152_mdio_write(tp, MII_BMCR, data); | |
2394 | } | |
43779f8d | 2395 | |
2396 | if (tp->version == RTL_VER_03) { | |
2397 | data = ocp_reg_read(tp, OCP_EEE_CFG); | |
2398 | data &= ~CTAP_SHORT_EN; | |
2399 | ocp_reg_write(tp, OCP_EEE_CFG, data); | |
2400 | } | |
2401 | ||
2402 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
2403 | data |= EEE_CLKDIV_EN; | |
2404 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
2405 | ||
2406 | data = ocp_reg_read(tp, OCP_DOWN_SPEED); | |
2407 | data |= EN_10M_BGOFF; | |
2408 | ocp_reg_write(tp, OCP_DOWN_SPEED, data); | |
2409 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
2410 | data |= EN_10M_PLLOFF; | |
2411 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
2412 | data = sram_read(tp, SRAM_IMPEDANCE); | |
2413 | data &= ~RX_DRIVING_MASK; | |
2414 | sram_write(tp, SRAM_IMPEDANCE, data); | |
2415 | ||
2416 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); | |
2417 | ocp_data |= PFM_PWM_SWITCH; | |
2418 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); | |
2419 | ||
2420 | data = sram_read(tp, SRAM_LPF_CFG); | |
2421 | data |= LPF_AUTO_TUNE; | |
2422 | sram_write(tp, SRAM_LPF_CFG, data); | |
2423 | ||
2424 | data = sram_read(tp, SRAM_10M_AMP1); | |
2425 | data |= GDAC_IB_UPALL; | |
2426 | sram_write(tp, SRAM_10M_AMP1, data); | |
2427 | data = sram_read(tp, SRAM_10M_AMP2); | |
2428 | data |= AMP_DN; | |
2429 | sram_write(tp, SRAM_10M_AMP2, data); | |
aa66a5f1 | 2430 | |
2431 | set_bit(PHY_RESET, &tp->flags); | |
43779f8d | 2432 | } |
2433 | ||
b9702723 | 2434 | static void r8153_u1u2en(struct r8152 *tp, bool enable) |
43779f8d | 2435 | { |
2436 | u8 u1u2[8]; | |
2437 | ||
2438 | if (enable) | |
2439 | memset(u1u2, 0xff, sizeof(u1u2)); | |
2440 | else | |
2441 | memset(u1u2, 0x00, sizeof(u1u2)); | |
2442 | ||
2443 | usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2); | |
2444 | } | |
2445 | ||
b9702723 | 2446 | static void r8153_u2p3en(struct r8152 *tp, bool enable) |
43779f8d | 2447 | { |
2448 | u32 ocp_data; | |
2449 | ||
2450 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); | |
2451 | if (enable) | |
2452 | ocp_data |= U2P3_ENABLE; | |
2453 | else | |
2454 | ocp_data &= ~U2P3_ENABLE; | |
2455 | ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); | |
2456 | } | |
2457 | ||
b9702723 | 2458 | static void r8153_power_cut_en(struct r8152 *tp, bool enable) |
43779f8d | 2459 | { |
2460 | u32 ocp_data; | |
2461 | ||
2462 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); | |
2463 | if (enable) | |
2464 | ocp_data |= PWR_EN | PHASE2_EN; | |
2465 | else | |
2466 | ocp_data &= ~(PWR_EN | PHASE2_EN); | |
2467 | ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); | |
2468 | ||
2469 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); | |
2470 | ocp_data &= ~PCUT_STATUS; | |
2471 | ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); | |
2472 | } | |
2473 | ||
43779f8d | 2474 | static void r8153_first_init(struct r8152 *tp) |
2475 | { | |
2476 | u32 ocp_data; | |
2477 | int i; | |
2478 | ||
00a5e360 | 2479 | rxdy_gated_en(tp, true); |
43779f8d | 2480 | r8153_teredo_off(tp); |
2481 | ||
2482 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2483 | ocp_data &= ~RCR_ACPT_ALL; | |
2484 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2485 | ||
2486 | r8153_hw_phy_cfg(tp); | |
2487 | ||
2488 | rtl8152_nic_reset(tp); | |
2489 | ||
2490 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2491 | ocp_data &= ~NOW_IS_OOB; | |
2492 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2493 | ||
2494 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2495 | ocp_data &= ~MCU_BORW_EN; | |
2496 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2497 | ||
2498 | for (i = 0; i < 1000; i++) { | |
2499 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2500 | if (ocp_data & LINK_LIST_READY) | |
2501 | break; | |
2502 | mdelay(1); | |
2503 | } | |
2504 | ||
2505 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2506 | ocp_data |= RE_INIT_LL; | |
2507 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2508 | ||
2509 | for (i = 0; i < 1000; i++) { | |
2510 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2511 | if (ocp_data & LINK_LIST_READY) | |
2512 | break; | |
2513 | mdelay(1); | |
2514 | } | |
2515 | ||
2516 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); | |
2517 | ocp_data &= ~CPCR_RX_VLAN; | |
2518 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); | |
2519 | ||
69b4b7a4 | 2520 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS); |
2521 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO); | |
43779f8d | 2522 | |
2523 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); | |
2524 | ocp_data |= TCR0_AUTO_FIFO; | |
2525 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); | |
2526 | ||
2527 | rtl8152_nic_reset(tp); | |
2528 | ||
2529 | /* rx share fifo credit full threshold */ | |
2530 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); | |
2531 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL); | |
2532 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL); | |
2533 | /* TX share fifo free credit full threshold */ | |
2534 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2); | |
2535 | ||
9629e3c0 | 2536 | /* rx aggregation */ |
43779f8d | 2537 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); |
2538 | ocp_data &= ~RX_AGG_DISABLE; | |
2539 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); | |
2540 | } | |
2541 | ||
2542 | static void r8153_enter_oob(struct r8152 *tp) | |
2543 | { | |
2544 | u32 ocp_data; | |
2545 | int i; | |
2546 | ||
2547 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2548 | ocp_data &= ~NOW_IS_OOB; | |
2549 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2550 | ||
d70b1137 | 2551 | rtl_disable(tp); |
43779f8d | 2552 | |
2553 | for (i = 0; i < 1000; i++) { | |
2554 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2555 | if (ocp_data & LINK_LIST_READY) | |
2556 | break; | |
2557 | mdelay(1); | |
2558 | } | |
2559 | ||
2560 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2561 | ocp_data |= RE_INIT_LL; | |
2562 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2563 | ||
2564 | for (i = 0; i < 1000; i++) { | |
2565 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2566 | if (ocp_data & LINK_LIST_READY) | |
2567 | break; | |
2568 | mdelay(1); | |
2569 | } | |
2570 | ||
69b4b7a4 | 2571 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS); |
43779f8d | 2572 | |
43779f8d | 2573 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); |
2574 | ocp_data &= ~TEREDO_WAKE_MASK; | |
2575 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); | |
2576 | ||
2577 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); | |
2578 | ocp_data |= CPCR_RX_VLAN; | |
2579 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); | |
2580 | ||
2581 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); | |
2582 | ocp_data |= ALDPS_PROXY_MODE; | |
2583 | ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); | |
2584 | ||
2585 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2586 | ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; | |
2587 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2588 | ||
00a5e360 | 2589 | rxdy_gated_en(tp, false); |
43779f8d | 2590 | |
2591 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2592 | ocp_data |= RCR_APM | RCR_AM | RCR_AB; | |
2593 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2594 | } | |
2595 | ||
2596 | static void r8153_disable_aldps(struct r8152 *tp) | |
2597 | { | |
2598 | u16 data; | |
2599 | ||
2600 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
2601 | data &= ~EN_ALDPS; | |
2602 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
2603 | msleep(20); | |
2604 | } | |
2605 | ||
2606 | static void r8153_enable_aldps(struct r8152 *tp) | |
2607 | { | |
2608 | u16 data; | |
2609 | ||
2610 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
2611 | data |= EN_ALDPS; | |
2612 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
2613 | } | |
2614 | ||
d70b1137 | 2615 | static void rtl8153_disable(struct r8152 *tp) |
2616 | { | |
2617 | r8153_disable_aldps(tp); | |
2618 | rtl_disable(tp); | |
2619 | r8153_enable_aldps(tp); | |
2620 | } | |
2621 | ||
ac718b69 | 2622 | static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex) |
2623 | { | |
43779f8d | 2624 | u16 bmcr, anar, gbcr; |
ac718b69 | 2625 | int ret = 0; |
2626 | ||
2627 | cancel_delayed_work_sync(&tp->schedule); | |
2628 | anar = r8152_mdio_read(tp, MII_ADVERTISE); | |
2629 | anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | | |
2630 | ADVERTISE_100HALF | ADVERTISE_100FULL); | |
43779f8d | 2631 | if (tp->mii.supports_gmii) { |
2632 | gbcr = r8152_mdio_read(tp, MII_CTRL1000); | |
2633 | gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); | |
2634 | } else { | |
2635 | gbcr = 0; | |
2636 | } | |
ac718b69 | 2637 | |
2638 | if (autoneg == AUTONEG_DISABLE) { | |
2639 | if (speed == SPEED_10) { | |
2640 | bmcr = 0; | |
2641 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
2642 | } else if (speed == SPEED_100) { | |
2643 | bmcr = BMCR_SPEED100; | |
2644 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; | |
43779f8d | 2645 | } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { |
2646 | bmcr = BMCR_SPEED1000; | |
2647 | gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; | |
ac718b69 | 2648 | } else { |
2649 | ret = -EINVAL; | |
2650 | goto out; | |
2651 | } | |
2652 | ||
2653 | if (duplex == DUPLEX_FULL) | |
2654 | bmcr |= BMCR_FULLDPLX; | |
2655 | } else { | |
2656 | if (speed == SPEED_10) { | |
2657 | if (duplex == DUPLEX_FULL) | |
2658 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
2659 | else | |
2660 | anar |= ADVERTISE_10HALF; | |
2661 | } else if (speed == SPEED_100) { | |
2662 | if (duplex == DUPLEX_FULL) { | |
2663 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
2664 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; | |
2665 | } else { | |
2666 | anar |= ADVERTISE_10HALF; | |
2667 | anar |= ADVERTISE_100HALF; | |
2668 | } | |
43779f8d | 2669 | } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { |
2670 | if (duplex == DUPLEX_FULL) { | |
2671 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
2672 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; | |
2673 | gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; | |
2674 | } else { | |
2675 | anar |= ADVERTISE_10HALF; | |
2676 | anar |= ADVERTISE_100HALF; | |
2677 | gbcr |= ADVERTISE_1000HALF; | |
2678 | } | |
ac718b69 | 2679 | } else { |
2680 | ret = -EINVAL; | |
2681 | goto out; | |
2682 | } | |
2683 | ||
2684 | bmcr = BMCR_ANENABLE | BMCR_ANRESTART; | |
2685 | } | |
2686 | ||
aa66a5f1 | 2687 | if (test_bit(PHY_RESET, &tp->flags)) |
2688 | bmcr |= BMCR_RESET; | |
2689 | ||
43779f8d | 2690 | if (tp->mii.supports_gmii) |
2691 | r8152_mdio_write(tp, MII_CTRL1000, gbcr); | |
2692 | ||
ac718b69 | 2693 | r8152_mdio_write(tp, MII_ADVERTISE, anar); |
2694 | r8152_mdio_write(tp, MII_BMCR, bmcr); | |
2695 | ||
aa66a5f1 | 2696 | if (test_bit(PHY_RESET, &tp->flags)) { |
2697 | int i; | |
2698 | ||
2699 | clear_bit(PHY_RESET, &tp->flags); | |
2700 | for (i = 0; i < 50; i++) { | |
2701 | msleep(20); | |
2702 | if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) | |
2703 | break; | |
2704 | } | |
2705 | } | |
2706 | ||
ac718b69 | 2707 | out: |
ac718b69 | 2708 | |
2709 | return ret; | |
2710 | } | |
2711 | ||
d70b1137 | 2712 | static void rtl8152_up(struct r8152 *tp) |
2713 | { | |
2714 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
2715 | return; | |
2716 | ||
2717 | r8152b_disable_aldps(tp); | |
2718 | r8152b_exit_oob(tp); | |
2719 | r8152b_enable_aldps(tp); | |
2720 | } | |
2721 | ||
ac718b69 | 2722 | static void rtl8152_down(struct r8152 *tp) |
2723 | { | |
6871438c | 2724 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) { |
2725 | rtl_drop_queued_tx(tp); | |
2726 | return; | |
2727 | } | |
2728 | ||
00a5e360 | 2729 | r8152_power_cut_en(tp, false); |
ac718b69 | 2730 | r8152b_disable_aldps(tp); |
2731 | r8152b_enter_oob(tp); | |
2732 | r8152b_enable_aldps(tp); | |
2733 | } | |
2734 | ||
d70b1137 | 2735 | static void rtl8153_up(struct r8152 *tp) |
2736 | { | |
2737 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
2738 | return; | |
2739 | ||
2740 | r8153_disable_aldps(tp); | |
2741 | r8153_first_init(tp); | |
2742 | r8153_enable_aldps(tp); | |
2743 | } | |
2744 | ||
43779f8d | 2745 | static void rtl8153_down(struct r8152 *tp) |
2746 | { | |
6871438c | 2747 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) { |
2748 | rtl_drop_queued_tx(tp); | |
2749 | return; | |
2750 | } | |
2751 | ||
b9702723 | 2752 | r8153_u1u2en(tp, false); |
2753 | r8153_power_cut_en(tp, false); | |
43779f8d | 2754 | r8153_disable_aldps(tp); |
2755 | r8153_enter_oob(tp); | |
2756 | r8153_enable_aldps(tp); | |
2757 | } | |
2758 | ||
ac718b69 | 2759 | static void set_carrier(struct r8152 *tp) |
2760 | { | |
2761 | struct net_device *netdev = tp->netdev; | |
2762 | u8 speed; | |
2763 | ||
40a82917 | 2764 | clear_bit(RTL8152_LINK_CHG, &tp->flags); |
ac718b69 | 2765 | speed = rtl8152_get_speed(tp); |
2766 | ||
2767 | if (speed & LINK_STATUS) { | |
2768 | if (!(tp->speed & LINK_STATUS)) { | |
c81229c9 | 2769 | tp->rtl_ops.enable(tp); |
ac718b69 | 2770 | set_bit(RTL8152_SET_RX_MODE, &tp->flags); |
2771 | netif_carrier_on(netdev); | |
2772 | } | |
2773 | } else { | |
2774 | if (tp->speed & LINK_STATUS) { | |
2775 | netif_carrier_off(netdev); | |
ebc2ec48 | 2776 | tasklet_disable(&tp->tl); |
c81229c9 | 2777 | tp->rtl_ops.disable(tp); |
ebc2ec48 | 2778 | tasklet_enable(&tp->tl); |
ac718b69 | 2779 | } |
2780 | } | |
2781 | tp->speed = speed; | |
2782 | } | |
2783 | ||
2784 | static void rtl_work_func_t(struct work_struct *work) | |
2785 | { | |
2786 | struct r8152 *tp = container_of(work, struct r8152, schedule.work); | |
2787 | ||
9a4be1bd | 2788 | if (usb_autopm_get_interface(tp->intf) < 0) |
2789 | return; | |
2790 | ||
ac718b69 | 2791 | if (!test_bit(WORK_ENABLE, &tp->flags)) |
2792 | goto out1; | |
2793 | ||
2794 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
2795 | goto out1; | |
2796 | ||
40a82917 | 2797 | if (test_bit(RTL8152_LINK_CHG, &tp->flags)) |
2798 | set_carrier(tp); | |
ac718b69 | 2799 | |
2800 | if (test_bit(RTL8152_SET_RX_MODE, &tp->flags)) | |
2801 | _rtl8152_set_rx_mode(tp->netdev); | |
2802 | ||
0c3121fc | 2803 | if (test_bit(SCHEDULE_TASKLET, &tp->flags) && |
2804 | (tp->speed & LINK_STATUS)) { | |
2805 | clear_bit(SCHEDULE_TASKLET, &tp->flags); | |
2806 | tasklet_schedule(&tp->tl); | |
2807 | } | |
aa66a5f1 | 2808 | |
2809 | if (test_bit(PHY_RESET, &tp->flags)) | |
2810 | rtl_phy_reset(tp); | |
2811 | ||
ac718b69 | 2812 | out1: |
9a4be1bd | 2813 | usb_autopm_put_interface(tp->intf); |
ac718b69 | 2814 | } |
2815 | ||
2816 | static int rtl8152_open(struct net_device *netdev) | |
2817 | { | |
2818 | struct r8152 *tp = netdev_priv(netdev); | |
2819 | int res = 0; | |
2820 | ||
7e9da481 | 2821 | res = alloc_all_mem(tp); |
2822 | if (res) | |
2823 | goto out; | |
2824 | ||
9a4be1bd | 2825 | res = usb_autopm_get_interface(tp->intf); |
2826 | if (res < 0) { | |
2827 | free_all_mem(tp); | |
2828 | goto out; | |
2829 | } | |
2830 | ||
2831 | /* The WORK_ENABLE may be set when autoresume occurs */ | |
2832 | if (test_bit(WORK_ENABLE, &tp->flags)) { | |
2833 | clear_bit(WORK_ENABLE, &tp->flags); | |
2834 | usb_kill_urb(tp->intr_urb); | |
2835 | cancel_delayed_work_sync(&tp->schedule); | |
2836 | if (tp->speed & LINK_STATUS) | |
2837 | tp->rtl_ops.disable(tp); | |
2838 | } | |
2839 | ||
7e9da481 | 2840 | tp->rtl_ops.up(tp); |
2841 | ||
3d55f44f | 2842 | rtl8152_set_speed(tp, AUTONEG_ENABLE, |
2843 | tp->mii.supports_gmii ? SPEED_1000 : SPEED_100, | |
2844 | DUPLEX_FULL); | |
2845 | tp->speed = 0; | |
2846 | netif_carrier_off(netdev); | |
2847 | netif_start_queue(netdev); | |
2848 | set_bit(WORK_ENABLE, &tp->flags); | |
db8515ef | 2849 | |
40a82917 | 2850 | res = usb_submit_urb(tp->intr_urb, GFP_KERNEL); |
2851 | if (res) { | |
2852 | if (res == -ENODEV) | |
2853 | netif_device_detach(tp->netdev); | |
4a8deae2 HW |
2854 | netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n", |
2855 | res); | |
7e9da481 | 2856 | free_all_mem(tp); |
ac718b69 | 2857 | } |
2858 | ||
9a4be1bd | 2859 | usb_autopm_put_interface(tp->intf); |
ac718b69 | 2860 | |
7e9da481 | 2861 | out: |
ac718b69 | 2862 | return res; |
2863 | } | |
2864 | ||
2865 | static int rtl8152_close(struct net_device *netdev) | |
2866 | { | |
2867 | struct r8152 *tp = netdev_priv(netdev); | |
2868 | int res = 0; | |
2869 | ||
2870 | clear_bit(WORK_ENABLE, &tp->flags); | |
3d55f44f | 2871 | usb_kill_urb(tp->intr_urb); |
ac718b69 | 2872 | cancel_delayed_work_sync(&tp->schedule); |
2873 | netif_stop_queue(netdev); | |
9a4be1bd | 2874 | |
2875 | res = usb_autopm_get_interface(tp->intf); | |
2876 | if (res < 0) { | |
2877 | rtl_drop_queued_tx(tp); | |
2878 | } else { | |
2879 | /* | |
2880 | * The autosuspend may have been enabled and wouldn't | |
2881 | * be disable when autoresume occurs, because the | |
2882 | * netif_running() would be false. | |
2883 | */ | |
2884 | if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { | |
2885 | rtl_runtime_suspend_enable(tp, false); | |
2886 | clear_bit(SELECTIVE_SUSPEND, &tp->flags); | |
2887 | } | |
2888 | ||
2889 | tasklet_disable(&tp->tl); | |
2890 | tp->rtl_ops.down(tp); | |
2891 | tasklet_enable(&tp->tl); | |
2892 | usb_autopm_put_interface(tp->intf); | |
2893 | } | |
ac718b69 | 2894 | |
7e9da481 | 2895 | free_all_mem(tp); |
2896 | ||
ac718b69 | 2897 | return res; |
2898 | } | |
2899 | ||
ac718b69 | 2900 | static void r8152b_enable_eee(struct r8152 *tp) |
2901 | { | |
45f4a19f | 2902 | u32 ocp_data; |
ac718b69 | 2903 | |
2904 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); | |
2905 | ocp_data |= EEE_RX_EN | EEE_TX_EN; | |
2906 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); | |
2907 | ocp_reg_write(tp, OCP_EEE_CONFIG1, RG_TXLPI_MSK_HFDUP | RG_MATCLR_EN | | |
2908 | EEE_10_CAP | EEE_NWAY_EN | | |
2909 | TX_QUIET_EN | RX_QUIET_EN | | |
2910 | SDRISETIME | RG_RXLPI_MSK_HFDUP | | |
2911 | SDFALLTIME); | |
2912 | ocp_reg_write(tp, OCP_EEE_CONFIG2, RG_LPIHYS_NUM | RG_DACQUIET_EN | | |
2913 | RG_LDVQUIET_EN | RG_CKRSEL | | |
2914 | RG_EEEPRG_EN); | |
2915 | ocp_reg_write(tp, OCP_EEE_CONFIG3, FST_SNR_EYE_R | RG_LFS_SEL | MSK_PH); | |
2916 | ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | DEVICE_ADDR); | |
2917 | ocp_reg_write(tp, OCP_EEE_DATA, EEE_ADDR); | |
2918 | ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | DEVICE_ADDR); | |
2919 | ocp_reg_write(tp, OCP_EEE_DATA, EEE_DATA); | |
2920 | ocp_reg_write(tp, OCP_EEE_AR, 0x0000); | |
2921 | } | |
2922 | ||
43779f8d | 2923 | static void r8153_enable_eee(struct r8152 *tp) |
2924 | { | |
2925 | u32 ocp_data; | |
2926 | u16 data; | |
2927 | ||
2928 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); | |
2929 | ocp_data |= EEE_RX_EN | EEE_TX_EN; | |
2930 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); | |
2931 | data = ocp_reg_read(tp, OCP_EEE_CFG); | |
2932 | data |= EEE10_EN; | |
2933 | ocp_reg_write(tp, OCP_EEE_CFG, data); | |
2934 | data = ocp_reg_read(tp, OCP_EEE_CFG2); | |
2935 | data |= MY1000_EEE | MY100_EEE; | |
2936 | ocp_reg_write(tp, OCP_EEE_CFG2, data); | |
2937 | } | |
2938 | ||
ac718b69 | 2939 | static void r8152b_enable_fc(struct r8152 *tp) |
2940 | { | |
2941 | u16 anar; | |
2942 | ||
2943 | anar = r8152_mdio_read(tp, MII_ADVERTISE); | |
2944 | anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; | |
2945 | r8152_mdio_write(tp, MII_ADVERTISE, anar); | |
2946 | } | |
2947 | ||
4f1d4d54 | 2948 | static void rtl_tally_reset(struct r8152 *tp) |
2949 | { | |
2950 | u32 ocp_data; | |
2951 | ||
2952 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY); | |
2953 | ocp_data |= TALLY_RESET; | |
2954 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data); | |
2955 | } | |
2956 | ||
ac718b69 | 2957 | static void r8152b_init(struct r8152 *tp) |
2958 | { | |
ebc2ec48 | 2959 | u32 ocp_data; |
ac718b69 | 2960 | |
6871438c | 2961 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
2962 | return; | |
2963 | ||
d70b1137 | 2964 | r8152b_disable_aldps(tp); |
2965 | ||
ac718b69 | 2966 | if (tp->version == RTL_VER_01) { |
2967 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); | |
2968 | ocp_data &= ~LED_MODE_MASK; | |
2969 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); | |
2970 | } | |
2971 | ||
00a5e360 | 2972 | r8152_power_cut_en(tp, false); |
ac718b69 | 2973 | |
ac718b69 | 2974 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); |
2975 | ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH; | |
2976 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); | |
2977 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL); | |
2978 | ocp_data &= ~MCU_CLK_RATIO_MASK; | |
2979 | ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN; | |
2980 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data); | |
2981 | ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK | | |
2982 | SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK; | |
2983 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data); | |
2984 | ||
2985 | r8152b_enable_eee(tp); | |
2986 | r8152b_enable_aldps(tp); | |
2987 | r8152b_enable_fc(tp); | |
4f1d4d54 | 2988 | rtl_tally_reset(tp); |
ac718b69 | 2989 | |
ebc2ec48 | 2990 | /* enable rx aggregation */ |
ac718b69 | 2991 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); |
ebc2ec48 | 2992 | ocp_data &= ~RX_AGG_DISABLE; |
ac718b69 | 2993 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); |
2994 | } | |
2995 | ||
43779f8d | 2996 | static void r8153_init(struct r8152 *tp) |
2997 | { | |
2998 | u32 ocp_data; | |
2999 | int i; | |
3000 | ||
6871438c | 3001 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
3002 | return; | |
3003 | ||
d70b1137 | 3004 | r8153_disable_aldps(tp); |
b9702723 | 3005 | r8153_u1u2en(tp, false); |
43779f8d | 3006 | |
3007 | for (i = 0; i < 500; i++) { | |
3008 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & | |
3009 | AUTOLOAD_DONE) | |
3010 | break; | |
3011 | msleep(20); | |
3012 | } | |
3013 | ||
3014 | for (i = 0; i < 500; i++) { | |
3015 | ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK; | |
3016 | if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN) | |
3017 | break; | |
3018 | msleep(20); | |
3019 | } | |
3020 | ||
b9702723 | 3021 | r8153_u2p3en(tp, false); |
43779f8d | 3022 | |
3023 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL); | |
3024 | ocp_data &= ~TIMER11_EN; | |
3025 | ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data); | |
3026 | ||
43779f8d | 3027 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); |
3028 | ocp_data &= ~LED_MODE_MASK; | |
3029 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); | |
3030 | ||
3031 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL); | |
3032 | ocp_data &= ~LPM_TIMER_MASK; | |
3033 | if (tp->udev->speed == USB_SPEED_SUPER) | |
3034 | ocp_data |= LPM_TIMER_500US; | |
3035 | else | |
3036 | ocp_data |= LPM_TIMER_500MS; | |
3037 | ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data); | |
3038 | ||
3039 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2); | |
3040 | ocp_data &= ~SEN_VAL_MASK; | |
3041 | ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE; | |
3042 | ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data); | |
3043 | ||
b9702723 | 3044 | r8153_power_cut_en(tp, false); |
3045 | r8153_u1u2en(tp, true); | |
43779f8d | 3046 | |
43779f8d | 3047 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO); |
3048 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO); | |
3049 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, | |
3050 | PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN | | |
3051 | U1U2_SPDWN_EN | L1_SPDWN_EN); | |
3052 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, | |
3053 | PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN | | |
3054 | TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN | | |
3055 | EEE_SPDWN_EN); | |
3056 | ||
3057 | r8153_enable_eee(tp); | |
3058 | r8153_enable_aldps(tp); | |
3059 | r8152b_enable_fc(tp); | |
4f1d4d54 | 3060 | rtl_tally_reset(tp); |
43779f8d | 3061 | } |
3062 | ||
ac718b69 | 3063 | static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message) |
3064 | { | |
3065 | struct r8152 *tp = usb_get_intfdata(intf); | |
3066 | ||
9a4be1bd | 3067 | if (PMSG_IS_AUTO(message)) |
3068 | set_bit(SELECTIVE_SUSPEND, &tp->flags); | |
3069 | else | |
3070 | netif_device_detach(tp->netdev); | |
ac718b69 | 3071 | |
3072 | if (netif_running(tp->netdev)) { | |
3073 | clear_bit(WORK_ENABLE, &tp->flags); | |
40a82917 | 3074 | usb_kill_urb(tp->intr_urb); |
ac718b69 | 3075 | cancel_delayed_work_sync(&tp->schedule); |
445f7f4d | 3076 | tasklet_disable(&tp->tl); |
9a4be1bd | 3077 | if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { |
445f7f4d | 3078 | rtl_stop_rx(tp); |
9a4be1bd | 3079 | rtl_runtime_suspend_enable(tp, true); |
3080 | } else { | |
9a4be1bd | 3081 | tp->rtl_ops.down(tp); |
9a4be1bd | 3082 | } |
445f7f4d | 3083 | tasklet_enable(&tp->tl); |
ac718b69 | 3084 | } |
3085 | ||
ac718b69 | 3086 | return 0; |
3087 | } | |
3088 | ||
3089 | static int rtl8152_resume(struct usb_interface *intf) | |
3090 | { | |
3091 | struct r8152 *tp = usb_get_intfdata(intf); | |
3092 | ||
9a4be1bd | 3093 | if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) { |
3094 | tp->rtl_ops.init(tp); | |
3095 | netif_device_attach(tp->netdev); | |
3096 | } | |
3097 | ||
ac718b69 | 3098 | if (netif_running(tp->netdev)) { |
9a4be1bd | 3099 | if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { |
3100 | rtl_runtime_suspend_enable(tp, false); | |
3101 | clear_bit(SELECTIVE_SUSPEND, &tp->flags); | |
445f7f4d | 3102 | set_bit(WORK_ENABLE, &tp->flags); |
9a4be1bd | 3103 | if (tp->speed & LINK_STATUS) |
445f7f4d | 3104 | rtl_start_rx(tp); |
9a4be1bd | 3105 | } else { |
3106 | tp->rtl_ops.up(tp); | |
3107 | rtl8152_set_speed(tp, AUTONEG_ENABLE, | |
43779f8d | 3108 | tp->mii.supports_gmii ? SPEED_1000 : SPEED_100, |
3109 | DUPLEX_FULL); | |
445f7f4d | 3110 | tp->speed = 0; |
3111 | netif_carrier_off(tp->netdev); | |
3112 | set_bit(WORK_ENABLE, &tp->flags); | |
9a4be1bd | 3113 | } |
40a82917 | 3114 | usb_submit_urb(tp->intr_urb, GFP_KERNEL); |
ac718b69 | 3115 | } |
3116 | ||
3117 | return 0; | |
3118 | } | |
3119 | ||
21ff2e89 | 3120 | static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
3121 | { | |
3122 | struct r8152 *tp = netdev_priv(dev); | |
3123 | ||
9a4be1bd | 3124 | if (usb_autopm_get_interface(tp->intf) < 0) |
3125 | return; | |
3126 | ||
21ff2e89 | 3127 | wol->supported = WAKE_ANY; |
3128 | wol->wolopts = __rtl_get_wol(tp); | |
9a4be1bd | 3129 | |
3130 | usb_autopm_put_interface(tp->intf); | |
21ff2e89 | 3131 | } |
3132 | ||
3133 | static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
3134 | { | |
3135 | struct r8152 *tp = netdev_priv(dev); | |
9a4be1bd | 3136 | int ret; |
3137 | ||
3138 | ret = usb_autopm_get_interface(tp->intf); | |
3139 | if (ret < 0) | |
3140 | goto out_set_wol; | |
21ff2e89 | 3141 | |
3142 | __rtl_set_wol(tp, wol->wolopts); | |
3143 | tp->saved_wolopts = wol->wolopts & WAKE_ANY; | |
3144 | ||
9a4be1bd | 3145 | usb_autopm_put_interface(tp->intf); |
3146 | ||
3147 | out_set_wol: | |
3148 | return ret; | |
21ff2e89 | 3149 | } |
3150 | ||
a5ec27c1 | 3151 | static u32 rtl8152_get_msglevel(struct net_device *dev) |
3152 | { | |
3153 | struct r8152 *tp = netdev_priv(dev); | |
3154 | ||
3155 | return tp->msg_enable; | |
3156 | } | |
3157 | ||
3158 | static void rtl8152_set_msglevel(struct net_device *dev, u32 value) | |
3159 | { | |
3160 | struct r8152 *tp = netdev_priv(dev); | |
3161 | ||
3162 | tp->msg_enable = value; | |
3163 | } | |
3164 | ||
ac718b69 | 3165 | static void rtl8152_get_drvinfo(struct net_device *netdev, |
3166 | struct ethtool_drvinfo *info) | |
3167 | { | |
3168 | struct r8152 *tp = netdev_priv(netdev); | |
3169 | ||
3170 | strncpy(info->driver, MODULENAME, ETHTOOL_BUSINFO_LEN); | |
3171 | strncpy(info->version, DRIVER_VERSION, ETHTOOL_BUSINFO_LEN); | |
3172 | usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info)); | |
3173 | } | |
3174 | ||
3175 | static | |
3176 | int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd) | |
3177 | { | |
3178 | struct r8152 *tp = netdev_priv(netdev); | |
3179 | ||
3180 | if (!tp->mii.mdio_read) | |
3181 | return -EOPNOTSUPP; | |
3182 | ||
3183 | return mii_ethtool_gset(&tp->mii, cmd); | |
3184 | } | |
3185 | ||
3186 | static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
3187 | { | |
3188 | struct r8152 *tp = netdev_priv(dev); | |
9a4be1bd | 3189 | int ret; |
3190 | ||
3191 | ret = usb_autopm_get_interface(tp->intf); | |
3192 | if (ret < 0) | |
3193 | goto out; | |
ac718b69 | 3194 | |
9a4be1bd | 3195 | ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex); |
3196 | ||
3197 | usb_autopm_put_interface(tp->intf); | |
3198 | ||
3199 | out: | |
3200 | return ret; | |
ac718b69 | 3201 | } |
3202 | ||
4f1d4d54 | 3203 | static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = { |
3204 | "tx_packets", | |
3205 | "rx_packets", | |
3206 | "tx_errors", | |
3207 | "rx_errors", | |
3208 | "rx_missed", | |
3209 | "align_errors", | |
3210 | "tx_single_collisions", | |
3211 | "tx_multi_collisions", | |
3212 | "rx_unicast", | |
3213 | "rx_broadcast", | |
3214 | "rx_multicast", | |
3215 | "tx_aborted", | |
3216 | "tx_underrun", | |
3217 | }; | |
3218 | ||
3219 | static int rtl8152_get_sset_count(struct net_device *dev, int sset) | |
3220 | { | |
3221 | switch (sset) { | |
3222 | case ETH_SS_STATS: | |
3223 | return ARRAY_SIZE(rtl8152_gstrings); | |
3224 | default: | |
3225 | return -EOPNOTSUPP; | |
3226 | } | |
3227 | } | |
3228 | ||
3229 | static void rtl8152_get_ethtool_stats(struct net_device *dev, | |
3230 | struct ethtool_stats *stats, u64 *data) | |
3231 | { | |
3232 | struct r8152 *tp = netdev_priv(dev); | |
3233 | struct tally_counter tally; | |
3234 | ||
0b030244 | 3235 | if (usb_autopm_get_interface(tp->intf) < 0) |
3236 | return; | |
3237 | ||
4f1d4d54 | 3238 | generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA); |
3239 | ||
0b030244 | 3240 | usb_autopm_put_interface(tp->intf); |
3241 | ||
4f1d4d54 | 3242 | data[0] = le64_to_cpu(tally.tx_packets); |
3243 | data[1] = le64_to_cpu(tally.rx_packets); | |
3244 | data[2] = le64_to_cpu(tally.tx_errors); | |
3245 | data[3] = le32_to_cpu(tally.rx_errors); | |
3246 | data[4] = le16_to_cpu(tally.rx_missed); | |
3247 | data[5] = le16_to_cpu(tally.align_errors); | |
3248 | data[6] = le32_to_cpu(tally.tx_one_collision); | |
3249 | data[7] = le32_to_cpu(tally.tx_multi_collision); | |
3250 | data[8] = le64_to_cpu(tally.rx_unicast); | |
3251 | data[9] = le64_to_cpu(tally.rx_broadcast); | |
3252 | data[10] = le32_to_cpu(tally.rx_multicast); | |
3253 | data[11] = le16_to_cpu(tally.tx_aborted); | |
3254 | data[12] = le16_to_cpu(tally.tx_underun); | |
3255 | } | |
3256 | ||
3257 | static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data) | |
3258 | { | |
3259 | switch (stringset) { | |
3260 | case ETH_SS_STATS: | |
3261 | memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings)); | |
3262 | break; | |
3263 | } | |
3264 | } | |
3265 | ||
ac718b69 | 3266 | static struct ethtool_ops ops = { |
3267 | .get_drvinfo = rtl8152_get_drvinfo, | |
3268 | .get_settings = rtl8152_get_settings, | |
3269 | .set_settings = rtl8152_set_settings, | |
3270 | .get_link = ethtool_op_get_link, | |
a5ec27c1 | 3271 | .get_msglevel = rtl8152_get_msglevel, |
3272 | .set_msglevel = rtl8152_set_msglevel, | |
21ff2e89 | 3273 | .get_wol = rtl8152_get_wol, |
3274 | .set_wol = rtl8152_set_wol, | |
4f1d4d54 | 3275 | .get_strings = rtl8152_get_strings, |
3276 | .get_sset_count = rtl8152_get_sset_count, | |
3277 | .get_ethtool_stats = rtl8152_get_ethtool_stats, | |
ac718b69 | 3278 | }; |
3279 | ||
3280 | static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) | |
3281 | { | |
3282 | struct r8152 *tp = netdev_priv(netdev); | |
3283 | struct mii_ioctl_data *data = if_mii(rq); | |
9a4be1bd | 3284 | int res; |
3285 | ||
6871438c | 3286 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
3287 | return -ENODEV; | |
3288 | ||
9a4be1bd | 3289 | res = usb_autopm_get_interface(tp->intf); |
3290 | if (res < 0) | |
3291 | goto out; | |
ac718b69 | 3292 | |
3293 | switch (cmd) { | |
3294 | case SIOCGMIIPHY: | |
3295 | data->phy_id = R8152_PHY_ID; /* Internal PHY */ | |
3296 | break; | |
3297 | ||
3298 | case SIOCGMIIREG: | |
3299 | data->val_out = r8152_mdio_read(tp, data->reg_num); | |
3300 | break; | |
3301 | ||
3302 | case SIOCSMIIREG: | |
3303 | if (!capable(CAP_NET_ADMIN)) { | |
3304 | res = -EPERM; | |
3305 | break; | |
3306 | } | |
3307 | r8152_mdio_write(tp, data->reg_num, data->val_in); | |
3308 | break; | |
3309 | ||
3310 | default: | |
3311 | res = -EOPNOTSUPP; | |
3312 | } | |
3313 | ||
9a4be1bd | 3314 | usb_autopm_put_interface(tp->intf); |
3315 | ||
3316 | out: | |
ac718b69 | 3317 | return res; |
3318 | } | |
3319 | ||
69b4b7a4 | 3320 | static int rtl8152_change_mtu(struct net_device *dev, int new_mtu) |
3321 | { | |
3322 | struct r8152 *tp = netdev_priv(dev); | |
3323 | ||
3324 | switch (tp->version) { | |
3325 | case RTL_VER_01: | |
3326 | case RTL_VER_02: | |
3327 | return eth_change_mtu(dev, new_mtu); | |
3328 | default: | |
3329 | break; | |
3330 | } | |
3331 | ||
3332 | if (new_mtu < 68 || new_mtu > RTL8153_MAX_MTU) | |
3333 | return -EINVAL; | |
3334 | ||
3335 | dev->mtu = new_mtu; | |
3336 | ||
3337 | return 0; | |
3338 | } | |
3339 | ||
ac718b69 | 3340 | static const struct net_device_ops rtl8152_netdev_ops = { |
3341 | .ndo_open = rtl8152_open, | |
3342 | .ndo_stop = rtl8152_close, | |
3343 | .ndo_do_ioctl = rtl8152_ioctl, | |
3344 | .ndo_start_xmit = rtl8152_start_xmit, | |
3345 | .ndo_tx_timeout = rtl8152_tx_timeout, | |
3346 | .ndo_set_rx_mode = rtl8152_set_rx_mode, | |
3347 | .ndo_set_mac_address = rtl8152_set_mac_address, | |
69b4b7a4 | 3348 | .ndo_change_mtu = rtl8152_change_mtu, |
ac718b69 | 3349 | .ndo_validate_addr = eth_validate_addr, |
3350 | }; | |
3351 | ||
3352 | static void r8152b_get_version(struct r8152 *tp) | |
3353 | { | |
3354 | u32 ocp_data; | |
3355 | u16 version; | |
3356 | ||
3357 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1); | |
3358 | version = (u16)(ocp_data & VERSION_MASK); | |
3359 | ||
3360 | switch (version) { | |
3361 | case 0x4c00: | |
3362 | tp->version = RTL_VER_01; | |
3363 | break; | |
3364 | case 0x4c10: | |
3365 | tp->version = RTL_VER_02; | |
3366 | break; | |
43779f8d | 3367 | case 0x5c00: |
3368 | tp->version = RTL_VER_03; | |
3369 | tp->mii.supports_gmii = 1; | |
3370 | break; | |
3371 | case 0x5c10: | |
3372 | tp->version = RTL_VER_04; | |
3373 | tp->mii.supports_gmii = 1; | |
3374 | break; | |
3375 | case 0x5c20: | |
3376 | tp->version = RTL_VER_05; | |
3377 | tp->mii.supports_gmii = 1; | |
3378 | break; | |
ac718b69 | 3379 | default: |
3380 | netif_info(tp, probe, tp->netdev, | |
3381 | "Unknown version 0x%04x\n", version); | |
3382 | break; | |
3383 | } | |
3384 | } | |
3385 | ||
e3fe0b1a | 3386 | static void rtl8152_unload(struct r8152 *tp) |
3387 | { | |
6871438c | 3388 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
3389 | return; | |
3390 | ||
00a5e360 | 3391 | if (tp->version != RTL_VER_01) |
3392 | r8152_power_cut_en(tp, true); | |
e3fe0b1a | 3393 | } |
3394 | ||
43779f8d | 3395 | static void rtl8153_unload(struct r8152 *tp) |
3396 | { | |
6871438c | 3397 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
3398 | return; | |
3399 | ||
49be1723 | 3400 | r8153_power_cut_en(tp, false); |
43779f8d | 3401 | } |
3402 | ||
31ca1dec | 3403 | static int rtl_ops_init(struct r8152 *tp, const struct usb_device_id *id) |
c81229c9 | 3404 | { |
3405 | struct rtl_ops *ops = &tp->rtl_ops; | |
31ca1dec | 3406 | int ret = -ENODEV; |
c81229c9 | 3407 | |
3408 | switch (id->idVendor) { | |
3409 | case VENDOR_ID_REALTEK: | |
3410 | switch (id->idProduct) { | |
3411 | case PRODUCT_ID_RTL8152: | |
3412 | ops->init = r8152b_init; | |
3413 | ops->enable = rtl8152_enable; | |
3414 | ops->disable = rtl8152_disable; | |
d70b1137 | 3415 | ops->up = rtl8152_up; |
c81229c9 | 3416 | ops->down = rtl8152_down; |
3417 | ops->unload = rtl8152_unload; | |
31ca1dec | 3418 | ret = 0; |
c81229c9 | 3419 | break; |
43779f8d | 3420 | case PRODUCT_ID_RTL8153: |
3421 | ops->init = r8153_init; | |
3422 | ops->enable = rtl8153_enable; | |
d70b1137 | 3423 | ops->disable = rtl8153_disable; |
3424 | ops->up = rtl8153_up; | |
43779f8d | 3425 | ops->down = rtl8153_down; |
3426 | ops->unload = rtl8153_unload; | |
31ca1dec | 3427 | ret = 0; |
43779f8d | 3428 | break; |
3429 | default: | |
43779f8d | 3430 | break; |
3431 | } | |
3432 | break; | |
3433 | ||
3434 | case VENDOR_ID_SAMSUNG: | |
3435 | switch (id->idProduct) { | |
3436 | case PRODUCT_ID_SAMSUNG: | |
3437 | ops->init = r8153_init; | |
3438 | ops->enable = rtl8153_enable; | |
d70b1137 | 3439 | ops->disable = rtl8153_disable; |
3440 | ops->up = rtl8153_up; | |
43779f8d | 3441 | ops->down = rtl8153_down; |
3442 | ops->unload = rtl8153_unload; | |
31ca1dec | 3443 | ret = 0; |
43779f8d | 3444 | break; |
c81229c9 | 3445 | default: |
c81229c9 | 3446 | break; |
3447 | } | |
3448 | break; | |
3449 | ||
3450 | default: | |
c81229c9 | 3451 | break; |
3452 | } | |
3453 | ||
31ca1dec | 3454 | if (ret) |
3455 | netif_err(tp, probe, tp->netdev, "Unknown Device\n"); | |
3456 | ||
c81229c9 | 3457 | return ret; |
3458 | } | |
3459 | ||
ac718b69 | 3460 | static int rtl8152_probe(struct usb_interface *intf, |
3461 | const struct usb_device_id *id) | |
3462 | { | |
3463 | struct usb_device *udev = interface_to_usbdev(intf); | |
3464 | struct r8152 *tp; | |
3465 | struct net_device *netdev; | |
ebc2ec48 | 3466 | int ret; |
ac718b69 | 3467 | |
10c32717 | 3468 | if (udev->actconfig->desc.bConfigurationValue != 1) { |
3469 | usb_driver_set_configuration(udev, 1); | |
3470 | return -ENODEV; | |
3471 | } | |
3472 | ||
3473 | usb_reset_device(udev); | |
ac718b69 | 3474 | netdev = alloc_etherdev(sizeof(struct r8152)); |
3475 | if (!netdev) { | |
4a8deae2 | 3476 | dev_err(&intf->dev, "Out of memory\n"); |
ac718b69 | 3477 | return -ENOMEM; |
3478 | } | |
3479 | ||
ebc2ec48 | 3480 | SET_NETDEV_DEV(netdev, &intf->dev); |
ac718b69 | 3481 | tp = netdev_priv(netdev); |
3482 | tp->msg_enable = 0x7FFF; | |
3483 | ||
e3ad412a | 3484 | tp->udev = udev; |
3485 | tp->netdev = netdev; | |
3486 | tp->intf = intf; | |
3487 | ||
31ca1dec | 3488 | ret = rtl_ops_init(tp, id); |
3489 | if (ret) | |
3490 | goto out; | |
c81229c9 | 3491 | |
ebc2ec48 | 3492 | tasklet_init(&tp->tl, bottom_half, (unsigned long)tp); |
ac718b69 | 3493 | INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t); |
3494 | ||
ac718b69 | 3495 | netdev->netdev_ops = &rtl8152_netdev_ops; |
3496 | netdev->watchdog_timeo = RTL8152_TX_TIMEOUT; | |
5bd23881 | 3497 | |
60c89071 | 3498 | netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | |
6128d1bb | 3499 | NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM | |
3500 | NETIF_F_TSO6; | |
60c89071 | 3501 | netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | |
6128d1bb | 3502 | NETIF_F_TSO | NETIF_F_FRAGLIST | |
3503 | NETIF_F_IPV6_CSUM | NETIF_F_TSO6; | |
db8515ef | 3504 | |
7ad24ea4 | 3505 | netdev->ethtool_ops = &ops; |
60c89071 | 3506 | netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE); |
ac718b69 | 3507 | |
3508 | tp->mii.dev = netdev; | |
3509 | tp->mii.mdio_read = read_mii_word; | |
3510 | tp->mii.mdio_write = write_mii_word; | |
3511 | tp->mii.phy_id_mask = 0x3f; | |
3512 | tp->mii.reg_num_mask = 0x1f; | |
3513 | tp->mii.phy_id = R8152_PHY_ID; | |
3514 | tp->mii.supports_gmii = 0; | |
3515 | ||
9a4be1bd | 3516 | intf->needs_remote_wakeup = 1; |
3517 | ||
ac718b69 | 3518 | r8152b_get_version(tp); |
c81229c9 | 3519 | tp->rtl_ops.init(tp); |
ac718b69 | 3520 | set_ethernet_addr(tp); |
3521 | ||
ac718b69 | 3522 | usb_set_intfdata(intf, tp); |
ac718b69 | 3523 | |
ebc2ec48 | 3524 | ret = register_netdev(netdev); |
3525 | if (ret != 0) { | |
4a8deae2 | 3526 | netif_err(tp, probe, netdev, "couldn't register the device\n"); |
ebc2ec48 | 3527 | goto out1; |
ac718b69 | 3528 | } |
3529 | ||
21ff2e89 | 3530 | tp->saved_wolopts = __rtl_get_wol(tp); |
3531 | if (tp->saved_wolopts) | |
3532 | device_set_wakeup_enable(&udev->dev, true); | |
3533 | else | |
3534 | device_set_wakeup_enable(&udev->dev, false); | |
3535 | ||
4a8deae2 | 3536 | netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION); |
ac718b69 | 3537 | |
3538 | return 0; | |
3539 | ||
ac718b69 | 3540 | out1: |
ebc2ec48 | 3541 | usb_set_intfdata(intf, NULL); |
ac718b69 | 3542 | out: |
3543 | free_netdev(netdev); | |
ebc2ec48 | 3544 | return ret; |
ac718b69 | 3545 | } |
3546 | ||
ac718b69 | 3547 | static void rtl8152_disconnect(struct usb_interface *intf) |
3548 | { | |
3549 | struct r8152 *tp = usb_get_intfdata(intf); | |
3550 | ||
3551 | usb_set_intfdata(intf, NULL); | |
3552 | if (tp) { | |
f561de33 | 3553 | struct usb_device *udev = tp->udev; |
3554 | ||
3555 | if (udev->state == USB_STATE_NOTATTACHED) | |
3556 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
3557 | ||
ac718b69 | 3558 | tasklet_kill(&tp->tl); |
3559 | unregister_netdev(tp->netdev); | |
c81229c9 | 3560 | tp->rtl_ops.unload(tp); |
ac718b69 | 3561 | free_netdev(tp->netdev); |
3562 | } | |
3563 | } | |
3564 | ||
3565 | /* table of devices that work with this driver */ | |
3566 | static struct usb_device_id rtl8152_table[] = { | |
10c32717 | 3567 | {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8152)}, |
3568 | {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8153)}, | |
3569 | {USB_DEVICE(VENDOR_ID_SAMSUNG, PRODUCT_ID_SAMSUNG)}, | |
ac718b69 | 3570 | {} |
3571 | }; | |
3572 | ||
3573 | MODULE_DEVICE_TABLE(usb, rtl8152_table); | |
3574 | ||
3575 | static struct usb_driver rtl8152_driver = { | |
3576 | .name = MODULENAME, | |
ebc2ec48 | 3577 | .id_table = rtl8152_table, |
ac718b69 | 3578 | .probe = rtl8152_probe, |
3579 | .disconnect = rtl8152_disconnect, | |
ac718b69 | 3580 | .suspend = rtl8152_suspend, |
ebc2ec48 | 3581 | .resume = rtl8152_resume, |
3582 | .reset_resume = rtl8152_resume, | |
9a4be1bd | 3583 | .supports_autosuspend = 1, |
a634782f | 3584 | .disable_hub_initiated_lpm = 1, |
ac718b69 | 3585 | }; |
3586 | ||
b4236daa | 3587 | module_usb_driver(rtl8152_driver); |
ac718b69 | 3588 | |
3589 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
3590 | MODULE_DESCRIPTION(DRIVER_DESC); | |
3591 | MODULE_LICENSE("GPL"); |