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ac718b69 | 1 | /* |
c7de7dec | 2 | * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved. |
ac718b69 | 3 | * |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * version 2 as published by the Free Software Foundation. | |
7 | * | |
8 | */ | |
9 | ||
ac718b69 | 10 | #include <linux/signal.h> |
11 | #include <linux/slab.h> | |
12 | #include <linux/module.h> | |
ac718b69 | 13 | #include <linux/netdevice.h> |
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/mii.h> | |
16 | #include <linux/ethtool.h> | |
17 | #include <linux/usb.h> | |
18 | #include <linux/crc32.h> | |
19 | #include <linux/if_vlan.h> | |
20 | #include <linux/uaccess.h> | |
ebc2ec48 | 21 | #include <linux/list.h> |
5bd23881 | 22 | #include <linux/ip.h> |
23 | #include <linux/ipv6.h> | |
6128d1bb | 24 | #include <net/ip6_checksum.h> |
ac718b69 | 25 | |
26 | /* Version Information */ | |
60c89071 | 27 | #define DRIVER_VERSION "v1.06.0 (2014/03/03)" |
ac718b69 | 28 | #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>" |
44d942a9 | 29 | #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters" |
ac718b69 | 30 | #define MODULENAME "r8152" |
31 | ||
32 | #define R8152_PHY_ID 32 | |
33 | ||
34 | #define PLA_IDR 0xc000 | |
35 | #define PLA_RCR 0xc010 | |
36 | #define PLA_RMS 0xc016 | |
37 | #define PLA_RXFIFO_CTRL0 0xc0a0 | |
38 | #define PLA_RXFIFO_CTRL1 0xc0a4 | |
39 | #define PLA_RXFIFO_CTRL2 0xc0a8 | |
40 | #define PLA_FMC 0xc0b4 | |
41 | #define PLA_CFG_WOL 0xc0b6 | |
43779f8d | 42 | #define PLA_TEREDO_CFG 0xc0bc |
ac718b69 | 43 | #define PLA_MAR 0xcd00 |
43779f8d | 44 | #define PLA_BACKUP 0xd000 |
ac718b69 | 45 | #define PAL_BDC_CR 0xd1a0 |
43779f8d | 46 | #define PLA_TEREDO_TIMER 0xd2cc |
47 | #define PLA_REALWOW_TIMER 0xd2e8 | |
ac718b69 | 48 | #define PLA_LEDSEL 0xdd90 |
49 | #define PLA_LED_FEATURE 0xdd92 | |
50 | #define PLA_PHYAR 0xde00 | |
43779f8d | 51 | #define PLA_BOOT_CTRL 0xe004 |
ac718b69 | 52 | #define PLA_GPHY_INTR_IMR 0xe022 |
53 | #define PLA_EEE_CR 0xe040 | |
54 | #define PLA_EEEP_CR 0xe080 | |
55 | #define PLA_MAC_PWR_CTRL 0xe0c0 | |
43779f8d | 56 | #define PLA_MAC_PWR_CTRL2 0xe0ca |
57 | #define PLA_MAC_PWR_CTRL3 0xe0cc | |
58 | #define PLA_MAC_PWR_CTRL4 0xe0ce | |
59 | #define PLA_WDT6_CTRL 0xe428 | |
ac718b69 | 60 | #define PLA_TCR0 0xe610 |
61 | #define PLA_TCR1 0xe612 | |
69b4b7a4 | 62 | #define PLA_MTPS 0xe615 |
ac718b69 | 63 | #define PLA_TXFIFO_CTRL 0xe618 |
4f1d4d54 | 64 | #define PLA_RSTTALLY 0xe800 |
ac718b69 | 65 | #define PLA_CR 0xe813 |
66 | #define PLA_CRWECR 0xe81c | |
21ff2e89 | 67 | #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */ |
68 | #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */ | |
ac718b69 | 69 | #define PLA_CONFIG5 0xe822 |
70 | #define PLA_PHY_PWR 0xe84c | |
71 | #define PLA_OOB_CTRL 0xe84f | |
72 | #define PLA_CPCR 0xe854 | |
73 | #define PLA_MISC_0 0xe858 | |
74 | #define PLA_MISC_1 0xe85a | |
75 | #define PLA_OCP_GPHY_BASE 0xe86c | |
4f1d4d54 | 76 | #define PLA_TALLYCNT 0xe890 |
ac718b69 | 77 | #define PLA_SFF_STS_7 0xe8de |
78 | #define PLA_PHYSTATUS 0xe908 | |
79 | #define PLA_BP_BA 0xfc26 | |
80 | #define PLA_BP_0 0xfc28 | |
81 | #define PLA_BP_1 0xfc2a | |
82 | #define PLA_BP_2 0xfc2c | |
83 | #define PLA_BP_3 0xfc2e | |
84 | #define PLA_BP_4 0xfc30 | |
85 | #define PLA_BP_5 0xfc32 | |
86 | #define PLA_BP_6 0xfc34 | |
87 | #define PLA_BP_7 0xfc36 | |
43779f8d | 88 | #define PLA_BP_EN 0xfc38 |
ac718b69 | 89 | |
43779f8d | 90 | #define USB_U2P3_CTRL 0xb460 |
ac718b69 | 91 | #define USB_DEV_STAT 0xb808 |
92 | #define USB_USB_CTRL 0xd406 | |
93 | #define USB_PHY_CTRL 0xd408 | |
94 | #define USB_TX_AGG 0xd40a | |
95 | #define USB_RX_BUF_TH 0xd40c | |
96 | #define USB_USB_TIMER 0xd428 | |
43779f8d | 97 | #define USB_RX_EARLY_AGG 0xd42c |
ac718b69 | 98 | #define USB_PM_CTRL_STATUS 0xd432 |
99 | #define USB_TX_DMA 0xd434 | |
43779f8d | 100 | #define USB_TOLERANCE 0xd490 |
101 | #define USB_LPM_CTRL 0xd41a | |
ac718b69 | 102 | #define USB_UPS_CTRL 0xd800 |
43779f8d | 103 | #define USB_MISC_0 0xd81a |
104 | #define USB_POWER_CUT 0xd80a | |
105 | #define USB_AFE_CTRL2 0xd824 | |
106 | #define USB_WDT11_CTRL 0xe43c | |
ac718b69 | 107 | #define USB_BP_BA 0xfc26 |
108 | #define USB_BP_0 0xfc28 | |
109 | #define USB_BP_1 0xfc2a | |
110 | #define USB_BP_2 0xfc2c | |
111 | #define USB_BP_3 0xfc2e | |
112 | #define USB_BP_4 0xfc30 | |
113 | #define USB_BP_5 0xfc32 | |
114 | #define USB_BP_6 0xfc34 | |
115 | #define USB_BP_7 0xfc36 | |
43779f8d | 116 | #define USB_BP_EN 0xfc38 |
ac718b69 | 117 | |
118 | /* OCP Registers */ | |
119 | #define OCP_ALDPS_CONFIG 0x2010 | |
120 | #define OCP_EEE_CONFIG1 0x2080 | |
121 | #define OCP_EEE_CONFIG2 0x2092 | |
122 | #define OCP_EEE_CONFIG3 0x2094 | |
ac244d3e | 123 | #define OCP_BASE_MII 0xa400 |
ac718b69 | 124 | #define OCP_EEE_AR 0xa41a |
125 | #define OCP_EEE_DATA 0xa41c | |
43779f8d | 126 | #define OCP_PHY_STATUS 0xa420 |
127 | #define OCP_POWER_CFG 0xa430 | |
128 | #define OCP_EEE_CFG 0xa432 | |
129 | #define OCP_SRAM_ADDR 0xa436 | |
130 | #define OCP_SRAM_DATA 0xa438 | |
131 | #define OCP_DOWN_SPEED 0xa442 | |
132 | #define OCP_EEE_CFG2 0xa5d0 | |
133 | #define OCP_ADC_CFG 0xbc06 | |
134 | ||
135 | /* SRAM Register */ | |
136 | #define SRAM_LPF_CFG 0x8012 | |
137 | #define SRAM_10M_AMP1 0x8080 | |
138 | #define SRAM_10M_AMP2 0x8082 | |
139 | #define SRAM_IMPEDANCE 0x8084 | |
ac718b69 | 140 | |
141 | /* PLA_RCR */ | |
142 | #define RCR_AAP 0x00000001 | |
143 | #define RCR_APM 0x00000002 | |
144 | #define RCR_AM 0x00000004 | |
145 | #define RCR_AB 0x00000008 | |
146 | #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB) | |
147 | ||
148 | /* PLA_RXFIFO_CTRL0 */ | |
149 | #define RXFIFO_THR1_NORMAL 0x00080002 | |
150 | #define RXFIFO_THR1_OOB 0x01800003 | |
151 | ||
152 | /* PLA_RXFIFO_CTRL1 */ | |
153 | #define RXFIFO_THR2_FULL 0x00000060 | |
154 | #define RXFIFO_THR2_HIGH 0x00000038 | |
155 | #define RXFIFO_THR2_OOB 0x0000004a | |
43779f8d | 156 | #define RXFIFO_THR2_NORMAL 0x00a0 |
ac718b69 | 157 | |
158 | /* PLA_RXFIFO_CTRL2 */ | |
159 | #define RXFIFO_THR3_FULL 0x00000078 | |
160 | #define RXFIFO_THR3_HIGH 0x00000048 | |
161 | #define RXFIFO_THR3_OOB 0x0000005a | |
43779f8d | 162 | #define RXFIFO_THR3_NORMAL 0x0110 |
ac718b69 | 163 | |
164 | /* PLA_TXFIFO_CTRL */ | |
165 | #define TXFIFO_THR_NORMAL 0x00400008 | |
43779f8d | 166 | #define TXFIFO_THR_NORMAL2 0x01000008 |
ac718b69 | 167 | |
168 | /* PLA_FMC */ | |
169 | #define FMC_FCR_MCU_EN 0x0001 | |
170 | ||
171 | /* PLA_EEEP_CR */ | |
172 | #define EEEP_CR_EEEP_TX 0x0002 | |
173 | ||
43779f8d | 174 | /* PLA_WDT6_CTRL */ |
175 | #define WDT6_SET_MODE 0x0010 | |
176 | ||
ac718b69 | 177 | /* PLA_TCR0 */ |
178 | #define TCR0_TX_EMPTY 0x0800 | |
179 | #define TCR0_AUTO_FIFO 0x0080 | |
180 | ||
181 | /* PLA_TCR1 */ | |
182 | #define VERSION_MASK 0x7cf0 | |
183 | ||
69b4b7a4 | 184 | /* PLA_MTPS */ |
185 | #define MTPS_JUMBO (12 * 1024 / 64) | |
186 | #define MTPS_DEFAULT (6 * 1024 / 64) | |
187 | ||
4f1d4d54 | 188 | /* PLA_RSTTALLY */ |
189 | #define TALLY_RESET 0x0001 | |
190 | ||
ac718b69 | 191 | /* PLA_CR */ |
192 | #define CR_RST 0x10 | |
193 | #define CR_RE 0x08 | |
194 | #define CR_TE 0x04 | |
195 | ||
196 | /* PLA_CRWECR */ | |
197 | #define CRWECR_NORAML 0x00 | |
198 | #define CRWECR_CONFIG 0xc0 | |
199 | ||
200 | /* PLA_OOB_CTRL */ | |
201 | #define NOW_IS_OOB 0x80 | |
202 | #define TXFIFO_EMPTY 0x20 | |
203 | #define RXFIFO_EMPTY 0x10 | |
204 | #define LINK_LIST_READY 0x02 | |
205 | #define DIS_MCU_CLROOB 0x01 | |
206 | #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY) | |
207 | ||
208 | /* PLA_MISC_1 */ | |
209 | #define RXDY_GATED_EN 0x0008 | |
210 | ||
211 | /* PLA_SFF_STS_7 */ | |
212 | #define RE_INIT_LL 0x8000 | |
213 | #define MCU_BORW_EN 0x4000 | |
214 | ||
215 | /* PLA_CPCR */ | |
216 | #define CPCR_RX_VLAN 0x0040 | |
217 | ||
218 | /* PLA_CFG_WOL */ | |
219 | #define MAGIC_EN 0x0001 | |
220 | ||
43779f8d | 221 | /* PLA_TEREDO_CFG */ |
222 | #define TEREDO_SEL 0x8000 | |
223 | #define TEREDO_WAKE_MASK 0x7f00 | |
224 | #define TEREDO_RS_EVENT_MASK 0x00fe | |
225 | #define OOB_TEREDO_EN 0x0001 | |
226 | ||
ac718b69 | 227 | /* PAL_BDC_CR */ |
228 | #define ALDPS_PROXY_MODE 0x0001 | |
229 | ||
21ff2e89 | 230 | /* PLA_CONFIG34 */ |
231 | #define LINK_ON_WAKE_EN 0x0010 | |
232 | #define LINK_OFF_WAKE_EN 0x0008 | |
233 | ||
ac718b69 | 234 | /* PLA_CONFIG5 */ |
21ff2e89 | 235 | #define BWF_EN 0x0040 |
236 | #define MWF_EN 0x0020 | |
237 | #define UWF_EN 0x0010 | |
ac718b69 | 238 | #define LAN_WAKE_EN 0x0002 |
239 | ||
240 | /* PLA_LED_FEATURE */ | |
241 | #define LED_MODE_MASK 0x0700 | |
242 | ||
243 | /* PLA_PHY_PWR */ | |
244 | #define TX_10M_IDLE_EN 0x0080 | |
245 | #define PFM_PWM_SWITCH 0x0040 | |
246 | ||
247 | /* PLA_MAC_PWR_CTRL */ | |
248 | #define D3_CLK_GATED_EN 0x00004000 | |
249 | #define MCU_CLK_RATIO 0x07010f07 | |
250 | #define MCU_CLK_RATIO_MASK 0x0f0f0f0f | |
43779f8d | 251 | #define ALDPS_SPDWN_RATIO 0x0f87 |
252 | ||
253 | /* PLA_MAC_PWR_CTRL2 */ | |
254 | #define EEE_SPDWN_RATIO 0x8007 | |
255 | ||
256 | /* PLA_MAC_PWR_CTRL3 */ | |
257 | #define PKT_AVAIL_SPDWN_EN 0x0100 | |
258 | #define SUSPEND_SPDWN_EN 0x0004 | |
259 | #define U1U2_SPDWN_EN 0x0002 | |
260 | #define L1_SPDWN_EN 0x0001 | |
261 | ||
262 | /* PLA_MAC_PWR_CTRL4 */ | |
263 | #define PWRSAVE_SPDWN_EN 0x1000 | |
264 | #define RXDV_SPDWN_EN 0x0800 | |
265 | #define TX10MIDLE_EN 0x0100 | |
266 | #define TP100_SPDWN_EN 0x0020 | |
267 | #define TP500_SPDWN_EN 0x0010 | |
268 | #define TP1000_SPDWN_EN 0x0008 | |
269 | #define EEE_SPDWN_EN 0x0001 | |
ac718b69 | 270 | |
271 | /* PLA_GPHY_INTR_IMR */ | |
272 | #define GPHY_STS_MSK 0x0001 | |
273 | #define SPEED_DOWN_MSK 0x0002 | |
274 | #define SPDWN_RXDV_MSK 0x0004 | |
275 | #define SPDWN_LINKCHG_MSK 0x0008 | |
276 | ||
277 | /* PLA_PHYAR */ | |
278 | #define PHYAR_FLAG 0x80000000 | |
279 | ||
280 | /* PLA_EEE_CR */ | |
281 | #define EEE_RX_EN 0x0001 | |
282 | #define EEE_TX_EN 0x0002 | |
283 | ||
43779f8d | 284 | /* PLA_BOOT_CTRL */ |
285 | #define AUTOLOAD_DONE 0x0002 | |
286 | ||
ac718b69 | 287 | /* USB_DEV_STAT */ |
288 | #define STAT_SPEED_MASK 0x0006 | |
289 | #define STAT_SPEED_HIGH 0x0000 | |
a3cc465d | 290 | #define STAT_SPEED_FULL 0x0002 |
ac718b69 | 291 | |
292 | /* USB_TX_AGG */ | |
293 | #define TX_AGG_MAX_THRESHOLD 0x03 | |
294 | ||
295 | /* USB_RX_BUF_TH */ | |
43779f8d | 296 | #define RX_THR_SUPPER 0x0c350180 |
8e1f51bd | 297 | #define RX_THR_HIGH 0x7a120180 |
43779f8d | 298 | #define RX_THR_SLOW 0xffff0180 |
ac718b69 | 299 | |
300 | /* USB_TX_DMA */ | |
301 | #define TEST_MODE_DISABLE 0x00000001 | |
302 | #define TX_SIZE_ADJUST1 0x00000100 | |
303 | ||
304 | /* USB_UPS_CTRL */ | |
305 | #define POWER_CUT 0x0100 | |
306 | ||
307 | /* USB_PM_CTRL_STATUS */ | |
8e1f51bd | 308 | #define RESUME_INDICATE 0x0001 |
ac718b69 | 309 | |
310 | /* USB_USB_CTRL */ | |
311 | #define RX_AGG_DISABLE 0x0010 | |
312 | ||
43779f8d | 313 | /* USB_U2P3_CTRL */ |
314 | #define U2P3_ENABLE 0x0001 | |
315 | ||
316 | /* USB_POWER_CUT */ | |
317 | #define PWR_EN 0x0001 | |
318 | #define PHASE2_EN 0x0008 | |
319 | ||
320 | /* USB_MISC_0 */ | |
321 | #define PCUT_STATUS 0x0001 | |
322 | ||
323 | /* USB_RX_EARLY_AGG */ | |
324 | #define EARLY_AGG_SUPPER 0x0e832981 | |
325 | #define EARLY_AGG_HIGH 0x0e837a12 | |
326 | #define EARLY_AGG_SLOW 0x0e83ffff | |
327 | ||
328 | /* USB_WDT11_CTRL */ | |
329 | #define TIMER11_EN 0x0001 | |
330 | ||
331 | /* USB_LPM_CTRL */ | |
332 | #define LPM_TIMER_MASK 0x0c | |
333 | #define LPM_TIMER_500MS 0x04 /* 500 ms */ | |
334 | #define LPM_TIMER_500US 0x0c /* 500 us */ | |
335 | ||
336 | /* USB_AFE_CTRL2 */ | |
337 | #define SEN_VAL_MASK 0xf800 | |
338 | #define SEN_VAL_NORMAL 0xa000 | |
339 | #define SEL_RXIDLE 0x0100 | |
340 | ||
ac718b69 | 341 | /* OCP_ALDPS_CONFIG */ |
342 | #define ENPWRSAVE 0x8000 | |
343 | #define ENPDNPS 0x0200 | |
344 | #define LINKENA 0x0100 | |
345 | #define DIS_SDSAVE 0x0010 | |
346 | ||
43779f8d | 347 | /* OCP_PHY_STATUS */ |
348 | #define PHY_STAT_MASK 0x0007 | |
349 | #define PHY_STAT_LAN_ON 3 | |
350 | #define PHY_STAT_PWRDN 5 | |
351 | ||
352 | /* OCP_POWER_CFG */ | |
353 | #define EEE_CLKDIV_EN 0x8000 | |
354 | #define EN_ALDPS 0x0004 | |
355 | #define EN_10M_PLLOFF 0x0001 | |
356 | ||
ac718b69 | 357 | /* OCP_EEE_CONFIG1 */ |
358 | #define RG_TXLPI_MSK_HFDUP 0x8000 | |
359 | #define RG_MATCLR_EN 0x4000 | |
360 | #define EEE_10_CAP 0x2000 | |
361 | #define EEE_NWAY_EN 0x1000 | |
362 | #define TX_QUIET_EN 0x0200 | |
363 | #define RX_QUIET_EN 0x0100 | |
364 | #define SDRISETIME 0x0010 /* bit 4 ~ 6 */ | |
365 | #define RG_RXLPI_MSK_HFDUP 0x0008 | |
366 | #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */ | |
367 | ||
368 | /* OCP_EEE_CONFIG2 */ | |
369 | #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */ | |
370 | #define RG_DACQUIET_EN 0x0400 | |
371 | #define RG_LDVQUIET_EN 0x0200 | |
372 | #define RG_CKRSEL 0x0020 | |
373 | #define RG_EEEPRG_EN 0x0010 | |
374 | ||
375 | /* OCP_EEE_CONFIG3 */ | |
376 | #define FST_SNR_EYE_R 0x1500 /* bit 7 ~ 15 */ | |
377 | #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */ | |
378 | #define MSK_PH 0x0006 /* bit 0 ~ 3 */ | |
379 | ||
380 | /* OCP_EEE_AR */ | |
381 | /* bit[15:14] function */ | |
382 | #define FUN_ADDR 0x0000 | |
383 | #define FUN_DATA 0x4000 | |
384 | /* bit[4:0] device addr */ | |
385 | #define DEVICE_ADDR 0x0007 | |
386 | ||
387 | /* OCP_EEE_DATA */ | |
388 | #define EEE_ADDR 0x003C | |
389 | #define EEE_DATA 0x0002 | |
390 | ||
43779f8d | 391 | /* OCP_EEE_CFG */ |
392 | #define CTAP_SHORT_EN 0x0040 | |
393 | #define EEE10_EN 0x0010 | |
394 | ||
395 | /* OCP_DOWN_SPEED */ | |
396 | #define EN_10M_BGOFF 0x0080 | |
397 | ||
398 | /* OCP_EEE_CFG2 */ | |
399 | #define MY1000_EEE 0x0004 | |
400 | #define MY100_EEE 0x0002 | |
401 | ||
402 | /* OCP_ADC_CFG */ | |
403 | #define CKADSEL_L 0x0100 | |
404 | #define ADC_EN 0x0080 | |
405 | #define EN_EMI_L 0x0040 | |
406 | ||
407 | /* SRAM_LPF_CFG */ | |
408 | #define LPF_AUTO_TUNE 0x8000 | |
409 | ||
410 | /* SRAM_10M_AMP1 */ | |
411 | #define GDAC_IB_UPALL 0x0008 | |
412 | ||
413 | /* SRAM_10M_AMP2 */ | |
414 | #define AMP_DN 0x0200 | |
415 | ||
416 | /* SRAM_IMPEDANCE */ | |
417 | #define RX_DRIVING_MASK 0x6000 | |
418 | ||
ac718b69 | 419 | enum rtl_register_content { |
43779f8d | 420 | _1000bps = 0x10, |
ac718b69 | 421 | _100bps = 0x08, |
422 | _10bps = 0x04, | |
423 | LINK_STATUS = 0x02, | |
424 | FULL_DUP = 0x01, | |
425 | }; | |
426 | ||
1764bcd9 | 427 | #define RTL8152_MAX_TX 4 |
ebc2ec48 | 428 | #define RTL8152_MAX_RX 10 |
40a82917 | 429 | #define INTBUFSIZE 2 |
8e1f51bd | 430 | #define CRC_SIZE 4 |
431 | #define TX_ALIGN 4 | |
432 | #define RX_ALIGN 8 | |
40a82917 | 433 | |
434 | #define INTR_LINK 0x0004 | |
ebc2ec48 | 435 | |
ac718b69 | 436 | #define RTL8152_REQT_READ 0xc0 |
437 | #define RTL8152_REQT_WRITE 0x40 | |
438 | #define RTL8152_REQ_GET_REGS 0x05 | |
439 | #define RTL8152_REQ_SET_REGS 0x05 | |
440 | ||
441 | #define BYTE_EN_DWORD 0xff | |
442 | #define BYTE_EN_WORD 0x33 | |
443 | #define BYTE_EN_BYTE 0x11 | |
444 | #define BYTE_EN_SIX_BYTES 0x3f | |
445 | #define BYTE_EN_START_MASK 0x0f | |
446 | #define BYTE_EN_END_MASK 0xf0 | |
447 | ||
69b4b7a4 | 448 | #define RTL8153_MAX_PACKET 9216 /* 9K */ |
449 | #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN) | |
ac718b69 | 450 | #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN) |
69b4b7a4 | 451 | #define RTL8153_RMS RTL8153_MAX_PACKET |
b8125404 | 452 | #define RTL8152_TX_TIMEOUT (5 * HZ) |
ac718b69 | 453 | |
454 | /* rtl8152 flags */ | |
455 | enum rtl8152_flags { | |
456 | RTL8152_UNPLUG = 0, | |
ac718b69 | 457 | RTL8152_SET_RX_MODE, |
40a82917 | 458 | WORK_ENABLE, |
459 | RTL8152_LINK_CHG, | |
9a4be1bd | 460 | SELECTIVE_SUSPEND, |
aa66a5f1 | 461 | PHY_RESET, |
0c3121fc | 462 | SCHEDULE_TASKLET, |
ac718b69 | 463 | }; |
464 | ||
465 | /* Define these values to match your device */ | |
466 | #define VENDOR_ID_REALTEK 0x0bda | |
467 | #define PRODUCT_ID_RTL8152 0x8152 | |
43779f8d | 468 | #define PRODUCT_ID_RTL8153 0x8153 |
469 | ||
470 | #define VENDOR_ID_SAMSUNG 0x04e8 | |
471 | #define PRODUCT_ID_SAMSUNG 0xa101 | |
ac718b69 | 472 | |
473 | #define MCU_TYPE_PLA 0x0100 | |
474 | #define MCU_TYPE_USB 0x0000 | |
475 | ||
c7de7dec | 476 | #define REALTEK_USB_DEVICE(vend, prod) \ |
477 | USB_DEVICE_INTERFACE_CLASS(vend, prod, USB_CLASS_VENDOR_SPEC) | |
478 | ||
4f1d4d54 | 479 | struct tally_counter { |
480 | __le64 tx_packets; | |
481 | __le64 rx_packets; | |
482 | __le64 tx_errors; | |
483 | __le32 rx_errors; | |
484 | __le16 rx_missed; | |
485 | __le16 align_errors; | |
486 | __le32 tx_one_collision; | |
487 | __le32 tx_multi_collision; | |
488 | __le64 rx_unicast; | |
489 | __le64 rx_broadcast; | |
490 | __le32 rx_multicast; | |
491 | __le16 tx_aborted; | |
492 | __le16 tx_underun; | |
493 | }; | |
494 | ||
ac718b69 | 495 | struct rx_desc { |
500b6d7e | 496 | __le32 opts1; |
ac718b69 | 497 | #define RX_LEN_MASK 0x7fff |
565cab0a | 498 | |
500b6d7e | 499 | __le32 opts2; |
565cab0a | 500 | #define RD_UDP_CS (1 << 23) |
501 | #define RD_TCP_CS (1 << 22) | |
6128d1bb | 502 | #define RD_IPV6_CS (1 << 20) |
565cab0a | 503 | #define RD_IPV4_CS (1 << 19) |
504 | ||
500b6d7e | 505 | __le32 opts3; |
565cab0a | 506 | #define IPF (1 << 23) /* IP checksum fail */ |
507 | #define UDPF (1 << 22) /* UDP checksum fail */ | |
508 | #define TCPF (1 << 21) /* TCP checksum fail */ | |
509 | ||
500b6d7e | 510 | __le32 opts4; |
511 | __le32 opts5; | |
512 | __le32 opts6; | |
ac718b69 | 513 | }; |
514 | ||
515 | struct tx_desc { | |
500b6d7e | 516 | __le32 opts1; |
ac718b69 | 517 | #define TX_FS (1 << 31) /* First segment of a packet */ |
518 | #define TX_LS (1 << 30) /* Final segment of a packet */ | |
60c89071 | 519 | #define GTSENDV4 (1 << 28) |
6128d1bb | 520 | #define GTSENDV6 (1 << 27) |
60c89071 | 521 | #define GTTCPHO_SHIFT 18 |
6128d1bb | 522 | #define GTTCPHO_MAX 0x7fU |
60c89071 | 523 | #define TX_LEN_MAX 0x3ffffU |
5bd23881 | 524 | |
500b6d7e | 525 | __le32 opts2; |
5bd23881 | 526 | #define UDP_CS (1 << 31) /* Calculate UDP/IP checksum */ |
527 | #define TCP_CS (1 << 30) /* Calculate TCP/IP checksum */ | |
528 | #define IPV4_CS (1 << 29) /* Calculate IPv4 checksum */ | |
529 | #define IPV6_CS (1 << 28) /* Calculate IPv6 checksum */ | |
60c89071 | 530 | #define MSS_SHIFT 17 |
531 | #define MSS_MAX 0x7ffU | |
532 | #define TCPHO_SHIFT 17 | |
6128d1bb | 533 | #define TCPHO_MAX 0x7ffU |
ac718b69 | 534 | }; |
535 | ||
dff4e8ad | 536 | struct r8152; |
537 | ||
ebc2ec48 | 538 | struct rx_agg { |
539 | struct list_head list; | |
540 | struct urb *urb; | |
dff4e8ad | 541 | struct r8152 *context; |
ebc2ec48 | 542 | void *buffer; |
543 | void *head; | |
544 | }; | |
545 | ||
546 | struct tx_agg { | |
547 | struct list_head list; | |
548 | struct urb *urb; | |
dff4e8ad | 549 | struct r8152 *context; |
ebc2ec48 | 550 | void *buffer; |
551 | void *head; | |
552 | u32 skb_num; | |
553 | u32 skb_len; | |
554 | }; | |
555 | ||
ac718b69 | 556 | struct r8152 { |
557 | unsigned long flags; | |
558 | struct usb_device *udev; | |
559 | struct tasklet_struct tl; | |
40a82917 | 560 | struct usb_interface *intf; |
ac718b69 | 561 | struct net_device *netdev; |
40a82917 | 562 | struct urb *intr_urb; |
ebc2ec48 | 563 | struct tx_agg tx_info[RTL8152_MAX_TX]; |
564 | struct rx_agg rx_info[RTL8152_MAX_RX]; | |
565 | struct list_head rx_done, tx_free; | |
566 | struct sk_buff_head tx_queue; | |
567 | spinlock_t rx_lock, tx_lock; | |
ac718b69 | 568 | struct delayed_work schedule; |
569 | struct mii_if_info mii; | |
c81229c9 | 570 | |
571 | struct rtl_ops { | |
572 | void (*init)(struct r8152 *); | |
573 | int (*enable)(struct r8152 *); | |
574 | void (*disable)(struct r8152 *); | |
7e9da481 | 575 | void (*up)(struct r8152 *); |
c81229c9 | 576 | void (*down)(struct r8152 *); |
577 | void (*unload)(struct r8152 *); | |
578 | } rtl_ops; | |
579 | ||
40a82917 | 580 | int intr_interval; |
21ff2e89 | 581 | u32 saved_wolopts; |
ac718b69 | 582 | u32 msg_enable; |
dd1b119c | 583 | u32 tx_qlen; |
ac718b69 | 584 | u16 ocp_base; |
40a82917 | 585 | u8 *intr_buff; |
ac718b69 | 586 | u8 version; |
587 | u8 speed; | |
588 | }; | |
589 | ||
590 | enum rtl_version { | |
591 | RTL_VER_UNKNOWN = 0, | |
592 | RTL_VER_01, | |
43779f8d | 593 | RTL_VER_02, |
594 | RTL_VER_03, | |
595 | RTL_VER_04, | |
596 | RTL_VER_05, | |
597 | RTL_VER_MAX | |
ac718b69 | 598 | }; |
599 | ||
60c89071 | 600 | enum tx_csum_stat { |
601 | TX_CSUM_SUCCESS = 0, | |
602 | TX_CSUM_TSO, | |
603 | TX_CSUM_NONE | |
604 | }; | |
605 | ||
ac718b69 | 606 | /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). |
607 | * The RTL chips use a 64 element hash table based on the Ethernet CRC. | |
608 | */ | |
609 | static const int multicast_filter_limit = 32; | |
52aec126 | 610 | static unsigned int agg_buf_sz = 16384; |
ac718b69 | 611 | |
52aec126 | 612 | #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \ |
60c89071 | 613 | VLAN_ETH_HLEN - VLAN_HLEN) |
614 | ||
ac718b69 | 615 | static |
616 | int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) | |
617 | { | |
31787f53 | 618 | int ret; |
619 | void *tmp; | |
620 | ||
621 | tmp = kmalloc(size, GFP_KERNEL); | |
622 | if (!tmp) | |
623 | return -ENOMEM; | |
624 | ||
625 | ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0), | |
b209af99 | 626 | RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, |
627 | value, index, tmp, size, 500); | |
31787f53 | 628 | |
629 | memcpy(data, tmp, size); | |
630 | kfree(tmp); | |
631 | ||
632 | return ret; | |
ac718b69 | 633 | } |
634 | ||
635 | static | |
636 | int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) | |
637 | { | |
31787f53 | 638 | int ret; |
639 | void *tmp; | |
640 | ||
c4438f03 | 641 | tmp = kmemdup(data, size, GFP_KERNEL); |
31787f53 | 642 | if (!tmp) |
643 | return -ENOMEM; | |
644 | ||
31787f53 | 645 | ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0), |
b209af99 | 646 | RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE, |
647 | value, index, tmp, size, 500); | |
31787f53 | 648 | |
649 | kfree(tmp); | |
db8515ef | 650 | |
31787f53 | 651 | return ret; |
ac718b69 | 652 | } |
653 | ||
654 | static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size, | |
b209af99 | 655 | void *data, u16 type) |
ac718b69 | 656 | { |
45f4a19f | 657 | u16 limit = 64; |
658 | int ret = 0; | |
ac718b69 | 659 | |
660 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
661 | return -ENODEV; | |
662 | ||
663 | /* both size and indix must be 4 bytes align */ | |
664 | if ((size & 3) || !size || (index & 3) || !data) | |
665 | return -EPERM; | |
666 | ||
667 | if ((u32)index + (u32)size > 0xffff) | |
668 | return -EPERM; | |
669 | ||
670 | while (size) { | |
671 | if (size > limit) { | |
672 | ret = get_registers(tp, index, type, limit, data); | |
673 | if (ret < 0) | |
674 | break; | |
675 | ||
676 | index += limit; | |
677 | data += limit; | |
678 | size -= limit; | |
679 | } else { | |
680 | ret = get_registers(tp, index, type, size, data); | |
681 | if (ret < 0) | |
682 | break; | |
683 | ||
684 | index += size; | |
685 | data += size; | |
686 | size = 0; | |
687 | break; | |
688 | } | |
689 | } | |
690 | ||
691 | return ret; | |
692 | } | |
693 | ||
694 | static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, | |
b209af99 | 695 | u16 size, void *data, u16 type) |
ac718b69 | 696 | { |
45f4a19f | 697 | int ret; |
698 | u16 byteen_start, byteen_end, byen; | |
699 | u16 limit = 512; | |
ac718b69 | 700 | |
701 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
702 | return -ENODEV; | |
703 | ||
704 | /* both size and indix must be 4 bytes align */ | |
705 | if ((size & 3) || !size || (index & 3) || !data) | |
706 | return -EPERM; | |
707 | ||
708 | if ((u32)index + (u32)size > 0xffff) | |
709 | return -EPERM; | |
710 | ||
711 | byteen_start = byteen & BYTE_EN_START_MASK; | |
712 | byteen_end = byteen & BYTE_EN_END_MASK; | |
713 | ||
714 | byen = byteen_start | (byteen_start << 4); | |
715 | ret = set_registers(tp, index, type | byen, 4, data); | |
716 | if (ret < 0) | |
717 | goto error1; | |
718 | ||
719 | index += 4; | |
720 | data += 4; | |
721 | size -= 4; | |
722 | ||
723 | if (size) { | |
724 | size -= 4; | |
725 | ||
726 | while (size) { | |
727 | if (size > limit) { | |
728 | ret = set_registers(tp, index, | |
b209af99 | 729 | type | BYTE_EN_DWORD, |
730 | limit, data); | |
ac718b69 | 731 | if (ret < 0) |
732 | goto error1; | |
733 | ||
734 | index += limit; | |
735 | data += limit; | |
736 | size -= limit; | |
737 | } else { | |
738 | ret = set_registers(tp, index, | |
b209af99 | 739 | type | BYTE_EN_DWORD, |
740 | size, data); | |
ac718b69 | 741 | if (ret < 0) |
742 | goto error1; | |
743 | ||
744 | index += size; | |
745 | data += size; | |
746 | size = 0; | |
747 | break; | |
748 | } | |
749 | } | |
750 | ||
751 | byen = byteen_end | (byteen_end >> 4); | |
752 | ret = set_registers(tp, index, type | byen, 4, data); | |
753 | if (ret < 0) | |
754 | goto error1; | |
755 | } | |
756 | ||
757 | error1: | |
758 | return ret; | |
759 | } | |
760 | ||
761 | static inline | |
762 | int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) | |
763 | { | |
764 | return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA); | |
765 | } | |
766 | ||
767 | static inline | |
768 | int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) | |
769 | { | |
770 | return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA); | |
771 | } | |
772 | ||
773 | static inline | |
774 | int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) | |
775 | { | |
776 | return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB); | |
777 | } | |
778 | ||
779 | static inline | |
780 | int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) | |
781 | { | |
782 | return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB); | |
783 | } | |
784 | ||
785 | static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index) | |
786 | { | |
c8826de8 | 787 | __le32 data; |
ac718b69 | 788 | |
c8826de8 | 789 | generic_ocp_read(tp, index, sizeof(data), &data, type); |
ac718b69 | 790 | |
791 | return __le32_to_cpu(data); | |
792 | } | |
793 | ||
794 | static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data) | |
795 | { | |
c8826de8 | 796 | __le32 tmp = __cpu_to_le32(data); |
797 | ||
798 | generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type); | |
ac718b69 | 799 | } |
800 | ||
801 | static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index) | |
802 | { | |
803 | u32 data; | |
c8826de8 | 804 | __le32 tmp; |
ac718b69 | 805 | u8 shift = index & 2; |
806 | ||
807 | index &= ~3; | |
808 | ||
c8826de8 | 809 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 810 | |
c8826de8 | 811 | data = __le32_to_cpu(tmp); |
ac718b69 | 812 | data >>= (shift * 8); |
813 | data &= 0xffff; | |
814 | ||
815 | return (u16)data; | |
816 | } | |
817 | ||
818 | static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data) | |
819 | { | |
c8826de8 | 820 | u32 mask = 0xffff; |
821 | __le32 tmp; | |
ac718b69 | 822 | u16 byen = BYTE_EN_WORD; |
823 | u8 shift = index & 2; | |
824 | ||
825 | data &= mask; | |
826 | ||
827 | if (index & 2) { | |
828 | byen <<= shift; | |
829 | mask <<= (shift * 8); | |
830 | data <<= (shift * 8); | |
831 | index &= ~3; | |
832 | } | |
833 | ||
c8826de8 | 834 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 835 | |
c8826de8 | 836 | data |= __le32_to_cpu(tmp) & ~mask; |
837 | tmp = __cpu_to_le32(data); | |
ac718b69 | 838 | |
c8826de8 | 839 | generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); |
ac718b69 | 840 | } |
841 | ||
842 | static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index) | |
843 | { | |
844 | u32 data; | |
c8826de8 | 845 | __le32 tmp; |
ac718b69 | 846 | u8 shift = index & 3; |
847 | ||
848 | index &= ~3; | |
849 | ||
c8826de8 | 850 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 851 | |
c8826de8 | 852 | data = __le32_to_cpu(tmp); |
ac718b69 | 853 | data >>= (shift * 8); |
854 | data &= 0xff; | |
855 | ||
856 | return (u8)data; | |
857 | } | |
858 | ||
859 | static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data) | |
860 | { | |
c8826de8 | 861 | u32 mask = 0xff; |
862 | __le32 tmp; | |
ac718b69 | 863 | u16 byen = BYTE_EN_BYTE; |
864 | u8 shift = index & 3; | |
865 | ||
866 | data &= mask; | |
867 | ||
868 | if (index & 3) { | |
869 | byen <<= shift; | |
870 | mask <<= (shift * 8); | |
871 | data <<= (shift * 8); | |
872 | index &= ~3; | |
873 | } | |
874 | ||
c8826de8 | 875 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 876 | |
c8826de8 | 877 | data |= __le32_to_cpu(tmp) & ~mask; |
878 | tmp = __cpu_to_le32(data); | |
ac718b69 | 879 | |
c8826de8 | 880 | generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); |
ac718b69 | 881 | } |
882 | ||
ac244d3e | 883 | static u16 ocp_reg_read(struct r8152 *tp, u16 addr) |
e3fe0b1a | 884 | { |
885 | u16 ocp_base, ocp_index; | |
886 | ||
887 | ocp_base = addr & 0xf000; | |
888 | if (ocp_base != tp->ocp_base) { | |
889 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); | |
890 | tp->ocp_base = ocp_base; | |
891 | } | |
892 | ||
893 | ocp_index = (addr & 0x0fff) | 0xb000; | |
ac244d3e | 894 | return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index); |
e3fe0b1a | 895 | } |
896 | ||
ac244d3e | 897 | static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) |
ac718b69 | 898 | { |
ac244d3e | 899 | u16 ocp_base, ocp_index; |
ac718b69 | 900 | |
ac244d3e | 901 | ocp_base = addr & 0xf000; |
902 | if (ocp_base != tp->ocp_base) { | |
903 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); | |
904 | tp->ocp_base = ocp_base; | |
ac718b69 | 905 | } |
ac244d3e | 906 | |
907 | ocp_index = (addr & 0x0fff) | 0xb000; | |
908 | ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data); | |
ac718b69 | 909 | } |
910 | ||
ac244d3e | 911 | static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value) |
ac718b69 | 912 | { |
ac244d3e | 913 | ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value); |
914 | } | |
ac718b69 | 915 | |
ac244d3e | 916 | static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr) |
917 | { | |
918 | return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2); | |
ac718b69 | 919 | } |
920 | ||
43779f8d | 921 | static void sram_write(struct r8152 *tp, u16 addr, u16 data) |
922 | { | |
923 | ocp_reg_write(tp, OCP_SRAM_ADDR, addr); | |
924 | ocp_reg_write(tp, OCP_SRAM_DATA, data); | |
925 | } | |
926 | ||
927 | static u16 sram_read(struct r8152 *tp, u16 addr) | |
928 | { | |
929 | ocp_reg_write(tp, OCP_SRAM_ADDR, addr); | |
930 | return ocp_reg_read(tp, OCP_SRAM_DATA); | |
931 | } | |
932 | ||
ac718b69 | 933 | static int read_mii_word(struct net_device *netdev, int phy_id, int reg) |
934 | { | |
935 | struct r8152 *tp = netdev_priv(netdev); | |
9a4be1bd | 936 | int ret; |
ac718b69 | 937 | |
6871438c | 938 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
939 | return -ENODEV; | |
940 | ||
ac718b69 | 941 | if (phy_id != R8152_PHY_ID) |
942 | return -EINVAL; | |
943 | ||
9a4be1bd | 944 | ret = usb_autopm_get_interface(tp->intf); |
945 | if (ret < 0) | |
946 | goto out; | |
947 | ||
948 | ret = r8152_mdio_read(tp, reg); | |
949 | ||
950 | usb_autopm_put_interface(tp->intf); | |
951 | ||
952 | out: | |
953 | return ret; | |
ac718b69 | 954 | } |
955 | ||
956 | static | |
957 | void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val) | |
958 | { | |
959 | struct r8152 *tp = netdev_priv(netdev); | |
960 | ||
6871438c | 961 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
962 | return; | |
963 | ||
ac718b69 | 964 | if (phy_id != R8152_PHY_ID) |
965 | return; | |
966 | ||
9a4be1bd | 967 | if (usb_autopm_get_interface(tp->intf) < 0) |
968 | return; | |
969 | ||
ac718b69 | 970 | r8152_mdio_write(tp, reg, val); |
9a4be1bd | 971 | |
972 | usb_autopm_put_interface(tp->intf); | |
ac718b69 | 973 | } |
974 | ||
b209af99 | 975 | static int |
976 | r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags); | |
ebc2ec48 | 977 | |
8ba789ab | 978 | static int rtl8152_set_mac_address(struct net_device *netdev, void *p) |
979 | { | |
980 | struct r8152 *tp = netdev_priv(netdev); | |
981 | struct sockaddr *addr = p; | |
982 | ||
983 | if (!is_valid_ether_addr(addr->sa_data)) | |
984 | return -EADDRNOTAVAIL; | |
985 | ||
986 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
987 | ||
988 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
989 | pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data); | |
990 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
991 | ||
992 | return 0; | |
993 | } | |
994 | ||
179bb6d7 | 995 | static int set_ethernet_addr(struct r8152 *tp) |
ac718b69 | 996 | { |
997 | struct net_device *dev = tp->netdev; | |
179bb6d7 | 998 | struct sockaddr sa; |
8a91c824 | 999 | int ret; |
ac718b69 | 1000 | |
8a91c824 | 1001 | if (tp->version == RTL_VER_01) |
179bb6d7 | 1002 | ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data); |
8a91c824 | 1003 | else |
179bb6d7 | 1004 | ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data); |
8a91c824 | 1005 | |
1006 | if (ret < 0) { | |
179bb6d7 | 1007 | netif_err(tp, probe, dev, "Get ether addr fail\n"); |
1008 | } else if (!is_valid_ether_addr(sa.sa_data)) { | |
1009 | netif_err(tp, probe, dev, "Invalid ether addr %pM\n", | |
1010 | sa.sa_data); | |
1011 | eth_hw_addr_random(dev); | |
1012 | ether_addr_copy(sa.sa_data, dev->dev_addr); | |
1013 | ret = rtl8152_set_mac_address(dev, &sa); | |
1014 | netif_info(tp, probe, dev, "Random ether addr %pM\n", | |
1015 | sa.sa_data); | |
8a91c824 | 1016 | } else { |
179bb6d7 | 1017 | if (tp->version == RTL_VER_01) |
1018 | ether_addr_copy(dev->dev_addr, sa.sa_data); | |
1019 | else | |
1020 | ret = rtl8152_set_mac_address(dev, &sa); | |
ac718b69 | 1021 | } |
179bb6d7 | 1022 | |
1023 | return ret; | |
ac718b69 | 1024 | } |
1025 | ||
ac718b69 | 1026 | static void read_bulk_callback(struct urb *urb) |
1027 | { | |
ac718b69 | 1028 | struct net_device *netdev; |
ac718b69 | 1029 | int status = urb->status; |
ebc2ec48 | 1030 | struct rx_agg *agg; |
1031 | struct r8152 *tp; | |
ac718b69 | 1032 | int result; |
ac718b69 | 1033 | |
ebc2ec48 | 1034 | agg = urb->context; |
1035 | if (!agg) | |
1036 | return; | |
1037 | ||
1038 | tp = agg->context; | |
ac718b69 | 1039 | if (!tp) |
1040 | return; | |
ebc2ec48 | 1041 | |
ac718b69 | 1042 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
1043 | return; | |
ebc2ec48 | 1044 | |
1045 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
1046 | return; | |
1047 | ||
ac718b69 | 1048 | netdev = tp->netdev; |
7559fb2f | 1049 | |
1050 | /* When link down, the driver would cancel all bulks. */ | |
1051 | /* This avoid the re-submitting bulk */ | |
ebc2ec48 | 1052 | if (!netif_carrier_ok(netdev)) |
ac718b69 | 1053 | return; |
1054 | ||
9a4be1bd | 1055 | usb_mark_last_busy(tp->udev); |
1056 | ||
ac718b69 | 1057 | switch (status) { |
1058 | case 0: | |
ebc2ec48 | 1059 | if (urb->actual_length < ETH_ZLEN) |
1060 | break; | |
1061 | ||
2685d410 | 1062 | spin_lock(&tp->rx_lock); |
ebc2ec48 | 1063 | list_add_tail(&agg->list, &tp->rx_done); |
2685d410 | 1064 | spin_unlock(&tp->rx_lock); |
ebc2ec48 | 1065 | tasklet_schedule(&tp->tl); |
1066 | return; | |
ac718b69 | 1067 | case -ESHUTDOWN: |
1068 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
1069 | netif_device_detach(tp->netdev); | |
ebc2ec48 | 1070 | return; |
ac718b69 | 1071 | case -ENOENT: |
1072 | return; /* the urb is in unlink state */ | |
1073 | case -ETIME: | |
4a8deae2 HW |
1074 | if (net_ratelimit()) |
1075 | netdev_warn(netdev, "maybe reset is needed?\n"); | |
ebc2ec48 | 1076 | break; |
ac718b69 | 1077 | default: |
4a8deae2 HW |
1078 | if (net_ratelimit()) |
1079 | netdev_warn(netdev, "Rx status %d\n", status); | |
ebc2ec48 | 1080 | break; |
ac718b69 | 1081 | } |
1082 | ||
ebc2ec48 | 1083 | result = r8152_submit_rx(tp, agg, GFP_ATOMIC); |
ac718b69 | 1084 | if (result == -ENODEV) { |
1085 | netif_device_detach(tp->netdev); | |
1086 | } else if (result) { | |
2685d410 | 1087 | spin_lock(&tp->rx_lock); |
ebc2ec48 | 1088 | list_add_tail(&agg->list, &tp->rx_done); |
2685d410 | 1089 | spin_unlock(&tp->rx_lock); |
ebc2ec48 | 1090 | tasklet_schedule(&tp->tl); |
ac718b69 | 1091 | } |
ac718b69 | 1092 | } |
1093 | ||
ebc2ec48 | 1094 | static void write_bulk_callback(struct urb *urb) |
ac718b69 | 1095 | { |
ebc2ec48 | 1096 | struct net_device_stats *stats; |
d104eafa | 1097 | struct net_device *netdev; |
ebc2ec48 | 1098 | struct tx_agg *agg; |
ac718b69 | 1099 | struct r8152 *tp; |
ebc2ec48 | 1100 | int status = urb->status; |
ac718b69 | 1101 | |
ebc2ec48 | 1102 | agg = urb->context; |
1103 | if (!agg) | |
ac718b69 | 1104 | return; |
1105 | ||
ebc2ec48 | 1106 | tp = agg->context; |
1107 | if (!tp) | |
1108 | return; | |
1109 | ||
d104eafa | 1110 | netdev = tp->netdev; |
05e0f1aa | 1111 | stats = &netdev->stats; |
ebc2ec48 | 1112 | if (status) { |
4a8deae2 | 1113 | if (net_ratelimit()) |
d104eafa | 1114 | netdev_warn(netdev, "Tx status %d\n", status); |
ebc2ec48 | 1115 | stats->tx_errors += agg->skb_num; |
ac718b69 | 1116 | } else { |
ebc2ec48 | 1117 | stats->tx_packets += agg->skb_num; |
1118 | stats->tx_bytes += agg->skb_len; | |
ac718b69 | 1119 | } |
1120 | ||
2685d410 | 1121 | spin_lock(&tp->tx_lock); |
ebc2ec48 | 1122 | list_add_tail(&agg->list, &tp->tx_free); |
2685d410 | 1123 | spin_unlock(&tp->tx_lock); |
ebc2ec48 | 1124 | |
9a4be1bd | 1125 | usb_autopm_put_interface_async(tp->intf); |
1126 | ||
d104eafa | 1127 | if (!netif_carrier_ok(netdev)) |
ebc2ec48 | 1128 | return; |
1129 | ||
1130 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
1131 | return; | |
1132 | ||
1133 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
1134 | return; | |
1135 | ||
1136 | if (!skb_queue_empty(&tp->tx_queue)) | |
0c3121fc | 1137 | tasklet_schedule(&tp->tl); |
ac718b69 | 1138 | } |
1139 | ||
40a82917 | 1140 | static void intr_callback(struct urb *urb) |
1141 | { | |
1142 | struct r8152 *tp; | |
500b6d7e | 1143 | __le16 *d; |
40a82917 | 1144 | int status = urb->status; |
1145 | int res; | |
1146 | ||
1147 | tp = urb->context; | |
1148 | if (!tp) | |
1149 | return; | |
1150 | ||
1151 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
1152 | return; | |
1153 | ||
1154 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
1155 | return; | |
1156 | ||
1157 | switch (status) { | |
1158 | case 0: /* success */ | |
1159 | break; | |
1160 | case -ECONNRESET: /* unlink */ | |
1161 | case -ESHUTDOWN: | |
1162 | netif_device_detach(tp->netdev); | |
1163 | case -ENOENT: | |
1164 | return; | |
1165 | case -EOVERFLOW: | |
1166 | netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n"); | |
1167 | goto resubmit; | |
1168 | /* -EPIPE: should clear the halt */ | |
1169 | default: | |
1170 | netif_info(tp, intr, tp->netdev, "intr status %d\n", status); | |
1171 | goto resubmit; | |
1172 | } | |
1173 | ||
1174 | d = urb->transfer_buffer; | |
1175 | if (INTR_LINK & __le16_to_cpu(d[0])) { | |
1176 | if (!(tp->speed & LINK_STATUS)) { | |
1177 | set_bit(RTL8152_LINK_CHG, &tp->flags); | |
1178 | schedule_delayed_work(&tp->schedule, 0); | |
1179 | } | |
1180 | } else { | |
1181 | if (tp->speed & LINK_STATUS) { | |
1182 | set_bit(RTL8152_LINK_CHG, &tp->flags); | |
1183 | schedule_delayed_work(&tp->schedule, 0); | |
1184 | } | |
1185 | } | |
1186 | ||
1187 | resubmit: | |
1188 | res = usb_submit_urb(urb, GFP_ATOMIC); | |
1189 | if (res == -ENODEV) | |
1190 | netif_device_detach(tp->netdev); | |
1191 | else if (res) | |
1192 | netif_err(tp, intr, tp->netdev, | |
4a8deae2 | 1193 | "can't resubmit intr, status %d\n", res); |
40a82917 | 1194 | } |
1195 | ||
ebc2ec48 | 1196 | static inline void *rx_agg_align(void *data) |
1197 | { | |
8e1f51bd | 1198 | return (void *)ALIGN((uintptr_t)data, RX_ALIGN); |
ebc2ec48 | 1199 | } |
1200 | ||
1201 | static inline void *tx_agg_align(void *data) | |
1202 | { | |
8e1f51bd | 1203 | return (void *)ALIGN((uintptr_t)data, TX_ALIGN); |
ebc2ec48 | 1204 | } |
1205 | ||
1206 | static void free_all_mem(struct r8152 *tp) | |
1207 | { | |
1208 | int i; | |
1209 | ||
1210 | for (i = 0; i < RTL8152_MAX_RX; i++) { | |
9629e3c0 | 1211 | usb_free_urb(tp->rx_info[i].urb); |
1212 | tp->rx_info[i].urb = NULL; | |
ebc2ec48 | 1213 | |
9629e3c0 | 1214 | kfree(tp->rx_info[i].buffer); |
1215 | tp->rx_info[i].buffer = NULL; | |
1216 | tp->rx_info[i].head = NULL; | |
ebc2ec48 | 1217 | } |
1218 | ||
1219 | for (i = 0; i < RTL8152_MAX_TX; i++) { | |
9629e3c0 | 1220 | usb_free_urb(tp->tx_info[i].urb); |
1221 | tp->tx_info[i].urb = NULL; | |
ebc2ec48 | 1222 | |
9629e3c0 | 1223 | kfree(tp->tx_info[i].buffer); |
1224 | tp->tx_info[i].buffer = NULL; | |
1225 | tp->tx_info[i].head = NULL; | |
ebc2ec48 | 1226 | } |
40a82917 | 1227 | |
9629e3c0 | 1228 | usb_free_urb(tp->intr_urb); |
1229 | tp->intr_urb = NULL; | |
40a82917 | 1230 | |
9629e3c0 | 1231 | kfree(tp->intr_buff); |
1232 | tp->intr_buff = NULL; | |
ebc2ec48 | 1233 | } |
1234 | ||
1235 | static int alloc_all_mem(struct r8152 *tp) | |
1236 | { | |
1237 | struct net_device *netdev = tp->netdev; | |
40a82917 | 1238 | struct usb_interface *intf = tp->intf; |
1239 | struct usb_host_interface *alt = intf->cur_altsetting; | |
1240 | struct usb_host_endpoint *ep_intr = alt->endpoint + 2; | |
ebc2ec48 | 1241 | struct urb *urb; |
1242 | int node, i; | |
1243 | u8 *buf; | |
1244 | ||
1245 | node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; | |
1246 | ||
1247 | spin_lock_init(&tp->rx_lock); | |
1248 | spin_lock_init(&tp->tx_lock); | |
1249 | INIT_LIST_HEAD(&tp->rx_done); | |
1250 | INIT_LIST_HEAD(&tp->tx_free); | |
1251 | skb_queue_head_init(&tp->tx_queue); | |
1252 | ||
1253 | for (i = 0; i < RTL8152_MAX_RX; i++) { | |
52aec126 | 1254 | buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); |
ebc2ec48 | 1255 | if (!buf) |
1256 | goto err1; | |
1257 | ||
1258 | if (buf != rx_agg_align(buf)) { | |
1259 | kfree(buf); | |
52aec126 | 1260 | buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL, |
8e1f51bd | 1261 | node); |
ebc2ec48 | 1262 | if (!buf) |
1263 | goto err1; | |
1264 | } | |
1265 | ||
1266 | urb = usb_alloc_urb(0, GFP_KERNEL); | |
1267 | if (!urb) { | |
1268 | kfree(buf); | |
1269 | goto err1; | |
1270 | } | |
1271 | ||
1272 | INIT_LIST_HEAD(&tp->rx_info[i].list); | |
1273 | tp->rx_info[i].context = tp; | |
1274 | tp->rx_info[i].urb = urb; | |
1275 | tp->rx_info[i].buffer = buf; | |
1276 | tp->rx_info[i].head = rx_agg_align(buf); | |
1277 | } | |
1278 | ||
1279 | for (i = 0; i < RTL8152_MAX_TX; i++) { | |
52aec126 | 1280 | buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); |
ebc2ec48 | 1281 | if (!buf) |
1282 | goto err1; | |
1283 | ||
1284 | if (buf != tx_agg_align(buf)) { | |
1285 | kfree(buf); | |
52aec126 | 1286 | buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL, |
8e1f51bd | 1287 | node); |
ebc2ec48 | 1288 | if (!buf) |
1289 | goto err1; | |
1290 | } | |
1291 | ||
1292 | urb = usb_alloc_urb(0, GFP_KERNEL); | |
1293 | if (!urb) { | |
1294 | kfree(buf); | |
1295 | goto err1; | |
1296 | } | |
1297 | ||
1298 | INIT_LIST_HEAD(&tp->tx_info[i].list); | |
1299 | tp->tx_info[i].context = tp; | |
1300 | tp->tx_info[i].urb = urb; | |
1301 | tp->tx_info[i].buffer = buf; | |
1302 | tp->tx_info[i].head = tx_agg_align(buf); | |
1303 | ||
1304 | list_add_tail(&tp->tx_info[i].list, &tp->tx_free); | |
1305 | } | |
1306 | ||
40a82917 | 1307 | tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL); |
1308 | if (!tp->intr_urb) | |
1309 | goto err1; | |
1310 | ||
1311 | tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL); | |
1312 | if (!tp->intr_buff) | |
1313 | goto err1; | |
1314 | ||
1315 | tp->intr_interval = (int)ep_intr->desc.bInterval; | |
1316 | usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3), | |
b209af99 | 1317 | tp->intr_buff, INTBUFSIZE, intr_callback, |
1318 | tp, tp->intr_interval); | |
40a82917 | 1319 | |
ebc2ec48 | 1320 | return 0; |
1321 | ||
1322 | err1: | |
1323 | free_all_mem(tp); | |
1324 | return -ENOMEM; | |
1325 | } | |
1326 | ||
0de98f6c | 1327 | static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp) |
1328 | { | |
1329 | struct tx_agg *agg = NULL; | |
1330 | unsigned long flags; | |
1331 | ||
21949ab7 | 1332 | if (list_empty(&tp->tx_free)) |
1333 | return NULL; | |
1334 | ||
0de98f6c | 1335 | spin_lock_irqsave(&tp->tx_lock, flags); |
1336 | if (!list_empty(&tp->tx_free)) { | |
1337 | struct list_head *cursor; | |
1338 | ||
1339 | cursor = tp->tx_free.next; | |
1340 | list_del_init(cursor); | |
1341 | agg = list_entry(cursor, struct tx_agg, list); | |
1342 | } | |
1343 | spin_unlock_irqrestore(&tp->tx_lock, flags); | |
1344 | ||
1345 | return agg; | |
1346 | } | |
1347 | ||
60c89071 | 1348 | static inline __be16 get_protocol(struct sk_buff *skb) |
5bd23881 | 1349 | { |
60c89071 | 1350 | __be16 protocol; |
5bd23881 | 1351 | |
60c89071 | 1352 | if (skb->protocol == htons(ETH_P_8021Q)) |
1353 | protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto; | |
1354 | else | |
1355 | protocol = skb->protocol; | |
5bd23881 | 1356 | |
60c89071 | 1357 | return protocol; |
1358 | } | |
5bd23881 | 1359 | |
b209af99 | 1360 | /* r8152_csum_workaround() |
6128d1bb | 1361 | * The hw limites the value the transport offset. When the offset is out of the |
1362 | * range, calculate the checksum by sw. | |
1363 | */ | |
1364 | static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb, | |
1365 | struct sk_buff_head *list) | |
1366 | { | |
1367 | if (skb_shinfo(skb)->gso_size) { | |
1368 | netdev_features_t features = tp->netdev->features; | |
1369 | struct sk_buff_head seg_list; | |
1370 | struct sk_buff *segs, *nskb; | |
1371 | ||
a91d45f1 | 1372 | features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6); |
6128d1bb | 1373 | segs = skb_gso_segment(skb, features); |
1374 | if (IS_ERR(segs) || !segs) | |
1375 | goto drop; | |
1376 | ||
1377 | __skb_queue_head_init(&seg_list); | |
1378 | ||
1379 | do { | |
1380 | nskb = segs; | |
1381 | segs = segs->next; | |
1382 | nskb->next = NULL; | |
1383 | __skb_queue_tail(&seg_list, nskb); | |
1384 | } while (segs); | |
1385 | ||
1386 | skb_queue_splice(&seg_list, list); | |
1387 | dev_kfree_skb(skb); | |
1388 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
1389 | if (skb_checksum_help(skb) < 0) | |
1390 | goto drop; | |
1391 | ||
1392 | __skb_queue_head(list, skb); | |
1393 | } else { | |
1394 | struct net_device_stats *stats; | |
1395 | ||
1396 | drop: | |
1397 | stats = &tp->netdev->stats; | |
1398 | stats->tx_dropped++; | |
1399 | dev_kfree_skb(skb); | |
1400 | } | |
1401 | } | |
1402 | ||
b209af99 | 1403 | /* msdn_giant_send_check() |
6128d1bb | 1404 | * According to the document of microsoft, the TCP Pseudo Header excludes the |
1405 | * packet length for IPv6 TCP large packets. | |
1406 | */ | |
1407 | static int msdn_giant_send_check(struct sk_buff *skb) | |
1408 | { | |
1409 | const struct ipv6hdr *ipv6h; | |
1410 | struct tcphdr *th; | |
fcb308d5 | 1411 | int ret; |
1412 | ||
1413 | ret = skb_cow_head(skb, 0); | |
1414 | if (ret) | |
1415 | return ret; | |
6128d1bb | 1416 | |
1417 | ipv6h = ipv6_hdr(skb); | |
1418 | th = tcp_hdr(skb); | |
1419 | ||
1420 | th->check = 0; | |
1421 | th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0); | |
1422 | ||
fcb308d5 | 1423 | return ret; |
6128d1bb | 1424 | } |
1425 | ||
60c89071 | 1426 | static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, |
1427 | struct sk_buff *skb, u32 len, u32 transport_offset) | |
1428 | { | |
1429 | u32 mss = skb_shinfo(skb)->gso_size; | |
1430 | u32 opts1, opts2 = 0; | |
1431 | int ret = TX_CSUM_SUCCESS; | |
1432 | ||
1433 | WARN_ON_ONCE(len > TX_LEN_MAX); | |
1434 | ||
1435 | opts1 = len | TX_FS | TX_LS; | |
1436 | ||
1437 | if (mss) { | |
6128d1bb | 1438 | if (transport_offset > GTTCPHO_MAX) { |
1439 | netif_warn(tp, tx_err, tp->netdev, | |
1440 | "Invalid transport offset 0x%x for TSO\n", | |
1441 | transport_offset); | |
1442 | ret = TX_CSUM_TSO; | |
1443 | goto unavailable; | |
1444 | } | |
1445 | ||
60c89071 | 1446 | switch (get_protocol(skb)) { |
1447 | case htons(ETH_P_IP): | |
1448 | opts1 |= GTSENDV4; | |
1449 | break; | |
1450 | ||
6128d1bb | 1451 | case htons(ETH_P_IPV6): |
fcb308d5 | 1452 | if (msdn_giant_send_check(skb)) { |
1453 | ret = TX_CSUM_TSO; | |
1454 | goto unavailable; | |
1455 | } | |
6128d1bb | 1456 | opts1 |= GTSENDV6; |
6128d1bb | 1457 | break; |
1458 | ||
60c89071 | 1459 | default: |
1460 | WARN_ON_ONCE(1); | |
1461 | break; | |
1462 | } | |
1463 | ||
1464 | opts1 |= transport_offset << GTTCPHO_SHIFT; | |
1465 | opts2 |= min(mss, MSS_MAX) << MSS_SHIFT; | |
1466 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
1467 | u8 ip_protocol; | |
5bd23881 | 1468 | |
6128d1bb | 1469 | if (transport_offset > TCPHO_MAX) { |
1470 | netif_warn(tp, tx_err, tp->netdev, | |
1471 | "Invalid transport offset 0x%x\n", | |
1472 | transport_offset); | |
1473 | ret = TX_CSUM_NONE; | |
1474 | goto unavailable; | |
1475 | } | |
1476 | ||
60c89071 | 1477 | switch (get_protocol(skb)) { |
5bd23881 | 1478 | case htons(ETH_P_IP): |
1479 | opts2 |= IPV4_CS; | |
1480 | ip_protocol = ip_hdr(skb)->protocol; | |
1481 | break; | |
1482 | ||
1483 | case htons(ETH_P_IPV6): | |
1484 | opts2 |= IPV6_CS; | |
1485 | ip_protocol = ipv6_hdr(skb)->nexthdr; | |
1486 | break; | |
1487 | ||
1488 | default: | |
1489 | ip_protocol = IPPROTO_RAW; | |
1490 | break; | |
1491 | } | |
1492 | ||
60c89071 | 1493 | if (ip_protocol == IPPROTO_TCP) |
5bd23881 | 1494 | opts2 |= TCP_CS; |
60c89071 | 1495 | else if (ip_protocol == IPPROTO_UDP) |
5bd23881 | 1496 | opts2 |= UDP_CS; |
60c89071 | 1497 | else |
5bd23881 | 1498 | WARN_ON_ONCE(1); |
5bd23881 | 1499 | |
60c89071 | 1500 | opts2 |= transport_offset << TCPHO_SHIFT; |
5bd23881 | 1501 | } |
60c89071 | 1502 | |
1503 | desc->opts2 = cpu_to_le32(opts2); | |
1504 | desc->opts1 = cpu_to_le32(opts1); | |
1505 | ||
6128d1bb | 1506 | unavailable: |
60c89071 | 1507 | return ret; |
5bd23881 | 1508 | } |
1509 | ||
b1379d9a | 1510 | static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg) |
1511 | { | |
d84130a1 | 1512 | struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; |
9a4be1bd | 1513 | int remain, ret; |
b1379d9a | 1514 | u8 *tx_data; |
1515 | ||
d84130a1 | 1516 | __skb_queue_head_init(&skb_head); |
0c3121fc | 1517 | spin_lock(&tx_queue->lock); |
d84130a1 | 1518 | skb_queue_splice_init(tx_queue, &skb_head); |
0c3121fc | 1519 | spin_unlock(&tx_queue->lock); |
d84130a1 | 1520 | |
b1379d9a | 1521 | tx_data = agg->head; |
b209af99 | 1522 | agg->skb_num = 0; |
1523 | agg->skb_len = 0; | |
52aec126 | 1524 | remain = agg_buf_sz; |
b1379d9a | 1525 | |
7937f9e5 | 1526 | while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) { |
b1379d9a | 1527 | struct tx_desc *tx_desc; |
1528 | struct sk_buff *skb; | |
1529 | unsigned int len; | |
60c89071 | 1530 | u32 offset; |
b1379d9a | 1531 | |
d84130a1 | 1532 | skb = __skb_dequeue(&skb_head); |
b1379d9a | 1533 | if (!skb) |
1534 | break; | |
1535 | ||
60c89071 | 1536 | len = skb->len + sizeof(*tx_desc); |
1537 | ||
1538 | if (len > remain) { | |
d84130a1 | 1539 | __skb_queue_head(&skb_head, skb); |
b1379d9a | 1540 | break; |
1541 | } | |
1542 | ||
7937f9e5 | 1543 | tx_data = tx_agg_align(tx_data); |
b1379d9a | 1544 | tx_desc = (struct tx_desc *)tx_data; |
60c89071 | 1545 | |
1546 | offset = (u32)skb_transport_offset(skb); | |
1547 | ||
6128d1bb | 1548 | if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) { |
1549 | r8152_csum_workaround(tp, skb, &skb_head); | |
1550 | continue; | |
1551 | } | |
60c89071 | 1552 | |
b1379d9a | 1553 | tx_data += sizeof(*tx_desc); |
1554 | ||
60c89071 | 1555 | len = skb->len; |
1556 | if (skb_copy_bits(skb, 0, tx_data, len) < 0) { | |
1557 | struct net_device_stats *stats = &tp->netdev->stats; | |
1558 | ||
1559 | stats->tx_dropped++; | |
1560 | dev_kfree_skb_any(skb); | |
1561 | tx_data -= sizeof(*tx_desc); | |
1562 | continue; | |
1563 | } | |
1564 | ||
1565 | tx_data += len; | |
b1379d9a | 1566 | agg->skb_len += len; |
60c89071 | 1567 | agg->skb_num++; |
1568 | ||
b1379d9a | 1569 | dev_kfree_skb_any(skb); |
1570 | ||
52aec126 | 1571 | remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head); |
b1379d9a | 1572 | } |
1573 | ||
d84130a1 | 1574 | if (!skb_queue_empty(&skb_head)) { |
0c3121fc | 1575 | spin_lock(&tx_queue->lock); |
d84130a1 | 1576 | skb_queue_splice(&skb_head, tx_queue); |
0c3121fc | 1577 | spin_unlock(&tx_queue->lock); |
d84130a1 | 1578 | } |
1579 | ||
0c3121fc | 1580 | netif_tx_lock(tp->netdev); |
dd1b119c | 1581 | |
1582 | if (netif_queue_stopped(tp->netdev) && | |
1583 | skb_queue_len(&tp->tx_queue) < tp->tx_qlen) | |
1584 | netif_wake_queue(tp->netdev); | |
1585 | ||
0c3121fc | 1586 | netif_tx_unlock(tp->netdev); |
9a4be1bd | 1587 | |
0c3121fc | 1588 | ret = usb_autopm_get_interface_async(tp->intf); |
9a4be1bd | 1589 | if (ret < 0) |
1590 | goto out_tx_fill; | |
dd1b119c | 1591 | |
b1379d9a | 1592 | usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2), |
1593 | agg->head, (int)(tx_data - (u8 *)agg->head), | |
1594 | (usb_complete_t)write_bulk_callback, agg); | |
1595 | ||
0c3121fc | 1596 | ret = usb_submit_urb(agg->urb, GFP_ATOMIC); |
9a4be1bd | 1597 | if (ret < 0) |
0c3121fc | 1598 | usb_autopm_put_interface_async(tp->intf); |
9a4be1bd | 1599 | |
1600 | out_tx_fill: | |
1601 | return ret; | |
b1379d9a | 1602 | } |
1603 | ||
565cab0a | 1604 | static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc) |
1605 | { | |
1606 | u8 checksum = CHECKSUM_NONE; | |
1607 | u32 opts2, opts3; | |
1608 | ||
1609 | if (tp->version == RTL_VER_01) | |
1610 | goto return_result; | |
1611 | ||
1612 | opts2 = le32_to_cpu(rx_desc->opts2); | |
1613 | opts3 = le32_to_cpu(rx_desc->opts3); | |
1614 | ||
1615 | if (opts2 & RD_IPV4_CS) { | |
1616 | if (opts3 & IPF) | |
1617 | checksum = CHECKSUM_NONE; | |
1618 | else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF)) | |
1619 | checksum = CHECKSUM_NONE; | |
1620 | else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF)) | |
1621 | checksum = CHECKSUM_NONE; | |
1622 | else | |
1623 | checksum = CHECKSUM_UNNECESSARY; | |
6128d1bb | 1624 | } else if (RD_IPV6_CS) { |
1625 | if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF)) | |
1626 | checksum = CHECKSUM_UNNECESSARY; | |
1627 | else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF)) | |
1628 | checksum = CHECKSUM_UNNECESSARY; | |
565cab0a | 1629 | } |
1630 | ||
1631 | return_result: | |
1632 | return checksum; | |
1633 | } | |
1634 | ||
ebc2ec48 | 1635 | static void rx_bottom(struct r8152 *tp) |
1636 | { | |
a5a4f468 | 1637 | unsigned long flags; |
d84130a1 | 1638 | struct list_head *cursor, *next, rx_queue; |
ebc2ec48 | 1639 | |
d84130a1 | 1640 | if (list_empty(&tp->rx_done)) |
1641 | return; | |
1642 | ||
1643 | INIT_LIST_HEAD(&rx_queue); | |
a5a4f468 | 1644 | spin_lock_irqsave(&tp->rx_lock, flags); |
d84130a1 | 1645 | list_splice_init(&tp->rx_done, &rx_queue); |
1646 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
1647 | ||
1648 | list_for_each_safe(cursor, next, &rx_queue) { | |
43a4478d | 1649 | struct rx_desc *rx_desc; |
1650 | struct rx_agg *agg; | |
43a4478d | 1651 | int len_used = 0; |
1652 | struct urb *urb; | |
1653 | u8 *rx_data; | |
1654 | int ret; | |
1655 | ||
ebc2ec48 | 1656 | list_del_init(cursor); |
ebc2ec48 | 1657 | |
1658 | agg = list_entry(cursor, struct rx_agg, list); | |
1659 | urb = agg->urb; | |
0de98f6c | 1660 | if (urb->actual_length < ETH_ZLEN) |
1661 | goto submit; | |
ebc2ec48 | 1662 | |
ebc2ec48 | 1663 | rx_desc = agg->head; |
1664 | rx_data = agg->head; | |
7937f9e5 | 1665 | len_used += sizeof(struct rx_desc); |
ebc2ec48 | 1666 | |
7937f9e5 | 1667 | while (urb->actual_length > len_used) { |
43a4478d | 1668 | struct net_device *netdev = tp->netdev; |
05e0f1aa | 1669 | struct net_device_stats *stats = &netdev->stats; |
7937f9e5 | 1670 | unsigned int pkt_len; |
43a4478d | 1671 | struct sk_buff *skb; |
1672 | ||
7937f9e5 | 1673 | pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; |
ebc2ec48 | 1674 | if (pkt_len < ETH_ZLEN) |
1675 | break; | |
1676 | ||
7937f9e5 | 1677 | len_used += pkt_len; |
1678 | if (urb->actual_length < len_used) | |
1679 | break; | |
1680 | ||
8e1f51bd | 1681 | pkt_len -= CRC_SIZE; |
ebc2ec48 | 1682 | rx_data += sizeof(struct rx_desc); |
1683 | ||
1684 | skb = netdev_alloc_skb_ip_align(netdev, pkt_len); | |
1685 | if (!skb) { | |
1686 | stats->rx_dropped++; | |
5e2f7485 | 1687 | goto find_next_rx; |
ebc2ec48 | 1688 | } |
565cab0a | 1689 | |
1690 | skb->ip_summed = r8152_rx_csum(tp, rx_desc); | |
ebc2ec48 | 1691 | memcpy(skb->data, rx_data, pkt_len); |
1692 | skb_put(skb, pkt_len); | |
1693 | skb->protocol = eth_type_trans(skb, netdev); | |
9d9aafa1 | 1694 | netif_receive_skb(skb); |
ebc2ec48 | 1695 | stats->rx_packets++; |
1696 | stats->rx_bytes += pkt_len; | |
1697 | ||
5e2f7485 | 1698 | find_next_rx: |
8e1f51bd | 1699 | rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE); |
ebc2ec48 | 1700 | rx_desc = (struct rx_desc *)rx_data; |
ebc2ec48 | 1701 | len_used = (int)(rx_data - (u8 *)agg->head); |
7937f9e5 | 1702 | len_used += sizeof(struct rx_desc); |
ebc2ec48 | 1703 | } |
1704 | ||
0de98f6c | 1705 | submit: |
ebc2ec48 | 1706 | ret = r8152_submit_rx(tp, agg, GFP_ATOMIC); |
ebc2ec48 | 1707 | if (ret && ret != -ENODEV) { |
d84130a1 | 1708 | spin_lock_irqsave(&tp->rx_lock, flags); |
1709 | list_add_tail(&agg->list, &tp->rx_done); | |
1710 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
ebc2ec48 | 1711 | tasklet_schedule(&tp->tl); |
1712 | } | |
1713 | } | |
ebc2ec48 | 1714 | } |
1715 | ||
1716 | static void tx_bottom(struct r8152 *tp) | |
1717 | { | |
ebc2ec48 | 1718 | int res; |
1719 | ||
b1379d9a | 1720 | do { |
1721 | struct tx_agg *agg; | |
ebc2ec48 | 1722 | |
b1379d9a | 1723 | if (skb_queue_empty(&tp->tx_queue)) |
ebc2ec48 | 1724 | break; |
1725 | ||
b1379d9a | 1726 | agg = r8152_get_tx_agg(tp); |
1727 | if (!agg) | |
ebc2ec48 | 1728 | break; |
ebc2ec48 | 1729 | |
b1379d9a | 1730 | res = r8152_tx_agg_fill(tp, agg); |
1731 | if (res) { | |
05e0f1aa | 1732 | struct net_device *netdev = tp->netdev; |
ebc2ec48 | 1733 | |
b1379d9a | 1734 | if (res == -ENODEV) { |
1735 | netif_device_detach(netdev); | |
1736 | } else { | |
05e0f1aa | 1737 | struct net_device_stats *stats = &netdev->stats; |
1738 | unsigned long flags; | |
1739 | ||
b1379d9a | 1740 | netif_warn(tp, tx_err, netdev, |
1741 | "failed tx_urb %d\n", res); | |
1742 | stats->tx_dropped += agg->skb_num; | |
db8515ef | 1743 | |
b1379d9a | 1744 | spin_lock_irqsave(&tp->tx_lock, flags); |
1745 | list_add_tail(&agg->list, &tp->tx_free); | |
1746 | spin_unlock_irqrestore(&tp->tx_lock, flags); | |
1747 | } | |
ebc2ec48 | 1748 | } |
b1379d9a | 1749 | } while (res == 0); |
ebc2ec48 | 1750 | } |
1751 | ||
1752 | static void bottom_half(unsigned long data) | |
ac718b69 | 1753 | { |
1754 | struct r8152 *tp; | |
ac718b69 | 1755 | |
ebc2ec48 | 1756 | tp = (struct r8152 *)data; |
1757 | ||
1758 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
1759 | return; | |
1760 | ||
1761 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
ac718b69 | 1762 | return; |
ebc2ec48 | 1763 | |
7559fb2f | 1764 | /* When link down, the driver would cancel all bulks. */ |
1765 | /* This avoid the re-submitting bulk */ | |
ebc2ec48 | 1766 | if (!netif_carrier_ok(tp->netdev)) |
ac718b69 | 1767 | return; |
ebc2ec48 | 1768 | |
1769 | rx_bottom(tp); | |
0c3121fc | 1770 | tx_bottom(tp); |
ebc2ec48 | 1771 | } |
1772 | ||
1773 | static | |
1774 | int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags) | |
1775 | { | |
1776 | usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1), | |
52aec126 | 1777 | agg->head, agg_buf_sz, |
b209af99 | 1778 | (usb_complete_t)read_bulk_callback, agg); |
ebc2ec48 | 1779 | |
1780 | return usb_submit_urb(agg->urb, mem_flags); | |
ac718b69 | 1781 | } |
1782 | ||
00a5e360 | 1783 | static void rtl_drop_queued_tx(struct r8152 *tp) |
1784 | { | |
1785 | struct net_device_stats *stats = &tp->netdev->stats; | |
d84130a1 | 1786 | struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; |
00a5e360 | 1787 | struct sk_buff *skb; |
1788 | ||
d84130a1 | 1789 | if (skb_queue_empty(tx_queue)) |
1790 | return; | |
1791 | ||
1792 | __skb_queue_head_init(&skb_head); | |
2685d410 | 1793 | spin_lock_bh(&tx_queue->lock); |
d84130a1 | 1794 | skb_queue_splice_init(tx_queue, &skb_head); |
2685d410 | 1795 | spin_unlock_bh(&tx_queue->lock); |
d84130a1 | 1796 | |
1797 | while ((skb = __skb_dequeue(&skb_head))) { | |
00a5e360 | 1798 | dev_kfree_skb(skb); |
1799 | stats->tx_dropped++; | |
1800 | } | |
1801 | } | |
1802 | ||
ac718b69 | 1803 | static void rtl8152_tx_timeout(struct net_device *netdev) |
1804 | { | |
1805 | struct r8152 *tp = netdev_priv(netdev); | |
ebc2ec48 | 1806 | int i; |
1807 | ||
4a8deae2 | 1808 | netif_warn(tp, tx_err, netdev, "Tx timeout\n"); |
ebc2ec48 | 1809 | for (i = 0; i < RTL8152_MAX_TX; i++) |
1810 | usb_unlink_urb(tp->tx_info[i].urb); | |
ac718b69 | 1811 | } |
1812 | ||
1813 | static void rtl8152_set_rx_mode(struct net_device *netdev) | |
1814 | { | |
1815 | struct r8152 *tp = netdev_priv(netdev); | |
1816 | ||
40a82917 | 1817 | if (tp->speed & LINK_STATUS) { |
ac718b69 | 1818 | set_bit(RTL8152_SET_RX_MODE, &tp->flags); |
40a82917 | 1819 | schedule_delayed_work(&tp->schedule, 0); |
1820 | } | |
ac718b69 | 1821 | } |
1822 | ||
1823 | static void _rtl8152_set_rx_mode(struct net_device *netdev) | |
1824 | { | |
1825 | struct r8152 *tp = netdev_priv(netdev); | |
31787f53 | 1826 | u32 mc_filter[2]; /* Multicast hash filter */ |
1827 | __le32 tmp[2]; | |
ac718b69 | 1828 | u32 ocp_data; |
1829 | ||
ac718b69 | 1830 | clear_bit(RTL8152_SET_RX_MODE, &tp->flags); |
1831 | netif_stop_queue(netdev); | |
1832 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
1833 | ocp_data &= ~RCR_ACPT_ALL; | |
1834 | ocp_data |= RCR_AB | RCR_APM; | |
1835 | ||
1836 | if (netdev->flags & IFF_PROMISC) { | |
1837 | /* Unconditionally log net taps. */ | |
1838 | netif_notice(tp, link, netdev, "Promiscuous mode enabled\n"); | |
1839 | ocp_data |= RCR_AM | RCR_AAP; | |
b209af99 | 1840 | mc_filter[1] = 0xffffffff; |
1841 | mc_filter[0] = 0xffffffff; | |
ac718b69 | 1842 | } else if ((netdev_mc_count(netdev) > multicast_filter_limit) || |
1843 | (netdev->flags & IFF_ALLMULTI)) { | |
1844 | /* Too many to filter perfectly -- accept all multicasts. */ | |
1845 | ocp_data |= RCR_AM; | |
b209af99 | 1846 | mc_filter[1] = 0xffffffff; |
1847 | mc_filter[0] = 0xffffffff; | |
ac718b69 | 1848 | } else { |
1849 | struct netdev_hw_addr *ha; | |
1850 | ||
b209af99 | 1851 | mc_filter[1] = 0; |
1852 | mc_filter[0] = 0; | |
ac718b69 | 1853 | netdev_for_each_mc_addr(ha, netdev) { |
1854 | int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; | |
b209af99 | 1855 | |
ac718b69 | 1856 | mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); |
1857 | ocp_data |= RCR_AM; | |
1858 | } | |
1859 | } | |
1860 | ||
31787f53 | 1861 | tmp[0] = __cpu_to_le32(swab32(mc_filter[1])); |
1862 | tmp[1] = __cpu_to_le32(swab32(mc_filter[0])); | |
ac718b69 | 1863 | |
31787f53 | 1864 | pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp); |
ac718b69 | 1865 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); |
1866 | netif_wake_queue(netdev); | |
ac718b69 | 1867 | } |
1868 | ||
1869 | static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb, | |
b209af99 | 1870 | struct net_device *netdev) |
ac718b69 | 1871 | { |
1872 | struct r8152 *tp = netdev_priv(netdev); | |
ac718b69 | 1873 | |
ebc2ec48 | 1874 | skb_tx_timestamp(skb); |
ac718b69 | 1875 | |
61598788 | 1876 | skb_queue_tail(&tp->tx_queue, skb); |
ebc2ec48 | 1877 | |
0c3121fc | 1878 | if (!list_empty(&tp->tx_free)) { |
1879 | if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { | |
1880 | set_bit(SCHEDULE_TASKLET, &tp->flags); | |
1881 | schedule_delayed_work(&tp->schedule, 0); | |
1882 | } else { | |
1883 | usb_mark_last_busy(tp->udev); | |
1884 | tasklet_schedule(&tp->tl); | |
1885 | } | |
b209af99 | 1886 | } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) { |
dd1b119c | 1887 | netif_stop_queue(netdev); |
b209af99 | 1888 | } |
dd1b119c | 1889 | |
ac718b69 | 1890 | return NETDEV_TX_OK; |
1891 | } | |
1892 | ||
1893 | static void r8152b_reset_packet_filter(struct r8152 *tp) | |
1894 | { | |
1895 | u32 ocp_data; | |
1896 | ||
1897 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); | |
1898 | ocp_data &= ~FMC_FCR_MCU_EN; | |
1899 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); | |
1900 | ocp_data |= FMC_FCR_MCU_EN; | |
1901 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); | |
1902 | } | |
1903 | ||
1904 | static void rtl8152_nic_reset(struct r8152 *tp) | |
1905 | { | |
1906 | int i; | |
1907 | ||
1908 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST); | |
1909 | ||
1910 | for (i = 0; i < 1000; i++) { | |
1911 | if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST)) | |
1912 | break; | |
b209af99 | 1913 | usleep_range(100, 400); |
ac718b69 | 1914 | } |
1915 | } | |
1916 | ||
dd1b119c | 1917 | static void set_tx_qlen(struct r8152 *tp) |
1918 | { | |
1919 | struct net_device *netdev = tp->netdev; | |
1920 | ||
52aec126 | 1921 | tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN + |
1922 | sizeof(struct tx_desc)); | |
dd1b119c | 1923 | } |
1924 | ||
ac718b69 | 1925 | static inline u8 rtl8152_get_speed(struct r8152 *tp) |
1926 | { | |
1927 | return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); | |
1928 | } | |
1929 | ||
507605a8 | 1930 | static void rtl_set_eee_plus(struct r8152 *tp) |
ac718b69 | 1931 | { |
ebc2ec48 | 1932 | u32 ocp_data; |
ac718b69 | 1933 | u8 speed; |
1934 | ||
1935 | speed = rtl8152_get_speed(tp); | |
ebc2ec48 | 1936 | if (speed & _10bps) { |
ac718b69 | 1937 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); |
ebc2ec48 | 1938 | ocp_data |= EEEP_CR_EEEP_TX; |
ac718b69 | 1939 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); |
1940 | } else { | |
1941 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); | |
ebc2ec48 | 1942 | ocp_data &= ~EEEP_CR_EEEP_TX; |
ac718b69 | 1943 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); |
1944 | } | |
507605a8 | 1945 | } |
1946 | ||
00a5e360 | 1947 | static void rxdy_gated_en(struct r8152 *tp, bool enable) |
1948 | { | |
1949 | u32 ocp_data; | |
1950 | ||
1951 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); | |
1952 | if (enable) | |
1953 | ocp_data |= RXDY_GATED_EN; | |
1954 | else | |
1955 | ocp_data &= ~RXDY_GATED_EN; | |
1956 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); | |
1957 | } | |
1958 | ||
507605a8 | 1959 | static int rtl_enable(struct r8152 *tp) |
1960 | { | |
1961 | u32 ocp_data; | |
1962 | int i, ret; | |
ac718b69 | 1963 | |
1964 | r8152b_reset_packet_filter(tp); | |
1965 | ||
1966 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); | |
1967 | ocp_data |= CR_RE | CR_TE; | |
1968 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); | |
1969 | ||
00a5e360 | 1970 | rxdy_gated_en(tp, false); |
ac718b69 | 1971 | |
ebc2ec48 | 1972 | INIT_LIST_HEAD(&tp->rx_done); |
1973 | ret = 0; | |
1974 | for (i = 0; i < RTL8152_MAX_RX; i++) { | |
1975 | INIT_LIST_HEAD(&tp->rx_info[i].list); | |
1976 | ret |= r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL); | |
1977 | } | |
ac718b69 | 1978 | |
ebc2ec48 | 1979 | return ret; |
ac718b69 | 1980 | } |
1981 | ||
507605a8 | 1982 | static int rtl8152_enable(struct r8152 *tp) |
1983 | { | |
6871438c | 1984 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
1985 | return -ENODEV; | |
1986 | ||
507605a8 | 1987 | set_tx_qlen(tp); |
1988 | rtl_set_eee_plus(tp); | |
1989 | ||
1990 | return rtl_enable(tp); | |
1991 | } | |
1992 | ||
43779f8d | 1993 | static void r8153_set_rx_agg(struct r8152 *tp) |
1994 | { | |
1995 | u8 speed; | |
1996 | ||
1997 | speed = rtl8152_get_speed(tp); | |
1998 | if (speed & _1000bps) { | |
1999 | if (tp->udev->speed == USB_SPEED_SUPER) { | |
2000 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, | |
2001 | RX_THR_SUPPER); | |
2002 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG, | |
2003 | EARLY_AGG_SUPPER); | |
2004 | } else { | |
2005 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, | |
2006 | RX_THR_HIGH); | |
2007 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG, | |
2008 | EARLY_AGG_HIGH); | |
2009 | } | |
2010 | } else { | |
2011 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_SLOW); | |
2012 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG, | |
2013 | EARLY_AGG_SLOW); | |
2014 | } | |
2015 | } | |
2016 | ||
2017 | static int rtl8153_enable(struct r8152 *tp) | |
2018 | { | |
6871438c | 2019 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
2020 | return -ENODEV; | |
2021 | ||
43779f8d | 2022 | set_tx_qlen(tp); |
2023 | rtl_set_eee_plus(tp); | |
2024 | r8153_set_rx_agg(tp); | |
2025 | ||
2026 | return rtl_enable(tp); | |
2027 | } | |
2028 | ||
ac718b69 | 2029 | static void rtl8152_disable(struct r8152 *tp) |
2030 | { | |
ebc2ec48 | 2031 | u32 ocp_data; |
2032 | int i; | |
ac718b69 | 2033 | |
6871438c | 2034 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) { |
2035 | rtl_drop_queued_tx(tp); | |
2036 | return; | |
2037 | } | |
2038 | ||
ac718b69 | 2039 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); |
2040 | ocp_data &= ~RCR_ACPT_ALL; | |
2041 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2042 | ||
00a5e360 | 2043 | rtl_drop_queued_tx(tp); |
ebc2ec48 | 2044 | |
2045 | for (i = 0; i < RTL8152_MAX_TX; i++) | |
2046 | usb_kill_urb(tp->tx_info[i].urb); | |
ac718b69 | 2047 | |
00a5e360 | 2048 | rxdy_gated_en(tp, true); |
ac718b69 | 2049 | |
2050 | for (i = 0; i < 1000; i++) { | |
2051 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2052 | if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY) | |
2053 | break; | |
2054 | mdelay(1); | |
2055 | } | |
2056 | ||
2057 | for (i = 0; i < 1000; i++) { | |
2058 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY) | |
2059 | break; | |
2060 | mdelay(1); | |
2061 | } | |
2062 | ||
ebc2ec48 | 2063 | for (i = 0; i < RTL8152_MAX_RX; i++) |
2064 | usb_kill_urb(tp->rx_info[i].urb); | |
ac718b69 | 2065 | |
2066 | rtl8152_nic_reset(tp); | |
2067 | } | |
2068 | ||
00a5e360 | 2069 | static void r8152_power_cut_en(struct r8152 *tp, bool enable) |
2070 | { | |
2071 | u32 ocp_data; | |
2072 | ||
2073 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); | |
2074 | if (enable) | |
2075 | ocp_data |= POWER_CUT; | |
2076 | else | |
2077 | ocp_data &= ~POWER_CUT; | |
2078 | ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); | |
2079 | ||
2080 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); | |
2081 | ocp_data &= ~RESUME_INDICATE; | |
2082 | ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); | |
00a5e360 | 2083 | } |
2084 | ||
21ff2e89 | 2085 | #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) |
2086 | ||
2087 | static u32 __rtl_get_wol(struct r8152 *tp) | |
2088 | { | |
2089 | u32 ocp_data; | |
2090 | u32 wolopts = 0; | |
2091 | ||
2092 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5); | |
2093 | if (!(ocp_data & LAN_WAKE_EN)) | |
2094 | return 0; | |
2095 | ||
2096 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); | |
2097 | if (ocp_data & LINK_ON_WAKE_EN) | |
2098 | wolopts |= WAKE_PHY; | |
2099 | ||
2100 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); | |
2101 | if (ocp_data & UWF_EN) | |
2102 | wolopts |= WAKE_UCAST; | |
2103 | if (ocp_data & BWF_EN) | |
2104 | wolopts |= WAKE_BCAST; | |
2105 | if (ocp_data & MWF_EN) | |
2106 | wolopts |= WAKE_MCAST; | |
2107 | ||
2108 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); | |
2109 | if (ocp_data & MAGIC_EN) | |
2110 | wolopts |= WAKE_MAGIC; | |
2111 | ||
2112 | return wolopts; | |
2113 | } | |
2114 | ||
2115 | static void __rtl_set_wol(struct r8152 *tp, u32 wolopts) | |
2116 | { | |
2117 | u32 ocp_data; | |
2118 | ||
2119 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
2120 | ||
2121 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); | |
2122 | ocp_data &= ~LINK_ON_WAKE_EN; | |
2123 | if (wolopts & WAKE_PHY) | |
2124 | ocp_data |= LINK_ON_WAKE_EN; | |
2125 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); | |
2126 | ||
2127 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); | |
2128 | ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN); | |
2129 | if (wolopts & WAKE_UCAST) | |
2130 | ocp_data |= UWF_EN; | |
2131 | if (wolopts & WAKE_BCAST) | |
2132 | ocp_data |= BWF_EN; | |
2133 | if (wolopts & WAKE_MCAST) | |
2134 | ocp_data |= MWF_EN; | |
2135 | if (wolopts & WAKE_ANY) | |
2136 | ocp_data |= LAN_WAKE_EN; | |
2137 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data); | |
2138 | ||
2139 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
2140 | ||
2141 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); | |
2142 | ocp_data &= ~MAGIC_EN; | |
2143 | if (wolopts & WAKE_MAGIC) | |
2144 | ocp_data |= MAGIC_EN; | |
2145 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data); | |
2146 | ||
2147 | if (wolopts & WAKE_ANY) | |
2148 | device_set_wakeup_enable(&tp->udev->dev, true); | |
2149 | else | |
2150 | device_set_wakeup_enable(&tp->udev->dev, false); | |
2151 | } | |
2152 | ||
9a4be1bd | 2153 | static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable) |
2154 | { | |
2155 | if (enable) { | |
2156 | u32 ocp_data; | |
2157 | ||
2158 | __rtl_set_wol(tp, WAKE_ANY); | |
2159 | ||
2160 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
2161 | ||
2162 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); | |
2163 | ocp_data |= LINK_OFF_WAKE_EN; | |
2164 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); | |
2165 | ||
2166 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
2167 | } else { | |
2168 | __rtl_set_wol(tp, tp->saved_wolopts); | |
2169 | } | |
2170 | } | |
2171 | ||
aa66a5f1 | 2172 | static void rtl_phy_reset(struct r8152 *tp) |
2173 | { | |
2174 | u16 data; | |
2175 | int i; | |
2176 | ||
2177 | clear_bit(PHY_RESET, &tp->flags); | |
2178 | ||
2179 | data = r8152_mdio_read(tp, MII_BMCR); | |
2180 | ||
2181 | /* don't reset again before the previous one complete */ | |
2182 | if (data & BMCR_RESET) | |
2183 | return; | |
2184 | ||
2185 | data |= BMCR_RESET; | |
2186 | r8152_mdio_write(tp, MII_BMCR, data); | |
2187 | ||
2188 | for (i = 0; i < 50; i++) { | |
2189 | msleep(20); | |
2190 | if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) | |
2191 | break; | |
2192 | } | |
2193 | } | |
2194 | ||
4349968a | 2195 | static void rtl_clear_bp(struct r8152 *tp) |
2196 | { | |
2197 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_0, 0); | |
2198 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_2, 0); | |
2199 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_4, 0); | |
2200 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_6, 0); | |
2201 | ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_0, 0); | |
2202 | ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_2, 0); | |
2203 | ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_4, 0); | |
2204 | ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_6, 0); | |
2205 | mdelay(3); | |
2206 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_BA, 0); | |
2207 | ocp_write_word(tp, MCU_TYPE_USB, USB_BP_BA, 0); | |
2208 | } | |
2209 | ||
2210 | static void r8153_clear_bp(struct r8152 *tp) | |
2211 | { | |
2212 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_BP_EN, 0); | |
2213 | ocp_write_byte(tp, MCU_TYPE_USB, USB_BP_EN, 0); | |
2214 | rtl_clear_bp(tp); | |
2215 | } | |
2216 | ||
2217 | static void r8153_teredo_off(struct r8152 *tp) | |
2218 | { | |
2219 | u32 ocp_data; | |
2220 | ||
2221 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); | |
2222 | ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN); | |
2223 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); | |
2224 | ||
2225 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE); | |
2226 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0); | |
2227 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0); | |
2228 | } | |
2229 | ||
2230 | static void r8152b_disable_aldps(struct r8152 *tp) | |
2231 | { | |
2232 | ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE); | |
2233 | msleep(20); | |
2234 | } | |
2235 | ||
2236 | static inline void r8152b_enable_aldps(struct r8152 *tp) | |
2237 | { | |
2238 | ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS | | |
2239 | LINKENA | DIS_SDSAVE); | |
2240 | } | |
2241 | ||
2242 | static void r8152b_hw_phy_cfg(struct r8152 *tp) | |
2243 | { | |
f0cbe0ac | 2244 | u16 data; |
2245 | ||
2246 | data = r8152_mdio_read(tp, MII_BMCR); | |
2247 | if (data & BMCR_PDOWN) { | |
2248 | data &= ~BMCR_PDOWN; | |
2249 | r8152_mdio_write(tp, MII_BMCR, data); | |
2250 | } | |
2251 | ||
4349968a | 2252 | r8152b_disable_aldps(tp); |
7e9da481 | 2253 | |
2254 | rtl_clear_bp(tp); | |
2255 | ||
2256 | r8152b_enable_aldps(tp); | |
aa66a5f1 | 2257 | set_bit(PHY_RESET, &tp->flags); |
4349968a | 2258 | } |
2259 | ||
ac718b69 | 2260 | static void r8152b_exit_oob(struct r8152 *tp) |
2261 | { | |
db8515ef | 2262 | u32 ocp_data; |
2263 | int i; | |
ac718b69 | 2264 | |
6871438c | 2265 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
2266 | return; | |
2267 | ||
ac718b69 | 2268 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); |
2269 | ocp_data &= ~RCR_ACPT_ALL; | |
2270 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2271 | ||
00a5e360 | 2272 | rxdy_gated_en(tp, true); |
da9bd117 | 2273 | r8153_teredo_off(tp); |
7e9da481 | 2274 | r8152b_hw_phy_cfg(tp); |
ac718b69 | 2275 | |
2276 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
2277 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); | |
2278 | ||
2279 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2280 | ocp_data &= ~NOW_IS_OOB; | |
2281 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2282 | ||
2283 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2284 | ocp_data &= ~MCU_BORW_EN; | |
2285 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2286 | ||
2287 | for (i = 0; i < 1000; i++) { | |
2288 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2289 | if (ocp_data & LINK_LIST_READY) | |
2290 | break; | |
2291 | mdelay(1); | |
2292 | } | |
2293 | ||
2294 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2295 | ocp_data |= RE_INIT_LL; | |
2296 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2297 | ||
2298 | for (i = 0; i < 1000; i++) { | |
2299 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2300 | if (ocp_data & LINK_LIST_READY) | |
2301 | break; | |
2302 | mdelay(1); | |
2303 | } | |
2304 | ||
2305 | rtl8152_nic_reset(tp); | |
2306 | ||
2307 | /* rx share fifo credit full threshold */ | |
2308 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); | |
2309 | ||
a3cc465d | 2310 | if (tp->udev->speed == USB_SPEED_FULL || |
2311 | tp->udev->speed == USB_SPEED_LOW) { | |
ac718b69 | 2312 | /* rx share fifo credit near full threshold */ |
2313 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, | |
2314 | RXFIFO_THR2_FULL); | |
2315 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, | |
2316 | RXFIFO_THR3_FULL); | |
2317 | } else { | |
2318 | /* rx share fifo credit near full threshold */ | |
2319 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, | |
2320 | RXFIFO_THR2_HIGH); | |
2321 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, | |
2322 | RXFIFO_THR3_HIGH); | |
2323 | } | |
2324 | ||
2325 | /* TX share fifo free credit full threshold */ | |
2326 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL); | |
2327 | ||
2328 | ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD); | |
8e1f51bd | 2329 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH); |
ac718b69 | 2330 | ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA, |
2331 | TEST_MODE_DISABLE | TX_SIZE_ADJUST1); | |
2332 | ||
2333 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); | |
2334 | ocp_data &= ~CPCR_RX_VLAN; | |
2335 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); | |
2336 | ||
2337 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); | |
2338 | ||
2339 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); | |
2340 | ocp_data |= TCR0_AUTO_FIFO; | |
2341 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); | |
2342 | } | |
2343 | ||
2344 | static void r8152b_enter_oob(struct r8152 *tp) | |
2345 | { | |
45f4a19f | 2346 | u32 ocp_data; |
2347 | int i; | |
ac718b69 | 2348 | |
2349 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2350 | ocp_data &= ~NOW_IS_OOB; | |
2351 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2352 | ||
2353 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); | |
2354 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); | |
2355 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB); | |
2356 | ||
2357 | rtl8152_disable(tp); | |
2358 | ||
2359 | for (i = 0; i < 1000; i++) { | |
2360 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2361 | if (ocp_data & LINK_LIST_READY) | |
2362 | break; | |
2363 | mdelay(1); | |
2364 | } | |
2365 | ||
2366 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2367 | ocp_data |= RE_INIT_LL; | |
2368 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2369 | ||
2370 | for (i = 0; i < 1000; i++) { | |
2371 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2372 | if (ocp_data & LINK_LIST_READY) | |
2373 | break; | |
2374 | mdelay(1); | |
2375 | } | |
2376 | ||
2377 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); | |
2378 | ||
ac718b69 | 2379 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); |
2380 | ocp_data |= CPCR_RX_VLAN; | |
2381 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); | |
2382 | ||
2383 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); | |
2384 | ocp_data |= ALDPS_PROXY_MODE; | |
2385 | ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); | |
2386 | ||
2387 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2388 | ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; | |
2389 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2390 | ||
00a5e360 | 2391 | rxdy_gated_en(tp, false); |
ac718b69 | 2392 | |
2393 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2394 | ocp_data |= RCR_APM | RCR_AM | RCR_AB; | |
2395 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2396 | } | |
2397 | ||
43779f8d | 2398 | static void r8153_hw_phy_cfg(struct r8152 *tp) |
2399 | { | |
2400 | u32 ocp_data; | |
2401 | u16 data; | |
2402 | ||
2403 | ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L); | |
f0cbe0ac | 2404 | data = r8152_mdio_read(tp, MII_BMCR); |
2405 | if (data & BMCR_PDOWN) { | |
2406 | data &= ~BMCR_PDOWN; | |
2407 | r8152_mdio_write(tp, MII_BMCR, data); | |
2408 | } | |
43779f8d | 2409 | |
7e9da481 | 2410 | r8153_clear_bp(tp); |
2411 | ||
43779f8d | 2412 | if (tp->version == RTL_VER_03) { |
2413 | data = ocp_reg_read(tp, OCP_EEE_CFG); | |
2414 | data &= ~CTAP_SHORT_EN; | |
2415 | ocp_reg_write(tp, OCP_EEE_CFG, data); | |
2416 | } | |
2417 | ||
2418 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
2419 | data |= EEE_CLKDIV_EN; | |
2420 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
2421 | ||
2422 | data = ocp_reg_read(tp, OCP_DOWN_SPEED); | |
2423 | data |= EN_10M_BGOFF; | |
2424 | ocp_reg_write(tp, OCP_DOWN_SPEED, data); | |
2425 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
2426 | data |= EN_10M_PLLOFF; | |
2427 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
2428 | data = sram_read(tp, SRAM_IMPEDANCE); | |
2429 | data &= ~RX_DRIVING_MASK; | |
2430 | sram_write(tp, SRAM_IMPEDANCE, data); | |
2431 | ||
2432 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); | |
2433 | ocp_data |= PFM_PWM_SWITCH; | |
2434 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); | |
2435 | ||
2436 | data = sram_read(tp, SRAM_LPF_CFG); | |
2437 | data |= LPF_AUTO_TUNE; | |
2438 | sram_write(tp, SRAM_LPF_CFG, data); | |
2439 | ||
2440 | data = sram_read(tp, SRAM_10M_AMP1); | |
2441 | data |= GDAC_IB_UPALL; | |
2442 | sram_write(tp, SRAM_10M_AMP1, data); | |
2443 | data = sram_read(tp, SRAM_10M_AMP2); | |
2444 | data |= AMP_DN; | |
2445 | sram_write(tp, SRAM_10M_AMP2, data); | |
aa66a5f1 | 2446 | |
2447 | set_bit(PHY_RESET, &tp->flags); | |
43779f8d | 2448 | } |
2449 | ||
b9702723 | 2450 | static void r8153_u1u2en(struct r8152 *tp, bool enable) |
43779f8d | 2451 | { |
2452 | u8 u1u2[8]; | |
2453 | ||
2454 | if (enable) | |
2455 | memset(u1u2, 0xff, sizeof(u1u2)); | |
2456 | else | |
2457 | memset(u1u2, 0x00, sizeof(u1u2)); | |
2458 | ||
2459 | usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2); | |
2460 | } | |
2461 | ||
b9702723 | 2462 | static void r8153_u2p3en(struct r8152 *tp, bool enable) |
43779f8d | 2463 | { |
2464 | u32 ocp_data; | |
2465 | ||
2466 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); | |
2467 | if (enable) | |
2468 | ocp_data |= U2P3_ENABLE; | |
2469 | else | |
2470 | ocp_data &= ~U2P3_ENABLE; | |
2471 | ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); | |
2472 | } | |
2473 | ||
b9702723 | 2474 | static void r8153_power_cut_en(struct r8152 *tp, bool enable) |
43779f8d | 2475 | { |
2476 | u32 ocp_data; | |
2477 | ||
2478 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); | |
2479 | if (enable) | |
2480 | ocp_data |= PWR_EN | PHASE2_EN; | |
2481 | else | |
2482 | ocp_data &= ~(PWR_EN | PHASE2_EN); | |
2483 | ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); | |
2484 | ||
2485 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); | |
2486 | ocp_data &= ~PCUT_STATUS; | |
2487 | ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); | |
2488 | } | |
2489 | ||
43779f8d | 2490 | static void r8153_first_init(struct r8152 *tp) |
2491 | { | |
2492 | u32 ocp_data; | |
2493 | int i; | |
2494 | ||
6871438c | 2495 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
2496 | return; | |
2497 | ||
00a5e360 | 2498 | rxdy_gated_en(tp, true); |
43779f8d | 2499 | r8153_teredo_off(tp); |
2500 | ||
2501 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2502 | ocp_data &= ~RCR_ACPT_ALL; | |
2503 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2504 | ||
2505 | r8153_hw_phy_cfg(tp); | |
2506 | ||
2507 | rtl8152_nic_reset(tp); | |
2508 | ||
2509 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2510 | ocp_data &= ~NOW_IS_OOB; | |
2511 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2512 | ||
2513 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2514 | ocp_data &= ~MCU_BORW_EN; | |
2515 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2516 | ||
2517 | for (i = 0; i < 1000; i++) { | |
2518 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2519 | if (ocp_data & LINK_LIST_READY) | |
2520 | break; | |
2521 | mdelay(1); | |
2522 | } | |
2523 | ||
2524 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2525 | ocp_data |= RE_INIT_LL; | |
2526 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2527 | ||
2528 | for (i = 0; i < 1000; i++) { | |
2529 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2530 | if (ocp_data & LINK_LIST_READY) | |
2531 | break; | |
2532 | mdelay(1); | |
2533 | } | |
2534 | ||
2535 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); | |
2536 | ocp_data &= ~CPCR_RX_VLAN; | |
2537 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); | |
2538 | ||
69b4b7a4 | 2539 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS); |
2540 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO); | |
43779f8d | 2541 | |
2542 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); | |
2543 | ocp_data |= TCR0_AUTO_FIFO; | |
2544 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); | |
2545 | ||
2546 | rtl8152_nic_reset(tp); | |
2547 | ||
2548 | /* rx share fifo credit full threshold */ | |
2549 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); | |
2550 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL); | |
2551 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL); | |
2552 | /* TX share fifo free credit full threshold */ | |
2553 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2); | |
2554 | ||
9629e3c0 | 2555 | /* rx aggregation */ |
43779f8d | 2556 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); |
2557 | ocp_data &= ~RX_AGG_DISABLE; | |
2558 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); | |
2559 | } | |
2560 | ||
2561 | static void r8153_enter_oob(struct r8152 *tp) | |
2562 | { | |
2563 | u32 ocp_data; | |
2564 | int i; | |
2565 | ||
2566 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2567 | ocp_data &= ~NOW_IS_OOB; | |
2568 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2569 | ||
2570 | rtl8152_disable(tp); | |
2571 | ||
2572 | for (i = 0; i < 1000; i++) { | |
2573 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2574 | if (ocp_data & LINK_LIST_READY) | |
2575 | break; | |
2576 | mdelay(1); | |
2577 | } | |
2578 | ||
2579 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2580 | ocp_data |= RE_INIT_LL; | |
2581 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2582 | ||
2583 | for (i = 0; i < 1000; i++) { | |
2584 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2585 | if (ocp_data & LINK_LIST_READY) | |
2586 | break; | |
2587 | mdelay(1); | |
2588 | } | |
2589 | ||
69b4b7a4 | 2590 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS); |
43779f8d | 2591 | |
43779f8d | 2592 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); |
2593 | ocp_data &= ~TEREDO_WAKE_MASK; | |
2594 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); | |
2595 | ||
2596 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); | |
2597 | ocp_data |= CPCR_RX_VLAN; | |
2598 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); | |
2599 | ||
2600 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); | |
2601 | ocp_data |= ALDPS_PROXY_MODE; | |
2602 | ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); | |
2603 | ||
2604 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2605 | ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; | |
2606 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2607 | ||
00a5e360 | 2608 | rxdy_gated_en(tp, false); |
43779f8d | 2609 | |
2610 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2611 | ocp_data |= RCR_APM | RCR_AM | RCR_AB; | |
2612 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2613 | } | |
2614 | ||
2615 | static void r8153_disable_aldps(struct r8152 *tp) | |
2616 | { | |
2617 | u16 data; | |
2618 | ||
2619 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
2620 | data &= ~EN_ALDPS; | |
2621 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
2622 | msleep(20); | |
2623 | } | |
2624 | ||
2625 | static void r8153_enable_aldps(struct r8152 *tp) | |
2626 | { | |
2627 | u16 data; | |
2628 | ||
2629 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
2630 | data |= EN_ALDPS; | |
2631 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
2632 | } | |
2633 | ||
ac718b69 | 2634 | static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex) |
2635 | { | |
43779f8d | 2636 | u16 bmcr, anar, gbcr; |
ac718b69 | 2637 | int ret = 0; |
2638 | ||
2639 | cancel_delayed_work_sync(&tp->schedule); | |
2640 | anar = r8152_mdio_read(tp, MII_ADVERTISE); | |
2641 | anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | | |
2642 | ADVERTISE_100HALF | ADVERTISE_100FULL); | |
43779f8d | 2643 | if (tp->mii.supports_gmii) { |
2644 | gbcr = r8152_mdio_read(tp, MII_CTRL1000); | |
2645 | gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); | |
2646 | } else { | |
2647 | gbcr = 0; | |
2648 | } | |
ac718b69 | 2649 | |
2650 | if (autoneg == AUTONEG_DISABLE) { | |
2651 | if (speed == SPEED_10) { | |
2652 | bmcr = 0; | |
2653 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
2654 | } else if (speed == SPEED_100) { | |
2655 | bmcr = BMCR_SPEED100; | |
2656 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; | |
43779f8d | 2657 | } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { |
2658 | bmcr = BMCR_SPEED1000; | |
2659 | gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; | |
ac718b69 | 2660 | } else { |
2661 | ret = -EINVAL; | |
2662 | goto out; | |
2663 | } | |
2664 | ||
2665 | if (duplex == DUPLEX_FULL) | |
2666 | bmcr |= BMCR_FULLDPLX; | |
2667 | } else { | |
2668 | if (speed == SPEED_10) { | |
2669 | if (duplex == DUPLEX_FULL) | |
2670 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
2671 | else | |
2672 | anar |= ADVERTISE_10HALF; | |
2673 | } else if (speed == SPEED_100) { | |
2674 | if (duplex == DUPLEX_FULL) { | |
2675 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
2676 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; | |
2677 | } else { | |
2678 | anar |= ADVERTISE_10HALF; | |
2679 | anar |= ADVERTISE_100HALF; | |
2680 | } | |
43779f8d | 2681 | } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { |
2682 | if (duplex == DUPLEX_FULL) { | |
2683 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
2684 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; | |
2685 | gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; | |
2686 | } else { | |
2687 | anar |= ADVERTISE_10HALF; | |
2688 | anar |= ADVERTISE_100HALF; | |
2689 | gbcr |= ADVERTISE_1000HALF; | |
2690 | } | |
ac718b69 | 2691 | } else { |
2692 | ret = -EINVAL; | |
2693 | goto out; | |
2694 | } | |
2695 | ||
2696 | bmcr = BMCR_ANENABLE | BMCR_ANRESTART; | |
2697 | } | |
2698 | ||
aa66a5f1 | 2699 | if (test_bit(PHY_RESET, &tp->flags)) |
2700 | bmcr |= BMCR_RESET; | |
2701 | ||
43779f8d | 2702 | if (tp->mii.supports_gmii) |
2703 | r8152_mdio_write(tp, MII_CTRL1000, gbcr); | |
2704 | ||
ac718b69 | 2705 | r8152_mdio_write(tp, MII_ADVERTISE, anar); |
2706 | r8152_mdio_write(tp, MII_BMCR, bmcr); | |
2707 | ||
aa66a5f1 | 2708 | if (test_bit(PHY_RESET, &tp->flags)) { |
2709 | int i; | |
2710 | ||
2711 | clear_bit(PHY_RESET, &tp->flags); | |
2712 | for (i = 0; i < 50; i++) { | |
2713 | msleep(20); | |
2714 | if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) | |
2715 | break; | |
2716 | } | |
2717 | } | |
2718 | ||
ac718b69 | 2719 | out: |
ac718b69 | 2720 | |
2721 | return ret; | |
2722 | } | |
2723 | ||
2724 | static void rtl8152_down(struct r8152 *tp) | |
2725 | { | |
6871438c | 2726 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) { |
2727 | rtl_drop_queued_tx(tp); | |
2728 | return; | |
2729 | } | |
2730 | ||
00a5e360 | 2731 | r8152_power_cut_en(tp, false); |
ac718b69 | 2732 | r8152b_disable_aldps(tp); |
2733 | r8152b_enter_oob(tp); | |
2734 | r8152b_enable_aldps(tp); | |
2735 | } | |
2736 | ||
43779f8d | 2737 | static void rtl8153_down(struct r8152 *tp) |
2738 | { | |
6871438c | 2739 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) { |
2740 | rtl_drop_queued_tx(tp); | |
2741 | return; | |
2742 | } | |
2743 | ||
b9702723 | 2744 | r8153_u1u2en(tp, false); |
2745 | r8153_power_cut_en(tp, false); | |
43779f8d | 2746 | r8153_disable_aldps(tp); |
2747 | r8153_enter_oob(tp); | |
2748 | r8153_enable_aldps(tp); | |
2749 | } | |
2750 | ||
ac718b69 | 2751 | static void set_carrier(struct r8152 *tp) |
2752 | { | |
2753 | struct net_device *netdev = tp->netdev; | |
2754 | u8 speed; | |
2755 | ||
40a82917 | 2756 | clear_bit(RTL8152_LINK_CHG, &tp->flags); |
ac718b69 | 2757 | speed = rtl8152_get_speed(tp); |
2758 | ||
2759 | if (speed & LINK_STATUS) { | |
2760 | if (!(tp->speed & LINK_STATUS)) { | |
c81229c9 | 2761 | tp->rtl_ops.enable(tp); |
ac718b69 | 2762 | set_bit(RTL8152_SET_RX_MODE, &tp->flags); |
2763 | netif_carrier_on(netdev); | |
2764 | } | |
2765 | } else { | |
2766 | if (tp->speed & LINK_STATUS) { | |
2767 | netif_carrier_off(netdev); | |
ebc2ec48 | 2768 | tasklet_disable(&tp->tl); |
c81229c9 | 2769 | tp->rtl_ops.disable(tp); |
ebc2ec48 | 2770 | tasklet_enable(&tp->tl); |
ac718b69 | 2771 | } |
2772 | } | |
2773 | tp->speed = speed; | |
2774 | } | |
2775 | ||
2776 | static void rtl_work_func_t(struct work_struct *work) | |
2777 | { | |
2778 | struct r8152 *tp = container_of(work, struct r8152, schedule.work); | |
2779 | ||
9a4be1bd | 2780 | if (usb_autopm_get_interface(tp->intf) < 0) |
2781 | return; | |
2782 | ||
ac718b69 | 2783 | if (!test_bit(WORK_ENABLE, &tp->flags)) |
2784 | goto out1; | |
2785 | ||
2786 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
2787 | goto out1; | |
2788 | ||
40a82917 | 2789 | if (test_bit(RTL8152_LINK_CHG, &tp->flags)) |
2790 | set_carrier(tp); | |
ac718b69 | 2791 | |
2792 | if (test_bit(RTL8152_SET_RX_MODE, &tp->flags)) | |
2793 | _rtl8152_set_rx_mode(tp->netdev); | |
2794 | ||
0c3121fc | 2795 | if (test_bit(SCHEDULE_TASKLET, &tp->flags) && |
2796 | (tp->speed & LINK_STATUS)) { | |
2797 | clear_bit(SCHEDULE_TASKLET, &tp->flags); | |
2798 | tasklet_schedule(&tp->tl); | |
2799 | } | |
aa66a5f1 | 2800 | |
2801 | if (test_bit(PHY_RESET, &tp->flags)) | |
2802 | rtl_phy_reset(tp); | |
2803 | ||
ac718b69 | 2804 | out1: |
9a4be1bd | 2805 | usb_autopm_put_interface(tp->intf); |
ac718b69 | 2806 | } |
2807 | ||
2808 | static int rtl8152_open(struct net_device *netdev) | |
2809 | { | |
2810 | struct r8152 *tp = netdev_priv(netdev); | |
2811 | int res = 0; | |
2812 | ||
7e9da481 | 2813 | res = alloc_all_mem(tp); |
2814 | if (res) | |
2815 | goto out; | |
2816 | ||
9a4be1bd | 2817 | res = usb_autopm_get_interface(tp->intf); |
2818 | if (res < 0) { | |
2819 | free_all_mem(tp); | |
2820 | goto out; | |
2821 | } | |
2822 | ||
2823 | /* The WORK_ENABLE may be set when autoresume occurs */ | |
2824 | if (test_bit(WORK_ENABLE, &tp->flags)) { | |
2825 | clear_bit(WORK_ENABLE, &tp->flags); | |
2826 | usb_kill_urb(tp->intr_urb); | |
2827 | cancel_delayed_work_sync(&tp->schedule); | |
2828 | if (tp->speed & LINK_STATUS) | |
2829 | tp->rtl_ops.disable(tp); | |
2830 | } | |
2831 | ||
7e9da481 | 2832 | tp->rtl_ops.up(tp); |
2833 | ||
3d55f44f | 2834 | rtl8152_set_speed(tp, AUTONEG_ENABLE, |
2835 | tp->mii.supports_gmii ? SPEED_1000 : SPEED_100, | |
2836 | DUPLEX_FULL); | |
2837 | tp->speed = 0; | |
2838 | netif_carrier_off(netdev); | |
2839 | netif_start_queue(netdev); | |
2840 | set_bit(WORK_ENABLE, &tp->flags); | |
db8515ef | 2841 | |
40a82917 | 2842 | res = usb_submit_urb(tp->intr_urb, GFP_KERNEL); |
2843 | if (res) { | |
2844 | if (res == -ENODEV) | |
2845 | netif_device_detach(tp->netdev); | |
4a8deae2 HW |
2846 | netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n", |
2847 | res); | |
7e9da481 | 2848 | free_all_mem(tp); |
ac718b69 | 2849 | } |
2850 | ||
9a4be1bd | 2851 | usb_autopm_put_interface(tp->intf); |
ac718b69 | 2852 | |
7e9da481 | 2853 | out: |
ac718b69 | 2854 | return res; |
2855 | } | |
2856 | ||
2857 | static int rtl8152_close(struct net_device *netdev) | |
2858 | { | |
2859 | struct r8152 *tp = netdev_priv(netdev); | |
2860 | int res = 0; | |
2861 | ||
2862 | clear_bit(WORK_ENABLE, &tp->flags); | |
3d55f44f | 2863 | usb_kill_urb(tp->intr_urb); |
ac718b69 | 2864 | cancel_delayed_work_sync(&tp->schedule); |
2865 | netif_stop_queue(netdev); | |
9a4be1bd | 2866 | |
2867 | res = usb_autopm_get_interface(tp->intf); | |
2868 | if (res < 0) { | |
2869 | rtl_drop_queued_tx(tp); | |
2870 | } else { | |
b209af99 | 2871 | /* The autosuspend may have been enabled and wouldn't |
9a4be1bd | 2872 | * be disable when autoresume occurs, because the |
2873 | * netif_running() would be false. | |
2874 | */ | |
2875 | if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { | |
2876 | rtl_runtime_suspend_enable(tp, false); | |
2877 | clear_bit(SELECTIVE_SUSPEND, &tp->flags); | |
2878 | } | |
2879 | ||
2880 | tasklet_disable(&tp->tl); | |
2881 | tp->rtl_ops.down(tp); | |
2882 | tasklet_enable(&tp->tl); | |
2883 | usb_autopm_put_interface(tp->intf); | |
2884 | } | |
ac718b69 | 2885 | |
7e9da481 | 2886 | free_all_mem(tp); |
2887 | ||
ac718b69 | 2888 | return res; |
2889 | } | |
2890 | ||
ac718b69 | 2891 | static void r8152b_enable_eee(struct r8152 *tp) |
2892 | { | |
45f4a19f | 2893 | u32 ocp_data; |
ac718b69 | 2894 | |
2895 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); | |
2896 | ocp_data |= EEE_RX_EN | EEE_TX_EN; | |
2897 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); | |
2898 | ocp_reg_write(tp, OCP_EEE_CONFIG1, RG_TXLPI_MSK_HFDUP | RG_MATCLR_EN | | |
2899 | EEE_10_CAP | EEE_NWAY_EN | | |
2900 | TX_QUIET_EN | RX_QUIET_EN | | |
2901 | SDRISETIME | RG_RXLPI_MSK_HFDUP | | |
2902 | SDFALLTIME); | |
2903 | ocp_reg_write(tp, OCP_EEE_CONFIG2, RG_LPIHYS_NUM | RG_DACQUIET_EN | | |
2904 | RG_LDVQUIET_EN | RG_CKRSEL | | |
2905 | RG_EEEPRG_EN); | |
2906 | ocp_reg_write(tp, OCP_EEE_CONFIG3, FST_SNR_EYE_R | RG_LFS_SEL | MSK_PH); | |
2907 | ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | DEVICE_ADDR); | |
2908 | ocp_reg_write(tp, OCP_EEE_DATA, EEE_ADDR); | |
2909 | ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | DEVICE_ADDR); | |
2910 | ocp_reg_write(tp, OCP_EEE_DATA, EEE_DATA); | |
2911 | ocp_reg_write(tp, OCP_EEE_AR, 0x0000); | |
2912 | } | |
2913 | ||
43779f8d | 2914 | static void r8153_enable_eee(struct r8152 *tp) |
2915 | { | |
2916 | u32 ocp_data; | |
2917 | u16 data; | |
2918 | ||
2919 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); | |
2920 | ocp_data |= EEE_RX_EN | EEE_TX_EN; | |
2921 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); | |
2922 | data = ocp_reg_read(tp, OCP_EEE_CFG); | |
2923 | data |= EEE10_EN; | |
2924 | ocp_reg_write(tp, OCP_EEE_CFG, data); | |
2925 | data = ocp_reg_read(tp, OCP_EEE_CFG2); | |
2926 | data |= MY1000_EEE | MY100_EEE; | |
2927 | ocp_reg_write(tp, OCP_EEE_CFG2, data); | |
2928 | } | |
2929 | ||
ac718b69 | 2930 | static void r8152b_enable_fc(struct r8152 *tp) |
2931 | { | |
2932 | u16 anar; | |
2933 | ||
2934 | anar = r8152_mdio_read(tp, MII_ADVERTISE); | |
2935 | anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; | |
2936 | r8152_mdio_write(tp, MII_ADVERTISE, anar); | |
2937 | } | |
2938 | ||
4f1d4d54 | 2939 | static void rtl_tally_reset(struct r8152 *tp) |
2940 | { | |
2941 | u32 ocp_data; | |
2942 | ||
2943 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY); | |
2944 | ocp_data |= TALLY_RESET; | |
2945 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data); | |
2946 | } | |
2947 | ||
ac718b69 | 2948 | static void r8152b_init(struct r8152 *tp) |
2949 | { | |
ebc2ec48 | 2950 | u32 ocp_data; |
ac718b69 | 2951 | |
6871438c | 2952 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
2953 | return; | |
2954 | ||
ac718b69 | 2955 | if (tp->version == RTL_VER_01) { |
2956 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); | |
2957 | ocp_data &= ~LED_MODE_MASK; | |
2958 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); | |
2959 | } | |
2960 | ||
00a5e360 | 2961 | r8152_power_cut_en(tp, false); |
ac718b69 | 2962 | |
ac718b69 | 2963 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); |
2964 | ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH; | |
2965 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); | |
2966 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL); | |
2967 | ocp_data &= ~MCU_CLK_RATIO_MASK; | |
2968 | ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN; | |
2969 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data); | |
2970 | ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK | | |
2971 | SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK; | |
2972 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data); | |
2973 | ||
2974 | r8152b_enable_eee(tp); | |
2975 | r8152b_enable_aldps(tp); | |
2976 | r8152b_enable_fc(tp); | |
4f1d4d54 | 2977 | rtl_tally_reset(tp); |
ac718b69 | 2978 | |
ebc2ec48 | 2979 | /* enable rx aggregation */ |
ac718b69 | 2980 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); |
ebc2ec48 | 2981 | ocp_data &= ~RX_AGG_DISABLE; |
ac718b69 | 2982 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); |
2983 | } | |
2984 | ||
43779f8d | 2985 | static void r8153_init(struct r8152 *tp) |
2986 | { | |
2987 | u32 ocp_data; | |
2988 | int i; | |
2989 | ||
6871438c | 2990 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
2991 | return; | |
2992 | ||
b9702723 | 2993 | r8153_u1u2en(tp, false); |
43779f8d | 2994 | |
2995 | for (i = 0; i < 500; i++) { | |
2996 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & | |
2997 | AUTOLOAD_DONE) | |
2998 | break; | |
2999 | msleep(20); | |
3000 | } | |
3001 | ||
3002 | for (i = 0; i < 500; i++) { | |
3003 | ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK; | |
3004 | if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN) | |
3005 | break; | |
3006 | msleep(20); | |
3007 | } | |
3008 | ||
b9702723 | 3009 | r8153_u2p3en(tp, false); |
43779f8d | 3010 | |
3011 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL); | |
3012 | ocp_data &= ~TIMER11_EN; | |
3013 | ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data); | |
3014 | ||
43779f8d | 3015 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); |
3016 | ocp_data &= ~LED_MODE_MASK; | |
3017 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); | |
3018 | ||
3019 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL); | |
3020 | ocp_data &= ~LPM_TIMER_MASK; | |
3021 | if (tp->udev->speed == USB_SPEED_SUPER) | |
3022 | ocp_data |= LPM_TIMER_500US; | |
3023 | else | |
3024 | ocp_data |= LPM_TIMER_500MS; | |
3025 | ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data); | |
3026 | ||
3027 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2); | |
3028 | ocp_data &= ~SEN_VAL_MASK; | |
3029 | ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE; | |
3030 | ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data); | |
3031 | ||
b9702723 | 3032 | r8153_power_cut_en(tp, false); |
3033 | r8153_u1u2en(tp, true); | |
43779f8d | 3034 | |
43779f8d | 3035 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO); |
3036 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO); | |
3037 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, | |
3038 | PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN | | |
3039 | U1U2_SPDWN_EN | L1_SPDWN_EN); | |
3040 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, | |
3041 | PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN | | |
3042 | TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN | | |
3043 | EEE_SPDWN_EN); | |
3044 | ||
3045 | r8153_enable_eee(tp); | |
3046 | r8153_enable_aldps(tp); | |
3047 | r8152b_enable_fc(tp); | |
4f1d4d54 | 3048 | rtl_tally_reset(tp); |
43779f8d | 3049 | } |
3050 | ||
ac718b69 | 3051 | static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message) |
3052 | { | |
3053 | struct r8152 *tp = usb_get_intfdata(intf); | |
3054 | ||
9a4be1bd | 3055 | if (PMSG_IS_AUTO(message)) |
3056 | set_bit(SELECTIVE_SUSPEND, &tp->flags); | |
3057 | else | |
3058 | netif_device_detach(tp->netdev); | |
ac718b69 | 3059 | |
3060 | if (netif_running(tp->netdev)) { | |
3061 | clear_bit(WORK_ENABLE, &tp->flags); | |
40a82917 | 3062 | usb_kill_urb(tp->intr_urb); |
ac718b69 | 3063 | cancel_delayed_work_sync(&tp->schedule); |
9a4be1bd | 3064 | if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { |
3065 | rtl_runtime_suspend_enable(tp, true); | |
3066 | } else { | |
3067 | tasklet_disable(&tp->tl); | |
3068 | tp->rtl_ops.down(tp); | |
3069 | tasklet_enable(&tp->tl); | |
3070 | } | |
ac718b69 | 3071 | } |
3072 | ||
ac718b69 | 3073 | return 0; |
3074 | } | |
3075 | ||
3076 | static int rtl8152_resume(struct usb_interface *intf) | |
3077 | { | |
3078 | struct r8152 *tp = usb_get_intfdata(intf); | |
3079 | ||
9a4be1bd | 3080 | if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) { |
3081 | tp->rtl_ops.init(tp); | |
3082 | netif_device_attach(tp->netdev); | |
3083 | } | |
3084 | ||
ac718b69 | 3085 | if (netif_running(tp->netdev)) { |
9a4be1bd | 3086 | if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { |
3087 | rtl_runtime_suspend_enable(tp, false); | |
3088 | clear_bit(SELECTIVE_SUSPEND, &tp->flags); | |
3089 | if (tp->speed & LINK_STATUS) | |
3090 | tp->rtl_ops.disable(tp); | |
3091 | } else { | |
3092 | tp->rtl_ops.up(tp); | |
3093 | rtl8152_set_speed(tp, AUTONEG_ENABLE, | |
b209af99 | 3094 | tp->mii.supports_gmii ? |
3095 | SPEED_1000 : SPEED_100, | |
3096 | DUPLEX_FULL); | |
9a4be1bd | 3097 | } |
40a82917 | 3098 | tp->speed = 0; |
3099 | netif_carrier_off(tp->netdev); | |
ac718b69 | 3100 | set_bit(WORK_ENABLE, &tp->flags); |
40a82917 | 3101 | usb_submit_urb(tp->intr_urb, GFP_KERNEL); |
ac718b69 | 3102 | } |
3103 | ||
3104 | return 0; | |
3105 | } | |
3106 | ||
21ff2e89 | 3107 | static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
3108 | { | |
3109 | struct r8152 *tp = netdev_priv(dev); | |
3110 | ||
9a4be1bd | 3111 | if (usb_autopm_get_interface(tp->intf) < 0) |
3112 | return; | |
3113 | ||
21ff2e89 | 3114 | wol->supported = WAKE_ANY; |
3115 | wol->wolopts = __rtl_get_wol(tp); | |
9a4be1bd | 3116 | |
3117 | usb_autopm_put_interface(tp->intf); | |
21ff2e89 | 3118 | } |
3119 | ||
3120 | static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
3121 | { | |
3122 | struct r8152 *tp = netdev_priv(dev); | |
9a4be1bd | 3123 | int ret; |
3124 | ||
3125 | ret = usb_autopm_get_interface(tp->intf); | |
3126 | if (ret < 0) | |
3127 | goto out_set_wol; | |
21ff2e89 | 3128 | |
3129 | __rtl_set_wol(tp, wol->wolopts); | |
3130 | tp->saved_wolopts = wol->wolopts & WAKE_ANY; | |
3131 | ||
9a4be1bd | 3132 | usb_autopm_put_interface(tp->intf); |
3133 | ||
3134 | out_set_wol: | |
3135 | return ret; | |
21ff2e89 | 3136 | } |
3137 | ||
a5ec27c1 | 3138 | static u32 rtl8152_get_msglevel(struct net_device *dev) |
3139 | { | |
3140 | struct r8152 *tp = netdev_priv(dev); | |
3141 | ||
3142 | return tp->msg_enable; | |
3143 | } | |
3144 | ||
3145 | static void rtl8152_set_msglevel(struct net_device *dev, u32 value) | |
3146 | { | |
3147 | struct r8152 *tp = netdev_priv(dev); | |
3148 | ||
3149 | tp->msg_enable = value; | |
3150 | } | |
3151 | ||
ac718b69 | 3152 | static void rtl8152_get_drvinfo(struct net_device *netdev, |
3153 | struct ethtool_drvinfo *info) | |
3154 | { | |
3155 | struct r8152 *tp = netdev_priv(netdev); | |
3156 | ||
b0b46c77 | 3157 | strlcpy(info->driver, MODULENAME, sizeof(info->driver)); |
3158 | strlcpy(info->version, DRIVER_VERSION, sizeof(info->version)); | |
ac718b69 | 3159 | usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info)); |
3160 | } | |
3161 | ||
3162 | static | |
3163 | int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd) | |
3164 | { | |
3165 | struct r8152 *tp = netdev_priv(netdev); | |
3166 | ||
3167 | if (!tp->mii.mdio_read) | |
3168 | return -EOPNOTSUPP; | |
3169 | ||
3170 | return mii_ethtool_gset(&tp->mii, cmd); | |
3171 | } | |
3172 | ||
3173 | static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
3174 | { | |
3175 | struct r8152 *tp = netdev_priv(dev); | |
9a4be1bd | 3176 | int ret; |
3177 | ||
3178 | ret = usb_autopm_get_interface(tp->intf); | |
3179 | if (ret < 0) | |
3180 | goto out; | |
ac718b69 | 3181 | |
9a4be1bd | 3182 | ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex); |
3183 | ||
3184 | usb_autopm_put_interface(tp->intf); | |
3185 | ||
3186 | out: | |
3187 | return ret; | |
ac718b69 | 3188 | } |
3189 | ||
4f1d4d54 | 3190 | static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = { |
3191 | "tx_packets", | |
3192 | "rx_packets", | |
3193 | "tx_errors", | |
3194 | "rx_errors", | |
3195 | "rx_missed", | |
3196 | "align_errors", | |
3197 | "tx_single_collisions", | |
3198 | "tx_multi_collisions", | |
3199 | "rx_unicast", | |
3200 | "rx_broadcast", | |
3201 | "rx_multicast", | |
3202 | "tx_aborted", | |
3203 | "tx_underrun", | |
3204 | }; | |
3205 | ||
3206 | static int rtl8152_get_sset_count(struct net_device *dev, int sset) | |
3207 | { | |
3208 | switch (sset) { | |
3209 | case ETH_SS_STATS: | |
3210 | return ARRAY_SIZE(rtl8152_gstrings); | |
3211 | default: | |
3212 | return -EOPNOTSUPP; | |
3213 | } | |
3214 | } | |
3215 | ||
3216 | static void rtl8152_get_ethtool_stats(struct net_device *dev, | |
3217 | struct ethtool_stats *stats, u64 *data) | |
3218 | { | |
3219 | struct r8152 *tp = netdev_priv(dev); | |
3220 | struct tally_counter tally; | |
3221 | ||
0b030244 | 3222 | if (usb_autopm_get_interface(tp->intf) < 0) |
3223 | return; | |
3224 | ||
4f1d4d54 | 3225 | generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA); |
3226 | ||
0b030244 | 3227 | usb_autopm_put_interface(tp->intf); |
3228 | ||
4f1d4d54 | 3229 | data[0] = le64_to_cpu(tally.tx_packets); |
3230 | data[1] = le64_to_cpu(tally.rx_packets); | |
3231 | data[2] = le64_to_cpu(tally.tx_errors); | |
3232 | data[3] = le32_to_cpu(tally.rx_errors); | |
3233 | data[4] = le16_to_cpu(tally.rx_missed); | |
3234 | data[5] = le16_to_cpu(tally.align_errors); | |
3235 | data[6] = le32_to_cpu(tally.tx_one_collision); | |
3236 | data[7] = le32_to_cpu(tally.tx_multi_collision); | |
3237 | data[8] = le64_to_cpu(tally.rx_unicast); | |
3238 | data[9] = le64_to_cpu(tally.rx_broadcast); | |
3239 | data[10] = le32_to_cpu(tally.rx_multicast); | |
3240 | data[11] = le16_to_cpu(tally.tx_aborted); | |
3241 | data[12] = le16_to_cpu(tally.tx_underun); | |
3242 | } | |
3243 | ||
3244 | static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data) | |
3245 | { | |
3246 | switch (stringset) { | |
3247 | case ETH_SS_STATS: | |
3248 | memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings)); | |
3249 | break; | |
3250 | } | |
3251 | } | |
3252 | ||
ac718b69 | 3253 | static struct ethtool_ops ops = { |
3254 | .get_drvinfo = rtl8152_get_drvinfo, | |
3255 | .get_settings = rtl8152_get_settings, | |
3256 | .set_settings = rtl8152_set_settings, | |
3257 | .get_link = ethtool_op_get_link, | |
a5ec27c1 | 3258 | .get_msglevel = rtl8152_get_msglevel, |
3259 | .set_msglevel = rtl8152_set_msglevel, | |
21ff2e89 | 3260 | .get_wol = rtl8152_get_wol, |
3261 | .set_wol = rtl8152_set_wol, | |
4f1d4d54 | 3262 | .get_strings = rtl8152_get_strings, |
3263 | .get_sset_count = rtl8152_get_sset_count, | |
3264 | .get_ethtool_stats = rtl8152_get_ethtool_stats, | |
ac718b69 | 3265 | }; |
3266 | ||
3267 | static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) | |
3268 | { | |
3269 | struct r8152 *tp = netdev_priv(netdev); | |
3270 | struct mii_ioctl_data *data = if_mii(rq); | |
9a4be1bd | 3271 | int res; |
3272 | ||
6871438c | 3273 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
3274 | return -ENODEV; | |
3275 | ||
9a4be1bd | 3276 | res = usb_autopm_get_interface(tp->intf); |
3277 | if (res < 0) | |
3278 | goto out; | |
ac718b69 | 3279 | |
3280 | switch (cmd) { | |
3281 | case SIOCGMIIPHY: | |
3282 | data->phy_id = R8152_PHY_ID; /* Internal PHY */ | |
3283 | break; | |
3284 | ||
3285 | case SIOCGMIIREG: | |
3286 | data->val_out = r8152_mdio_read(tp, data->reg_num); | |
3287 | break; | |
3288 | ||
3289 | case SIOCSMIIREG: | |
3290 | if (!capable(CAP_NET_ADMIN)) { | |
3291 | res = -EPERM; | |
3292 | break; | |
3293 | } | |
3294 | r8152_mdio_write(tp, data->reg_num, data->val_in); | |
3295 | break; | |
3296 | ||
3297 | default: | |
3298 | res = -EOPNOTSUPP; | |
3299 | } | |
3300 | ||
9a4be1bd | 3301 | usb_autopm_put_interface(tp->intf); |
3302 | ||
3303 | out: | |
ac718b69 | 3304 | return res; |
3305 | } | |
3306 | ||
69b4b7a4 | 3307 | static int rtl8152_change_mtu(struct net_device *dev, int new_mtu) |
3308 | { | |
3309 | struct r8152 *tp = netdev_priv(dev); | |
3310 | ||
3311 | switch (tp->version) { | |
3312 | case RTL_VER_01: | |
3313 | case RTL_VER_02: | |
3314 | return eth_change_mtu(dev, new_mtu); | |
3315 | default: | |
3316 | break; | |
3317 | } | |
3318 | ||
3319 | if (new_mtu < 68 || new_mtu > RTL8153_MAX_MTU) | |
3320 | return -EINVAL; | |
3321 | ||
3322 | dev->mtu = new_mtu; | |
3323 | ||
3324 | return 0; | |
3325 | } | |
3326 | ||
ac718b69 | 3327 | static const struct net_device_ops rtl8152_netdev_ops = { |
3328 | .ndo_open = rtl8152_open, | |
3329 | .ndo_stop = rtl8152_close, | |
3330 | .ndo_do_ioctl = rtl8152_ioctl, | |
3331 | .ndo_start_xmit = rtl8152_start_xmit, | |
3332 | .ndo_tx_timeout = rtl8152_tx_timeout, | |
3333 | .ndo_set_rx_mode = rtl8152_set_rx_mode, | |
3334 | .ndo_set_mac_address = rtl8152_set_mac_address, | |
69b4b7a4 | 3335 | .ndo_change_mtu = rtl8152_change_mtu, |
ac718b69 | 3336 | .ndo_validate_addr = eth_validate_addr, |
3337 | }; | |
3338 | ||
3339 | static void r8152b_get_version(struct r8152 *tp) | |
3340 | { | |
3341 | u32 ocp_data; | |
3342 | u16 version; | |
3343 | ||
3344 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1); | |
3345 | version = (u16)(ocp_data & VERSION_MASK); | |
3346 | ||
3347 | switch (version) { | |
3348 | case 0x4c00: | |
3349 | tp->version = RTL_VER_01; | |
3350 | break; | |
3351 | case 0x4c10: | |
3352 | tp->version = RTL_VER_02; | |
3353 | break; | |
43779f8d | 3354 | case 0x5c00: |
3355 | tp->version = RTL_VER_03; | |
3356 | tp->mii.supports_gmii = 1; | |
3357 | break; | |
3358 | case 0x5c10: | |
3359 | tp->version = RTL_VER_04; | |
3360 | tp->mii.supports_gmii = 1; | |
3361 | break; | |
3362 | case 0x5c20: | |
3363 | tp->version = RTL_VER_05; | |
3364 | tp->mii.supports_gmii = 1; | |
3365 | break; | |
ac718b69 | 3366 | default: |
3367 | netif_info(tp, probe, tp->netdev, | |
3368 | "Unknown version 0x%04x\n", version); | |
3369 | break; | |
3370 | } | |
3371 | } | |
3372 | ||
e3fe0b1a | 3373 | static void rtl8152_unload(struct r8152 *tp) |
3374 | { | |
6871438c | 3375 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
3376 | return; | |
3377 | ||
00a5e360 | 3378 | if (tp->version != RTL_VER_01) |
3379 | r8152_power_cut_en(tp, true); | |
e3fe0b1a | 3380 | } |
3381 | ||
43779f8d | 3382 | static void rtl8153_unload(struct r8152 *tp) |
3383 | { | |
6871438c | 3384 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
3385 | return; | |
3386 | ||
b9702723 | 3387 | r8153_power_cut_en(tp, true); |
43779f8d | 3388 | } |
3389 | ||
31ca1dec | 3390 | static int rtl_ops_init(struct r8152 *tp, const struct usb_device_id *id) |
c81229c9 | 3391 | { |
3392 | struct rtl_ops *ops = &tp->rtl_ops; | |
31ca1dec | 3393 | int ret = -ENODEV; |
c81229c9 | 3394 | |
3395 | switch (id->idVendor) { | |
3396 | case VENDOR_ID_REALTEK: | |
3397 | switch (id->idProduct) { | |
3398 | case PRODUCT_ID_RTL8152: | |
3399 | ops->init = r8152b_init; | |
3400 | ops->enable = rtl8152_enable; | |
3401 | ops->disable = rtl8152_disable; | |
7e9da481 | 3402 | ops->up = r8152b_exit_oob; |
c81229c9 | 3403 | ops->down = rtl8152_down; |
3404 | ops->unload = rtl8152_unload; | |
31ca1dec | 3405 | ret = 0; |
c81229c9 | 3406 | break; |
43779f8d | 3407 | case PRODUCT_ID_RTL8153: |
3408 | ops->init = r8153_init; | |
3409 | ops->enable = rtl8153_enable; | |
3410 | ops->disable = rtl8152_disable; | |
7e9da481 | 3411 | ops->up = r8153_first_init; |
43779f8d | 3412 | ops->down = rtl8153_down; |
3413 | ops->unload = rtl8153_unload; | |
31ca1dec | 3414 | ret = 0; |
43779f8d | 3415 | break; |
3416 | default: | |
43779f8d | 3417 | break; |
3418 | } | |
3419 | break; | |
3420 | ||
3421 | case VENDOR_ID_SAMSUNG: | |
3422 | switch (id->idProduct) { | |
3423 | case PRODUCT_ID_SAMSUNG: | |
3424 | ops->init = r8153_init; | |
3425 | ops->enable = rtl8153_enable; | |
3426 | ops->disable = rtl8152_disable; | |
7e9da481 | 3427 | ops->up = r8153_first_init; |
43779f8d | 3428 | ops->down = rtl8153_down; |
3429 | ops->unload = rtl8153_unload; | |
31ca1dec | 3430 | ret = 0; |
43779f8d | 3431 | break; |
c81229c9 | 3432 | default: |
c81229c9 | 3433 | break; |
3434 | } | |
3435 | break; | |
3436 | ||
3437 | default: | |
c81229c9 | 3438 | break; |
3439 | } | |
3440 | ||
31ca1dec | 3441 | if (ret) |
3442 | netif_err(tp, probe, tp->netdev, "Unknown Device\n"); | |
3443 | ||
c81229c9 | 3444 | return ret; |
3445 | } | |
3446 | ||
ac718b69 | 3447 | static int rtl8152_probe(struct usb_interface *intf, |
3448 | const struct usb_device_id *id) | |
3449 | { | |
3450 | struct usb_device *udev = interface_to_usbdev(intf); | |
3451 | struct r8152 *tp; | |
3452 | struct net_device *netdev; | |
ebc2ec48 | 3453 | int ret; |
ac718b69 | 3454 | |
10c32717 | 3455 | if (udev->actconfig->desc.bConfigurationValue != 1) { |
3456 | usb_driver_set_configuration(udev, 1); | |
3457 | return -ENODEV; | |
3458 | } | |
3459 | ||
3460 | usb_reset_device(udev); | |
ac718b69 | 3461 | netdev = alloc_etherdev(sizeof(struct r8152)); |
3462 | if (!netdev) { | |
4a8deae2 | 3463 | dev_err(&intf->dev, "Out of memory\n"); |
ac718b69 | 3464 | return -ENOMEM; |
3465 | } | |
3466 | ||
ebc2ec48 | 3467 | SET_NETDEV_DEV(netdev, &intf->dev); |
ac718b69 | 3468 | tp = netdev_priv(netdev); |
3469 | tp->msg_enable = 0x7FFF; | |
3470 | ||
e3ad412a | 3471 | tp->udev = udev; |
3472 | tp->netdev = netdev; | |
3473 | tp->intf = intf; | |
3474 | ||
31ca1dec | 3475 | ret = rtl_ops_init(tp, id); |
3476 | if (ret) | |
3477 | goto out; | |
c81229c9 | 3478 | |
ebc2ec48 | 3479 | tasklet_init(&tp->tl, bottom_half, (unsigned long)tp); |
ac718b69 | 3480 | INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t); |
3481 | ||
ac718b69 | 3482 | netdev->netdev_ops = &rtl8152_netdev_ops; |
3483 | netdev->watchdog_timeo = RTL8152_TX_TIMEOUT; | |
5bd23881 | 3484 | |
60c89071 | 3485 | netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | |
6128d1bb | 3486 | NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM | |
3487 | NETIF_F_TSO6; | |
60c89071 | 3488 | netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | |
6128d1bb | 3489 | NETIF_F_TSO | NETIF_F_FRAGLIST | |
3490 | NETIF_F_IPV6_CSUM | NETIF_F_TSO6; | |
db8515ef | 3491 | |
7ad24ea4 | 3492 | netdev->ethtool_ops = &ops; |
60c89071 | 3493 | netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE); |
ac718b69 | 3494 | |
3495 | tp->mii.dev = netdev; | |
3496 | tp->mii.mdio_read = read_mii_word; | |
3497 | tp->mii.mdio_write = write_mii_word; | |
3498 | tp->mii.phy_id_mask = 0x3f; | |
3499 | tp->mii.reg_num_mask = 0x1f; | |
3500 | tp->mii.phy_id = R8152_PHY_ID; | |
3501 | tp->mii.supports_gmii = 0; | |
3502 | ||
9a4be1bd | 3503 | intf->needs_remote_wakeup = 1; |
3504 | ||
ac718b69 | 3505 | r8152b_get_version(tp); |
c81229c9 | 3506 | tp->rtl_ops.init(tp); |
ac718b69 | 3507 | set_ethernet_addr(tp); |
3508 | ||
ac718b69 | 3509 | usb_set_intfdata(intf, tp); |
ac718b69 | 3510 | |
ebc2ec48 | 3511 | ret = register_netdev(netdev); |
3512 | if (ret != 0) { | |
4a8deae2 | 3513 | netif_err(tp, probe, netdev, "couldn't register the device\n"); |
ebc2ec48 | 3514 | goto out1; |
ac718b69 | 3515 | } |
3516 | ||
21ff2e89 | 3517 | tp->saved_wolopts = __rtl_get_wol(tp); |
3518 | if (tp->saved_wolopts) | |
3519 | device_set_wakeup_enable(&udev->dev, true); | |
3520 | else | |
3521 | device_set_wakeup_enable(&udev->dev, false); | |
3522 | ||
4a8deae2 | 3523 | netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION); |
ac718b69 | 3524 | |
3525 | return 0; | |
3526 | ||
ac718b69 | 3527 | out1: |
ebc2ec48 | 3528 | usb_set_intfdata(intf, NULL); |
ac718b69 | 3529 | out: |
3530 | free_netdev(netdev); | |
ebc2ec48 | 3531 | return ret; |
ac718b69 | 3532 | } |
3533 | ||
ac718b69 | 3534 | static void rtl8152_disconnect(struct usb_interface *intf) |
3535 | { | |
3536 | struct r8152 *tp = usb_get_intfdata(intf); | |
3537 | ||
3538 | usb_set_intfdata(intf, NULL); | |
3539 | if (tp) { | |
3540 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
3541 | tasklet_kill(&tp->tl); | |
3542 | unregister_netdev(tp->netdev); | |
c81229c9 | 3543 | tp->rtl_ops.unload(tp); |
ac718b69 | 3544 | free_netdev(tp->netdev); |
3545 | } | |
3546 | } | |
3547 | ||
3548 | /* table of devices that work with this driver */ | |
3549 | static struct usb_device_id rtl8152_table[] = { | |
10c32717 | 3550 | {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8152)}, |
3551 | {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8153)}, | |
3552 | {USB_DEVICE(VENDOR_ID_SAMSUNG, PRODUCT_ID_SAMSUNG)}, | |
ac718b69 | 3553 | {} |
3554 | }; | |
3555 | ||
3556 | MODULE_DEVICE_TABLE(usb, rtl8152_table); | |
3557 | ||
3558 | static struct usb_driver rtl8152_driver = { | |
3559 | .name = MODULENAME, | |
ebc2ec48 | 3560 | .id_table = rtl8152_table, |
ac718b69 | 3561 | .probe = rtl8152_probe, |
3562 | .disconnect = rtl8152_disconnect, | |
ac718b69 | 3563 | .suspend = rtl8152_suspend, |
ebc2ec48 | 3564 | .resume = rtl8152_resume, |
3565 | .reset_resume = rtl8152_resume, | |
9a4be1bd | 3566 | .supports_autosuspend = 1, |
a634782f | 3567 | .disable_hub_initiated_lpm = 1, |
ac718b69 | 3568 | }; |
3569 | ||
b4236daa | 3570 | module_usb_driver(rtl8152_driver); |
ac718b69 | 3571 | |
3572 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
3573 | MODULE_DESCRIPTION(DRIVER_DESC); | |
3574 | MODULE_LICENSE("GPL"); |