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ac718b69 | 1 | /* |
c7de7dec | 2 | * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved. |
ac718b69 | 3 | * |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * version 2 as published by the Free Software Foundation. | |
7 | * | |
8 | */ | |
9 | ||
ac718b69 | 10 | #include <linux/signal.h> |
11 | #include <linux/slab.h> | |
12 | #include <linux/module.h> | |
ac718b69 | 13 | #include <linux/netdevice.h> |
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/mii.h> | |
16 | #include <linux/ethtool.h> | |
17 | #include <linux/usb.h> | |
18 | #include <linux/crc32.h> | |
19 | #include <linux/if_vlan.h> | |
20 | #include <linux/uaccess.h> | |
ebc2ec48 | 21 | #include <linux/list.h> |
5bd23881 | 22 | #include <linux/ip.h> |
23 | #include <linux/ipv6.h> | |
ac718b69 | 24 | |
25 | /* Version Information */ | |
c7de7dec | 26 | #define DRIVER_VERSION "v1.04.0 (2014/01/15)" |
ac718b69 | 27 | #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>" |
44d942a9 | 28 | #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters" |
ac718b69 | 29 | #define MODULENAME "r8152" |
30 | ||
31 | #define R8152_PHY_ID 32 | |
32 | ||
33 | #define PLA_IDR 0xc000 | |
34 | #define PLA_RCR 0xc010 | |
35 | #define PLA_RMS 0xc016 | |
36 | #define PLA_RXFIFO_CTRL0 0xc0a0 | |
37 | #define PLA_RXFIFO_CTRL1 0xc0a4 | |
38 | #define PLA_RXFIFO_CTRL2 0xc0a8 | |
39 | #define PLA_FMC 0xc0b4 | |
40 | #define PLA_CFG_WOL 0xc0b6 | |
43779f8d | 41 | #define PLA_TEREDO_CFG 0xc0bc |
ac718b69 | 42 | #define PLA_MAR 0xcd00 |
43779f8d | 43 | #define PLA_BACKUP 0xd000 |
ac718b69 | 44 | #define PAL_BDC_CR 0xd1a0 |
43779f8d | 45 | #define PLA_TEREDO_TIMER 0xd2cc |
46 | #define PLA_REALWOW_TIMER 0xd2e8 | |
ac718b69 | 47 | #define PLA_LEDSEL 0xdd90 |
48 | #define PLA_LED_FEATURE 0xdd92 | |
49 | #define PLA_PHYAR 0xde00 | |
43779f8d | 50 | #define PLA_BOOT_CTRL 0xe004 |
ac718b69 | 51 | #define PLA_GPHY_INTR_IMR 0xe022 |
52 | #define PLA_EEE_CR 0xe040 | |
53 | #define PLA_EEEP_CR 0xe080 | |
54 | #define PLA_MAC_PWR_CTRL 0xe0c0 | |
43779f8d | 55 | #define PLA_MAC_PWR_CTRL2 0xe0ca |
56 | #define PLA_MAC_PWR_CTRL3 0xe0cc | |
57 | #define PLA_MAC_PWR_CTRL4 0xe0ce | |
58 | #define PLA_WDT6_CTRL 0xe428 | |
ac718b69 | 59 | #define PLA_TCR0 0xe610 |
60 | #define PLA_TCR1 0xe612 | |
61 | #define PLA_TXFIFO_CTRL 0xe618 | |
62 | #define PLA_RSTTELLY 0xe800 | |
63 | #define PLA_CR 0xe813 | |
64 | #define PLA_CRWECR 0xe81c | |
65 | #define PLA_CONFIG5 0xe822 | |
66 | #define PLA_PHY_PWR 0xe84c | |
67 | #define PLA_OOB_CTRL 0xe84f | |
68 | #define PLA_CPCR 0xe854 | |
69 | #define PLA_MISC_0 0xe858 | |
70 | #define PLA_MISC_1 0xe85a | |
71 | #define PLA_OCP_GPHY_BASE 0xe86c | |
72 | #define PLA_TELLYCNT 0xe890 | |
73 | #define PLA_SFF_STS_7 0xe8de | |
74 | #define PLA_PHYSTATUS 0xe908 | |
75 | #define PLA_BP_BA 0xfc26 | |
76 | #define PLA_BP_0 0xfc28 | |
77 | #define PLA_BP_1 0xfc2a | |
78 | #define PLA_BP_2 0xfc2c | |
79 | #define PLA_BP_3 0xfc2e | |
80 | #define PLA_BP_4 0xfc30 | |
81 | #define PLA_BP_5 0xfc32 | |
82 | #define PLA_BP_6 0xfc34 | |
83 | #define PLA_BP_7 0xfc36 | |
43779f8d | 84 | #define PLA_BP_EN 0xfc38 |
ac718b69 | 85 | |
43779f8d | 86 | #define USB_U2P3_CTRL 0xb460 |
ac718b69 | 87 | #define USB_DEV_STAT 0xb808 |
88 | #define USB_USB_CTRL 0xd406 | |
89 | #define USB_PHY_CTRL 0xd408 | |
90 | #define USB_TX_AGG 0xd40a | |
91 | #define USB_RX_BUF_TH 0xd40c | |
92 | #define USB_USB_TIMER 0xd428 | |
43779f8d | 93 | #define USB_RX_EARLY_AGG 0xd42c |
ac718b69 | 94 | #define USB_PM_CTRL_STATUS 0xd432 |
95 | #define USB_TX_DMA 0xd434 | |
43779f8d | 96 | #define USB_TOLERANCE 0xd490 |
97 | #define USB_LPM_CTRL 0xd41a | |
ac718b69 | 98 | #define USB_UPS_CTRL 0xd800 |
43779f8d | 99 | #define USB_MISC_0 0xd81a |
100 | #define USB_POWER_CUT 0xd80a | |
101 | #define USB_AFE_CTRL2 0xd824 | |
102 | #define USB_WDT11_CTRL 0xe43c | |
ac718b69 | 103 | #define USB_BP_BA 0xfc26 |
104 | #define USB_BP_0 0xfc28 | |
105 | #define USB_BP_1 0xfc2a | |
106 | #define USB_BP_2 0xfc2c | |
107 | #define USB_BP_3 0xfc2e | |
108 | #define USB_BP_4 0xfc30 | |
109 | #define USB_BP_5 0xfc32 | |
110 | #define USB_BP_6 0xfc34 | |
111 | #define USB_BP_7 0xfc36 | |
43779f8d | 112 | #define USB_BP_EN 0xfc38 |
ac718b69 | 113 | |
114 | /* OCP Registers */ | |
115 | #define OCP_ALDPS_CONFIG 0x2010 | |
116 | #define OCP_EEE_CONFIG1 0x2080 | |
117 | #define OCP_EEE_CONFIG2 0x2092 | |
118 | #define OCP_EEE_CONFIG3 0x2094 | |
ac244d3e | 119 | #define OCP_BASE_MII 0xa400 |
ac718b69 | 120 | #define OCP_EEE_AR 0xa41a |
121 | #define OCP_EEE_DATA 0xa41c | |
43779f8d | 122 | #define OCP_PHY_STATUS 0xa420 |
123 | #define OCP_POWER_CFG 0xa430 | |
124 | #define OCP_EEE_CFG 0xa432 | |
125 | #define OCP_SRAM_ADDR 0xa436 | |
126 | #define OCP_SRAM_DATA 0xa438 | |
127 | #define OCP_DOWN_SPEED 0xa442 | |
128 | #define OCP_EEE_CFG2 0xa5d0 | |
129 | #define OCP_ADC_CFG 0xbc06 | |
130 | ||
131 | /* SRAM Register */ | |
132 | #define SRAM_LPF_CFG 0x8012 | |
133 | #define SRAM_10M_AMP1 0x8080 | |
134 | #define SRAM_10M_AMP2 0x8082 | |
135 | #define SRAM_IMPEDANCE 0x8084 | |
ac718b69 | 136 | |
137 | /* PLA_RCR */ | |
138 | #define RCR_AAP 0x00000001 | |
139 | #define RCR_APM 0x00000002 | |
140 | #define RCR_AM 0x00000004 | |
141 | #define RCR_AB 0x00000008 | |
142 | #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB) | |
143 | ||
144 | /* PLA_RXFIFO_CTRL0 */ | |
145 | #define RXFIFO_THR1_NORMAL 0x00080002 | |
146 | #define RXFIFO_THR1_OOB 0x01800003 | |
147 | ||
148 | /* PLA_RXFIFO_CTRL1 */ | |
149 | #define RXFIFO_THR2_FULL 0x00000060 | |
150 | #define RXFIFO_THR2_HIGH 0x00000038 | |
151 | #define RXFIFO_THR2_OOB 0x0000004a | |
43779f8d | 152 | #define RXFIFO_THR2_NORMAL 0x00a0 |
ac718b69 | 153 | |
154 | /* PLA_RXFIFO_CTRL2 */ | |
155 | #define RXFIFO_THR3_FULL 0x00000078 | |
156 | #define RXFIFO_THR3_HIGH 0x00000048 | |
157 | #define RXFIFO_THR3_OOB 0x0000005a | |
43779f8d | 158 | #define RXFIFO_THR3_NORMAL 0x0110 |
ac718b69 | 159 | |
160 | /* PLA_TXFIFO_CTRL */ | |
161 | #define TXFIFO_THR_NORMAL 0x00400008 | |
43779f8d | 162 | #define TXFIFO_THR_NORMAL2 0x01000008 |
ac718b69 | 163 | |
164 | /* PLA_FMC */ | |
165 | #define FMC_FCR_MCU_EN 0x0001 | |
166 | ||
167 | /* PLA_EEEP_CR */ | |
168 | #define EEEP_CR_EEEP_TX 0x0002 | |
169 | ||
43779f8d | 170 | /* PLA_WDT6_CTRL */ |
171 | #define WDT6_SET_MODE 0x0010 | |
172 | ||
ac718b69 | 173 | /* PLA_TCR0 */ |
174 | #define TCR0_TX_EMPTY 0x0800 | |
175 | #define TCR0_AUTO_FIFO 0x0080 | |
176 | ||
177 | /* PLA_TCR1 */ | |
178 | #define VERSION_MASK 0x7cf0 | |
179 | ||
180 | /* PLA_CR */ | |
181 | #define CR_RST 0x10 | |
182 | #define CR_RE 0x08 | |
183 | #define CR_TE 0x04 | |
184 | ||
185 | /* PLA_CRWECR */ | |
186 | #define CRWECR_NORAML 0x00 | |
187 | #define CRWECR_CONFIG 0xc0 | |
188 | ||
189 | /* PLA_OOB_CTRL */ | |
190 | #define NOW_IS_OOB 0x80 | |
191 | #define TXFIFO_EMPTY 0x20 | |
192 | #define RXFIFO_EMPTY 0x10 | |
193 | #define LINK_LIST_READY 0x02 | |
194 | #define DIS_MCU_CLROOB 0x01 | |
195 | #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY) | |
196 | ||
197 | /* PLA_MISC_1 */ | |
198 | #define RXDY_GATED_EN 0x0008 | |
199 | ||
200 | /* PLA_SFF_STS_7 */ | |
201 | #define RE_INIT_LL 0x8000 | |
202 | #define MCU_BORW_EN 0x4000 | |
203 | ||
204 | /* PLA_CPCR */ | |
205 | #define CPCR_RX_VLAN 0x0040 | |
206 | ||
207 | /* PLA_CFG_WOL */ | |
208 | #define MAGIC_EN 0x0001 | |
209 | ||
43779f8d | 210 | /* PLA_TEREDO_CFG */ |
211 | #define TEREDO_SEL 0x8000 | |
212 | #define TEREDO_WAKE_MASK 0x7f00 | |
213 | #define TEREDO_RS_EVENT_MASK 0x00fe | |
214 | #define OOB_TEREDO_EN 0x0001 | |
215 | ||
ac718b69 | 216 | /* PAL_BDC_CR */ |
217 | #define ALDPS_PROXY_MODE 0x0001 | |
218 | ||
219 | /* PLA_CONFIG5 */ | |
220 | #define LAN_WAKE_EN 0x0002 | |
221 | ||
222 | /* PLA_LED_FEATURE */ | |
223 | #define LED_MODE_MASK 0x0700 | |
224 | ||
225 | /* PLA_PHY_PWR */ | |
226 | #define TX_10M_IDLE_EN 0x0080 | |
227 | #define PFM_PWM_SWITCH 0x0040 | |
228 | ||
229 | /* PLA_MAC_PWR_CTRL */ | |
230 | #define D3_CLK_GATED_EN 0x00004000 | |
231 | #define MCU_CLK_RATIO 0x07010f07 | |
232 | #define MCU_CLK_RATIO_MASK 0x0f0f0f0f | |
43779f8d | 233 | #define ALDPS_SPDWN_RATIO 0x0f87 |
234 | ||
235 | /* PLA_MAC_PWR_CTRL2 */ | |
236 | #define EEE_SPDWN_RATIO 0x8007 | |
237 | ||
238 | /* PLA_MAC_PWR_CTRL3 */ | |
239 | #define PKT_AVAIL_SPDWN_EN 0x0100 | |
240 | #define SUSPEND_SPDWN_EN 0x0004 | |
241 | #define U1U2_SPDWN_EN 0x0002 | |
242 | #define L1_SPDWN_EN 0x0001 | |
243 | ||
244 | /* PLA_MAC_PWR_CTRL4 */ | |
245 | #define PWRSAVE_SPDWN_EN 0x1000 | |
246 | #define RXDV_SPDWN_EN 0x0800 | |
247 | #define TX10MIDLE_EN 0x0100 | |
248 | #define TP100_SPDWN_EN 0x0020 | |
249 | #define TP500_SPDWN_EN 0x0010 | |
250 | #define TP1000_SPDWN_EN 0x0008 | |
251 | #define EEE_SPDWN_EN 0x0001 | |
ac718b69 | 252 | |
253 | /* PLA_GPHY_INTR_IMR */ | |
254 | #define GPHY_STS_MSK 0x0001 | |
255 | #define SPEED_DOWN_MSK 0x0002 | |
256 | #define SPDWN_RXDV_MSK 0x0004 | |
257 | #define SPDWN_LINKCHG_MSK 0x0008 | |
258 | ||
259 | /* PLA_PHYAR */ | |
260 | #define PHYAR_FLAG 0x80000000 | |
261 | ||
262 | /* PLA_EEE_CR */ | |
263 | #define EEE_RX_EN 0x0001 | |
264 | #define EEE_TX_EN 0x0002 | |
265 | ||
43779f8d | 266 | /* PLA_BOOT_CTRL */ |
267 | #define AUTOLOAD_DONE 0x0002 | |
268 | ||
ac718b69 | 269 | /* USB_DEV_STAT */ |
270 | #define STAT_SPEED_MASK 0x0006 | |
271 | #define STAT_SPEED_HIGH 0x0000 | |
272 | #define STAT_SPEED_FULL 0x0001 | |
273 | ||
274 | /* USB_TX_AGG */ | |
275 | #define TX_AGG_MAX_THRESHOLD 0x03 | |
276 | ||
277 | /* USB_RX_BUF_TH */ | |
43779f8d | 278 | #define RX_THR_SUPPER 0x0c350180 |
8e1f51bd | 279 | #define RX_THR_HIGH 0x7a120180 |
43779f8d | 280 | #define RX_THR_SLOW 0xffff0180 |
ac718b69 | 281 | |
282 | /* USB_TX_DMA */ | |
283 | #define TEST_MODE_DISABLE 0x00000001 | |
284 | #define TX_SIZE_ADJUST1 0x00000100 | |
285 | ||
286 | /* USB_UPS_CTRL */ | |
287 | #define POWER_CUT 0x0100 | |
288 | ||
289 | /* USB_PM_CTRL_STATUS */ | |
8e1f51bd | 290 | #define RESUME_INDICATE 0x0001 |
ac718b69 | 291 | |
292 | /* USB_USB_CTRL */ | |
293 | #define RX_AGG_DISABLE 0x0010 | |
294 | ||
43779f8d | 295 | /* USB_U2P3_CTRL */ |
296 | #define U2P3_ENABLE 0x0001 | |
297 | ||
298 | /* USB_POWER_CUT */ | |
299 | #define PWR_EN 0x0001 | |
300 | #define PHASE2_EN 0x0008 | |
301 | ||
302 | /* USB_MISC_0 */ | |
303 | #define PCUT_STATUS 0x0001 | |
304 | ||
305 | /* USB_RX_EARLY_AGG */ | |
306 | #define EARLY_AGG_SUPPER 0x0e832981 | |
307 | #define EARLY_AGG_HIGH 0x0e837a12 | |
308 | #define EARLY_AGG_SLOW 0x0e83ffff | |
309 | ||
310 | /* USB_WDT11_CTRL */ | |
311 | #define TIMER11_EN 0x0001 | |
312 | ||
313 | /* USB_LPM_CTRL */ | |
314 | #define LPM_TIMER_MASK 0x0c | |
315 | #define LPM_TIMER_500MS 0x04 /* 500 ms */ | |
316 | #define LPM_TIMER_500US 0x0c /* 500 us */ | |
317 | ||
318 | /* USB_AFE_CTRL2 */ | |
319 | #define SEN_VAL_MASK 0xf800 | |
320 | #define SEN_VAL_NORMAL 0xa000 | |
321 | #define SEL_RXIDLE 0x0100 | |
322 | ||
ac718b69 | 323 | /* OCP_ALDPS_CONFIG */ |
324 | #define ENPWRSAVE 0x8000 | |
325 | #define ENPDNPS 0x0200 | |
326 | #define LINKENA 0x0100 | |
327 | #define DIS_SDSAVE 0x0010 | |
328 | ||
43779f8d | 329 | /* OCP_PHY_STATUS */ |
330 | #define PHY_STAT_MASK 0x0007 | |
331 | #define PHY_STAT_LAN_ON 3 | |
332 | #define PHY_STAT_PWRDN 5 | |
333 | ||
334 | /* OCP_POWER_CFG */ | |
335 | #define EEE_CLKDIV_EN 0x8000 | |
336 | #define EN_ALDPS 0x0004 | |
337 | #define EN_10M_PLLOFF 0x0001 | |
338 | ||
ac718b69 | 339 | /* OCP_EEE_CONFIG1 */ |
340 | #define RG_TXLPI_MSK_HFDUP 0x8000 | |
341 | #define RG_MATCLR_EN 0x4000 | |
342 | #define EEE_10_CAP 0x2000 | |
343 | #define EEE_NWAY_EN 0x1000 | |
344 | #define TX_QUIET_EN 0x0200 | |
345 | #define RX_QUIET_EN 0x0100 | |
346 | #define SDRISETIME 0x0010 /* bit 4 ~ 6 */ | |
347 | #define RG_RXLPI_MSK_HFDUP 0x0008 | |
348 | #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */ | |
349 | ||
350 | /* OCP_EEE_CONFIG2 */ | |
351 | #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */ | |
352 | #define RG_DACQUIET_EN 0x0400 | |
353 | #define RG_LDVQUIET_EN 0x0200 | |
354 | #define RG_CKRSEL 0x0020 | |
355 | #define RG_EEEPRG_EN 0x0010 | |
356 | ||
357 | /* OCP_EEE_CONFIG3 */ | |
358 | #define FST_SNR_EYE_R 0x1500 /* bit 7 ~ 15 */ | |
359 | #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */ | |
360 | #define MSK_PH 0x0006 /* bit 0 ~ 3 */ | |
361 | ||
362 | /* OCP_EEE_AR */ | |
363 | /* bit[15:14] function */ | |
364 | #define FUN_ADDR 0x0000 | |
365 | #define FUN_DATA 0x4000 | |
366 | /* bit[4:0] device addr */ | |
367 | #define DEVICE_ADDR 0x0007 | |
368 | ||
369 | /* OCP_EEE_DATA */ | |
370 | #define EEE_ADDR 0x003C | |
371 | #define EEE_DATA 0x0002 | |
372 | ||
43779f8d | 373 | /* OCP_EEE_CFG */ |
374 | #define CTAP_SHORT_EN 0x0040 | |
375 | #define EEE10_EN 0x0010 | |
376 | ||
377 | /* OCP_DOWN_SPEED */ | |
378 | #define EN_10M_BGOFF 0x0080 | |
379 | ||
380 | /* OCP_EEE_CFG2 */ | |
381 | #define MY1000_EEE 0x0004 | |
382 | #define MY100_EEE 0x0002 | |
383 | ||
384 | /* OCP_ADC_CFG */ | |
385 | #define CKADSEL_L 0x0100 | |
386 | #define ADC_EN 0x0080 | |
387 | #define EN_EMI_L 0x0040 | |
388 | ||
389 | /* SRAM_LPF_CFG */ | |
390 | #define LPF_AUTO_TUNE 0x8000 | |
391 | ||
392 | /* SRAM_10M_AMP1 */ | |
393 | #define GDAC_IB_UPALL 0x0008 | |
394 | ||
395 | /* SRAM_10M_AMP2 */ | |
396 | #define AMP_DN 0x0200 | |
397 | ||
398 | /* SRAM_IMPEDANCE */ | |
399 | #define RX_DRIVING_MASK 0x6000 | |
400 | ||
ac718b69 | 401 | enum rtl_register_content { |
43779f8d | 402 | _1000bps = 0x10, |
ac718b69 | 403 | _100bps = 0x08, |
404 | _10bps = 0x04, | |
405 | LINK_STATUS = 0x02, | |
406 | FULL_DUP = 0x01, | |
407 | }; | |
408 | ||
ebc2ec48 | 409 | #define RTL8152_MAX_TX 10 |
410 | #define RTL8152_MAX_RX 10 | |
40a82917 | 411 | #define INTBUFSIZE 2 |
8e1f51bd | 412 | #define CRC_SIZE 4 |
413 | #define TX_ALIGN 4 | |
414 | #define RX_ALIGN 8 | |
40a82917 | 415 | |
416 | #define INTR_LINK 0x0004 | |
ebc2ec48 | 417 | |
ac718b69 | 418 | #define RTL8152_REQT_READ 0xc0 |
419 | #define RTL8152_REQT_WRITE 0x40 | |
420 | #define RTL8152_REQ_GET_REGS 0x05 | |
421 | #define RTL8152_REQ_SET_REGS 0x05 | |
422 | ||
423 | #define BYTE_EN_DWORD 0xff | |
424 | #define BYTE_EN_WORD 0x33 | |
425 | #define BYTE_EN_BYTE 0x11 | |
426 | #define BYTE_EN_SIX_BYTES 0x3f | |
427 | #define BYTE_EN_START_MASK 0x0f | |
428 | #define BYTE_EN_END_MASK 0xf0 | |
429 | ||
430 | #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN) | |
431 | #define RTL8152_TX_TIMEOUT (HZ) | |
432 | ||
433 | /* rtl8152 flags */ | |
434 | enum rtl8152_flags { | |
435 | RTL8152_UNPLUG = 0, | |
ac718b69 | 436 | RTL8152_SET_RX_MODE, |
40a82917 | 437 | WORK_ENABLE, |
438 | RTL8152_LINK_CHG, | |
aa66a5f1 | 439 | PHY_RESET, |
ac718b69 | 440 | }; |
441 | ||
442 | /* Define these values to match your device */ | |
443 | #define VENDOR_ID_REALTEK 0x0bda | |
444 | #define PRODUCT_ID_RTL8152 0x8152 | |
43779f8d | 445 | #define PRODUCT_ID_RTL8153 0x8153 |
446 | ||
447 | #define VENDOR_ID_SAMSUNG 0x04e8 | |
448 | #define PRODUCT_ID_SAMSUNG 0xa101 | |
ac718b69 | 449 | |
450 | #define MCU_TYPE_PLA 0x0100 | |
451 | #define MCU_TYPE_USB 0x0000 | |
452 | ||
c7de7dec | 453 | #define REALTEK_USB_DEVICE(vend, prod) \ |
454 | USB_DEVICE_INTERFACE_CLASS(vend, prod, USB_CLASS_VENDOR_SPEC) | |
455 | ||
ac718b69 | 456 | struct rx_desc { |
500b6d7e | 457 | __le32 opts1; |
ac718b69 | 458 | #define RX_LEN_MASK 0x7fff |
500b6d7e | 459 | __le32 opts2; |
460 | __le32 opts3; | |
461 | __le32 opts4; | |
462 | __le32 opts5; | |
463 | __le32 opts6; | |
ac718b69 | 464 | }; |
465 | ||
466 | struct tx_desc { | |
500b6d7e | 467 | __le32 opts1; |
ac718b69 | 468 | #define TX_FS (1 << 31) /* First segment of a packet */ |
469 | #define TX_LS (1 << 30) /* Final segment of a packet */ | |
5bd23881 | 470 | #define TX_LEN_MASK 0x3ffff |
471 | ||
500b6d7e | 472 | __le32 opts2; |
5bd23881 | 473 | #define UDP_CS (1 << 31) /* Calculate UDP/IP checksum */ |
474 | #define TCP_CS (1 << 30) /* Calculate TCP/IP checksum */ | |
475 | #define IPV4_CS (1 << 29) /* Calculate IPv4 checksum */ | |
476 | #define IPV6_CS (1 << 28) /* Calculate IPv6 checksum */ | |
ac718b69 | 477 | }; |
478 | ||
dff4e8ad | 479 | struct r8152; |
480 | ||
ebc2ec48 | 481 | struct rx_agg { |
482 | struct list_head list; | |
483 | struct urb *urb; | |
dff4e8ad | 484 | struct r8152 *context; |
ebc2ec48 | 485 | void *buffer; |
486 | void *head; | |
487 | }; | |
488 | ||
489 | struct tx_agg { | |
490 | struct list_head list; | |
491 | struct urb *urb; | |
dff4e8ad | 492 | struct r8152 *context; |
ebc2ec48 | 493 | void *buffer; |
494 | void *head; | |
495 | u32 skb_num; | |
496 | u32 skb_len; | |
497 | }; | |
498 | ||
ac718b69 | 499 | struct r8152 { |
500 | unsigned long flags; | |
501 | struct usb_device *udev; | |
502 | struct tasklet_struct tl; | |
40a82917 | 503 | struct usb_interface *intf; |
ac718b69 | 504 | struct net_device *netdev; |
40a82917 | 505 | struct urb *intr_urb; |
ebc2ec48 | 506 | struct tx_agg tx_info[RTL8152_MAX_TX]; |
507 | struct rx_agg rx_info[RTL8152_MAX_RX]; | |
508 | struct list_head rx_done, tx_free; | |
509 | struct sk_buff_head tx_queue; | |
510 | spinlock_t rx_lock, tx_lock; | |
ac718b69 | 511 | struct delayed_work schedule; |
512 | struct mii_if_info mii; | |
c81229c9 | 513 | |
514 | struct rtl_ops { | |
515 | void (*init)(struct r8152 *); | |
516 | int (*enable)(struct r8152 *); | |
517 | void (*disable)(struct r8152 *); | |
518 | void (*down)(struct r8152 *); | |
519 | void (*unload)(struct r8152 *); | |
520 | } rtl_ops; | |
521 | ||
40a82917 | 522 | int intr_interval; |
ac718b69 | 523 | u32 msg_enable; |
dd1b119c | 524 | u32 tx_qlen; |
ac718b69 | 525 | u16 ocp_base; |
40a82917 | 526 | u8 *intr_buff; |
ac718b69 | 527 | u8 version; |
528 | u8 speed; | |
529 | }; | |
530 | ||
531 | enum rtl_version { | |
532 | RTL_VER_UNKNOWN = 0, | |
533 | RTL_VER_01, | |
43779f8d | 534 | RTL_VER_02, |
535 | RTL_VER_03, | |
536 | RTL_VER_04, | |
537 | RTL_VER_05, | |
538 | RTL_VER_MAX | |
ac718b69 | 539 | }; |
540 | ||
541 | /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). | |
542 | * The RTL chips use a 64 element hash table based on the Ethernet CRC. | |
543 | */ | |
544 | static const int multicast_filter_limit = 32; | |
ebc2ec48 | 545 | static unsigned int rx_buf_sz = 16384; |
ac718b69 | 546 | |
547 | static | |
548 | int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) | |
549 | { | |
31787f53 | 550 | int ret; |
551 | void *tmp; | |
552 | ||
553 | tmp = kmalloc(size, GFP_KERNEL); | |
554 | if (!tmp) | |
555 | return -ENOMEM; | |
556 | ||
557 | ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0), | |
ac718b69 | 558 | RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, |
31787f53 | 559 | value, index, tmp, size, 500); |
560 | ||
561 | memcpy(data, tmp, size); | |
562 | kfree(tmp); | |
563 | ||
564 | return ret; | |
ac718b69 | 565 | } |
566 | ||
567 | static | |
568 | int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) | |
569 | { | |
31787f53 | 570 | int ret; |
571 | void *tmp; | |
572 | ||
573 | tmp = kmalloc(size, GFP_KERNEL); | |
574 | if (!tmp) | |
575 | return -ENOMEM; | |
576 | ||
577 | memcpy(tmp, data, size); | |
578 | ||
579 | ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0), | |
ac718b69 | 580 | RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE, |
31787f53 | 581 | value, index, tmp, size, 500); |
582 | ||
583 | kfree(tmp); | |
584 | return ret; | |
ac718b69 | 585 | } |
586 | ||
587 | static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size, | |
588 | void *data, u16 type) | |
589 | { | |
45f4a19f | 590 | u16 limit = 64; |
591 | int ret = 0; | |
ac718b69 | 592 | |
593 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
594 | return -ENODEV; | |
595 | ||
596 | /* both size and indix must be 4 bytes align */ | |
597 | if ((size & 3) || !size || (index & 3) || !data) | |
598 | return -EPERM; | |
599 | ||
600 | if ((u32)index + (u32)size > 0xffff) | |
601 | return -EPERM; | |
602 | ||
603 | while (size) { | |
604 | if (size > limit) { | |
605 | ret = get_registers(tp, index, type, limit, data); | |
606 | if (ret < 0) | |
607 | break; | |
608 | ||
609 | index += limit; | |
610 | data += limit; | |
611 | size -= limit; | |
612 | } else { | |
613 | ret = get_registers(tp, index, type, size, data); | |
614 | if (ret < 0) | |
615 | break; | |
616 | ||
617 | index += size; | |
618 | data += size; | |
619 | size = 0; | |
620 | break; | |
621 | } | |
622 | } | |
623 | ||
624 | return ret; | |
625 | } | |
626 | ||
627 | static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, | |
628 | u16 size, void *data, u16 type) | |
629 | { | |
45f4a19f | 630 | int ret; |
631 | u16 byteen_start, byteen_end, byen; | |
632 | u16 limit = 512; | |
ac718b69 | 633 | |
634 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
635 | return -ENODEV; | |
636 | ||
637 | /* both size and indix must be 4 bytes align */ | |
638 | if ((size & 3) || !size || (index & 3) || !data) | |
639 | return -EPERM; | |
640 | ||
641 | if ((u32)index + (u32)size > 0xffff) | |
642 | return -EPERM; | |
643 | ||
644 | byteen_start = byteen & BYTE_EN_START_MASK; | |
645 | byteen_end = byteen & BYTE_EN_END_MASK; | |
646 | ||
647 | byen = byteen_start | (byteen_start << 4); | |
648 | ret = set_registers(tp, index, type | byen, 4, data); | |
649 | if (ret < 0) | |
650 | goto error1; | |
651 | ||
652 | index += 4; | |
653 | data += 4; | |
654 | size -= 4; | |
655 | ||
656 | if (size) { | |
657 | size -= 4; | |
658 | ||
659 | while (size) { | |
660 | if (size > limit) { | |
661 | ret = set_registers(tp, index, | |
662 | type | BYTE_EN_DWORD, | |
663 | limit, data); | |
664 | if (ret < 0) | |
665 | goto error1; | |
666 | ||
667 | index += limit; | |
668 | data += limit; | |
669 | size -= limit; | |
670 | } else { | |
671 | ret = set_registers(tp, index, | |
672 | type | BYTE_EN_DWORD, | |
673 | size, data); | |
674 | if (ret < 0) | |
675 | goto error1; | |
676 | ||
677 | index += size; | |
678 | data += size; | |
679 | size = 0; | |
680 | break; | |
681 | } | |
682 | } | |
683 | ||
684 | byen = byteen_end | (byteen_end >> 4); | |
685 | ret = set_registers(tp, index, type | byen, 4, data); | |
686 | if (ret < 0) | |
687 | goto error1; | |
688 | } | |
689 | ||
690 | error1: | |
691 | return ret; | |
692 | } | |
693 | ||
694 | static inline | |
695 | int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) | |
696 | { | |
697 | return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA); | |
698 | } | |
699 | ||
700 | static inline | |
701 | int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) | |
702 | { | |
703 | return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA); | |
704 | } | |
705 | ||
706 | static inline | |
707 | int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) | |
708 | { | |
709 | return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB); | |
710 | } | |
711 | ||
712 | static inline | |
713 | int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) | |
714 | { | |
715 | return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB); | |
716 | } | |
717 | ||
718 | static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index) | |
719 | { | |
c8826de8 | 720 | __le32 data; |
ac718b69 | 721 | |
c8826de8 | 722 | generic_ocp_read(tp, index, sizeof(data), &data, type); |
ac718b69 | 723 | |
724 | return __le32_to_cpu(data); | |
725 | } | |
726 | ||
727 | static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data) | |
728 | { | |
c8826de8 | 729 | __le32 tmp = __cpu_to_le32(data); |
730 | ||
731 | generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type); | |
ac718b69 | 732 | } |
733 | ||
734 | static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index) | |
735 | { | |
736 | u32 data; | |
c8826de8 | 737 | __le32 tmp; |
ac718b69 | 738 | u8 shift = index & 2; |
739 | ||
740 | index &= ~3; | |
741 | ||
c8826de8 | 742 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 743 | |
c8826de8 | 744 | data = __le32_to_cpu(tmp); |
ac718b69 | 745 | data >>= (shift * 8); |
746 | data &= 0xffff; | |
747 | ||
748 | return (u16)data; | |
749 | } | |
750 | ||
751 | static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data) | |
752 | { | |
c8826de8 | 753 | u32 mask = 0xffff; |
754 | __le32 tmp; | |
ac718b69 | 755 | u16 byen = BYTE_EN_WORD; |
756 | u8 shift = index & 2; | |
757 | ||
758 | data &= mask; | |
759 | ||
760 | if (index & 2) { | |
761 | byen <<= shift; | |
762 | mask <<= (shift * 8); | |
763 | data <<= (shift * 8); | |
764 | index &= ~3; | |
765 | } | |
766 | ||
c8826de8 | 767 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 768 | |
c8826de8 | 769 | data |= __le32_to_cpu(tmp) & ~mask; |
770 | tmp = __cpu_to_le32(data); | |
ac718b69 | 771 | |
c8826de8 | 772 | generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); |
ac718b69 | 773 | } |
774 | ||
775 | static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index) | |
776 | { | |
777 | u32 data; | |
c8826de8 | 778 | __le32 tmp; |
ac718b69 | 779 | u8 shift = index & 3; |
780 | ||
781 | index &= ~3; | |
782 | ||
c8826de8 | 783 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 784 | |
c8826de8 | 785 | data = __le32_to_cpu(tmp); |
ac718b69 | 786 | data >>= (shift * 8); |
787 | data &= 0xff; | |
788 | ||
789 | return (u8)data; | |
790 | } | |
791 | ||
792 | static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data) | |
793 | { | |
c8826de8 | 794 | u32 mask = 0xff; |
795 | __le32 tmp; | |
ac718b69 | 796 | u16 byen = BYTE_EN_BYTE; |
797 | u8 shift = index & 3; | |
798 | ||
799 | data &= mask; | |
800 | ||
801 | if (index & 3) { | |
802 | byen <<= shift; | |
803 | mask <<= (shift * 8); | |
804 | data <<= (shift * 8); | |
805 | index &= ~3; | |
806 | } | |
807 | ||
c8826de8 | 808 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 809 | |
c8826de8 | 810 | data |= __le32_to_cpu(tmp) & ~mask; |
811 | tmp = __cpu_to_le32(data); | |
ac718b69 | 812 | |
c8826de8 | 813 | generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); |
ac718b69 | 814 | } |
815 | ||
ac244d3e | 816 | static u16 ocp_reg_read(struct r8152 *tp, u16 addr) |
e3fe0b1a | 817 | { |
818 | u16 ocp_base, ocp_index; | |
819 | ||
820 | ocp_base = addr & 0xf000; | |
821 | if (ocp_base != tp->ocp_base) { | |
822 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); | |
823 | tp->ocp_base = ocp_base; | |
824 | } | |
825 | ||
826 | ocp_index = (addr & 0x0fff) | 0xb000; | |
ac244d3e | 827 | return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index); |
e3fe0b1a | 828 | } |
829 | ||
ac244d3e | 830 | static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) |
ac718b69 | 831 | { |
ac244d3e | 832 | u16 ocp_base, ocp_index; |
ac718b69 | 833 | |
ac244d3e | 834 | ocp_base = addr & 0xf000; |
835 | if (ocp_base != tp->ocp_base) { | |
836 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); | |
837 | tp->ocp_base = ocp_base; | |
ac718b69 | 838 | } |
ac244d3e | 839 | |
840 | ocp_index = (addr & 0x0fff) | 0xb000; | |
841 | ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data); | |
ac718b69 | 842 | } |
843 | ||
ac244d3e | 844 | static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value) |
ac718b69 | 845 | { |
ac244d3e | 846 | ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value); |
847 | } | |
ac718b69 | 848 | |
ac244d3e | 849 | static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr) |
850 | { | |
851 | return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2); | |
ac718b69 | 852 | } |
853 | ||
43779f8d | 854 | static void sram_write(struct r8152 *tp, u16 addr, u16 data) |
855 | { | |
856 | ocp_reg_write(tp, OCP_SRAM_ADDR, addr); | |
857 | ocp_reg_write(tp, OCP_SRAM_DATA, data); | |
858 | } | |
859 | ||
860 | static u16 sram_read(struct r8152 *tp, u16 addr) | |
861 | { | |
862 | ocp_reg_write(tp, OCP_SRAM_ADDR, addr); | |
863 | return ocp_reg_read(tp, OCP_SRAM_DATA); | |
864 | } | |
865 | ||
ac718b69 | 866 | static int read_mii_word(struct net_device *netdev, int phy_id, int reg) |
867 | { | |
868 | struct r8152 *tp = netdev_priv(netdev); | |
869 | ||
870 | if (phy_id != R8152_PHY_ID) | |
871 | return -EINVAL; | |
872 | ||
873 | return r8152_mdio_read(tp, reg); | |
874 | } | |
875 | ||
876 | static | |
877 | void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val) | |
878 | { | |
879 | struct r8152 *tp = netdev_priv(netdev); | |
880 | ||
881 | if (phy_id != R8152_PHY_ID) | |
882 | return; | |
883 | ||
884 | r8152_mdio_write(tp, reg, val); | |
885 | } | |
886 | ||
ebc2ec48 | 887 | static |
888 | int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags); | |
889 | ||
ac718b69 | 890 | static inline void set_ethernet_addr(struct r8152 *tp) |
891 | { | |
892 | struct net_device *dev = tp->netdev; | |
8a91c824 | 893 | int ret; |
31787f53 | 894 | u8 node_id[8] = {0}; |
ac718b69 | 895 | |
8a91c824 | 896 | if (tp->version == RTL_VER_01) |
897 | ret = pla_ocp_read(tp, PLA_IDR, sizeof(node_id), node_id); | |
898 | else | |
899 | ret = pla_ocp_read(tp, PLA_BACKUP, sizeof(node_id), node_id); | |
900 | ||
901 | if (ret < 0) { | |
ac718b69 | 902 | netif_notice(tp, probe, dev, "inet addr fail\n"); |
8a91c824 | 903 | } else { |
904 | if (tp->version != RTL_VER_01) { | |
905 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, | |
906 | CRWECR_CONFIG); | |
907 | pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, | |
908 | sizeof(node_id), node_id); | |
909 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, | |
910 | CRWECR_NORAML); | |
911 | } | |
912 | ||
ac718b69 | 913 | memcpy(dev->dev_addr, node_id, dev->addr_len); |
914 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); | |
915 | } | |
ac718b69 | 916 | } |
917 | ||
918 | static int rtl8152_set_mac_address(struct net_device *netdev, void *p) | |
919 | { | |
920 | struct r8152 *tp = netdev_priv(netdev); | |
921 | struct sockaddr *addr = p; | |
922 | ||
923 | if (!is_valid_ether_addr(addr->sa_data)) | |
924 | return -EADDRNOTAVAIL; | |
925 | ||
926 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
927 | ||
928 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
929 | pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data); | |
930 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
931 | ||
932 | return 0; | |
933 | } | |
934 | ||
ac718b69 | 935 | static struct net_device_stats *rtl8152_get_stats(struct net_device *dev) |
936 | { | |
937 | return &dev->stats; | |
938 | } | |
939 | ||
940 | static void read_bulk_callback(struct urb *urb) | |
941 | { | |
ac718b69 | 942 | struct net_device *netdev; |
a5a4f468 | 943 | unsigned long flags; |
ac718b69 | 944 | int status = urb->status; |
ebc2ec48 | 945 | struct rx_agg *agg; |
946 | struct r8152 *tp; | |
ac718b69 | 947 | int result; |
ac718b69 | 948 | |
ebc2ec48 | 949 | agg = urb->context; |
950 | if (!agg) | |
951 | return; | |
952 | ||
953 | tp = agg->context; | |
ac718b69 | 954 | if (!tp) |
955 | return; | |
ebc2ec48 | 956 | |
ac718b69 | 957 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
958 | return; | |
ebc2ec48 | 959 | |
960 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
961 | return; | |
962 | ||
ac718b69 | 963 | netdev = tp->netdev; |
7559fb2f | 964 | |
965 | /* When link down, the driver would cancel all bulks. */ | |
966 | /* This avoid the re-submitting bulk */ | |
ebc2ec48 | 967 | if (!netif_carrier_ok(netdev)) |
ac718b69 | 968 | return; |
969 | ||
ac718b69 | 970 | switch (status) { |
971 | case 0: | |
ebc2ec48 | 972 | if (urb->actual_length < ETH_ZLEN) |
973 | break; | |
974 | ||
a5a4f468 | 975 | spin_lock_irqsave(&tp->rx_lock, flags); |
ebc2ec48 | 976 | list_add_tail(&agg->list, &tp->rx_done); |
a5a4f468 | 977 | spin_unlock_irqrestore(&tp->rx_lock, flags); |
ebc2ec48 | 978 | tasklet_schedule(&tp->tl); |
979 | return; | |
ac718b69 | 980 | case -ESHUTDOWN: |
981 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
982 | netif_device_detach(tp->netdev); | |
ebc2ec48 | 983 | return; |
ac718b69 | 984 | case -ENOENT: |
985 | return; /* the urb is in unlink state */ | |
986 | case -ETIME: | |
4a8deae2 HW |
987 | if (net_ratelimit()) |
988 | netdev_warn(netdev, "maybe reset is needed?\n"); | |
ebc2ec48 | 989 | break; |
ac718b69 | 990 | default: |
4a8deae2 HW |
991 | if (net_ratelimit()) |
992 | netdev_warn(netdev, "Rx status %d\n", status); | |
ebc2ec48 | 993 | break; |
ac718b69 | 994 | } |
995 | ||
ebc2ec48 | 996 | result = r8152_submit_rx(tp, agg, GFP_ATOMIC); |
ac718b69 | 997 | if (result == -ENODEV) { |
998 | netif_device_detach(tp->netdev); | |
999 | } else if (result) { | |
a5a4f468 | 1000 | spin_lock_irqsave(&tp->rx_lock, flags); |
ebc2ec48 | 1001 | list_add_tail(&agg->list, &tp->rx_done); |
a5a4f468 | 1002 | spin_unlock_irqrestore(&tp->rx_lock, flags); |
ebc2ec48 | 1003 | tasklet_schedule(&tp->tl); |
ac718b69 | 1004 | } |
ac718b69 | 1005 | } |
1006 | ||
ebc2ec48 | 1007 | static void write_bulk_callback(struct urb *urb) |
ac718b69 | 1008 | { |
ebc2ec48 | 1009 | struct net_device_stats *stats; |
a5a4f468 | 1010 | unsigned long flags; |
ebc2ec48 | 1011 | struct tx_agg *agg; |
ac718b69 | 1012 | struct r8152 *tp; |
ebc2ec48 | 1013 | int status = urb->status; |
ac718b69 | 1014 | |
ebc2ec48 | 1015 | agg = urb->context; |
1016 | if (!agg) | |
ac718b69 | 1017 | return; |
1018 | ||
ebc2ec48 | 1019 | tp = agg->context; |
1020 | if (!tp) | |
1021 | return; | |
1022 | ||
1023 | stats = rtl8152_get_stats(tp->netdev); | |
1024 | if (status) { | |
4a8deae2 HW |
1025 | if (net_ratelimit()) |
1026 | netdev_warn(tp->netdev, "Tx status %d\n", status); | |
ebc2ec48 | 1027 | stats->tx_errors += agg->skb_num; |
ac718b69 | 1028 | } else { |
ebc2ec48 | 1029 | stats->tx_packets += agg->skb_num; |
1030 | stats->tx_bytes += agg->skb_len; | |
ac718b69 | 1031 | } |
1032 | ||
a5a4f468 | 1033 | spin_lock_irqsave(&tp->tx_lock, flags); |
ebc2ec48 | 1034 | list_add_tail(&agg->list, &tp->tx_free); |
a5a4f468 | 1035 | spin_unlock_irqrestore(&tp->tx_lock, flags); |
ebc2ec48 | 1036 | |
1037 | if (!netif_carrier_ok(tp->netdev)) | |
1038 | return; | |
1039 | ||
1040 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
1041 | return; | |
1042 | ||
1043 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
1044 | return; | |
1045 | ||
1046 | if (!skb_queue_empty(&tp->tx_queue)) | |
1047 | tasklet_schedule(&tp->tl); | |
ac718b69 | 1048 | } |
1049 | ||
40a82917 | 1050 | static void intr_callback(struct urb *urb) |
1051 | { | |
1052 | struct r8152 *tp; | |
500b6d7e | 1053 | __le16 *d; |
40a82917 | 1054 | int status = urb->status; |
1055 | int res; | |
1056 | ||
1057 | tp = urb->context; | |
1058 | if (!tp) | |
1059 | return; | |
1060 | ||
1061 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
1062 | return; | |
1063 | ||
1064 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
1065 | return; | |
1066 | ||
1067 | switch (status) { | |
1068 | case 0: /* success */ | |
1069 | break; | |
1070 | case -ECONNRESET: /* unlink */ | |
1071 | case -ESHUTDOWN: | |
1072 | netif_device_detach(tp->netdev); | |
1073 | case -ENOENT: | |
1074 | return; | |
1075 | case -EOVERFLOW: | |
1076 | netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n"); | |
1077 | goto resubmit; | |
1078 | /* -EPIPE: should clear the halt */ | |
1079 | default: | |
1080 | netif_info(tp, intr, tp->netdev, "intr status %d\n", status); | |
1081 | goto resubmit; | |
1082 | } | |
1083 | ||
1084 | d = urb->transfer_buffer; | |
1085 | if (INTR_LINK & __le16_to_cpu(d[0])) { | |
1086 | if (!(tp->speed & LINK_STATUS)) { | |
1087 | set_bit(RTL8152_LINK_CHG, &tp->flags); | |
1088 | schedule_delayed_work(&tp->schedule, 0); | |
1089 | } | |
1090 | } else { | |
1091 | if (tp->speed & LINK_STATUS) { | |
1092 | set_bit(RTL8152_LINK_CHG, &tp->flags); | |
1093 | schedule_delayed_work(&tp->schedule, 0); | |
1094 | } | |
1095 | } | |
1096 | ||
1097 | resubmit: | |
1098 | res = usb_submit_urb(urb, GFP_ATOMIC); | |
1099 | if (res == -ENODEV) | |
1100 | netif_device_detach(tp->netdev); | |
1101 | else if (res) | |
1102 | netif_err(tp, intr, tp->netdev, | |
4a8deae2 | 1103 | "can't resubmit intr, status %d\n", res); |
40a82917 | 1104 | } |
1105 | ||
ebc2ec48 | 1106 | static inline void *rx_agg_align(void *data) |
1107 | { | |
8e1f51bd | 1108 | return (void *)ALIGN((uintptr_t)data, RX_ALIGN); |
ebc2ec48 | 1109 | } |
1110 | ||
1111 | static inline void *tx_agg_align(void *data) | |
1112 | { | |
8e1f51bd | 1113 | return (void *)ALIGN((uintptr_t)data, TX_ALIGN); |
ebc2ec48 | 1114 | } |
1115 | ||
1116 | static void free_all_mem(struct r8152 *tp) | |
1117 | { | |
1118 | int i; | |
1119 | ||
1120 | for (i = 0; i < RTL8152_MAX_RX; i++) { | |
9629e3c0 | 1121 | usb_free_urb(tp->rx_info[i].urb); |
1122 | tp->rx_info[i].urb = NULL; | |
ebc2ec48 | 1123 | |
9629e3c0 | 1124 | kfree(tp->rx_info[i].buffer); |
1125 | tp->rx_info[i].buffer = NULL; | |
1126 | tp->rx_info[i].head = NULL; | |
ebc2ec48 | 1127 | } |
1128 | ||
1129 | for (i = 0; i < RTL8152_MAX_TX; i++) { | |
9629e3c0 | 1130 | usb_free_urb(tp->tx_info[i].urb); |
1131 | tp->tx_info[i].urb = NULL; | |
ebc2ec48 | 1132 | |
9629e3c0 | 1133 | kfree(tp->tx_info[i].buffer); |
1134 | tp->tx_info[i].buffer = NULL; | |
1135 | tp->tx_info[i].head = NULL; | |
ebc2ec48 | 1136 | } |
40a82917 | 1137 | |
9629e3c0 | 1138 | usb_free_urb(tp->intr_urb); |
1139 | tp->intr_urb = NULL; | |
40a82917 | 1140 | |
9629e3c0 | 1141 | kfree(tp->intr_buff); |
1142 | tp->intr_buff = NULL; | |
ebc2ec48 | 1143 | } |
1144 | ||
1145 | static int alloc_all_mem(struct r8152 *tp) | |
1146 | { | |
1147 | struct net_device *netdev = tp->netdev; | |
40a82917 | 1148 | struct usb_interface *intf = tp->intf; |
1149 | struct usb_host_interface *alt = intf->cur_altsetting; | |
1150 | struct usb_host_endpoint *ep_intr = alt->endpoint + 2; | |
ebc2ec48 | 1151 | struct urb *urb; |
1152 | int node, i; | |
1153 | u8 *buf; | |
1154 | ||
1155 | node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; | |
1156 | ||
1157 | spin_lock_init(&tp->rx_lock); | |
1158 | spin_lock_init(&tp->tx_lock); | |
1159 | INIT_LIST_HEAD(&tp->rx_done); | |
1160 | INIT_LIST_HEAD(&tp->tx_free); | |
1161 | skb_queue_head_init(&tp->tx_queue); | |
1162 | ||
1163 | for (i = 0; i < RTL8152_MAX_RX; i++) { | |
1164 | buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node); | |
1165 | if (!buf) | |
1166 | goto err1; | |
1167 | ||
1168 | if (buf != rx_agg_align(buf)) { | |
1169 | kfree(buf); | |
8e1f51bd | 1170 | buf = kmalloc_node(rx_buf_sz + RX_ALIGN, GFP_KERNEL, |
1171 | node); | |
ebc2ec48 | 1172 | if (!buf) |
1173 | goto err1; | |
1174 | } | |
1175 | ||
1176 | urb = usb_alloc_urb(0, GFP_KERNEL); | |
1177 | if (!urb) { | |
1178 | kfree(buf); | |
1179 | goto err1; | |
1180 | } | |
1181 | ||
1182 | INIT_LIST_HEAD(&tp->rx_info[i].list); | |
1183 | tp->rx_info[i].context = tp; | |
1184 | tp->rx_info[i].urb = urb; | |
1185 | tp->rx_info[i].buffer = buf; | |
1186 | tp->rx_info[i].head = rx_agg_align(buf); | |
1187 | } | |
1188 | ||
1189 | for (i = 0; i < RTL8152_MAX_TX; i++) { | |
1190 | buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node); | |
1191 | if (!buf) | |
1192 | goto err1; | |
1193 | ||
1194 | if (buf != tx_agg_align(buf)) { | |
1195 | kfree(buf); | |
8e1f51bd | 1196 | buf = kmalloc_node(rx_buf_sz + TX_ALIGN, GFP_KERNEL, |
1197 | node); | |
ebc2ec48 | 1198 | if (!buf) |
1199 | goto err1; | |
1200 | } | |
1201 | ||
1202 | urb = usb_alloc_urb(0, GFP_KERNEL); | |
1203 | if (!urb) { | |
1204 | kfree(buf); | |
1205 | goto err1; | |
1206 | } | |
1207 | ||
1208 | INIT_LIST_HEAD(&tp->tx_info[i].list); | |
1209 | tp->tx_info[i].context = tp; | |
1210 | tp->tx_info[i].urb = urb; | |
1211 | tp->tx_info[i].buffer = buf; | |
1212 | tp->tx_info[i].head = tx_agg_align(buf); | |
1213 | ||
1214 | list_add_tail(&tp->tx_info[i].list, &tp->tx_free); | |
1215 | } | |
1216 | ||
40a82917 | 1217 | tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL); |
1218 | if (!tp->intr_urb) | |
1219 | goto err1; | |
1220 | ||
1221 | tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL); | |
1222 | if (!tp->intr_buff) | |
1223 | goto err1; | |
1224 | ||
1225 | tp->intr_interval = (int)ep_intr->desc.bInterval; | |
1226 | usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3), | |
1227 | tp->intr_buff, INTBUFSIZE, intr_callback, | |
1228 | tp, tp->intr_interval); | |
1229 | ||
ebc2ec48 | 1230 | return 0; |
1231 | ||
1232 | err1: | |
1233 | free_all_mem(tp); | |
1234 | return -ENOMEM; | |
1235 | } | |
1236 | ||
0de98f6c | 1237 | static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp) |
1238 | { | |
1239 | struct tx_agg *agg = NULL; | |
1240 | unsigned long flags; | |
1241 | ||
1242 | spin_lock_irqsave(&tp->tx_lock, flags); | |
1243 | if (!list_empty(&tp->tx_free)) { | |
1244 | struct list_head *cursor; | |
1245 | ||
1246 | cursor = tp->tx_free.next; | |
1247 | list_del_init(cursor); | |
1248 | agg = list_entry(cursor, struct tx_agg, list); | |
1249 | } | |
1250 | spin_unlock_irqrestore(&tp->tx_lock, flags); | |
1251 | ||
1252 | return agg; | |
1253 | } | |
1254 | ||
5bd23881 | 1255 | static void |
1256 | r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, struct sk_buff *skb) | |
1257 | { | |
1258 | memset(desc, 0, sizeof(*desc)); | |
1259 | ||
1260 | desc->opts1 = cpu_to_le32((skb->len & TX_LEN_MASK) | TX_FS | TX_LS); | |
1261 | ||
1262 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
1263 | __be16 protocol; | |
1264 | u8 ip_protocol; | |
1265 | u32 opts2 = 0; | |
1266 | ||
1267 | if (skb->protocol == htons(ETH_P_8021Q)) | |
1268 | protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto; | |
1269 | else | |
1270 | protocol = skb->protocol; | |
1271 | ||
1272 | switch (protocol) { | |
1273 | case htons(ETH_P_IP): | |
1274 | opts2 |= IPV4_CS; | |
1275 | ip_protocol = ip_hdr(skb)->protocol; | |
1276 | break; | |
1277 | ||
1278 | case htons(ETH_P_IPV6): | |
1279 | opts2 |= IPV6_CS; | |
1280 | ip_protocol = ipv6_hdr(skb)->nexthdr; | |
1281 | break; | |
1282 | ||
1283 | default: | |
1284 | ip_protocol = IPPROTO_RAW; | |
1285 | break; | |
1286 | } | |
1287 | ||
1288 | if (ip_protocol == IPPROTO_TCP) { | |
1289 | opts2 |= TCP_CS; | |
1290 | opts2 |= (skb_transport_offset(skb) & 0x7fff) << 17; | |
1291 | } else if (ip_protocol == IPPROTO_UDP) { | |
1292 | opts2 |= UDP_CS; | |
1293 | } else { | |
1294 | WARN_ON_ONCE(1); | |
1295 | } | |
1296 | ||
1297 | desc->opts2 = cpu_to_le32(opts2); | |
1298 | } | |
1299 | } | |
1300 | ||
b1379d9a | 1301 | static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg) |
1302 | { | |
d84130a1 | 1303 | struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; |
1304 | unsigned long flags; | |
7937f9e5 | 1305 | int remain; |
b1379d9a | 1306 | u8 *tx_data; |
1307 | ||
d84130a1 | 1308 | __skb_queue_head_init(&skb_head); |
1309 | spin_lock_irqsave(&tx_queue->lock, flags); | |
1310 | skb_queue_splice_init(tx_queue, &skb_head); | |
1311 | spin_unlock_irqrestore(&tx_queue->lock, flags); | |
1312 | ||
b1379d9a | 1313 | tx_data = agg->head; |
1314 | agg->skb_num = agg->skb_len = 0; | |
7937f9e5 | 1315 | remain = rx_buf_sz; |
b1379d9a | 1316 | |
7937f9e5 | 1317 | while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) { |
b1379d9a | 1318 | struct tx_desc *tx_desc; |
1319 | struct sk_buff *skb; | |
1320 | unsigned int len; | |
1321 | ||
d84130a1 | 1322 | skb = __skb_dequeue(&skb_head); |
b1379d9a | 1323 | if (!skb) |
1324 | break; | |
1325 | ||
7937f9e5 | 1326 | remain -= sizeof(*tx_desc); |
b1379d9a | 1327 | len = skb->len; |
1328 | if (remain < len) { | |
d84130a1 | 1329 | __skb_queue_head(&skb_head, skb); |
b1379d9a | 1330 | break; |
1331 | } | |
1332 | ||
7937f9e5 | 1333 | tx_data = tx_agg_align(tx_data); |
b1379d9a | 1334 | tx_desc = (struct tx_desc *)tx_data; |
1335 | tx_data += sizeof(*tx_desc); | |
1336 | ||
1337 | r8152_tx_csum(tp, tx_desc, skb); | |
1338 | memcpy(tx_data, skb->data, len); | |
1339 | agg->skb_num++; | |
1340 | agg->skb_len += len; | |
1341 | dev_kfree_skb_any(skb); | |
1342 | ||
7937f9e5 | 1343 | tx_data += len; |
1344 | remain = rx_buf_sz - (int)(tx_agg_align(tx_data) - agg->head); | |
b1379d9a | 1345 | } |
1346 | ||
d84130a1 | 1347 | if (!skb_queue_empty(&skb_head)) { |
1348 | spin_lock_irqsave(&tx_queue->lock, flags); | |
1349 | skb_queue_splice(&skb_head, tx_queue); | |
1350 | spin_unlock_irqrestore(&tx_queue->lock, flags); | |
1351 | } | |
1352 | ||
dd1b119c | 1353 | netif_tx_lock(tp->netdev); |
1354 | ||
1355 | if (netif_queue_stopped(tp->netdev) && | |
1356 | skb_queue_len(&tp->tx_queue) < tp->tx_qlen) | |
1357 | netif_wake_queue(tp->netdev); | |
1358 | ||
1359 | netif_tx_unlock(tp->netdev); | |
1360 | ||
b1379d9a | 1361 | usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2), |
1362 | agg->head, (int)(tx_data - (u8 *)agg->head), | |
1363 | (usb_complete_t)write_bulk_callback, agg); | |
1364 | ||
1365 | return usb_submit_urb(agg->urb, GFP_ATOMIC); | |
1366 | } | |
1367 | ||
ebc2ec48 | 1368 | static void rx_bottom(struct r8152 *tp) |
1369 | { | |
a5a4f468 | 1370 | unsigned long flags; |
d84130a1 | 1371 | struct list_head *cursor, *next, rx_queue; |
ebc2ec48 | 1372 | |
d84130a1 | 1373 | if (list_empty(&tp->rx_done)) |
1374 | return; | |
1375 | ||
1376 | INIT_LIST_HEAD(&rx_queue); | |
a5a4f468 | 1377 | spin_lock_irqsave(&tp->rx_lock, flags); |
d84130a1 | 1378 | list_splice_init(&tp->rx_done, &rx_queue); |
1379 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
1380 | ||
1381 | list_for_each_safe(cursor, next, &rx_queue) { | |
43a4478d | 1382 | struct rx_desc *rx_desc; |
1383 | struct rx_agg *agg; | |
43a4478d | 1384 | int len_used = 0; |
1385 | struct urb *urb; | |
1386 | u8 *rx_data; | |
1387 | int ret; | |
1388 | ||
ebc2ec48 | 1389 | list_del_init(cursor); |
ebc2ec48 | 1390 | |
1391 | agg = list_entry(cursor, struct rx_agg, list); | |
1392 | urb = agg->urb; | |
0de98f6c | 1393 | if (urb->actual_length < ETH_ZLEN) |
1394 | goto submit; | |
ebc2ec48 | 1395 | |
ebc2ec48 | 1396 | rx_desc = agg->head; |
1397 | rx_data = agg->head; | |
7937f9e5 | 1398 | len_used += sizeof(struct rx_desc); |
ebc2ec48 | 1399 | |
7937f9e5 | 1400 | while (urb->actual_length > len_used) { |
43a4478d | 1401 | struct net_device *netdev = tp->netdev; |
1402 | struct net_device_stats *stats; | |
7937f9e5 | 1403 | unsigned int pkt_len; |
43a4478d | 1404 | struct sk_buff *skb; |
1405 | ||
7937f9e5 | 1406 | pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; |
ebc2ec48 | 1407 | if (pkt_len < ETH_ZLEN) |
1408 | break; | |
1409 | ||
7937f9e5 | 1410 | len_used += pkt_len; |
1411 | if (urb->actual_length < len_used) | |
1412 | break; | |
1413 | ||
43a4478d | 1414 | stats = rtl8152_get_stats(netdev); |
1415 | ||
8e1f51bd | 1416 | pkt_len -= CRC_SIZE; |
ebc2ec48 | 1417 | rx_data += sizeof(struct rx_desc); |
1418 | ||
1419 | skb = netdev_alloc_skb_ip_align(netdev, pkt_len); | |
1420 | if (!skb) { | |
1421 | stats->rx_dropped++; | |
1422 | break; | |
1423 | } | |
1424 | memcpy(skb->data, rx_data, pkt_len); | |
1425 | skb_put(skb, pkt_len); | |
1426 | skb->protocol = eth_type_trans(skb, netdev); | |
1427 | netif_rx(skb); | |
1428 | stats->rx_packets++; | |
1429 | stats->rx_bytes += pkt_len; | |
1430 | ||
8e1f51bd | 1431 | rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE); |
ebc2ec48 | 1432 | rx_desc = (struct rx_desc *)rx_data; |
ebc2ec48 | 1433 | len_used = (int)(rx_data - (u8 *)agg->head); |
7937f9e5 | 1434 | len_used += sizeof(struct rx_desc); |
ebc2ec48 | 1435 | } |
1436 | ||
0de98f6c | 1437 | submit: |
ebc2ec48 | 1438 | ret = r8152_submit_rx(tp, agg, GFP_ATOMIC); |
ebc2ec48 | 1439 | if (ret && ret != -ENODEV) { |
d84130a1 | 1440 | spin_lock_irqsave(&tp->rx_lock, flags); |
1441 | list_add_tail(&agg->list, &tp->rx_done); | |
1442 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
ebc2ec48 | 1443 | tasklet_schedule(&tp->tl); |
1444 | } | |
1445 | } | |
ebc2ec48 | 1446 | } |
1447 | ||
1448 | static void tx_bottom(struct r8152 *tp) | |
1449 | { | |
ebc2ec48 | 1450 | int res; |
1451 | ||
b1379d9a | 1452 | do { |
1453 | struct tx_agg *agg; | |
ebc2ec48 | 1454 | |
b1379d9a | 1455 | if (skb_queue_empty(&tp->tx_queue)) |
ebc2ec48 | 1456 | break; |
1457 | ||
b1379d9a | 1458 | agg = r8152_get_tx_agg(tp); |
1459 | if (!agg) | |
ebc2ec48 | 1460 | break; |
ebc2ec48 | 1461 | |
b1379d9a | 1462 | res = r8152_tx_agg_fill(tp, agg); |
1463 | if (res) { | |
1464 | struct net_device_stats *stats; | |
1465 | struct net_device *netdev; | |
1466 | unsigned long flags; | |
ebc2ec48 | 1467 | |
b1379d9a | 1468 | netdev = tp->netdev; |
1469 | stats = rtl8152_get_stats(netdev); | |
ebc2ec48 | 1470 | |
b1379d9a | 1471 | if (res == -ENODEV) { |
1472 | netif_device_detach(netdev); | |
1473 | } else { | |
1474 | netif_warn(tp, tx_err, netdev, | |
1475 | "failed tx_urb %d\n", res); | |
1476 | stats->tx_dropped += agg->skb_num; | |
1477 | spin_lock_irqsave(&tp->tx_lock, flags); | |
1478 | list_add_tail(&agg->list, &tp->tx_free); | |
1479 | spin_unlock_irqrestore(&tp->tx_lock, flags); | |
1480 | } | |
ebc2ec48 | 1481 | } |
b1379d9a | 1482 | } while (res == 0); |
ebc2ec48 | 1483 | } |
1484 | ||
1485 | static void bottom_half(unsigned long data) | |
ac718b69 | 1486 | { |
1487 | struct r8152 *tp; | |
ac718b69 | 1488 | |
ebc2ec48 | 1489 | tp = (struct r8152 *)data; |
1490 | ||
1491 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
1492 | return; | |
1493 | ||
1494 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
ac718b69 | 1495 | return; |
ebc2ec48 | 1496 | |
7559fb2f | 1497 | /* When link down, the driver would cancel all bulks. */ |
1498 | /* This avoid the re-submitting bulk */ | |
ebc2ec48 | 1499 | if (!netif_carrier_ok(tp->netdev)) |
ac718b69 | 1500 | return; |
ebc2ec48 | 1501 | |
1502 | rx_bottom(tp); | |
1503 | tx_bottom(tp); | |
1504 | } | |
1505 | ||
1506 | static | |
1507 | int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags) | |
1508 | { | |
1509 | usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1), | |
1510 | agg->head, rx_buf_sz, | |
1511 | (usb_complete_t)read_bulk_callback, agg); | |
1512 | ||
1513 | return usb_submit_urb(agg->urb, mem_flags); | |
ac718b69 | 1514 | } |
1515 | ||
00a5e360 | 1516 | static void rtl_drop_queued_tx(struct r8152 *tp) |
1517 | { | |
1518 | struct net_device_stats *stats = &tp->netdev->stats; | |
d84130a1 | 1519 | struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; |
1520 | unsigned long flags; | |
00a5e360 | 1521 | struct sk_buff *skb; |
1522 | ||
d84130a1 | 1523 | if (skb_queue_empty(tx_queue)) |
1524 | return; | |
1525 | ||
1526 | __skb_queue_head_init(&skb_head); | |
1527 | spin_lock_irqsave(&tx_queue->lock, flags); | |
1528 | skb_queue_splice_init(tx_queue, &skb_head); | |
1529 | spin_unlock_irqrestore(&tx_queue->lock, flags); | |
1530 | ||
1531 | while ((skb = __skb_dequeue(&skb_head))) { | |
00a5e360 | 1532 | dev_kfree_skb(skb); |
1533 | stats->tx_dropped++; | |
1534 | } | |
1535 | } | |
1536 | ||
ac718b69 | 1537 | static void rtl8152_tx_timeout(struct net_device *netdev) |
1538 | { | |
1539 | struct r8152 *tp = netdev_priv(netdev); | |
ebc2ec48 | 1540 | int i; |
1541 | ||
4a8deae2 | 1542 | netif_warn(tp, tx_err, netdev, "Tx timeout\n"); |
ebc2ec48 | 1543 | for (i = 0; i < RTL8152_MAX_TX; i++) |
1544 | usb_unlink_urb(tp->tx_info[i].urb); | |
ac718b69 | 1545 | } |
1546 | ||
1547 | static void rtl8152_set_rx_mode(struct net_device *netdev) | |
1548 | { | |
1549 | struct r8152 *tp = netdev_priv(netdev); | |
1550 | ||
40a82917 | 1551 | if (tp->speed & LINK_STATUS) { |
ac718b69 | 1552 | set_bit(RTL8152_SET_RX_MODE, &tp->flags); |
40a82917 | 1553 | schedule_delayed_work(&tp->schedule, 0); |
1554 | } | |
ac718b69 | 1555 | } |
1556 | ||
1557 | static void _rtl8152_set_rx_mode(struct net_device *netdev) | |
1558 | { | |
1559 | struct r8152 *tp = netdev_priv(netdev); | |
31787f53 | 1560 | u32 mc_filter[2]; /* Multicast hash filter */ |
1561 | __le32 tmp[2]; | |
ac718b69 | 1562 | u32 ocp_data; |
1563 | ||
ac718b69 | 1564 | clear_bit(RTL8152_SET_RX_MODE, &tp->flags); |
1565 | netif_stop_queue(netdev); | |
1566 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
1567 | ocp_data &= ~RCR_ACPT_ALL; | |
1568 | ocp_data |= RCR_AB | RCR_APM; | |
1569 | ||
1570 | if (netdev->flags & IFF_PROMISC) { | |
1571 | /* Unconditionally log net taps. */ | |
1572 | netif_notice(tp, link, netdev, "Promiscuous mode enabled\n"); | |
1573 | ocp_data |= RCR_AM | RCR_AAP; | |
1574 | mc_filter[1] = mc_filter[0] = 0xffffffff; | |
1575 | } else if ((netdev_mc_count(netdev) > multicast_filter_limit) || | |
1576 | (netdev->flags & IFF_ALLMULTI)) { | |
1577 | /* Too many to filter perfectly -- accept all multicasts. */ | |
1578 | ocp_data |= RCR_AM; | |
1579 | mc_filter[1] = mc_filter[0] = 0xffffffff; | |
1580 | } else { | |
1581 | struct netdev_hw_addr *ha; | |
1582 | ||
1583 | mc_filter[1] = mc_filter[0] = 0; | |
1584 | netdev_for_each_mc_addr(ha, netdev) { | |
1585 | int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; | |
1586 | mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); | |
1587 | ocp_data |= RCR_AM; | |
1588 | } | |
1589 | } | |
1590 | ||
31787f53 | 1591 | tmp[0] = __cpu_to_le32(swab32(mc_filter[1])); |
1592 | tmp[1] = __cpu_to_le32(swab32(mc_filter[0])); | |
ac718b69 | 1593 | |
31787f53 | 1594 | pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp); |
ac718b69 | 1595 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); |
1596 | netif_wake_queue(netdev); | |
ac718b69 | 1597 | } |
1598 | ||
1599 | static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb, | |
1600 | struct net_device *netdev) | |
1601 | { | |
1602 | struct r8152 *tp = netdev_priv(netdev); | |
ac718b69 | 1603 | |
ebc2ec48 | 1604 | skb_tx_timestamp(skb); |
ac718b69 | 1605 | |
61598788 | 1606 | skb_queue_tail(&tp->tx_queue, skb); |
ebc2ec48 | 1607 | |
dd1b119c | 1608 | if (list_empty(&tp->tx_free) && |
1609 | skb_queue_len(&tp->tx_queue) > tp->tx_qlen) | |
1610 | netif_stop_queue(netdev); | |
1611 | ||
61598788 | 1612 | if (!list_empty(&tp->tx_free)) |
1613 | tasklet_schedule(&tp->tl); | |
ac718b69 | 1614 | |
1615 | return NETDEV_TX_OK; | |
1616 | } | |
1617 | ||
1618 | static void r8152b_reset_packet_filter(struct r8152 *tp) | |
1619 | { | |
1620 | u32 ocp_data; | |
1621 | ||
1622 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); | |
1623 | ocp_data &= ~FMC_FCR_MCU_EN; | |
1624 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); | |
1625 | ocp_data |= FMC_FCR_MCU_EN; | |
1626 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); | |
1627 | } | |
1628 | ||
1629 | static void rtl8152_nic_reset(struct r8152 *tp) | |
1630 | { | |
1631 | int i; | |
1632 | ||
1633 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST); | |
1634 | ||
1635 | for (i = 0; i < 1000; i++) { | |
1636 | if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST)) | |
1637 | break; | |
1638 | udelay(100); | |
1639 | } | |
1640 | } | |
1641 | ||
dd1b119c | 1642 | static void set_tx_qlen(struct r8152 *tp) |
1643 | { | |
1644 | struct net_device *netdev = tp->netdev; | |
1645 | ||
1646 | tp->tx_qlen = rx_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN + | |
1647 | sizeof(struct tx_desc)); | |
1648 | } | |
1649 | ||
ac718b69 | 1650 | static inline u8 rtl8152_get_speed(struct r8152 *tp) |
1651 | { | |
1652 | return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); | |
1653 | } | |
1654 | ||
507605a8 | 1655 | static void rtl_set_eee_plus(struct r8152 *tp) |
ac718b69 | 1656 | { |
ebc2ec48 | 1657 | u32 ocp_data; |
ac718b69 | 1658 | u8 speed; |
1659 | ||
1660 | speed = rtl8152_get_speed(tp); | |
ebc2ec48 | 1661 | if (speed & _10bps) { |
ac718b69 | 1662 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); |
ebc2ec48 | 1663 | ocp_data |= EEEP_CR_EEEP_TX; |
ac718b69 | 1664 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); |
1665 | } else { | |
1666 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); | |
ebc2ec48 | 1667 | ocp_data &= ~EEEP_CR_EEEP_TX; |
ac718b69 | 1668 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); |
1669 | } | |
507605a8 | 1670 | } |
1671 | ||
00a5e360 | 1672 | static void rxdy_gated_en(struct r8152 *tp, bool enable) |
1673 | { | |
1674 | u32 ocp_data; | |
1675 | ||
1676 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); | |
1677 | if (enable) | |
1678 | ocp_data |= RXDY_GATED_EN; | |
1679 | else | |
1680 | ocp_data &= ~RXDY_GATED_EN; | |
1681 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); | |
1682 | } | |
1683 | ||
507605a8 | 1684 | static int rtl_enable(struct r8152 *tp) |
1685 | { | |
1686 | u32 ocp_data; | |
1687 | int i, ret; | |
ac718b69 | 1688 | |
1689 | r8152b_reset_packet_filter(tp); | |
1690 | ||
1691 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); | |
1692 | ocp_data |= CR_RE | CR_TE; | |
1693 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); | |
1694 | ||
00a5e360 | 1695 | rxdy_gated_en(tp, false); |
ac718b69 | 1696 | |
ebc2ec48 | 1697 | INIT_LIST_HEAD(&tp->rx_done); |
1698 | ret = 0; | |
1699 | for (i = 0; i < RTL8152_MAX_RX; i++) { | |
1700 | INIT_LIST_HEAD(&tp->rx_info[i].list); | |
1701 | ret |= r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL); | |
1702 | } | |
ac718b69 | 1703 | |
ebc2ec48 | 1704 | return ret; |
ac718b69 | 1705 | } |
1706 | ||
507605a8 | 1707 | static int rtl8152_enable(struct r8152 *tp) |
1708 | { | |
1709 | set_tx_qlen(tp); | |
1710 | rtl_set_eee_plus(tp); | |
1711 | ||
1712 | return rtl_enable(tp); | |
1713 | } | |
1714 | ||
43779f8d | 1715 | static void r8153_set_rx_agg(struct r8152 *tp) |
1716 | { | |
1717 | u8 speed; | |
1718 | ||
1719 | speed = rtl8152_get_speed(tp); | |
1720 | if (speed & _1000bps) { | |
1721 | if (tp->udev->speed == USB_SPEED_SUPER) { | |
1722 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, | |
1723 | RX_THR_SUPPER); | |
1724 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG, | |
1725 | EARLY_AGG_SUPPER); | |
1726 | } else { | |
1727 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, | |
1728 | RX_THR_HIGH); | |
1729 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG, | |
1730 | EARLY_AGG_HIGH); | |
1731 | } | |
1732 | } else { | |
1733 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_SLOW); | |
1734 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG, | |
1735 | EARLY_AGG_SLOW); | |
1736 | } | |
1737 | } | |
1738 | ||
1739 | static int rtl8153_enable(struct r8152 *tp) | |
1740 | { | |
1741 | set_tx_qlen(tp); | |
1742 | rtl_set_eee_plus(tp); | |
1743 | r8153_set_rx_agg(tp); | |
1744 | ||
1745 | return rtl_enable(tp); | |
1746 | } | |
1747 | ||
ac718b69 | 1748 | static void rtl8152_disable(struct r8152 *tp) |
1749 | { | |
ebc2ec48 | 1750 | u32 ocp_data; |
1751 | int i; | |
ac718b69 | 1752 | |
1753 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
1754 | ocp_data &= ~RCR_ACPT_ALL; | |
1755 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
1756 | ||
00a5e360 | 1757 | rtl_drop_queued_tx(tp); |
ebc2ec48 | 1758 | |
1759 | for (i = 0; i < RTL8152_MAX_TX; i++) | |
1760 | usb_kill_urb(tp->tx_info[i].urb); | |
ac718b69 | 1761 | |
00a5e360 | 1762 | rxdy_gated_en(tp, true); |
ac718b69 | 1763 | |
1764 | for (i = 0; i < 1000; i++) { | |
1765 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
1766 | if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY) | |
1767 | break; | |
1768 | mdelay(1); | |
1769 | } | |
1770 | ||
1771 | for (i = 0; i < 1000; i++) { | |
1772 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY) | |
1773 | break; | |
1774 | mdelay(1); | |
1775 | } | |
1776 | ||
ebc2ec48 | 1777 | for (i = 0; i < RTL8152_MAX_RX; i++) |
1778 | usb_kill_urb(tp->rx_info[i].urb); | |
ac718b69 | 1779 | |
1780 | rtl8152_nic_reset(tp); | |
1781 | } | |
1782 | ||
00a5e360 | 1783 | static void r8152_power_cut_en(struct r8152 *tp, bool enable) |
1784 | { | |
1785 | u32 ocp_data; | |
1786 | ||
1787 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); | |
1788 | if (enable) | |
1789 | ocp_data |= POWER_CUT; | |
1790 | else | |
1791 | ocp_data &= ~POWER_CUT; | |
1792 | ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); | |
1793 | ||
1794 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); | |
1795 | ocp_data &= ~RESUME_INDICATE; | |
1796 | ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); | |
1797 | ||
1798 | } | |
1799 | ||
aa66a5f1 | 1800 | static void rtl_phy_reset(struct r8152 *tp) |
1801 | { | |
1802 | u16 data; | |
1803 | int i; | |
1804 | ||
1805 | clear_bit(PHY_RESET, &tp->flags); | |
1806 | ||
1807 | data = r8152_mdio_read(tp, MII_BMCR); | |
1808 | ||
1809 | /* don't reset again before the previous one complete */ | |
1810 | if (data & BMCR_RESET) | |
1811 | return; | |
1812 | ||
1813 | data |= BMCR_RESET; | |
1814 | r8152_mdio_write(tp, MII_BMCR, data); | |
1815 | ||
1816 | for (i = 0; i < 50; i++) { | |
1817 | msleep(20); | |
1818 | if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) | |
1819 | break; | |
1820 | } | |
1821 | } | |
1822 | ||
4349968a | 1823 | static void rtl_clear_bp(struct r8152 *tp) |
1824 | { | |
1825 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_0, 0); | |
1826 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_2, 0); | |
1827 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_4, 0); | |
1828 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_6, 0); | |
1829 | ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_0, 0); | |
1830 | ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_2, 0); | |
1831 | ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_4, 0); | |
1832 | ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_6, 0); | |
1833 | mdelay(3); | |
1834 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_BA, 0); | |
1835 | ocp_write_word(tp, MCU_TYPE_USB, USB_BP_BA, 0); | |
1836 | } | |
1837 | ||
1838 | static void r8153_clear_bp(struct r8152 *tp) | |
1839 | { | |
1840 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_BP_EN, 0); | |
1841 | ocp_write_byte(tp, MCU_TYPE_USB, USB_BP_EN, 0); | |
1842 | rtl_clear_bp(tp); | |
1843 | } | |
1844 | ||
1845 | static void r8153_teredo_off(struct r8152 *tp) | |
1846 | { | |
1847 | u32 ocp_data; | |
1848 | ||
1849 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); | |
1850 | ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN); | |
1851 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); | |
1852 | ||
1853 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE); | |
1854 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0); | |
1855 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0); | |
1856 | } | |
1857 | ||
1858 | static void r8152b_disable_aldps(struct r8152 *tp) | |
1859 | { | |
1860 | ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE); | |
1861 | msleep(20); | |
1862 | } | |
1863 | ||
1864 | static inline void r8152b_enable_aldps(struct r8152 *tp) | |
1865 | { | |
1866 | ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS | | |
1867 | LINKENA | DIS_SDSAVE); | |
1868 | } | |
1869 | ||
1870 | static void r8152b_hw_phy_cfg(struct r8152 *tp) | |
1871 | { | |
f0cbe0ac | 1872 | u16 data; |
1873 | ||
1874 | data = r8152_mdio_read(tp, MII_BMCR); | |
1875 | if (data & BMCR_PDOWN) { | |
1876 | data &= ~BMCR_PDOWN; | |
1877 | r8152_mdio_write(tp, MII_BMCR, data); | |
1878 | } | |
1879 | ||
4349968a | 1880 | r8152b_disable_aldps(tp); |
aa66a5f1 | 1881 | set_bit(PHY_RESET, &tp->flags); |
4349968a | 1882 | } |
1883 | ||
ac718b69 | 1884 | static void r8152b_exit_oob(struct r8152 *tp) |
1885 | { | |
1886 | u32 ocp_data; | |
1887 | int i; | |
1888 | ||
1889 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
1890 | ocp_data &= ~RCR_ACPT_ALL; | |
1891 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
1892 | ||
00a5e360 | 1893 | rxdy_gated_en(tp, true); |
ac718b69 | 1894 | |
1895 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
1896 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); | |
1897 | ||
1898 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
1899 | ocp_data &= ~NOW_IS_OOB; | |
1900 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
1901 | ||
1902 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
1903 | ocp_data &= ~MCU_BORW_EN; | |
1904 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
1905 | ||
1906 | for (i = 0; i < 1000; i++) { | |
1907 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
1908 | if (ocp_data & LINK_LIST_READY) | |
1909 | break; | |
1910 | mdelay(1); | |
1911 | } | |
1912 | ||
1913 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
1914 | ocp_data |= RE_INIT_LL; | |
1915 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
1916 | ||
1917 | for (i = 0; i < 1000; i++) { | |
1918 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
1919 | if (ocp_data & LINK_LIST_READY) | |
1920 | break; | |
1921 | mdelay(1); | |
1922 | } | |
1923 | ||
1924 | rtl8152_nic_reset(tp); | |
1925 | ||
1926 | /* rx share fifo credit full threshold */ | |
1927 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); | |
1928 | ||
1929 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_DEV_STAT); | |
1930 | ocp_data &= STAT_SPEED_MASK; | |
1931 | if (ocp_data == STAT_SPEED_FULL) { | |
1932 | /* rx share fifo credit near full threshold */ | |
1933 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, | |
1934 | RXFIFO_THR2_FULL); | |
1935 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, | |
1936 | RXFIFO_THR3_FULL); | |
1937 | } else { | |
1938 | /* rx share fifo credit near full threshold */ | |
1939 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, | |
1940 | RXFIFO_THR2_HIGH); | |
1941 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, | |
1942 | RXFIFO_THR3_HIGH); | |
1943 | } | |
1944 | ||
1945 | /* TX share fifo free credit full threshold */ | |
1946 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL); | |
1947 | ||
1948 | ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD); | |
8e1f51bd | 1949 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH); |
ac718b69 | 1950 | ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA, |
1951 | TEST_MODE_DISABLE | TX_SIZE_ADJUST1); | |
1952 | ||
1953 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); | |
1954 | ocp_data &= ~CPCR_RX_VLAN; | |
1955 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); | |
1956 | ||
1957 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); | |
1958 | ||
1959 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); | |
1960 | ocp_data |= TCR0_AUTO_FIFO; | |
1961 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); | |
1962 | } | |
1963 | ||
1964 | static void r8152b_enter_oob(struct r8152 *tp) | |
1965 | { | |
45f4a19f | 1966 | u32 ocp_data; |
1967 | int i; | |
ac718b69 | 1968 | |
1969 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
1970 | ocp_data &= ~NOW_IS_OOB; | |
1971 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
1972 | ||
1973 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); | |
1974 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); | |
1975 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB); | |
1976 | ||
1977 | rtl8152_disable(tp); | |
1978 | ||
1979 | for (i = 0; i < 1000; i++) { | |
1980 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
1981 | if (ocp_data & LINK_LIST_READY) | |
1982 | break; | |
1983 | mdelay(1); | |
1984 | } | |
1985 | ||
1986 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
1987 | ocp_data |= RE_INIT_LL; | |
1988 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
1989 | ||
1990 | for (i = 0; i < 1000; i++) { | |
1991 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
1992 | if (ocp_data & LINK_LIST_READY) | |
1993 | break; | |
1994 | mdelay(1); | |
1995 | } | |
1996 | ||
1997 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); | |
1998 | ||
1999 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); | |
2000 | ocp_data |= MAGIC_EN; | |
2001 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data); | |
2002 | ||
2003 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); | |
2004 | ocp_data |= CPCR_RX_VLAN; | |
2005 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); | |
2006 | ||
2007 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); | |
2008 | ocp_data |= ALDPS_PROXY_MODE; | |
2009 | ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); | |
2010 | ||
2011 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2012 | ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; | |
2013 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2014 | ||
2015 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5, LAN_WAKE_EN); | |
2016 | ||
00a5e360 | 2017 | rxdy_gated_en(tp, false); |
ac718b69 | 2018 | |
2019 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2020 | ocp_data |= RCR_APM | RCR_AM | RCR_AB; | |
2021 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2022 | } | |
2023 | ||
43779f8d | 2024 | static void r8153_hw_phy_cfg(struct r8152 *tp) |
2025 | { | |
2026 | u32 ocp_data; | |
2027 | u16 data; | |
2028 | ||
2029 | ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L); | |
f0cbe0ac | 2030 | data = r8152_mdio_read(tp, MII_BMCR); |
2031 | if (data & BMCR_PDOWN) { | |
2032 | data &= ~BMCR_PDOWN; | |
2033 | r8152_mdio_write(tp, MII_BMCR, data); | |
2034 | } | |
43779f8d | 2035 | |
2036 | if (tp->version == RTL_VER_03) { | |
2037 | data = ocp_reg_read(tp, OCP_EEE_CFG); | |
2038 | data &= ~CTAP_SHORT_EN; | |
2039 | ocp_reg_write(tp, OCP_EEE_CFG, data); | |
2040 | } | |
2041 | ||
2042 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
2043 | data |= EEE_CLKDIV_EN; | |
2044 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
2045 | ||
2046 | data = ocp_reg_read(tp, OCP_DOWN_SPEED); | |
2047 | data |= EN_10M_BGOFF; | |
2048 | ocp_reg_write(tp, OCP_DOWN_SPEED, data); | |
2049 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
2050 | data |= EN_10M_PLLOFF; | |
2051 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
2052 | data = sram_read(tp, SRAM_IMPEDANCE); | |
2053 | data &= ~RX_DRIVING_MASK; | |
2054 | sram_write(tp, SRAM_IMPEDANCE, data); | |
2055 | ||
2056 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); | |
2057 | ocp_data |= PFM_PWM_SWITCH; | |
2058 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); | |
2059 | ||
2060 | data = sram_read(tp, SRAM_LPF_CFG); | |
2061 | data |= LPF_AUTO_TUNE; | |
2062 | sram_write(tp, SRAM_LPF_CFG, data); | |
2063 | ||
2064 | data = sram_read(tp, SRAM_10M_AMP1); | |
2065 | data |= GDAC_IB_UPALL; | |
2066 | sram_write(tp, SRAM_10M_AMP1, data); | |
2067 | data = sram_read(tp, SRAM_10M_AMP2); | |
2068 | data |= AMP_DN; | |
2069 | sram_write(tp, SRAM_10M_AMP2, data); | |
aa66a5f1 | 2070 | |
2071 | set_bit(PHY_RESET, &tp->flags); | |
43779f8d | 2072 | } |
2073 | ||
b9702723 | 2074 | static void r8153_u1u2en(struct r8152 *tp, bool enable) |
43779f8d | 2075 | { |
2076 | u8 u1u2[8]; | |
2077 | ||
2078 | if (enable) | |
2079 | memset(u1u2, 0xff, sizeof(u1u2)); | |
2080 | else | |
2081 | memset(u1u2, 0x00, sizeof(u1u2)); | |
2082 | ||
2083 | usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2); | |
2084 | } | |
2085 | ||
b9702723 | 2086 | static void r8153_u2p3en(struct r8152 *tp, bool enable) |
43779f8d | 2087 | { |
2088 | u32 ocp_data; | |
2089 | ||
2090 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); | |
2091 | if (enable) | |
2092 | ocp_data |= U2P3_ENABLE; | |
2093 | else | |
2094 | ocp_data &= ~U2P3_ENABLE; | |
2095 | ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); | |
2096 | } | |
2097 | ||
b9702723 | 2098 | static void r8153_power_cut_en(struct r8152 *tp, bool enable) |
43779f8d | 2099 | { |
2100 | u32 ocp_data; | |
2101 | ||
2102 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); | |
2103 | if (enable) | |
2104 | ocp_data |= PWR_EN | PHASE2_EN; | |
2105 | else | |
2106 | ocp_data &= ~(PWR_EN | PHASE2_EN); | |
2107 | ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); | |
2108 | ||
2109 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); | |
2110 | ocp_data &= ~PCUT_STATUS; | |
2111 | ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); | |
2112 | } | |
2113 | ||
43779f8d | 2114 | static void r8153_first_init(struct r8152 *tp) |
2115 | { | |
2116 | u32 ocp_data; | |
2117 | int i; | |
2118 | ||
00a5e360 | 2119 | rxdy_gated_en(tp, true); |
43779f8d | 2120 | r8153_teredo_off(tp); |
2121 | ||
2122 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2123 | ocp_data &= ~RCR_ACPT_ALL; | |
2124 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2125 | ||
2126 | r8153_hw_phy_cfg(tp); | |
2127 | ||
2128 | rtl8152_nic_reset(tp); | |
2129 | ||
2130 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2131 | ocp_data &= ~NOW_IS_OOB; | |
2132 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2133 | ||
2134 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2135 | ocp_data &= ~MCU_BORW_EN; | |
2136 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2137 | ||
2138 | for (i = 0; i < 1000; i++) { | |
2139 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2140 | if (ocp_data & LINK_LIST_READY) | |
2141 | break; | |
2142 | mdelay(1); | |
2143 | } | |
2144 | ||
2145 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2146 | ocp_data |= RE_INIT_LL; | |
2147 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2148 | ||
2149 | for (i = 0; i < 1000; i++) { | |
2150 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2151 | if (ocp_data & LINK_LIST_READY) | |
2152 | break; | |
2153 | mdelay(1); | |
2154 | } | |
2155 | ||
2156 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); | |
2157 | ocp_data &= ~CPCR_RX_VLAN; | |
2158 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); | |
2159 | ||
2160 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); | |
2161 | ||
2162 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); | |
2163 | ocp_data |= TCR0_AUTO_FIFO; | |
2164 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); | |
2165 | ||
2166 | rtl8152_nic_reset(tp); | |
2167 | ||
2168 | /* rx share fifo credit full threshold */ | |
2169 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); | |
2170 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL); | |
2171 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL); | |
2172 | /* TX share fifo free credit full threshold */ | |
2173 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2); | |
2174 | ||
9629e3c0 | 2175 | /* rx aggregation */ |
43779f8d | 2176 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); |
2177 | ocp_data &= ~RX_AGG_DISABLE; | |
2178 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); | |
2179 | } | |
2180 | ||
2181 | static void r8153_enter_oob(struct r8152 *tp) | |
2182 | { | |
2183 | u32 ocp_data; | |
2184 | int i; | |
2185 | ||
2186 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2187 | ocp_data &= ~NOW_IS_OOB; | |
2188 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2189 | ||
2190 | rtl8152_disable(tp); | |
2191 | ||
2192 | for (i = 0; i < 1000; i++) { | |
2193 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2194 | if (ocp_data & LINK_LIST_READY) | |
2195 | break; | |
2196 | mdelay(1); | |
2197 | } | |
2198 | ||
2199 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2200 | ocp_data |= RE_INIT_LL; | |
2201 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2202 | ||
2203 | for (i = 0; i < 1000; i++) { | |
2204 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2205 | if (ocp_data & LINK_LIST_READY) | |
2206 | break; | |
2207 | mdelay(1); | |
2208 | } | |
2209 | ||
2210 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); | |
2211 | ||
2212 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); | |
2213 | ocp_data |= MAGIC_EN; | |
2214 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data); | |
2215 | ||
2216 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); | |
2217 | ocp_data &= ~TEREDO_WAKE_MASK; | |
2218 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); | |
2219 | ||
2220 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); | |
2221 | ocp_data |= CPCR_RX_VLAN; | |
2222 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); | |
2223 | ||
2224 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); | |
2225 | ocp_data |= ALDPS_PROXY_MODE; | |
2226 | ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); | |
2227 | ||
2228 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2229 | ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; | |
2230 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2231 | ||
2232 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5, LAN_WAKE_EN); | |
2233 | ||
00a5e360 | 2234 | rxdy_gated_en(tp, false); |
43779f8d | 2235 | |
2236 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2237 | ocp_data |= RCR_APM | RCR_AM | RCR_AB; | |
2238 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2239 | } | |
2240 | ||
2241 | static void r8153_disable_aldps(struct r8152 *tp) | |
2242 | { | |
2243 | u16 data; | |
2244 | ||
2245 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
2246 | data &= ~EN_ALDPS; | |
2247 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
2248 | msleep(20); | |
2249 | } | |
2250 | ||
2251 | static void r8153_enable_aldps(struct r8152 *tp) | |
2252 | { | |
2253 | u16 data; | |
2254 | ||
2255 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
2256 | data |= EN_ALDPS; | |
2257 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
2258 | } | |
2259 | ||
ac718b69 | 2260 | static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex) |
2261 | { | |
43779f8d | 2262 | u16 bmcr, anar, gbcr; |
ac718b69 | 2263 | int ret = 0; |
2264 | ||
2265 | cancel_delayed_work_sync(&tp->schedule); | |
2266 | anar = r8152_mdio_read(tp, MII_ADVERTISE); | |
2267 | anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | | |
2268 | ADVERTISE_100HALF | ADVERTISE_100FULL); | |
43779f8d | 2269 | if (tp->mii.supports_gmii) { |
2270 | gbcr = r8152_mdio_read(tp, MII_CTRL1000); | |
2271 | gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); | |
2272 | } else { | |
2273 | gbcr = 0; | |
2274 | } | |
ac718b69 | 2275 | |
2276 | if (autoneg == AUTONEG_DISABLE) { | |
2277 | if (speed == SPEED_10) { | |
2278 | bmcr = 0; | |
2279 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
2280 | } else if (speed == SPEED_100) { | |
2281 | bmcr = BMCR_SPEED100; | |
2282 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; | |
43779f8d | 2283 | } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { |
2284 | bmcr = BMCR_SPEED1000; | |
2285 | gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; | |
ac718b69 | 2286 | } else { |
2287 | ret = -EINVAL; | |
2288 | goto out; | |
2289 | } | |
2290 | ||
2291 | if (duplex == DUPLEX_FULL) | |
2292 | bmcr |= BMCR_FULLDPLX; | |
2293 | } else { | |
2294 | if (speed == SPEED_10) { | |
2295 | if (duplex == DUPLEX_FULL) | |
2296 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
2297 | else | |
2298 | anar |= ADVERTISE_10HALF; | |
2299 | } else if (speed == SPEED_100) { | |
2300 | if (duplex == DUPLEX_FULL) { | |
2301 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
2302 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; | |
2303 | } else { | |
2304 | anar |= ADVERTISE_10HALF; | |
2305 | anar |= ADVERTISE_100HALF; | |
2306 | } | |
43779f8d | 2307 | } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { |
2308 | if (duplex == DUPLEX_FULL) { | |
2309 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
2310 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; | |
2311 | gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; | |
2312 | } else { | |
2313 | anar |= ADVERTISE_10HALF; | |
2314 | anar |= ADVERTISE_100HALF; | |
2315 | gbcr |= ADVERTISE_1000HALF; | |
2316 | } | |
ac718b69 | 2317 | } else { |
2318 | ret = -EINVAL; | |
2319 | goto out; | |
2320 | } | |
2321 | ||
2322 | bmcr = BMCR_ANENABLE | BMCR_ANRESTART; | |
2323 | } | |
2324 | ||
aa66a5f1 | 2325 | if (test_bit(PHY_RESET, &tp->flags)) |
2326 | bmcr |= BMCR_RESET; | |
2327 | ||
43779f8d | 2328 | if (tp->mii.supports_gmii) |
2329 | r8152_mdio_write(tp, MII_CTRL1000, gbcr); | |
2330 | ||
ac718b69 | 2331 | r8152_mdio_write(tp, MII_ADVERTISE, anar); |
2332 | r8152_mdio_write(tp, MII_BMCR, bmcr); | |
2333 | ||
aa66a5f1 | 2334 | if (test_bit(PHY_RESET, &tp->flags)) { |
2335 | int i; | |
2336 | ||
2337 | clear_bit(PHY_RESET, &tp->flags); | |
2338 | for (i = 0; i < 50; i++) { | |
2339 | msleep(20); | |
2340 | if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) | |
2341 | break; | |
2342 | } | |
2343 | } | |
2344 | ||
ac718b69 | 2345 | out: |
ac718b69 | 2346 | |
2347 | return ret; | |
2348 | } | |
2349 | ||
2350 | static void rtl8152_down(struct r8152 *tp) | |
2351 | { | |
00a5e360 | 2352 | r8152_power_cut_en(tp, false); |
ac718b69 | 2353 | r8152b_disable_aldps(tp); |
2354 | r8152b_enter_oob(tp); | |
2355 | r8152b_enable_aldps(tp); | |
2356 | } | |
2357 | ||
43779f8d | 2358 | static void rtl8153_down(struct r8152 *tp) |
2359 | { | |
b9702723 | 2360 | r8153_u1u2en(tp, false); |
2361 | r8153_power_cut_en(tp, false); | |
43779f8d | 2362 | r8153_disable_aldps(tp); |
2363 | r8153_enter_oob(tp); | |
2364 | r8153_enable_aldps(tp); | |
2365 | } | |
2366 | ||
ac718b69 | 2367 | static void set_carrier(struct r8152 *tp) |
2368 | { | |
2369 | struct net_device *netdev = tp->netdev; | |
2370 | u8 speed; | |
2371 | ||
40a82917 | 2372 | clear_bit(RTL8152_LINK_CHG, &tp->flags); |
ac718b69 | 2373 | speed = rtl8152_get_speed(tp); |
2374 | ||
2375 | if (speed & LINK_STATUS) { | |
2376 | if (!(tp->speed & LINK_STATUS)) { | |
c81229c9 | 2377 | tp->rtl_ops.enable(tp); |
ac718b69 | 2378 | set_bit(RTL8152_SET_RX_MODE, &tp->flags); |
2379 | netif_carrier_on(netdev); | |
2380 | } | |
2381 | } else { | |
2382 | if (tp->speed & LINK_STATUS) { | |
2383 | netif_carrier_off(netdev); | |
ebc2ec48 | 2384 | tasklet_disable(&tp->tl); |
c81229c9 | 2385 | tp->rtl_ops.disable(tp); |
ebc2ec48 | 2386 | tasklet_enable(&tp->tl); |
ac718b69 | 2387 | } |
2388 | } | |
2389 | tp->speed = speed; | |
2390 | } | |
2391 | ||
2392 | static void rtl_work_func_t(struct work_struct *work) | |
2393 | { | |
2394 | struct r8152 *tp = container_of(work, struct r8152, schedule.work); | |
2395 | ||
2396 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
2397 | goto out1; | |
2398 | ||
2399 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
2400 | goto out1; | |
2401 | ||
40a82917 | 2402 | if (test_bit(RTL8152_LINK_CHG, &tp->flags)) |
2403 | set_carrier(tp); | |
ac718b69 | 2404 | |
2405 | if (test_bit(RTL8152_SET_RX_MODE, &tp->flags)) | |
2406 | _rtl8152_set_rx_mode(tp->netdev); | |
2407 | ||
aa66a5f1 | 2408 | |
2409 | if (test_bit(PHY_RESET, &tp->flags)) | |
2410 | rtl_phy_reset(tp); | |
2411 | ||
ac718b69 | 2412 | out1: |
2413 | return; | |
2414 | } | |
2415 | ||
2416 | static int rtl8152_open(struct net_device *netdev) | |
2417 | { | |
2418 | struct r8152 *tp = netdev_priv(netdev); | |
2419 | int res = 0; | |
2420 | ||
3d55f44f | 2421 | rtl8152_set_speed(tp, AUTONEG_ENABLE, |
2422 | tp->mii.supports_gmii ? SPEED_1000 : SPEED_100, | |
2423 | DUPLEX_FULL); | |
2424 | tp->speed = 0; | |
2425 | netif_carrier_off(netdev); | |
2426 | netif_start_queue(netdev); | |
2427 | set_bit(WORK_ENABLE, &tp->flags); | |
40a82917 | 2428 | res = usb_submit_urb(tp->intr_urb, GFP_KERNEL); |
2429 | if (res) { | |
2430 | if (res == -ENODEV) | |
2431 | netif_device_detach(tp->netdev); | |
4a8deae2 HW |
2432 | netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n", |
2433 | res); | |
ac718b69 | 2434 | } |
2435 | ||
ac718b69 | 2436 | |
2437 | return res; | |
2438 | } | |
2439 | ||
2440 | static int rtl8152_close(struct net_device *netdev) | |
2441 | { | |
2442 | struct r8152 *tp = netdev_priv(netdev); | |
2443 | int res = 0; | |
2444 | ||
2445 | clear_bit(WORK_ENABLE, &tp->flags); | |
3d55f44f | 2446 | usb_kill_urb(tp->intr_urb); |
ac718b69 | 2447 | cancel_delayed_work_sync(&tp->schedule); |
2448 | netif_stop_queue(netdev); | |
ebc2ec48 | 2449 | tasklet_disable(&tp->tl); |
c81229c9 | 2450 | tp->rtl_ops.disable(tp); |
ebc2ec48 | 2451 | tasklet_enable(&tp->tl); |
ac718b69 | 2452 | |
2453 | return res; | |
2454 | } | |
2455 | ||
ac718b69 | 2456 | static void r8152b_enable_eee(struct r8152 *tp) |
2457 | { | |
45f4a19f | 2458 | u32 ocp_data; |
ac718b69 | 2459 | |
2460 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); | |
2461 | ocp_data |= EEE_RX_EN | EEE_TX_EN; | |
2462 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); | |
2463 | ocp_reg_write(tp, OCP_EEE_CONFIG1, RG_TXLPI_MSK_HFDUP | RG_MATCLR_EN | | |
2464 | EEE_10_CAP | EEE_NWAY_EN | | |
2465 | TX_QUIET_EN | RX_QUIET_EN | | |
2466 | SDRISETIME | RG_RXLPI_MSK_HFDUP | | |
2467 | SDFALLTIME); | |
2468 | ocp_reg_write(tp, OCP_EEE_CONFIG2, RG_LPIHYS_NUM | RG_DACQUIET_EN | | |
2469 | RG_LDVQUIET_EN | RG_CKRSEL | | |
2470 | RG_EEEPRG_EN); | |
2471 | ocp_reg_write(tp, OCP_EEE_CONFIG3, FST_SNR_EYE_R | RG_LFS_SEL | MSK_PH); | |
2472 | ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | DEVICE_ADDR); | |
2473 | ocp_reg_write(tp, OCP_EEE_DATA, EEE_ADDR); | |
2474 | ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | DEVICE_ADDR); | |
2475 | ocp_reg_write(tp, OCP_EEE_DATA, EEE_DATA); | |
2476 | ocp_reg_write(tp, OCP_EEE_AR, 0x0000); | |
2477 | } | |
2478 | ||
43779f8d | 2479 | static void r8153_enable_eee(struct r8152 *tp) |
2480 | { | |
2481 | u32 ocp_data; | |
2482 | u16 data; | |
2483 | ||
2484 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); | |
2485 | ocp_data |= EEE_RX_EN | EEE_TX_EN; | |
2486 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); | |
2487 | data = ocp_reg_read(tp, OCP_EEE_CFG); | |
2488 | data |= EEE10_EN; | |
2489 | ocp_reg_write(tp, OCP_EEE_CFG, data); | |
2490 | data = ocp_reg_read(tp, OCP_EEE_CFG2); | |
2491 | data |= MY1000_EEE | MY100_EEE; | |
2492 | ocp_reg_write(tp, OCP_EEE_CFG2, data); | |
2493 | } | |
2494 | ||
ac718b69 | 2495 | static void r8152b_enable_fc(struct r8152 *tp) |
2496 | { | |
2497 | u16 anar; | |
2498 | ||
2499 | anar = r8152_mdio_read(tp, MII_ADVERTISE); | |
2500 | anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; | |
2501 | r8152_mdio_write(tp, MII_ADVERTISE, anar); | |
2502 | } | |
2503 | ||
ac718b69 | 2504 | static void r8152b_init(struct r8152 *tp) |
2505 | { | |
ebc2ec48 | 2506 | u32 ocp_data; |
ac718b69 | 2507 | |
2508 | rtl_clear_bp(tp); | |
2509 | ||
2510 | if (tp->version == RTL_VER_01) { | |
2511 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); | |
2512 | ocp_data &= ~LED_MODE_MASK; | |
2513 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); | |
2514 | } | |
2515 | ||
2516 | r8152b_hw_phy_cfg(tp); | |
2517 | ||
00a5e360 | 2518 | r8152_power_cut_en(tp, false); |
ac718b69 | 2519 | |
ac718b69 | 2520 | |
2521 | r8152b_exit_oob(tp); | |
2522 | ||
2523 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); | |
2524 | ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH; | |
2525 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); | |
2526 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL); | |
2527 | ocp_data &= ~MCU_CLK_RATIO_MASK; | |
2528 | ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN; | |
2529 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data); | |
2530 | ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK | | |
2531 | SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK; | |
2532 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data); | |
2533 | ||
2534 | r8152b_enable_eee(tp); | |
2535 | r8152b_enable_aldps(tp); | |
2536 | r8152b_enable_fc(tp); | |
2537 | ||
ebc2ec48 | 2538 | /* enable rx aggregation */ |
ac718b69 | 2539 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); |
ebc2ec48 | 2540 | ocp_data &= ~RX_AGG_DISABLE; |
ac718b69 | 2541 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); |
2542 | } | |
2543 | ||
43779f8d | 2544 | static void r8153_init(struct r8152 *tp) |
2545 | { | |
2546 | u32 ocp_data; | |
2547 | int i; | |
2548 | ||
b9702723 | 2549 | r8153_u1u2en(tp, false); |
43779f8d | 2550 | |
2551 | for (i = 0; i < 500; i++) { | |
2552 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & | |
2553 | AUTOLOAD_DONE) | |
2554 | break; | |
2555 | msleep(20); | |
2556 | } | |
2557 | ||
2558 | for (i = 0; i < 500; i++) { | |
2559 | ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK; | |
2560 | if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN) | |
2561 | break; | |
2562 | msleep(20); | |
2563 | } | |
2564 | ||
b9702723 | 2565 | r8153_u2p3en(tp, false); |
43779f8d | 2566 | |
2567 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL); | |
2568 | ocp_data &= ~TIMER11_EN; | |
2569 | ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data); | |
2570 | ||
2571 | r8153_clear_bp(tp); | |
2572 | ||
2573 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); | |
2574 | ocp_data &= ~LED_MODE_MASK; | |
2575 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); | |
2576 | ||
2577 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL); | |
2578 | ocp_data &= ~LPM_TIMER_MASK; | |
2579 | if (tp->udev->speed == USB_SPEED_SUPER) | |
2580 | ocp_data |= LPM_TIMER_500US; | |
2581 | else | |
2582 | ocp_data |= LPM_TIMER_500MS; | |
2583 | ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data); | |
2584 | ||
2585 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2); | |
2586 | ocp_data &= ~SEN_VAL_MASK; | |
2587 | ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE; | |
2588 | ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data); | |
2589 | ||
b9702723 | 2590 | r8153_power_cut_en(tp, false); |
2591 | r8153_u1u2en(tp, true); | |
43779f8d | 2592 | |
2593 | r8153_first_init(tp); | |
2594 | ||
2595 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO); | |
2596 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO); | |
2597 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, | |
2598 | PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN | | |
2599 | U1U2_SPDWN_EN | L1_SPDWN_EN); | |
2600 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, | |
2601 | PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN | | |
2602 | TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN | | |
2603 | EEE_SPDWN_EN); | |
2604 | ||
2605 | r8153_enable_eee(tp); | |
2606 | r8153_enable_aldps(tp); | |
2607 | r8152b_enable_fc(tp); | |
43779f8d | 2608 | } |
2609 | ||
ac718b69 | 2610 | static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message) |
2611 | { | |
2612 | struct r8152 *tp = usb_get_intfdata(intf); | |
2613 | ||
2614 | netif_device_detach(tp->netdev); | |
2615 | ||
2616 | if (netif_running(tp->netdev)) { | |
2617 | clear_bit(WORK_ENABLE, &tp->flags); | |
40a82917 | 2618 | usb_kill_urb(tp->intr_urb); |
ac718b69 | 2619 | cancel_delayed_work_sync(&tp->schedule); |
ebc2ec48 | 2620 | tasklet_disable(&tp->tl); |
ac718b69 | 2621 | } |
2622 | ||
c81229c9 | 2623 | tp->rtl_ops.down(tp); |
ac718b69 | 2624 | |
2625 | return 0; | |
2626 | } | |
2627 | ||
2628 | static int rtl8152_resume(struct usb_interface *intf) | |
2629 | { | |
2630 | struct r8152 *tp = usb_get_intfdata(intf); | |
2631 | ||
c81229c9 | 2632 | tp->rtl_ops.init(tp); |
ac718b69 | 2633 | netif_device_attach(tp->netdev); |
2634 | if (netif_running(tp->netdev)) { | |
43779f8d | 2635 | rtl8152_set_speed(tp, AUTONEG_ENABLE, |
2636 | tp->mii.supports_gmii ? SPEED_1000 : SPEED_100, | |
2637 | DUPLEX_FULL); | |
40a82917 | 2638 | tp->speed = 0; |
2639 | netif_carrier_off(tp->netdev); | |
ac718b69 | 2640 | set_bit(WORK_ENABLE, &tp->flags); |
40a82917 | 2641 | usb_submit_urb(tp->intr_urb, GFP_KERNEL); |
ebc2ec48 | 2642 | tasklet_enable(&tp->tl); |
ac718b69 | 2643 | } |
2644 | ||
2645 | return 0; | |
2646 | } | |
2647 | ||
2648 | static void rtl8152_get_drvinfo(struct net_device *netdev, | |
2649 | struct ethtool_drvinfo *info) | |
2650 | { | |
2651 | struct r8152 *tp = netdev_priv(netdev); | |
2652 | ||
2653 | strncpy(info->driver, MODULENAME, ETHTOOL_BUSINFO_LEN); | |
2654 | strncpy(info->version, DRIVER_VERSION, ETHTOOL_BUSINFO_LEN); | |
2655 | usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info)); | |
2656 | } | |
2657 | ||
2658 | static | |
2659 | int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd) | |
2660 | { | |
2661 | struct r8152 *tp = netdev_priv(netdev); | |
2662 | ||
2663 | if (!tp->mii.mdio_read) | |
2664 | return -EOPNOTSUPP; | |
2665 | ||
2666 | return mii_ethtool_gset(&tp->mii, cmd); | |
2667 | } | |
2668 | ||
2669 | static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
2670 | { | |
2671 | struct r8152 *tp = netdev_priv(dev); | |
2672 | ||
2673 | return rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex); | |
2674 | } | |
2675 | ||
2676 | static struct ethtool_ops ops = { | |
2677 | .get_drvinfo = rtl8152_get_drvinfo, | |
2678 | .get_settings = rtl8152_get_settings, | |
2679 | .set_settings = rtl8152_set_settings, | |
2680 | .get_link = ethtool_op_get_link, | |
2681 | }; | |
2682 | ||
2683 | static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) | |
2684 | { | |
2685 | struct r8152 *tp = netdev_priv(netdev); | |
2686 | struct mii_ioctl_data *data = if_mii(rq); | |
2687 | int res = 0; | |
2688 | ||
2689 | switch (cmd) { | |
2690 | case SIOCGMIIPHY: | |
2691 | data->phy_id = R8152_PHY_ID; /* Internal PHY */ | |
2692 | break; | |
2693 | ||
2694 | case SIOCGMIIREG: | |
2695 | data->val_out = r8152_mdio_read(tp, data->reg_num); | |
2696 | break; | |
2697 | ||
2698 | case SIOCSMIIREG: | |
2699 | if (!capable(CAP_NET_ADMIN)) { | |
2700 | res = -EPERM; | |
2701 | break; | |
2702 | } | |
2703 | r8152_mdio_write(tp, data->reg_num, data->val_in); | |
2704 | break; | |
2705 | ||
2706 | default: | |
2707 | res = -EOPNOTSUPP; | |
2708 | } | |
2709 | ||
2710 | return res; | |
2711 | } | |
2712 | ||
2713 | static const struct net_device_ops rtl8152_netdev_ops = { | |
2714 | .ndo_open = rtl8152_open, | |
2715 | .ndo_stop = rtl8152_close, | |
2716 | .ndo_do_ioctl = rtl8152_ioctl, | |
2717 | .ndo_start_xmit = rtl8152_start_xmit, | |
2718 | .ndo_tx_timeout = rtl8152_tx_timeout, | |
2719 | .ndo_set_rx_mode = rtl8152_set_rx_mode, | |
2720 | .ndo_set_mac_address = rtl8152_set_mac_address, | |
2721 | ||
2722 | .ndo_change_mtu = eth_change_mtu, | |
2723 | .ndo_validate_addr = eth_validate_addr, | |
2724 | }; | |
2725 | ||
2726 | static void r8152b_get_version(struct r8152 *tp) | |
2727 | { | |
2728 | u32 ocp_data; | |
2729 | u16 version; | |
2730 | ||
2731 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1); | |
2732 | version = (u16)(ocp_data & VERSION_MASK); | |
2733 | ||
2734 | switch (version) { | |
2735 | case 0x4c00: | |
2736 | tp->version = RTL_VER_01; | |
2737 | break; | |
2738 | case 0x4c10: | |
2739 | tp->version = RTL_VER_02; | |
2740 | break; | |
43779f8d | 2741 | case 0x5c00: |
2742 | tp->version = RTL_VER_03; | |
2743 | tp->mii.supports_gmii = 1; | |
2744 | break; | |
2745 | case 0x5c10: | |
2746 | tp->version = RTL_VER_04; | |
2747 | tp->mii.supports_gmii = 1; | |
2748 | break; | |
2749 | case 0x5c20: | |
2750 | tp->version = RTL_VER_05; | |
2751 | tp->mii.supports_gmii = 1; | |
2752 | break; | |
ac718b69 | 2753 | default: |
2754 | netif_info(tp, probe, tp->netdev, | |
2755 | "Unknown version 0x%04x\n", version); | |
2756 | break; | |
2757 | } | |
2758 | } | |
2759 | ||
e3fe0b1a | 2760 | static void rtl8152_unload(struct r8152 *tp) |
2761 | { | |
00a5e360 | 2762 | if (tp->version != RTL_VER_01) |
2763 | r8152_power_cut_en(tp, true); | |
e3fe0b1a | 2764 | } |
2765 | ||
43779f8d | 2766 | static void rtl8153_unload(struct r8152 *tp) |
2767 | { | |
b9702723 | 2768 | r8153_power_cut_en(tp, true); |
43779f8d | 2769 | } |
2770 | ||
31ca1dec | 2771 | static int rtl_ops_init(struct r8152 *tp, const struct usb_device_id *id) |
c81229c9 | 2772 | { |
2773 | struct rtl_ops *ops = &tp->rtl_ops; | |
31ca1dec | 2774 | int ret = -ENODEV; |
c81229c9 | 2775 | |
2776 | switch (id->idVendor) { | |
2777 | case VENDOR_ID_REALTEK: | |
2778 | switch (id->idProduct) { | |
2779 | case PRODUCT_ID_RTL8152: | |
2780 | ops->init = r8152b_init; | |
2781 | ops->enable = rtl8152_enable; | |
2782 | ops->disable = rtl8152_disable; | |
2783 | ops->down = rtl8152_down; | |
2784 | ops->unload = rtl8152_unload; | |
31ca1dec | 2785 | ret = 0; |
c81229c9 | 2786 | break; |
43779f8d | 2787 | case PRODUCT_ID_RTL8153: |
2788 | ops->init = r8153_init; | |
2789 | ops->enable = rtl8153_enable; | |
2790 | ops->disable = rtl8152_disable; | |
2791 | ops->down = rtl8153_down; | |
2792 | ops->unload = rtl8153_unload; | |
31ca1dec | 2793 | ret = 0; |
43779f8d | 2794 | break; |
2795 | default: | |
43779f8d | 2796 | break; |
2797 | } | |
2798 | break; | |
2799 | ||
2800 | case VENDOR_ID_SAMSUNG: | |
2801 | switch (id->idProduct) { | |
2802 | case PRODUCT_ID_SAMSUNG: | |
2803 | ops->init = r8153_init; | |
2804 | ops->enable = rtl8153_enable; | |
2805 | ops->disable = rtl8152_disable; | |
2806 | ops->down = rtl8153_down; | |
2807 | ops->unload = rtl8153_unload; | |
31ca1dec | 2808 | ret = 0; |
43779f8d | 2809 | break; |
c81229c9 | 2810 | default: |
c81229c9 | 2811 | break; |
2812 | } | |
2813 | break; | |
2814 | ||
2815 | default: | |
c81229c9 | 2816 | break; |
2817 | } | |
2818 | ||
31ca1dec | 2819 | if (ret) |
2820 | netif_err(tp, probe, tp->netdev, "Unknown Device\n"); | |
2821 | ||
c81229c9 | 2822 | return ret; |
2823 | } | |
2824 | ||
ac718b69 | 2825 | static int rtl8152_probe(struct usb_interface *intf, |
2826 | const struct usb_device_id *id) | |
2827 | { | |
2828 | struct usb_device *udev = interface_to_usbdev(intf); | |
2829 | struct r8152 *tp; | |
2830 | struct net_device *netdev; | |
ebc2ec48 | 2831 | int ret; |
ac718b69 | 2832 | |
ac718b69 | 2833 | netdev = alloc_etherdev(sizeof(struct r8152)); |
2834 | if (!netdev) { | |
4a8deae2 | 2835 | dev_err(&intf->dev, "Out of memory\n"); |
ac718b69 | 2836 | return -ENOMEM; |
2837 | } | |
2838 | ||
ebc2ec48 | 2839 | SET_NETDEV_DEV(netdev, &intf->dev); |
ac718b69 | 2840 | tp = netdev_priv(netdev); |
2841 | tp->msg_enable = 0x7FFF; | |
2842 | ||
e3ad412a | 2843 | tp->udev = udev; |
2844 | tp->netdev = netdev; | |
2845 | tp->intf = intf; | |
2846 | ||
31ca1dec | 2847 | ret = rtl_ops_init(tp, id); |
2848 | if (ret) | |
2849 | goto out; | |
c81229c9 | 2850 | |
ebc2ec48 | 2851 | tasklet_init(&tp->tl, bottom_half, (unsigned long)tp); |
ac718b69 | 2852 | INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t); |
2853 | ||
ac718b69 | 2854 | netdev->netdev_ops = &rtl8152_netdev_ops; |
2855 | netdev->watchdog_timeo = RTL8152_TX_TIMEOUT; | |
5bd23881 | 2856 | |
2857 | netdev->features |= NETIF_F_IP_CSUM; | |
2858 | netdev->hw_features = NETIF_F_IP_CSUM; | |
ac718b69 | 2859 | SET_ETHTOOL_OPS(netdev, &ops); |
ac718b69 | 2860 | |
2861 | tp->mii.dev = netdev; | |
2862 | tp->mii.mdio_read = read_mii_word; | |
2863 | tp->mii.mdio_write = write_mii_word; | |
2864 | tp->mii.phy_id_mask = 0x3f; | |
2865 | tp->mii.reg_num_mask = 0x1f; | |
2866 | tp->mii.phy_id = R8152_PHY_ID; | |
2867 | tp->mii.supports_gmii = 0; | |
2868 | ||
2869 | r8152b_get_version(tp); | |
c81229c9 | 2870 | tp->rtl_ops.init(tp); |
ac718b69 | 2871 | set_ethernet_addr(tp); |
2872 | ||
ebc2ec48 | 2873 | ret = alloc_all_mem(tp); |
2874 | if (ret) | |
ac718b69 | 2875 | goto out; |
ac718b69 | 2876 | |
2877 | usb_set_intfdata(intf, tp); | |
ac718b69 | 2878 | |
ebc2ec48 | 2879 | ret = register_netdev(netdev); |
2880 | if (ret != 0) { | |
4a8deae2 | 2881 | netif_err(tp, probe, netdev, "couldn't register the device\n"); |
ebc2ec48 | 2882 | goto out1; |
ac718b69 | 2883 | } |
2884 | ||
4a8deae2 | 2885 | netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION); |
ac718b69 | 2886 | |
2887 | return 0; | |
2888 | ||
ac718b69 | 2889 | out1: |
ebc2ec48 | 2890 | usb_set_intfdata(intf, NULL); |
ac718b69 | 2891 | out: |
2892 | free_netdev(netdev); | |
ebc2ec48 | 2893 | return ret; |
ac718b69 | 2894 | } |
2895 | ||
ac718b69 | 2896 | static void rtl8152_disconnect(struct usb_interface *intf) |
2897 | { | |
2898 | struct r8152 *tp = usb_get_intfdata(intf); | |
2899 | ||
2900 | usb_set_intfdata(intf, NULL); | |
2901 | if (tp) { | |
2902 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
2903 | tasklet_kill(&tp->tl); | |
2904 | unregister_netdev(tp->netdev); | |
c81229c9 | 2905 | tp->rtl_ops.unload(tp); |
ebc2ec48 | 2906 | free_all_mem(tp); |
ac718b69 | 2907 | free_netdev(tp->netdev); |
2908 | } | |
2909 | } | |
2910 | ||
2911 | /* table of devices that work with this driver */ | |
2912 | static struct usb_device_id rtl8152_table[] = { | |
c7de7dec | 2913 | {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8152)}, |
2914 | {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8153)}, | |
2915 | {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, PRODUCT_ID_SAMSUNG)}, | |
ac718b69 | 2916 | {} |
2917 | }; | |
2918 | ||
2919 | MODULE_DEVICE_TABLE(usb, rtl8152_table); | |
2920 | ||
2921 | static struct usb_driver rtl8152_driver = { | |
2922 | .name = MODULENAME, | |
ebc2ec48 | 2923 | .id_table = rtl8152_table, |
ac718b69 | 2924 | .probe = rtl8152_probe, |
2925 | .disconnect = rtl8152_disconnect, | |
ac718b69 | 2926 | .suspend = rtl8152_suspend, |
ebc2ec48 | 2927 | .resume = rtl8152_resume, |
2928 | .reset_resume = rtl8152_resume, | |
ac718b69 | 2929 | }; |
2930 | ||
b4236daa | 2931 | module_usb_driver(rtl8152_driver); |
ac718b69 | 2932 | |
2933 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
2934 | MODULE_DESCRIPTION(DRIVER_DESC); | |
2935 | MODULE_LICENSE("GPL"); |