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ac718b69 1/*
c7de7dec 2 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
ac718b69 3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * version 2 as published by the Free Software Foundation.
7 *
8 */
9
ac718b69 10#include <linux/signal.h>
11#include <linux/slab.h>
12#include <linux/module.h>
ac718b69 13#include <linux/netdevice.h>
14#include <linux/etherdevice.h>
15#include <linux/mii.h>
16#include <linux/ethtool.h>
17#include <linux/usb.h>
18#include <linux/crc32.h>
19#include <linux/if_vlan.h>
20#include <linux/uaccess.h>
ebc2ec48 21#include <linux/list.h>
5bd23881 22#include <linux/ip.h>
23#include <linux/ipv6.h>
6128d1bb 24#include <net/ip6_checksum.h>
4c4a6b1b 25#include <uapi/linux/mdio.h>
26#include <linux/mdio.h>
d9a28c5b 27#include <linux/usb/cdc.h>
5ee3c60c 28#include <linux/suspend.h>
34ee32c9 29#include <linux/acpi.h>
ac718b69 30
d0942473 31/* Information for net-next */
32#define NETNEXT_VERSION "08"
33
34/* Information for net */
7489bdad 35#define NET_VERSION "8"
d0942473 36
37#define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION
ac718b69 38#define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
44d942a9 39#define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
ac718b69 40#define MODULENAME "r8152"
41
42#define R8152_PHY_ID 32
43
44#define PLA_IDR 0xc000
45#define PLA_RCR 0xc010
46#define PLA_RMS 0xc016
47#define PLA_RXFIFO_CTRL0 0xc0a0
48#define PLA_RXFIFO_CTRL1 0xc0a4
49#define PLA_RXFIFO_CTRL2 0xc0a8
65bab84c 50#define PLA_DMY_REG0 0xc0b0
ac718b69 51#define PLA_FMC 0xc0b4
52#define PLA_CFG_WOL 0xc0b6
43779f8d 53#define PLA_TEREDO_CFG 0xc0bc
ac718b69 54#define PLA_MAR 0xcd00
43779f8d 55#define PLA_BACKUP 0xd000
ac718b69 56#define PAL_BDC_CR 0xd1a0
43779f8d 57#define PLA_TEREDO_TIMER 0xd2cc
58#define PLA_REALWOW_TIMER 0xd2e8
ac718b69 59#define PLA_LEDSEL 0xdd90
60#define PLA_LED_FEATURE 0xdd92
61#define PLA_PHYAR 0xde00
43779f8d 62#define PLA_BOOT_CTRL 0xe004
ac718b69 63#define PLA_GPHY_INTR_IMR 0xe022
64#define PLA_EEE_CR 0xe040
65#define PLA_EEEP_CR 0xe080
66#define PLA_MAC_PWR_CTRL 0xe0c0
43779f8d 67#define PLA_MAC_PWR_CTRL2 0xe0ca
68#define PLA_MAC_PWR_CTRL3 0xe0cc
69#define PLA_MAC_PWR_CTRL4 0xe0ce
70#define PLA_WDT6_CTRL 0xe428
ac718b69 71#define PLA_TCR0 0xe610
72#define PLA_TCR1 0xe612
69b4b7a4 73#define PLA_MTPS 0xe615
ac718b69 74#define PLA_TXFIFO_CTRL 0xe618
4f1d4d54 75#define PLA_RSTTALLY 0xe800
ac718b69 76#define PLA_CR 0xe813
77#define PLA_CRWECR 0xe81c
21ff2e89 78#define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
79#define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
ac718b69 80#define PLA_CONFIG5 0xe822
81#define PLA_PHY_PWR 0xe84c
82#define PLA_OOB_CTRL 0xe84f
83#define PLA_CPCR 0xe854
84#define PLA_MISC_0 0xe858
85#define PLA_MISC_1 0xe85a
86#define PLA_OCP_GPHY_BASE 0xe86c
4f1d4d54 87#define PLA_TALLYCNT 0xe890
ac718b69 88#define PLA_SFF_STS_7 0xe8de
89#define PLA_PHYSTATUS 0xe908
90#define PLA_BP_BA 0xfc26
91#define PLA_BP_0 0xfc28
92#define PLA_BP_1 0xfc2a
93#define PLA_BP_2 0xfc2c
94#define PLA_BP_3 0xfc2e
95#define PLA_BP_4 0xfc30
96#define PLA_BP_5 0xfc32
97#define PLA_BP_6 0xfc34
98#define PLA_BP_7 0xfc36
43779f8d 99#define PLA_BP_EN 0xfc38
ac718b69 100
65bab84c 101#define USB_USB2PHY 0xb41e
102#define USB_SSPHYLINK2 0xb428
43779f8d 103#define USB_U2P3_CTRL 0xb460
65bab84c 104#define USB_CSR_DUMMY1 0xb464
105#define USB_CSR_DUMMY2 0xb466
ac718b69 106#define USB_DEV_STAT 0xb808
65bab84c 107#define USB_CONNECT_TIMER 0xcbf8
108#define USB_BURST_SIZE 0xcfc0
ac718b69 109#define USB_USB_CTRL 0xd406
110#define USB_PHY_CTRL 0xd408
111#define USB_TX_AGG 0xd40a
112#define USB_RX_BUF_TH 0xd40c
113#define USB_USB_TIMER 0xd428
464ec10a 114#define USB_RX_EARLY_TIMEOUT 0xd42c
115#define USB_RX_EARLY_SIZE 0xd42e
ac718b69 116#define USB_PM_CTRL_STATUS 0xd432
117#define USB_TX_DMA 0xd434
43779f8d 118#define USB_TOLERANCE 0xd490
119#define USB_LPM_CTRL 0xd41a
93fe9b18 120#define USB_BMU_RESET 0xd4b0
ac718b69 121#define USB_UPS_CTRL 0xd800
43779f8d 122#define USB_MISC_0 0xd81a
123#define USB_POWER_CUT 0xd80a
124#define USB_AFE_CTRL2 0xd824
125#define USB_WDT11_CTRL 0xe43c
ac718b69 126#define USB_BP_BA 0xfc26
127#define USB_BP_0 0xfc28
128#define USB_BP_1 0xfc2a
129#define USB_BP_2 0xfc2c
130#define USB_BP_3 0xfc2e
131#define USB_BP_4 0xfc30
132#define USB_BP_5 0xfc32
133#define USB_BP_6 0xfc34
134#define USB_BP_7 0xfc36
43779f8d 135#define USB_BP_EN 0xfc38
ac718b69 136
137/* OCP Registers */
138#define OCP_ALDPS_CONFIG 0x2010
139#define OCP_EEE_CONFIG1 0x2080
140#define OCP_EEE_CONFIG2 0x2092
141#define OCP_EEE_CONFIG3 0x2094
ac244d3e 142#define OCP_BASE_MII 0xa400
ac718b69 143#define OCP_EEE_AR 0xa41a
144#define OCP_EEE_DATA 0xa41c
43779f8d 145#define OCP_PHY_STATUS 0xa420
146#define OCP_POWER_CFG 0xa430
147#define OCP_EEE_CFG 0xa432
148#define OCP_SRAM_ADDR 0xa436
149#define OCP_SRAM_DATA 0xa438
150#define OCP_DOWN_SPEED 0xa442
df35d283 151#define OCP_EEE_ABLE 0xa5c4
4c4a6b1b 152#define OCP_EEE_ADV 0xa5d0
df35d283 153#define OCP_EEE_LPABLE 0xa5d2
2dd49e0f 154#define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
43779f8d 155#define OCP_ADC_CFG 0xbc06
156
157/* SRAM Register */
158#define SRAM_LPF_CFG 0x8012
159#define SRAM_10M_AMP1 0x8080
160#define SRAM_10M_AMP2 0x8082
161#define SRAM_IMPEDANCE 0x8084
ac718b69 162
163/* PLA_RCR */
164#define RCR_AAP 0x00000001
165#define RCR_APM 0x00000002
166#define RCR_AM 0x00000004
167#define RCR_AB 0x00000008
168#define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
169
170/* PLA_RXFIFO_CTRL0 */
171#define RXFIFO_THR1_NORMAL 0x00080002
172#define RXFIFO_THR1_OOB 0x01800003
173
174/* PLA_RXFIFO_CTRL1 */
175#define RXFIFO_THR2_FULL 0x00000060
176#define RXFIFO_THR2_HIGH 0x00000038
177#define RXFIFO_THR2_OOB 0x0000004a
43779f8d 178#define RXFIFO_THR2_NORMAL 0x00a0
ac718b69 179
180/* PLA_RXFIFO_CTRL2 */
181#define RXFIFO_THR3_FULL 0x00000078
182#define RXFIFO_THR3_HIGH 0x00000048
183#define RXFIFO_THR3_OOB 0x0000005a
43779f8d 184#define RXFIFO_THR3_NORMAL 0x0110
ac718b69 185
186/* PLA_TXFIFO_CTRL */
187#define TXFIFO_THR_NORMAL 0x00400008
43779f8d 188#define TXFIFO_THR_NORMAL2 0x01000008
ac718b69 189
65bab84c 190/* PLA_DMY_REG0 */
191#define ECM_ALDPS 0x0002
192
ac718b69 193/* PLA_FMC */
194#define FMC_FCR_MCU_EN 0x0001
195
196/* PLA_EEEP_CR */
197#define EEEP_CR_EEEP_TX 0x0002
198
43779f8d 199/* PLA_WDT6_CTRL */
200#define WDT6_SET_MODE 0x0010
201
ac718b69 202/* PLA_TCR0 */
203#define TCR0_TX_EMPTY 0x0800
204#define TCR0_AUTO_FIFO 0x0080
205
206/* PLA_TCR1 */
207#define VERSION_MASK 0x7cf0
208
69b4b7a4 209/* PLA_MTPS */
210#define MTPS_JUMBO (12 * 1024 / 64)
211#define MTPS_DEFAULT (6 * 1024 / 64)
212
4f1d4d54 213/* PLA_RSTTALLY */
214#define TALLY_RESET 0x0001
215
ac718b69 216/* PLA_CR */
217#define CR_RST 0x10
218#define CR_RE 0x08
219#define CR_TE 0x04
220
221/* PLA_CRWECR */
222#define CRWECR_NORAML 0x00
223#define CRWECR_CONFIG 0xc0
224
225/* PLA_OOB_CTRL */
226#define NOW_IS_OOB 0x80
227#define TXFIFO_EMPTY 0x20
228#define RXFIFO_EMPTY 0x10
229#define LINK_LIST_READY 0x02
230#define DIS_MCU_CLROOB 0x01
231#define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
232
233/* PLA_MISC_1 */
234#define RXDY_GATED_EN 0x0008
235
236/* PLA_SFF_STS_7 */
237#define RE_INIT_LL 0x8000
238#define MCU_BORW_EN 0x4000
239
240/* PLA_CPCR */
241#define CPCR_RX_VLAN 0x0040
242
243/* PLA_CFG_WOL */
244#define MAGIC_EN 0x0001
245
43779f8d 246/* PLA_TEREDO_CFG */
247#define TEREDO_SEL 0x8000
248#define TEREDO_WAKE_MASK 0x7f00
249#define TEREDO_RS_EVENT_MASK 0x00fe
250#define OOB_TEREDO_EN 0x0001
251
ac718b69 252/* PAL_BDC_CR */
253#define ALDPS_PROXY_MODE 0x0001
254
21ff2e89 255/* PLA_CONFIG34 */
256#define LINK_ON_WAKE_EN 0x0010
257#define LINK_OFF_WAKE_EN 0x0008
258
ac718b69 259/* PLA_CONFIG5 */
21ff2e89 260#define BWF_EN 0x0040
261#define MWF_EN 0x0020
262#define UWF_EN 0x0010
ac718b69 263#define LAN_WAKE_EN 0x0002
264
265/* PLA_LED_FEATURE */
266#define LED_MODE_MASK 0x0700
267
268/* PLA_PHY_PWR */
269#define TX_10M_IDLE_EN 0x0080
270#define PFM_PWM_SWITCH 0x0040
271
272/* PLA_MAC_PWR_CTRL */
273#define D3_CLK_GATED_EN 0x00004000
274#define MCU_CLK_RATIO 0x07010f07
275#define MCU_CLK_RATIO_MASK 0x0f0f0f0f
43779f8d 276#define ALDPS_SPDWN_RATIO 0x0f87
277
278/* PLA_MAC_PWR_CTRL2 */
279#define EEE_SPDWN_RATIO 0x8007
280
281/* PLA_MAC_PWR_CTRL3 */
282#define PKT_AVAIL_SPDWN_EN 0x0100
283#define SUSPEND_SPDWN_EN 0x0004
284#define U1U2_SPDWN_EN 0x0002
285#define L1_SPDWN_EN 0x0001
286
287/* PLA_MAC_PWR_CTRL4 */
288#define PWRSAVE_SPDWN_EN 0x1000
289#define RXDV_SPDWN_EN 0x0800
290#define TX10MIDLE_EN 0x0100
291#define TP100_SPDWN_EN 0x0020
292#define TP500_SPDWN_EN 0x0010
293#define TP1000_SPDWN_EN 0x0008
294#define EEE_SPDWN_EN 0x0001
ac718b69 295
296/* PLA_GPHY_INTR_IMR */
297#define GPHY_STS_MSK 0x0001
298#define SPEED_DOWN_MSK 0x0002
299#define SPDWN_RXDV_MSK 0x0004
300#define SPDWN_LINKCHG_MSK 0x0008
301
302/* PLA_PHYAR */
303#define PHYAR_FLAG 0x80000000
304
305/* PLA_EEE_CR */
306#define EEE_RX_EN 0x0001
307#define EEE_TX_EN 0x0002
308
43779f8d 309/* PLA_BOOT_CTRL */
310#define AUTOLOAD_DONE 0x0002
311
65bab84c 312/* USB_USB2PHY */
313#define USB2PHY_SUSPEND 0x0001
314#define USB2PHY_L1 0x0002
315
316/* USB_SSPHYLINK2 */
317#define pwd_dn_scale_mask 0x3ffe
318#define pwd_dn_scale(x) ((x) << 1)
319
320/* USB_CSR_DUMMY1 */
321#define DYNAMIC_BURST 0x0001
322
323/* USB_CSR_DUMMY2 */
324#define EP4_FULL_FC 0x0001
325
ac718b69 326/* USB_DEV_STAT */
327#define STAT_SPEED_MASK 0x0006
328#define STAT_SPEED_HIGH 0x0000
a3cc465d 329#define STAT_SPEED_FULL 0x0002
ac718b69 330
331/* USB_TX_AGG */
332#define TX_AGG_MAX_THRESHOLD 0x03
333
334/* USB_RX_BUF_TH */
43779f8d 335#define RX_THR_SUPPER 0x0c350180
8e1f51bd 336#define RX_THR_HIGH 0x7a120180
43779f8d 337#define RX_THR_SLOW 0xffff0180
ac718b69 338
339/* USB_TX_DMA */
340#define TEST_MODE_DISABLE 0x00000001
341#define TX_SIZE_ADJUST1 0x00000100
342
93fe9b18 343/* USB_BMU_RESET */
344#define BMU_RESET_EP_IN 0x01
345#define BMU_RESET_EP_OUT 0x02
346
ac718b69 347/* USB_UPS_CTRL */
348#define POWER_CUT 0x0100
349
350/* USB_PM_CTRL_STATUS */
8e1f51bd 351#define RESUME_INDICATE 0x0001
ac718b69 352
353/* USB_USB_CTRL */
354#define RX_AGG_DISABLE 0x0010
e90fba8d 355#define RX_ZERO_EN 0x0080
ac718b69 356
43779f8d 357/* USB_U2P3_CTRL */
358#define U2P3_ENABLE 0x0001
359
360/* USB_POWER_CUT */
361#define PWR_EN 0x0001
362#define PHASE2_EN 0x0008
363
364/* USB_MISC_0 */
365#define PCUT_STATUS 0x0001
366
464ec10a 367/* USB_RX_EARLY_TIMEOUT */
368#define COALESCE_SUPER 85000U
369#define COALESCE_HIGH 250000U
370#define COALESCE_SLOW 524280U
43779f8d 371
372/* USB_WDT11_CTRL */
373#define TIMER11_EN 0x0001
374
375/* USB_LPM_CTRL */
65bab84c 376/* bit 4 ~ 5: fifo empty boundary */
377#define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
378/* bit 2 ~ 3: LMP timer */
43779f8d 379#define LPM_TIMER_MASK 0x0c
380#define LPM_TIMER_500MS 0x04 /* 500 ms */
381#define LPM_TIMER_500US 0x0c /* 500 us */
65bab84c 382#define ROK_EXIT_LPM 0x02
43779f8d 383
384/* USB_AFE_CTRL2 */
385#define SEN_VAL_MASK 0xf800
386#define SEN_VAL_NORMAL 0xa000
387#define SEL_RXIDLE 0x0100
388
ac718b69 389/* OCP_ALDPS_CONFIG */
390#define ENPWRSAVE 0x8000
391#define ENPDNPS 0x0200
392#define LINKENA 0x0100
393#define DIS_SDSAVE 0x0010
394
43779f8d 395/* OCP_PHY_STATUS */
396#define PHY_STAT_MASK 0x0007
397#define PHY_STAT_LAN_ON 3
398#define PHY_STAT_PWRDN 5
399
400/* OCP_POWER_CFG */
401#define EEE_CLKDIV_EN 0x8000
402#define EN_ALDPS 0x0004
403#define EN_10M_PLLOFF 0x0001
404
ac718b69 405/* OCP_EEE_CONFIG1 */
406#define RG_TXLPI_MSK_HFDUP 0x8000
407#define RG_MATCLR_EN 0x4000
408#define EEE_10_CAP 0x2000
409#define EEE_NWAY_EN 0x1000
410#define TX_QUIET_EN 0x0200
411#define RX_QUIET_EN 0x0100
d24f6134 412#define sd_rise_time_mask 0x0070
4c4a6b1b 413#define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
ac718b69 414#define RG_RXLPI_MSK_HFDUP 0x0008
415#define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
416
417/* OCP_EEE_CONFIG2 */
418#define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
419#define RG_DACQUIET_EN 0x0400
420#define RG_LDVQUIET_EN 0x0200
421#define RG_CKRSEL 0x0020
422#define RG_EEEPRG_EN 0x0010
423
424/* OCP_EEE_CONFIG3 */
d24f6134 425#define fast_snr_mask 0xff80
4c4a6b1b 426#define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
ac718b69 427#define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
428#define MSK_PH 0x0006 /* bit 0 ~ 3 */
429
430/* OCP_EEE_AR */
431/* bit[15:14] function */
432#define FUN_ADDR 0x0000
433#define FUN_DATA 0x4000
434/* bit[4:0] device addr */
ac718b69 435
43779f8d 436/* OCP_EEE_CFG */
437#define CTAP_SHORT_EN 0x0040
438#define EEE10_EN 0x0010
439
440/* OCP_DOWN_SPEED */
441#define EN_10M_BGOFF 0x0080
442
2dd49e0f 443/* OCP_PHY_STATE */
444#define TXDIS_STATE 0x01
445#define ABD_STATE 0x02
446
43779f8d 447/* OCP_ADC_CFG */
448#define CKADSEL_L 0x0100
449#define ADC_EN 0x0080
450#define EN_EMI_L 0x0040
451
452/* SRAM_LPF_CFG */
453#define LPF_AUTO_TUNE 0x8000
454
455/* SRAM_10M_AMP1 */
456#define GDAC_IB_UPALL 0x0008
457
458/* SRAM_10M_AMP2 */
459#define AMP_DN 0x0200
460
461/* SRAM_IMPEDANCE */
462#define RX_DRIVING_MASK 0x6000
463
34ee32c9
ML
464/* MAC PASSTHRU */
465#define AD_MASK 0xfee0
466#define EFUSE 0xcfdb
467#define PASS_THRU_MASK 0x1
468
ac718b69 469enum rtl_register_content {
43779f8d 470 _1000bps = 0x10,
ac718b69 471 _100bps = 0x08,
472 _10bps = 0x04,
473 LINK_STATUS = 0x02,
474 FULL_DUP = 0x01,
475};
476
1764bcd9 477#define RTL8152_MAX_TX 4
ebc2ec48 478#define RTL8152_MAX_RX 10
40a82917 479#define INTBUFSIZE 2
8e1f51bd 480#define CRC_SIZE 4
481#define TX_ALIGN 4
482#define RX_ALIGN 8
40a82917 483
484#define INTR_LINK 0x0004
ebc2ec48 485
ac718b69 486#define RTL8152_REQT_READ 0xc0
487#define RTL8152_REQT_WRITE 0x40
488#define RTL8152_REQ_GET_REGS 0x05
489#define RTL8152_REQ_SET_REGS 0x05
490
491#define BYTE_EN_DWORD 0xff
492#define BYTE_EN_WORD 0x33
493#define BYTE_EN_BYTE 0x11
494#define BYTE_EN_SIX_BYTES 0x3f
495#define BYTE_EN_START_MASK 0x0f
496#define BYTE_EN_END_MASK 0xf0
497
69b4b7a4 498#define RTL8153_MAX_PACKET 9216 /* 9K */
499#define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN)
ac718b69 500#define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
69b4b7a4 501#define RTL8153_RMS RTL8153_MAX_PACKET
b8125404 502#define RTL8152_TX_TIMEOUT (5 * HZ)
d823ab68 503#define RTL8152_NAPI_WEIGHT 64
ac718b69 504
505/* rtl8152 flags */
506enum rtl8152_flags {
507 RTL8152_UNPLUG = 0,
ac718b69 508 RTL8152_SET_RX_MODE,
40a82917 509 WORK_ENABLE,
510 RTL8152_LINK_CHG,
9a4be1bd 511 SELECTIVE_SUSPEND,
aa66a5f1 512 PHY_RESET,
d823ab68 513 SCHEDULE_NAPI,
ac718b69 514};
515
516/* Define these values to match your device */
517#define VENDOR_ID_REALTEK 0x0bda
43779f8d 518#define VENDOR_ID_SAMSUNG 0x04e8
347eec34 519#define VENDOR_ID_LENOVO 0x17ef
d065c3c1 520#define VENDOR_ID_NVIDIA 0x0955
ac718b69 521
522#define MCU_TYPE_PLA 0x0100
523#define MCU_TYPE_USB 0x0000
524
4f1d4d54 525struct tally_counter {
526 __le64 tx_packets;
527 __le64 rx_packets;
528 __le64 tx_errors;
529 __le32 rx_errors;
530 __le16 rx_missed;
531 __le16 align_errors;
532 __le32 tx_one_collision;
533 __le32 tx_multi_collision;
534 __le64 rx_unicast;
535 __le64 rx_broadcast;
536 __le32 rx_multicast;
537 __le16 tx_aborted;
f37119c5 538 __le16 tx_underrun;
4f1d4d54 539};
540
ac718b69 541struct rx_desc {
500b6d7e 542 __le32 opts1;
ac718b69 543#define RX_LEN_MASK 0x7fff
565cab0a 544
500b6d7e 545 __le32 opts2;
f5aaaa6d 546#define RD_UDP_CS BIT(23)
547#define RD_TCP_CS BIT(22)
548#define RD_IPV6_CS BIT(20)
549#define RD_IPV4_CS BIT(19)
565cab0a 550
500b6d7e 551 __le32 opts3;
f5aaaa6d 552#define IPF BIT(23) /* IP checksum fail */
553#define UDPF BIT(22) /* UDP checksum fail */
554#define TCPF BIT(21) /* TCP checksum fail */
555#define RX_VLAN_TAG BIT(16)
565cab0a 556
500b6d7e 557 __le32 opts4;
558 __le32 opts5;
559 __le32 opts6;
ac718b69 560};
561
562struct tx_desc {
500b6d7e 563 __le32 opts1;
f5aaaa6d 564#define TX_FS BIT(31) /* First segment of a packet */
565#define TX_LS BIT(30) /* Final segment of a packet */
566#define GTSENDV4 BIT(28)
567#define GTSENDV6 BIT(27)
60c89071 568#define GTTCPHO_SHIFT 18
6128d1bb 569#define GTTCPHO_MAX 0x7fU
60c89071 570#define TX_LEN_MAX 0x3ffffU
5bd23881 571
500b6d7e 572 __le32 opts2;
f5aaaa6d 573#define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
574#define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
575#define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
576#define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
60c89071 577#define MSS_SHIFT 17
578#define MSS_MAX 0x7ffU
579#define TCPHO_SHIFT 17
6128d1bb 580#define TCPHO_MAX 0x7ffU
f5aaaa6d 581#define TX_VLAN_TAG BIT(16)
ac718b69 582};
583
dff4e8ad 584struct r8152;
585
ebc2ec48 586struct rx_agg {
587 struct list_head list;
588 struct urb *urb;
dff4e8ad 589 struct r8152 *context;
ebc2ec48 590 void *buffer;
591 void *head;
592};
593
594struct tx_agg {
595 struct list_head list;
596 struct urb *urb;
dff4e8ad 597 struct r8152 *context;
ebc2ec48 598 void *buffer;
599 void *head;
600 u32 skb_num;
601 u32 skb_len;
602};
603
ac718b69 604struct r8152 {
605 unsigned long flags;
606 struct usb_device *udev;
d823ab68 607 struct napi_struct napi;
40a82917 608 struct usb_interface *intf;
ac718b69 609 struct net_device *netdev;
40a82917 610 struct urb *intr_urb;
ebc2ec48 611 struct tx_agg tx_info[RTL8152_MAX_TX];
612 struct rx_agg rx_info[RTL8152_MAX_RX];
613 struct list_head rx_done, tx_free;
d823ab68 614 struct sk_buff_head tx_queue, rx_queue;
ebc2ec48 615 spinlock_t rx_lock, tx_lock;
a028a9e0 616 struct delayed_work schedule, hw_phy_work;
ac718b69 617 struct mii_if_info mii;
b5403273 618 struct mutex control; /* use for hw setting */
5ee3c60c 619#ifdef CONFIG_PM_SLEEP
620 struct notifier_block pm_notifier;
621#endif
c81229c9 622
623 struct rtl_ops {
624 void (*init)(struct r8152 *);
625 int (*enable)(struct r8152 *);
626 void (*disable)(struct r8152 *);
7e9da481 627 void (*up)(struct r8152 *);
c81229c9 628 void (*down)(struct r8152 *);
629 void (*unload)(struct r8152 *);
df35d283 630 int (*eee_get)(struct r8152 *, struct ethtool_eee *);
631 int (*eee_set)(struct r8152 *, struct ethtool_eee *);
2dd49e0f 632 bool (*in_nway)(struct r8152 *);
a028a9e0 633 void (*hw_phy_cfg)(struct r8152 *);
2609af19 634 void (*autosuspend_en)(struct r8152 *tp, bool enable);
c81229c9 635 } rtl_ops;
636
40a82917 637 int intr_interval;
21ff2e89 638 u32 saved_wolopts;
ac718b69 639 u32 msg_enable;
dd1b119c 640 u32 tx_qlen;
464ec10a 641 u32 coalesce;
ac718b69 642 u16 ocp_base;
aa7e26b6 643 u16 speed;
40a82917 644 u8 *intr_buff;
ac718b69 645 u8 version;
aa7e26b6 646 u8 duplex;
647 u8 autoneg;
ac718b69 648};
649
650enum rtl_version {
651 RTL_VER_UNKNOWN = 0,
652 RTL_VER_01,
43779f8d 653 RTL_VER_02,
654 RTL_VER_03,
655 RTL_VER_04,
656 RTL_VER_05,
fb02eb4a 657 RTL_VER_06,
43779f8d 658 RTL_VER_MAX
ac718b69 659};
660
60c89071 661enum tx_csum_stat {
662 TX_CSUM_SUCCESS = 0,
663 TX_CSUM_TSO,
664 TX_CSUM_NONE
665};
666
ac718b69 667/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
668 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
669 */
670static const int multicast_filter_limit = 32;
52aec126 671static unsigned int agg_buf_sz = 16384;
ac718b69 672
52aec126 673#define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \
60c89071 674 VLAN_ETH_HLEN - VLAN_HLEN)
675
ac718b69 676static
677int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
678{
31787f53 679 int ret;
680 void *tmp;
681
682 tmp = kmalloc(size, GFP_KERNEL);
683 if (!tmp)
684 return -ENOMEM;
685
686 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
b209af99 687 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
688 value, index, tmp, size, 500);
31787f53 689
690 memcpy(data, tmp, size);
691 kfree(tmp);
692
693 return ret;
ac718b69 694}
695
696static
697int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
698{
31787f53 699 int ret;
700 void *tmp;
701
c4438f03 702 tmp = kmemdup(data, size, GFP_KERNEL);
31787f53 703 if (!tmp)
704 return -ENOMEM;
705
31787f53 706 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
b209af99 707 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
708 value, index, tmp, size, 500);
31787f53 709
710 kfree(tmp);
db8515ef 711
31787f53 712 return ret;
ac718b69 713}
714
715static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
b209af99 716 void *data, u16 type)
ac718b69 717{
45f4a19f 718 u16 limit = 64;
719 int ret = 0;
ac718b69 720
721 if (test_bit(RTL8152_UNPLUG, &tp->flags))
722 return -ENODEV;
723
724 /* both size and indix must be 4 bytes align */
725 if ((size & 3) || !size || (index & 3) || !data)
726 return -EPERM;
727
728 if ((u32)index + (u32)size > 0xffff)
729 return -EPERM;
730
731 while (size) {
732 if (size > limit) {
733 ret = get_registers(tp, index, type, limit, data);
734 if (ret < 0)
735 break;
736
737 index += limit;
738 data += limit;
739 size -= limit;
740 } else {
741 ret = get_registers(tp, index, type, size, data);
742 if (ret < 0)
743 break;
744
745 index += size;
746 data += size;
747 size = 0;
748 break;
749 }
750 }
751
67610496 752 if (ret == -ENODEV)
753 set_bit(RTL8152_UNPLUG, &tp->flags);
754
ac718b69 755 return ret;
756}
757
758static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
b209af99 759 u16 size, void *data, u16 type)
ac718b69 760{
45f4a19f 761 int ret;
762 u16 byteen_start, byteen_end, byen;
763 u16 limit = 512;
ac718b69 764
765 if (test_bit(RTL8152_UNPLUG, &tp->flags))
766 return -ENODEV;
767
768 /* both size and indix must be 4 bytes align */
769 if ((size & 3) || !size || (index & 3) || !data)
770 return -EPERM;
771
772 if ((u32)index + (u32)size > 0xffff)
773 return -EPERM;
774
775 byteen_start = byteen & BYTE_EN_START_MASK;
776 byteen_end = byteen & BYTE_EN_END_MASK;
777
778 byen = byteen_start | (byteen_start << 4);
779 ret = set_registers(tp, index, type | byen, 4, data);
780 if (ret < 0)
781 goto error1;
782
783 index += 4;
784 data += 4;
785 size -= 4;
786
787 if (size) {
788 size -= 4;
789
790 while (size) {
791 if (size > limit) {
792 ret = set_registers(tp, index,
b209af99 793 type | BYTE_EN_DWORD,
794 limit, data);
ac718b69 795 if (ret < 0)
796 goto error1;
797
798 index += limit;
799 data += limit;
800 size -= limit;
801 } else {
802 ret = set_registers(tp, index,
b209af99 803 type | BYTE_EN_DWORD,
804 size, data);
ac718b69 805 if (ret < 0)
806 goto error1;
807
808 index += size;
809 data += size;
810 size = 0;
811 break;
812 }
813 }
814
815 byen = byteen_end | (byteen_end >> 4);
816 ret = set_registers(tp, index, type | byen, 4, data);
817 if (ret < 0)
818 goto error1;
819 }
820
821error1:
67610496 822 if (ret == -ENODEV)
823 set_bit(RTL8152_UNPLUG, &tp->flags);
824
ac718b69 825 return ret;
826}
827
828static inline
829int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
830{
831 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
832}
833
834static inline
835int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
836{
837 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
838}
839
840static inline
841int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
842{
843 return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
844}
845
846static inline
847int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
848{
849 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
850}
851
852static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
853{
c8826de8 854 __le32 data;
ac718b69 855
c8826de8 856 generic_ocp_read(tp, index, sizeof(data), &data, type);
ac718b69 857
858 return __le32_to_cpu(data);
859}
860
861static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
862{
c8826de8 863 __le32 tmp = __cpu_to_le32(data);
864
865 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
ac718b69 866}
867
868static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
869{
870 u32 data;
c8826de8 871 __le32 tmp;
ac718b69 872 u8 shift = index & 2;
873
874 index &= ~3;
875
c8826de8 876 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
ac718b69 877
c8826de8 878 data = __le32_to_cpu(tmp);
ac718b69 879 data >>= (shift * 8);
880 data &= 0xffff;
881
882 return (u16)data;
883}
884
885static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
886{
c8826de8 887 u32 mask = 0xffff;
888 __le32 tmp;
ac718b69 889 u16 byen = BYTE_EN_WORD;
890 u8 shift = index & 2;
891
892 data &= mask;
893
894 if (index & 2) {
895 byen <<= shift;
896 mask <<= (shift * 8);
897 data <<= (shift * 8);
898 index &= ~3;
899 }
900
c8826de8 901 tmp = __cpu_to_le32(data);
ac718b69 902
c8826de8 903 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
ac718b69 904}
905
906static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
907{
908 u32 data;
c8826de8 909 __le32 tmp;
ac718b69 910 u8 shift = index & 3;
911
912 index &= ~3;
913
c8826de8 914 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
ac718b69 915
c8826de8 916 data = __le32_to_cpu(tmp);
ac718b69 917 data >>= (shift * 8);
918 data &= 0xff;
919
920 return (u8)data;
921}
922
923static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
924{
c8826de8 925 u32 mask = 0xff;
926 __le32 tmp;
ac718b69 927 u16 byen = BYTE_EN_BYTE;
928 u8 shift = index & 3;
929
930 data &= mask;
931
932 if (index & 3) {
933 byen <<= shift;
934 mask <<= (shift * 8);
935 data <<= (shift * 8);
936 index &= ~3;
937 }
938
c8826de8 939 tmp = __cpu_to_le32(data);
ac718b69 940
c8826de8 941 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
ac718b69 942}
943
ac244d3e 944static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
e3fe0b1a 945{
946 u16 ocp_base, ocp_index;
947
948 ocp_base = addr & 0xf000;
949 if (ocp_base != tp->ocp_base) {
950 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
951 tp->ocp_base = ocp_base;
952 }
953
954 ocp_index = (addr & 0x0fff) | 0xb000;
ac244d3e 955 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
e3fe0b1a 956}
957
ac244d3e 958static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
ac718b69 959{
ac244d3e 960 u16 ocp_base, ocp_index;
ac718b69 961
ac244d3e 962 ocp_base = addr & 0xf000;
963 if (ocp_base != tp->ocp_base) {
964 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
965 tp->ocp_base = ocp_base;
ac718b69 966 }
ac244d3e 967
968 ocp_index = (addr & 0x0fff) | 0xb000;
969 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
ac718b69 970}
971
ac244d3e 972static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
ac718b69 973{
ac244d3e 974 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
975}
ac718b69 976
ac244d3e 977static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
978{
979 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
ac718b69 980}
981
43779f8d 982static void sram_write(struct r8152 *tp, u16 addr, u16 data)
983{
984 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
985 ocp_reg_write(tp, OCP_SRAM_DATA, data);
986}
987
ac718b69 988static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
989{
990 struct r8152 *tp = netdev_priv(netdev);
9a4be1bd 991 int ret;
ac718b69 992
6871438c 993 if (test_bit(RTL8152_UNPLUG, &tp->flags))
994 return -ENODEV;
995
ac718b69 996 if (phy_id != R8152_PHY_ID)
997 return -EINVAL;
998
9a4be1bd 999 ret = r8152_mdio_read(tp, reg);
1000
9a4be1bd 1001 return ret;
ac718b69 1002}
1003
1004static
1005void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
1006{
1007 struct r8152 *tp = netdev_priv(netdev);
1008
6871438c 1009 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1010 return;
1011
ac718b69 1012 if (phy_id != R8152_PHY_ID)
1013 return;
1014
1015 r8152_mdio_write(tp, reg, val);
1016}
1017
b209af99 1018static int
1019r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
ebc2ec48 1020
8ba789ab 1021static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
1022{
1023 struct r8152 *tp = netdev_priv(netdev);
1024 struct sockaddr *addr = p;
ea6a7112 1025 int ret = -EADDRNOTAVAIL;
8ba789ab 1026
1027 if (!is_valid_ether_addr(addr->sa_data))
ea6a7112 1028 goto out1;
1029
1030 ret = usb_autopm_get_interface(tp->intf);
1031 if (ret < 0)
1032 goto out1;
8ba789ab 1033
b5403273 1034 mutex_lock(&tp->control);
1035
8ba789ab 1036 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1037
1038 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1039 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1040 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1041
b5403273 1042 mutex_unlock(&tp->control);
1043
ea6a7112 1044 usb_autopm_put_interface(tp->intf);
1045out1:
1046 return ret;
8ba789ab 1047}
1048
34ee32c9
ML
1049/* Devices containing RTL8153-AD can support a persistent
1050 * host system provided MAC address.
1051 * Examples of this are Dell TB15 and Dell WD15 docks
1052 */
1053static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa)
1054{
1055 acpi_status status;
1056 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
1057 union acpi_object *obj;
1058 int ret = -EINVAL;
1059 u32 ocp_data;
1060 unsigned char buf[6];
1061
1062 /* test for -AD variant of RTL8153 */
1063 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
1064 if ((ocp_data & AD_MASK) != 0x1000)
1065 return -ENODEV;
1066
1067 /* test for MAC address pass-through bit */
1068 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);
1069 if ((ocp_data & PASS_THRU_MASK) != 1)
1070 return -ENODEV;
1071
1072 /* returns _AUXMAC_#AABBCCDDEEFF# */
1073 status = acpi_evaluate_object(NULL, "\\_SB.AMAC", NULL, &buffer);
1074 obj = (union acpi_object *)buffer.pointer;
1075 if (!ACPI_SUCCESS(status))
1076 return -ENODEV;
1077 if (obj->type != ACPI_TYPE_BUFFER || obj->string.length != 0x17) {
1078 netif_warn(tp, probe, tp->netdev,
53700f0c 1079 "Invalid buffer for pass-thru MAC addr: (%d, %d)\n",
34ee32c9
ML
1080 obj->type, obj->string.length);
1081 goto amacout;
1082 }
1083 if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||
1084 strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {
1085 netif_warn(tp, probe, tp->netdev,
1086 "Invalid header when reading pass-thru MAC addr\n");
1087 goto amacout;
1088 }
1089 ret = hex2bin(buf, obj->string.pointer + 9, 6);
1090 if (!(ret == 0 && is_valid_ether_addr(buf))) {
1091 netif_warn(tp, probe, tp->netdev,
53700f0c 1092 "Invalid MAC for pass-thru MAC addr: %d, %pM\n",
1093 ret, buf);
34ee32c9
ML
1094 ret = -EINVAL;
1095 goto amacout;
1096 }
1097 memcpy(sa->sa_data, buf, 6);
1098 ether_addr_copy(tp->netdev->dev_addr, sa->sa_data);
1099 netif_info(tp, probe, tp->netdev,
1100 "Using pass-thru MAC addr %pM\n", sa->sa_data);
1101
1102amacout:
1103 kfree(obj);
1104 return ret;
1105}
1106
179bb6d7 1107static int set_ethernet_addr(struct r8152 *tp)
ac718b69 1108{
1109 struct net_device *dev = tp->netdev;
179bb6d7 1110 struct sockaddr sa;
8a91c824 1111 int ret;
ac718b69 1112
53700f0c 1113 if (tp->version == RTL_VER_01) {
179bb6d7 1114 ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data);
53700f0c 1115 } else {
34ee32c9
ML
1116 /* if this is not an RTL8153-AD, no eFuse mac pass thru set,
1117 * or system doesn't provide valid _SB.AMAC this will be
1118 * be expected to non-zero
1119 */
1120 ret = vendor_mac_passthru_addr_read(tp, &sa);
1121 if (ret < 0)
1122 ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data);
1123 }
8a91c824 1124
1125 if (ret < 0) {
179bb6d7 1126 netif_err(tp, probe, dev, "Get ether addr fail\n");
1127 } else if (!is_valid_ether_addr(sa.sa_data)) {
1128 netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1129 sa.sa_data);
1130 eth_hw_addr_random(dev);
1131 ether_addr_copy(sa.sa_data, dev->dev_addr);
1132 ret = rtl8152_set_mac_address(dev, &sa);
1133 netif_info(tp, probe, dev, "Random ether addr %pM\n",
1134 sa.sa_data);
8a91c824 1135 } else {
179bb6d7 1136 if (tp->version == RTL_VER_01)
1137 ether_addr_copy(dev->dev_addr, sa.sa_data);
1138 else
1139 ret = rtl8152_set_mac_address(dev, &sa);
ac718b69 1140 }
179bb6d7 1141
1142 return ret;
ac718b69 1143}
1144
ac718b69 1145static void read_bulk_callback(struct urb *urb)
1146{
ac718b69 1147 struct net_device *netdev;
ac718b69 1148 int status = urb->status;
ebc2ec48 1149 struct rx_agg *agg;
1150 struct r8152 *tp;
ac718b69 1151
ebc2ec48 1152 agg = urb->context;
1153 if (!agg)
1154 return;
1155
1156 tp = agg->context;
ac718b69 1157 if (!tp)
1158 return;
ebc2ec48 1159
ac718b69 1160 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1161 return;
ebc2ec48 1162
1163 if (!test_bit(WORK_ENABLE, &tp->flags))
1164 return;
1165
ac718b69 1166 netdev = tp->netdev;
7559fb2f 1167
1168 /* When link down, the driver would cancel all bulks. */
1169 /* This avoid the re-submitting bulk */
ebc2ec48 1170 if (!netif_carrier_ok(netdev))
ac718b69 1171 return;
1172
9a4be1bd 1173 usb_mark_last_busy(tp->udev);
1174
ac718b69 1175 switch (status) {
1176 case 0:
ebc2ec48 1177 if (urb->actual_length < ETH_ZLEN)
1178 break;
1179
2685d410 1180 spin_lock(&tp->rx_lock);
ebc2ec48 1181 list_add_tail(&agg->list, &tp->rx_done);
2685d410 1182 spin_unlock(&tp->rx_lock);
d823ab68 1183 napi_schedule(&tp->napi);
ebc2ec48 1184 return;
ac718b69 1185 case -ESHUTDOWN:
1186 set_bit(RTL8152_UNPLUG, &tp->flags);
1187 netif_device_detach(tp->netdev);
ebc2ec48 1188 return;
ac718b69 1189 case -ENOENT:
1190 return; /* the urb is in unlink state */
1191 case -ETIME:
4a8deae2
HW
1192 if (net_ratelimit())
1193 netdev_warn(netdev, "maybe reset is needed?\n");
ebc2ec48 1194 break;
ac718b69 1195 default:
4a8deae2
HW
1196 if (net_ratelimit())
1197 netdev_warn(netdev, "Rx status %d\n", status);
ebc2ec48 1198 break;
ac718b69 1199 }
1200
a0fccd48 1201 r8152_submit_rx(tp, agg, GFP_ATOMIC);
ac718b69 1202}
1203
ebc2ec48 1204static void write_bulk_callback(struct urb *urb)
ac718b69 1205{
ebc2ec48 1206 struct net_device_stats *stats;
d104eafa 1207 struct net_device *netdev;
ebc2ec48 1208 struct tx_agg *agg;
ac718b69 1209 struct r8152 *tp;
ebc2ec48 1210 int status = urb->status;
ac718b69 1211
ebc2ec48 1212 agg = urb->context;
1213 if (!agg)
ac718b69 1214 return;
1215
ebc2ec48 1216 tp = agg->context;
1217 if (!tp)
1218 return;
1219
d104eafa 1220 netdev = tp->netdev;
05e0f1aa 1221 stats = &netdev->stats;
ebc2ec48 1222 if (status) {
4a8deae2 1223 if (net_ratelimit())
d104eafa 1224 netdev_warn(netdev, "Tx status %d\n", status);
ebc2ec48 1225 stats->tx_errors += agg->skb_num;
ac718b69 1226 } else {
ebc2ec48 1227 stats->tx_packets += agg->skb_num;
1228 stats->tx_bytes += agg->skb_len;
ac718b69 1229 }
1230
2685d410 1231 spin_lock(&tp->tx_lock);
ebc2ec48 1232 list_add_tail(&agg->list, &tp->tx_free);
2685d410 1233 spin_unlock(&tp->tx_lock);
ebc2ec48 1234
9a4be1bd 1235 usb_autopm_put_interface_async(tp->intf);
1236
d104eafa 1237 if (!netif_carrier_ok(netdev))
ebc2ec48 1238 return;
1239
1240 if (!test_bit(WORK_ENABLE, &tp->flags))
1241 return;
1242
1243 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1244 return;
1245
1246 if (!skb_queue_empty(&tp->tx_queue))
d823ab68 1247 napi_schedule(&tp->napi);
ac718b69 1248}
1249
40a82917 1250static void intr_callback(struct urb *urb)
1251{
1252 struct r8152 *tp;
500b6d7e 1253 __le16 *d;
40a82917 1254 int status = urb->status;
1255 int res;
1256
1257 tp = urb->context;
1258 if (!tp)
1259 return;
1260
1261 if (!test_bit(WORK_ENABLE, &tp->flags))
1262 return;
1263
1264 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1265 return;
1266
1267 switch (status) {
1268 case 0: /* success */
1269 break;
1270 case -ECONNRESET: /* unlink */
1271 case -ESHUTDOWN:
1272 netif_device_detach(tp->netdev);
1273 case -ENOENT:
d59c876d 1274 case -EPROTO:
1275 netif_info(tp, intr, tp->netdev,
1276 "Stop submitting intr, status %d\n", status);
40a82917 1277 return;
1278 case -EOVERFLOW:
1279 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1280 goto resubmit;
1281 /* -EPIPE: should clear the halt */
1282 default:
1283 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1284 goto resubmit;
1285 }
1286
1287 d = urb->transfer_buffer;
1288 if (INTR_LINK & __le16_to_cpu(d[0])) {
51d979fa 1289 if (!netif_carrier_ok(tp->netdev)) {
40a82917 1290 set_bit(RTL8152_LINK_CHG, &tp->flags);
1291 schedule_delayed_work(&tp->schedule, 0);
1292 }
1293 } else {
51d979fa 1294 if (netif_carrier_ok(tp->netdev)) {
40a82917 1295 set_bit(RTL8152_LINK_CHG, &tp->flags);
1296 schedule_delayed_work(&tp->schedule, 0);
1297 }
1298 }
1299
1300resubmit:
1301 res = usb_submit_urb(urb, GFP_ATOMIC);
67610496 1302 if (res == -ENODEV) {
1303 set_bit(RTL8152_UNPLUG, &tp->flags);
40a82917 1304 netif_device_detach(tp->netdev);
67610496 1305 } else if (res) {
40a82917 1306 netif_err(tp, intr, tp->netdev,
4a8deae2 1307 "can't resubmit intr, status %d\n", res);
67610496 1308 }
40a82917 1309}
1310
ebc2ec48 1311static inline void *rx_agg_align(void *data)
1312{
8e1f51bd 1313 return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
ebc2ec48 1314}
1315
1316static inline void *tx_agg_align(void *data)
1317{
8e1f51bd 1318 return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
ebc2ec48 1319}
1320
1321static void free_all_mem(struct r8152 *tp)
1322{
1323 int i;
1324
1325 for (i = 0; i < RTL8152_MAX_RX; i++) {
9629e3c0 1326 usb_free_urb(tp->rx_info[i].urb);
1327 tp->rx_info[i].urb = NULL;
ebc2ec48 1328
9629e3c0 1329 kfree(tp->rx_info[i].buffer);
1330 tp->rx_info[i].buffer = NULL;
1331 tp->rx_info[i].head = NULL;
ebc2ec48 1332 }
1333
1334 for (i = 0; i < RTL8152_MAX_TX; i++) {
9629e3c0 1335 usb_free_urb(tp->tx_info[i].urb);
1336 tp->tx_info[i].urb = NULL;
ebc2ec48 1337
9629e3c0 1338 kfree(tp->tx_info[i].buffer);
1339 tp->tx_info[i].buffer = NULL;
1340 tp->tx_info[i].head = NULL;
ebc2ec48 1341 }
40a82917 1342
9629e3c0 1343 usb_free_urb(tp->intr_urb);
1344 tp->intr_urb = NULL;
40a82917 1345
9629e3c0 1346 kfree(tp->intr_buff);
1347 tp->intr_buff = NULL;
ebc2ec48 1348}
1349
1350static int alloc_all_mem(struct r8152 *tp)
1351{
1352 struct net_device *netdev = tp->netdev;
40a82917 1353 struct usb_interface *intf = tp->intf;
1354 struct usb_host_interface *alt = intf->cur_altsetting;
1355 struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
ebc2ec48 1356 struct urb *urb;
1357 int node, i;
1358 u8 *buf;
1359
1360 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1361
1362 spin_lock_init(&tp->rx_lock);
1363 spin_lock_init(&tp->tx_lock);
ebc2ec48 1364 INIT_LIST_HEAD(&tp->tx_free);
1365 skb_queue_head_init(&tp->tx_queue);
d823ab68 1366 skb_queue_head_init(&tp->rx_queue);
ebc2ec48 1367
1368 for (i = 0; i < RTL8152_MAX_RX; i++) {
52aec126 1369 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
ebc2ec48 1370 if (!buf)
1371 goto err1;
1372
1373 if (buf != rx_agg_align(buf)) {
1374 kfree(buf);
52aec126 1375 buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL,
8e1f51bd 1376 node);
ebc2ec48 1377 if (!buf)
1378 goto err1;
1379 }
1380
1381 urb = usb_alloc_urb(0, GFP_KERNEL);
1382 if (!urb) {
1383 kfree(buf);
1384 goto err1;
1385 }
1386
1387 INIT_LIST_HEAD(&tp->rx_info[i].list);
1388 tp->rx_info[i].context = tp;
1389 tp->rx_info[i].urb = urb;
1390 tp->rx_info[i].buffer = buf;
1391 tp->rx_info[i].head = rx_agg_align(buf);
1392 }
1393
1394 for (i = 0; i < RTL8152_MAX_TX; i++) {
52aec126 1395 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
ebc2ec48 1396 if (!buf)
1397 goto err1;
1398
1399 if (buf != tx_agg_align(buf)) {
1400 kfree(buf);
52aec126 1401 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
8e1f51bd 1402 node);
ebc2ec48 1403 if (!buf)
1404 goto err1;
1405 }
1406
1407 urb = usb_alloc_urb(0, GFP_KERNEL);
1408 if (!urb) {
1409 kfree(buf);
1410 goto err1;
1411 }
1412
1413 INIT_LIST_HEAD(&tp->tx_info[i].list);
1414 tp->tx_info[i].context = tp;
1415 tp->tx_info[i].urb = urb;
1416 tp->tx_info[i].buffer = buf;
1417 tp->tx_info[i].head = tx_agg_align(buf);
1418
1419 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1420 }
1421
40a82917 1422 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1423 if (!tp->intr_urb)
1424 goto err1;
1425
1426 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1427 if (!tp->intr_buff)
1428 goto err1;
1429
1430 tp->intr_interval = (int)ep_intr->desc.bInterval;
1431 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
b209af99 1432 tp->intr_buff, INTBUFSIZE, intr_callback,
1433 tp, tp->intr_interval);
40a82917 1434
ebc2ec48 1435 return 0;
1436
1437err1:
1438 free_all_mem(tp);
1439 return -ENOMEM;
1440}
1441
0de98f6c 1442static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1443{
1444 struct tx_agg *agg = NULL;
1445 unsigned long flags;
1446
21949ab7 1447 if (list_empty(&tp->tx_free))
1448 return NULL;
1449
0de98f6c 1450 spin_lock_irqsave(&tp->tx_lock, flags);
1451 if (!list_empty(&tp->tx_free)) {
1452 struct list_head *cursor;
1453
1454 cursor = tp->tx_free.next;
1455 list_del_init(cursor);
1456 agg = list_entry(cursor, struct tx_agg, list);
1457 }
1458 spin_unlock_irqrestore(&tp->tx_lock, flags);
1459
1460 return agg;
1461}
1462
b209af99 1463/* r8152_csum_workaround()
6128d1bb 1464 * The hw limites the value the transport offset. When the offset is out of the
1465 * range, calculate the checksum by sw.
1466 */
1467static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1468 struct sk_buff_head *list)
1469{
1470 if (skb_shinfo(skb)->gso_size) {
1471 netdev_features_t features = tp->netdev->features;
1472 struct sk_buff_head seg_list;
1473 struct sk_buff *segs, *nskb;
1474
a91d45f1 1475 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6128d1bb 1476 segs = skb_gso_segment(skb, features);
1477 if (IS_ERR(segs) || !segs)
1478 goto drop;
1479
1480 __skb_queue_head_init(&seg_list);
1481
1482 do {
1483 nskb = segs;
1484 segs = segs->next;
1485 nskb->next = NULL;
1486 __skb_queue_tail(&seg_list, nskb);
1487 } while (segs);
1488
1489 skb_queue_splice(&seg_list, list);
1490 dev_kfree_skb(skb);
1491 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1492 if (skb_checksum_help(skb) < 0)
1493 goto drop;
1494
1495 __skb_queue_head(list, skb);
1496 } else {
1497 struct net_device_stats *stats;
1498
1499drop:
1500 stats = &tp->netdev->stats;
1501 stats->tx_dropped++;
1502 dev_kfree_skb(skb);
1503 }
1504}
1505
b209af99 1506/* msdn_giant_send_check()
6128d1bb 1507 * According to the document of microsoft, the TCP Pseudo Header excludes the
1508 * packet length for IPv6 TCP large packets.
1509 */
1510static int msdn_giant_send_check(struct sk_buff *skb)
1511{
1512 const struct ipv6hdr *ipv6h;
1513 struct tcphdr *th;
fcb308d5 1514 int ret;
1515
1516 ret = skb_cow_head(skb, 0);
1517 if (ret)
1518 return ret;
6128d1bb 1519
1520 ipv6h = ipv6_hdr(skb);
1521 th = tcp_hdr(skb);
1522
1523 th->check = 0;
1524 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
1525
fcb308d5 1526 return ret;
6128d1bb 1527}
1528
c5554298 1529static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1530{
df8a39de 1531 if (skb_vlan_tag_present(skb)) {
c5554298 1532 u32 opts2;
1533
df8a39de 1534 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
c5554298 1535 desc->opts2 |= cpu_to_le32(opts2);
1536 }
1537}
1538
1539static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1540{
1541 u32 opts2 = le32_to_cpu(desc->opts2);
1542
1543 if (opts2 & RX_VLAN_TAG)
1544 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1545 swab16(opts2 & 0xffff));
1546}
1547
60c89071 1548static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1549 struct sk_buff *skb, u32 len, u32 transport_offset)
1550{
1551 u32 mss = skb_shinfo(skb)->gso_size;
1552 u32 opts1, opts2 = 0;
1553 int ret = TX_CSUM_SUCCESS;
1554
1555 WARN_ON_ONCE(len > TX_LEN_MAX);
1556
1557 opts1 = len | TX_FS | TX_LS;
1558
1559 if (mss) {
6128d1bb 1560 if (transport_offset > GTTCPHO_MAX) {
1561 netif_warn(tp, tx_err, tp->netdev,
1562 "Invalid transport offset 0x%x for TSO\n",
1563 transport_offset);
1564 ret = TX_CSUM_TSO;
1565 goto unavailable;
1566 }
1567
6e74d174 1568 switch (vlan_get_protocol(skb)) {
60c89071 1569 case htons(ETH_P_IP):
1570 opts1 |= GTSENDV4;
1571 break;
1572
6128d1bb 1573 case htons(ETH_P_IPV6):
fcb308d5 1574 if (msdn_giant_send_check(skb)) {
1575 ret = TX_CSUM_TSO;
1576 goto unavailable;
1577 }
6128d1bb 1578 opts1 |= GTSENDV6;
6128d1bb 1579 break;
1580
60c89071 1581 default:
1582 WARN_ON_ONCE(1);
1583 break;
1584 }
1585
1586 opts1 |= transport_offset << GTTCPHO_SHIFT;
1587 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
1588 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1589 u8 ip_protocol;
5bd23881 1590
6128d1bb 1591 if (transport_offset > TCPHO_MAX) {
1592 netif_warn(tp, tx_err, tp->netdev,
1593 "Invalid transport offset 0x%x\n",
1594 transport_offset);
1595 ret = TX_CSUM_NONE;
1596 goto unavailable;
1597 }
1598
6e74d174 1599 switch (vlan_get_protocol(skb)) {
5bd23881 1600 case htons(ETH_P_IP):
1601 opts2 |= IPV4_CS;
1602 ip_protocol = ip_hdr(skb)->protocol;
1603 break;
1604
1605 case htons(ETH_P_IPV6):
1606 opts2 |= IPV6_CS;
1607 ip_protocol = ipv6_hdr(skb)->nexthdr;
1608 break;
1609
1610 default:
1611 ip_protocol = IPPROTO_RAW;
1612 break;
1613 }
1614
60c89071 1615 if (ip_protocol == IPPROTO_TCP)
5bd23881 1616 opts2 |= TCP_CS;
60c89071 1617 else if (ip_protocol == IPPROTO_UDP)
5bd23881 1618 opts2 |= UDP_CS;
60c89071 1619 else
5bd23881 1620 WARN_ON_ONCE(1);
5bd23881 1621
60c89071 1622 opts2 |= transport_offset << TCPHO_SHIFT;
5bd23881 1623 }
60c89071 1624
1625 desc->opts2 = cpu_to_le32(opts2);
1626 desc->opts1 = cpu_to_le32(opts1);
1627
6128d1bb 1628unavailable:
60c89071 1629 return ret;
5bd23881 1630}
1631
b1379d9a 1632static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
1633{
d84130a1 1634 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
9a4be1bd 1635 int remain, ret;
b1379d9a 1636 u8 *tx_data;
1637
d84130a1 1638 __skb_queue_head_init(&skb_head);
0c3121fc 1639 spin_lock(&tx_queue->lock);
d84130a1 1640 skb_queue_splice_init(tx_queue, &skb_head);
0c3121fc 1641 spin_unlock(&tx_queue->lock);
d84130a1 1642
b1379d9a 1643 tx_data = agg->head;
b209af99 1644 agg->skb_num = 0;
1645 agg->skb_len = 0;
52aec126 1646 remain = agg_buf_sz;
b1379d9a 1647
7937f9e5 1648 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
b1379d9a 1649 struct tx_desc *tx_desc;
1650 struct sk_buff *skb;
1651 unsigned int len;
60c89071 1652 u32 offset;
b1379d9a 1653
d84130a1 1654 skb = __skb_dequeue(&skb_head);
b1379d9a 1655 if (!skb)
1656 break;
1657
60c89071 1658 len = skb->len + sizeof(*tx_desc);
1659
1660 if (len > remain) {
d84130a1 1661 __skb_queue_head(&skb_head, skb);
b1379d9a 1662 break;
1663 }
1664
7937f9e5 1665 tx_data = tx_agg_align(tx_data);
b1379d9a 1666 tx_desc = (struct tx_desc *)tx_data;
60c89071 1667
1668 offset = (u32)skb_transport_offset(skb);
1669
6128d1bb 1670 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
1671 r8152_csum_workaround(tp, skb, &skb_head);
1672 continue;
1673 }
60c89071 1674
c5554298 1675 rtl_tx_vlan_tag(tx_desc, skb);
1676
b1379d9a 1677 tx_data += sizeof(*tx_desc);
1678
60c89071 1679 len = skb->len;
1680 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
1681 struct net_device_stats *stats = &tp->netdev->stats;
1682
1683 stats->tx_dropped++;
1684 dev_kfree_skb_any(skb);
1685 tx_data -= sizeof(*tx_desc);
1686 continue;
1687 }
1688
1689 tx_data += len;
b1379d9a 1690 agg->skb_len += len;
60c89071 1691 agg->skb_num++;
1692
b1379d9a 1693 dev_kfree_skb_any(skb);
1694
52aec126 1695 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
b1379d9a 1696 }
1697
d84130a1 1698 if (!skb_queue_empty(&skb_head)) {
0c3121fc 1699 spin_lock(&tx_queue->lock);
d84130a1 1700 skb_queue_splice(&skb_head, tx_queue);
0c3121fc 1701 spin_unlock(&tx_queue->lock);
d84130a1 1702 }
1703
0c3121fc 1704 netif_tx_lock(tp->netdev);
dd1b119c 1705
1706 if (netif_queue_stopped(tp->netdev) &&
1707 skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
1708 netif_wake_queue(tp->netdev);
1709
0c3121fc 1710 netif_tx_unlock(tp->netdev);
9a4be1bd 1711
0c3121fc 1712 ret = usb_autopm_get_interface_async(tp->intf);
9a4be1bd 1713 if (ret < 0)
1714 goto out_tx_fill;
dd1b119c 1715
b1379d9a 1716 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1717 agg->head, (int)(tx_data - (u8 *)agg->head),
1718 (usb_complete_t)write_bulk_callback, agg);
1719
0c3121fc 1720 ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
9a4be1bd 1721 if (ret < 0)
0c3121fc 1722 usb_autopm_put_interface_async(tp->intf);
9a4be1bd 1723
1724out_tx_fill:
1725 return ret;
b1379d9a 1726}
1727
565cab0a 1728static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
1729{
1730 u8 checksum = CHECKSUM_NONE;
1731 u32 opts2, opts3;
1732
19c0f40d 1733 if (!(tp->netdev->features & NETIF_F_RXCSUM))
565cab0a 1734 goto return_result;
1735
1736 opts2 = le32_to_cpu(rx_desc->opts2);
1737 opts3 = le32_to_cpu(rx_desc->opts3);
1738
1739 if (opts2 & RD_IPV4_CS) {
1740 if (opts3 & IPF)
1741 checksum = CHECKSUM_NONE;
1742 else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF))
1743 checksum = CHECKSUM_NONE;
1744 else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF))
1745 checksum = CHECKSUM_NONE;
1746 else
1747 checksum = CHECKSUM_UNNECESSARY;
b9a321b4 1748 } else if (opts2 & RD_IPV6_CS) {
6128d1bb 1749 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1750 checksum = CHECKSUM_UNNECESSARY;
1751 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1752 checksum = CHECKSUM_UNNECESSARY;
565cab0a 1753 }
1754
1755return_result:
1756 return checksum;
1757}
1758
d823ab68 1759static int rx_bottom(struct r8152 *tp, int budget)
ebc2ec48 1760{
a5a4f468 1761 unsigned long flags;
d84130a1 1762 struct list_head *cursor, *next, rx_queue;
e1a2ca92 1763 int ret = 0, work_done = 0;
ce594e98 1764 struct napi_struct *napi = &tp->napi;
d823ab68 1765
1766 if (!skb_queue_empty(&tp->rx_queue)) {
1767 while (work_done < budget) {
1768 struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
1769 struct net_device *netdev = tp->netdev;
1770 struct net_device_stats *stats = &netdev->stats;
1771 unsigned int pkt_len;
1772
1773 if (!skb)
1774 break;
1775
1776 pkt_len = skb->len;
ce594e98 1777 napi_gro_receive(napi, skb);
d823ab68 1778 work_done++;
1779 stats->rx_packets++;
1780 stats->rx_bytes += pkt_len;
1781 }
1782 }
ebc2ec48 1783
d84130a1 1784 if (list_empty(&tp->rx_done))
d823ab68 1785 goto out1;
d84130a1 1786
1787 INIT_LIST_HEAD(&rx_queue);
a5a4f468 1788 spin_lock_irqsave(&tp->rx_lock, flags);
d84130a1 1789 list_splice_init(&tp->rx_done, &rx_queue);
1790 spin_unlock_irqrestore(&tp->rx_lock, flags);
1791
1792 list_for_each_safe(cursor, next, &rx_queue) {
43a4478d 1793 struct rx_desc *rx_desc;
1794 struct rx_agg *agg;
43a4478d 1795 int len_used = 0;
1796 struct urb *urb;
1797 u8 *rx_data;
43a4478d 1798
ebc2ec48 1799 list_del_init(cursor);
ebc2ec48 1800
1801 agg = list_entry(cursor, struct rx_agg, list);
1802 urb = agg->urb;
0de98f6c 1803 if (urb->actual_length < ETH_ZLEN)
1804 goto submit;
ebc2ec48 1805
ebc2ec48 1806 rx_desc = agg->head;
1807 rx_data = agg->head;
7937f9e5 1808 len_used += sizeof(struct rx_desc);
ebc2ec48 1809
7937f9e5 1810 while (urb->actual_length > len_used) {
43a4478d 1811 struct net_device *netdev = tp->netdev;
05e0f1aa 1812 struct net_device_stats *stats = &netdev->stats;
7937f9e5 1813 unsigned int pkt_len;
43a4478d 1814 struct sk_buff *skb;
1815
7937f9e5 1816 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
ebc2ec48 1817 if (pkt_len < ETH_ZLEN)
1818 break;
1819
7937f9e5 1820 len_used += pkt_len;
1821 if (urb->actual_length < len_used)
1822 break;
1823
8e1f51bd 1824 pkt_len -= CRC_SIZE;
ebc2ec48 1825 rx_data += sizeof(struct rx_desc);
1826
ce594e98 1827 skb = napi_alloc_skb(napi, pkt_len);
ebc2ec48 1828 if (!skb) {
1829 stats->rx_dropped++;
5e2f7485 1830 goto find_next_rx;
ebc2ec48 1831 }
565cab0a 1832
1833 skb->ip_summed = r8152_rx_csum(tp, rx_desc);
ebc2ec48 1834 memcpy(skb->data, rx_data, pkt_len);
1835 skb_put(skb, pkt_len);
1836 skb->protocol = eth_type_trans(skb, netdev);
c5554298 1837 rtl_rx_vlan_tag(rx_desc, skb);
d823ab68 1838 if (work_done < budget) {
ce594e98 1839 napi_gro_receive(napi, skb);
d823ab68 1840 work_done++;
1841 stats->rx_packets++;
1842 stats->rx_bytes += pkt_len;
1843 } else {
1844 __skb_queue_tail(&tp->rx_queue, skb);
1845 }
ebc2ec48 1846
5e2f7485 1847find_next_rx:
8e1f51bd 1848 rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE);
ebc2ec48 1849 rx_desc = (struct rx_desc *)rx_data;
ebc2ec48 1850 len_used = (int)(rx_data - (u8 *)agg->head);
7937f9e5 1851 len_used += sizeof(struct rx_desc);
ebc2ec48 1852 }
1853
0de98f6c 1854submit:
e1a2ca92 1855 if (!ret) {
1856 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
1857 } else {
1858 urb->actual_length = 0;
1859 list_add_tail(&agg->list, next);
1860 }
1861 }
1862
1863 if (!list_empty(&rx_queue)) {
1864 spin_lock_irqsave(&tp->rx_lock, flags);
1865 list_splice_tail(&rx_queue, &tp->rx_done);
1866 spin_unlock_irqrestore(&tp->rx_lock, flags);
ebc2ec48 1867 }
d823ab68 1868
1869out1:
1870 return work_done;
ebc2ec48 1871}
1872
1873static void tx_bottom(struct r8152 *tp)
1874{
ebc2ec48 1875 int res;
1876
b1379d9a 1877 do {
1878 struct tx_agg *agg;
ebc2ec48 1879
b1379d9a 1880 if (skb_queue_empty(&tp->tx_queue))
ebc2ec48 1881 break;
1882
b1379d9a 1883 agg = r8152_get_tx_agg(tp);
1884 if (!agg)
ebc2ec48 1885 break;
ebc2ec48 1886
b1379d9a 1887 res = r8152_tx_agg_fill(tp, agg);
1888 if (res) {
05e0f1aa 1889 struct net_device *netdev = tp->netdev;
ebc2ec48 1890
b1379d9a 1891 if (res == -ENODEV) {
67610496 1892 set_bit(RTL8152_UNPLUG, &tp->flags);
b1379d9a 1893 netif_device_detach(netdev);
1894 } else {
05e0f1aa 1895 struct net_device_stats *stats = &netdev->stats;
1896 unsigned long flags;
1897
b1379d9a 1898 netif_warn(tp, tx_err, netdev,
1899 "failed tx_urb %d\n", res);
1900 stats->tx_dropped += agg->skb_num;
db8515ef 1901
b1379d9a 1902 spin_lock_irqsave(&tp->tx_lock, flags);
1903 list_add_tail(&agg->list, &tp->tx_free);
1904 spin_unlock_irqrestore(&tp->tx_lock, flags);
1905 }
ebc2ec48 1906 }
b1379d9a 1907 } while (res == 0);
ebc2ec48 1908}
1909
d823ab68 1910static void bottom_half(struct r8152 *tp)
ac718b69 1911{
ebc2ec48 1912 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1913 return;
1914
1915 if (!test_bit(WORK_ENABLE, &tp->flags))
ac718b69 1916 return;
ebc2ec48 1917
7559fb2f 1918 /* When link down, the driver would cancel all bulks. */
1919 /* This avoid the re-submitting bulk */
ebc2ec48 1920 if (!netif_carrier_ok(tp->netdev))
ac718b69 1921 return;
ebc2ec48 1922
d823ab68 1923 clear_bit(SCHEDULE_NAPI, &tp->flags);
9451a11c 1924
0c3121fc 1925 tx_bottom(tp);
ebc2ec48 1926}
1927
d823ab68 1928static int r8152_poll(struct napi_struct *napi, int budget)
1929{
1930 struct r8152 *tp = container_of(napi, struct r8152, napi);
1931 int work_done;
1932
1933 work_done = rx_bottom(tp, budget);
1934 bottom_half(tp);
1935
1936 if (work_done < budget) {
1937 napi_complete(napi);
1938 if (!list_empty(&tp->rx_done))
1939 napi_schedule(napi);
248b213a 1940 else if (!skb_queue_empty(&tp->tx_queue) &&
1941 !list_empty(&tp->tx_free))
1942 napi_schedule(napi);
d823ab68 1943 }
1944
1945 return work_done;
1946}
1947
ebc2ec48 1948static
1949int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
1950{
a0fccd48 1951 int ret;
1952
ef827a5b 1953 /* The rx would be stopped, so skip submitting */
1954 if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
1955 !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
1956 return 0;
1957
ebc2ec48 1958 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
52aec126 1959 agg->head, agg_buf_sz,
b209af99 1960 (usb_complete_t)read_bulk_callback, agg);
ebc2ec48 1961
a0fccd48 1962 ret = usb_submit_urb(agg->urb, mem_flags);
1963 if (ret == -ENODEV) {
1964 set_bit(RTL8152_UNPLUG, &tp->flags);
1965 netif_device_detach(tp->netdev);
1966 } else if (ret) {
1967 struct urb *urb = agg->urb;
1968 unsigned long flags;
1969
1970 urb->actual_length = 0;
1971 spin_lock_irqsave(&tp->rx_lock, flags);
1972 list_add_tail(&agg->list, &tp->rx_done);
1973 spin_unlock_irqrestore(&tp->rx_lock, flags);
d823ab68 1974
1975 netif_err(tp, rx_err, tp->netdev,
1976 "Couldn't submit rx[%p], ret = %d\n", agg, ret);
1977
1978 napi_schedule(&tp->napi);
a0fccd48 1979 }
1980
1981 return ret;
ac718b69 1982}
1983
00a5e360 1984static void rtl_drop_queued_tx(struct r8152 *tp)
1985{
1986 struct net_device_stats *stats = &tp->netdev->stats;
d84130a1 1987 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
00a5e360 1988 struct sk_buff *skb;
1989
d84130a1 1990 if (skb_queue_empty(tx_queue))
1991 return;
1992
1993 __skb_queue_head_init(&skb_head);
2685d410 1994 spin_lock_bh(&tx_queue->lock);
d84130a1 1995 skb_queue_splice_init(tx_queue, &skb_head);
2685d410 1996 spin_unlock_bh(&tx_queue->lock);
d84130a1 1997
1998 while ((skb = __skb_dequeue(&skb_head))) {
00a5e360 1999 dev_kfree_skb(skb);
2000 stats->tx_dropped++;
2001 }
2002}
2003
ac718b69 2004static void rtl8152_tx_timeout(struct net_device *netdev)
2005{
2006 struct r8152 *tp = netdev_priv(netdev);
ebc2ec48 2007
4a8deae2 2008 netif_warn(tp, tx_err, netdev, "Tx timeout\n");
37608f3e 2009
2010 usb_queue_reset_device(tp->intf);
ac718b69 2011}
2012
2013static void rtl8152_set_rx_mode(struct net_device *netdev)
2014{
2015 struct r8152 *tp = netdev_priv(netdev);
2016
51d979fa 2017 if (netif_carrier_ok(netdev)) {
ac718b69 2018 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
40a82917 2019 schedule_delayed_work(&tp->schedule, 0);
2020 }
ac718b69 2021}
2022
2023static void _rtl8152_set_rx_mode(struct net_device *netdev)
2024{
2025 struct r8152 *tp = netdev_priv(netdev);
31787f53 2026 u32 mc_filter[2]; /* Multicast hash filter */
2027 __le32 tmp[2];
ac718b69 2028 u32 ocp_data;
2029
ac718b69 2030 netif_stop_queue(netdev);
2031 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2032 ocp_data &= ~RCR_ACPT_ALL;
2033 ocp_data |= RCR_AB | RCR_APM;
2034
2035 if (netdev->flags & IFF_PROMISC) {
2036 /* Unconditionally log net taps. */
2037 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
2038 ocp_data |= RCR_AM | RCR_AAP;
b209af99 2039 mc_filter[1] = 0xffffffff;
2040 mc_filter[0] = 0xffffffff;
ac718b69 2041 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
2042 (netdev->flags & IFF_ALLMULTI)) {
2043 /* Too many to filter perfectly -- accept all multicasts. */
2044 ocp_data |= RCR_AM;
b209af99 2045 mc_filter[1] = 0xffffffff;
2046 mc_filter[0] = 0xffffffff;
ac718b69 2047 } else {
2048 struct netdev_hw_addr *ha;
2049
b209af99 2050 mc_filter[1] = 0;
2051 mc_filter[0] = 0;
ac718b69 2052 netdev_for_each_mc_addr(ha, netdev) {
2053 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
b209af99 2054
ac718b69 2055 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2056 ocp_data |= RCR_AM;
2057 }
2058 }
2059
31787f53 2060 tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
2061 tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
ac718b69 2062
31787f53 2063 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
ac718b69 2064 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2065 netif_wake_queue(netdev);
ac718b69 2066}
2067
a5e31255 2068static netdev_features_t
2069rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
2070 netdev_features_t features)
2071{
2072 u32 mss = skb_shinfo(skb)->gso_size;
2073 int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
2074 int offset = skb_transport_offset(skb);
2075
2076 if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
a188222b 2077 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
a5e31255 2078 else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
2079 features &= ~NETIF_F_GSO_MASK;
2080
2081 return features;
2082}
2083
ac718b69 2084static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
b209af99 2085 struct net_device *netdev)
ac718b69 2086{
2087 struct r8152 *tp = netdev_priv(netdev);
ac718b69 2088
ebc2ec48 2089 skb_tx_timestamp(skb);
ac718b69 2090
61598788 2091 skb_queue_tail(&tp->tx_queue, skb);
ebc2ec48 2092
0c3121fc 2093 if (!list_empty(&tp->tx_free)) {
2094 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
d823ab68 2095 set_bit(SCHEDULE_NAPI, &tp->flags);
0c3121fc 2096 schedule_delayed_work(&tp->schedule, 0);
2097 } else {
2098 usb_mark_last_busy(tp->udev);
d823ab68 2099 napi_schedule(&tp->napi);
0c3121fc 2100 }
b209af99 2101 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
dd1b119c 2102 netif_stop_queue(netdev);
b209af99 2103 }
dd1b119c 2104
ac718b69 2105 return NETDEV_TX_OK;
2106}
2107
2108static void r8152b_reset_packet_filter(struct r8152 *tp)
2109{
2110 u32 ocp_data;
2111
2112 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
2113 ocp_data &= ~FMC_FCR_MCU_EN;
2114 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2115 ocp_data |= FMC_FCR_MCU_EN;
2116 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2117}
2118
2119static void rtl8152_nic_reset(struct r8152 *tp)
2120{
2121 int i;
2122
2123 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
2124
2125 for (i = 0; i < 1000; i++) {
2126 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
2127 break;
b209af99 2128 usleep_range(100, 400);
ac718b69 2129 }
2130}
2131
dd1b119c 2132static void set_tx_qlen(struct r8152 *tp)
2133{
2134 struct net_device *netdev = tp->netdev;
2135
52aec126 2136 tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN +
2137 sizeof(struct tx_desc));
dd1b119c 2138}
2139
ac718b69 2140static inline u8 rtl8152_get_speed(struct r8152 *tp)
2141{
2142 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
2143}
2144
507605a8 2145static void rtl_set_eee_plus(struct r8152 *tp)
ac718b69 2146{
ebc2ec48 2147 u32 ocp_data;
ac718b69 2148 u8 speed;
2149
2150 speed = rtl8152_get_speed(tp);
ebc2ec48 2151 if (speed & _10bps) {
ac718b69 2152 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
ebc2ec48 2153 ocp_data |= EEEP_CR_EEEP_TX;
ac718b69 2154 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2155 } else {
2156 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
ebc2ec48 2157 ocp_data &= ~EEEP_CR_EEEP_TX;
ac718b69 2158 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2159 }
507605a8 2160}
2161
00a5e360 2162static void rxdy_gated_en(struct r8152 *tp, bool enable)
2163{
2164 u32 ocp_data;
2165
2166 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
2167 if (enable)
2168 ocp_data |= RXDY_GATED_EN;
2169 else
2170 ocp_data &= ~RXDY_GATED_EN;
2171 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2172}
2173
445f7f4d 2174static int rtl_start_rx(struct r8152 *tp)
2175{
2176 int i, ret = 0;
2177
2178 INIT_LIST_HEAD(&tp->rx_done);
2179 for (i = 0; i < RTL8152_MAX_RX; i++) {
2180 INIT_LIST_HEAD(&tp->rx_info[i].list);
2181 ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
2182 if (ret)
2183 break;
2184 }
2185
7bcf4f60 2186 if (ret && ++i < RTL8152_MAX_RX) {
2187 struct list_head rx_queue;
2188 unsigned long flags;
2189
2190 INIT_LIST_HEAD(&rx_queue);
2191
2192 do {
2193 struct rx_agg *agg = &tp->rx_info[i++];
2194 struct urb *urb = agg->urb;
2195
2196 urb->actual_length = 0;
2197 list_add_tail(&agg->list, &rx_queue);
2198 } while (i < RTL8152_MAX_RX);
2199
2200 spin_lock_irqsave(&tp->rx_lock, flags);
2201 list_splice_tail(&rx_queue, &tp->rx_done);
2202 spin_unlock_irqrestore(&tp->rx_lock, flags);
2203 }
2204
445f7f4d 2205 return ret;
2206}
2207
2208static int rtl_stop_rx(struct r8152 *tp)
2209{
2210 int i;
2211
2212 for (i = 0; i < RTL8152_MAX_RX; i++)
2213 usb_kill_urb(tp->rx_info[i].urb);
2214
d823ab68 2215 while (!skb_queue_empty(&tp->rx_queue))
2216 dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
2217
445f7f4d 2218 return 0;
2219}
2220
507605a8 2221static int rtl_enable(struct r8152 *tp)
2222{
2223 u32 ocp_data;
ac718b69 2224
2225 r8152b_reset_packet_filter(tp);
2226
2227 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2228 ocp_data |= CR_RE | CR_TE;
2229 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2230
00a5e360 2231 rxdy_gated_en(tp, false);
ac718b69 2232
aa2e0926 2233 return 0;
ac718b69 2234}
2235
507605a8 2236static int rtl8152_enable(struct r8152 *tp)
2237{
6871438c 2238 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2239 return -ENODEV;
2240
507605a8 2241 set_tx_qlen(tp);
2242 rtl_set_eee_plus(tp);
2243
2244 return rtl_enable(tp);
2245}
2246
464ec10a 2247static void r8153_set_rx_early_timeout(struct r8152 *tp)
43779f8d 2248{
464ec10a 2249 u32 ocp_data = tp->coalesce / 8;
43779f8d 2250
464ec10a 2251 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, ocp_data);
2252}
2253
2254static void r8153_set_rx_early_size(struct r8152 *tp)
2255{
2256 u32 mtu = tp->netdev->mtu;
a59e6d81 2257 u32 ocp_data = (agg_buf_sz - mtu - VLAN_ETH_HLEN - VLAN_HLEN) / 8;
464ec10a 2258
2259 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, ocp_data);
43779f8d 2260}
2261
2262static int rtl8153_enable(struct r8152 *tp)
2263{
6871438c 2264 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2265 return -ENODEV;
2266
b214396f 2267 usb_disable_lpm(tp->udev);
43779f8d 2268 set_tx_qlen(tp);
2269 rtl_set_eee_plus(tp);
464ec10a 2270 r8153_set_rx_early_timeout(tp);
2271 r8153_set_rx_early_size(tp);
43779f8d 2272
2273 return rtl_enable(tp);
2274}
2275
d70b1137 2276static void rtl_disable(struct r8152 *tp)
ac718b69 2277{
ebc2ec48 2278 u32 ocp_data;
2279 int i;
ac718b69 2280
6871438c 2281 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2282 rtl_drop_queued_tx(tp);
2283 return;
2284 }
2285
ac718b69 2286 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2287 ocp_data &= ~RCR_ACPT_ALL;
2288 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2289
00a5e360 2290 rtl_drop_queued_tx(tp);
ebc2ec48 2291
2292 for (i = 0; i < RTL8152_MAX_TX; i++)
2293 usb_kill_urb(tp->tx_info[i].urb);
ac718b69 2294
00a5e360 2295 rxdy_gated_en(tp, true);
ac718b69 2296
2297 for (i = 0; i < 1000; i++) {
2298 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2299 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2300 break;
8ddfa077 2301 usleep_range(1000, 2000);
ac718b69 2302 }
2303
2304 for (i = 0; i < 1000; i++) {
2305 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2306 break;
8ddfa077 2307 usleep_range(1000, 2000);
ac718b69 2308 }
2309
445f7f4d 2310 rtl_stop_rx(tp);
ac718b69 2311
2312 rtl8152_nic_reset(tp);
2313}
2314
00a5e360 2315static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2316{
2317 u32 ocp_data;
2318
2319 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2320 if (enable)
2321 ocp_data |= POWER_CUT;
2322 else
2323 ocp_data &= ~POWER_CUT;
2324 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2325
2326 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2327 ocp_data &= ~RESUME_INDICATE;
2328 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
00a5e360 2329}
2330
c5554298 2331static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2332{
2333 u32 ocp_data;
2334
2335 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2336 if (enable)
2337 ocp_data |= CPCR_RX_VLAN;
2338 else
2339 ocp_data &= ~CPCR_RX_VLAN;
2340 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2341}
2342
2343static int rtl8152_set_features(struct net_device *dev,
2344 netdev_features_t features)
2345{
2346 netdev_features_t changed = features ^ dev->features;
2347 struct r8152 *tp = netdev_priv(dev);
405f8a0e 2348 int ret;
2349
2350 ret = usb_autopm_get_interface(tp->intf);
2351 if (ret < 0)
2352 goto out;
c5554298 2353
b5403273 2354 mutex_lock(&tp->control);
2355
c5554298 2356 if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2357 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2358 rtl_rx_vlan_en(tp, true);
2359 else
2360 rtl_rx_vlan_en(tp, false);
2361 }
2362
b5403273 2363 mutex_unlock(&tp->control);
2364
405f8a0e 2365 usb_autopm_put_interface(tp->intf);
2366
2367out:
2368 return ret;
c5554298 2369}
2370
21ff2e89 2371#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2372
2373static u32 __rtl_get_wol(struct r8152 *tp)
2374{
2375 u32 ocp_data;
2376 u32 wolopts = 0;
2377
21ff2e89 2378 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2379 if (ocp_data & LINK_ON_WAKE_EN)
2380 wolopts |= WAKE_PHY;
2381
2382 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2383 if (ocp_data & UWF_EN)
2384 wolopts |= WAKE_UCAST;
2385 if (ocp_data & BWF_EN)
2386 wolopts |= WAKE_BCAST;
2387 if (ocp_data & MWF_EN)
2388 wolopts |= WAKE_MCAST;
2389
2390 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2391 if (ocp_data & MAGIC_EN)
2392 wolopts |= WAKE_MAGIC;
2393
2394 return wolopts;
2395}
2396
2397static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
2398{
2399 u32 ocp_data;
2400
2401 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2402
2403 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2404 ocp_data &= ~LINK_ON_WAKE_EN;
2405 if (wolopts & WAKE_PHY)
2406 ocp_data |= LINK_ON_WAKE_EN;
2407 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2408
2409 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
92f7d07d 2410 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);
21ff2e89 2411 if (wolopts & WAKE_UCAST)
2412 ocp_data |= UWF_EN;
2413 if (wolopts & WAKE_BCAST)
2414 ocp_data |= BWF_EN;
2415 if (wolopts & WAKE_MCAST)
2416 ocp_data |= MWF_EN;
21ff2e89 2417 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
2418
2419 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2420
2421 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2422 ocp_data &= ~MAGIC_EN;
2423 if (wolopts & WAKE_MAGIC)
2424 ocp_data |= MAGIC_EN;
2425 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
2426
2427 if (wolopts & WAKE_ANY)
2428 device_set_wakeup_enable(&tp->udev->dev, true);
2429 else
2430 device_set_wakeup_enable(&tp->udev->dev, false);
2431}
2432
b214396f 2433static void r8153_u1u2en(struct r8152 *tp, bool enable)
2434{
2435 u8 u1u2[8];
2436
2437 if (enable)
2438 memset(u1u2, 0xff, sizeof(u1u2));
2439 else
2440 memset(u1u2, 0x00, sizeof(u1u2));
2441
2442 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
2443}
2444
2445static void r8153_u2p3en(struct r8152 *tp, bool enable)
2446{
2447 u32 ocp_data;
2448
2449 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
2450 if (enable && tp->version != RTL_VER_03 && tp->version != RTL_VER_04)
2451 ocp_data |= U2P3_ENABLE;
2452 else
2453 ocp_data &= ~U2P3_ENABLE;
2454 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
2455}
2456
2457static void r8153_power_cut_en(struct r8152 *tp, bool enable)
2458{
2459 u32 ocp_data;
2460
2461 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2462 if (enable)
2463 ocp_data |= PWR_EN | PHASE2_EN;
2464 else
2465 ocp_data &= ~(PWR_EN | PHASE2_EN);
2466 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2467
2468 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2469 ocp_data &= ~PCUT_STATUS;
2470 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2471}
2472
7daed8dc 2473static bool rtl_can_wakeup(struct r8152 *tp)
2474{
2475 struct usb_device *udev = tp->udev;
2476
2477 return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
2478}
2479
9a4be1bd 2480static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
2481{
2482 if (enable) {
2483 u32 ocp_data;
2484
2485 __rtl_set_wol(tp, WAKE_ANY);
2486
2487 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2488
2489 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2490 ocp_data |= LINK_OFF_WAKE_EN;
2491 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2492
2493 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2494 } else {
f95ae8a0 2495 u32 ocp_data;
2496
9a4be1bd 2497 __rtl_set_wol(tp, tp->saved_wolopts);
f95ae8a0 2498
2499 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2500
2501 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2502 ocp_data &= ~LINK_OFF_WAKE_EN;
2503 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2504
2505 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2609af19 2506 }
2507}
f95ae8a0 2508
2609af19 2509static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
2510{
2511 rtl_runtime_suspend_enable(tp, enable);
2512
2513 if (enable) {
2514 r8153_u1u2en(tp, false);
2515 r8153_u2p3en(tp, false);
2516 } else {
b214396f 2517 r8153_u2p3en(tp, true);
2518 r8153_u1u2en(tp, true);
9a4be1bd 2519 }
2520}
2521
4349968a 2522static void r8153_teredo_off(struct r8152 *tp)
2523{
2524 u32 ocp_data;
2525
2526 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2527 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN);
2528 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2529
2530 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
2531 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
2532 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
2533}
2534
93fe9b18 2535static void rtl_reset_bmu(struct r8152 *tp)
2536{
2537 u32 ocp_data;
2538
2539 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
2540 ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
2541 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2542 ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
2543 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2544}
2545
cda9fb01 2546static void r8152_aldps_en(struct r8152 *tp, bool enable)
4349968a 2547{
cda9fb01 2548 if (enable) {
2549 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
2550 LINKENA | DIS_SDSAVE);
2551 } else {
2552 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
2553 DIS_SDSAVE);
2554 msleep(20);
2555 }
4349968a 2556}
2557
e6449539 2558static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
2559{
2560 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
2561 ocp_reg_write(tp, OCP_EEE_DATA, reg);
2562 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
2563}
2564
2565static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
2566{
2567 u16 data;
2568
2569 r8152_mmd_indirect(tp, dev, reg);
2570 data = ocp_reg_read(tp, OCP_EEE_DATA);
2571 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
2572
2573 return data;
2574}
2575
2576static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
2577{
2578 r8152_mmd_indirect(tp, dev, reg);
2579 ocp_reg_write(tp, OCP_EEE_DATA, data);
2580 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
2581}
2582
2583static void r8152_eee_en(struct r8152 *tp, bool enable)
2584{
2585 u16 config1, config2, config3;
2586 u32 ocp_data;
2587
2588 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
2589 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
2590 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
2591 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
2592
2593 if (enable) {
2594 ocp_data |= EEE_RX_EN | EEE_TX_EN;
2595 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
2596 config1 |= sd_rise_time(1);
2597 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
2598 config3 |= fast_snr(42);
2599 } else {
2600 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
2601 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
2602 RX_QUIET_EN);
2603 config1 |= sd_rise_time(7);
2604 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
2605 config3 |= fast_snr(511);
2606 }
2607
2608 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
2609 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
2610 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
2611 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
2612}
2613
2614static void r8152b_enable_eee(struct r8152 *tp)
2615{
2616 r8152_eee_en(tp, true);
2617 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
2618}
2619
2620static void r8152b_enable_fc(struct r8152 *tp)
2621{
2622 u16 anar;
2623
2624 anar = r8152_mdio_read(tp, MII_ADVERTISE);
2625 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
2626 r8152_mdio_write(tp, MII_ADVERTISE, anar);
2627}
2628
d70b1137 2629static void rtl8152_disable(struct r8152 *tp)
2630{
cda9fb01 2631 r8152_aldps_en(tp, false);
d70b1137 2632 rtl_disable(tp);
cda9fb01 2633 r8152_aldps_en(tp, true);
d70b1137 2634}
2635
4349968a 2636static void r8152b_hw_phy_cfg(struct r8152 *tp)
2637{
ef39df8e 2638 r8152b_enable_eee(tp);
2639 r8152_aldps_en(tp, true);
2640 r8152b_enable_fc(tp);
f0cbe0ac 2641
aa66a5f1 2642 set_bit(PHY_RESET, &tp->flags);
4349968a 2643}
2644
ac718b69 2645static void r8152b_exit_oob(struct r8152 *tp)
2646{
db8515ef 2647 u32 ocp_data;
2648 int i;
ac718b69 2649
2650 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2651 ocp_data &= ~RCR_ACPT_ALL;
2652 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2653
00a5e360 2654 rxdy_gated_en(tp, true);
da9bd117 2655 r8153_teredo_off(tp);
ac718b69 2656 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2657 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
2658
2659 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2660 ocp_data &= ~NOW_IS_OOB;
2661 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2662
2663 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2664 ocp_data &= ~MCU_BORW_EN;
2665 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2666
2667 for (i = 0; i < 1000; i++) {
2668 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2669 if (ocp_data & LINK_LIST_READY)
2670 break;
8ddfa077 2671 usleep_range(1000, 2000);
ac718b69 2672 }
2673
2674 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2675 ocp_data |= RE_INIT_LL;
2676 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2677
2678 for (i = 0; i < 1000; i++) {
2679 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2680 if (ocp_data & LINK_LIST_READY)
2681 break;
8ddfa077 2682 usleep_range(1000, 2000);
ac718b69 2683 }
2684
2685 rtl8152_nic_reset(tp);
2686
2687 /* rx share fifo credit full threshold */
2688 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2689
a3cc465d 2690 if (tp->udev->speed == USB_SPEED_FULL ||
2691 tp->udev->speed == USB_SPEED_LOW) {
ac718b69 2692 /* rx share fifo credit near full threshold */
2693 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2694 RXFIFO_THR2_FULL);
2695 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2696 RXFIFO_THR3_FULL);
2697 } else {
2698 /* rx share fifo credit near full threshold */
2699 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2700 RXFIFO_THR2_HIGH);
2701 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2702 RXFIFO_THR3_HIGH);
2703 }
2704
2705 /* TX share fifo free credit full threshold */
2706 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
2707
2708 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
8e1f51bd 2709 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
ac718b69 2710 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
2711 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
2712
c5554298 2713 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
ac718b69 2714
2715 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2716
2717 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2718 ocp_data |= TCR0_AUTO_FIFO;
2719 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2720}
2721
2722static void r8152b_enter_oob(struct r8152 *tp)
2723{
45f4a19f 2724 u32 ocp_data;
2725 int i;
ac718b69 2726
2727 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2728 ocp_data &= ~NOW_IS_OOB;
2729 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2730
2731 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
2732 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
2733 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
2734
d70b1137 2735 rtl_disable(tp);
ac718b69 2736
2737 for (i = 0; i < 1000; i++) {
2738 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2739 if (ocp_data & LINK_LIST_READY)
2740 break;
8ddfa077 2741 usleep_range(1000, 2000);
ac718b69 2742 }
2743
2744 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2745 ocp_data |= RE_INIT_LL;
2746 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2747
2748 for (i = 0; i < 1000; i++) {
2749 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2750 if (ocp_data & LINK_LIST_READY)
2751 break;
8ddfa077 2752 usleep_range(1000, 2000);
ac718b69 2753 }
2754
2755 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2756
c5554298 2757 rtl_rx_vlan_en(tp, true);
ac718b69 2758
2759 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2760 ocp_data |= ALDPS_PROXY_MODE;
2761 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2762
2763 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2764 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2765 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2766
00a5e360 2767 rxdy_gated_en(tp, false);
ac718b69 2768
2769 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2770 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2771 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2772}
2773
e6449539 2774static void r8153_aldps_en(struct r8152 *tp, bool enable)
2775{
2776 u16 data;
2777
2778 data = ocp_reg_read(tp, OCP_POWER_CFG);
2779 if (enable) {
2780 data |= EN_ALDPS;
2781 ocp_reg_write(tp, OCP_POWER_CFG, data);
2782 } else {
2783 data &= ~EN_ALDPS;
2784 ocp_reg_write(tp, OCP_POWER_CFG, data);
2785 msleep(20);
2786 }
2787}
2788
2789static void r8153_eee_en(struct r8152 *tp, bool enable)
2790{
2791 u32 ocp_data;
2792 u16 config;
2793
2794 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
2795 config = ocp_reg_read(tp, OCP_EEE_CFG);
2796
2797 if (enable) {
2798 ocp_data |= EEE_RX_EN | EEE_TX_EN;
2799 config |= EEE10_EN;
2800 } else {
2801 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
2802 config &= ~EEE10_EN;
2803 }
2804
2805 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
2806 ocp_reg_write(tp, OCP_EEE_CFG, config);
2807}
2808
43779f8d 2809static void r8153_hw_phy_cfg(struct r8152 *tp)
2810{
2811 u32 ocp_data;
2812 u16 data;
2813
d768c61b 2814 /* disable ALDPS before updating the PHY parameters */
2815 r8153_aldps_en(tp, false);
fb02eb4a 2816
d768c61b 2817 /* disable EEE before updating the PHY parameters */
2818 r8153_eee_en(tp, false);
2819 ocp_reg_write(tp, OCP_EEE_ADV, 0);
43779f8d 2820
2821 if (tp->version == RTL_VER_03) {
2822 data = ocp_reg_read(tp, OCP_EEE_CFG);
2823 data &= ~CTAP_SHORT_EN;
2824 ocp_reg_write(tp, OCP_EEE_CFG, data);
2825 }
2826
2827 data = ocp_reg_read(tp, OCP_POWER_CFG);
2828 data |= EEE_CLKDIV_EN;
2829 ocp_reg_write(tp, OCP_POWER_CFG, data);
2830
2831 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
2832 data |= EN_10M_BGOFF;
2833 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
2834 data = ocp_reg_read(tp, OCP_POWER_CFG);
2835 data |= EN_10M_PLLOFF;
2836 ocp_reg_write(tp, OCP_POWER_CFG, data);
b4d99def 2837 sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
43779f8d 2838
2839 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
2840 ocp_data |= PFM_PWM_SWITCH;
2841 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
2842
b4d99def 2843 /* Enable LPF corner auto tune */
2844 sram_write(tp, SRAM_LPF_CFG, 0xf70f);
43779f8d 2845
b4d99def 2846 /* Adjust 10M Amplitude */
2847 sram_write(tp, SRAM_10M_AMP1, 0x00af);
2848 sram_write(tp, SRAM_10M_AMP2, 0x0208);
aa66a5f1 2849
af0287ec 2850 r8153_eee_en(tp, true);
2851 ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
2852
ef39df8e 2853 r8153_aldps_en(tp, true);
2854 r8152b_enable_fc(tp);
2855
aa66a5f1 2856 set_bit(PHY_RESET, &tp->flags);
43779f8d 2857}
2858
43779f8d 2859static void r8153_first_init(struct r8152 *tp)
2860{
2861 u32 ocp_data;
2862 int i;
2863
00a5e360 2864 rxdy_gated_en(tp, true);
43779f8d 2865 r8153_teredo_off(tp);
2866
2867 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2868 ocp_data &= ~RCR_ACPT_ALL;
2869 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2870
43779f8d 2871 rtl8152_nic_reset(tp);
93fe9b18 2872 rtl_reset_bmu(tp);
43779f8d 2873
2874 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2875 ocp_data &= ~NOW_IS_OOB;
2876 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2877
2878 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2879 ocp_data &= ~MCU_BORW_EN;
2880 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2881
2882 for (i = 0; i < 1000; i++) {
2883 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2884 if (ocp_data & LINK_LIST_READY)
2885 break;
8ddfa077 2886 usleep_range(1000, 2000);
43779f8d 2887 }
2888
2889 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2890 ocp_data |= RE_INIT_LL;
2891 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2892
2893 for (i = 0; i < 1000; i++) {
2894 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2895 if (ocp_data & LINK_LIST_READY)
2896 break;
8ddfa077 2897 usleep_range(1000, 2000);
43779f8d 2898 }
2899
c5554298 2900 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
43779f8d 2901
69b4b7a4 2902 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
2903 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
43779f8d 2904
2905 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2906 ocp_data |= TCR0_AUTO_FIFO;
2907 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2908
2909 rtl8152_nic_reset(tp);
2910
2911 /* rx share fifo credit full threshold */
2912 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2913 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
2914 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
2915 /* TX share fifo free credit full threshold */
2916 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
2917
9629e3c0 2918 /* rx aggregation */
43779f8d 2919 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
e90fba8d 2920 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
43779f8d 2921 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2922}
2923
2924static void r8153_enter_oob(struct r8152 *tp)
2925{
2926 u32 ocp_data;
2927 int i;
2928
2929 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2930 ocp_data &= ~NOW_IS_OOB;
2931 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2932
d70b1137 2933 rtl_disable(tp);
93fe9b18 2934 rtl_reset_bmu(tp);
43779f8d 2935
2936 for (i = 0; i < 1000; i++) {
2937 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2938 if (ocp_data & LINK_LIST_READY)
2939 break;
8ddfa077 2940 usleep_range(1000, 2000);
43779f8d 2941 }
2942
2943 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2944 ocp_data |= RE_INIT_LL;
2945 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2946
2947 for (i = 0; i < 1000; i++) {
2948 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2949 if (ocp_data & LINK_LIST_READY)
2950 break;
8ddfa077 2951 usleep_range(1000, 2000);
43779f8d 2952 }
2953
69b4b7a4 2954 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
43779f8d 2955
43779f8d 2956 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2957 ocp_data &= ~TEREDO_WAKE_MASK;
2958 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2959
c5554298 2960 rtl_rx_vlan_en(tp, true);
43779f8d 2961
2962 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2963 ocp_data |= ALDPS_PROXY_MODE;
2964 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2965
2966 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2967 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2968 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2969
00a5e360 2970 rxdy_gated_en(tp, false);
43779f8d 2971
2972 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2973 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2974 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2975}
2976
d70b1137 2977static void rtl8153_disable(struct r8152 *tp)
2978{
cda9fb01 2979 r8153_aldps_en(tp, false);
d70b1137 2980 rtl_disable(tp);
93fe9b18 2981 rtl_reset_bmu(tp);
cda9fb01 2982 r8153_aldps_en(tp, true);
b214396f 2983 usb_enable_lpm(tp->udev);
d70b1137 2984}
2985
ac718b69 2986static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
2987{
43779f8d 2988 u16 bmcr, anar, gbcr;
ac718b69 2989 int ret = 0;
2990
ac718b69 2991 anar = r8152_mdio_read(tp, MII_ADVERTISE);
2992 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
2993 ADVERTISE_100HALF | ADVERTISE_100FULL);
43779f8d 2994 if (tp->mii.supports_gmii) {
2995 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
2996 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
2997 } else {
2998 gbcr = 0;
2999 }
ac718b69 3000
3001 if (autoneg == AUTONEG_DISABLE) {
3002 if (speed == SPEED_10) {
3003 bmcr = 0;
3004 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3005 } else if (speed == SPEED_100) {
3006 bmcr = BMCR_SPEED100;
3007 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
43779f8d 3008 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
3009 bmcr = BMCR_SPEED1000;
3010 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
ac718b69 3011 } else {
3012 ret = -EINVAL;
3013 goto out;
3014 }
3015
3016 if (duplex == DUPLEX_FULL)
3017 bmcr |= BMCR_FULLDPLX;
3018 } else {
3019 if (speed == SPEED_10) {
3020 if (duplex == DUPLEX_FULL)
3021 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3022 else
3023 anar |= ADVERTISE_10HALF;
3024 } else if (speed == SPEED_100) {
3025 if (duplex == DUPLEX_FULL) {
3026 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3027 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
3028 } else {
3029 anar |= ADVERTISE_10HALF;
3030 anar |= ADVERTISE_100HALF;
3031 }
43779f8d 3032 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
3033 if (duplex == DUPLEX_FULL) {
3034 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3035 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
3036 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
3037 } else {
3038 anar |= ADVERTISE_10HALF;
3039 anar |= ADVERTISE_100HALF;
3040 gbcr |= ADVERTISE_1000HALF;
3041 }
ac718b69 3042 } else {
3043 ret = -EINVAL;
3044 goto out;
3045 }
3046
3047 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
3048 }
3049
fae56178 3050 if (test_and_clear_bit(PHY_RESET, &tp->flags))
aa66a5f1 3051 bmcr |= BMCR_RESET;
3052
43779f8d 3053 if (tp->mii.supports_gmii)
3054 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
3055
ac718b69 3056 r8152_mdio_write(tp, MII_ADVERTISE, anar);
3057 r8152_mdio_write(tp, MII_BMCR, bmcr);
3058
fae56178 3059 if (bmcr & BMCR_RESET) {
aa66a5f1 3060 int i;
3061
aa66a5f1 3062 for (i = 0; i < 50; i++) {
3063 msleep(20);
3064 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
3065 break;
3066 }
3067 }
3068
ac718b69 3069out:
ac718b69 3070 return ret;
3071}
3072
d70b1137 3073static void rtl8152_up(struct r8152 *tp)
3074{
3075 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3076 return;
3077
cda9fb01 3078 r8152_aldps_en(tp, false);
d70b1137 3079 r8152b_exit_oob(tp);
cda9fb01 3080 r8152_aldps_en(tp, true);
d70b1137 3081}
3082
ac718b69 3083static void rtl8152_down(struct r8152 *tp)
3084{
6871438c 3085 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3086 rtl_drop_queued_tx(tp);
3087 return;
3088 }
3089
00a5e360 3090 r8152_power_cut_en(tp, false);
cda9fb01 3091 r8152_aldps_en(tp, false);
ac718b69 3092 r8152b_enter_oob(tp);
cda9fb01 3093 r8152_aldps_en(tp, true);
ac718b69 3094}
3095
d70b1137 3096static void rtl8153_up(struct r8152 *tp)
3097{
3098 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3099 return;
3100
b214396f 3101 r8153_u1u2en(tp, false);
cda9fb01 3102 r8153_aldps_en(tp, false);
d70b1137 3103 r8153_first_init(tp);
cda9fb01 3104 r8153_aldps_en(tp, true);
b214396f 3105 r8153_u2p3en(tp, true);
3106 r8153_u1u2en(tp, true);
3107 usb_enable_lpm(tp->udev);
d70b1137 3108}
3109
43779f8d 3110static void rtl8153_down(struct r8152 *tp)
3111{
6871438c 3112 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3113 rtl_drop_queued_tx(tp);
3114 return;
3115 }
3116
b9702723 3117 r8153_u1u2en(tp, false);
b214396f 3118 r8153_u2p3en(tp, false);
b9702723 3119 r8153_power_cut_en(tp, false);
cda9fb01 3120 r8153_aldps_en(tp, false);
43779f8d 3121 r8153_enter_oob(tp);
cda9fb01 3122 r8153_aldps_en(tp, true);
43779f8d 3123}
3124
2dd49e0f 3125static bool rtl8152_in_nway(struct r8152 *tp)
3126{
3127 u16 nway_state;
3128
3129 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
3130 tp->ocp_base = 0x2000;
3131 ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */
3132 nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
3133
3134 /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
3135 if (nway_state & 0xc000)
3136 return false;
3137 else
3138 return true;
3139}
3140
3141static bool rtl8153_in_nway(struct r8152 *tp)
3142{
3143 u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
3144
3145 if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
3146 return false;
3147 else
3148 return true;
3149}
3150
ac718b69 3151static void set_carrier(struct r8152 *tp)
3152{
3153 struct net_device *netdev = tp->netdev;
ce594e98 3154 struct napi_struct *napi = &tp->napi;
ac718b69 3155 u8 speed;
3156
3157 speed = rtl8152_get_speed(tp);
3158
3159 if (speed & LINK_STATUS) {
51d979fa 3160 if (!netif_carrier_ok(netdev)) {
c81229c9 3161 tp->rtl_ops.enable(tp);
ac718b69 3162 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
de9bf29d 3163 netif_stop_queue(netdev);
ce594e98 3164 napi_disable(napi);
ac718b69 3165 netif_carrier_on(netdev);
aa2e0926 3166 rtl_start_rx(tp);
41cec84c 3167 napi_enable(&tp->napi);
de9bf29d 3168 netif_wake_queue(netdev);
3169 netif_info(tp, link, netdev, "carrier on\n");
ac718b69 3170 }
3171 } else {
51d979fa 3172 if (netif_carrier_ok(netdev)) {
ac718b69 3173 netif_carrier_off(netdev);
ce594e98 3174 napi_disable(napi);
c81229c9 3175 tp->rtl_ops.disable(tp);
ce594e98 3176 napi_enable(napi);
de9bf29d 3177 netif_info(tp, link, netdev, "carrier off\n");
ac718b69 3178 }
3179 }
ac718b69 3180}
3181
3182static void rtl_work_func_t(struct work_struct *work)
3183{
3184 struct r8152 *tp = container_of(work, struct r8152, schedule.work);
3185
a1f83fee 3186 /* If the device is unplugged or !netif_running(), the workqueue
3187 * doesn't need to wake the device, and could return directly.
3188 */
3189 if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
3190 return;
3191
9a4be1bd 3192 if (usb_autopm_get_interface(tp->intf) < 0)
3193 return;
3194
ac718b69 3195 if (!test_bit(WORK_ENABLE, &tp->flags))
3196 goto out1;
3197
b5403273 3198 if (!mutex_trylock(&tp->control)) {
3199 schedule_delayed_work(&tp->schedule, 0);
3200 goto out1;
3201 }
3202
216a8349 3203 if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
40a82917 3204 set_carrier(tp);
ac718b69 3205
216a8349 3206 if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
ac718b69 3207 _rtl8152_set_rx_mode(tp->netdev);
3208
d823ab68 3209 /* don't schedule napi before linking */
216a8349 3210 if (test_and_clear_bit(SCHEDULE_NAPI, &tp->flags) &&
3211 netif_carrier_ok(tp->netdev))
d823ab68 3212 napi_schedule(&tp->napi);
aa66a5f1 3213
b5403273 3214 mutex_unlock(&tp->control);
3215
ac718b69 3216out1:
9a4be1bd 3217 usb_autopm_put_interface(tp->intf);
ac718b69 3218}
3219
a028a9e0 3220static void rtl_hw_phy_work_func_t(struct work_struct *work)
3221{
3222 struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
3223
3224 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3225 return;
3226
3227 if (usb_autopm_get_interface(tp->intf) < 0)
3228 return;
3229
3230 mutex_lock(&tp->control);
3231
3232 tp->rtl_ops.hw_phy_cfg(tp);
3233
aa7e26b6 3234 rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex);
9d21c0d8 3235
a028a9e0 3236 mutex_unlock(&tp->control);
3237
3238 usb_autopm_put_interface(tp->intf);
3239}
3240
5ee3c60c 3241#ifdef CONFIG_PM_SLEEP
3242static int rtl_notifier(struct notifier_block *nb, unsigned long action,
3243 void *data)
3244{
3245 struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
3246
3247 switch (action) {
3248 case PM_HIBERNATION_PREPARE:
3249 case PM_SUSPEND_PREPARE:
3250 usb_autopm_get_interface(tp->intf);
3251 break;
3252
3253 case PM_POST_HIBERNATION:
3254 case PM_POST_SUSPEND:
3255 usb_autopm_put_interface(tp->intf);
3256 break;
3257
3258 case PM_POST_RESTORE:
3259 case PM_RESTORE_PREPARE:
3260 default:
3261 break;
3262 }
3263
3264 return NOTIFY_DONE;
3265}
3266#endif
3267
ac718b69 3268static int rtl8152_open(struct net_device *netdev)
3269{
3270 struct r8152 *tp = netdev_priv(netdev);
3271 int res = 0;
3272
7e9da481 3273 res = alloc_all_mem(tp);
3274 if (res)
3275 goto out;
3276
9a4be1bd 3277 res = usb_autopm_get_interface(tp->intf);
ca0a7531
GR
3278 if (res < 0)
3279 goto out_free;
9a4be1bd 3280
b5403273 3281 mutex_lock(&tp->control);
3282
7e9da481 3283 tp->rtl_ops.up(tp);
3284
3d55f44f 3285 netif_carrier_off(netdev);
3286 netif_start_queue(netdev);
3287 set_bit(WORK_ENABLE, &tp->flags);
db8515ef 3288
40a82917 3289 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
3290 if (res) {
3291 if (res == -ENODEV)
3292 netif_device_detach(tp->netdev);
4a8deae2
HW
3293 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
3294 res);
ca0a7531 3295 goto out_unlock;
ac718b69 3296 }
ca0a7531 3297 napi_enable(&tp->napi);
ac718b69 3298
b5403273 3299 mutex_unlock(&tp->control);
3300
9a4be1bd 3301 usb_autopm_put_interface(tp->intf);
5ee3c60c 3302#ifdef CONFIG_PM_SLEEP
3303 tp->pm_notifier.notifier_call = rtl_notifier;
3304 register_pm_notifier(&tp->pm_notifier);
3305#endif
ca0a7531 3306 return 0;
ac718b69 3307
ca0a7531
GR
3308out_unlock:
3309 mutex_unlock(&tp->control);
3310 usb_autopm_put_interface(tp->intf);
3311out_free:
3312 free_all_mem(tp);
7e9da481 3313out:
ac718b69 3314 return res;
3315}
3316
3317static int rtl8152_close(struct net_device *netdev)
3318{
3319 struct r8152 *tp = netdev_priv(netdev);
3320 int res = 0;
3321
5ee3c60c 3322#ifdef CONFIG_PM_SLEEP
3323 unregister_pm_notifier(&tp->pm_notifier);
3324#endif
d823ab68 3325 napi_disable(&tp->napi);
ac718b69 3326 clear_bit(WORK_ENABLE, &tp->flags);
3d55f44f 3327 usb_kill_urb(tp->intr_urb);
ac718b69 3328 cancel_delayed_work_sync(&tp->schedule);
3329 netif_stop_queue(netdev);
9a4be1bd 3330
3331 res = usb_autopm_get_interface(tp->intf);
53543db5 3332 if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
9a4be1bd 3333 rtl_drop_queued_tx(tp);
d823ab68 3334 rtl_stop_rx(tp);
9a4be1bd 3335 } else {
b5403273 3336 mutex_lock(&tp->control);
3337
9a4be1bd 3338 tp->rtl_ops.down(tp);
b5403273 3339
3340 mutex_unlock(&tp->control);
3341
9a4be1bd 3342 usb_autopm_put_interface(tp->intf);
3343 }
ac718b69 3344
7e9da481 3345 free_all_mem(tp);
3346
ac718b69 3347 return res;
3348}
3349
4f1d4d54 3350static void rtl_tally_reset(struct r8152 *tp)
3351{
3352 u32 ocp_data;
3353
3354 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
3355 ocp_data |= TALLY_RESET;
3356 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
3357}
3358
ac718b69 3359static void r8152b_init(struct r8152 *tp)
3360{
ebc2ec48 3361 u32 ocp_data;
2dd436da 3362 u16 data;
ac718b69 3363
6871438c 3364 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3365 return;
3366
2dd436da 3367 data = r8152_mdio_read(tp, MII_BMCR);
3368 if (data & BMCR_PDOWN) {
3369 data &= ~BMCR_PDOWN;
3370 r8152_mdio_write(tp, MII_BMCR, data);
3371 }
3372
cda9fb01 3373 r8152_aldps_en(tp, false);
d70b1137 3374
ac718b69 3375 if (tp->version == RTL_VER_01) {
3376 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3377 ocp_data &= ~LED_MODE_MASK;
3378 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3379 }
3380
00a5e360 3381 r8152_power_cut_en(tp, false);
ac718b69 3382
ac718b69 3383 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3384 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
3385 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3386 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
3387 ocp_data &= ~MCU_CLK_RATIO_MASK;
3388 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
3389 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
3390 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
3391 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
3392 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
3393
4f1d4d54 3394 rtl_tally_reset(tp);
ac718b69 3395
ebc2ec48 3396 /* enable rx aggregation */
ac718b69 3397 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
e90fba8d 3398 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
ac718b69 3399 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
3400}
3401
43779f8d 3402static void r8153_init(struct r8152 *tp)
3403{
3404 u32 ocp_data;
2dd436da 3405 u16 data;
43779f8d 3406 int i;
3407
6871438c 3408 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3409 return;
3410
b9702723 3411 r8153_u1u2en(tp, false);
43779f8d 3412
3413 for (i = 0; i < 500; i++) {
3414 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3415 AUTOLOAD_DONE)
3416 break;
3417 msleep(20);
3418 }
3419
3420 for (i = 0; i < 500; i++) {
3421 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
3422 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
3423 break;
3424 msleep(20);
3425 }
3426
2dd436da 3427 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
3428 tp->version == RTL_VER_05)
3429 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
3430
3431 data = r8152_mdio_read(tp, MII_BMCR);
3432 if (data & BMCR_PDOWN) {
3433 data &= ~BMCR_PDOWN;
3434 r8152_mdio_write(tp, MII_BMCR, data);
3435 }
3436
3437 for (i = 0; i < 500; i++) {
3438 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
3439 if (ocp_data == PHY_STAT_LAN_ON)
3440 break;
3441 msleep(20);
3442 }
3443
b214396f 3444 usb_disable_lpm(tp->udev);
b9702723 3445 r8153_u2p3en(tp, false);
43779f8d 3446
65bab84c 3447 if (tp->version == RTL_VER_04) {
3448 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
3449 ocp_data &= ~pwd_dn_scale_mask;
3450 ocp_data |= pwd_dn_scale(96);
3451 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
3452
3453 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
3454 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
3455 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
3456 } else if (tp->version == RTL_VER_05) {
3457 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
3458 ocp_data &= ~ECM_ALDPS;
3459 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
3460
fb02eb4a 3461 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
3462 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
3463 ocp_data &= ~DYNAMIC_BURST;
3464 else
3465 ocp_data |= DYNAMIC_BURST;
3466 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
3467 } else if (tp->version == RTL_VER_06) {
65bab84c 3468 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
3469 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
3470 ocp_data &= ~DYNAMIC_BURST;
3471 else
3472 ocp_data |= DYNAMIC_BURST;
3473 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
3474 }
3475
3476 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
3477 ocp_data |= EP4_FULL_FC;
3478 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
3479
43779f8d 3480 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
3481 ocp_data &= ~TIMER11_EN;
3482 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
3483
43779f8d 3484 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3485 ocp_data &= ~LED_MODE_MASK;
3486 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3487
65bab84c 3488 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
2b84af94 3489 if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
43779f8d 3490 ocp_data |= LPM_TIMER_500MS;
34203e25 3491 else
3492 ocp_data |= LPM_TIMER_500US;
43779f8d 3493 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
3494
3495 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
3496 ocp_data &= ~SEN_VAL_MASK;
3497 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
3498 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
3499
65bab84c 3500 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
3501
b9702723 3502 r8153_power_cut_en(tp, false);
3503 r8153_u1u2en(tp, true);
43779f8d 3504
4e384ac1 3505 /* MAC clock speed down */
3506 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0);
3507 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0);
3508 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0);
3509 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0);
43779f8d 3510
4f1d4d54 3511 rtl_tally_reset(tp);
b214396f 3512 r8153_u2p3en(tp, true);
43779f8d 3513}
3514
e501139a 3515static int rtl8152_pre_reset(struct usb_interface *intf)
3516{
3517 struct r8152 *tp = usb_get_intfdata(intf);
3518 struct net_device *netdev;
3519
3520 if (!tp)
3521 return 0;
3522
3523 netdev = tp->netdev;
3524 if (!netif_running(netdev))
3525 return 0;
3526
de9bf29d 3527 netif_stop_queue(netdev);
e501139a 3528 napi_disable(&tp->napi);
3529 clear_bit(WORK_ENABLE, &tp->flags);
3530 usb_kill_urb(tp->intr_urb);
3531 cancel_delayed_work_sync(&tp->schedule);
3532 if (netif_carrier_ok(netdev)) {
e501139a 3533 mutex_lock(&tp->control);
3534 tp->rtl_ops.disable(tp);
3535 mutex_unlock(&tp->control);
3536 }
3537
3538 return 0;
3539}
3540
3541static int rtl8152_post_reset(struct usb_interface *intf)
3542{
3543 struct r8152 *tp = usb_get_intfdata(intf);
3544 struct net_device *netdev;
3545
3546 if (!tp)
3547 return 0;
3548
3549 netdev = tp->netdev;
3550 if (!netif_running(netdev))
3551 return 0;
3552
3553 set_bit(WORK_ENABLE, &tp->flags);
3554 if (netif_carrier_ok(netdev)) {
3555 mutex_lock(&tp->control);
3556 tp->rtl_ops.enable(tp);
2c561b2b 3557 rtl_start_rx(tp);
e501139a 3558 rtl8152_set_rx_mode(netdev);
3559 mutex_unlock(&tp->control);
e501139a 3560 }
3561
3562 napi_enable(&tp->napi);
de9bf29d 3563 netif_wake_queue(netdev);
2c561b2b 3564 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
e501139a 3565
7489bdad 3566 if (!list_empty(&tp->rx_done))
3567 napi_schedule(&tp->napi);
e501139a 3568
3569 return 0;
43779f8d 3570}
3571
2dd49e0f 3572static bool delay_autosuspend(struct r8152 *tp)
3573{
3574 bool sw_linking = !!netif_carrier_ok(tp->netdev);
3575 bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
3576
3577 /* This means a linking change occurs and the driver doesn't detect it,
3578 * yet. If the driver has disabled tx/rx and hw is linking on, the
3579 * device wouldn't wake up by receiving any packet.
3580 */
3581 if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
3582 return true;
3583
3584 /* If the linking down is occurred by nway, the device may miss the
3585 * linking change event. And it wouldn't wake when linking on.
3586 */
3587 if (!sw_linking && tp->rtl_ops.in_nway(tp))
3588 return true;
6a0b76c0 3589 else if (!skb_queue_empty(&tp->tx_queue))
3590 return true;
2dd49e0f 3591 else
3592 return false;
3593}
3594
a9c54ad2 3595static int rtl8152_runtime_suspend(struct r8152 *tp)
ac718b69 3596{
6cc69f2a 3597 struct net_device *netdev = tp->netdev;
3598 int ret = 0;
ac718b69 3599
26afec39 3600 set_bit(SELECTIVE_SUSPEND, &tp->flags);
3601 smp_mb__after_atomic();
3602
8fb28061 3603 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
75dc692e 3604 u32 rcr = 0;
3605
8fb28061 3606 if (delay_autosuspend(tp)) {
26afec39 3607 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
3608 smp_mb__after_atomic();
6cc69f2a 3609 ret = -EBUSY;
3610 goto out1;
3611 }
3612
75dc692e 3613 if (netif_carrier_ok(netdev)) {
3614 u32 ocp_data;
3615
3616 rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3617 ocp_data = rcr & ~RCR_ACPT_ALL;
3618 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3619 rxdy_gated_en(tp, true);
3620 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA,
3621 PLA_OOB_CTRL);
3622 if (!(ocp_data & RXFIFO_EMPTY)) {
3623 rxdy_gated_en(tp, false);
3624 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
26afec39 3625 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
3626 smp_mb__after_atomic();
75dc692e 3627 ret = -EBUSY;
3628 goto out1;
3629 }
3630 }
3631
8fb28061 3632 clear_bit(WORK_ENABLE, &tp->flags);
3633 usb_kill_urb(tp->intr_urb);
75dc692e 3634
8fb28061 3635 tp->rtl_ops.autosuspend_en(tp, true);
75dc692e 3636
3637 if (netif_carrier_ok(netdev)) {
ce594e98 3638 struct napi_struct *napi = &tp->napi;
3639
3640 napi_disable(napi);
75dc692e 3641 rtl_stop_rx(tp);
3642 rxdy_gated_en(tp, false);
3643 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
ce594e98 3644 napi_enable(napi);
75dc692e 3645 }
6cc69f2a 3646 }
ac718b69 3647
8fb28061 3648out1:
3649 return ret;
3650}
3651
3652static int rtl8152_system_suspend(struct r8152 *tp)
3653{
3654 struct net_device *netdev = tp->netdev;
3655 int ret = 0;
3656
3657 netif_device_detach(netdev);
3658
e3bd1a81 3659 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
ce594e98 3660 struct napi_struct *napi = &tp->napi;
3661
ac718b69 3662 clear_bit(WORK_ENABLE, &tp->flags);
40a82917 3663 usb_kill_urb(tp->intr_urb);
ce594e98 3664 napi_disable(napi);
8fb28061 3665 cancel_delayed_work_sync(&tp->schedule);
3666 tp->rtl_ops.down(tp);
ce594e98 3667 napi_enable(napi);
ac718b69 3668 }
8fb28061 3669
3670 return ret;
3671}
3672
3673static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
3674{
3675 struct r8152 *tp = usb_get_intfdata(intf);
3676 int ret;
3677
3678 mutex_lock(&tp->control);
3679
3680 if (PMSG_IS_AUTO(message))
a9c54ad2 3681 ret = rtl8152_runtime_suspend(tp);
8fb28061 3682 else
3683 ret = rtl8152_system_suspend(tp);
3684
b5403273 3685 mutex_unlock(&tp->control);
3686
6cc69f2a 3687 return ret;
ac718b69 3688}
3689
3690static int rtl8152_resume(struct usb_interface *intf)
3691{
3692 struct r8152 *tp = usb_get_intfdata(intf);
ce594e98 3693 struct net_device *netdev = tp->netdev;
ac718b69 3694
b5403273 3695 mutex_lock(&tp->control);
3696
9a4be1bd 3697 if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3698 tp->rtl_ops.init(tp);
a028a9e0 3699 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
ce594e98 3700 netif_device_attach(netdev);
9a4be1bd 3701 }
3702
ce594e98 3703 if (netif_running(netdev) && netdev->flags & IFF_UP) {
9a4be1bd 3704 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
ce594e98 3705 struct napi_struct *napi = &tp->napi;
3706
2609af19 3707 tp->rtl_ops.autosuspend_en(tp, false);
ce594e98 3708 napi_disable(napi);
445f7f4d 3709 set_bit(WORK_ENABLE, &tp->flags);
ce594e98 3710 if (netif_carrier_ok(netdev))
445f7f4d 3711 rtl_start_rx(tp);
ce594e98 3712 napi_enable(napi);
26afec39 3713 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
3714 smp_mb__after_atomic();
7489bdad 3715 if (!list_empty(&tp->rx_done))
3716 napi_schedule(&tp->napi);
9a4be1bd 3717 } else {
3718 tp->rtl_ops.up(tp);
ce594e98 3719 netif_carrier_off(netdev);
445f7f4d 3720 set_bit(WORK_ENABLE, &tp->flags);
9a4be1bd 3721 }
40a82917 3722 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
923e1ee3 3723 } else if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
ce594e98 3724 if (netdev->flags & IFF_UP)
2609af19 3725 tp->rtl_ops.autosuspend_en(tp, false);
923e1ee3 3726 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
ac718b69 3727 }
3728
b5403273 3729 mutex_unlock(&tp->control);
3730
ac718b69 3731 return 0;
3732}
3733
7ec2541a 3734static int rtl8152_reset_resume(struct usb_interface *intf)
3735{
3736 struct r8152 *tp = usb_get_intfdata(intf);
3737
3738 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
3739 return rtl8152_resume(intf);
3740}
3741
21ff2e89 3742static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3743{
3744 struct r8152 *tp = netdev_priv(dev);
3745
9a4be1bd 3746 if (usb_autopm_get_interface(tp->intf) < 0)
3747 return;
3748
7daed8dc 3749 if (!rtl_can_wakeup(tp)) {
3750 wol->supported = 0;
3751 wol->wolopts = 0;
3752 } else {
3753 mutex_lock(&tp->control);
3754 wol->supported = WAKE_ANY;
3755 wol->wolopts = __rtl_get_wol(tp);
3756 mutex_unlock(&tp->control);
3757 }
b5403273 3758
9a4be1bd 3759 usb_autopm_put_interface(tp->intf);
21ff2e89 3760}
3761
3762static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3763{
3764 struct r8152 *tp = netdev_priv(dev);
9a4be1bd 3765 int ret;
3766
7daed8dc 3767 if (!rtl_can_wakeup(tp))
3768 return -EOPNOTSUPP;
3769
9a4be1bd 3770 ret = usb_autopm_get_interface(tp->intf);
3771 if (ret < 0)
3772 goto out_set_wol;
21ff2e89 3773
b5403273 3774 mutex_lock(&tp->control);
3775
21ff2e89 3776 __rtl_set_wol(tp, wol->wolopts);
3777 tp->saved_wolopts = wol->wolopts & WAKE_ANY;
3778
b5403273 3779 mutex_unlock(&tp->control);
3780
9a4be1bd 3781 usb_autopm_put_interface(tp->intf);
3782
3783out_set_wol:
3784 return ret;
21ff2e89 3785}
3786
a5ec27c1 3787static u32 rtl8152_get_msglevel(struct net_device *dev)
3788{
3789 struct r8152 *tp = netdev_priv(dev);
3790
3791 return tp->msg_enable;
3792}
3793
3794static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
3795{
3796 struct r8152 *tp = netdev_priv(dev);
3797
3798 tp->msg_enable = value;
3799}
3800
ac718b69 3801static void rtl8152_get_drvinfo(struct net_device *netdev,
3802 struct ethtool_drvinfo *info)
3803{
3804 struct r8152 *tp = netdev_priv(netdev);
3805
b0b46c77 3806 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
3807 strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
ac718b69 3808 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
3809}
3810
3811static
06144dcf
PR
3812int rtl8152_get_link_ksettings(struct net_device *netdev,
3813 struct ethtool_link_ksettings *cmd)
ac718b69 3814{
3815 struct r8152 *tp = netdev_priv(netdev);
8d4a4d72 3816 int ret;
ac718b69 3817
3818 if (!tp->mii.mdio_read)
3819 return -EOPNOTSUPP;
3820
8d4a4d72 3821 ret = usb_autopm_get_interface(tp->intf);
3822 if (ret < 0)
3823 goto out;
3824
b5403273 3825 mutex_lock(&tp->control);
3826
06144dcf 3827 ret = mii_ethtool_get_link_ksettings(&tp->mii, cmd);
8d4a4d72 3828
b5403273 3829 mutex_unlock(&tp->control);
3830
8d4a4d72 3831 usb_autopm_put_interface(tp->intf);
3832
3833out:
3834 return ret;
ac718b69 3835}
3836
06144dcf
PR
3837static int rtl8152_set_link_ksettings(struct net_device *dev,
3838 const struct ethtool_link_ksettings *cmd)
ac718b69 3839{
3840 struct r8152 *tp = netdev_priv(dev);
9a4be1bd 3841 int ret;
3842
3843 ret = usb_autopm_get_interface(tp->intf);
3844 if (ret < 0)
3845 goto out;
ac718b69 3846
b5403273 3847 mutex_lock(&tp->control);
3848
06144dcf
PR
3849 ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed,
3850 cmd->base.duplex);
aa7e26b6 3851 if (!ret) {
06144dcf
PR
3852 tp->autoneg = cmd->base.autoneg;
3853 tp->speed = cmd->base.speed;
3854 tp->duplex = cmd->base.duplex;
aa7e26b6 3855 }
9a4be1bd 3856
b5403273 3857 mutex_unlock(&tp->control);
3858
9a4be1bd 3859 usb_autopm_put_interface(tp->intf);
3860
3861out:
3862 return ret;
ac718b69 3863}
3864
4f1d4d54 3865static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
3866 "tx_packets",
3867 "rx_packets",
3868 "tx_errors",
3869 "rx_errors",
3870 "rx_missed",
3871 "align_errors",
3872 "tx_single_collisions",
3873 "tx_multi_collisions",
3874 "rx_unicast",
3875 "rx_broadcast",
3876 "rx_multicast",
3877 "tx_aborted",
3878 "tx_underrun",
3879};
3880
3881static int rtl8152_get_sset_count(struct net_device *dev, int sset)
3882{
3883 switch (sset) {
3884 case ETH_SS_STATS:
3885 return ARRAY_SIZE(rtl8152_gstrings);
3886 default:
3887 return -EOPNOTSUPP;
3888 }
3889}
3890
3891static void rtl8152_get_ethtool_stats(struct net_device *dev,
3892 struct ethtool_stats *stats, u64 *data)
3893{
3894 struct r8152 *tp = netdev_priv(dev);
3895 struct tally_counter tally;
3896
0b030244 3897 if (usb_autopm_get_interface(tp->intf) < 0)
3898 return;
3899
4f1d4d54 3900 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
3901
0b030244 3902 usb_autopm_put_interface(tp->intf);
3903
4f1d4d54 3904 data[0] = le64_to_cpu(tally.tx_packets);
3905 data[1] = le64_to_cpu(tally.rx_packets);
3906 data[2] = le64_to_cpu(tally.tx_errors);
3907 data[3] = le32_to_cpu(tally.rx_errors);
3908 data[4] = le16_to_cpu(tally.rx_missed);
3909 data[5] = le16_to_cpu(tally.align_errors);
3910 data[6] = le32_to_cpu(tally.tx_one_collision);
3911 data[7] = le32_to_cpu(tally.tx_multi_collision);
3912 data[8] = le64_to_cpu(tally.rx_unicast);
3913 data[9] = le64_to_cpu(tally.rx_broadcast);
3914 data[10] = le32_to_cpu(tally.rx_multicast);
3915 data[11] = le16_to_cpu(tally.tx_aborted);
f37119c5 3916 data[12] = le16_to_cpu(tally.tx_underrun);
4f1d4d54 3917}
3918
3919static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
3920{
3921 switch (stringset) {
3922 case ETH_SS_STATS:
3923 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
3924 break;
3925 }
3926}
3927
df35d283 3928static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
3929{
3930 u32 ocp_data, lp, adv, supported = 0;
3931 u16 val;
3932
3933 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
3934 supported = mmd_eee_cap_to_ethtool_sup_t(val);
3935
3936 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
3937 adv = mmd_eee_adv_to_ethtool_adv_t(val);
3938
3939 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
3940 lp = mmd_eee_adv_to_ethtool_adv_t(val);
3941
3942 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3943 ocp_data &= EEE_RX_EN | EEE_TX_EN;
3944
3945 eee->eee_enabled = !!ocp_data;
3946 eee->eee_active = !!(supported & adv & lp);
3947 eee->supported = supported;
3948 eee->advertised = adv;
3949 eee->lp_advertised = lp;
3950
3951 return 0;
3952}
3953
3954static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
3955{
3956 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
3957
3958 r8152_eee_en(tp, eee->eee_enabled);
3959
3960 if (!eee->eee_enabled)
3961 val = 0;
3962
3963 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
3964
3965 return 0;
3966}
3967
3968static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
3969{
3970 u32 ocp_data, lp, adv, supported = 0;
3971 u16 val;
3972
3973 val = ocp_reg_read(tp, OCP_EEE_ABLE);
3974 supported = mmd_eee_cap_to_ethtool_sup_t(val);
3975
3976 val = ocp_reg_read(tp, OCP_EEE_ADV);
3977 adv = mmd_eee_adv_to_ethtool_adv_t(val);
3978
3979 val = ocp_reg_read(tp, OCP_EEE_LPABLE);
3980 lp = mmd_eee_adv_to_ethtool_adv_t(val);
3981
3982 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3983 ocp_data &= EEE_RX_EN | EEE_TX_EN;
3984
3985 eee->eee_enabled = !!ocp_data;
3986 eee->eee_active = !!(supported & adv & lp);
3987 eee->supported = supported;
3988 eee->advertised = adv;
3989 eee->lp_advertised = lp;
3990
3991 return 0;
3992}
3993
3994static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
3995{
3996 u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
3997
3998 r8153_eee_en(tp, eee->eee_enabled);
3999
4000 if (!eee->eee_enabled)
4001 val = 0;
4002
4003 ocp_reg_write(tp, OCP_EEE_ADV, val);
4004
4005 return 0;
4006}
4007
4008static int
4009rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
4010{
4011 struct r8152 *tp = netdev_priv(net);
4012 int ret;
4013
4014 ret = usb_autopm_get_interface(tp->intf);
4015 if (ret < 0)
4016 goto out;
4017
b5403273 4018 mutex_lock(&tp->control);
4019
df35d283 4020 ret = tp->rtl_ops.eee_get(tp, edata);
4021
b5403273 4022 mutex_unlock(&tp->control);
4023
df35d283 4024 usb_autopm_put_interface(tp->intf);
4025
4026out:
4027 return ret;
4028}
4029
4030static int
4031rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
4032{
4033 struct r8152 *tp = netdev_priv(net);
4034 int ret;
4035
4036 ret = usb_autopm_get_interface(tp->intf);
4037 if (ret < 0)
4038 goto out;
4039
b5403273 4040 mutex_lock(&tp->control);
4041
df35d283 4042 ret = tp->rtl_ops.eee_set(tp, edata);
9d31a7b9 4043 if (!ret)
4044 ret = mii_nway_restart(&tp->mii);
df35d283 4045
b5403273 4046 mutex_unlock(&tp->control);
4047
df35d283 4048 usb_autopm_put_interface(tp->intf);
4049
4050out:
4051 return ret;
4052}
4053
8884f507 4054static int rtl8152_nway_reset(struct net_device *dev)
4055{
4056 struct r8152 *tp = netdev_priv(dev);
4057 int ret;
4058
4059 ret = usb_autopm_get_interface(tp->intf);
4060 if (ret < 0)
4061 goto out;
4062
4063 mutex_lock(&tp->control);
4064
4065 ret = mii_nway_restart(&tp->mii);
4066
4067 mutex_unlock(&tp->control);
4068
4069 usb_autopm_put_interface(tp->intf);
4070
4071out:
4072 return ret;
4073}
4074
efb3dd88 4075static int rtl8152_get_coalesce(struct net_device *netdev,
4076 struct ethtool_coalesce *coalesce)
4077{
4078 struct r8152 *tp = netdev_priv(netdev);
4079
4080 switch (tp->version) {
4081 case RTL_VER_01:
4082 case RTL_VER_02:
4083 return -EOPNOTSUPP;
4084 default:
4085 break;
4086 }
4087
4088 coalesce->rx_coalesce_usecs = tp->coalesce;
4089
4090 return 0;
4091}
4092
4093static int rtl8152_set_coalesce(struct net_device *netdev,
4094 struct ethtool_coalesce *coalesce)
4095{
4096 struct r8152 *tp = netdev_priv(netdev);
4097 int ret;
4098
4099 switch (tp->version) {
4100 case RTL_VER_01:
4101 case RTL_VER_02:
4102 return -EOPNOTSUPP;
4103 default:
4104 break;
4105 }
4106
4107 if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
4108 return -EINVAL;
4109
4110 ret = usb_autopm_get_interface(tp->intf);
4111 if (ret < 0)
4112 return ret;
4113
4114 mutex_lock(&tp->control);
4115
4116 if (tp->coalesce != coalesce->rx_coalesce_usecs) {
4117 tp->coalesce = coalesce->rx_coalesce_usecs;
4118
4119 if (netif_running(tp->netdev) && netif_carrier_ok(netdev))
4120 r8153_set_rx_early_timeout(tp);
4121 }
4122
4123 mutex_unlock(&tp->control);
4124
4125 usb_autopm_put_interface(tp->intf);
4126
4127 return ret;
4128}
4129
407a471d 4130static const struct ethtool_ops ops = {
ac718b69 4131 .get_drvinfo = rtl8152_get_drvinfo,
ac718b69 4132 .get_link = ethtool_op_get_link,
8884f507 4133 .nway_reset = rtl8152_nway_reset,
a5ec27c1 4134 .get_msglevel = rtl8152_get_msglevel,
4135 .set_msglevel = rtl8152_set_msglevel,
21ff2e89 4136 .get_wol = rtl8152_get_wol,
4137 .set_wol = rtl8152_set_wol,
4f1d4d54 4138 .get_strings = rtl8152_get_strings,
4139 .get_sset_count = rtl8152_get_sset_count,
4140 .get_ethtool_stats = rtl8152_get_ethtool_stats,
efb3dd88 4141 .get_coalesce = rtl8152_get_coalesce,
4142 .set_coalesce = rtl8152_set_coalesce,
df35d283 4143 .get_eee = rtl_ethtool_get_eee,
4144 .set_eee = rtl_ethtool_set_eee,
06144dcf
PR
4145 .get_link_ksettings = rtl8152_get_link_ksettings,
4146 .set_link_ksettings = rtl8152_set_link_ksettings,
ac718b69 4147};
4148
4149static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
4150{
4151 struct r8152 *tp = netdev_priv(netdev);
4152 struct mii_ioctl_data *data = if_mii(rq);
9a4be1bd 4153 int res;
4154
6871438c 4155 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4156 return -ENODEV;
4157
9a4be1bd 4158 res = usb_autopm_get_interface(tp->intf);
4159 if (res < 0)
4160 goto out;
ac718b69 4161
4162 switch (cmd) {
4163 case SIOCGMIIPHY:
4164 data->phy_id = R8152_PHY_ID; /* Internal PHY */
4165 break;
4166
4167 case SIOCGMIIREG:
b5403273 4168 mutex_lock(&tp->control);
ac718b69 4169 data->val_out = r8152_mdio_read(tp, data->reg_num);
b5403273 4170 mutex_unlock(&tp->control);
ac718b69 4171 break;
4172
4173 case SIOCSMIIREG:
4174 if (!capable(CAP_NET_ADMIN)) {
4175 res = -EPERM;
4176 break;
4177 }
b5403273 4178 mutex_lock(&tp->control);
ac718b69 4179 r8152_mdio_write(tp, data->reg_num, data->val_in);
b5403273 4180 mutex_unlock(&tp->control);
ac718b69 4181 break;
4182
4183 default:
4184 res = -EOPNOTSUPP;
4185 }
4186
9a4be1bd 4187 usb_autopm_put_interface(tp->intf);
4188
4189out:
ac718b69 4190 return res;
4191}
4192
69b4b7a4 4193static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
4194{
4195 struct r8152 *tp = netdev_priv(dev);
396e2e23 4196 int ret;
69b4b7a4 4197
4198 switch (tp->version) {
4199 case RTL_VER_01:
4200 case RTL_VER_02:
a52ad514
JW
4201 dev->mtu = new_mtu;
4202 return 0;
69b4b7a4 4203 default:
4204 break;
4205 }
4206
396e2e23 4207 ret = usb_autopm_get_interface(tp->intf);
4208 if (ret < 0)
4209 return ret;
4210
4211 mutex_lock(&tp->control);
4212
69b4b7a4 4213 dev->mtu = new_mtu;
4214
396e2e23 4215 if (netif_running(dev) && netif_carrier_ok(dev))
4216 r8153_set_rx_early_size(tp);
4217
4218 mutex_unlock(&tp->control);
4219
4220 usb_autopm_put_interface(tp->intf);
4221
4222 return ret;
69b4b7a4 4223}
4224
ac718b69 4225static const struct net_device_ops rtl8152_netdev_ops = {
4226 .ndo_open = rtl8152_open,
4227 .ndo_stop = rtl8152_close,
4228 .ndo_do_ioctl = rtl8152_ioctl,
4229 .ndo_start_xmit = rtl8152_start_xmit,
4230 .ndo_tx_timeout = rtl8152_tx_timeout,
c5554298 4231 .ndo_set_features = rtl8152_set_features,
ac718b69 4232 .ndo_set_rx_mode = rtl8152_set_rx_mode,
4233 .ndo_set_mac_address = rtl8152_set_mac_address,
69b4b7a4 4234 .ndo_change_mtu = rtl8152_change_mtu,
ac718b69 4235 .ndo_validate_addr = eth_validate_addr,
a5e31255 4236 .ndo_features_check = rtl8152_features_check,
ac718b69 4237};
4238
4239static void r8152b_get_version(struct r8152 *tp)
4240{
4241 u32 ocp_data;
4242 u16 version;
4243
4244 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
4245 version = (u16)(ocp_data & VERSION_MASK);
4246
4247 switch (version) {
4248 case 0x4c00:
4249 tp->version = RTL_VER_01;
4250 break;
4251 case 0x4c10:
4252 tp->version = RTL_VER_02;
4253 break;
43779f8d 4254 case 0x5c00:
4255 tp->version = RTL_VER_03;
4256 tp->mii.supports_gmii = 1;
4257 break;
4258 case 0x5c10:
4259 tp->version = RTL_VER_04;
4260 tp->mii.supports_gmii = 1;
4261 break;
4262 case 0x5c20:
4263 tp->version = RTL_VER_05;
4264 tp->mii.supports_gmii = 1;
4265 break;
fb02eb4a 4266 case 0x5c30:
4267 tp->version = RTL_VER_06;
4268 tp->mii.supports_gmii = 1;
4269 break;
ac718b69 4270 default:
4271 netif_info(tp, probe, tp->netdev,
4272 "Unknown version 0x%04x\n", version);
4273 break;
4274 }
4275}
4276
e3fe0b1a 4277static void rtl8152_unload(struct r8152 *tp)
4278{
6871438c 4279 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4280 return;
4281
00a5e360 4282 if (tp->version != RTL_VER_01)
4283 r8152_power_cut_en(tp, true);
e3fe0b1a 4284}
4285
43779f8d 4286static void rtl8153_unload(struct r8152 *tp)
4287{
6871438c 4288 if (test_bit(RTL8152_UNPLUG, &tp->flags))
4289 return;
4290
49be1723 4291 r8153_power_cut_en(tp, false);
43779f8d 4292}
4293
55b65475 4294static int rtl_ops_init(struct r8152 *tp)
c81229c9 4295{
4296 struct rtl_ops *ops = &tp->rtl_ops;
55b65475 4297 int ret = 0;
4298
4299 switch (tp->version) {
4300 case RTL_VER_01:
4301 case RTL_VER_02:
4302 ops->init = r8152b_init;
4303 ops->enable = rtl8152_enable;
4304 ops->disable = rtl8152_disable;
4305 ops->up = rtl8152_up;
4306 ops->down = rtl8152_down;
4307 ops->unload = rtl8152_unload;
4308 ops->eee_get = r8152_get_eee;
4309 ops->eee_set = r8152_set_eee;
2dd49e0f 4310 ops->in_nway = rtl8152_in_nway;
a028a9e0 4311 ops->hw_phy_cfg = r8152b_hw_phy_cfg;
2609af19 4312 ops->autosuspend_en = rtl_runtime_suspend_enable;
43779f8d 4313 break;
4314
55b65475 4315 case RTL_VER_03:
4316 case RTL_VER_04:
4317 case RTL_VER_05:
fb02eb4a 4318 case RTL_VER_06:
55b65475 4319 ops->init = r8153_init;
4320 ops->enable = rtl8153_enable;
4321 ops->disable = rtl8153_disable;
4322 ops->up = rtl8153_up;
4323 ops->down = rtl8153_down;
4324 ops->unload = rtl8153_unload;
4325 ops->eee_get = r8153_get_eee;
4326 ops->eee_set = r8153_set_eee;
2dd49e0f 4327 ops->in_nway = rtl8153_in_nway;
a028a9e0 4328 ops->hw_phy_cfg = r8153_hw_phy_cfg;
2609af19 4329 ops->autosuspend_en = rtl8153_runtime_enable;
c81229c9 4330 break;
4331
4332 default:
55b65475 4333 ret = -ENODEV;
4334 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
c81229c9 4335 break;
4336 }
4337
4338 return ret;
4339}
4340
ac718b69 4341static int rtl8152_probe(struct usb_interface *intf,
4342 const struct usb_device_id *id)
4343{
4344 struct usb_device *udev = interface_to_usbdev(intf);
4345 struct r8152 *tp;
4346 struct net_device *netdev;
ebc2ec48 4347 int ret;
ac718b69 4348
10c32717 4349 if (udev->actconfig->desc.bConfigurationValue != 1) {
4350 usb_driver_set_configuration(udev, 1);
4351 return -ENODEV;
4352 }
4353
4354 usb_reset_device(udev);
ac718b69 4355 netdev = alloc_etherdev(sizeof(struct r8152));
4356 if (!netdev) {
4a8deae2 4357 dev_err(&intf->dev, "Out of memory\n");
ac718b69 4358 return -ENOMEM;
4359 }
4360
ebc2ec48 4361 SET_NETDEV_DEV(netdev, &intf->dev);
ac718b69 4362 tp = netdev_priv(netdev);
4363 tp->msg_enable = 0x7FFF;
4364
e3ad412a 4365 tp->udev = udev;
4366 tp->netdev = netdev;
4367 tp->intf = intf;
4368
82cf94cb 4369 r8152b_get_version(tp);
55b65475 4370 ret = rtl_ops_init(tp);
31ca1dec 4371 if (ret)
4372 goto out;
c81229c9 4373
b5403273 4374 mutex_init(&tp->control);
ac718b69 4375 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
a028a9e0 4376 INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
ac718b69 4377
ac718b69 4378 netdev->netdev_ops = &rtl8152_netdev_ops;
4379 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
5bd23881 4380
60c89071 4381 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
6128d1bb 4382 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
c5554298 4383 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
4384 NETIF_F_HW_VLAN_CTAG_TX;
60c89071 4385 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
6128d1bb 4386 NETIF_F_TSO | NETIF_F_FRAGLIST |
c5554298 4387 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
ccc39faf 4388 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
c5554298 4389 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
4390 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
4391 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
db8515ef 4392
19c0f40d 4393 if (tp->version == RTL_VER_01) {
4394 netdev->features &= ~NETIF_F_RXCSUM;
4395 netdev->hw_features &= ~NETIF_F_RXCSUM;
4396 }
4397
7ad24ea4 4398 netdev->ethtool_ops = &ops;
60c89071 4399 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
ac718b69 4400
f77f0aee
JW
4401 /* MTU range: 68 - 1500 or 9194 */
4402 netdev->min_mtu = ETH_MIN_MTU;
4403 switch (tp->version) {
4404 case RTL_VER_01:
4405 case RTL_VER_02:
4406 netdev->max_mtu = ETH_DATA_LEN;
4407 break;
4408 default:
4409 netdev->max_mtu = RTL8153_MAX_MTU;
4410 break;
4411 }
4412
ac718b69 4413 tp->mii.dev = netdev;
4414 tp->mii.mdio_read = read_mii_word;
4415 tp->mii.mdio_write = write_mii_word;
4416 tp->mii.phy_id_mask = 0x3f;
4417 tp->mii.reg_num_mask = 0x1f;
4418 tp->mii.phy_id = R8152_PHY_ID;
ac718b69 4419
464ec10a 4420 switch (udev->speed) {
4421 case USB_SPEED_SUPER:
2b84af94 4422 case USB_SPEED_SUPER_PLUS:
464ec10a 4423 tp->coalesce = COALESCE_SUPER;
4424 break;
4425 case USB_SPEED_HIGH:
4426 tp->coalesce = COALESCE_HIGH;
4427 break;
4428 default:
4429 tp->coalesce = COALESCE_SLOW;
4430 break;
4431 }
4432
aa7e26b6 4433 tp->autoneg = AUTONEG_ENABLE;
4434 tp->speed = tp->mii.supports_gmii ? SPEED_1000 : SPEED_100;
4435 tp->duplex = DUPLEX_FULL;
4436
9a4be1bd 4437 intf->needs_remote_wakeup = 1;
4438
c81229c9 4439 tp->rtl_ops.init(tp);
a028a9e0 4440 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
ac718b69 4441 set_ethernet_addr(tp);
4442
ac718b69 4443 usb_set_intfdata(intf, tp);
d823ab68 4444 netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
ac718b69 4445
ebc2ec48 4446 ret = register_netdev(netdev);
4447 if (ret != 0) {
4a8deae2 4448 netif_err(tp, probe, netdev, "couldn't register the device\n");
ebc2ec48 4449 goto out1;
ac718b69 4450 }
4451
7daed8dc 4452 if (!rtl_can_wakeup(tp))
4453 __rtl_set_wol(tp, 0);
4454
21ff2e89 4455 tp->saved_wolopts = __rtl_get_wol(tp);
4456 if (tp->saved_wolopts)
4457 device_set_wakeup_enable(&udev->dev, true);
4458 else
4459 device_set_wakeup_enable(&udev->dev, false);
4460
4a8deae2 4461 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
ac718b69 4462
4463 return 0;
4464
ac718b69 4465out1:
d823ab68 4466 netif_napi_del(&tp->napi);
ebc2ec48 4467 usb_set_intfdata(intf, NULL);
ac718b69 4468out:
4469 free_netdev(netdev);
ebc2ec48 4470 return ret;
ac718b69 4471}
4472
ac718b69 4473static void rtl8152_disconnect(struct usb_interface *intf)
4474{
4475 struct r8152 *tp = usb_get_intfdata(intf);
4476
4477 usb_set_intfdata(intf, NULL);
4478 if (tp) {
f561de33 4479 struct usb_device *udev = tp->udev;
4480
4481 if (udev->state == USB_STATE_NOTATTACHED)
4482 set_bit(RTL8152_UNPLUG, &tp->flags);
4483
d823ab68 4484 netif_napi_del(&tp->napi);
ac718b69 4485 unregister_netdev(tp->netdev);
a028a9e0 4486 cancel_delayed_work_sync(&tp->hw_phy_work);
c81229c9 4487 tp->rtl_ops.unload(tp);
ac718b69 4488 free_netdev(tp->netdev);
4489 }
4490}
4491
d9a28c5b 4492#define REALTEK_USB_DEVICE(vend, prod) \
4493 .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
4494 USB_DEVICE_ID_MATCH_INT_CLASS, \
4495 .idVendor = (vend), \
4496 .idProduct = (prod), \
4497 .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
4498}, \
4499{ \
4500 .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
4501 USB_DEVICE_ID_MATCH_DEVICE, \
4502 .idVendor = (vend), \
4503 .idProduct = (prod), \
4504 .bInterfaceClass = USB_CLASS_COMM, \
4505 .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
4506 .bInterfaceProtocol = USB_CDC_PROTO_NONE
4507
ac718b69 4508/* table of devices that work with this driver */
4509static struct usb_device_id rtl8152_table[] = {
d9a28c5b 4510 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
4511 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
4512 {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
1006da19 4513 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)},
d248cafc 4514 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3062)},
4515 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3069)},
4516 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)},
4517 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x720c)},
4518 {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7214)},
d065c3c1 4519 {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)},
ac718b69 4520 {}
4521};
4522
4523MODULE_DEVICE_TABLE(usb, rtl8152_table);
4524
4525static struct usb_driver rtl8152_driver = {
4526 .name = MODULENAME,
ebc2ec48 4527 .id_table = rtl8152_table,
ac718b69 4528 .probe = rtl8152_probe,
4529 .disconnect = rtl8152_disconnect,
ac718b69 4530 .suspend = rtl8152_suspend,
ebc2ec48 4531 .resume = rtl8152_resume,
7ec2541a 4532 .reset_resume = rtl8152_reset_resume,
e501139a 4533 .pre_reset = rtl8152_pre_reset,
4534 .post_reset = rtl8152_post_reset,
9a4be1bd 4535 .supports_autosuspend = 1,
a634782f 4536 .disable_hub_initiated_lpm = 1,
ac718b69 4537};
4538
b4236daa 4539module_usb_driver(rtl8152_driver);
ac718b69 4540
4541MODULE_AUTHOR(DRIVER_AUTHOR);
4542MODULE_DESCRIPTION(DRIVER_DESC);
4543MODULE_LICENSE("GPL");
c961e877 4544MODULE_VERSION(DRIVER_VERSION);