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ac718b69 | 1 | /* |
2 | * Copyright (c) 2013 Realtek Semiconductor Corp. All rights reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * version 2 as published by the Free Software Foundation. | |
7 | * | |
8 | */ | |
9 | ||
10 | #include <linux/init.h> | |
11 | #include <linux/signal.h> | |
12 | #include <linux/slab.h> | |
13 | #include <linux/module.h> | |
ac718b69 | 14 | #include <linux/netdevice.h> |
15 | #include <linux/etherdevice.h> | |
16 | #include <linux/mii.h> | |
17 | #include <linux/ethtool.h> | |
18 | #include <linux/usb.h> | |
19 | #include <linux/crc32.h> | |
20 | #include <linux/if_vlan.h> | |
21 | #include <linux/uaccess.h> | |
ebc2ec48 | 22 | #include <linux/list.h> |
5bd23881 | 23 | #include <linux/ip.h> |
24 | #include <linux/ipv6.h> | |
ac718b69 | 25 | |
26 | /* Version Information */ | |
7937f9e5 | 27 | #define DRIVER_VERSION "v1.02.0 (2013/10/28)" |
ac718b69 | 28 | #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>" |
29 | #define DRIVER_DESC "Realtek RTL8152 Based USB 2.0 Ethernet Adapters" | |
30 | #define MODULENAME "r8152" | |
31 | ||
32 | #define R8152_PHY_ID 32 | |
33 | ||
34 | #define PLA_IDR 0xc000 | |
35 | #define PLA_RCR 0xc010 | |
36 | #define PLA_RMS 0xc016 | |
37 | #define PLA_RXFIFO_CTRL0 0xc0a0 | |
38 | #define PLA_RXFIFO_CTRL1 0xc0a4 | |
39 | #define PLA_RXFIFO_CTRL2 0xc0a8 | |
40 | #define PLA_FMC 0xc0b4 | |
41 | #define PLA_CFG_WOL 0xc0b6 | |
42 | #define PLA_MAR 0xcd00 | |
43 | #define PAL_BDC_CR 0xd1a0 | |
44 | #define PLA_LEDSEL 0xdd90 | |
45 | #define PLA_LED_FEATURE 0xdd92 | |
46 | #define PLA_PHYAR 0xde00 | |
47 | #define PLA_GPHY_INTR_IMR 0xe022 | |
48 | #define PLA_EEE_CR 0xe040 | |
49 | #define PLA_EEEP_CR 0xe080 | |
50 | #define PLA_MAC_PWR_CTRL 0xe0c0 | |
51 | #define PLA_TCR0 0xe610 | |
52 | #define PLA_TCR1 0xe612 | |
53 | #define PLA_TXFIFO_CTRL 0xe618 | |
54 | #define PLA_RSTTELLY 0xe800 | |
55 | #define PLA_CR 0xe813 | |
56 | #define PLA_CRWECR 0xe81c | |
57 | #define PLA_CONFIG5 0xe822 | |
58 | #define PLA_PHY_PWR 0xe84c | |
59 | #define PLA_OOB_CTRL 0xe84f | |
60 | #define PLA_CPCR 0xe854 | |
61 | #define PLA_MISC_0 0xe858 | |
62 | #define PLA_MISC_1 0xe85a | |
63 | #define PLA_OCP_GPHY_BASE 0xe86c | |
64 | #define PLA_TELLYCNT 0xe890 | |
65 | #define PLA_SFF_STS_7 0xe8de | |
66 | #define PLA_PHYSTATUS 0xe908 | |
67 | #define PLA_BP_BA 0xfc26 | |
68 | #define PLA_BP_0 0xfc28 | |
69 | #define PLA_BP_1 0xfc2a | |
70 | #define PLA_BP_2 0xfc2c | |
71 | #define PLA_BP_3 0xfc2e | |
72 | #define PLA_BP_4 0xfc30 | |
73 | #define PLA_BP_5 0xfc32 | |
74 | #define PLA_BP_6 0xfc34 | |
75 | #define PLA_BP_7 0xfc36 | |
76 | ||
77 | #define USB_DEV_STAT 0xb808 | |
78 | #define USB_USB_CTRL 0xd406 | |
79 | #define USB_PHY_CTRL 0xd408 | |
80 | #define USB_TX_AGG 0xd40a | |
81 | #define USB_RX_BUF_TH 0xd40c | |
82 | #define USB_USB_TIMER 0xd428 | |
83 | #define USB_PM_CTRL_STATUS 0xd432 | |
84 | #define USB_TX_DMA 0xd434 | |
85 | #define USB_UPS_CTRL 0xd800 | |
86 | #define USB_BP_BA 0xfc26 | |
87 | #define USB_BP_0 0xfc28 | |
88 | #define USB_BP_1 0xfc2a | |
89 | #define USB_BP_2 0xfc2c | |
90 | #define USB_BP_3 0xfc2e | |
91 | #define USB_BP_4 0xfc30 | |
92 | #define USB_BP_5 0xfc32 | |
93 | #define USB_BP_6 0xfc34 | |
94 | #define USB_BP_7 0xfc36 | |
95 | ||
96 | /* OCP Registers */ | |
97 | #define OCP_ALDPS_CONFIG 0x2010 | |
98 | #define OCP_EEE_CONFIG1 0x2080 | |
99 | #define OCP_EEE_CONFIG2 0x2092 | |
100 | #define OCP_EEE_CONFIG3 0x2094 | |
ac244d3e | 101 | #define OCP_BASE_MII 0xa400 |
ac718b69 | 102 | #define OCP_EEE_AR 0xa41a |
103 | #define OCP_EEE_DATA 0xa41c | |
104 | ||
105 | /* PLA_RCR */ | |
106 | #define RCR_AAP 0x00000001 | |
107 | #define RCR_APM 0x00000002 | |
108 | #define RCR_AM 0x00000004 | |
109 | #define RCR_AB 0x00000008 | |
110 | #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB) | |
111 | ||
112 | /* PLA_RXFIFO_CTRL0 */ | |
113 | #define RXFIFO_THR1_NORMAL 0x00080002 | |
114 | #define RXFIFO_THR1_OOB 0x01800003 | |
115 | ||
116 | /* PLA_RXFIFO_CTRL1 */ | |
117 | #define RXFIFO_THR2_FULL 0x00000060 | |
118 | #define RXFIFO_THR2_HIGH 0x00000038 | |
119 | #define RXFIFO_THR2_OOB 0x0000004a | |
120 | ||
121 | /* PLA_RXFIFO_CTRL2 */ | |
122 | #define RXFIFO_THR3_FULL 0x00000078 | |
123 | #define RXFIFO_THR3_HIGH 0x00000048 | |
124 | #define RXFIFO_THR3_OOB 0x0000005a | |
125 | ||
126 | /* PLA_TXFIFO_CTRL */ | |
127 | #define TXFIFO_THR_NORMAL 0x00400008 | |
128 | ||
129 | /* PLA_FMC */ | |
130 | #define FMC_FCR_MCU_EN 0x0001 | |
131 | ||
132 | /* PLA_EEEP_CR */ | |
133 | #define EEEP_CR_EEEP_TX 0x0002 | |
134 | ||
135 | /* PLA_TCR0 */ | |
136 | #define TCR0_TX_EMPTY 0x0800 | |
137 | #define TCR0_AUTO_FIFO 0x0080 | |
138 | ||
139 | /* PLA_TCR1 */ | |
140 | #define VERSION_MASK 0x7cf0 | |
141 | ||
142 | /* PLA_CR */ | |
143 | #define CR_RST 0x10 | |
144 | #define CR_RE 0x08 | |
145 | #define CR_TE 0x04 | |
146 | ||
147 | /* PLA_CRWECR */ | |
148 | #define CRWECR_NORAML 0x00 | |
149 | #define CRWECR_CONFIG 0xc0 | |
150 | ||
151 | /* PLA_OOB_CTRL */ | |
152 | #define NOW_IS_OOB 0x80 | |
153 | #define TXFIFO_EMPTY 0x20 | |
154 | #define RXFIFO_EMPTY 0x10 | |
155 | #define LINK_LIST_READY 0x02 | |
156 | #define DIS_MCU_CLROOB 0x01 | |
157 | #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY) | |
158 | ||
159 | /* PLA_MISC_1 */ | |
160 | #define RXDY_GATED_EN 0x0008 | |
161 | ||
162 | /* PLA_SFF_STS_7 */ | |
163 | #define RE_INIT_LL 0x8000 | |
164 | #define MCU_BORW_EN 0x4000 | |
165 | ||
166 | /* PLA_CPCR */ | |
167 | #define CPCR_RX_VLAN 0x0040 | |
168 | ||
169 | /* PLA_CFG_WOL */ | |
170 | #define MAGIC_EN 0x0001 | |
171 | ||
172 | /* PAL_BDC_CR */ | |
173 | #define ALDPS_PROXY_MODE 0x0001 | |
174 | ||
175 | /* PLA_CONFIG5 */ | |
176 | #define LAN_WAKE_EN 0x0002 | |
177 | ||
178 | /* PLA_LED_FEATURE */ | |
179 | #define LED_MODE_MASK 0x0700 | |
180 | ||
181 | /* PLA_PHY_PWR */ | |
182 | #define TX_10M_IDLE_EN 0x0080 | |
183 | #define PFM_PWM_SWITCH 0x0040 | |
184 | ||
185 | /* PLA_MAC_PWR_CTRL */ | |
186 | #define D3_CLK_GATED_EN 0x00004000 | |
187 | #define MCU_CLK_RATIO 0x07010f07 | |
188 | #define MCU_CLK_RATIO_MASK 0x0f0f0f0f | |
189 | ||
190 | /* PLA_GPHY_INTR_IMR */ | |
191 | #define GPHY_STS_MSK 0x0001 | |
192 | #define SPEED_DOWN_MSK 0x0002 | |
193 | #define SPDWN_RXDV_MSK 0x0004 | |
194 | #define SPDWN_LINKCHG_MSK 0x0008 | |
195 | ||
196 | /* PLA_PHYAR */ | |
197 | #define PHYAR_FLAG 0x80000000 | |
198 | ||
199 | /* PLA_EEE_CR */ | |
200 | #define EEE_RX_EN 0x0001 | |
201 | #define EEE_TX_EN 0x0002 | |
202 | ||
203 | /* USB_DEV_STAT */ | |
204 | #define STAT_SPEED_MASK 0x0006 | |
205 | #define STAT_SPEED_HIGH 0x0000 | |
206 | #define STAT_SPEED_FULL 0x0001 | |
207 | ||
208 | /* USB_TX_AGG */ | |
209 | #define TX_AGG_MAX_THRESHOLD 0x03 | |
210 | ||
211 | /* USB_RX_BUF_TH */ | |
8e1f51bd | 212 | #define RX_THR_HIGH 0x7a120180 |
ac718b69 | 213 | |
214 | /* USB_TX_DMA */ | |
215 | #define TEST_MODE_DISABLE 0x00000001 | |
216 | #define TX_SIZE_ADJUST1 0x00000100 | |
217 | ||
218 | /* USB_UPS_CTRL */ | |
219 | #define POWER_CUT 0x0100 | |
220 | ||
221 | /* USB_PM_CTRL_STATUS */ | |
8e1f51bd | 222 | #define RESUME_INDICATE 0x0001 |
ac718b69 | 223 | |
224 | /* USB_USB_CTRL */ | |
225 | #define RX_AGG_DISABLE 0x0010 | |
226 | ||
227 | /* OCP_ALDPS_CONFIG */ | |
228 | #define ENPWRSAVE 0x8000 | |
229 | #define ENPDNPS 0x0200 | |
230 | #define LINKENA 0x0100 | |
231 | #define DIS_SDSAVE 0x0010 | |
232 | ||
233 | /* OCP_EEE_CONFIG1 */ | |
234 | #define RG_TXLPI_MSK_HFDUP 0x8000 | |
235 | #define RG_MATCLR_EN 0x4000 | |
236 | #define EEE_10_CAP 0x2000 | |
237 | #define EEE_NWAY_EN 0x1000 | |
238 | #define TX_QUIET_EN 0x0200 | |
239 | #define RX_QUIET_EN 0x0100 | |
240 | #define SDRISETIME 0x0010 /* bit 4 ~ 6 */ | |
241 | #define RG_RXLPI_MSK_HFDUP 0x0008 | |
242 | #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */ | |
243 | ||
244 | /* OCP_EEE_CONFIG2 */ | |
245 | #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */ | |
246 | #define RG_DACQUIET_EN 0x0400 | |
247 | #define RG_LDVQUIET_EN 0x0200 | |
248 | #define RG_CKRSEL 0x0020 | |
249 | #define RG_EEEPRG_EN 0x0010 | |
250 | ||
251 | /* OCP_EEE_CONFIG3 */ | |
252 | #define FST_SNR_EYE_R 0x1500 /* bit 7 ~ 15 */ | |
253 | #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */ | |
254 | #define MSK_PH 0x0006 /* bit 0 ~ 3 */ | |
255 | ||
256 | /* OCP_EEE_AR */ | |
257 | /* bit[15:14] function */ | |
258 | #define FUN_ADDR 0x0000 | |
259 | #define FUN_DATA 0x4000 | |
260 | /* bit[4:0] device addr */ | |
261 | #define DEVICE_ADDR 0x0007 | |
262 | ||
263 | /* OCP_EEE_DATA */ | |
264 | #define EEE_ADDR 0x003C | |
265 | #define EEE_DATA 0x0002 | |
266 | ||
267 | enum rtl_register_content { | |
268 | _100bps = 0x08, | |
269 | _10bps = 0x04, | |
270 | LINK_STATUS = 0x02, | |
271 | FULL_DUP = 0x01, | |
272 | }; | |
273 | ||
ebc2ec48 | 274 | #define RTL8152_MAX_TX 10 |
275 | #define RTL8152_MAX_RX 10 | |
40a82917 | 276 | #define INTBUFSIZE 2 |
8e1f51bd | 277 | #define CRC_SIZE 4 |
278 | #define TX_ALIGN 4 | |
279 | #define RX_ALIGN 8 | |
40a82917 | 280 | |
281 | #define INTR_LINK 0x0004 | |
ebc2ec48 | 282 | |
ac718b69 | 283 | #define RTL8152_REQT_READ 0xc0 |
284 | #define RTL8152_REQT_WRITE 0x40 | |
285 | #define RTL8152_REQ_GET_REGS 0x05 | |
286 | #define RTL8152_REQ_SET_REGS 0x05 | |
287 | ||
288 | #define BYTE_EN_DWORD 0xff | |
289 | #define BYTE_EN_WORD 0x33 | |
290 | #define BYTE_EN_BYTE 0x11 | |
291 | #define BYTE_EN_SIX_BYTES 0x3f | |
292 | #define BYTE_EN_START_MASK 0x0f | |
293 | #define BYTE_EN_END_MASK 0xf0 | |
294 | ||
295 | #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN) | |
296 | #define RTL8152_TX_TIMEOUT (HZ) | |
297 | ||
298 | /* rtl8152 flags */ | |
299 | enum rtl8152_flags { | |
300 | RTL8152_UNPLUG = 0, | |
ac718b69 | 301 | RTL8152_SET_RX_MODE, |
40a82917 | 302 | WORK_ENABLE, |
303 | RTL8152_LINK_CHG, | |
ac718b69 | 304 | }; |
305 | ||
306 | /* Define these values to match your device */ | |
307 | #define VENDOR_ID_REALTEK 0x0bda | |
308 | #define PRODUCT_ID_RTL8152 0x8152 | |
309 | ||
310 | #define MCU_TYPE_PLA 0x0100 | |
311 | #define MCU_TYPE_USB 0x0000 | |
312 | ||
313 | struct rx_desc { | |
500b6d7e | 314 | __le32 opts1; |
ac718b69 | 315 | #define RX_LEN_MASK 0x7fff |
500b6d7e | 316 | __le32 opts2; |
317 | __le32 opts3; | |
318 | __le32 opts4; | |
319 | __le32 opts5; | |
320 | __le32 opts6; | |
ac718b69 | 321 | }; |
322 | ||
323 | struct tx_desc { | |
500b6d7e | 324 | __le32 opts1; |
ac718b69 | 325 | #define TX_FS (1 << 31) /* First segment of a packet */ |
326 | #define TX_LS (1 << 30) /* Final segment of a packet */ | |
5bd23881 | 327 | #define TX_LEN_MASK 0x3ffff |
328 | ||
500b6d7e | 329 | __le32 opts2; |
5bd23881 | 330 | #define UDP_CS (1 << 31) /* Calculate UDP/IP checksum */ |
331 | #define TCP_CS (1 << 30) /* Calculate TCP/IP checksum */ | |
332 | #define IPV4_CS (1 << 29) /* Calculate IPv4 checksum */ | |
333 | #define IPV6_CS (1 << 28) /* Calculate IPv6 checksum */ | |
ac718b69 | 334 | }; |
335 | ||
dff4e8ad | 336 | struct r8152; |
337 | ||
ebc2ec48 | 338 | struct rx_agg { |
339 | struct list_head list; | |
340 | struct urb *urb; | |
dff4e8ad | 341 | struct r8152 *context; |
ebc2ec48 | 342 | void *buffer; |
343 | void *head; | |
344 | }; | |
345 | ||
346 | struct tx_agg { | |
347 | struct list_head list; | |
348 | struct urb *urb; | |
dff4e8ad | 349 | struct r8152 *context; |
ebc2ec48 | 350 | void *buffer; |
351 | void *head; | |
352 | u32 skb_num; | |
353 | u32 skb_len; | |
354 | }; | |
355 | ||
ac718b69 | 356 | struct r8152 { |
357 | unsigned long flags; | |
358 | struct usb_device *udev; | |
359 | struct tasklet_struct tl; | |
40a82917 | 360 | struct usb_interface *intf; |
ac718b69 | 361 | struct net_device *netdev; |
40a82917 | 362 | struct urb *intr_urb; |
ebc2ec48 | 363 | struct tx_agg tx_info[RTL8152_MAX_TX]; |
364 | struct rx_agg rx_info[RTL8152_MAX_RX]; | |
365 | struct list_head rx_done, tx_free; | |
366 | struct sk_buff_head tx_queue; | |
367 | spinlock_t rx_lock, tx_lock; | |
ac718b69 | 368 | struct delayed_work schedule; |
369 | struct mii_if_info mii; | |
c81229c9 | 370 | |
371 | struct rtl_ops { | |
372 | void (*init)(struct r8152 *); | |
373 | int (*enable)(struct r8152 *); | |
374 | void (*disable)(struct r8152 *); | |
375 | void (*down)(struct r8152 *); | |
376 | void (*unload)(struct r8152 *); | |
377 | } rtl_ops; | |
378 | ||
40a82917 | 379 | int intr_interval; |
ac718b69 | 380 | u32 msg_enable; |
dd1b119c | 381 | u32 tx_qlen; |
ac718b69 | 382 | u16 ocp_base; |
40a82917 | 383 | u8 *intr_buff; |
ac718b69 | 384 | u8 version; |
385 | u8 speed; | |
386 | }; | |
387 | ||
388 | enum rtl_version { | |
389 | RTL_VER_UNKNOWN = 0, | |
390 | RTL_VER_01, | |
391 | RTL_VER_02 | |
392 | }; | |
393 | ||
394 | /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). | |
395 | * The RTL chips use a 64 element hash table based on the Ethernet CRC. | |
396 | */ | |
397 | static const int multicast_filter_limit = 32; | |
ebc2ec48 | 398 | static unsigned int rx_buf_sz = 16384; |
ac718b69 | 399 | |
400 | static | |
401 | int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) | |
402 | { | |
31787f53 | 403 | int ret; |
404 | void *tmp; | |
405 | ||
406 | tmp = kmalloc(size, GFP_KERNEL); | |
407 | if (!tmp) | |
408 | return -ENOMEM; | |
409 | ||
410 | ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0), | |
ac718b69 | 411 | RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, |
31787f53 | 412 | value, index, tmp, size, 500); |
413 | ||
414 | memcpy(data, tmp, size); | |
415 | kfree(tmp); | |
416 | ||
417 | return ret; | |
ac718b69 | 418 | } |
419 | ||
420 | static | |
421 | int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) | |
422 | { | |
31787f53 | 423 | int ret; |
424 | void *tmp; | |
425 | ||
426 | tmp = kmalloc(size, GFP_KERNEL); | |
427 | if (!tmp) | |
428 | return -ENOMEM; | |
429 | ||
430 | memcpy(tmp, data, size); | |
431 | ||
432 | ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0), | |
ac718b69 | 433 | RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE, |
31787f53 | 434 | value, index, tmp, size, 500); |
435 | ||
436 | kfree(tmp); | |
437 | return ret; | |
ac718b69 | 438 | } |
439 | ||
440 | static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size, | |
441 | void *data, u16 type) | |
442 | { | |
443 | u16 limit = 64; | |
444 | int ret = 0; | |
445 | ||
446 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
447 | return -ENODEV; | |
448 | ||
449 | /* both size and indix must be 4 bytes align */ | |
450 | if ((size & 3) || !size || (index & 3) || !data) | |
451 | return -EPERM; | |
452 | ||
453 | if ((u32)index + (u32)size > 0xffff) | |
454 | return -EPERM; | |
455 | ||
456 | while (size) { | |
457 | if (size > limit) { | |
458 | ret = get_registers(tp, index, type, limit, data); | |
459 | if (ret < 0) | |
460 | break; | |
461 | ||
462 | index += limit; | |
463 | data += limit; | |
464 | size -= limit; | |
465 | } else { | |
466 | ret = get_registers(tp, index, type, size, data); | |
467 | if (ret < 0) | |
468 | break; | |
469 | ||
470 | index += size; | |
471 | data += size; | |
472 | size = 0; | |
473 | break; | |
474 | } | |
475 | } | |
476 | ||
477 | return ret; | |
478 | } | |
479 | ||
480 | static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, | |
481 | u16 size, void *data, u16 type) | |
482 | { | |
483 | int ret; | |
484 | u16 byteen_start, byteen_end, byen; | |
485 | u16 limit = 512; | |
486 | ||
487 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
488 | return -ENODEV; | |
489 | ||
490 | /* both size and indix must be 4 bytes align */ | |
491 | if ((size & 3) || !size || (index & 3) || !data) | |
492 | return -EPERM; | |
493 | ||
494 | if ((u32)index + (u32)size > 0xffff) | |
495 | return -EPERM; | |
496 | ||
497 | byteen_start = byteen & BYTE_EN_START_MASK; | |
498 | byteen_end = byteen & BYTE_EN_END_MASK; | |
499 | ||
500 | byen = byteen_start | (byteen_start << 4); | |
501 | ret = set_registers(tp, index, type | byen, 4, data); | |
502 | if (ret < 0) | |
503 | goto error1; | |
504 | ||
505 | index += 4; | |
506 | data += 4; | |
507 | size -= 4; | |
508 | ||
509 | if (size) { | |
510 | size -= 4; | |
511 | ||
512 | while (size) { | |
513 | if (size > limit) { | |
514 | ret = set_registers(tp, index, | |
515 | type | BYTE_EN_DWORD, | |
516 | limit, data); | |
517 | if (ret < 0) | |
518 | goto error1; | |
519 | ||
520 | index += limit; | |
521 | data += limit; | |
522 | size -= limit; | |
523 | } else { | |
524 | ret = set_registers(tp, index, | |
525 | type | BYTE_EN_DWORD, | |
526 | size, data); | |
527 | if (ret < 0) | |
528 | goto error1; | |
529 | ||
530 | index += size; | |
531 | data += size; | |
532 | size = 0; | |
533 | break; | |
534 | } | |
535 | } | |
536 | ||
537 | byen = byteen_end | (byteen_end >> 4); | |
538 | ret = set_registers(tp, index, type | byen, 4, data); | |
539 | if (ret < 0) | |
540 | goto error1; | |
541 | } | |
542 | ||
543 | error1: | |
544 | return ret; | |
545 | } | |
546 | ||
547 | static inline | |
548 | int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) | |
549 | { | |
550 | return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA); | |
551 | } | |
552 | ||
553 | static inline | |
554 | int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) | |
555 | { | |
556 | return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA); | |
557 | } | |
558 | ||
559 | static inline | |
560 | int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) | |
561 | { | |
562 | return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB); | |
563 | } | |
564 | ||
565 | static inline | |
566 | int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) | |
567 | { | |
568 | return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB); | |
569 | } | |
570 | ||
571 | static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index) | |
572 | { | |
c8826de8 | 573 | __le32 data; |
ac718b69 | 574 | |
c8826de8 | 575 | generic_ocp_read(tp, index, sizeof(data), &data, type); |
ac718b69 | 576 | |
577 | return __le32_to_cpu(data); | |
578 | } | |
579 | ||
580 | static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data) | |
581 | { | |
c8826de8 | 582 | __le32 tmp = __cpu_to_le32(data); |
583 | ||
584 | generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type); | |
ac718b69 | 585 | } |
586 | ||
587 | static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index) | |
588 | { | |
589 | u32 data; | |
c8826de8 | 590 | __le32 tmp; |
ac718b69 | 591 | u8 shift = index & 2; |
592 | ||
593 | index &= ~3; | |
594 | ||
c8826de8 | 595 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 596 | |
c8826de8 | 597 | data = __le32_to_cpu(tmp); |
ac718b69 | 598 | data >>= (shift * 8); |
599 | data &= 0xffff; | |
600 | ||
601 | return (u16)data; | |
602 | } | |
603 | ||
604 | static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data) | |
605 | { | |
c8826de8 | 606 | u32 mask = 0xffff; |
607 | __le32 tmp; | |
ac718b69 | 608 | u16 byen = BYTE_EN_WORD; |
609 | u8 shift = index & 2; | |
610 | ||
611 | data &= mask; | |
612 | ||
613 | if (index & 2) { | |
614 | byen <<= shift; | |
615 | mask <<= (shift * 8); | |
616 | data <<= (shift * 8); | |
617 | index &= ~3; | |
618 | } | |
619 | ||
c8826de8 | 620 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 621 | |
c8826de8 | 622 | data |= __le32_to_cpu(tmp) & ~mask; |
623 | tmp = __cpu_to_le32(data); | |
ac718b69 | 624 | |
c8826de8 | 625 | generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); |
ac718b69 | 626 | } |
627 | ||
628 | static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index) | |
629 | { | |
630 | u32 data; | |
c8826de8 | 631 | __le32 tmp; |
ac718b69 | 632 | u8 shift = index & 3; |
633 | ||
634 | index &= ~3; | |
635 | ||
c8826de8 | 636 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 637 | |
c8826de8 | 638 | data = __le32_to_cpu(tmp); |
ac718b69 | 639 | data >>= (shift * 8); |
640 | data &= 0xff; | |
641 | ||
642 | return (u8)data; | |
643 | } | |
644 | ||
645 | static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data) | |
646 | { | |
c8826de8 | 647 | u32 mask = 0xff; |
648 | __le32 tmp; | |
ac718b69 | 649 | u16 byen = BYTE_EN_BYTE; |
650 | u8 shift = index & 3; | |
651 | ||
652 | data &= mask; | |
653 | ||
654 | if (index & 3) { | |
655 | byen <<= shift; | |
656 | mask <<= (shift * 8); | |
657 | data <<= (shift * 8); | |
658 | index &= ~3; | |
659 | } | |
660 | ||
c8826de8 | 661 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 662 | |
c8826de8 | 663 | data |= __le32_to_cpu(tmp) & ~mask; |
664 | tmp = __cpu_to_le32(data); | |
ac718b69 | 665 | |
c8826de8 | 666 | generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); |
ac718b69 | 667 | } |
668 | ||
ac244d3e | 669 | static u16 ocp_reg_read(struct r8152 *tp, u16 addr) |
e3fe0b1a | 670 | { |
671 | u16 ocp_base, ocp_index; | |
672 | ||
673 | ocp_base = addr & 0xf000; | |
674 | if (ocp_base != tp->ocp_base) { | |
675 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); | |
676 | tp->ocp_base = ocp_base; | |
677 | } | |
678 | ||
679 | ocp_index = (addr & 0x0fff) | 0xb000; | |
ac244d3e | 680 | return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index); |
e3fe0b1a | 681 | } |
682 | ||
ac244d3e | 683 | static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) |
ac718b69 | 684 | { |
ac244d3e | 685 | u16 ocp_base, ocp_index; |
ac718b69 | 686 | |
ac244d3e | 687 | ocp_base = addr & 0xf000; |
688 | if (ocp_base != tp->ocp_base) { | |
689 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); | |
690 | tp->ocp_base = ocp_base; | |
ac718b69 | 691 | } |
ac244d3e | 692 | |
693 | ocp_index = (addr & 0x0fff) | 0xb000; | |
694 | ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data); | |
ac718b69 | 695 | } |
696 | ||
ac244d3e | 697 | static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value) |
ac718b69 | 698 | { |
ac244d3e | 699 | ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value); |
700 | } | |
ac718b69 | 701 | |
ac244d3e | 702 | static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr) |
703 | { | |
704 | return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2); | |
ac718b69 | 705 | } |
706 | ||
707 | static int read_mii_word(struct net_device *netdev, int phy_id, int reg) | |
708 | { | |
709 | struct r8152 *tp = netdev_priv(netdev); | |
710 | ||
711 | if (phy_id != R8152_PHY_ID) | |
712 | return -EINVAL; | |
713 | ||
714 | return r8152_mdio_read(tp, reg); | |
715 | } | |
716 | ||
717 | static | |
718 | void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val) | |
719 | { | |
720 | struct r8152 *tp = netdev_priv(netdev); | |
721 | ||
722 | if (phy_id != R8152_PHY_ID) | |
723 | return; | |
724 | ||
725 | r8152_mdio_write(tp, reg, val); | |
726 | } | |
727 | ||
ebc2ec48 | 728 | static |
729 | int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags); | |
730 | ||
ac718b69 | 731 | static inline void set_ethernet_addr(struct r8152 *tp) |
732 | { | |
733 | struct net_device *dev = tp->netdev; | |
31787f53 | 734 | u8 node_id[8] = {0}; |
ac718b69 | 735 | |
31787f53 | 736 | if (pla_ocp_read(tp, PLA_IDR, sizeof(node_id), node_id) < 0) |
ac718b69 | 737 | netif_notice(tp, probe, dev, "inet addr fail\n"); |
738 | else { | |
739 | memcpy(dev->dev_addr, node_id, dev->addr_len); | |
740 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); | |
741 | } | |
ac718b69 | 742 | } |
743 | ||
744 | static int rtl8152_set_mac_address(struct net_device *netdev, void *p) | |
745 | { | |
746 | struct r8152 *tp = netdev_priv(netdev); | |
747 | struct sockaddr *addr = p; | |
748 | ||
749 | if (!is_valid_ether_addr(addr->sa_data)) | |
750 | return -EADDRNOTAVAIL; | |
751 | ||
752 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
753 | ||
754 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
755 | pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data); | |
756 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
757 | ||
758 | return 0; | |
759 | } | |
760 | ||
ac718b69 | 761 | static struct net_device_stats *rtl8152_get_stats(struct net_device *dev) |
762 | { | |
763 | return &dev->stats; | |
764 | } | |
765 | ||
766 | static void read_bulk_callback(struct urb *urb) | |
767 | { | |
ac718b69 | 768 | struct net_device *netdev; |
a5a4f468 | 769 | unsigned long flags; |
ac718b69 | 770 | int status = urb->status; |
ebc2ec48 | 771 | struct rx_agg *agg; |
772 | struct r8152 *tp; | |
ac718b69 | 773 | int result; |
ac718b69 | 774 | |
ebc2ec48 | 775 | agg = urb->context; |
776 | if (!agg) | |
777 | return; | |
778 | ||
779 | tp = agg->context; | |
ac718b69 | 780 | if (!tp) |
781 | return; | |
ebc2ec48 | 782 | |
ac718b69 | 783 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
784 | return; | |
ebc2ec48 | 785 | |
786 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
787 | return; | |
788 | ||
ac718b69 | 789 | netdev = tp->netdev; |
7559fb2f | 790 | |
791 | /* When link down, the driver would cancel all bulks. */ | |
792 | /* This avoid the re-submitting bulk */ | |
ebc2ec48 | 793 | if (!netif_carrier_ok(netdev)) |
ac718b69 | 794 | return; |
795 | ||
ac718b69 | 796 | switch (status) { |
797 | case 0: | |
ebc2ec48 | 798 | if (urb->actual_length < ETH_ZLEN) |
799 | break; | |
800 | ||
a5a4f468 | 801 | spin_lock_irqsave(&tp->rx_lock, flags); |
ebc2ec48 | 802 | list_add_tail(&agg->list, &tp->rx_done); |
a5a4f468 | 803 | spin_unlock_irqrestore(&tp->rx_lock, flags); |
ebc2ec48 | 804 | tasklet_schedule(&tp->tl); |
805 | return; | |
ac718b69 | 806 | case -ESHUTDOWN: |
807 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
808 | netif_device_detach(tp->netdev); | |
ebc2ec48 | 809 | return; |
ac718b69 | 810 | case -ENOENT: |
811 | return; /* the urb is in unlink state */ | |
812 | case -ETIME: | |
813 | pr_warn_ratelimited("may be reset is needed?..\n"); | |
ebc2ec48 | 814 | break; |
ac718b69 | 815 | default: |
816 | pr_warn_ratelimited("Rx status %d\n", status); | |
ebc2ec48 | 817 | break; |
ac718b69 | 818 | } |
819 | ||
ebc2ec48 | 820 | result = r8152_submit_rx(tp, agg, GFP_ATOMIC); |
ac718b69 | 821 | if (result == -ENODEV) { |
822 | netif_device_detach(tp->netdev); | |
823 | } else if (result) { | |
a5a4f468 | 824 | spin_lock_irqsave(&tp->rx_lock, flags); |
ebc2ec48 | 825 | list_add_tail(&agg->list, &tp->rx_done); |
a5a4f468 | 826 | spin_unlock_irqrestore(&tp->rx_lock, flags); |
ebc2ec48 | 827 | tasklet_schedule(&tp->tl); |
ac718b69 | 828 | } |
ac718b69 | 829 | } |
830 | ||
ebc2ec48 | 831 | static void write_bulk_callback(struct urb *urb) |
ac718b69 | 832 | { |
ebc2ec48 | 833 | struct net_device_stats *stats; |
a5a4f468 | 834 | unsigned long flags; |
ebc2ec48 | 835 | struct tx_agg *agg; |
ac718b69 | 836 | struct r8152 *tp; |
ebc2ec48 | 837 | int status = urb->status; |
ac718b69 | 838 | |
ebc2ec48 | 839 | agg = urb->context; |
840 | if (!agg) | |
ac718b69 | 841 | return; |
842 | ||
ebc2ec48 | 843 | tp = agg->context; |
844 | if (!tp) | |
845 | return; | |
846 | ||
847 | stats = rtl8152_get_stats(tp->netdev); | |
848 | if (status) { | |
849 | pr_warn_ratelimited("Tx status %d\n", status); | |
850 | stats->tx_errors += agg->skb_num; | |
ac718b69 | 851 | } else { |
ebc2ec48 | 852 | stats->tx_packets += agg->skb_num; |
853 | stats->tx_bytes += agg->skb_len; | |
ac718b69 | 854 | } |
855 | ||
a5a4f468 | 856 | spin_lock_irqsave(&tp->tx_lock, flags); |
ebc2ec48 | 857 | list_add_tail(&agg->list, &tp->tx_free); |
a5a4f468 | 858 | spin_unlock_irqrestore(&tp->tx_lock, flags); |
ebc2ec48 | 859 | |
860 | if (!netif_carrier_ok(tp->netdev)) | |
861 | return; | |
862 | ||
863 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
864 | return; | |
865 | ||
866 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
867 | return; | |
868 | ||
869 | if (!skb_queue_empty(&tp->tx_queue)) | |
870 | tasklet_schedule(&tp->tl); | |
ac718b69 | 871 | } |
872 | ||
40a82917 | 873 | static void intr_callback(struct urb *urb) |
874 | { | |
875 | struct r8152 *tp; | |
500b6d7e | 876 | __le16 *d; |
40a82917 | 877 | int status = urb->status; |
878 | int res; | |
879 | ||
880 | tp = urb->context; | |
881 | if (!tp) | |
882 | return; | |
883 | ||
884 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
885 | return; | |
886 | ||
887 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
888 | return; | |
889 | ||
890 | switch (status) { | |
891 | case 0: /* success */ | |
892 | break; | |
893 | case -ECONNRESET: /* unlink */ | |
894 | case -ESHUTDOWN: | |
895 | netif_device_detach(tp->netdev); | |
896 | case -ENOENT: | |
897 | return; | |
898 | case -EOVERFLOW: | |
899 | netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n"); | |
900 | goto resubmit; | |
901 | /* -EPIPE: should clear the halt */ | |
902 | default: | |
903 | netif_info(tp, intr, tp->netdev, "intr status %d\n", status); | |
904 | goto resubmit; | |
905 | } | |
906 | ||
907 | d = urb->transfer_buffer; | |
908 | if (INTR_LINK & __le16_to_cpu(d[0])) { | |
909 | if (!(tp->speed & LINK_STATUS)) { | |
910 | set_bit(RTL8152_LINK_CHG, &tp->flags); | |
911 | schedule_delayed_work(&tp->schedule, 0); | |
912 | } | |
913 | } else { | |
914 | if (tp->speed & LINK_STATUS) { | |
915 | set_bit(RTL8152_LINK_CHG, &tp->flags); | |
916 | schedule_delayed_work(&tp->schedule, 0); | |
917 | } | |
918 | } | |
919 | ||
920 | resubmit: | |
921 | res = usb_submit_urb(urb, GFP_ATOMIC); | |
922 | if (res == -ENODEV) | |
923 | netif_device_detach(tp->netdev); | |
924 | else if (res) | |
925 | netif_err(tp, intr, tp->netdev, | |
926 | "can't resubmit intr, status %d\n", res); | |
927 | } | |
928 | ||
ebc2ec48 | 929 | static inline void *rx_agg_align(void *data) |
930 | { | |
8e1f51bd | 931 | return (void *)ALIGN((uintptr_t)data, RX_ALIGN); |
ebc2ec48 | 932 | } |
933 | ||
934 | static inline void *tx_agg_align(void *data) | |
935 | { | |
8e1f51bd | 936 | return (void *)ALIGN((uintptr_t)data, TX_ALIGN); |
ebc2ec48 | 937 | } |
938 | ||
939 | static void free_all_mem(struct r8152 *tp) | |
940 | { | |
941 | int i; | |
942 | ||
943 | for (i = 0; i < RTL8152_MAX_RX; i++) { | |
944 | if (tp->rx_info[i].urb) { | |
945 | usb_free_urb(tp->rx_info[i].urb); | |
946 | tp->rx_info[i].urb = NULL; | |
947 | } | |
948 | ||
949 | if (tp->rx_info[i].buffer) { | |
950 | kfree(tp->rx_info[i].buffer); | |
951 | tp->rx_info[i].buffer = NULL; | |
952 | tp->rx_info[i].head = NULL; | |
953 | } | |
954 | } | |
955 | ||
956 | for (i = 0; i < RTL8152_MAX_TX; i++) { | |
957 | if (tp->tx_info[i].urb) { | |
958 | usb_free_urb(tp->tx_info[i].urb); | |
959 | tp->tx_info[i].urb = NULL; | |
960 | } | |
961 | ||
962 | if (tp->tx_info[i].buffer) { | |
963 | kfree(tp->tx_info[i].buffer); | |
964 | tp->tx_info[i].buffer = NULL; | |
965 | tp->tx_info[i].head = NULL; | |
966 | } | |
967 | } | |
40a82917 | 968 | |
969 | if (tp->intr_urb) { | |
970 | usb_free_urb(tp->intr_urb); | |
971 | tp->intr_urb = NULL; | |
972 | } | |
973 | ||
974 | if (tp->intr_buff) { | |
975 | kfree(tp->intr_buff); | |
976 | tp->intr_buff = NULL; | |
977 | } | |
ebc2ec48 | 978 | } |
979 | ||
980 | static int alloc_all_mem(struct r8152 *tp) | |
981 | { | |
982 | struct net_device *netdev = tp->netdev; | |
40a82917 | 983 | struct usb_interface *intf = tp->intf; |
984 | struct usb_host_interface *alt = intf->cur_altsetting; | |
985 | struct usb_host_endpoint *ep_intr = alt->endpoint + 2; | |
ebc2ec48 | 986 | struct urb *urb; |
987 | int node, i; | |
988 | u8 *buf; | |
989 | ||
990 | node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; | |
991 | ||
992 | spin_lock_init(&tp->rx_lock); | |
993 | spin_lock_init(&tp->tx_lock); | |
994 | INIT_LIST_HEAD(&tp->rx_done); | |
995 | INIT_LIST_HEAD(&tp->tx_free); | |
996 | skb_queue_head_init(&tp->tx_queue); | |
997 | ||
998 | for (i = 0; i < RTL8152_MAX_RX; i++) { | |
999 | buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node); | |
1000 | if (!buf) | |
1001 | goto err1; | |
1002 | ||
1003 | if (buf != rx_agg_align(buf)) { | |
1004 | kfree(buf); | |
8e1f51bd | 1005 | buf = kmalloc_node(rx_buf_sz + RX_ALIGN, GFP_KERNEL, |
1006 | node); | |
ebc2ec48 | 1007 | if (!buf) |
1008 | goto err1; | |
1009 | } | |
1010 | ||
1011 | urb = usb_alloc_urb(0, GFP_KERNEL); | |
1012 | if (!urb) { | |
1013 | kfree(buf); | |
1014 | goto err1; | |
1015 | } | |
1016 | ||
1017 | INIT_LIST_HEAD(&tp->rx_info[i].list); | |
1018 | tp->rx_info[i].context = tp; | |
1019 | tp->rx_info[i].urb = urb; | |
1020 | tp->rx_info[i].buffer = buf; | |
1021 | tp->rx_info[i].head = rx_agg_align(buf); | |
1022 | } | |
1023 | ||
1024 | for (i = 0; i < RTL8152_MAX_TX; i++) { | |
1025 | buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node); | |
1026 | if (!buf) | |
1027 | goto err1; | |
1028 | ||
1029 | if (buf != tx_agg_align(buf)) { | |
1030 | kfree(buf); | |
8e1f51bd | 1031 | buf = kmalloc_node(rx_buf_sz + TX_ALIGN, GFP_KERNEL, |
1032 | node); | |
ebc2ec48 | 1033 | if (!buf) |
1034 | goto err1; | |
1035 | } | |
1036 | ||
1037 | urb = usb_alloc_urb(0, GFP_KERNEL); | |
1038 | if (!urb) { | |
1039 | kfree(buf); | |
1040 | goto err1; | |
1041 | } | |
1042 | ||
1043 | INIT_LIST_HEAD(&tp->tx_info[i].list); | |
1044 | tp->tx_info[i].context = tp; | |
1045 | tp->tx_info[i].urb = urb; | |
1046 | tp->tx_info[i].buffer = buf; | |
1047 | tp->tx_info[i].head = tx_agg_align(buf); | |
1048 | ||
1049 | list_add_tail(&tp->tx_info[i].list, &tp->tx_free); | |
1050 | } | |
1051 | ||
40a82917 | 1052 | tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL); |
1053 | if (!tp->intr_urb) | |
1054 | goto err1; | |
1055 | ||
1056 | tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL); | |
1057 | if (!tp->intr_buff) | |
1058 | goto err1; | |
1059 | ||
1060 | tp->intr_interval = (int)ep_intr->desc.bInterval; | |
1061 | usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3), | |
1062 | tp->intr_buff, INTBUFSIZE, intr_callback, | |
1063 | tp, tp->intr_interval); | |
1064 | ||
ebc2ec48 | 1065 | return 0; |
1066 | ||
1067 | err1: | |
1068 | free_all_mem(tp); | |
1069 | return -ENOMEM; | |
1070 | } | |
1071 | ||
0de98f6c | 1072 | static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp) |
1073 | { | |
1074 | struct tx_agg *agg = NULL; | |
1075 | unsigned long flags; | |
1076 | ||
1077 | spin_lock_irqsave(&tp->tx_lock, flags); | |
1078 | if (!list_empty(&tp->tx_free)) { | |
1079 | struct list_head *cursor; | |
1080 | ||
1081 | cursor = tp->tx_free.next; | |
1082 | list_del_init(cursor); | |
1083 | agg = list_entry(cursor, struct tx_agg, list); | |
1084 | } | |
1085 | spin_unlock_irqrestore(&tp->tx_lock, flags); | |
1086 | ||
1087 | return agg; | |
1088 | } | |
1089 | ||
5bd23881 | 1090 | static void |
1091 | r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, struct sk_buff *skb) | |
1092 | { | |
1093 | memset(desc, 0, sizeof(*desc)); | |
1094 | ||
1095 | desc->opts1 = cpu_to_le32((skb->len & TX_LEN_MASK) | TX_FS | TX_LS); | |
1096 | ||
1097 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
1098 | __be16 protocol; | |
1099 | u8 ip_protocol; | |
1100 | u32 opts2 = 0; | |
1101 | ||
1102 | if (skb->protocol == htons(ETH_P_8021Q)) | |
1103 | protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto; | |
1104 | else | |
1105 | protocol = skb->protocol; | |
1106 | ||
1107 | switch (protocol) { | |
1108 | case htons(ETH_P_IP): | |
1109 | opts2 |= IPV4_CS; | |
1110 | ip_protocol = ip_hdr(skb)->protocol; | |
1111 | break; | |
1112 | ||
1113 | case htons(ETH_P_IPV6): | |
1114 | opts2 |= IPV6_CS; | |
1115 | ip_protocol = ipv6_hdr(skb)->nexthdr; | |
1116 | break; | |
1117 | ||
1118 | default: | |
1119 | ip_protocol = IPPROTO_RAW; | |
1120 | break; | |
1121 | } | |
1122 | ||
1123 | if (ip_protocol == IPPROTO_TCP) { | |
1124 | opts2 |= TCP_CS; | |
1125 | opts2 |= (skb_transport_offset(skb) & 0x7fff) << 17; | |
1126 | } else if (ip_protocol == IPPROTO_UDP) { | |
1127 | opts2 |= UDP_CS; | |
1128 | } else { | |
1129 | WARN_ON_ONCE(1); | |
1130 | } | |
1131 | ||
1132 | desc->opts2 = cpu_to_le32(opts2); | |
1133 | } | |
1134 | } | |
1135 | ||
b1379d9a | 1136 | static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg) |
1137 | { | |
7937f9e5 | 1138 | int remain; |
b1379d9a | 1139 | u8 *tx_data; |
1140 | ||
1141 | tx_data = agg->head; | |
1142 | agg->skb_num = agg->skb_len = 0; | |
7937f9e5 | 1143 | remain = rx_buf_sz; |
b1379d9a | 1144 | |
7937f9e5 | 1145 | while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) { |
b1379d9a | 1146 | struct tx_desc *tx_desc; |
1147 | struct sk_buff *skb; | |
1148 | unsigned int len; | |
1149 | ||
1150 | skb = skb_dequeue(&tp->tx_queue); | |
1151 | if (!skb) | |
1152 | break; | |
1153 | ||
7937f9e5 | 1154 | remain -= sizeof(*tx_desc); |
b1379d9a | 1155 | len = skb->len; |
1156 | if (remain < len) { | |
1157 | skb_queue_head(&tp->tx_queue, skb); | |
1158 | break; | |
1159 | } | |
1160 | ||
7937f9e5 | 1161 | tx_data = tx_agg_align(tx_data); |
b1379d9a | 1162 | tx_desc = (struct tx_desc *)tx_data; |
1163 | tx_data += sizeof(*tx_desc); | |
1164 | ||
1165 | r8152_tx_csum(tp, tx_desc, skb); | |
1166 | memcpy(tx_data, skb->data, len); | |
1167 | agg->skb_num++; | |
1168 | agg->skb_len += len; | |
1169 | dev_kfree_skb_any(skb); | |
1170 | ||
7937f9e5 | 1171 | tx_data += len; |
1172 | remain = rx_buf_sz - (int)(tx_agg_align(tx_data) - agg->head); | |
b1379d9a | 1173 | } |
1174 | ||
dd1b119c | 1175 | netif_tx_lock(tp->netdev); |
1176 | ||
1177 | if (netif_queue_stopped(tp->netdev) && | |
1178 | skb_queue_len(&tp->tx_queue) < tp->tx_qlen) | |
1179 | netif_wake_queue(tp->netdev); | |
1180 | ||
1181 | netif_tx_unlock(tp->netdev); | |
1182 | ||
b1379d9a | 1183 | usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2), |
1184 | agg->head, (int)(tx_data - (u8 *)agg->head), | |
1185 | (usb_complete_t)write_bulk_callback, agg); | |
1186 | ||
1187 | return usb_submit_urb(agg->urb, GFP_ATOMIC); | |
1188 | } | |
1189 | ||
ebc2ec48 | 1190 | static void rx_bottom(struct r8152 *tp) |
1191 | { | |
a5a4f468 | 1192 | unsigned long flags; |
ebc2ec48 | 1193 | struct list_head *cursor, *next; |
ebc2ec48 | 1194 | |
a5a4f468 | 1195 | spin_lock_irqsave(&tp->rx_lock, flags); |
ebc2ec48 | 1196 | list_for_each_safe(cursor, next, &tp->rx_done) { |
43a4478d | 1197 | struct rx_desc *rx_desc; |
1198 | struct rx_agg *agg; | |
43a4478d | 1199 | int len_used = 0; |
1200 | struct urb *urb; | |
1201 | u8 *rx_data; | |
1202 | int ret; | |
1203 | ||
ebc2ec48 | 1204 | list_del_init(cursor); |
a5a4f468 | 1205 | spin_unlock_irqrestore(&tp->rx_lock, flags); |
ebc2ec48 | 1206 | |
1207 | agg = list_entry(cursor, struct rx_agg, list); | |
1208 | urb = agg->urb; | |
0de98f6c | 1209 | if (urb->actual_length < ETH_ZLEN) |
1210 | goto submit; | |
ebc2ec48 | 1211 | |
ebc2ec48 | 1212 | rx_desc = agg->head; |
1213 | rx_data = agg->head; | |
7937f9e5 | 1214 | len_used += sizeof(struct rx_desc); |
ebc2ec48 | 1215 | |
7937f9e5 | 1216 | while (urb->actual_length > len_used) { |
43a4478d | 1217 | struct net_device *netdev = tp->netdev; |
1218 | struct net_device_stats *stats; | |
7937f9e5 | 1219 | unsigned int pkt_len; |
43a4478d | 1220 | struct sk_buff *skb; |
1221 | ||
7937f9e5 | 1222 | pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; |
ebc2ec48 | 1223 | if (pkt_len < ETH_ZLEN) |
1224 | break; | |
1225 | ||
7937f9e5 | 1226 | len_used += pkt_len; |
1227 | if (urb->actual_length < len_used) | |
1228 | break; | |
1229 | ||
43a4478d | 1230 | stats = rtl8152_get_stats(netdev); |
1231 | ||
8e1f51bd | 1232 | pkt_len -= CRC_SIZE; |
ebc2ec48 | 1233 | rx_data += sizeof(struct rx_desc); |
1234 | ||
1235 | skb = netdev_alloc_skb_ip_align(netdev, pkt_len); | |
1236 | if (!skb) { | |
1237 | stats->rx_dropped++; | |
1238 | break; | |
1239 | } | |
1240 | memcpy(skb->data, rx_data, pkt_len); | |
1241 | skb_put(skb, pkt_len); | |
1242 | skb->protocol = eth_type_trans(skb, netdev); | |
1243 | netif_rx(skb); | |
1244 | stats->rx_packets++; | |
1245 | stats->rx_bytes += pkt_len; | |
1246 | ||
8e1f51bd | 1247 | rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE); |
ebc2ec48 | 1248 | rx_desc = (struct rx_desc *)rx_data; |
ebc2ec48 | 1249 | len_used = (int)(rx_data - (u8 *)agg->head); |
7937f9e5 | 1250 | len_used += sizeof(struct rx_desc); |
ebc2ec48 | 1251 | } |
1252 | ||
0de98f6c | 1253 | submit: |
ebc2ec48 | 1254 | ret = r8152_submit_rx(tp, agg, GFP_ATOMIC); |
a5a4f468 | 1255 | spin_lock_irqsave(&tp->rx_lock, flags); |
ebc2ec48 | 1256 | if (ret && ret != -ENODEV) { |
1257 | list_add_tail(&agg->list, next); | |
1258 | tasklet_schedule(&tp->tl); | |
1259 | } | |
1260 | } | |
a5a4f468 | 1261 | spin_unlock_irqrestore(&tp->rx_lock, flags); |
ebc2ec48 | 1262 | } |
1263 | ||
1264 | static void tx_bottom(struct r8152 *tp) | |
1265 | { | |
ebc2ec48 | 1266 | int res; |
1267 | ||
b1379d9a | 1268 | do { |
1269 | struct tx_agg *agg; | |
ebc2ec48 | 1270 | |
b1379d9a | 1271 | if (skb_queue_empty(&tp->tx_queue)) |
ebc2ec48 | 1272 | break; |
1273 | ||
b1379d9a | 1274 | agg = r8152_get_tx_agg(tp); |
1275 | if (!agg) | |
ebc2ec48 | 1276 | break; |
ebc2ec48 | 1277 | |
b1379d9a | 1278 | res = r8152_tx_agg_fill(tp, agg); |
1279 | if (res) { | |
1280 | struct net_device_stats *stats; | |
1281 | struct net_device *netdev; | |
1282 | unsigned long flags; | |
ebc2ec48 | 1283 | |
b1379d9a | 1284 | netdev = tp->netdev; |
1285 | stats = rtl8152_get_stats(netdev); | |
ebc2ec48 | 1286 | |
b1379d9a | 1287 | if (res == -ENODEV) { |
1288 | netif_device_detach(netdev); | |
1289 | } else { | |
1290 | netif_warn(tp, tx_err, netdev, | |
1291 | "failed tx_urb %d\n", res); | |
1292 | stats->tx_dropped += agg->skb_num; | |
1293 | spin_lock_irqsave(&tp->tx_lock, flags); | |
1294 | list_add_tail(&agg->list, &tp->tx_free); | |
1295 | spin_unlock_irqrestore(&tp->tx_lock, flags); | |
1296 | } | |
ebc2ec48 | 1297 | } |
b1379d9a | 1298 | } while (res == 0); |
ebc2ec48 | 1299 | } |
1300 | ||
1301 | static void bottom_half(unsigned long data) | |
ac718b69 | 1302 | { |
1303 | struct r8152 *tp; | |
ac718b69 | 1304 | |
ebc2ec48 | 1305 | tp = (struct r8152 *)data; |
1306 | ||
1307 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
1308 | return; | |
1309 | ||
1310 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
ac718b69 | 1311 | return; |
ebc2ec48 | 1312 | |
7559fb2f | 1313 | /* When link down, the driver would cancel all bulks. */ |
1314 | /* This avoid the re-submitting bulk */ | |
ebc2ec48 | 1315 | if (!netif_carrier_ok(tp->netdev)) |
ac718b69 | 1316 | return; |
ebc2ec48 | 1317 | |
1318 | rx_bottom(tp); | |
1319 | tx_bottom(tp); | |
1320 | } | |
1321 | ||
1322 | static | |
1323 | int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags) | |
1324 | { | |
1325 | usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1), | |
1326 | agg->head, rx_buf_sz, | |
1327 | (usb_complete_t)read_bulk_callback, agg); | |
1328 | ||
1329 | return usb_submit_urb(agg->urb, mem_flags); | |
ac718b69 | 1330 | } |
1331 | ||
1332 | static void rtl8152_tx_timeout(struct net_device *netdev) | |
1333 | { | |
1334 | struct r8152 *tp = netdev_priv(netdev); | |
ebc2ec48 | 1335 | int i; |
1336 | ||
ac718b69 | 1337 | netif_warn(tp, tx_err, netdev, "Tx timeout.\n"); |
ebc2ec48 | 1338 | for (i = 0; i < RTL8152_MAX_TX; i++) |
1339 | usb_unlink_urb(tp->tx_info[i].urb); | |
ac718b69 | 1340 | } |
1341 | ||
1342 | static void rtl8152_set_rx_mode(struct net_device *netdev) | |
1343 | { | |
1344 | struct r8152 *tp = netdev_priv(netdev); | |
1345 | ||
40a82917 | 1346 | if (tp->speed & LINK_STATUS) { |
ac718b69 | 1347 | set_bit(RTL8152_SET_RX_MODE, &tp->flags); |
40a82917 | 1348 | schedule_delayed_work(&tp->schedule, 0); |
1349 | } | |
ac718b69 | 1350 | } |
1351 | ||
1352 | static void _rtl8152_set_rx_mode(struct net_device *netdev) | |
1353 | { | |
1354 | struct r8152 *tp = netdev_priv(netdev); | |
31787f53 | 1355 | u32 mc_filter[2]; /* Multicast hash filter */ |
1356 | __le32 tmp[2]; | |
ac718b69 | 1357 | u32 ocp_data; |
1358 | ||
ac718b69 | 1359 | clear_bit(RTL8152_SET_RX_MODE, &tp->flags); |
1360 | netif_stop_queue(netdev); | |
1361 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
1362 | ocp_data &= ~RCR_ACPT_ALL; | |
1363 | ocp_data |= RCR_AB | RCR_APM; | |
1364 | ||
1365 | if (netdev->flags & IFF_PROMISC) { | |
1366 | /* Unconditionally log net taps. */ | |
1367 | netif_notice(tp, link, netdev, "Promiscuous mode enabled\n"); | |
1368 | ocp_data |= RCR_AM | RCR_AAP; | |
1369 | mc_filter[1] = mc_filter[0] = 0xffffffff; | |
1370 | } else if ((netdev_mc_count(netdev) > multicast_filter_limit) || | |
1371 | (netdev->flags & IFF_ALLMULTI)) { | |
1372 | /* Too many to filter perfectly -- accept all multicasts. */ | |
1373 | ocp_data |= RCR_AM; | |
1374 | mc_filter[1] = mc_filter[0] = 0xffffffff; | |
1375 | } else { | |
1376 | struct netdev_hw_addr *ha; | |
1377 | ||
1378 | mc_filter[1] = mc_filter[0] = 0; | |
1379 | netdev_for_each_mc_addr(ha, netdev) { | |
1380 | int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; | |
1381 | mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); | |
1382 | ocp_data |= RCR_AM; | |
1383 | } | |
1384 | } | |
1385 | ||
31787f53 | 1386 | tmp[0] = __cpu_to_le32(swab32(mc_filter[1])); |
1387 | tmp[1] = __cpu_to_le32(swab32(mc_filter[0])); | |
ac718b69 | 1388 | |
31787f53 | 1389 | pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp); |
ac718b69 | 1390 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); |
1391 | netif_wake_queue(netdev); | |
ac718b69 | 1392 | } |
1393 | ||
1394 | static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb, | |
1395 | struct net_device *netdev) | |
1396 | { | |
1397 | struct r8152 *tp = netdev_priv(netdev); | |
ac718b69 | 1398 | |
ebc2ec48 | 1399 | skb_tx_timestamp(skb); |
ac718b69 | 1400 | |
61598788 | 1401 | skb_queue_tail(&tp->tx_queue, skb); |
ebc2ec48 | 1402 | |
dd1b119c | 1403 | if (list_empty(&tp->tx_free) && |
1404 | skb_queue_len(&tp->tx_queue) > tp->tx_qlen) | |
1405 | netif_stop_queue(netdev); | |
1406 | ||
61598788 | 1407 | if (!list_empty(&tp->tx_free)) |
1408 | tasklet_schedule(&tp->tl); | |
ac718b69 | 1409 | |
1410 | return NETDEV_TX_OK; | |
1411 | } | |
1412 | ||
1413 | static void r8152b_reset_packet_filter(struct r8152 *tp) | |
1414 | { | |
1415 | u32 ocp_data; | |
1416 | ||
1417 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); | |
1418 | ocp_data &= ~FMC_FCR_MCU_EN; | |
1419 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); | |
1420 | ocp_data |= FMC_FCR_MCU_EN; | |
1421 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); | |
1422 | } | |
1423 | ||
1424 | static void rtl8152_nic_reset(struct r8152 *tp) | |
1425 | { | |
1426 | int i; | |
1427 | ||
1428 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST); | |
1429 | ||
1430 | for (i = 0; i < 1000; i++) { | |
1431 | if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST)) | |
1432 | break; | |
1433 | udelay(100); | |
1434 | } | |
1435 | } | |
1436 | ||
dd1b119c | 1437 | static void set_tx_qlen(struct r8152 *tp) |
1438 | { | |
1439 | struct net_device *netdev = tp->netdev; | |
1440 | ||
1441 | tp->tx_qlen = rx_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN + | |
1442 | sizeof(struct tx_desc)); | |
1443 | } | |
1444 | ||
ac718b69 | 1445 | static inline u8 rtl8152_get_speed(struct r8152 *tp) |
1446 | { | |
1447 | return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); | |
1448 | } | |
1449 | ||
1450 | static int rtl8152_enable(struct r8152 *tp) | |
1451 | { | |
ebc2ec48 | 1452 | u32 ocp_data; |
1453 | int i, ret; | |
ac718b69 | 1454 | u8 speed; |
1455 | ||
dd1b119c | 1456 | set_tx_qlen(tp); |
ac718b69 | 1457 | speed = rtl8152_get_speed(tp); |
ebc2ec48 | 1458 | if (speed & _10bps) { |
ac718b69 | 1459 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); |
ebc2ec48 | 1460 | ocp_data |= EEEP_CR_EEEP_TX; |
ac718b69 | 1461 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); |
1462 | } else { | |
1463 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); | |
ebc2ec48 | 1464 | ocp_data &= ~EEEP_CR_EEEP_TX; |
ac718b69 | 1465 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); |
1466 | } | |
1467 | ||
1468 | r8152b_reset_packet_filter(tp); | |
1469 | ||
1470 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); | |
1471 | ocp_data |= CR_RE | CR_TE; | |
1472 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); | |
1473 | ||
1474 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); | |
1475 | ocp_data &= ~RXDY_GATED_EN; | |
1476 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); | |
1477 | ||
ebc2ec48 | 1478 | INIT_LIST_HEAD(&tp->rx_done); |
1479 | ret = 0; | |
1480 | for (i = 0; i < RTL8152_MAX_RX; i++) { | |
1481 | INIT_LIST_HEAD(&tp->rx_info[i].list); | |
1482 | ret |= r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL); | |
1483 | } | |
ac718b69 | 1484 | |
ebc2ec48 | 1485 | return ret; |
ac718b69 | 1486 | } |
1487 | ||
1488 | static void rtl8152_disable(struct r8152 *tp) | |
1489 | { | |
ebc2ec48 | 1490 | struct net_device_stats *stats = rtl8152_get_stats(tp->netdev); |
1491 | struct sk_buff *skb; | |
1492 | u32 ocp_data; | |
1493 | int i; | |
ac718b69 | 1494 | |
1495 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
1496 | ocp_data &= ~RCR_ACPT_ALL; | |
1497 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
1498 | ||
ebc2ec48 | 1499 | while ((skb = skb_dequeue(&tp->tx_queue))) { |
1500 | dev_kfree_skb(skb); | |
1501 | stats->tx_dropped++; | |
1502 | } | |
1503 | ||
1504 | for (i = 0; i < RTL8152_MAX_TX; i++) | |
1505 | usb_kill_urb(tp->tx_info[i].urb); | |
ac718b69 | 1506 | |
1507 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); | |
1508 | ocp_data |= RXDY_GATED_EN; | |
1509 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); | |
1510 | ||
1511 | for (i = 0; i < 1000; i++) { | |
1512 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
1513 | if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY) | |
1514 | break; | |
1515 | mdelay(1); | |
1516 | } | |
1517 | ||
1518 | for (i = 0; i < 1000; i++) { | |
1519 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY) | |
1520 | break; | |
1521 | mdelay(1); | |
1522 | } | |
1523 | ||
ebc2ec48 | 1524 | for (i = 0; i < RTL8152_MAX_RX; i++) |
1525 | usb_kill_urb(tp->rx_info[i].urb); | |
ac718b69 | 1526 | |
1527 | rtl8152_nic_reset(tp); | |
1528 | } | |
1529 | ||
1530 | static void r8152b_exit_oob(struct r8152 *tp) | |
1531 | { | |
1532 | u32 ocp_data; | |
1533 | int i; | |
1534 | ||
1535 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
1536 | ocp_data &= ~RCR_ACPT_ALL; | |
1537 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
1538 | ||
1539 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); | |
1540 | ocp_data |= RXDY_GATED_EN; | |
1541 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); | |
1542 | ||
1543 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
1544 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); | |
1545 | ||
1546 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
1547 | ocp_data &= ~NOW_IS_OOB; | |
1548 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
1549 | ||
1550 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
1551 | ocp_data &= ~MCU_BORW_EN; | |
1552 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
1553 | ||
1554 | for (i = 0; i < 1000; i++) { | |
1555 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
1556 | if (ocp_data & LINK_LIST_READY) | |
1557 | break; | |
1558 | mdelay(1); | |
1559 | } | |
1560 | ||
1561 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
1562 | ocp_data |= RE_INIT_LL; | |
1563 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
1564 | ||
1565 | for (i = 0; i < 1000; i++) { | |
1566 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
1567 | if (ocp_data & LINK_LIST_READY) | |
1568 | break; | |
1569 | mdelay(1); | |
1570 | } | |
1571 | ||
1572 | rtl8152_nic_reset(tp); | |
1573 | ||
1574 | /* rx share fifo credit full threshold */ | |
1575 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); | |
1576 | ||
1577 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_DEV_STAT); | |
1578 | ocp_data &= STAT_SPEED_MASK; | |
1579 | if (ocp_data == STAT_SPEED_FULL) { | |
1580 | /* rx share fifo credit near full threshold */ | |
1581 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, | |
1582 | RXFIFO_THR2_FULL); | |
1583 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, | |
1584 | RXFIFO_THR3_FULL); | |
1585 | } else { | |
1586 | /* rx share fifo credit near full threshold */ | |
1587 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, | |
1588 | RXFIFO_THR2_HIGH); | |
1589 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, | |
1590 | RXFIFO_THR3_HIGH); | |
1591 | } | |
1592 | ||
1593 | /* TX share fifo free credit full threshold */ | |
1594 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL); | |
1595 | ||
1596 | ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD); | |
8e1f51bd | 1597 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH); |
ac718b69 | 1598 | ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA, |
1599 | TEST_MODE_DISABLE | TX_SIZE_ADJUST1); | |
1600 | ||
1601 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); | |
1602 | ocp_data &= ~CPCR_RX_VLAN; | |
1603 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); | |
1604 | ||
1605 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); | |
1606 | ||
1607 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); | |
1608 | ocp_data |= TCR0_AUTO_FIFO; | |
1609 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); | |
1610 | } | |
1611 | ||
1612 | static void r8152b_enter_oob(struct r8152 *tp) | |
1613 | { | |
1614 | u32 ocp_data; | |
1615 | int i; | |
1616 | ||
1617 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
1618 | ocp_data &= ~NOW_IS_OOB; | |
1619 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
1620 | ||
1621 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); | |
1622 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); | |
1623 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB); | |
1624 | ||
1625 | rtl8152_disable(tp); | |
1626 | ||
1627 | for (i = 0; i < 1000; i++) { | |
1628 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
1629 | if (ocp_data & LINK_LIST_READY) | |
1630 | break; | |
1631 | mdelay(1); | |
1632 | } | |
1633 | ||
1634 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
1635 | ocp_data |= RE_INIT_LL; | |
1636 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
1637 | ||
1638 | for (i = 0; i < 1000; i++) { | |
1639 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
1640 | if (ocp_data & LINK_LIST_READY) | |
1641 | break; | |
1642 | mdelay(1); | |
1643 | } | |
1644 | ||
1645 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); | |
1646 | ||
1647 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); | |
1648 | ocp_data |= MAGIC_EN; | |
1649 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data); | |
1650 | ||
1651 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); | |
1652 | ocp_data |= CPCR_RX_VLAN; | |
1653 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); | |
1654 | ||
1655 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); | |
1656 | ocp_data |= ALDPS_PROXY_MODE; | |
1657 | ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); | |
1658 | ||
1659 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
1660 | ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; | |
1661 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
1662 | ||
1663 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5, LAN_WAKE_EN); | |
1664 | ||
1665 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); | |
1666 | ocp_data &= ~RXDY_GATED_EN; | |
1667 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); | |
1668 | ||
1669 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
1670 | ocp_data |= RCR_APM | RCR_AM | RCR_AB; | |
1671 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
1672 | } | |
1673 | ||
1674 | static void r8152b_disable_aldps(struct r8152 *tp) | |
1675 | { | |
1676 | ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE); | |
1677 | msleep(20); | |
1678 | } | |
1679 | ||
1680 | static inline void r8152b_enable_aldps(struct r8152 *tp) | |
1681 | { | |
1682 | ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS | | |
1683 | LINKENA | DIS_SDSAVE); | |
1684 | } | |
1685 | ||
1686 | static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex) | |
1687 | { | |
1688 | u16 bmcr, anar; | |
1689 | int ret = 0; | |
1690 | ||
1691 | cancel_delayed_work_sync(&tp->schedule); | |
1692 | anar = r8152_mdio_read(tp, MII_ADVERTISE); | |
1693 | anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | | |
1694 | ADVERTISE_100HALF | ADVERTISE_100FULL); | |
1695 | ||
1696 | if (autoneg == AUTONEG_DISABLE) { | |
1697 | if (speed == SPEED_10) { | |
1698 | bmcr = 0; | |
1699 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
1700 | } else if (speed == SPEED_100) { | |
1701 | bmcr = BMCR_SPEED100; | |
1702 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; | |
1703 | } else { | |
1704 | ret = -EINVAL; | |
1705 | goto out; | |
1706 | } | |
1707 | ||
1708 | if (duplex == DUPLEX_FULL) | |
1709 | bmcr |= BMCR_FULLDPLX; | |
1710 | } else { | |
1711 | if (speed == SPEED_10) { | |
1712 | if (duplex == DUPLEX_FULL) | |
1713 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
1714 | else | |
1715 | anar |= ADVERTISE_10HALF; | |
1716 | } else if (speed == SPEED_100) { | |
1717 | if (duplex == DUPLEX_FULL) { | |
1718 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
1719 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; | |
1720 | } else { | |
1721 | anar |= ADVERTISE_10HALF; | |
1722 | anar |= ADVERTISE_100HALF; | |
1723 | } | |
1724 | } else { | |
1725 | ret = -EINVAL; | |
1726 | goto out; | |
1727 | } | |
1728 | ||
1729 | bmcr = BMCR_ANENABLE | BMCR_ANRESTART; | |
1730 | } | |
1731 | ||
1732 | r8152_mdio_write(tp, MII_ADVERTISE, anar); | |
1733 | r8152_mdio_write(tp, MII_BMCR, bmcr); | |
1734 | ||
1735 | out: | |
ac718b69 | 1736 | |
1737 | return ret; | |
1738 | } | |
1739 | ||
1740 | static void rtl8152_down(struct r8152 *tp) | |
1741 | { | |
1742 | u32 ocp_data; | |
1743 | ||
1744 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); | |
1745 | ocp_data &= ~POWER_CUT; | |
1746 | ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); | |
1747 | ||
1748 | r8152b_disable_aldps(tp); | |
1749 | r8152b_enter_oob(tp); | |
1750 | r8152b_enable_aldps(tp); | |
1751 | } | |
1752 | ||
1753 | static void set_carrier(struct r8152 *tp) | |
1754 | { | |
1755 | struct net_device *netdev = tp->netdev; | |
1756 | u8 speed; | |
1757 | ||
40a82917 | 1758 | clear_bit(RTL8152_LINK_CHG, &tp->flags); |
ac718b69 | 1759 | speed = rtl8152_get_speed(tp); |
1760 | ||
1761 | if (speed & LINK_STATUS) { | |
1762 | if (!(tp->speed & LINK_STATUS)) { | |
c81229c9 | 1763 | tp->rtl_ops.enable(tp); |
ac718b69 | 1764 | set_bit(RTL8152_SET_RX_MODE, &tp->flags); |
1765 | netif_carrier_on(netdev); | |
1766 | } | |
1767 | } else { | |
1768 | if (tp->speed & LINK_STATUS) { | |
1769 | netif_carrier_off(netdev); | |
ebc2ec48 | 1770 | tasklet_disable(&tp->tl); |
c81229c9 | 1771 | tp->rtl_ops.disable(tp); |
ebc2ec48 | 1772 | tasklet_enable(&tp->tl); |
ac718b69 | 1773 | } |
1774 | } | |
1775 | tp->speed = speed; | |
1776 | } | |
1777 | ||
1778 | static void rtl_work_func_t(struct work_struct *work) | |
1779 | { | |
1780 | struct r8152 *tp = container_of(work, struct r8152, schedule.work); | |
1781 | ||
1782 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
1783 | goto out1; | |
1784 | ||
1785 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
1786 | goto out1; | |
1787 | ||
40a82917 | 1788 | if (test_bit(RTL8152_LINK_CHG, &tp->flags)) |
1789 | set_carrier(tp); | |
ac718b69 | 1790 | |
1791 | if (test_bit(RTL8152_SET_RX_MODE, &tp->flags)) | |
1792 | _rtl8152_set_rx_mode(tp->netdev); | |
1793 | ||
ac718b69 | 1794 | out1: |
1795 | return; | |
1796 | } | |
1797 | ||
1798 | static int rtl8152_open(struct net_device *netdev) | |
1799 | { | |
1800 | struct r8152 *tp = netdev_priv(netdev); | |
1801 | int res = 0; | |
1802 | ||
40a82917 | 1803 | res = usb_submit_urb(tp->intr_urb, GFP_KERNEL); |
1804 | if (res) { | |
1805 | if (res == -ENODEV) | |
1806 | netif_device_detach(tp->netdev); | |
1807 | netif_warn(tp, ifup, netdev, | |
1808 | "intr_urb submit failed: %d\n", res); | |
1809 | return res; | |
ac718b69 | 1810 | } |
1811 | ||
1812 | rtl8152_set_speed(tp, AUTONEG_ENABLE, SPEED_100, DUPLEX_FULL); | |
40a82917 | 1813 | tp->speed = 0; |
1814 | netif_carrier_off(netdev); | |
ac718b69 | 1815 | netif_start_queue(netdev); |
1816 | set_bit(WORK_ENABLE, &tp->flags); | |
ac718b69 | 1817 | |
1818 | return res; | |
1819 | } | |
1820 | ||
1821 | static int rtl8152_close(struct net_device *netdev) | |
1822 | { | |
1823 | struct r8152 *tp = netdev_priv(netdev); | |
1824 | int res = 0; | |
1825 | ||
40a82917 | 1826 | usb_kill_urb(tp->intr_urb); |
ac718b69 | 1827 | clear_bit(WORK_ENABLE, &tp->flags); |
1828 | cancel_delayed_work_sync(&tp->schedule); | |
1829 | netif_stop_queue(netdev); | |
ebc2ec48 | 1830 | tasklet_disable(&tp->tl); |
c81229c9 | 1831 | tp->rtl_ops.disable(tp); |
ebc2ec48 | 1832 | tasklet_enable(&tp->tl); |
ac718b69 | 1833 | |
1834 | return res; | |
1835 | } | |
1836 | ||
1837 | static void rtl_clear_bp(struct r8152 *tp) | |
1838 | { | |
1839 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_0, 0); | |
1840 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_2, 0); | |
1841 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_4, 0); | |
1842 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_6, 0); | |
1843 | ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_0, 0); | |
1844 | ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_2, 0); | |
1845 | ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_4, 0); | |
1846 | ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_6, 0); | |
1847 | mdelay(3); | |
1848 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_BA, 0); | |
1849 | ocp_write_word(tp, MCU_TYPE_USB, USB_BP_BA, 0); | |
1850 | } | |
1851 | ||
1852 | static void r8152b_enable_eee(struct r8152 *tp) | |
1853 | { | |
1854 | u32 ocp_data; | |
1855 | ||
1856 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); | |
1857 | ocp_data |= EEE_RX_EN | EEE_TX_EN; | |
1858 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); | |
1859 | ocp_reg_write(tp, OCP_EEE_CONFIG1, RG_TXLPI_MSK_HFDUP | RG_MATCLR_EN | | |
1860 | EEE_10_CAP | EEE_NWAY_EN | | |
1861 | TX_QUIET_EN | RX_QUIET_EN | | |
1862 | SDRISETIME | RG_RXLPI_MSK_HFDUP | | |
1863 | SDFALLTIME); | |
1864 | ocp_reg_write(tp, OCP_EEE_CONFIG2, RG_LPIHYS_NUM | RG_DACQUIET_EN | | |
1865 | RG_LDVQUIET_EN | RG_CKRSEL | | |
1866 | RG_EEEPRG_EN); | |
1867 | ocp_reg_write(tp, OCP_EEE_CONFIG3, FST_SNR_EYE_R | RG_LFS_SEL | MSK_PH); | |
1868 | ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | DEVICE_ADDR); | |
1869 | ocp_reg_write(tp, OCP_EEE_DATA, EEE_ADDR); | |
1870 | ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | DEVICE_ADDR); | |
1871 | ocp_reg_write(tp, OCP_EEE_DATA, EEE_DATA); | |
1872 | ocp_reg_write(tp, OCP_EEE_AR, 0x0000); | |
1873 | } | |
1874 | ||
1875 | static void r8152b_enable_fc(struct r8152 *tp) | |
1876 | { | |
1877 | u16 anar; | |
1878 | ||
1879 | anar = r8152_mdio_read(tp, MII_ADVERTISE); | |
1880 | anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; | |
1881 | r8152_mdio_write(tp, MII_ADVERTISE, anar); | |
1882 | } | |
1883 | ||
1884 | static void r8152b_hw_phy_cfg(struct r8152 *tp) | |
1885 | { | |
1886 | r8152_mdio_write(tp, MII_BMCR, BMCR_ANENABLE); | |
1887 | r8152b_disable_aldps(tp); | |
1888 | } | |
1889 | ||
1890 | static void r8152b_init(struct r8152 *tp) | |
1891 | { | |
ebc2ec48 | 1892 | u32 ocp_data; |
1893 | int i; | |
ac718b69 | 1894 | |
1895 | rtl_clear_bp(tp); | |
1896 | ||
1897 | if (tp->version == RTL_VER_01) { | |
1898 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); | |
1899 | ocp_data &= ~LED_MODE_MASK; | |
1900 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); | |
1901 | } | |
1902 | ||
1903 | r8152b_hw_phy_cfg(tp); | |
1904 | ||
1905 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); | |
1906 | ocp_data &= ~POWER_CUT; | |
1907 | ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); | |
1908 | ||
1909 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); | |
8e1f51bd | 1910 | ocp_data &= ~RESUME_INDICATE; |
ac718b69 | 1911 | ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); |
1912 | ||
1913 | r8152b_exit_oob(tp); | |
1914 | ||
1915 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); | |
1916 | ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH; | |
1917 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); | |
1918 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL); | |
1919 | ocp_data &= ~MCU_CLK_RATIO_MASK; | |
1920 | ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN; | |
1921 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data); | |
1922 | ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK | | |
1923 | SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK; | |
1924 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data); | |
1925 | ||
1926 | r8152b_enable_eee(tp); | |
1927 | r8152b_enable_aldps(tp); | |
1928 | r8152b_enable_fc(tp); | |
1929 | ||
1930 | r8152_mdio_write(tp, MII_BMCR, BMCR_RESET | BMCR_ANENABLE | | |
1931 | BMCR_ANRESTART); | |
1932 | for (i = 0; i < 100; i++) { | |
1933 | udelay(100); | |
1934 | if (!(r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET)) | |
1935 | break; | |
1936 | } | |
1937 | ||
ebc2ec48 | 1938 | /* enable rx aggregation */ |
ac718b69 | 1939 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); |
ebc2ec48 | 1940 | ocp_data &= ~RX_AGG_DISABLE; |
ac718b69 | 1941 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); |
1942 | } | |
1943 | ||
1944 | static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message) | |
1945 | { | |
1946 | struct r8152 *tp = usb_get_intfdata(intf); | |
1947 | ||
1948 | netif_device_detach(tp->netdev); | |
1949 | ||
1950 | if (netif_running(tp->netdev)) { | |
1951 | clear_bit(WORK_ENABLE, &tp->flags); | |
40a82917 | 1952 | usb_kill_urb(tp->intr_urb); |
ac718b69 | 1953 | cancel_delayed_work_sync(&tp->schedule); |
ebc2ec48 | 1954 | tasklet_disable(&tp->tl); |
ac718b69 | 1955 | } |
1956 | ||
c81229c9 | 1957 | tp->rtl_ops.down(tp); |
ac718b69 | 1958 | |
1959 | return 0; | |
1960 | } | |
1961 | ||
1962 | static int rtl8152_resume(struct usb_interface *intf) | |
1963 | { | |
1964 | struct r8152 *tp = usb_get_intfdata(intf); | |
1965 | ||
c81229c9 | 1966 | tp->rtl_ops.init(tp); |
ac718b69 | 1967 | netif_device_attach(tp->netdev); |
1968 | if (netif_running(tp->netdev)) { | |
40a82917 | 1969 | rtl8152_set_speed(tp, AUTONEG_ENABLE, SPEED_100, DUPLEX_FULL); |
1970 | tp->speed = 0; | |
1971 | netif_carrier_off(tp->netdev); | |
ac718b69 | 1972 | set_bit(WORK_ENABLE, &tp->flags); |
40a82917 | 1973 | usb_submit_urb(tp->intr_urb, GFP_KERNEL); |
ebc2ec48 | 1974 | tasklet_enable(&tp->tl); |
ac718b69 | 1975 | } |
1976 | ||
1977 | return 0; | |
1978 | } | |
1979 | ||
1980 | static void rtl8152_get_drvinfo(struct net_device *netdev, | |
1981 | struct ethtool_drvinfo *info) | |
1982 | { | |
1983 | struct r8152 *tp = netdev_priv(netdev); | |
1984 | ||
1985 | strncpy(info->driver, MODULENAME, ETHTOOL_BUSINFO_LEN); | |
1986 | strncpy(info->version, DRIVER_VERSION, ETHTOOL_BUSINFO_LEN); | |
1987 | usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info)); | |
1988 | } | |
1989 | ||
1990 | static | |
1991 | int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd) | |
1992 | { | |
1993 | struct r8152 *tp = netdev_priv(netdev); | |
1994 | ||
1995 | if (!tp->mii.mdio_read) | |
1996 | return -EOPNOTSUPP; | |
1997 | ||
1998 | return mii_ethtool_gset(&tp->mii, cmd); | |
1999 | } | |
2000 | ||
2001 | static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
2002 | { | |
2003 | struct r8152 *tp = netdev_priv(dev); | |
2004 | ||
2005 | return rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex); | |
2006 | } | |
2007 | ||
2008 | static struct ethtool_ops ops = { | |
2009 | .get_drvinfo = rtl8152_get_drvinfo, | |
2010 | .get_settings = rtl8152_get_settings, | |
2011 | .set_settings = rtl8152_set_settings, | |
2012 | .get_link = ethtool_op_get_link, | |
2013 | }; | |
2014 | ||
2015 | static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) | |
2016 | { | |
2017 | struct r8152 *tp = netdev_priv(netdev); | |
2018 | struct mii_ioctl_data *data = if_mii(rq); | |
2019 | int res = 0; | |
2020 | ||
2021 | switch (cmd) { | |
2022 | case SIOCGMIIPHY: | |
2023 | data->phy_id = R8152_PHY_ID; /* Internal PHY */ | |
2024 | break; | |
2025 | ||
2026 | case SIOCGMIIREG: | |
2027 | data->val_out = r8152_mdio_read(tp, data->reg_num); | |
2028 | break; | |
2029 | ||
2030 | case SIOCSMIIREG: | |
2031 | if (!capable(CAP_NET_ADMIN)) { | |
2032 | res = -EPERM; | |
2033 | break; | |
2034 | } | |
2035 | r8152_mdio_write(tp, data->reg_num, data->val_in); | |
2036 | break; | |
2037 | ||
2038 | default: | |
2039 | res = -EOPNOTSUPP; | |
2040 | } | |
2041 | ||
2042 | return res; | |
2043 | } | |
2044 | ||
2045 | static const struct net_device_ops rtl8152_netdev_ops = { | |
2046 | .ndo_open = rtl8152_open, | |
2047 | .ndo_stop = rtl8152_close, | |
2048 | .ndo_do_ioctl = rtl8152_ioctl, | |
2049 | .ndo_start_xmit = rtl8152_start_xmit, | |
2050 | .ndo_tx_timeout = rtl8152_tx_timeout, | |
2051 | .ndo_set_rx_mode = rtl8152_set_rx_mode, | |
2052 | .ndo_set_mac_address = rtl8152_set_mac_address, | |
2053 | ||
2054 | .ndo_change_mtu = eth_change_mtu, | |
2055 | .ndo_validate_addr = eth_validate_addr, | |
2056 | }; | |
2057 | ||
2058 | static void r8152b_get_version(struct r8152 *tp) | |
2059 | { | |
2060 | u32 ocp_data; | |
2061 | u16 version; | |
2062 | ||
2063 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1); | |
2064 | version = (u16)(ocp_data & VERSION_MASK); | |
2065 | ||
2066 | switch (version) { | |
2067 | case 0x4c00: | |
2068 | tp->version = RTL_VER_01; | |
2069 | break; | |
2070 | case 0x4c10: | |
2071 | tp->version = RTL_VER_02; | |
2072 | break; | |
2073 | default: | |
2074 | netif_info(tp, probe, tp->netdev, | |
2075 | "Unknown version 0x%04x\n", version); | |
2076 | break; | |
2077 | } | |
2078 | } | |
2079 | ||
e3fe0b1a | 2080 | static void rtl8152_unload(struct r8152 *tp) |
2081 | { | |
2082 | u32 ocp_data; | |
2083 | ||
2084 | if (tp->version != RTL_VER_01) { | |
2085 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); | |
2086 | ocp_data |= POWER_CUT; | |
2087 | ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); | |
2088 | } | |
2089 | ||
2090 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); | |
8e1f51bd | 2091 | ocp_data &= ~RESUME_INDICATE; |
e3fe0b1a | 2092 | ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); |
2093 | } | |
2094 | ||
c81229c9 | 2095 | static bool rtl_ops_init(struct r8152 *tp, const struct usb_device_id *id) |
2096 | { | |
2097 | struct rtl_ops *ops = &tp->rtl_ops; | |
2098 | bool ret = true; | |
2099 | ||
2100 | switch (id->idVendor) { | |
2101 | case VENDOR_ID_REALTEK: | |
2102 | switch (id->idProduct) { | |
2103 | case PRODUCT_ID_RTL8152: | |
2104 | ops->init = r8152b_init; | |
2105 | ops->enable = rtl8152_enable; | |
2106 | ops->disable = rtl8152_disable; | |
2107 | ops->down = rtl8152_down; | |
2108 | ops->unload = rtl8152_unload; | |
2109 | break; | |
2110 | default: | |
2111 | ret = false; | |
2112 | break; | |
2113 | } | |
2114 | break; | |
2115 | ||
2116 | default: | |
2117 | ret = false; | |
2118 | break; | |
2119 | } | |
2120 | ||
2121 | return ret; | |
2122 | } | |
2123 | ||
ac718b69 | 2124 | static int rtl8152_probe(struct usb_interface *intf, |
2125 | const struct usb_device_id *id) | |
2126 | { | |
2127 | struct usb_device *udev = interface_to_usbdev(intf); | |
2128 | struct r8152 *tp; | |
2129 | struct net_device *netdev; | |
ebc2ec48 | 2130 | int ret; |
ac718b69 | 2131 | |
2132 | if (udev->actconfig->desc.bConfigurationValue != 1) { | |
2133 | usb_driver_set_configuration(udev, 1); | |
2134 | return -ENODEV; | |
2135 | } | |
2136 | ||
2137 | netdev = alloc_etherdev(sizeof(struct r8152)); | |
2138 | if (!netdev) { | |
2139 | dev_err(&intf->dev, "Out of memory"); | |
2140 | return -ENOMEM; | |
2141 | } | |
2142 | ||
ebc2ec48 | 2143 | SET_NETDEV_DEV(netdev, &intf->dev); |
ac718b69 | 2144 | tp = netdev_priv(netdev); |
2145 | tp->msg_enable = 0x7FFF; | |
2146 | ||
c81229c9 | 2147 | if (!rtl_ops_init(tp, id)) { |
2148 | netif_err(tp, probe, netdev, "Unknown Device"); | |
2149 | return -ENODEV; | |
2150 | } | |
2151 | ||
ebc2ec48 | 2152 | tasklet_init(&tp->tl, bottom_half, (unsigned long)tp); |
ac718b69 | 2153 | INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t); |
2154 | ||
2155 | tp->udev = udev; | |
2156 | tp->netdev = netdev; | |
40a82917 | 2157 | tp->intf = intf; |
ac718b69 | 2158 | netdev->netdev_ops = &rtl8152_netdev_ops; |
2159 | netdev->watchdog_timeo = RTL8152_TX_TIMEOUT; | |
5bd23881 | 2160 | |
2161 | netdev->features |= NETIF_F_IP_CSUM; | |
2162 | netdev->hw_features = NETIF_F_IP_CSUM; | |
ac718b69 | 2163 | SET_ETHTOOL_OPS(netdev, &ops); |
ac718b69 | 2164 | |
2165 | tp->mii.dev = netdev; | |
2166 | tp->mii.mdio_read = read_mii_word; | |
2167 | tp->mii.mdio_write = write_mii_word; | |
2168 | tp->mii.phy_id_mask = 0x3f; | |
2169 | tp->mii.reg_num_mask = 0x1f; | |
2170 | tp->mii.phy_id = R8152_PHY_ID; | |
2171 | tp->mii.supports_gmii = 0; | |
2172 | ||
2173 | r8152b_get_version(tp); | |
c81229c9 | 2174 | tp->rtl_ops.init(tp); |
ac718b69 | 2175 | set_ethernet_addr(tp); |
2176 | ||
ebc2ec48 | 2177 | ret = alloc_all_mem(tp); |
2178 | if (ret) | |
ac718b69 | 2179 | goto out; |
ac718b69 | 2180 | |
2181 | usb_set_intfdata(intf, tp); | |
ac718b69 | 2182 | |
ebc2ec48 | 2183 | ret = register_netdev(netdev); |
2184 | if (ret != 0) { | |
ac718b69 | 2185 | netif_err(tp, probe, netdev, "couldn't register the device"); |
ebc2ec48 | 2186 | goto out1; |
ac718b69 | 2187 | } |
2188 | ||
2189 | netif_info(tp, probe, netdev, "%s", DRIVER_VERSION); | |
2190 | ||
2191 | return 0; | |
2192 | ||
ac718b69 | 2193 | out1: |
ebc2ec48 | 2194 | usb_set_intfdata(intf, NULL); |
ac718b69 | 2195 | out: |
2196 | free_netdev(netdev); | |
ebc2ec48 | 2197 | return ret; |
ac718b69 | 2198 | } |
2199 | ||
ac718b69 | 2200 | static void rtl8152_disconnect(struct usb_interface *intf) |
2201 | { | |
2202 | struct r8152 *tp = usb_get_intfdata(intf); | |
2203 | ||
2204 | usb_set_intfdata(intf, NULL); | |
2205 | if (tp) { | |
2206 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
2207 | tasklet_kill(&tp->tl); | |
2208 | unregister_netdev(tp->netdev); | |
c81229c9 | 2209 | tp->rtl_ops.unload(tp); |
ebc2ec48 | 2210 | free_all_mem(tp); |
ac718b69 | 2211 | free_netdev(tp->netdev); |
2212 | } | |
2213 | } | |
2214 | ||
2215 | /* table of devices that work with this driver */ | |
2216 | static struct usb_device_id rtl8152_table[] = { | |
2217 | {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8152)}, | |
2218 | {} | |
2219 | }; | |
2220 | ||
2221 | MODULE_DEVICE_TABLE(usb, rtl8152_table); | |
2222 | ||
2223 | static struct usb_driver rtl8152_driver = { | |
2224 | .name = MODULENAME, | |
ebc2ec48 | 2225 | .id_table = rtl8152_table, |
ac718b69 | 2226 | .probe = rtl8152_probe, |
2227 | .disconnect = rtl8152_disconnect, | |
ac718b69 | 2228 | .suspend = rtl8152_suspend, |
ebc2ec48 | 2229 | .resume = rtl8152_resume, |
2230 | .reset_resume = rtl8152_resume, | |
ac718b69 | 2231 | }; |
2232 | ||
b4236daa | 2233 | module_usb_driver(rtl8152_driver); |
ac718b69 | 2234 | |
2235 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
2236 | MODULE_DESCRIPTION(DRIVER_DESC); | |
2237 | MODULE_LICENSE("GPL"); |