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ac718b69 | 1 | /* |
c7de7dec | 2 | * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved. |
ac718b69 | 3 | * |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * version 2 as published by the Free Software Foundation. | |
7 | * | |
8 | */ | |
9 | ||
ac718b69 | 10 | #include <linux/signal.h> |
11 | #include <linux/slab.h> | |
12 | #include <linux/module.h> | |
ac718b69 | 13 | #include <linux/netdevice.h> |
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/mii.h> | |
16 | #include <linux/ethtool.h> | |
17 | #include <linux/usb.h> | |
18 | #include <linux/crc32.h> | |
19 | #include <linux/if_vlan.h> | |
20 | #include <linux/uaccess.h> | |
ebc2ec48 | 21 | #include <linux/list.h> |
5bd23881 | 22 | #include <linux/ip.h> |
23 | #include <linux/ipv6.h> | |
ac718b69 | 24 | |
25 | /* Version Information */ | |
21ff2e89 | 26 | #define DRIVER_VERSION "v1.05.0 (2014/02/18)" |
ac718b69 | 27 | #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>" |
44d942a9 | 28 | #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters" |
ac718b69 | 29 | #define MODULENAME "r8152" |
30 | ||
31 | #define R8152_PHY_ID 32 | |
32 | ||
33 | #define PLA_IDR 0xc000 | |
34 | #define PLA_RCR 0xc010 | |
35 | #define PLA_RMS 0xc016 | |
36 | #define PLA_RXFIFO_CTRL0 0xc0a0 | |
37 | #define PLA_RXFIFO_CTRL1 0xc0a4 | |
38 | #define PLA_RXFIFO_CTRL2 0xc0a8 | |
39 | #define PLA_FMC 0xc0b4 | |
40 | #define PLA_CFG_WOL 0xc0b6 | |
43779f8d | 41 | #define PLA_TEREDO_CFG 0xc0bc |
ac718b69 | 42 | #define PLA_MAR 0xcd00 |
43779f8d | 43 | #define PLA_BACKUP 0xd000 |
ac718b69 | 44 | #define PAL_BDC_CR 0xd1a0 |
43779f8d | 45 | #define PLA_TEREDO_TIMER 0xd2cc |
46 | #define PLA_REALWOW_TIMER 0xd2e8 | |
ac718b69 | 47 | #define PLA_LEDSEL 0xdd90 |
48 | #define PLA_LED_FEATURE 0xdd92 | |
49 | #define PLA_PHYAR 0xde00 | |
43779f8d | 50 | #define PLA_BOOT_CTRL 0xe004 |
ac718b69 | 51 | #define PLA_GPHY_INTR_IMR 0xe022 |
52 | #define PLA_EEE_CR 0xe040 | |
53 | #define PLA_EEEP_CR 0xe080 | |
54 | #define PLA_MAC_PWR_CTRL 0xe0c0 | |
43779f8d | 55 | #define PLA_MAC_PWR_CTRL2 0xe0ca |
56 | #define PLA_MAC_PWR_CTRL3 0xe0cc | |
57 | #define PLA_MAC_PWR_CTRL4 0xe0ce | |
58 | #define PLA_WDT6_CTRL 0xe428 | |
ac718b69 | 59 | #define PLA_TCR0 0xe610 |
60 | #define PLA_TCR1 0xe612 | |
61 | #define PLA_TXFIFO_CTRL 0xe618 | |
62 | #define PLA_RSTTELLY 0xe800 | |
63 | #define PLA_CR 0xe813 | |
64 | #define PLA_CRWECR 0xe81c | |
21ff2e89 | 65 | #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */ |
66 | #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */ | |
ac718b69 | 67 | #define PLA_CONFIG5 0xe822 |
68 | #define PLA_PHY_PWR 0xe84c | |
69 | #define PLA_OOB_CTRL 0xe84f | |
70 | #define PLA_CPCR 0xe854 | |
71 | #define PLA_MISC_0 0xe858 | |
72 | #define PLA_MISC_1 0xe85a | |
73 | #define PLA_OCP_GPHY_BASE 0xe86c | |
74 | #define PLA_TELLYCNT 0xe890 | |
75 | #define PLA_SFF_STS_7 0xe8de | |
76 | #define PLA_PHYSTATUS 0xe908 | |
77 | #define PLA_BP_BA 0xfc26 | |
78 | #define PLA_BP_0 0xfc28 | |
79 | #define PLA_BP_1 0xfc2a | |
80 | #define PLA_BP_2 0xfc2c | |
81 | #define PLA_BP_3 0xfc2e | |
82 | #define PLA_BP_4 0xfc30 | |
83 | #define PLA_BP_5 0xfc32 | |
84 | #define PLA_BP_6 0xfc34 | |
85 | #define PLA_BP_7 0xfc36 | |
43779f8d | 86 | #define PLA_BP_EN 0xfc38 |
ac718b69 | 87 | |
43779f8d | 88 | #define USB_U2P3_CTRL 0xb460 |
ac718b69 | 89 | #define USB_DEV_STAT 0xb808 |
90 | #define USB_USB_CTRL 0xd406 | |
91 | #define USB_PHY_CTRL 0xd408 | |
92 | #define USB_TX_AGG 0xd40a | |
93 | #define USB_RX_BUF_TH 0xd40c | |
94 | #define USB_USB_TIMER 0xd428 | |
43779f8d | 95 | #define USB_RX_EARLY_AGG 0xd42c |
ac718b69 | 96 | #define USB_PM_CTRL_STATUS 0xd432 |
97 | #define USB_TX_DMA 0xd434 | |
43779f8d | 98 | #define USB_TOLERANCE 0xd490 |
99 | #define USB_LPM_CTRL 0xd41a | |
ac718b69 | 100 | #define USB_UPS_CTRL 0xd800 |
43779f8d | 101 | #define USB_MISC_0 0xd81a |
102 | #define USB_POWER_CUT 0xd80a | |
103 | #define USB_AFE_CTRL2 0xd824 | |
104 | #define USB_WDT11_CTRL 0xe43c | |
ac718b69 | 105 | #define USB_BP_BA 0xfc26 |
106 | #define USB_BP_0 0xfc28 | |
107 | #define USB_BP_1 0xfc2a | |
108 | #define USB_BP_2 0xfc2c | |
109 | #define USB_BP_3 0xfc2e | |
110 | #define USB_BP_4 0xfc30 | |
111 | #define USB_BP_5 0xfc32 | |
112 | #define USB_BP_6 0xfc34 | |
113 | #define USB_BP_7 0xfc36 | |
43779f8d | 114 | #define USB_BP_EN 0xfc38 |
ac718b69 | 115 | |
116 | /* OCP Registers */ | |
117 | #define OCP_ALDPS_CONFIG 0x2010 | |
118 | #define OCP_EEE_CONFIG1 0x2080 | |
119 | #define OCP_EEE_CONFIG2 0x2092 | |
120 | #define OCP_EEE_CONFIG3 0x2094 | |
ac244d3e | 121 | #define OCP_BASE_MII 0xa400 |
ac718b69 | 122 | #define OCP_EEE_AR 0xa41a |
123 | #define OCP_EEE_DATA 0xa41c | |
43779f8d | 124 | #define OCP_PHY_STATUS 0xa420 |
125 | #define OCP_POWER_CFG 0xa430 | |
126 | #define OCP_EEE_CFG 0xa432 | |
127 | #define OCP_SRAM_ADDR 0xa436 | |
128 | #define OCP_SRAM_DATA 0xa438 | |
129 | #define OCP_DOWN_SPEED 0xa442 | |
130 | #define OCP_EEE_CFG2 0xa5d0 | |
131 | #define OCP_ADC_CFG 0xbc06 | |
132 | ||
133 | /* SRAM Register */ | |
134 | #define SRAM_LPF_CFG 0x8012 | |
135 | #define SRAM_10M_AMP1 0x8080 | |
136 | #define SRAM_10M_AMP2 0x8082 | |
137 | #define SRAM_IMPEDANCE 0x8084 | |
ac718b69 | 138 | |
139 | /* PLA_RCR */ | |
140 | #define RCR_AAP 0x00000001 | |
141 | #define RCR_APM 0x00000002 | |
142 | #define RCR_AM 0x00000004 | |
143 | #define RCR_AB 0x00000008 | |
144 | #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB) | |
145 | ||
146 | /* PLA_RXFIFO_CTRL0 */ | |
147 | #define RXFIFO_THR1_NORMAL 0x00080002 | |
148 | #define RXFIFO_THR1_OOB 0x01800003 | |
149 | ||
150 | /* PLA_RXFIFO_CTRL1 */ | |
151 | #define RXFIFO_THR2_FULL 0x00000060 | |
152 | #define RXFIFO_THR2_HIGH 0x00000038 | |
153 | #define RXFIFO_THR2_OOB 0x0000004a | |
43779f8d | 154 | #define RXFIFO_THR2_NORMAL 0x00a0 |
ac718b69 | 155 | |
156 | /* PLA_RXFIFO_CTRL2 */ | |
157 | #define RXFIFO_THR3_FULL 0x00000078 | |
158 | #define RXFIFO_THR3_HIGH 0x00000048 | |
159 | #define RXFIFO_THR3_OOB 0x0000005a | |
43779f8d | 160 | #define RXFIFO_THR3_NORMAL 0x0110 |
ac718b69 | 161 | |
162 | /* PLA_TXFIFO_CTRL */ | |
163 | #define TXFIFO_THR_NORMAL 0x00400008 | |
43779f8d | 164 | #define TXFIFO_THR_NORMAL2 0x01000008 |
ac718b69 | 165 | |
166 | /* PLA_FMC */ | |
167 | #define FMC_FCR_MCU_EN 0x0001 | |
168 | ||
169 | /* PLA_EEEP_CR */ | |
170 | #define EEEP_CR_EEEP_TX 0x0002 | |
171 | ||
43779f8d | 172 | /* PLA_WDT6_CTRL */ |
173 | #define WDT6_SET_MODE 0x0010 | |
174 | ||
ac718b69 | 175 | /* PLA_TCR0 */ |
176 | #define TCR0_TX_EMPTY 0x0800 | |
177 | #define TCR0_AUTO_FIFO 0x0080 | |
178 | ||
179 | /* PLA_TCR1 */ | |
180 | #define VERSION_MASK 0x7cf0 | |
181 | ||
182 | /* PLA_CR */ | |
183 | #define CR_RST 0x10 | |
184 | #define CR_RE 0x08 | |
185 | #define CR_TE 0x04 | |
186 | ||
187 | /* PLA_CRWECR */ | |
188 | #define CRWECR_NORAML 0x00 | |
189 | #define CRWECR_CONFIG 0xc0 | |
190 | ||
191 | /* PLA_OOB_CTRL */ | |
192 | #define NOW_IS_OOB 0x80 | |
193 | #define TXFIFO_EMPTY 0x20 | |
194 | #define RXFIFO_EMPTY 0x10 | |
195 | #define LINK_LIST_READY 0x02 | |
196 | #define DIS_MCU_CLROOB 0x01 | |
197 | #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY) | |
198 | ||
199 | /* PLA_MISC_1 */ | |
200 | #define RXDY_GATED_EN 0x0008 | |
201 | ||
202 | /* PLA_SFF_STS_7 */ | |
203 | #define RE_INIT_LL 0x8000 | |
204 | #define MCU_BORW_EN 0x4000 | |
205 | ||
206 | /* PLA_CPCR */ | |
207 | #define CPCR_RX_VLAN 0x0040 | |
208 | ||
209 | /* PLA_CFG_WOL */ | |
210 | #define MAGIC_EN 0x0001 | |
211 | ||
43779f8d | 212 | /* PLA_TEREDO_CFG */ |
213 | #define TEREDO_SEL 0x8000 | |
214 | #define TEREDO_WAKE_MASK 0x7f00 | |
215 | #define TEREDO_RS_EVENT_MASK 0x00fe | |
216 | #define OOB_TEREDO_EN 0x0001 | |
217 | ||
ac718b69 | 218 | /* PAL_BDC_CR */ |
219 | #define ALDPS_PROXY_MODE 0x0001 | |
220 | ||
21ff2e89 | 221 | /* PLA_CONFIG34 */ |
222 | #define LINK_ON_WAKE_EN 0x0010 | |
223 | #define LINK_OFF_WAKE_EN 0x0008 | |
224 | ||
ac718b69 | 225 | /* PLA_CONFIG5 */ |
21ff2e89 | 226 | #define BWF_EN 0x0040 |
227 | #define MWF_EN 0x0020 | |
228 | #define UWF_EN 0x0010 | |
ac718b69 | 229 | #define LAN_WAKE_EN 0x0002 |
230 | ||
231 | /* PLA_LED_FEATURE */ | |
232 | #define LED_MODE_MASK 0x0700 | |
233 | ||
234 | /* PLA_PHY_PWR */ | |
235 | #define TX_10M_IDLE_EN 0x0080 | |
236 | #define PFM_PWM_SWITCH 0x0040 | |
237 | ||
238 | /* PLA_MAC_PWR_CTRL */ | |
239 | #define D3_CLK_GATED_EN 0x00004000 | |
240 | #define MCU_CLK_RATIO 0x07010f07 | |
241 | #define MCU_CLK_RATIO_MASK 0x0f0f0f0f | |
43779f8d | 242 | #define ALDPS_SPDWN_RATIO 0x0f87 |
243 | ||
244 | /* PLA_MAC_PWR_CTRL2 */ | |
245 | #define EEE_SPDWN_RATIO 0x8007 | |
246 | ||
247 | /* PLA_MAC_PWR_CTRL3 */ | |
248 | #define PKT_AVAIL_SPDWN_EN 0x0100 | |
249 | #define SUSPEND_SPDWN_EN 0x0004 | |
250 | #define U1U2_SPDWN_EN 0x0002 | |
251 | #define L1_SPDWN_EN 0x0001 | |
252 | ||
253 | /* PLA_MAC_PWR_CTRL4 */ | |
254 | #define PWRSAVE_SPDWN_EN 0x1000 | |
255 | #define RXDV_SPDWN_EN 0x0800 | |
256 | #define TX10MIDLE_EN 0x0100 | |
257 | #define TP100_SPDWN_EN 0x0020 | |
258 | #define TP500_SPDWN_EN 0x0010 | |
259 | #define TP1000_SPDWN_EN 0x0008 | |
260 | #define EEE_SPDWN_EN 0x0001 | |
ac718b69 | 261 | |
262 | /* PLA_GPHY_INTR_IMR */ | |
263 | #define GPHY_STS_MSK 0x0001 | |
264 | #define SPEED_DOWN_MSK 0x0002 | |
265 | #define SPDWN_RXDV_MSK 0x0004 | |
266 | #define SPDWN_LINKCHG_MSK 0x0008 | |
267 | ||
268 | /* PLA_PHYAR */ | |
269 | #define PHYAR_FLAG 0x80000000 | |
270 | ||
271 | /* PLA_EEE_CR */ | |
272 | #define EEE_RX_EN 0x0001 | |
273 | #define EEE_TX_EN 0x0002 | |
274 | ||
43779f8d | 275 | /* PLA_BOOT_CTRL */ |
276 | #define AUTOLOAD_DONE 0x0002 | |
277 | ||
ac718b69 | 278 | /* USB_DEV_STAT */ |
279 | #define STAT_SPEED_MASK 0x0006 | |
280 | #define STAT_SPEED_HIGH 0x0000 | |
281 | #define STAT_SPEED_FULL 0x0001 | |
282 | ||
283 | /* USB_TX_AGG */ | |
284 | #define TX_AGG_MAX_THRESHOLD 0x03 | |
285 | ||
286 | /* USB_RX_BUF_TH */ | |
43779f8d | 287 | #define RX_THR_SUPPER 0x0c350180 |
8e1f51bd | 288 | #define RX_THR_HIGH 0x7a120180 |
43779f8d | 289 | #define RX_THR_SLOW 0xffff0180 |
ac718b69 | 290 | |
291 | /* USB_TX_DMA */ | |
292 | #define TEST_MODE_DISABLE 0x00000001 | |
293 | #define TX_SIZE_ADJUST1 0x00000100 | |
294 | ||
295 | /* USB_UPS_CTRL */ | |
296 | #define POWER_CUT 0x0100 | |
297 | ||
298 | /* USB_PM_CTRL_STATUS */ | |
8e1f51bd | 299 | #define RESUME_INDICATE 0x0001 |
ac718b69 | 300 | |
301 | /* USB_USB_CTRL */ | |
302 | #define RX_AGG_DISABLE 0x0010 | |
303 | ||
43779f8d | 304 | /* USB_U2P3_CTRL */ |
305 | #define U2P3_ENABLE 0x0001 | |
306 | ||
307 | /* USB_POWER_CUT */ | |
308 | #define PWR_EN 0x0001 | |
309 | #define PHASE2_EN 0x0008 | |
310 | ||
311 | /* USB_MISC_0 */ | |
312 | #define PCUT_STATUS 0x0001 | |
313 | ||
314 | /* USB_RX_EARLY_AGG */ | |
315 | #define EARLY_AGG_SUPPER 0x0e832981 | |
316 | #define EARLY_AGG_HIGH 0x0e837a12 | |
317 | #define EARLY_AGG_SLOW 0x0e83ffff | |
318 | ||
319 | /* USB_WDT11_CTRL */ | |
320 | #define TIMER11_EN 0x0001 | |
321 | ||
322 | /* USB_LPM_CTRL */ | |
323 | #define LPM_TIMER_MASK 0x0c | |
324 | #define LPM_TIMER_500MS 0x04 /* 500 ms */ | |
325 | #define LPM_TIMER_500US 0x0c /* 500 us */ | |
326 | ||
327 | /* USB_AFE_CTRL2 */ | |
328 | #define SEN_VAL_MASK 0xf800 | |
329 | #define SEN_VAL_NORMAL 0xa000 | |
330 | #define SEL_RXIDLE 0x0100 | |
331 | ||
ac718b69 | 332 | /* OCP_ALDPS_CONFIG */ |
333 | #define ENPWRSAVE 0x8000 | |
334 | #define ENPDNPS 0x0200 | |
335 | #define LINKENA 0x0100 | |
336 | #define DIS_SDSAVE 0x0010 | |
337 | ||
43779f8d | 338 | /* OCP_PHY_STATUS */ |
339 | #define PHY_STAT_MASK 0x0007 | |
340 | #define PHY_STAT_LAN_ON 3 | |
341 | #define PHY_STAT_PWRDN 5 | |
342 | ||
343 | /* OCP_POWER_CFG */ | |
344 | #define EEE_CLKDIV_EN 0x8000 | |
345 | #define EN_ALDPS 0x0004 | |
346 | #define EN_10M_PLLOFF 0x0001 | |
347 | ||
ac718b69 | 348 | /* OCP_EEE_CONFIG1 */ |
349 | #define RG_TXLPI_MSK_HFDUP 0x8000 | |
350 | #define RG_MATCLR_EN 0x4000 | |
351 | #define EEE_10_CAP 0x2000 | |
352 | #define EEE_NWAY_EN 0x1000 | |
353 | #define TX_QUIET_EN 0x0200 | |
354 | #define RX_QUIET_EN 0x0100 | |
355 | #define SDRISETIME 0x0010 /* bit 4 ~ 6 */ | |
356 | #define RG_RXLPI_MSK_HFDUP 0x0008 | |
357 | #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */ | |
358 | ||
359 | /* OCP_EEE_CONFIG2 */ | |
360 | #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */ | |
361 | #define RG_DACQUIET_EN 0x0400 | |
362 | #define RG_LDVQUIET_EN 0x0200 | |
363 | #define RG_CKRSEL 0x0020 | |
364 | #define RG_EEEPRG_EN 0x0010 | |
365 | ||
366 | /* OCP_EEE_CONFIG3 */ | |
367 | #define FST_SNR_EYE_R 0x1500 /* bit 7 ~ 15 */ | |
368 | #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */ | |
369 | #define MSK_PH 0x0006 /* bit 0 ~ 3 */ | |
370 | ||
371 | /* OCP_EEE_AR */ | |
372 | /* bit[15:14] function */ | |
373 | #define FUN_ADDR 0x0000 | |
374 | #define FUN_DATA 0x4000 | |
375 | /* bit[4:0] device addr */ | |
376 | #define DEVICE_ADDR 0x0007 | |
377 | ||
378 | /* OCP_EEE_DATA */ | |
379 | #define EEE_ADDR 0x003C | |
380 | #define EEE_DATA 0x0002 | |
381 | ||
43779f8d | 382 | /* OCP_EEE_CFG */ |
383 | #define CTAP_SHORT_EN 0x0040 | |
384 | #define EEE10_EN 0x0010 | |
385 | ||
386 | /* OCP_DOWN_SPEED */ | |
387 | #define EN_10M_BGOFF 0x0080 | |
388 | ||
389 | /* OCP_EEE_CFG2 */ | |
390 | #define MY1000_EEE 0x0004 | |
391 | #define MY100_EEE 0x0002 | |
392 | ||
393 | /* OCP_ADC_CFG */ | |
394 | #define CKADSEL_L 0x0100 | |
395 | #define ADC_EN 0x0080 | |
396 | #define EN_EMI_L 0x0040 | |
397 | ||
398 | /* SRAM_LPF_CFG */ | |
399 | #define LPF_AUTO_TUNE 0x8000 | |
400 | ||
401 | /* SRAM_10M_AMP1 */ | |
402 | #define GDAC_IB_UPALL 0x0008 | |
403 | ||
404 | /* SRAM_10M_AMP2 */ | |
405 | #define AMP_DN 0x0200 | |
406 | ||
407 | /* SRAM_IMPEDANCE */ | |
408 | #define RX_DRIVING_MASK 0x6000 | |
409 | ||
ac718b69 | 410 | enum rtl_register_content { |
43779f8d | 411 | _1000bps = 0x10, |
ac718b69 | 412 | _100bps = 0x08, |
413 | _10bps = 0x04, | |
414 | LINK_STATUS = 0x02, | |
415 | FULL_DUP = 0x01, | |
416 | }; | |
417 | ||
ebc2ec48 | 418 | #define RTL8152_MAX_TX 10 |
419 | #define RTL8152_MAX_RX 10 | |
40a82917 | 420 | #define INTBUFSIZE 2 |
8e1f51bd | 421 | #define CRC_SIZE 4 |
422 | #define TX_ALIGN 4 | |
423 | #define RX_ALIGN 8 | |
40a82917 | 424 | |
425 | #define INTR_LINK 0x0004 | |
ebc2ec48 | 426 | |
ac718b69 | 427 | #define RTL8152_REQT_READ 0xc0 |
428 | #define RTL8152_REQT_WRITE 0x40 | |
429 | #define RTL8152_REQ_GET_REGS 0x05 | |
430 | #define RTL8152_REQ_SET_REGS 0x05 | |
431 | ||
432 | #define BYTE_EN_DWORD 0xff | |
433 | #define BYTE_EN_WORD 0x33 | |
434 | #define BYTE_EN_BYTE 0x11 | |
435 | #define BYTE_EN_SIX_BYTES 0x3f | |
436 | #define BYTE_EN_START_MASK 0x0f | |
437 | #define BYTE_EN_END_MASK 0xf0 | |
438 | ||
439 | #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN) | |
440 | #define RTL8152_TX_TIMEOUT (HZ) | |
441 | ||
442 | /* rtl8152 flags */ | |
443 | enum rtl8152_flags { | |
444 | RTL8152_UNPLUG = 0, | |
ac718b69 | 445 | RTL8152_SET_RX_MODE, |
40a82917 | 446 | WORK_ENABLE, |
447 | RTL8152_LINK_CHG, | |
9a4be1bd | 448 | SELECTIVE_SUSPEND, |
aa66a5f1 | 449 | PHY_RESET, |
ac718b69 | 450 | }; |
451 | ||
452 | /* Define these values to match your device */ | |
453 | #define VENDOR_ID_REALTEK 0x0bda | |
454 | #define PRODUCT_ID_RTL8152 0x8152 | |
43779f8d | 455 | #define PRODUCT_ID_RTL8153 0x8153 |
456 | ||
457 | #define VENDOR_ID_SAMSUNG 0x04e8 | |
458 | #define PRODUCT_ID_SAMSUNG 0xa101 | |
ac718b69 | 459 | |
460 | #define MCU_TYPE_PLA 0x0100 | |
461 | #define MCU_TYPE_USB 0x0000 | |
462 | ||
c7de7dec | 463 | #define REALTEK_USB_DEVICE(vend, prod) \ |
464 | USB_DEVICE_INTERFACE_CLASS(vend, prod, USB_CLASS_VENDOR_SPEC) | |
465 | ||
ac718b69 | 466 | struct rx_desc { |
500b6d7e | 467 | __le32 opts1; |
ac718b69 | 468 | #define RX_LEN_MASK 0x7fff |
500b6d7e | 469 | __le32 opts2; |
470 | __le32 opts3; | |
471 | __le32 opts4; | |
472 | __le32 opts5; | |
473 | __le32 opts6; | |
ac718b69 | 474 | }; |
475 | ||
476 | struct tx_desc { | |
500b6d7e | 477 | __le32 opts1; |
ac718b69 | 478 | #define TX_FS (1 << 31) /* First segment of a packet */ |
479 | #define TX_LS (1 << 30) /* Final segment of a packet */ | |
5bd23881 | 480 | #define TX_LEN_MASK 0x3ffff |
481 | ||
500b6d7e | 482 | __le32 opts2; |
5bd23881 | 483 | #define UDP_CS (1 << 31) /* Calculate UDP/IP checksum */ |
484 | #define TCP_CS (1 << 30) /* Calculate TCP/IP checksum */ | |
485 | #define IPV4_CS (1 << 29) /* Calculate IPv4 checksum */ | |
486 | #define IPV6_CS (1 << 28) /* Calculate IPv6 checksum */ | |
ac718b69 | 487 | }; |
488 | ||
dff4e8ad | 489 | struct r8152; |
490 | ||
ebc2ec48 | 491 | struct rx_agg { |
492 | struct list_head list; | |
493 | struct urb *urb; | |
dff4e8ad | 494 | struct r8152 *context; |
ebc2ec48 | 495 | void *buffer; |
496 | void *head; | |
497 | }; | |
498 | ||
499 | struct tx_agg { | |
500 | struct list_head list; | |
501 | struct urb *urb; | |
dff4e8ad | 502 | struct r8152 *context; |
ebc2ec48 | 503 | void *buffer; |
504 | void *head; | |
505 | u32 skb_num; | |
506 | u32 skb_len; | |
507 | }; | |
508 | ||
ac718b69 | 509 | struct r8152 { |
510 | unsigned long flags; | |
511 | struct usb_device *udev; | |
512 | struct tasklet_struct tl; | |
40a82917 | 513 | struct usb_interface *intf; |
ac718b69 | 514 | struct net_device *netdev; |
40a82917 | 515 | struct urb *intr_urb; |
ebc2ec48 | 516 | struct tx_agg tx_info[RTL8152_MAX_TX]; |
517 | struct rx_agg rx_info[RTL8152_MAX_RX]; | |
518 | struct list_head rx_done, tx_free; | |
519 | struct sk_buff_head tx_queue; | |
520 | spinlock_t rx_lock, tx_lock; | |
ac718b69 | 521 | struct delayed_work schedule; |
522 | struct mii_if_info mii; | |
c81229c9 | 523 | |
524 | struct rtl_ops { | |
525 | void (*init)(struct r8152 *); | |
526 | int (*enable)(struct r8152 *); | |
527 | void (*disable)(struct r8152 *); | |
7e9da481 | 528 | void (*up)(struct r8152 *); |
c81229c9 | 529 | void (*down)(struct r8152 *); |
530 | void (*unload)(struct r8152 *); | |
531 | } rtl_ops; | |
532 | ||
40a82917 | 533 | int intr_interval; |
21ff2e89 | 534 | u32 saved_wolopts; |
ac718b69 | 535 | u32 msg_enable; |
dd1b119c | 536 | u32 tx_qlen; |
ac718b69 | 537 | u16 ocp_base; |
40a82917 | 538 | u8 *intr_buff; |
ac718b69 | 539 | u8 version; |
540 | u8 speed; | |
541 | }; | |
542 | ||
543 | enum rtl_version { | |
544 | RTL_VER_UNKNOWN = 0, | |
545 | RTL_VER_01, | |
43779f8d | 546 | RTL_VER_02, |
547 | RTL_VER_03, | |
548 | RTL_VER_04, | |
549 | RTL_VER_05, | |
550 | RTL_VER_MAX | |
ac718b69 | 551 | }; |
552 | ||
553 | /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). | |
554 | * The RTL chips use a 64 element hash table based on the Ethernet CRC. | |
555 | */ | |
556 | static const int multicast_filter_limit = 32; | |
ebc2ec48 | 557 | static unsigned int rx_buf_sz = 16384; |
ac718b69 | 558 | |
559 | static | |
560 | int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) | |
561 | { | |
31787f53 | 562 | int ret; |
563 | void *tmp; | |
564 | ||
565 | tmp = kmalloc(size, GFP_KERNEL); | |
566 | if (!tmp) | |
567 | return -ENOMEM; | |
568 | ||
569 | ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0), | |
ac718b69 | 570 | RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, |
31787f53 | 571 | value, index, tmp, size, 500); |
572 | ||
573 | memcpy(data, tmp, size); | |
574 | kfree(tmp); | |
575 | ||
576 | return ret; | |
ac718b69 | 577 | } |
578 | ||
579 | static | |
580 | int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) | |
581 | { | |
31787f53 | 582 | int ret; |
583 | void *tmp; | |
584 | ||
585 | tmp = kmalloc(size, GFP_KERNEL); | |
586 | if (!tmp) | |
587 | return -ENOMEM; | |
588 | ||
589 | memcpy(tmp, data, size); | |
590 | ||
591 | ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0), | |
ac718b69 | 592 | RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE, |
31787f53 | 593 | value, index, tmp, size, 500); |
594 | ||
595 | kfree(tmp); | |
db8515ef | 596 | |
31787f53 | 597 | return ret; |
ac718b69 | 598 | } |
599 | ||
600 | static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size, | |
601 | void *data, u16 type) | |
602 | { | |
45f4a19f | 603 | u16 limit = 64; |
604 | int ret = 0; | |
ac718b69 | 605 | |
606 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
607 | return -ENODEV; | |
608 | ||
609 | /* both size and indix must be 4 bytes align */ | |
610 | if ((size & 3) || !size || (index & 3) || !data) | |
611 | return -EPERM; | |
612 | ||
613 | if ((u32)index + (u32)size > 0xffff) | |
614 | return -EPERM; | |
615 | ||
616 | while (size) { | |
617 | if (size > limit) { | |
618 | ret = get_registers(tp, index, type, limit, data); | |
619 | if (ret < 0) | |
620 | break; | |
621 | ||
622 | index += limit; | |
623 | data += limit; | |
624 | size -= limit; | |
625 | } else { | |
626 | ret = get_registers(tp, index, type, size, data); | |
627 | if (ret < 0) | |
628 | break; | |
629 | ||
630 | index += size; | |
631 | data += size; | |
632 | size = 0; | |
633 | break; | |
634 | } | |
635 | } | |
636 | ||
637 | return ret; | |
638 | } | |
639 | ||
640 | static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, | |
641 | u16 size, void *data, u16 type) | |
642 | { | |
45f4a19f | 643 | int ret; |
644 | u16 byteen_start, byteen_end, byen; | |
645 | u16 limit = 512; | |
ac718b69 | 646 | |
647 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
648 | return -ENODEV; | |
649 | ||
650 | /* both size and indix must be 4 bytes align */ | |
651 | if ((size & 3) || !size || (index & 3) || !data) | |
652 | return -EPERM; | |
653 | ||
654 | if ((u32)index + (u32)size > 0xffff) | |
655 | return -EPERM; | |
656 | ||
657 | byteen_start = byteen & BYTE_EN_START_MASK; | |
658 | byteen_end = byteen & BYTE_EN_END_MASK; | |
659 | ||
660 | byen = byteen_start | (byteen_start << 4); | |
661 | ret = set_registers(tp, index, type | byen, 4, data); | |
662 | if (ret < 0) | |
663 | goto error1; | |
664 | ||
665 | index += 4; | |
666 | data += 4; | |
667 | size -= 4; | |
668 | ||
669 | if (size) { | |
670 | size -= 4; | |
671 | ||
672 | while (size) { | |
673 | if (size > limit) { | |
674 | ret = set_registers(tp, index, | |
675 | type | BYTE_EN_DWORD, | |
676 | limit, data); | |
677 | if (ret < 0) | |
678 | goto error1; | |
679 | ||
680 | index += limit; | |
681 | data += limit; | |
682 | size -= limit; | |
683 | } else { | |
684 | ret = set_registers(tp, index, | |
685 | type | BYTE_EN_DWORD, | |
686 | size, data); | |
687 | if (ret < 0) | |
688 | goto error1; | |
689 | ||
690 | index += size; | |
691 | data += size; | |
692 | size = 0; | |
693 | break; | |
694 | } | |
695 | } | |
696 | ||
697 | byen = byteen_end | (byteen_end >> 4); | |
698 | ret = set_registers(tp, index, type | byen, 4, data); | |
699 | if (ret < 0) | |
700 | goto error1; | |
701 | } | |
702 | ||
703 | error1: | |
704 | return ret; | |
705 | } | |
706 | ||
707 | static inline | |
708 | int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) | |
709 | { | |
710 | return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA); | |
711 | } | |
712 | ||
713 | static inline | |
714 | int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) | |
715 | { | |
716 | return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA); | |
717 | } | |
718 | ||
719 | static inline | |
720 | int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) | |
721 | { | |
722 | return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB); | |
723 | } | |
724 | ||
725 | static inline | |
726 | int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) | |
727 | { | |
728 | return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB); | |
729 | } | |
730 | ||
731 | static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index) | |
732 | { | |
c8826de8 | 733 | __le32 data; |
ac718b69 | 734 | |
c8826de8 | 735 | generic_ocp_read(tp, index, sizeof(data), &data, type); |
ac718b69 | 736 | |
737 | return __le32_to_cpu(data); | |
738 | } | |
739 | ||
740 | static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data) | |
741 | { | |
c8826de8 | 742 | __le32 tmp = __cpu_to_le32(data); |
743 | ||
744 | generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type); | |
ac718b69 | 745 | } |
746 | ||
747 | static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index) | |
748 | { | |
749 | u32 data; | |
c8826de8 | 750 | __le32 tmp; |
ac718b69 | 751 | u8 shift = index & 2; |
752 | ||
753 | index &= ~3; | |
754 | ||
c8826de8 | 755 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 756 | |
c8826de8 | 757 | data = __le32_to_cpu(tmp); |
ac718b69 | 758 | data >>= (shift * 8); |
759 | data &= 0xffff; | |
760 | ||
761 | return (u16)data; | |
762 | } | |
763 | ||
764 | static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data) | |
765 | { | |
c8826de8 | 766 | u32 mask = 0xffff; |
767 | __le32 tmp; | |
ac718b69 | 768 | u16 byen = BYTE_EN_WORD; |
769 | u8 shift = index & 2; | |
770 | ||
771 | data &= mask; | |
772 | ||
773 | if (index & 2) { | |
774 | byen <<= shift; | |
775 | mask <<= (shift * 8); | |
776 | data <<= (shift * 8); | |
777 | index &= ~3; | |
778 | } | |
779 | ||
c8826de8 | 780 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 781 | |
c8826de8 | 782 | data |= __le32_to_cpu(tmp) & ~mask; |
783 | tmp = __cpu_to_le32(data); | |
ac718b69 | 784 | |
c8826de8 | 785 | generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); |
ac718b69 | 786 | } |
787 | ||
788 | static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index) | |
789 | { | |
790 | u32 data; | |
c8826de8 | 791 | __le32 tmp; |
ac718b69 | 792 | u8 shift = index & 3; |
793 | ||
794 | index &= ~3; | |
795 | ||
c8826de8 | 796 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 797 | |
c8826de8 | 798 | data = __le32_to_cpu(tmp); |
ac718b69 | 799 | data >>= (shift * 8); |
800 | data &= 0xff; | |
801 | ||
802 | return (u8)data; | |
803 | } | |
804 | ||
805 | static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data) | |
806 | { | |
c8826de8 | 807 | u32 mask = 0xff; |
808 | __le32 tmp; | |
ac718b69 | 809 | u16 byen = BYTE_EN_BYTE; |
810 | u8 shift = index & 3; | |
811 | ||
812 | data &= mask; | |
813 | ||
814 | if (index & 3) { | |
815 | byen <<= shift; | |
816 | mask <<= (shift * 8); | |
817 | data <<= (shift * 8); | |
818 | index &= ~3; | |
819 | } | |
820 | ||
c8826de8 | 821 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 822 | |
c8826de8 | 823 | data |= __le32_to_cpu(tmp) & ~mask; |
824 | tmp = __cpu_to_le32(data); | |
ac718b69 | 825 | |
c8826de8 | 826 | generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); |
ac718b69 | 827 | } |
828 | ||
ac244d3e | 829 | static u16 ocp_reg_read(struct r8152 *tp, u16 addr) |
e3fe0b1a | 830 | { |
831 | u16 ocp_base, ocp_index; | |
832 | ||
833 | ocp_base = addr & 0xf000; | |
834 | if (ocp_base != tp->ocp_base) { | |
835 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); | |
836 | tp->ocp_base = ocp_base; | |
837 | } | |
838 | ||
839 | ocp_index = (addr & 0x0fff) | 0xb000; | |
ac244d3e | 840 | return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index); |
e3fe0b1a | 841 | } |
842 | ||
ac244d3e | 843 | static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) |
ac718b69 | 844 | { |
ac244d3e | 845 | u16 ocp_base, ocp_index; |
ac718b69 | 846 | |
ac244d3e | 847 | ocp_base = addr & 0xf000; |
848 | if (ocp_base != tp->ocp_base) { | |
849 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); | |
850 | tp->ocp_base = ocp_base; | |
ac718b69 | 851 | } |
ac244d3e | 852 | |
853 | ocp_index = (addr & 0x0fff) | 0xb000; | |
854 | ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data); | |
ac718b69 | 855 | } |
856 | ||
ac244d3e | 857 | static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value) |
ac718b69 | 858 | { |
ac244d3e | 859 | ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value); |
860 | } | |
ac718b69 | 861 | |
ac244d3e | 862 | static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr) |
863 | { | |
864 | return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2); | |
ac718b69 | 865 | } |
866 | ||
43779f8d | 867 | static void sram_write(struct r8152 *tp, u16 addr, u16 data) |
868 | { | |
869 | ocp_reg_write(tp, OCP_SRAM_ADDR, addr); | |
870 | ocp_reg_write(tp, OCP_SRAM_DATA, data); | |
871 | } | |
872 | ||
873 | static u16 sram_read(struct r8152 *tp, u16 addr) | |
874 | { | |
875 | ocp_reg_write(tp, OCP_SRAM_ADDR, addr); | |
876 | return ocp_reg_read(tp, OCP_SRAM_DATA); | |
877 | } | |
878 | ||
ac718b69 | 879 | static int read_mii_word(struct net_device *netdev, int phy_id, int reg) |
880 | { | |
881 | struct r8152 *tp = netdev_priv(netdev); | |
9a4be1bd | 882 | int ret; |
ac718b69 | 883 | |
884 | if (phy_id != R8152_PHY_ID) | |
885 | return -EINVAL; | |
886 | ||
9a4be1bd | 887 | ret = usb_autopm_get_interface(tp->intf); |
888 | if (ret < 0) | |
889 | goto out; | |
890 | ||
891 | ret = r8152_mdio_read(tp, reg); | |
892 | ||
893 | usb_autopm_put_interface(tp->intf); | |
894 | ||
895 | out: | |
896 | return ret; | |
ac718b69 | 897 | } |
898 | ||
899 | static | |
900 | void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val) | |
901 | { | |
902 | struct r8152 *tp = netdev_priv(netdev); | |
903 | ||
904 | if (phy_id != R8152_PHY_ID) | |
905 | return; | |
906 | ||
9a4be1bd | 907 | if (usb_autopm_get_interface(tp->intf) < 0) |
908 | return; | |
909 | ||
ac718b69 | 910 | r8152_mdio_write(tp, reg, val); |
9a4be1bd | 911 | |
912 | usb_autopm_put_interface(tp->intf); | |
ac718b69 | 913 | } |
914 | ||
ebc2ec48 | 915 | static |
916 | int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags); | |
917 | ||
ac718b69 | 918 | static inline void set_ethernet_addr(struct r8152 *tp) |
919 | { | |
920 | struct net_device *dev = tp->netdev; | |
8a91c824 | 921 | int ret; |
31787f53 | 922 | u8 node_id[8] = {0}; |
ac718b69 | 923 | |
8a91c824 | 924 | if (tp->version == RTL_VER_01) |
925 | ret = pla_ocp_read(tp, PLA_IDR, sizeof(node_id), node_id); | |
926 | else | |
927 | ret = pla_ocp_read(tp, PLA_BACKUP, sizeof(node_id), node_id); | |
928 | ||
929 | if (ret < 0) { | |
ac718b69 | 930 | netif_notice(tp, probe, dev, "inet addr fail\n"); |
8a91c824 | 931 | } else { |
932 | if (tp->version != RTL_VER_01) { | |
933 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, | |
934 | CRWECR_CONFIG); | |
935 | pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, | |
936 | sizeof(node_id), node_id); | |
937 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, | |
938 | CRWECR_NORAML); | |
939 | } | |
940 | ||
ac718b69 | 941 | memcpy(dev->dev_addr, node_id, dev->addr_len); |
942 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); | |
943 | } | |
ac718b69 | 944 | } |
945 | ||
946 | static int rtl8152_set_mac_address(struct net_device *netdev, void *p) | |
947 | { | |
948 | struct r8152 *tp = netdev_priv(netdev); | |
949 | struct sockaddr *addr = p; | |
950 | ||
951 | if (!is_valid_ether_addr(addr->sa_data)) | |
952 | return -EADDRNOTAVAIL; | |
953 | ||
954 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); | |
955 | ||
956 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
957 | pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data); | |
958 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
959 | ||
960 | return 0; | |
961 | } | |
962 | ||
ac718b69 | 963 | static struct net_device_stats *rtl8152_get_stats(struct net_device *dev) |
964 | { | |
965 | return &dev->stats; | |
966 | } | |
967 | ||
968 | static void read_bulk_callback(struct urb *urb) | |
969 | { | |
ac718b69 | 970 | struct net_device *netdev; |
a5a4f468 | 971 | unsigned long flags; |
ac718b69 | 972 | int status = urb->status; |
ebc2ec48 | 973 | struct rx_agg *agg; |
974 | struct r8152 *tp; | |
ac718b69 | 975 | int result; |
ac718b69 | 976 | |
ebc2ec48 | 977 | agg = urb->context; |
978 | if (!agg) | |
979 | return; | |
980 | ||
981 | tp = agg->context; | |
ac718b69 | 982 | if (!tp) |
983 | return; | |
ebc2ec48 | 984 | |
ac718b69 | 985 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
986 | return; | |
ebc2ec48 | 987 | |
988 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
989 | return; | |
990 | ||
ac718b69 | 991 | netdev = tp->netdev; |
7559fb2f | 992 | |
993 | /* When link down, the driver would cancel all bulks. */ | |
994 | /* This avoid the re-submitting bulk */ | |
ebc2ec48 | 995 | if (!netif_carrier_ok(netdev)) |
ac718b69 | 996 | return; |
997 | ||
9a4be1bd | 998 | usb_mark_last_busy(tp->udev); |
999 | ||
ac718b69 | 1000 | switch (status) { |
1001 | case 0: | |
ebc2ec48 | 1002 | if (urb->actual_length < ETH_ZLEN) |
1003 | break; | |
1004 | ||
a5a4f468 | 1005 | spin_lock_irqsave(&tp->rx_lock, flags); |
ebc2ec48 | 1006 | list_add_tail(&agg->list, &tp->rx_done); |
a5a4f468 | 1007 | spin_unlock_irqrestore(&tp->rx_lock, flags); |
ebc2ec48 | 1008 | tasklet_schedule(&tp->tl); |
1009 | return; | |
ac718b69 | 1010 | case -ESHUTDOWN: |
1011 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
1012 | netif_device_detach(tp->netdev); | |
ebc2ec48 | 1013 | return; |
ac718b69 | 1014 | case -ENOENT: |
1015 | return; /* the urb is in unlink state */ | |
1016 | case -ETIME: | |
4a8deae2 HW |
1017 | if (net_ratelimit()) |
1018 | netdev_warn(netdev, "maybe reset is needed?\n"); | |
ebc2ec48 | 1019 | break; |
ac718b69 | 1020 | default: |
4a8deae2 HW |
1021 | if (net_ratelimit()) |
1022 | netdev_warn(netdev, "Rx status %d\n", status); | |
ebc2ec48 | 1023 | break; |
ac718b69 | 1024 | } |
1025 | ||
ebc2ec48 | 1026 | result = r8152_submit_rx(tp, agg, GFP_ATOMIC); |
ac718b69 | 1027 | if (result == -ENODEV) { |
1028 | netif_device_detach(tp->netdev); | |
1029 | } else if (result) { | |
a5a4f468 | 1030 | spin_lock_irqsave(&tp->rx_lock, flags); |
ebc2ec48 | 1031 | list_add_tail(&agg->list, &tp->rx_done); |
a5a4f468 | 1032 | spin_unlock_irqrestore(&tp->rx_lock, flags); |
ebc2ec48 | 1033 | tasklet_schedule(&tp->tl); |
ac718b69 | 1034 | } |
ac718b69 | 1035 | } |
1036 | ||
ebc2ec48 | 1037 | static void write_bulk_callback(struct urb *urb) |
ac718b69 | 1038 | { |
ebc2ec48 | 1039 | struct net_device_stats *stats; |
d104eafa | 1040 | struct net_device *netdev; |
a5a4f468 | 1041 | unsigned long flags; |
ebc2ec48 | 1042 | struct tx_agg *agg; |
ac718b69 | 1043 | struct r8152 *tp; |
ebc2ec48 | 1044 | int status = urb->status; |
ac718b69 | 1045 | |
ebc2ec48 | 1046 | agg = urb->context; |
1047 | if (!agg) | |
ac718b69 | 1048 | return; |
1049 | ||
ebc2ec48 | 1050 | tp = agg->context; |
1051 | if (!tp) | |
1052 | return; | |
1053 | ||
d104eafa | 1054 | netdev = tp->netdev; |
1055 | stats = rtl8152_get_stats(netdev); | |
ebc2ec48 | 1056 | if (status) { |
4a8deae2 | 1057 | if (net_ratelimit()) |
d104eafa | 1058 | netdev_warn(netdev, "Tx status %d\n", status); |
ebc2ec48 | 1059 | stats->tx_errors += agg->skb_num; |
ac718b69 | 1060 | } else { |
ebc2ec48 | 1061 | stats->tx_packets += agg->skb_num; |
1062 | stats->tx_bytes += agg->skb_len; | |
ac718b69 | 1063 | } |
1064 | ||
a5a4f468 | 1065 | spin_lock_irqsave(&tp->tx_lock, flags); |
ebc2ec48 | 1066 | list_add_tail(&agg->list, &tp->tx_free); |
a5a4f468 | 1067 | spin_unlock_irqrestore(&tp->tx_lock, flags); |
ebc2ec48 | 1068 | |
9a4be1bd | 1069 | usb_autopm_put_interface_async(tp->intf); |
1070 | ||
d104eafa | 1071 | if (!netif_carrier_ok(netdev)) |
ebc2ec48 | 1072 | return; |
1073 | ||
1074 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
1075 | return; | |
1076 | ||
1077 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
1078 | return; | |
1079 | ||
1080 | if (!skb_queue_empty(&tp->tx_queue)) | |
9a4be1bd | 1081 | schedule_delayed_work(&tp->schedule, 0); |
ac718b69 | 1082 | } |
1083 | ||
40a82917 | 1084 | static void intr_callback(struct urb *urb) |
1085 | { | |
1086 | struct r8152 *tp; | |
500b6d7e | 1087 | __le16 *d; |
40a82917 | 1088 | int status = urb->status; |
1089 | int res; | |
1090 | ||
1091 | tp = urb->context; | |
1092 | if (!tp) | |
1093 | return; | |
1094 | ||
1095 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
1096 | return; | |
1097 | ||
1098 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
1099 | return; | |
1100 | ||
1101 | switch (status) { | |
1102 | case 0: /* success */ | |
1103 | break; | |
1104 | case -ECONNRESET: /* unlink */ | |
1105 | case -ESHUTDOWN: | |
1106 | netif_device_detach(tp->netdev); | |
1107 | case -ENOENT: | |
1108 | return; | |
1109 | case -EOVERFLOW: | |
1110 | netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n"); | |
1111 | goto resubmit; | |
1112 | /* -EPIPE: should clear the halt */ | |
1113 | default: | |
1114 | netif_info(tp, intr, tp->netdev, "intr status %d\n", status); | |
1115 | goto resubmit; | |
1116 | } | |
1117 | ||
1118 | d = urb->transfer_buffer; | |
1119 | if (INTR_LINK & __le16_to_cpu(d[0])) { | |
1120 | if (!(tp->speed & LINK_STATUS)) { | |
1121 | set_bit(RTL8152_LINK_CHG, &tp->flags); | |
1122 | schedule_delayed_work(&tp->schedule, 0); | |
1123 | } | |
1124 | } else { | |
1125 | if (tp->speed & LINK_STATUS) { | |
1126 | set_bit(RTL8152_LINK_CHG, &tp->flags); | |
1127 | schedule_delayed_work(&tp->schedule, 0); | |
1128 | } | |
1129 | } | |
1130 | ||
1131 | resubmit: | |
1132 | res = usb_submit_urb(urb, GFP_ATOMIC); | |
1133 | if (res == -ENODEV) | |
1134 | netif_device_detach(tp->netdev); | |
1135 | else if (res) | |
1136 | netif_err(tp, intr, tp->netdev, | |
4a8deae2 | 1137 | "can't resubmit intr, status %d\n", res); |
40a82917 | 1138 | } |
1139 | ||
ebc2ec48 | 1140 | static inline void *rx_agg_align(void *data) |
1141 | { | |
8e1f51bd | 1142 | return (void *)ALIGN((uintptr_t)data, RX_ALIGN); |
ebc2ec48 | 1143 | } |
1144 | ||
1145 | static inline void *tx_agg_align(void *data) | |
1146 | { | |
8e1f51bd | 1147 | return (void *)ALIGN((uintptr_t)data, TX_ALIGN); |
ebc2ec48 | 1148 | } |
1149 | ||
1150 | static void free_all_mem(struct r8152 *tp) | |
1151 | { | |
1152 | int i; | |
1153 | ||
1154 | for (i = 0; i < RTL8152_MAX_RX; i++) { | |
9629e3c0 | 1155 | usb_free_urb(tp->rx_info[i].urb); |
1156 | tp->rx_info[i].urb = NULL; | |
ebc2ec48 | 1157 | |
9629e3c0 | 1158 | kfree(tp->rx_info[i].buffer); |
1159 | tp->rx_info[i].buffer = NULL; | |
1160 | tp->rx_info[i].head = NULL; | |
ebc2ec48 | 1161 | } |
1162 | ||
1163 | for (i = 0; i < RTL8152_MAX_TX; i++) { | |
9629e3c0 | 1164 | usb_free_urb(tp->tx_info[i].urb); |
1165 | tp->tx_info[i].urb = NULL; | |
ebc2ec48 | 1166 | |
9629e3c0 | 1167 | kfree(tp->tx_info[i].buffer); |
1168 | tp->tx_info[i].buffer = NULL; | |
1169 | tp->tx_info[i].head = NULL; | |
ebc2ec48 | 1170 | } |
40a82917 | 1171 | |
9629e3c0 | 1172 | usb_free_urb(tp->intr_urb); |
1173 | tp->intr_urb = NULL; | |
40a82917 | 1174 | |
9629e3c0 | 1175 | kfree(tp->intr_buff); |
1176 | tp->intr_buff = NULL; | |
ebc2ec48 | 1177 | } |
1178 | ||
1179 | static int alloc_all_mem(struct r8152 *tp) | |
1180 | { | |
1181 | struct net_device *netdev = tp->netdev; | |
40a82917 | 1182 | struct usb_interface *intf = tp->intf; |
1183 | struct usb_host_interface *alt = intf->cur_altsetting; | |
1184 | struct usb_host_endpoint *ep_intr = alt->endpoint + 2; | |
ebc2ec48 | 1185 | struct urb *urb; |
1186 | int node, i; | |
1187 | u8 *buf; | |
1188 | ||
1189 | node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; | |
1190 | ||
1191 | spin_lock_init(&tp->rx_lock); | |
1192 | spin_lock_init(&tp->tx_lock); | |
1193 | INIT_LIST_HEAD(&tp->rx_done); | |
1194 | INIT_LIST_HEAD(&tp->tx_free); | |
1195 | skb_queue_head_init(&tp->tx_queue); | |
1196 | ||
1197 | for (i = 0; i < RTL8152_MAX_RX; i++) { | |
1198 | buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node); | |
1199 | if (!buf) | |
1200 | goto err1; | |
1201 | ||
1202 | if (buf != rx_agg_align(buf)) { | |
1203 | kfree(buf); | |
8e1f51bd | 1204 | buf = kmalloc_node(rx_buf_sz + RX_ALIGN, GFP_KERNEL, |
1205 | node); | |
ebc2ec48 | 1206 | if (!buf) |
1207 | goto err1; | |
1208 | } | |
1209 | ||
1210 | urb = usb_alloc_urb(0, GFP_KERNEL); | |
1211 | if (!urb) { | |
1212 | kfree(buf); | |
1213 | goto err1; | |
1214 | } | |
1215 | ||
1216 | INIT_LIST_HEAD(&tp->rx_info[i].list); | |
1217 | tp->rx_info[i].context = tp; | |
1218 | tp->rx_info[i].urb = urb; | |
1219 | tp->rx_info[i].buffer = buf; | |
1220 | tp->rx_info[i].head = rx_agg_align(buf); | |
1221 | } | |
1222 | ||
1223 | for (i = 0; i < RTL8152_MAX_TX; i++) { | |
1224 | buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node); | |
1225 | if (!buf) | |
1226 | goto err1; | |
1227 | ||
1228 | if (buf != tx_agg_align(buf)) { | |
1229 | kfree(buf); | |
8e1f51bd | 1230 | buf = kmalloc_node(rx_buf_sz + TX_ALIGN, GFP_KERNEL, |
1231 | node); | |
ebc2ec48 | 1232 | if (!buf) |
1233 | goto err1; | |
1234 | } | |
1235 | ||
1236 | urb = usb_alloc_urb(0, GFP_KERNEL); | |
1237 | if (!urb) { | |
1238 | kfree(buf); | |
1239 | goto err1; | |
1240 | } | |
1241 | ||
1242 | INIT_LIST_HEAD(&tp->tx_info[i].list); | |
1243 | tp->tx_info[i].context = tp; | |
1244 | tp->tx_info[i].urb = urb; | |
1245 | tp->tx_info[i].buffer = buf; | |
1246 | tp->tx_info[i].head = tx_agg_align(buf); | |
1247 | ||
1248 | list_add_tail(&tp->tx_info[i].list, &tp->tx_free); | |
1249 | } | |
1250 | ||
40a82917 | 1251 | tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL); |
1252 | if (!tp->intr_urb) | |
1253 | goto err1; | |
1254 | ||
1255 | tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL); | |
1256 | if (!tp->intr_buff) | |
1257 | goto err1; | |
1258 | ||
1259 | tp->intr_interval = (int)ep_intr->desc.bInterval; | |
1260 | usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3), | |
1261 | tp->intr_buff, INTBUFSIZE, intr_callback, | |
1262 | tp, tp->intr_interval); | |
1263 | ||
ebc2ec48 | 1264 | return 0; |
1265 | ||
1266 | err1: | |
1267 | free_all_mem(tp); | |
1268 | return -ENOMEM; | |
1269 | } | |
1270 | ||
0de98f6c | 1271 | static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp) |
1272 | { | |
1273 | struct tx_agg *agg = NULL; | |
1274 | unsigned long flags; | |
1275 | ||
1276 | spin_lock_irqsave(&tp->tx_lock, flags); | |
1277 | if (!list_empty(&tp->tx_free)) { | |
1278 | struct list_head *cursor; | |
1279 | ||
1280 | cursor = tp->tx_free.next; | |
1281 | list_del_init(cursor); | |
1282 | agg = list_entry(cursor, struct tx_agg, list); | |
1283 | } | |
1284 | spin_unlock_irqrestore(&tp->tx_lock, flags); | |
1285 | ||
1286 | return agg; | |
1287 | } | |
1288 | ||
5bd23881 | 1289 | static void |
1290 | r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, struct sk_buff *skb) | |
1291 | { | |
1292 | memset(desc, 0, sizeof(*desc)); | |
1293 | ||
1294 | desc->opts1 = cpu_to_le32((skb->len & TX_LEN_MASK) | TX_FS | TX_LS); | |
1295 | ||
1296 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
1297 | __be16 protocol; | |
1298 | u8 ip_protocol; | |
1299 | u32 opts2 = 0; | |
1300 | ||
1301 | if (skb->protocol == htons(ETH_P_8021Q)) | |
1302 | protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto; | |
1303 | else | |
1304 | protocol = skb->protocol; | |
1305 | ||
1306 | switch (protocol) { | |
1307 | case htons(ETH_P_IP): | |
1308 | opts2 |= IPV4_CS; | |
1309 | ip_protocol = ip_hdr(skb)->protocol; | |
1310 | break; | |
1311 | ||
1312 | case htons(ETH_P_IPV6): | |
1313 | opts2 |= IPV6_CS; | |
1314 | ip_protocol = ipv6_hdr(skb)->nexthdr; | |
1315 | break; | |
1316 | ||
1317 | default: | |
1318 | ip_protocol = IPPROTO_RAW; | |
1319 | break; | |
1320 | } | |
1321 | ||
1322 | if (ip_protocol == IPPROTO_TCP) { | |
1323 | opts2 |= TCP_CS; | |
1324 | opts2 |= (skb_transport_offset(skb) & 0x7fff) << 17; | |
1325 | } else if (ip_protocol == IPPROTO_UDP) { | |
1326 | opts2 |= UDP_CS; | |
1327 | } else { | |
1328 | WARN_ON_ONCE(1); | |
1329 | } | |
1330 | ||
1331 | desc->opts2 = cpu_to_le32(opts2); | |
1332 | } | |
1333 | } | |
1334 | ||
b1379d9a | 1335 | static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg) |
1336 | { | |
d84130a1 | 1337 | struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; |
1338 | unsigned long flags; | |
9a4be1bd | 1339 | int remain, ret; |
b1379d9a | 1340 | u8 *tx_data; |
1341 | ||
d84130a1 | 1342 | __skb_queue_head_init(&skb_head); |
1343 | spin_lock_irqsave(&tx_queue->lock, flags); | |
1344 | skb_queue_splice_init(tx_queue, &skb_head); | |
1345 | spin_unlock_irqrestore(&tx_queue->lock, flags); | |
1346 | ||
b1379d9a | 1347 | tx_data = agg->head; |
1348 | agg->skb_num = agg->skb_len = 0; | |
7937f9e5 | 1349 | remain = rx_buf_sz; |
b1379d9a | 1350 | |
7937f9e5 | 1351 | while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) { |
b1379d9a | 1352 | struct tx_desc *tx_desc; |
1353 | struct sk_buff *skb; | |
1354 | unsigned int len; | |
1355 | ||
d84130a1 | 1356 | skb = __skb_dequeue(&skb_head); |
b1379d9a | 1357 | if (!skb) |
1358 | break; | |
1359 | ||
7937f9e5 | 1360 | remain -= sizeof(*tx_desc); |
b1379d9a | 1361 | len = skb->len; |
1362 | if (remain < len) { | |
d84130a1 | 1363 | __skb_queue_head(&skb_head, skb); |
b1379d9a | 1364 | break; |
1365 | } | |
1366 | ||
7937f9e5 | 1367 | tx_data = tx_agg_align(tx_data); |
b1379d9a | 1368 | tx_desc = (struct tx_desc *)tx_data; |
1369 | tx_data += sizeof(*tx_desc); | |
1370 | ||
1371 | r8152_tx_csum(tp, tx_desc, skb); | |
1372 | memcpy(tx_data, skb->data, len); | |
1373 | agg->skb_num++; | |
1374 | agg->skb_len += len; | |
1375 | dev_kfree_skb_any(skb); | |
1376 | ||
7937f9e5 | 1377 | tx_data += len; |
1378 | remain = rx_buf_sz - (int)(tx_agg_align(tx_data) - agg->head); | |
b1379d9a | 1379 | } |
1380 | ||
d84130a1 | 1381 | if (!skb_queue_empty(&skb_head)) { |
1382 | spin_lock_irqsave(&tx_queue->lock, flags); | |
1383 | skb_queue_splice(&skb_head, tx_queue); | |
1384 | spin_unlock_irqrestore(&tx_queue->lock, flags); | |
1385 | } | |
1386 | ||
9a4be1bd | 1387 | netif_tx_lock_bh(tp->netdev); |
dd1b119c | 1388 | |
1389 | if (netif_queue_stopped(tp->netdev) && | |
1390 | skb_queue_len(&tp->tx_queue) < tp->tx_qlen) | |
1391 | netif_wake_queue(tp->netdev); | |
1392 | ||
9a4be1bd | 1393 | netif_tx_unlock_bh(tp->netdev); |
1394 | ||
1395 | ret = usb_autopm_get_interface(tp->intf); | |
1396 | if (ret < 0) | |
1397 | goto out_tx_fill; | |
dd1b119c | 1398 | |
b1379d9a | 1399 | usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2), |
1400 | agg->head, (int)(tx_data - (u8 *)agg->head), | |
1401 | (usb_complete_t)write_bulk_callback, agg); | |
1402 | ||
9a4be1bd | 1403 | ret = usb_submit_urb(agg->urb, GFP_KERNEL); |
1404 | if (ret < 0) | |
1405 | usb_autopm_put_interface(tp->intf); | |
1406 | ||
1407 | out_tx_fill: | |
1408 | return ret; | |
b1379d9a | 1409 | } |
1410 | ||
ebc2ec48 | 1411 | static void rx_bottom(struct r8152 *tp) |
1412 | { | |
a5a4f468 | 1413 | unsigned long flags; |
d84130a1 | 1414 | struct list_head *cursor, *next, rx_queue; |
ebc2ec48 | 1415 | |
d84130a1 | 1416 | if (list_empty(&tp->rx_done)) |
1417 | return; | |
1418 | ||
1419 | INIT_LIST_HEAD(&rx_queue); | |
a5a4f468 | 1420 | spin_lock_irqsave(&tp->rx_lock, flags); |
d84130a1 | 1421 | list_splice_init(&tp->rx_done, &rx_queue); |
1422 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
1423 | ||
1424 | list_for_each_safe(cursor, next, &rx_queue) { | |
43a4478d | 1425 | struct rx_desc *rx_desc; |
1426 | struct rx_agg *agg; | |
43a4478d | 1427 | int len_used = 0; |
1428 | struct urb *urb; | |
1429 | u8 *rx_data; | |
1430 | int ret; | |
1431 | ||
ebc2ec48 | 1432 | list_del_init(cursor); |
ebc2ec48 | 1433 | |
1434 | agg = list_entry(cursor, struct rx_agg, list); | |
1435 | urb = agg->urb; | |
0de98f6c | 1436 | if (urb->actual_length < ETH_ZLEN) |
1437 | goto submit; | |
ebc2ec48 | 1438 | |
ebc2ec48 | 1439 | rx_desc = agg->head; |
1440 | rx_data = agg->head; | |
7937f9e5 | 1441 | len_used += sizeof(struct rx_desc); |
ebc2ec48 | 1442 | |
7937f9e5 | 1443 | while (urb->actual_length > len_used) { |
43a4478d | 1444 | struct net_device *netdev = tp->netdev; |
1445 | struct net_device_stats *stats; | |
7937f9e5 | 1446 | unsigned int pkt_len; |
43a4478d | 1447 | struct sk_buff *skb; |
1448 | ||
7937f9e5 | 1449 | pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; |
ebc2ec48 | 1450 | if (pkt_len < ETH_ZLEN) |
1451 | break; | |
1452 | ||
7937f9e5 | 1453 | len_used += pkt_len; |
1454 | if (urb->actual_length < len_used) | |
1455 | break; | |
1456 | ||
43a4478d | 1457 | stats = rtl8152_get_stats(netdev); |
1458 | ||
8e1f51bd | 1459 | pkt_len -= CRC_SIZE; |
ebc2ec48 | 1460 | rx_data += sizeof(struct rx_desc); |
1461 | ||
1462 | skb = netdev_alloc_skb_ip_align(netdev, pkt_len); | |
1463 | if (!skb) { | |
1464 | stats->rx_dropped++; | |
1465 | break; | |
1466 | } | |
1467 | memcpy(skb->data, rx_data, pkt_len); | |
1468 | skb_put(skb, pkt_len); | |
1469 | skb->protocol = eth_type_trans(skb, netdev); | |
9d9aafa1 | 1470 | netif_receive_skb(skb); |
ebc2ec48 | 1471 | stats->rx_packets++; |
1472 | stats->rx_bytes += pkt_len; | |
1473 | ||
8e1f51bd | 1474 | rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE); |
ebc2ec48 | 1475 | rx_desc = (struct rx_desc *)rx_data; |
ebc2ec48 | 1476 | len_used = (int)(rx_data - (u8 *)agg->head); |
7937f9e5 | 1477 | len_used += sizeof(struct rx_desc); |
ebc2ec48 | 1478 | } |
1479 | ||
0de98f6c | 1480 | submit: |
ebc2ec48 | 1481 | ret = r8152_submit_rx(tp, agg, GFP_ATOMIC); |
ebc2ec48 | 1482 | if (ret && ret != -ENODEV) { |
d84130a1 | 1483 | spin_lock_irqsave(&tp->rx_lock, flags); |
1484 | list_add_tail(&agg->list, &tp->rx_done); | |
1485 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
ebc2ec48 | 1486 | tasklet_schedule(&tp->tl); |
1487 | } | |
1488 | } | |
ebc2ec48 | 1489 | } |
1490 | ||
1491 | static void tx_bottom(struct r8152 *tp) | |
1492 | { | |
ebc2ec48 | 1493 | int res; |
1494 | ||
b1379d9a | 1495 | do { |
1496 | struct tx_agg *agg; | |
ebc2ec48 | 1497 | |
b1379d9a | 1498 | if (skb_queue_empty(&tp->tx_queue)) |
ebc2ec48 | 1499 | break; |
1500 | ||
b1379d9a | 1501 | agg = r8152_get_tx_agg(tp); |
1502 | if (!agg) | |
ebc2ec48 | 1503 | break; |
ebc2ec48 | 1504 | |
b1379d9a | 1505 | res = r8152_tx_agg_fill(tp, agg); |
1506 | if (res) { | |
1507 | struct net_device_stats *stats; | |
1508 | struct net_device *netdev; | |
1509 | unsigned long flags; | |
ebc2ec48 | 1510 | |
b1379d9a | 1511 | netdev = tp->netdev; |
1512 | stats = rtl8152_get_stats(netdev); | |
ebc2ec48 | 1513 | |
b1379d9a | 1514 | if (res == -ENODEV) { |
1515 | netif_device_detach(netdev); | |
1516 | } else { | |
1517 | netif_warn(tp, tx_err, netdev, | |
1518 | "failed tx_urb %d\n", res); | |
1519 | stats->tx_dropped += agg->skb_num; | |
db8515ef | 1520 | |
b1379d9a | 1521 | spin_lock_irqsave(&tp->tx_lock, flags); |
1522 | list_add_tail(&agg->list, &tp->tx_free); | |
1523 | spin_unlock_irqrestore(&tp->tx_lock, flags); | |
1524 | } | |
ebc2ec48 | 1525 | } |
b1379d9a | 1526 | } while (res == 0); |
ebc2ec48 | 1527 | } |
1528 | ||
1529 | static void bottom_half(unsigned long data) | |
ac718b69 | 1530 | { |
1531 | struct r8152 *tp; | |
ac718b69 | 1532 | |
ebc2ec48 | 1533 | tp = (struct r8152 *)data; |
1534 | ||
1535 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
1536 | return; | |
1537 | ||
1538 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
ac718b69 | 1539 | return; |
ebc2ec48 | 1540 | |
7559fb2f | 1541 | /* When link down, the driver would cancel all bulks. */ |
1542 | /* This avoid the re-submitting bulk */ | |
ebc2ec48 | 1543 | if (!netif_carrier_ok(tp->netdev)) |
ac718b69 | 1544 | return; |
ebc2ec48 | 1545 | |
1546 | rx_bottom(tp); | |
ebc2ec48 | 1547 | } |
1548 | ||
1549 | static | |
1550 | int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags) | |
1551 | { | |
1552 | usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1), | |
1553 | agg->head, rx_buf_sz, | |
1554 | (usb_complete_t)read_bulk_callback, agg); | |
1555 | ||
1556 | return usb_submit_urb(agg->urb, mem_flags); | |
ac718b69 | 1557 | } |
1558 | ||
00a5e360 | 1559 | static void rtl_drop_queued_tx(struct r8152 *tp) |
1560 | { | |
1561 | struct net_device_stats *stats = &tp->netdev->stats; | |
d84130a1 | 1562 | struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; |
1563 | unsigned long flags; | |
00a5e360 | 1564 | struct sk_buff *skb; |
1565 | ||
d84130a1 | 1566 | if (skb_queue_empty(tx_queue)) |
1567 | return; | |
1568 | ||
1569 | __skb_queue_head_init(&skb_head); | |
1570 | spin_lock_irqsave(&tx_queue->lock, flags); | |
1571 | skb_queue_splice_init(tx_queue, &skb_head); | |
1572 | spin_unlock_irqrestore(&tx_queue->lock, flags); | |
1573 | ||
1574 | while ((skb = __skb_dequeue(&skb_head))) { | |
00a5e360 | 1575 | dev_kfree_skb(skb); |
1576 | stats->tx_dropped++; | |
1577 | } | |
1578 | } | |
1579 | ||
ac718b69 | 1580 | static void rtl8152_tx_timeout(struct net_device *netdev) |
1581 | { | |
1582 | struct r8152 *tp = netdev_priv(netdev); | |
ebc2ec48 | 1583 | int i; |
1584 | ||
4a8deae2 | 1585 | netif_warn(tp, tx_err, netdev, "Tx timeout\n"); |
ebc2ec48 | 1586 | for (i = 0; i < RTL8152_MAX_TX; i++) |
1587 | usb_unlink_urb(tp->tx_info[i].urb); | |
ac718b69 | 1588 | } |
1589 | ||
1590 | static void rtl8152_set_rx_mode(struct net_device *netdev) | |
1591 | { | |
1592 | struct r8152 *tp = netdev_priv(netdev); | |
1593 | ||
40a82917 | 1594 | if (tp->speed & LINK_STATUS) { |
ac718b69 | 1595 | set_bit(RTL8152_SET_RX_MODE, &tp->flags); |
40a82917 | 1596 | schedule_delayed_work(&tp->schedule, 0); |
1597 | } | |
ac718b69 | 1598 | } |
1599 | ||
1600 | static void _rtl8152_set_rx_mode(struct net_device *netdev) | |
1601 | { | |
1602 | struct r8152 *tp = netdev_priv(netdev); | |
31787f53 | 1603 | u32 mc_filter[2]; /* Multicast hash filter */ |
1604 | __le32 tmp[2]; | |
ac718b69 | 1605 | u32 ocp_data; |
1606 | ||
ac718b69 | 1607 | clear_bit(RTL8152_SET_RX_MODE, &tp->flags); |
1608 | netif_stop_queue(netdev); | |
1609 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
1610 | ocp_data &= ~RCR_ACPT_ALL; | |
1611 | ocp_data |= RCR_AB | RCR_APM; | |
1612 | ||
1613 | if (netdev->flags & IFF_PROMISC) { | |
1614 | /* Unconditionally log net taps. */ | |
1615 | netif_notice(tp, link, netdev, "Promiscuous mode enabled\n"); | |
1616 | ocp_data |= RCR_AM | RCR_AAP; | |
1617 | mc_filter[1] = mc_filter[0] = 0xffffffff; | |
1618 | } else if ((netdev_mc_count(netdev) > multicast_filter_limit) || | |
1619 | (netdev->flags & IFF_ALLMULTI)) { | |
1620 | /* Too many to filter perfectly -- accept all multicasts. */ | |
1621 | ocp_data |= RCR_AM; | |
1622 | mc_filter[1] = mc_filter[0] = 0xffffffff; | |
1623 | } else { | |
1624 | struct netdev_hw_addr *ha; | |
1625 | ||
1626 | mc_filter[1] = mc_filter[0] = 0; | |
1627 | netdev_for_each_mc_addr(ha, netdev) { | |
1628 | int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; | |
1629 | mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); | |
1630 | ocp_data |= RCR_AM; | |
1631 | } | |
1632 | } | |
1633 | ||
31787f53 | 1634 | tmp[0] = __cpu_to_le32(swab32(mc_filter[1])); |
1635 | tmp[1] = __cpu_to_le32(swab32(mc_filter[0])); | |
ac718b69 | 1636 | |
31787f53 | 1637 | pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp); |
ac718b69 | 1638 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); |
1639 | netif_wake_queue(netdev); | |
ac718b69 | 1640 | } |
1641 | ||
1642 | static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb, | |
1643 | struct net_device *netdev) | |
1644 | { | |
1645 | struct r8152 *tp = netdev_priv(netdev); | |
ac718b69 | 1646 | |
ebc2ec48 | 1647 | skb_tx_timestamp(skb); |
ac718b69 | 1648 | |
61598788 | 1649 | skb_queue_tail(&tp->tx_queue, skb); |
ebc2ec48 | 1650 | |
dd1b119c | 1651 | if (list_empty(&tp->tx_free) && |
1652 | skb_queue_len(&tp->tx_queue) > tp->tx_qlen) | |
1653 | netif_stop_queue(netdev); | |
1654 | ||
61598788 | 1655 | if (!list_empty(&tp->tx_free)) |
9a4be1bd | 1656 | schedule_delayed_work(&tp->schedule, 0); |
ac718b69 | 1657 | |
1658 | return NETDEV_TX_OK; | |
1659 | } | |
1660 | ||
1661 | static void r8152b_reset_packet_filter(struct r8152 *tp) | |
1662 | { | |
1663 | u32 ocp_data; | |
1664 | ||
1665 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); | |
1666 | ocp_data &= ~FMC_FCR_MCU_EN; | |
1667 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); | |
1668 | ocp_data |= FMC_FCR_MCU_EN; | |
1669 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); | |
1670 | } | |
1671 | ||
1672 | static void rtl8152_nic_reset(struct r8152 *tp) | |
1673 | { | |
1674 | int i; | |
1675 | ||
1676 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST); | |
1677 | ||
1678 | for (i = 0; i < 1000; i++) { | |
1679 | if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST)) | |
1680 | break; | |
1681 | udelay(100); | |
1682 | } | |
1683 | } | |
1684 | ||
dd1b119c | 1685 | static void set_tx_qlen(struct r8152 *tp) |
1686 | { | |
1687 | struct net_device *netdev = tp->netdev; | |
1688 | ||
1689 | tp->tx_qlen = rx_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN + | |
1690 | sizeof(struct tx_desc)); | |
1691 | } | |
1692 | ||
ac718b69 | 1693 | static inline u8 rtl8152_get_speed(struct r8152 *tp) |
1694 | { | |
1695 | return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); | |
1696 | } | |
1697 | ||
507605a8 | 1698 | static void rtl_set_eee_plus(struct r8152 *tp) |
ac718b69 | 1699 | { |
ebc2ec48 | 1700 | u32 ocp_data; |
ac718b69 | 1701 | u8 speed; |
1702 | ||
1703 | speed = rtl8152_get_speed(tp); | |
ebc2ec48 | 1704 | if (speed & _10bps) { |
ac718b69 | 1705 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); |
ebc2ec48 | 1706 | ocp_data |= EEEP_CR_EEEP_TX; |
ac718b69 | 1707 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); |
1708 | } else { | |
1709 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); | |
ebc2ec48 | 1710 | ocp_data &= ~EEEP_CR_EEEP_TX; |
ac718b69 | 1711 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); |
1712 | } | |
507605a8 | 1713 | } |
1714 | ||
00a5e360 | 1715 | static void rxdy_gated_en(struct r8152 *tp, bool enable) |
1716 | { | |
1717 | u32 ocp_data; | |
1718 | ||
1719 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); | |
1720 | if (enable) | |
1721 | ocp_data |= RXDY_GATED_EN; | |
1722 | else | |
1723 | ocp_data &= ~RXDY_GATED_EN; | |
1724 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); | |
1725 | } | |
1726 | ||
507605a8 | 1727 | static int rtl_enable(struct r8152 *tp) |
1728 | { | |
1729 | u32 ocp_data; | |
1730 | int i, ret; | |
ac718b69 | 1731 | |
1732 | r8152b_reset_packet_filter(tp); | |
1733 | ||
1734 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); | |
1735 | ocp_data |= CR_RE | CR_TE; | |
1736 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); | |
1737 | ||
00a5e360 | 1738 | rxdy_gated_en(tp, false); |
ac718b69 | 1739 | |
ebc2ec48 | 1740 | INIT_LIST_HEAD(&tp->rx_done); |
1741 | ret = 0; | |
1742 | for (i = 0; i < RTL8152_MAX_RX; i++) { | |
1743 | INIT_LIST_HEAD(&tp->rx_info[i].list); | |
1744 | ret |= r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL); | |
1745 | } | |
ac718b69 | 1746 | |
ebc2ec48 | 1747 | return ret; |
ac718b69 | 1748 | } |
1749 | ||
507605a8 | 1750 | static int rtl8152_enable(struct r8152 *tp) |
1751 | { | |
1752 | set_tx_qlen(tp); | |
1753 | rtl_set_eee_plus(tp); | |
1754 | ||
1755 | return rtl_enable(tp); | |
1756 | } | |
1757 | ||
43779f8d | 1758 | static void r8153_set_rx_agg(struct r8152 *tp) |
1759 | { | |
1760 | u8 speed; | |
1761 | ||
1762 | speed = rtl8152_get_speed(tp); | |
1763 | if (speed & _1000bps) { | |
1764 | if (tp->udev->speed == USB_SPEED_SUPER) { | |
1765 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, | |
1766 | RX_THR_SUPPER); | |
1767 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG, | |
1768 | EARLY_AGG_SUPPER); | |
1769 | } else { | |
1770 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, | |
1771 | RX_THR_HIGH); | |
1772 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG, | |
1773 | EARLY_AGG_HIGH); | |
1774 | } | |
1775 | } else { | |
1776 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_SLOW); | |
1777 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG, | |
1778 | EARLY_AGG_SLOW); | |
1779 | } | |
1780 | } | |
1781 | ||
1782 | static int rtl8153_enable(struct r8152 *tp) | |
1783 | { | |
1784 | set_tx_qlen(tp); | |
1785 | rtl_set_eee_plus(tp); | |
1786 | r8153_set_rx_agg(tp); | |
1787 | ||
1788 | return rtl_enable(tp); | |
1789 | } | |
1790 | ||
ac718b69 | 1791 | static void rtl8152_disable(struct r8152 *tp) |
1792 | { | |
ebc2ec48 | 1793 | u32 ocp_data; |
1794 | int i; | |
ac718b69 | 1795 | |
1796 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
1797 | ocp_data &= ~RCR_ACPT_ALL; | |
1798 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
1799 | ||
00a5e360 | 1800 | rtl_drop_queued_tx(tp); |
ebc2ec48 | 1801 | |
1802 | for (i = 0; i < RTL8152_MAX_TX; i++) | |
1803 | usb_kill_urb(tp->tx_info[i].urb); | |
ac718b69 | 1804 | |
00a5e360 | 1805 | rxdy_gated_en(tp, true); |
ac718b69 | 1806 | |
1807 | for (i = 0; i < 1000; i++) { | |
1808 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
1809 | if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY) | |
1810 | break; | |
1811 | mdelay(1); | |
1812 | } | |
1813 | ||
1814 | for (i = 0; i < 1000; i++) { | |
1815 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY) | |
1816 | break; | |
1817 | mdelay(1); | |
1818 | } | |
1819 | ||
ebc2ec48 | 1820 | for (i = 0; i < RTL8152_MAX_RX; i++) |
1821 | usb_kill_urb(tp->rx_info[i].urb); | |
ac718b69 | 1822 | |
1823 | rtl8152_nic_reset(tp); | |
1824 | } | |
1825 | ||
00a5e360 | 1826 | static void r8152_power_cut_en(struct r8152 *tp, bool enable) |
1827 | { | |
1828 | u32 ocp_data; | |
1829 | ||
1830 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); | |
1831 | if (enable) | |
1832 | ocp_data |= POWER_CUT; | |
1833 | else | |
1834 | ocp_data &= ~POWER_CUT; | |
1835 | ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); | |
1836 | ||
1837 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); | |
1838 | ocp_data &= ~RESUME_INDICATE; | |
1839 | ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); | |
00a5e360 | 1840 | } |
1841 | ||
21ff2e89 | 1842 | #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) |
1843 | ||
1844 | static u32 __rtl_get_wol(struct r8152 *tp) | |
1845 | { | |
1846 | u32 ocp_data; | |
1847 | u32 wolopts = 0; | |
1848 | ||
1849 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5); | |
1850 | if (!(ocp_data & LAN_WAKE_EN)) | |
1851 | return 0; | |
1852 | ||
1853 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); | |
1854 | if (ocp_data & LINK_ON_WAKE_EN) | |
1855 | wolopts |= WAKE_PHY; | |
1856 | ||
1857 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); | |
1858 | if (ocp_data & UWF_EN) | |
1859 | wolopts |= WAKE_UCAST; | |
1860 | if (ocp_data & BWF_EN) | |
1861 | wolopts |= WAKE_BCAST; | |
1862 | if (ocp_data & MWF_EN) | |
1863 | wolopts |= WAKE_MCAST; | |
1864 | ||
1865 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); | |
1866 | if (ocp_data & MAGIC_EN) | |
1867 | wolopts |= WAKE_MAGIC; | |
1868 | ||
1869 | return wolopts; | |
1870 | } | |
1871 | ||
1872 | static void __rtl_set_wol(struct r8152 *tp, u32 wolopts) | |
1873 | { | |
1874 | u32 ocp_data; | |
1875 | ||
1876 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
1877 | ||
1878 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); | |
1879 | ocp_data &= ~LINK_ON_WAKE_EN; | |
1880 | if (wolopts & WAKE_PHY) | |
1881 | ocp_data |= LINK_ON_WAKE_EN; | |
1882 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); | |
1883 | ||
1884 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); | |
1885 | ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN); | |
1886 | if (wolopts & WAKE_UCAST) | |
1887 | ocp_data |= UWF_EN; | |
1888 | if (wolopts & WAKE_BCAST) | |
1889 | ocp_data |= BWF_EN; | |
1890 | if (wolopts & WAKE_MCAST) | |
1891 | ocp_data |= MWF_EN; | |
1892 | if (wolopts & WAKE_ANY) | |
1893 | ocp_data |= LAN_WAKE_EN; | |
1894 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data); | |
1895 | ||
1896 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
1897 | ||
1898 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); | |
1899 | ocp_data &= ~MAGIC_EN; | |
1900 | if (wolopts & WAKE_MAGIC) | |
1901 | ocp_data |= MAGIC_EN; | |
1902 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data); | |
1903 | ||
1904 | if (wolopts & WAKE_ANY) | |
1905 | device_set_wakeup_enable(&tp->udev->dev, true); | |
1906 | else | |
1907 | device_set_wakeup_enable(&tp->udev->dev, false); | |
1908 | } | |
1909 | ||
9a4be1bd | 1910 | static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable) |
1911 | { | |
1912 | if (enable) { | |
1913 | u32 ocp_data; | |
1914 | ||
1915 | __rtl_set_wol(tp, WAKE_ANY); | |
1916 | ||
1917 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
1918 | ||
1919 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); | |
1920 | ocp_data |= LINK_OFF_WAKE_EN; | |
1921 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); | |
1922 | ||
1923 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
1924 | } else { | |
1925 | __rtl_set_wol(tp, tp->saved_wolopts); | |
1926 | } | |
1927 | } | |
1928 | ||
aa66a5f1 | 1929 | static void rtl_phy_reset(struct r8152 *tp) |
1930 | { | |
1931 | u16 data; | |
1932 | int i; | |
1933 | ||
1934 | clear_bit(PHY_RESET, &tp->flags); | |
1935 | ||
1936 | data = r8152_mdio_read(tp, MII_BMCR); | |
1937 | ||
1938 | /* don't reset again before the previous one complete */ | |
1939 | if (data & BMCR_RESET) | |
1940 | return; | |
1941 | ||
1942 | data |= BMCR_RESET; | |
1943 | r8152_mdio_write(tp, MII_BMCR, data); | |
1944 | ||
1945 | for (i = 0; i < 50; i++) { | |
1946 | msleep(20); | |
1947 | if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) | |
1948 | break; | |
1949 | } | |
1950 | } | |
1951 | ||
4349968a | 1952 | static void rtl_clear_bp(struct r8152 *tp) |
1953 | { | |
1954 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_0, 0); | |
1955 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_2, 0); | |
1956 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_4, 0); | |
1957 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_6, 0); | |
1958 | ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_0, 0); | |
1959 | ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_2, 0); | |
1960 | ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_4, 0); | |
1961 | ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_6, 0); | |
1962 | mdelay(3); | |
1963 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_BA, 0); | |
1964 | ocp_write_word(tp, MCU_TYPE_USB, USB_BP_BA, 0); | |
1965 | } | |
1966 | ||
1967 | static void r8153_clear_bp(struct r8152 *tp) | |
1968 | { | |
1969 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_BP_EN, 0); | |
1970 | ocp_write_byte(tp, MCU_TYPE_USB, USB_BP_EN, 0); | |
1971 | rtl_clear_bp(tp); | |
1972 | } | |
1973 | ||
1974 | static void r8153_teredo_off(struct r8152 *tp) | |
1975 | { | |
1976 | u32 ocp_data; | |
1977 | ||
1978 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); | |
1979 | ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN); | |
1980 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); | |
1981 | ||
1982 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE); | |
1983 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0); | |
1984 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0); | |
1985 | } | |
1986 | ||
1987 | static void r8152b_disable_aldps(struct r8152 *tp) | |
1988 | { | |
1989 | ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE); | |
1990 | msleep(20); | |
1991 | } | |
1992 | ||
1993 | static inline void r8152b_enable_aldps(struct r8152 *tp) | |
1994 | { | |
1995 | ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS | | |
1996 | LINKENA | DIS_SDSAVE); | |
1997 | } | |
1998 | ||
1999 | static void r8152b_hw_phy_cfg(struct r8152 *tp) | |
2000 | { | |
f0cbe0ac | 2001 | u16 data; |
2002 | ||
2003 | data = r8152_mdio_read(tp, MII_BMCR); | |
2004 | if (data & BMCR_PDOWN) { | |
2005 | data &= ~BMCR_PDOWN; | |
2006 | r8152_mdio_write(tp, MII_BMCR, data); | |
2007 | } | |
2008 | ||
4349968a | 2009 | r8152b_disable_aldps(tp); |
7e9da481 | 2010 | |
2011 | rtl_clear_bp(tp); | |
2012 | ||
2013 | r8152b_enable_aldps(tp); | |
aa66a5f1 | 2014 | set_bit(PHY_RESET, &tp->flags); |
4349968a | 2015 | } |
2016 | ||
ac718b69 | 2017 | static void r8152b_exit_oob(struct r8152 *tp) |
2018 | { | |
db8515ef | 2019 | u32 ocp_data; |
2020 | int i; | |
ac718b69 | 2021 | |
2022 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2023 | ocp_data &= ~RCR_ACPT_ALL; | |
2024 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2025 | ||
00a5e360 | 2026 | rxdy_gated_en(tp, true); |
da9bd117 | 2027 | r8153_teredo_off(tp); |
7e9da481 | 2028 | r8152b_hw_phy_cfg(tp); |
ac718b69 | 2029 | |
2030 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
2031 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); | |
2032 | ||
2033 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2034 | ocp_data &= ~NOW_IS_OOB; | |
2035 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2036 | ||
2037 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2038 | ocp_data &= ~MCU_BORW_EN; | |
2039 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2040 | ||
2041 | for (i = 0; i < 1000; i++) { | |
2042 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2043 | if (ocp_data & LINK_LIST_READY) | |
2044 | break; | |
2045 | mdelay(1); | |
2046 | } | |
2047 | ||
2048 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2049 | ocp_data |= RE_INIT_LL; | |
2050 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2051 | ||
2052 | for (i = 0; i < 1000; i++) { | |
2053 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2054 | if (ocp_data & LINK_LIST_READY) | |
2055 | break; | |
2056 | mdelay(1); | |
2057 | } | |
2058 | ||
2059 | rtl8152_nic_reset(tp); | |
2060 | ||
2061 | /* rx share fifo credit full threshold */ | |
2062 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); | |
2063 | ||
2064 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_DEV_STAT); | |
2065 | ocp_data &= STAT_SPEED_MASK; | |
2066 | if (ocp_data == STAT_SPEED_FULL) { | |
2067 | /* rx share fifo credit near full threshold */ | |
2068 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, | |
2069 | RXFIFO_THR2_FULL); | |
2070 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, | |
2071 | RXFIFO_THR3_FULL); | |
2072 | } else { | |
2073 | /* rx share fifo credit near full threshold */ | |
2074 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, | |
2075 | RXFIFO_THR2_HIGH); | |
2076 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, | |
2077 | RXFIFO_THR3_HIGH); | |
2078 | } | |
2079 | ||
2080 | /* TX share fifo free credit full threshold */ | |
2081 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL); | |
2082 | ||
2083 | ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD); | |
8e1f51bd | 2084 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH); |
ac718b69 | 2085 | ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA, |
2086 | TEST_MODE_DISABLE | TX_SIZE_ADJUST1); | |
2087 | ||
2088 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); | |
2089 | ocp_data &= ~CPCR_RX_VLAN; | |
2090 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); | |
2091 | ||
2092 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); | |
2093 | ||
2094 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); | |
2095 | ocp_data |= TCR0_AUTO_FIFO; | |
2096 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); | |
2097 | } | |
2098 | ||
2099 | static void r8152b_enter_oob(struct r8152 *tp) | |
2100 | { | |
45f4a19f | 2101 | u32 ocp_data; |
2102 | int i; | |
ac718b69 | 2103 | |
2104 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2105 | ocp_data &= ~NOW_IS_OOB; | |
2106 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2107 | ||
2108 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); | |
2109 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); | |
2110 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB); | |
2111 | ||
2112 | rtl8152_disable(tp); | |
2113 | ||
2114 | for (i = 0; i < 1000; i++) { | |
2115 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2116 | if (ocp_data & LINK_LIST_READY) | |
2117 | break; | |
2118 | mdelay(1); | |
2119 | } | |
2120 | ||
2121 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2122 | ocp_data |= RE_INIT_LL; | |
2123 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2124 | ||
2125 | for (i = 0; i < 1000; i++) { | |
2126 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2127 | if (ocp_data & LINK_LIST_READY) | |
2128 | break; | |
2129 | mdelay(1); | |
2130 | } | |
2131 | ||
2132 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); | |
2133 | ||
ac718b69 | 2134 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); |
2135 | ocp_data |= CPCR_RX_VLAN; | |
2136 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); | |
2137 | ||
2138 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); | |
2139 | ocp_data |= ALDPS_PROXY_MODE; | |
2140 | ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); | |
2141 | ||
2142 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2143 | ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; | |
2144 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2145 | ||
00a5e360 | 2146 | rxdy_gated_en(tp, false); |
ac718b69 | 2147 | |
2148 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2149 | ocp_data |= RCR_APM | RCR_AM | RCR_AB; | |
2150 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2151 | } | |
2152 | ||
43779f8d | 2153 | static void r8153_hw_phy_cfg(struct r8152 *tp) |
2154 | { | |
2155 | u32 ocp_data; | |
2156 | u16 data; | |
2157 | ||
2158 | ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L); | |
f0cbe0ac | 2159 | data = r8152_mdio_read(tp, MII_BMCR); |
2160 | if (data & BMCR_PDOWN) { | |
2161 | data &= ~BMCR_PDOWN; | |
2162 | r8152_mdio_write(tp, MII_BMCR, data); | |
2163 | } | |
43779f8d | 2164 | |
7e9da481 | 2165 | r8153_clear_bp(tp); |
2166 | ||
43779f8d | 2167 | if (tp->version == RTL_VER_03) { |
2168 | data = ocp_reg_read(tp, OCP_EEE_CFG); | |
2169 | data &= ~CTAP_SHORT_EN; | |
2170 | ocp_reg_write(tp, OCP_EEE_CFG, data); | |
2171 | } | |
2172 | ||
2173 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
2174 | data |= EEE_CLKDIV_EN; | |
2175 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
2176 | ||
2177 | data = ocp_reg_read(tp, OCP_DOWN_SPEED); | |
2178 | data |= EN_10M_BGOFF; | |
2179 | ocp_reg_write(tp, OCP_DOWN_SPEED, data); | |
2180 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
2181 | data |= EN_10M_PLLOFF; | |
2182 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
2183 | data = sram_read(tp, SRAM_IMPEDANCE); | |
2184 | data &= ~RX_DRIVING_MASK; | |
2185 | sram_write(tp, SRAM_IMPEDANCE, data); | |
2186 | ||
2187 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); | |
2188 | ocp_data |= PFM_PWM_SWITCH; | |
2189 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); | |
2190 | ||
2191 | data = sram_read(tp, SRAM_LPF_CFG); | |
2192 | data |= LPF_AUTO_TUNE; | |
2193 | sram_write(tp, SRAM_LPF_CFG, data); | |
2194 | ||
2195 | data = sram_read(tp, SRAM_10M_AMP1); | |
2196 | data |= GDAC_IB_UPALL; | |
2197 | sram_write(tp, SRAM_10M_AMP1, data); | |
2198 | data = sram_read(tp, SRAM_10M_AMP2); | |
2199 | data |= AMP_DN; | |
2200 | sram_write(tp, SRAM_10M_AMP2, data); | |
aa66a5f1 | 2201 | |
2202 | set_bit(PHY_RESET, &tp->flags); | |
43779f8d | 2203 | } |
2204 | ||
b9702723 | 2205 | static void r8153_u1u2en(struct r8152 *tp, bool enable) |
43779f8d | 2206 | { |
2207 | u8 u1u2[8]; | |
2208 | ||
2209 | if (enable) | |
2210 | memset(u1u2, 0xff, sizeof(u1u2)); | |
2211 | else | |
2212 | memset(u1u2, 0x00, sizeof(u1u2)); | |
2213 | ||
2214 | usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2); | |
2215 | } | |
2216 | ||
b9702723 | 2217 | static void r8153_u2p3en(struct r8152 *tp, bool enable) |
43779f8d | 2218 | { |
2219 | u32 ocp_data; | |
2220 | ||
2221 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); | |
2222 | if (enable) | |
2223 | ocp_data |= U2P3_ENABLE; | |
2224 | else | |
2225 | ocp_data &= ~U2P3_ENABLE; | |
2226 | ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); | |
2227 | } | |
2228 | ||
b9702723 | 2229 | static void r8153_power_cut_en(struct r8152 *tp, bool enable) |
43779f8d | 2230 | { |
2231 | u32 ocp_data; | |
2232 | ||
2233 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); | |
2234 | if (enable) | |
2235 | ocp_data |= PWR_EN | PHASE2_EN; | |
2236 | else | |
2237 | ocp_data &= ~(PWR_EN | PHASE2_EN); | |
2238 | ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); | |
2239 | ||
2240 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); | |
2241 | ocp_data &= ~PCUT_STATUS; | |
2242 | ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); | |
2243 | } | |
2244 | ||
43779f8d | 2245 | static void r8153_first_init(struct r8152 *tp) |
2246 | { | |
2247 | u32 ocp_data; | |
2248 | int i; | |
2249 | ||
00a5e360 | 2250 | rxdy_gated_en(tp, true); |
43779f8d | 2251 | r8153_teredo_off(tp); |
2252 | ||
2253 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2254 | ocp_data &= ~RCR_ACPT_ALL; | |
2255 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2256 | ||
2257 | r8153_hw_phy_cfg(tp); | |
2258 | ||
2259 | rtl8152_nic_reset(tp); | |
2260 | ||
2261 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2262 | ocp_data &= ~NOW_IS_OOB; | |
2263 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2264 | ||
2265 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2266 | ocp_data &= ~MCU_BORW_EN; | |
2267 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2268 | ||
2269 | for (i = 0; i < 1000; i++) { | |
2270 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2271 | if (ocp_data & LINK_LIST_READY) | |
2272 | break; | |
2273 | mdelay(1); | |
2274 | } | |
2275 | ||
2276 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2277 | ocp_data |= RE_INIT_LL; | |
2278 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2279 | ||
2280 | for (i = 0; i < 1000; i++) { | |
2281 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2282 | if (ocp_data & LINK_LIST_READY) | |
2283 | break; | |
2284 | mdelay(1); | |
2285 | } | |
2286 | ||
2287 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); | |
2288 | ocp_data &= ~CPCR_RX_VLAN; | |
2289 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); | |
2290 | ||
2291 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); | |
2292 | ||
2293 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); | |
2294 | ocp_data |= TCR0_AUTO_FIFO; | |
2295 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); | |
2296 | ||
2297 | rtl8152_nic_reset(tp); | |
2298 | ||
2299 | /* rx share fifo credit full threshold */ | |
2300 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); | |
2301 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL); | |
2302 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL); | |
2303 | /* TX share fifo free credit full threshold */ | |
2304 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2); | |
2305 | ||
9629e3c0 | 2306 | /* rx aggregation */ |
43779f8d | 2307 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); |
2308 | ocp_data &= ~RX_AGG_DISABLE; | |
2309 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); | |
2310 | } | |
2311 | ||
2312 | static void r8153_enter_oob(struct r8152 *tp) | |
2313 | { | |
2314 | u32 ocp_data; | |
2315 | int i; | |
2316 | ||
2317 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2318 | ocp_data &= ~NOW_IS_OOB; | |
2319 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2320 | ||
2321 | rtl8152_disable(tp); | |
2322 | ||
2323 | for (i = 0; i < 1000; i++) { | |
2324 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2325 | if (ocp_data & LINK_LIST_READY) | |
2326 | break; | |
2327 | mdelay(1); | |
2328 | } | |
2329 | ||
2330 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
2331 | ocp_data |= RE_INIT_LL; | |
2332 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
2333 | ||
2334 | for (i = 0; i < 1000; i++) { | |
2335 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2336 | if (ocp_data & LINK_LIST_READY) | |
2337 | break; | |
2338 | mdelay(1); | |
2339 | } | |
2340 | ||
2341 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); | |
2342 | ||
43779f8d | 2343 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); |
2344 | ocp_data &= ~TEREDO_WAKE_MASK; | |
2345 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); | |
2346 | ||
2347 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); | |
2348 | ocp_data |= CPCR_RX_VLAN; | |
2349 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); | |
2350 | ||
2351 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); | |
2352 | ocp_data |= ALDPS_PROXY_MODE; | |
2353 | ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); | |
2354 | ||
2355 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2356 | ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; | |
2357 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
2358 | ||
00a5e360 | 2359 | rxdy_gated_en(tp, false); |
43779f8d | 2360 | |
2361 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2362 | ocp_data |= RCR_APM | RCR_AM | RCR_AB; | |
2363 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2364 | } | |
2365 | ||
2366 | static void r8153_disable_aldps(struct r8152 *tp) | |
2367 | { | |
2368 | u16 data; | |
2369 | ||
2370 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
2371 | data &= ~EN_ALDPS; | |
2372 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
2373 | msleep(20); | |
2374 | } | |
2375 | ||
2376 | static void r8153_enable_aldps(struct r8152 *tp) | |
2377 | { | |
2378 | u16 data; | |
2379 | ||
2380 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
2381 | data |= EN_ALDPS; | |
2382 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
2383 | } | |
2384 | ||
ac718b69 | 2385 | static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex) |
2386 | { | |
43779f8d | 2387 | u16 bmcr, anar, gbcr; |
ac718b69 | 2388 | int ret = 0; |
2389 | ||
2390 | cancel_delayed_work_sync(&tp->schedule); | |
2391 | anar = r8152_mdio_read(tp, MII_ADVERTISE); | |
2392 | anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | | |
2393 | ADVERTISE_100HALF | ADVERTISE_100FULL); | |
43779f8d | 2394 | if (tp->mii.supports_gmii) { |
2395 | gbcr = r8152_mdio_read(tp, MII_CTRL1000); | |
2396 | gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); | |
2397 | } else { | |
2398 | gbcr = 0; | |
2399 | } | |
ac718b69 | 2400 | |
2401 | if (autoneg == AUTONEG_DISABLE) { | |
2402 | if (speed == SPEED_10) { | |
2403 | bmcr = 0; | |
2404 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
2405 | } else if (speed == SPEED_100) { | |
2406 | bmcr = BMCR_SPEED100; | |
2407 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; | |
43779f8d | 2408 | } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { |
2409 | bmcr = BMCR_SPEED1000; | |
2410 | gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; | |
ac718b69 | 2411 | } else { |
2412 | ret = -EINVAL; | |
2413 | goto out; | |
2414 | } | |
2415 | ||
2416 | if (duplex == DUPLEX_FULL) | |
2417 | bmcr |= BMCR_FULLDPLX; | |
2418 | } else { | |
2419 | if (speed == SPEED_10) { | |
2420 | if (duplex == DUPLEX_FULL) | |
2421 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
2422 | else | |
2423 | anar |= ADVERTISE_10HALF; | |
2424 | } else if (speed == SPEED_100) { | |
2425 | if (duplex == DUPLEX_FULL) { | |
2426 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
2427 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; | |
2428 | } else { | |
2429 | anar |= ADVERTISE_10HALF; | |
2430 | anar |= ADVERTISE_100HALF; | |
2431 | } | |
43779f8d | 2432 | } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { |
2433 | if (duplex == DUPLEX_FULL) { | |
2434 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
2435 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; | |
2436 | gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; | |
2437 | } else { | |
2438 | anar |= ADVERTISE_10HALF; | |
2439 | anar |= ADVERTISE_100HALF; | |
2440 | gbcr |= ADVERTISE_1000HALF; | |
2441 | } | |
ac718b69 | 2442 | } else { |
2443 | ret = -EINVAL; | |
2444 | goto out; | |
2445 | } | |
2446 | ||
2447 | bmcr = BMCR_ANENABLE | BMCR_ANRESTART; | |
2448 | } | |
2449 | ||
aa66a5f1 | 2450 | if (test_bit(PHY_RESET, &tp->flags)) |
2451 | bmcr |= BMCR_RESET; | |
2452 | ||
43779f8d | 2453 | if (tp->mii.supports_gmii) |
2454 | r8152_mdio_write(tp, MII_CTRL1000, gbcr); | |
2455 | ||
ac718b69 | 2456 | r8152_mdio_write(tp, MII_ADVERTISE, anar); |
2457 | r8152_mdio_write(tp, MII_BMCR, bmcr); | |
2458 | ||
aa66a5f1 | 2459 | if (test_bit(PHY_RESET, &tp->flags)) { |
2460 | int i; | |
2461 | ||
2462 | clear_bit(PHY_RESET, &tp->flags); | |
2463 | for (i = 0; i < 50; i++) { | |
2464 | msleep(20); | |
2465 | if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) | |
2466 | break; | |
2467 | } | |
2468 | } | |
2469 | ||
ac718b69 | 2470 | out: |
ac718b69 | 2471 | |
2472 | return ret; | |
2473 | } | |
2474 | ||
2475 | static void rtl8152_down(struct r8152 *tp) | |
2476 | { | |
00a5e360 | 2477 | r8152_power_cut_en(tp, false); |
ac718b69 | 2478 | r8152b_disable_aldps(tp); |
2479 | r8152b_enter_oob(tp); | |
2480 | r8152b_enable_aldps(tp); | |
2481 | } | |
2482 | ||
43779f8d | 2483 | static void rtl8153_down(struct r8152 *tp) |
2484 | { | |
b9702723 | 2485 | r8153_u1u2en(tp, false); |
2486 | r8153_power_cut_en(tp, false); | |
43779f8d | 2487 | r8153_disable_aldps(tp); |
2488 | r8153_enter_oob(tp); | |
2489 | r8153_enable_aldps(tp); | |
2490 | } | |
2491 | ||
ac718b69 | 2492 | static void set_carrier(struct r8152 *tp) |
2493 | { | |
2494 | struct net_device *netdev = tp->netdev; | |
2495 | u8 speed; | |
2496 | ||
40a82917 | 2497 | clear_bit(RTL8152_LINK_CHG, &tp->flags); |
ac718b69 | 2498 | speed = rtl8152_get_speed(tp); |
2499 | ||
2500 | if (speed & LINK_STATUS) { | |
2501 | if (!(tp->speed & LINK_STATUS)) { | |
c81229c9 | 2502 | tp->rtl_ops.enable(tp); |
ac718b69 | 2503 | set_bit(RTL8152_SET_RX_MODE, &tp->flags); |
2504 | netif_carrier_on(netdev); | |
2505 | } | |
2506 | } else { | |
2507 | if (tp->speed & LINK_STATUS) { | |
2508 | netif_carrier_off(netdev); | |
ebc2ec48 | 2509 | tasklet_disable(&tp->tl); |
c81229c9 | 2510 | tp->rtl_ops.disable(tp); |
ebc2ec48 | 2511 | tasklet_enable(&tp->tl); |
ac718b69 | 2512 | } |
2513 | } | |
2514 | tp->speed = speed; | |
2515 | } | |
2516 | ||
2517 | static void rtl_work_func_t(struct work_struct *work) | |
2518 | { | |
2519 | struct r8152 *tp = container_of(work, struct r8152, schedule.work); | |
2520 | ||
9a4be1bd | 2521 | if (usb_autopm_get_interface(tp->intf) < 0) |
2522 | return; | |
2523 | ||
ac718b69 | 2524 | if (!test_bit(WORK_ENABLE, &tp->flags)) |
2525 | goto out1; | |
2526 | ||
2527 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
2528 | goto out1; | |
2529 | ||
40a82917 | 2530 | if (test_bit(RTL8152_LINK_CHG, &tp->flags)) |
2531 | set_carrier(tp); | |
ac718b69 | 2532 | |
2533 | if (test_bit(RTL8152_SET_RX_MODE, &tp->flags)) | |
2534 | _rtl8152_set_rx_mode(tp->netdev); | |
2535 | ||
9a4be1bd | 2536 | if (tp->speed & LINK_STATUS) |
2537 | tx_bottom(tp); | |
aa66a5f1 | 2538 | |
2539 | if (test_bit(PHY_RESET, &tp->flags)) | |
2540 | rtl_phy_reset(tp); | |
2541 | ||
ac718b69 | 2542 | out1: |
9a4be1bd | 2543 | usb_autopm_put_interface(tp->intf); |
ac718b69 | 2544 | } |
2545 | ||
2546 | static int rtl8152_open(struct net_device *netdev) | |
2547 | { | |
2548 | struct r8152 *tp = netdev_priv(netdev); | |
2549 | int res = 0; | |
2550 | ||
7e9da481 | 2551 | res = alloc_all_mem(tp); |
2552 | if (res) | |
2553 | goto out; | |
2554 | ||
9a4be1bd | 2555 | res = usb_autopm_get_interface(tp->intf); |
2556 | if (res < 0) { | |
2557 | free_all_mem(tp); | |
2558 | goto out; | |
2559 | } | |
2560 | ||
2561 | /* The WORK_ENABLE may be set when autoresume occurs */ | |
2562 | if (test_bit(WORK_ENABLE, &tp->flags)) { | |
2563 | clear_bit(WORK_ENABLE, &tp->flags); | |
2564 | usb_kill_urb(tp->intr_urb); | |
2565 | cancel_delayed_work_sync(&tp->schedule); | |
2566 | if (tp->speed & LINK_STATUS) | |
2567 | tp->rtl_ops.disable(tp); | |
2568 | } | |
2569 | ||
7e9da481 | 2570 | tp->rtl_ops.up(tp); |
2571 | ||
3d55f44f | 2572 | rtl8152_set_speed(tp, AUTONEG_ENABLE, |
2573 | tp->mii.supports_gmii ? SPEED_1000 : SPEED_100, | |
2574 | DUPLEX_FULL); | |
2575 | tp->speed = 0; | |
2576 | netif_carrier_off(netdev); | |
2577 | netif_start_queue(netdev); | |
2578 | set_bit(WORK_ENABLE, &tp->flags); | |
db8515ef | 2579 | |
40a82917 | 2580 | res = usb_submit_urb(tp->intr_urb, GFP_KERNEL); |
2581 | if (res) { | |
2582 | if (res == -ENODEV) | |
2583 | netif_device_detach(tp->netdev); | |
4a8deae2 HW |
2584 | netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n", |
2585 | res); | |
7e9da481 | 2586 | free_all_mem(tp); |
ac718b69 | 2587 | } |
2588 | ||
9a4be1bd | 2589 | usb_autopm_put_interface(tp->intf); |
ac718b69 | 2590 | |
7e9da481 | 2591 | out: |
ac718b69 | 2592 | return res; |
2593 | } | |
2594 | ||
2595 | static int rtl8152_close(struct net_device *netdev) | |
2596 | { | |
2597 | struct r8152 *tp = netdev_priv(netdev); | |
2598 | int res = 0; | |
2599 | ||
2600 | clear_bit(WORK_ENABLE, &tp->flags); | |
3d55f44f | 2601 | usb_kill_urb(tp->intr_urb); |
ac718b69 | 2602 | cancel_delayed_work_sync(&tp->schedule); |
2603 | netif_stop_queue(netdev); | |
9a4be1bd | 2604 | |
2605 | res = usb_autopm_get_interface(tp->intf); | |
2606 | if (res < 0) { | |
2607 | rtl_drop_queued_tx(tp); | |
2608 | } else { | |
2609 | /* | |
2610 | * The autosuspend may have been enabled and wouldn't | |
2611 | * be disable when autoresume occurs, because the | |
2612 | * netif_running() would be false. | |
2613 | */ | |
2614 | if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { | |
2615 | rtl_runtime_suspend_enable(tp, false); | |
2616 | clear_bit(SELECTIVE_SUSPEND, &tp->flags); | |
2617 | } | |
2618 | ||
2619 | tasklet_disable(&tp->tl); | |
2620 | tp->rtl_ops.down(tp); | |
2621 | tasklet_enable(&tp->tl); | |
2622 | usb_autopm_put_interface(tp->intf); | |
2623 | } | |
ac718b69 | 2624 | |
7e9da481 | 2625 | free_all_mem(tp); |
2626 | ||
ac718b69 | 2627 | return res; |
2628 | } | |
2629 | ||
ac718b69 | 2630 | static void r8152b_enable_eee(struct r8152 *tp) |
2631 | { | |
45f4a19f | 2632 | u32 ocp_data; |
ac718b69 | 2633 | |
2634 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); | |
2635 | ocp_data |= EEE_RX_EN | EEE_TX_EN; | |
2636 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); | |
2637 | ocp_reg_write(tp, OCP_EEE_CONFIG1, RG_TXLPI_MSK_HFDUP | RG_MATCLR_EN | | |
2638 | EEE_10_CAP | EEE_NWAY_EN | | |
2639 | TX_QUIET_EN | RX_QUIET_EN | | |
2640 | SDRISETIME | RG_RXLPI_MSK_HFDUP | | |
2641 | SDFALLTIME); | |
2642 | ocp_reg_write(tp, OCP_EEE_CONFIG2, RG_LPIHYS_NUM | RG_DACQUIET_EN | | |
2643 | RG_LDVQUIET_EN | RG_CKRSEL | | |
2644 | RG_EEEPRG_EN); | |
2645 | ocp_reg_write(tp, OCP_EEE_CONFIG3, FST_SNR_EYE_R | RG_LFS_SEL | MSK_PH); | |
2646 | ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | DEVICE_ADDR); | |
2647 | ocp_reg_write(tp, OCP_EEE_DATA, EEE_ADDR); | |
2648 | ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | DEVICE_ADDR); | |
2649 | ocp_reg_write(tp, OCP_EEE_DATA, EEE_DATA); | |
2650 | ocp_reg_write(tp, OCP_EEE_AR, 0x0000); | |
2651 | } | |
2652 | ||
43779f8d | 2653 | static void r8153_enable_eee(struct r8152 *tp) |
2654 | { | |
2655 | u32 ocp_data; | |
2656 | u16 data; | |
2657 | ||
2658 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); | |
2659 | ocp_data |= EEE_RX_EN | EEE_TX_EN; | |
2660 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); | |
2661 | data = ocp_reg_read(tp, OCP_EEE_CFG); | |
2662 | data |= EEE10_EN; | |
2663 | ocp_reg_write(tp, OCP_EEE_CFG, data); | |
2664 | data = ocp_reg_read(tp, OCP_EEE_CFG2); | |
2665 | data |= MY1000_EEE | MY100_EEE; | |
2666 | ocp_reg_write(tp, OCP_EEE_CFG2, data); | |
2667 | } | |
2668 | ||
ac718b69 | 2669 | static void r8152b_enable_fc(struct r8152 *tp) |
2670 | { | |
2671 | u16 anar; | |
2672 | ||
2673 | anar = r8152_mdio_read(tp, MII_ADVERTISE); | |
2674 | anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; | |
2675 | r8152_mdio_write(tp, MII_ADVERTISE, anar); | |
2676 | } | |
2677 | ||
ac718b69 | 2678 | static void r8152b_init(struct r8152 *tp) |
2679 | { | |
ebc2ec48 | 2680 | u32 ocp_data; |
ac718b69 | 2681 | |
ac718b69 | 2682 | if (tp->version == RTL_VER_01) { |
2683 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); | |
2684 | ocp_data &= ~LED_MODE_MASK; | |
2685 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); | |
2686 | } | |
2687 | ||
00a5e360 | 2688 | r8152_power_cut_en(tp, false); |
ac718b69 | 2689 | |
ac718b69 | 2690 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); |
2691 | ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH; | |
2692 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); | |
2693 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL); | |
2694 | ocp_data &= ~MCU_CLK_RATIO_MASK; | |
2695 | ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN; | |
2696 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data); | |
2697 | ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK | | |
2698 | SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK; | |
2699 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data); | |
2700 | ||
2701 | r8152b_enable_eee(tp); | |
2702 | r8152b_enable_aldps(tp); | |
2703 | r8152b_enable_fc(tp); | |
2704 | ||
ebc2ec48 | 2705 | /* enable rx aggregation */ |
ac718b69 | 2706 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); |
ebc2ec48 | 2707 | ocp_data &= ~RX_AGG_DISABLE; |
ac718b69 | 2708 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); |
2709 | } | |
2710 | ||
43779f8d | 2711 | static void r8153_init(struct r8152 *tp) |
2712 | { | |
2713 | u32 ocp_data; | |
2714 | int i; | |
2715 | ||
b9702723 | 2716 | r8153_u1u2en(tp, false); |
43779f8d | 2717 | |
2718 | for (i = 0; i < 500; i++) { | |
2719 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & | |
2720 | AUTOLOAD_DONE) | |
2721 | break; | |
2722 | msleep(20); | |
2723 | } | |
2724 | ||
2725 | for (i = 0; i < 500; i++) { | |
2726 | ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK; | |
2727 | if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN) | |
2728 | break; | |
2729 | msleep(20); | |
2730 | } | |
2731 | ||
b9702723 | 2732 | r8153_u2p3en(tp, false); |
43779f8d | 2733 | |
2734 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL); | |
2735 | ocp_data &= ~TIMER11_EN; | |
2736 | ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data); | |
2737 | ||
43779f8d | 2738 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); |
2739 | ocp_data &= ~LED_MODE_MASK; | |
2740 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); | |
2741 | ||
2742 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL); | |
2743 | ocp_data &= ~LPM_TIMER_MASK; | |
2744 | if (tp->udev->speed == USB_SPEED_SUPER) | |
2745 | ocp_data |= LPM_TIMER_500US; | |
2746 | else | |
2747 | ocp_data |= LPM_TIMER_500MS; | |
2748 | ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data); | |
2749 | ||
2750 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2); | |
2751 | ocp_data &= ~SEN_VAL_MASK; | |
2752 | ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE; | |
2753 | ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data); | |
2754 | ||
b9702723 | 2755 | r8153_power_cut_en(tp, false); |
2756 | r8153_u1u2en(tp, true); | |
43779f8d | 2757 | |
43779f8d | 2758 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO); |
2759 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO); | |
2760 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, | |
2761 | PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN | | |
2762 | U1U2_SPDWN_EN | L1_SPDWN_EN); | |
2763 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, | |
2764 | PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN | | |
2765 | TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN | | |
2766 | EEE_SPDWN_EN); | |
2767 | ||
2768 | r8153_enable_eee(tp); | |
2769 | r8153_enable_aldps(tp); | |
2770 | r8152b_enable_fc(tp); | |
43779f8d | 2771 | } |
2772 | ||
ac718b69 | 2773 | static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message) |
2774 | { | |
2775 | struct r8152 *tp = usb_get_intfdata(intf); | |
2776 | ||
9a4be1bd | 2777 | if (PMSG_IS_AUTO(message)) |
2778 | set_bit(SELECTIVE_SUSPEND, &tp->flags); | |
2779 | else | |
2780 | netif_device_detach(tp->netdev); | |
ac718b69 | 2781 | |
2782 | if (netif_running(tp->netdev)) { | |
2783 | clear_bit(WORK_ENABLE, &tp->flags); | |
40a82917 | 2784 | usb_kill_urb(tp->intr_urb); |
ac718b69 | 2785 | cancel_delayed_work_sync(&tp->schedule); |
9a4be1bd | 2786 | if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { |
2787 | rtl_runtime_suspend_enable(tp, true); | |
2788 | } else { | |
2789 | tasklet_disable(&tp->tl); | |
2790 | tp->rtl_ops.down(tp); | |
2791 | tasklet_enable(&tp->tl); | |
2792 | } | |
ac718b69 | 2793 | } |
2794 | ||
ac718b69 | 2795 | return 0; |
2796 | } | |
2797 | ||
2798 | static int rtl8152_resume(struct usb_interface *intf) | |
2799 | { | |
2800 | struct r8152 *tp = usb_get_intfdata(intf); | |
2801 | ||
9a4be1bd | 2802 | if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) { |
2803 | tp->rtl_ops.init(tp); | |
2804 | netif_device_attach(tp->netdev); | |
2805 | } | |
2806 | ||
ac718b69 | 2807 | if (netif_running(tp->netdev)) { |
9a4be1bd | 2808 | if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { |
2809 | rtl_runtime_suspend_enable(tp, false); | |
2810 | clear_bit(SELECTIVE_SUSPEND, &tp->flags); | |
2811 | if (tp->speed & LINK_STATUS) | |
2812 | tp->rtl_ops.disable(tp); | |
2813 | } else { | |
2814 | tp->rtl_ops.up(tp); | |
2815 | rtl8152_set_speed(tp, AUTONEG_ENABLE, | |
43779f8d | 2816 | tp->mii.supports_gmii ? SPEED_1000 : SPEED_100, |
2817 | DUPLEX_FULL); | |
9a4be1bd | 2818 | } |
40a82917 | 2819 | tp->speed = 0; |
2820 | netif_carrier_off(tp->netdev); | |
ac718b69 | 2821 | set_bit(WORK_ENABLE, &tp->flags); |
40a82917 | 2822 | usb_submit_urb(tp->intr_urb, GFP_KERNEL); |
ac718b69 | 2823 | } |
2824 | ||
2825 | return 0; | |
2826 | } | |
2827 | ||
21ff2e89 | 2828 | static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
2829 | { | |
2830 | struct r8152 *tp = netdev_priv(dev); | |
2831 | ||
9a4be1bd | 2832 | if (usb_autopm_get_interface(tp->intf) < 0) |
2833 | return; | |
2834 | ||
21ff2e89 | 2835 | wol->supported = WAKE_ANY; |
2836 | wol->wolopts = __rtl_get_wol(tp); | |
9a4be1bd | 2837 | |
2838 | usb_autopm_put_interface(tp->intf); | |
21ff2e89 | 2839 | } |
2840 | ||
2841 | static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
2842 | { | |
2843 | struct r8152 *tp = netdev_priv(dev); | |
9a4be1bd | 2844 | int ret; |
2845 | ||
2846 | ret = usb_autopm_get_interface(tp->intf); | |
2847 | if (ret < 0) | |
2848 | goto out_set_wol; | |
21ff2e89 | 2849 | |
2850 | __rtl_set_wol(tp, wol->wolopts); | |
2851 | tp->saved_wolopts = wol->wolopts & WAKE_ANY; | |
2852 | ||
9a4be1bd | 2853 | usb_autopm_put_interface(tp->intf); |
2854 | ||
2855 | out_set_wol: | |
2856 | return ret; | |
21ff2e89 | 2857 | } |
2858 | ||
a5ec27c1 | 2859 | static u32 rtl8152_get_msglevel(struct net_device *dev) |
2860 | { | |
2861 | struct r8152 *tp = netdev_priv(dev); | |
2862 | ||
2863 | return tp->msg_enable; | |
2864 | } | |
2865 | ||
2866 | static void rtl8152_set_msglevel(struct net_device *dev, u32 value) | |
2867 | { | |
2868 | struct r8152 *tp = netdev_priv(dev); | |
2869 | ||
2870 | tp->msg_enable = value; | |
2871 | } | |
2872 | ||
ac718b69 | 2873 | static void rtl8152_get_drvinfo(struct net_device *netdev, |
2874 | struct ethtool_drvinfo *info) | |
2875 | { | |
2876 | struct r8152 *tp = netdev_priv(netdev); | |
2877 | ||
2878 | strncpy(info->driver, MODULENAME, ETHTOOL_BUSINFO_LEN); | |
2879 | strncpy(info->version, DRIVER_VERSION, ETHTOOL_BUSINFO_LEN); | |
2880 | usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info)); | |
2881 | } | |
2882 | ||
2883 | static | |
2884 | int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd) | |
2885 | { | |
2886 | struct r8152 *tp = netdev_priv(netdev); | |
2887 | ||
2888 | if (!tp->mii.mdio_read) | |
2889 | return -EOPNOTSUPP; | |
2890 | ||
2891 | return mii_ethtool_gset(&tp->mii, cmd); | |
2892 | } | |
2893 | ||
2894 | static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
2895 | { | |
2896 | struct r8152 *tp = netdev_priv(dev); | |
9a4be1bd | 2897 | int ret; |
2898 | ||
2899 | ret = usb_autopm_get_interface(tp->intf); | |
2900 | if (ret < 0) | |
2901 | goto out; | |
ac718b69 | 2902 | |
9a4be1bd | 2903 | ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex); |
2904 | ||
2905 | usb_autopm_put_interface(tp->intf); | |
2906 | ||
2907 | out: | |
2908 | return ret; | |
ac718b69 | 2909 | } |
2910 | ||
2911 | static struct ethtool_ops ops = { | |
2912 | .get_drvinfo = rtl8152_get_drvinfo, | |
2913 | .get_settings = rtl8152_get_settings, | |
2914 | .set_settings = rtl8152_set_settings, | |
2915 | .get_link = ethtool_op_get_link, | |
a5ec27c1 | 2916 | .get_msglevel = rtl8152_get_msglevel, |
2917 | .set_msglevel = rtl8152_set_msglevel, | |
21ff2e89 | 2918 | .get_wol = rtl8152_get_wol, |
2919 | .set_wol = rtl8152_set_wol, | |
ac718b69 | 2920 | }; |
2921 | ||
2922 | static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) | |
2923 | { | |
2924 | struct r8152 *tp = netdev_priv(netdev); | |
2925 | struct mii_ioctl_data *data = if_mii(rq); | |
9a4be1bd | 2926 | int res; |
2927 | ||
2928 | res = usb_autopm_get_interface(tp->intf); | |
2929 | if (res < 0) | |
2930 | goto out; | |
ac718b69 | 2931 | |
2932 | switch (cmd) { | |
2933 | case SIOCGMIIPHY: | |
2934 | data->phy_id = R8152_PHY_ID; /* Internal PHY */ | |
2935 | break; | |
2936 | ||
2937 | case SIOCGMIIREG: | |
2938 | data->val_out = r8152_mdio_read(tp, data->reg_num); | |
2939 | break; | |
2940 | ||
2941 | case SIOCSMIIREG: | |
2942 | if (!capable(CAP_NET_ADMIN)) { | |
2943 | res = -EPERM; | |
2944 | break; | |
2945 | } | |
2946 | r8152_mdio_write(tp, data->reg_num, data->val_in); | |
2947 | break; | |
2948 | ||
2949 | default: | |
2950 | res = -EOPNOTSUPP; | |
2951 | } | |
2952 | ||
9a4be1bd | 2953 | usb_autopm_put_interface(tp->intf); |
2954 | ||
2955 | out: | |
ac718b69 | 2956 | return res; |
2957 | } | |
2958 | ||
2959 | static const struct net_device_ops rtl8152_netdev_ops = { | |
2960 | .ndo_open = rtl8152_open, | |
2961 | .ndo_stop = rtl8152_close, | |
2962 | .ndo_do_ioctl = rtl8152_ioctl, | |
2963 | .ndo_start_xmit = rtl8152_start_xmit, | |
2964 | .ndo_tx_timeout = rtl8152_tx_timeout, | |
2965 | .ndo_set_rx_mode = rtl8152_set_rx_mode, | |
2966 | .ndo_set_mac_address = rtl8152_set_mac_address, | |
2967 | ||
2968 | .ndo_change_mtu = eth_change_mtu, | |
2969 | .ndo_validate_addr = eth_validate_addr, | |
2970 | }; | |
2971 | ||
2972 | static void r8152b_get_version(struct r8152 *tp) | |
2973 | { | |
2974 | u32 ocp_data; | |
2975 | u16 version; | |
2976 | ||
2977 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1); | |
2978 | version = (u16)(ocp_data & VERSION_MASK); | |
2979 | ||
2980 | switch (version) { | |
2981 | case 0x4c00: | |
2982 | tp->version = RTL_VER_01; | |
2983 | break; | |
2984 | case 0x4c10: | |
2985 | tp->version = RTL_VER_02; | |
2986 | break; | |
43779f8d | 2987 | case 0x5c00: |
2988 | tp->version = RTL_VER_03; | |
2989 | tp->mii.supports_gmii = 1; | |
2990 | break; | |
2991 | case 0x5c10: | |
2992 | tp->version = RTL_VER_04; | |
2993 | tp->mii.supports_gmii = 1; | |
2994 | break; | |
2995 | case 0x5c20: | |
2996 | tp->version = RTL_VER_05; | |
2997 | tp->mii.supports_gmii = 1; | |
2998 | break; | |
ac718b69 | 2999 | default: |
3000 | netif_info(tp, probe, tp->netdev, | |
3001 | "Unknown version 0x%04x\n", version); | |
3002 | break; | |
3003 | } | |
3004 | } | |
3005 | ||
e3fe0b1a | 3006 | static void rtl8152_unload(struct r8152 *tp) |
3007 | { | |
00a5e360 | 3008 | if (tp->version != RTL_VER_01) |
3009 | r8152_power_cut_en(tp, true); | |
e3fe0b1a | 3010 | } |
3011 | ||
43779f8d | 3012 | static void rtl8153_unload(struct r8152 *tp) |
3013 | { | |
b9702723 | 3014 | r8153_power_cut_en(tp, true); |
43779f8d | 3015 | } |
3016 | ||
31ca1dec | 3017 | static int rtl_ops_init(struct r8152 *tp, const struct usb_device_id *id) |
c81229c9 | 3018 | { |
3019 | struct rtl_ops *ops = &tp->rtl_ops; | |
31ca1dec | 3020 | int ret = -ENODEV; |
c81229c9 | 3021 | |
3022 | switch (id->idVendor) { | |
3023 | case VENDOR_ID_REALTEK: | |
3024 | switch (id->idProduct) { | |
3025 | case PRODUCT_ID_RTL8152: | |
3026 | ops->init = r8152b_init; | |
3027 | ops->enable = rtl8152_enable; | |
3028 | ops->disable = rtl8152_disable; | |
7e9da481 | 3029 | ops->up = r8152b_exit_oob; |
c81229c9 | 3030 | ops->down = rtl8152_down; |
3031 | ops->unload = rtl8152_unload; | |
31ca1dec | 3032 | ret = 0; |
c81229c9 | 3033 | break; |
43779f8d | 3034 | case PRODUCT_ID_RTL8153: |
3035 | ops->init = r8153_init; | |
3036 | ops->enable = rtl8153_enable; | |
3037 | ops->disable = rtl8152_disable; | |
7e9da481 | 3038 | ops->up = r8153_first_init; |
43779f8d | 3039 | ops->down = rtl8153_down; |
3040 | ops->unload = rtl8153_unload; | |
31ca1dec | 3041 | ret = 0; |
43779f8d | 3042 | break; |
3043 | default: | |
43779f8d | 3044 | break; |
3045 | } | |
3046 | break; | |
3047 | ||
3048 | case VENDOR_ID_SAMSUNG: | |
3049 | switch (id->idProduct) { | |
3050 | case PRODUCT_ID_SAMSUNG: | |
3051 | ops->init = r8153_init; | |
3052 | ops->enable = rtl8153_enable; | |
3053 | ops->disable = rtl8152_disable; | |
7e9da481 | 3054 | ops->up = r8153_first_init; |
43779f8d | 3055 | ops->down = rtl8153_down; |
3056 | ops->unload = rtl8153_unload; | |
31ca1dec | 3057 | ret = 0; |
43779f8d | 3058 | break; |
c81229c9 | 3059 | default: |
c81229c9 | 3060 | break; |
3061 | } | |
3062 | break; | |
3063 | ||
3064 | default: | |
c81229c9 | 3065 | break; |
3066 | } | |
3067 | ||
31ca1dec | 3068 | if (ret) |
3069 | netif_err(tp, probe, tp->netdev, "Unknown Device\n"); | |
3070 | ||
c81229c9 | 3071 | return ret; |
3072 | } | |
3073 | ||
ac718b69 | 3074 | static int rtl8152_probe(struct usb_interface *intf, |
3075 | const struct usb_device_id *id) | |
3076 | { | |
3077 | struct usb_device *udev = interface_to_usbdev(intf); | |
3078 | struct r8152 *tp; | |
3079 | struct net_device *netdev; | |
ebc2ec48 | 3080 | int ret; |
ac718b69 | 3081 | |
ac718b69 | 3082 | netdev = alloc_etherdev(sizeof(struct r8152)); |
3083 | if (!netdev) { | |
4a8deae2 | 3084 | dev_err(&intf->dev, "Out of memory\n"); |
ac718b69 | 3085 | return -ENOMEM; |
3086 | } | |
3087 | ||
ebc2ec48 | 3088 | SET_NETDEV_DEV(netdev, &intf->dev); |
ac718b69 | 3089 | tp = netdev_priv(netdev); |
3090 | tp->msg_enable = 0x7FFF; | |
3091 | ||
e3ad412a | 3092 | tp->udev = udev; |
3093 | tp->netdev = netdev; | |
3094 | tp->intf = intf; | |
3095 | ||
31ca1dec | 3096 | ret = rtl_ops_init(tp, id); |
3097 | if (ret) | |
3098 | goto out; | |
c81229c9 | 3099 | |
ebc2ec48 | 3100 | tasklet_init(&tp->tl, bottom_half, (unsigned long)tp); |
ac718b69 | 3101 | INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t); |
3102 | ||
ac718b69 | 3103 | netdev->netdev_ops = &rtl8152_netdev_ops; |
3104 | netdev->watchdog_timeo = RTL8152_TX_TIMEOUT; | |
5bd23881 | 3105 | |
3106 | netdev->features |= NETIF_F_IP_CSUM; | |
3107 | netdev->hw_features = NETIF_F_IP_CSUM; | |
db8515ef | 3108 | |
ac718b69 | 3109 | SET_ETHTOOL_OPS(netdev, &ops); |
ac718b69 | 3110 | |
3111 | tp->mii.dev = netdev; | |
3112 | tp->mii.mdio_read = read_mii_word; | |
3113 | tp->mii.mdio_write = write_mii_word; | |
3114 | tp->mii.phy_id_mask = 0x3f; | |
3115 | tp->mii.reg_num_mask = 0x1f; | |
3116 | tp->mii.phy_id = R8152_PHY_ID; | |
3117 | tp->mii.supports_gmii = 0; | |
3118 | ||
9a4be1bd | 3119 | intf->needs_remote_wakeup = 1; |
3120 | ||
ac718b69 | 3121 | r8152b_get_version(tp); |
c81229c9 | 3122 | tp->rtl_ops.init(tp); |
ac718b69 | 3123 | set_ethernet_addr(tp); |
3124 | ||
ac718b69 | 3125 | usb_set_intfdata(intf, tp); |
ac718b69 | 3126 | |
ebc2ec48 | 3127 | ret = register_netdev(netdev); |
3128 | if (ret != 0) { | |
4a8deae2 | 3129 | netif_err(tp, probe, netdev, "couldn't register the device\n"); |
ebc2ec48 | 3130 | goto out1; |
ac718b69 | 3131 | } |
3132 | ||
21ff2e89 | 3133 | tp->saved_wolopts = __rtl_get_wol(tp); |
3134 | if (tp->saved_wolopts) | |
3135 | device_set_wakeup_enable(&udev->dev, true); | |
3136 | else | |
3137 | device_set_wakeup_enable(&udev->dev, false); | |
3138 | ||
4a8deae2 | 3139 | netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION); |
ac718b69 | 3140 | |
3141 | return 0; | |
3142 | ||
ac718b69 | 3143 | out1: |
ebc2ec48 | 3144 | usb_set_intfdata(intf, NULL); |
ac718b69 | 3145 | out: |
3146 | free_netdev(netdev); | |
ebc2ec48 | 3147 | return ret; |
ac718b69 | 3148 | } |
3149 | ||
ac718b69 | 3150 | static void rtl8152_disconnect(struct usb_interface *intf) |
3151 | { | |
3152 | struct r8152 *tp = usb_get_intfdata(intf); | |
3153 | ||
3154 | usb_set_intfdata(intf, NULL); | |
3155 | if (tp) { | |
3156 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
3157 | tasklet_kill(&tp->tl); | |
3158 | unregister_netdev(tp->netdev); | |
c81229c9 | 3159 | tp->rtl_ops.unload(tp); |
ac718b69 | 3160 | free_netdev(tp->netdev); |
3161 | } | |
3162 | } | |
3163 | ||
3164 | /* table of devices that work with this driver */ | |
3165 | static struct usb_device_id rtl8152_table[] = { | |
c7de7dec | 3166 | {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8152)}, |
3167 | {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8153)}, | |
3168 | {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, PRODUCT_ID_SAMSUNG)}, | |
ac718b69 | 3169 | {} |
3170 | }; | |
3171 | ||
3172 | MODULE_DEVICE_TABLE(usb, rtl8152_table); | |
3173 | ||
3174 | static struct usb_driver rtl8152_driver = { | |
3175 | .name = MODULENAME, | |
ebc2ec48 | 3176 | .id_table = rtl8152_table, |
ac718b69 | 3177 | .probe = rtl8152_probe, |
3178 | .disconnect = rtl8152_disconnect, | |
ac718b69 | 3179 | .suspend = rtl8152_suspend, |
ebc2ec48 | 3180 | .resume = rtl8152_resume, |
3181 | .reset_resume = rtl8152_resume, | |
9a4be1bd | 3182 | .supports_autosuspend = 1, |
a634782f | 3183 | .disable_hub_initiated_lpm = 1, |
ac718b69 | 3184 | }; |
3185 | ||
b4236daa | 3186 | module_usb_driver(rtl8152_driver); |
ac718b69 | 3187 | |
3188 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
3189 | MODULE_DESCRIPTION(DRIVER_DESC); | |
3190 | MODULE_LICENSE("GPL"); |