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ac718b69 | 1 | /* |
c7de7dec | 2 | * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved. |
ac718b69 | 3 | * |
4 | * This program is free software; you can redistribute it and/or | |
5 | * modify it under the terms of the GNU General Public License | |
6 | * version 2 as published by the Free Software Foundation. | |
7 | * | |
8 | */ | |
9 | ||
ac718b69 | 10 | #include <linux/signal.h> |
11 | #include <linux/slab.h> | |
12 | #include <linux/module.h> | |
ac718b69 | 13 | #include <linux/netdevice.h> |
14 | #include <linux/etherdevice.h> | |
15 | #include <linux/mii.h> | |
16 | #include <linux/ethtool.h> | |
17 | #include <linux/usb.h> | |
18 | #include <linux/crc32.h> | |
19 | #include <linux/if_vlan.h> | |
20 | #include <linux/uaccess.h> | |
ebc2ec48 | 21 | #include <linux/list.h> |
5bd23881 | 22 | #include <linux/ip.h> |
23 | #include <linux/ipv6.h> | |
6128d1bb | 24 | #include <net/ip6_checksum.h> |
4c4a6b1b | 25 | #include <uapi/linux/mdio.h> |
26 | #include <linux/mdio.h> | |
d9a28c5b | 27 | #include <linux/usb/cdc.h> |
5ee3c60c | 28 | #include <linux/suspend.h> |
34ee32c9 | 29 | #include <linux/acpi.h> |
ac718b69 | 30 | |
d0942473 | 31 | /* Information for net-next */ |
65b82d69 | 32 | #define NETNEXT_VERSION "09" |
d0942473 | 33 | |
34 | /* Information for net */ | |
b20cb60e | 35 | #define NET_VERSION "9" |
d0942473 | 36 | |
37 | #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION | |
ac718b69 | 38 | #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>" |
44d942a9 | 39 | #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters" |
ac718b69 | 40 | #define MODULENAME "r8152" |
41 | ||
42 | #define R8152_PHY_ID 32 | |
43 | ||
44 | #define PLA_IDR 0xc000 | |
45 | #define PLA_RCR 0xc010 | |
46 | #define PLA_RMS 0xc016 | |
47 | #define PLA_RXFIFO_CTRL0 0xc0a0 | |
48 | #define PLA_RXFIFO_CTRL1 0xc0a4 | |
49 | #define PLA_RXFIFO_CTRL2 0xc0a8 | |
65bab84c | 50 | #define PLA_DMY_REG0 0xc0b0 |
ac718b69 | 51 | #define PLA_FMC 0xc0b4 |
52 | #define PLA_CFG_WOL 0xc0b6 | |
43779f8d | 53 | #define PLA_TEREDO_CFG 0xc0bc |
65b82d69 | 54 | #define PLA_TEREDO_WAKE_BASE 0xc0c4 |
ac718b69 | 55 | #define PLA_MAR 0xcd00 |
43779f8d | 56 | #define PLA_BACKUP 0xd000 |
ac718b69 | 57 | #define PAL_BDC_CR 0xd1a0 |
43779f8d | 58 | #define PLA_TEREDO_TIMER 0xd2cc |
59 | #define PLA_REALWOW_TIMER 0xd2e8 | |
65b82d69 | 60 | #define PLA_EFUSE_DATA 0xdd00 |
61 | #define PLA_EFUSE_CMD 0xdd02 | |
ac718b69 | 62 | #define PLA_LEDSEL 0xdd90 |
63 | #define PLA_LED_FEATURE 0xdd92 | |
64 | #define PLA_PHYAR 0xde00 | |
43779f8d | 65 | #define PLA_BOOT_CTRL 0xe004 |
ac718b69 | 66 | #define PLA_GPHY_INTR_IMR 0xe022 |
67 | #define PLA_EEE_CR 0xe040 | |
68 | #define PLA_EEEP_CR 0xe080 | |
69 | #define PLA_MAC_PWR_CTRL 0xe0c0 | |
43779f8d | 70 | #define PLA_MAC_PWR_CTRL2 0xe0ca |
71 | #define PLA_MAC_PWR_CTRL3 0xe0cc | |
72 | #define PLA_MAC_PWR_CTRL4 0xe0ce | |
73 | #define PLA_WDT6_CTRL 0xe428 | |
ac718b69 | 74 | #define PLA_TCR0 0xe610 |
75 | #define PLA_TCR1 0xe612 | |
69b4b7a4 | 76 | #define PLA_MTPS 0xe615 |
ac718b69 | 77 | #define PLA_TXFIFO_CTRL 0xe618 |
4f1d4d54 | 78 | #define PLA_RSTTALLY 0xe800 |
ac718b69 | 79 | #define PLA_CR 0xe813 |
80 | #define PLA_CRWECR 0xe81c | |
21ff2e89 | 81 | #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */ |
82 | #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */ | |
ac718b69 | 83 | #define PLA_CONFIG5 0xe822 |
84 | #define PLA_PHY_PWR 0xe84c | |
85 | #define PLA_OOB_CTRL 0xe84f | |
86 | #define PLA_CPCR 0xe854 | |
87 | #define PLA_MISC_0 0xe858 | |
88 | #define PLA_MISC_1 0xe85a | |
89 | #define PLA_OCP_GPHY_BASE 0xe86c | |
4f1d4d54 | 90 | #define PLA_TALLYCNT 0xe890 |
ac718b69 | 91 | #define PLA_SFF_STS_7 0xe8de |
92 | #define PLA_PHYSTATUS 0xe908 | |
93 | #define PLA_BP_BA 0xfc26 | |
94 | #define PLA_BP_0 0xfc28 | |
95 | #define PLA_BP_1 0xfc2a | |
96 | #define PLA_BP_2 0xfc2c | |
97 | #define PLA_BP_3 0xfc2e | |
98 | #define PLA_BP_4 0xfc30 | |
99 | #define PLA_BP_5 0xfc32 | |
100 | #define PLA_BP_6 0xfc34 | |
101 | #define PLA_BP_7 0xfc36 | |
43779f8d | 102 | #define PLA_BP_EN 0xfc38 |
ac718b69 | 103 | |
65bab84c | 104 | #define USB_USB2PHY 0xb41e |
105 | #define USB_SSPHYLINK2 0xb428 | |
43779f8d | 106 | #define USB_U2P3_CTRL 0xb460 |
65bab84c | 107 | #define USB_CSR_DUMMY1 0xb464 |
108 | #define USB_CSR_DUMMY2 0xb466 | |
ac718b69 | 109 | #define USB_DEV_STAT 0xb808 |
65bab84c | 110 | #define USB_CONNECT_TIMER 0xcbf8 |
65b82d69 | 111 | #define USB_MSC_TIMER 0xcbfc |
65bab84c | 112 | #define USB_BURST_SIZE 0xcfc0 |
65b82d69 | 113 | #define USB_LPM_CONFIG 0xcfd8 |
ac718b69 | 114 | #define USB_USB_CTRL 0xd406 |
115 | #define USB_PHY_CTRL 0xd408 | |
116 | #define USB_TX_AGG 0xd40a | |
117 | #define USB_RX_BUF_TH 0xd40c | |
118 | #define USB_USB_TIMER 0xd428 | |
464ec10a | 119 | #define USB_RX_EARLY_TIMEOUT 0xd42c |
120 | #define USB_RX_EARLY_SIZE 0xd42e | |
65b82d69 | 121 | #define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */ |
122 | #define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */ | |
ac718b69 | 123 | #define USB_TX_DMA 0xd434 |
65b82d69 | 124 | #define USB_UPT_RXDMA_OWN 0xd437 |
43779f8d | 125 | #define USB_TOLERANCE 0xd490 |
126 | #define USB_LPM_CTRL 0xd41a | |
93fe9b18 | 127 | #define USB_BMU_RESET 0xd4b0 |
65b82d69 | 128 | #define USB_U1U2_TIMER 0xd4da |
ac718b69 | 129 | #define USB_UPS_CTRL 0xd800 |
43779f8d | 130 | #define USB_POWER_CUT 0xd80a |
65b82d69 | 131 | #define USB_MISC_0 0xd81a |
91891485 | 132 | #define USB_MISC_1 0xd81f |
43779f8d | 133 | #define USB_AFE_CTRL2 0xd824 |
65b82d69 | 134 | #define USB_UPS_CFG 0xd842 |
135 | #define USB_UPS_FLAGS 0xd848 | |
43779f8d | 136 | #define USB_WDT11_CTRL 0xe43c |
ac718b69 | 137 | #define USB_BP_BA 0xfc26 |
138 | #define USB_BP_0 0xfc28 | |
139 | #define USB_BP_1 0xfc2a | |
140 | #define USB_BP_2 0xfc2c | |
141 | #define USB_BP_3 0xfc2e | |
142 | #define USB_BP_4 0xfc30 | |
143 | #define USB_BP_5 0xfc32 | |
144 | #define USB_BP_6 0xfc34 | |
145 | #define USB_BP_7 0xfc36 | |
43779f8d | 146 | #define USB_BP_EN 0xfc38 |
65b82d69 | 147 | #define USB_BP_8 0xfc38 |
148 | #define USB_BP_9 0xfc3a | |
149 | #define USB_BP_10 0xfc3c | |
150 | #define USB_BP_11 0xfc3e | |
151 | #define USB_BP_12 0xfc40 | |
152 | #define USB_BP_13 0xfc42 | |
153 | #define USB_BP_14 0xfc44 | |
154 | #define USB_BP_15 0xfc46 | |
155 | #define USB_BP2_EN 0xfc48 | |
ac718b69 | 156 | |
157 | /* OCP Registers */ | |
158 | #define OCP_ALDPS_CONFIG 0x2010 | |
159 | #define OCP_EEE_CONFIG1 0x2080 | |
160 | #define OCP_EEE_CONFIG2 0x2092 | |
161 | #define OCP_EEE_CONFIG3 0x2094 | |
ac244d3e | 162 | #define OCP_BASE_MII 0xa400 |
ac718b69 | 163 | #define OCP_EEE_AR 0xa41a |
164 | #define OCP_EEE_DATA 0xa41c | |
43779f8d | 165 | #define OCP_PHY_STATUS 0xa420 |
65b82d69 | 166 | #define OCP_NCTL_CFG 0xa42c |
43779f8d | 167 | #define OCP_POWER_CFG 0xa430 |
168 | #define OCP_EEE_CFG 0xa432 | |
169 | #define OCP_SRAM_ADDR 0xa436 | |
170 | #define OCP_SRAM_DATA 0xa438 | |
171 | #define OCP_DOWN_SPEED 0xa442 | |
df35d283 | 172 | #define OCP_EEE_ABLE 0xa5c4 |
4c4a6b1b | 173 | #define OCP_EEE_ADV 0xa5d0 |
df35d283 | 174 | #define OCP_EEE_LPABLE 0xa5d2 |
2dd49e0f | 175 | #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */ |
65b82d69 | 176 | #define OCP_PHY_PATCH_STAT 0xb800 |
177 | #define OCP_PHY_PATCH_CMD 0xb820 | |
178 | #define OCP_ADC_IOFFSET 0xbcfc | |
43779f8d | 179 | #define OCP_ADC_CFG 0xbc06 |
65b82d69 | 180 | #define OCP_SYSCLK_CFG 0xc416 |
43779f8d | 181 | |
182 | /* SRAM Register */ | |
65b82d69 | 183 | #define SRAM_GREEN_CFG 0x8011 |
43779f8d | 184 | #define SRAM_LPF_CFG 0x8012 |
185 | #define SRAM_10M_AMP1 0x8080 | |
186 | #define SRAM_10M_AMP2 0x8082 | |
187 | #define SRAM_IMPEDANCE 0x8084 | |
ac718b69 | 188 | |
189 | /* PLA_RCR */ | |
190 | #define RCR_AAP 0x00000001 | |
191 | #define RCR_APM 0x00000002 | |
192 | #define RCR_AM 0x00000004 | |
193 | #define RCR_AB 0x00000008 | |
194 | #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB) | |
195 | ||
196 | /* PLA_RXFIFO_CTRL0 */ | |
197 | #define RXFIFO_THR1_NORMAL 0x00080002 | |
198 | #define RXFIFO_THR1_OOB 0x01800003 | |
199 | ||
200 | /* PLA_RXFIFO_CTRL1 */ | |
201 | #define RXFIFO_THR2_FULL 0x00000060 | |
202 | #define RXFIFO_THR2_HIGH 0x00000038 | |
203 | #define RXFIFO_THR2_OOB 0x0000004a | |
43779f8d | 204 | #define RXFIFO_THR2_NORMAL 0x00a0 |
ac718b69 | 205 | |
206 | /* PLA_RXFIFO_CTRL2 */ | |
207 | #define RXFIFO_THR3_FULL 0x00000078 | |
208 | #define RXFIFO_THR3_HIGH 0x00000048 | |
209 | #define RXFIFO_THR3_OOB 0x0000005a | |
43779f8d | 210 | #define RXFIFO_THR3_NORMAL 0x0110 |
ac718b69 | 211 | |
212 | /* PLA_TXFIFO_CTRL */ | |
213 | #define TXFIFO_THR_NORMAL 0x00400008 | |
43779f8d | 214 | #define TXFIFO_THR_NORMAL2 0x01000008 |
ac718b69 | 215 | |
65bab84c | 216 | /* PLA_DMY_REG0 */ |
217 | #define ECM_ALDPS 0x0002 | |
218 | ||
ac718b69 | 219 | /* PLA_FMC */ |
220 | #define FMC_FCR_MCU_EN 0x0001 | |
221 | ||
222 | /* PLA_EEEP_CR */ | |
223 | #define EEEP_CR_EEEP_TX 0x0002 | |
224 | ||
43779f8d | 225 | /* PLA_WDT6_CTRL */ |
226 | #define WDT6_SET_MODE 0x0010 | |
227 | ||
ac718b69 | 228 | /* PLA_TCR0 */ |
229 | #define TCR0_TX_EMPTY 0x0800 | |
230 | #define TCR0_AUTO_FIFO 0x0080 | |
231 | ||
232 | /* PLA_TCR1 */ | |
233 | #define VERSION_MASK 0x7cf0 | |
234 | ||
69b4b7a4 | 235 | /* PLA_MTPS */ |
236 | #define MTPS_JUMBO (12 * 1024 / 64) | |
237 | #define MTPS_DEFAULT (6 * 1024 / 64) | |
238 | ||
4f1d4d54 | 239 | /* PLA_RSTTALLY */ |
240 | #define TALLY_RESET 0x0001 | |
241 | ||
ac718b69 | 242 | /* PLA_CR */ |
243 | #define CR_RST 0x10 | |
244 | #define CR_RE 0x08 | |
245 | #define CR_TE 0x04 | |
246 | ||
247 | /* PLA_CRWECR */ | |
248 | #define CRWECR_NORAML 0x00 | |
249 | #define CRWECR_CONFIG 0xc0 | |
250 | ||
251 | /* PLA_OOB_CTRL */ | |
252 | #define NOW_IS_OOB 0x80 | |
253 | #define TXFIFO_EMPTY 0x20 | |
254 | #define RXFIFO_EMPTY 0x10 | |
255 | #define LINK_LIST_READY 0x02 | |
256 | #define DIS_MCU_CLROOB 0x01 | |
257 | #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY) | |
258 | ||
259 | /* PLA_MISC_1 */ | |
260 | #define RXDY_GATED_EN 0x0008 | |
261 | ||
262 | /* PLA_SFF_STS_7 */ | |
263 | #define RE_INIT_LL 0x8000 | |
264 | #define MCU_BORW_EN 0x4000 | |
265 | ||
266 | /* PLA_CPCR */ | |
267 | #define CPCR_RX_VLAN 0x0040 | |
268 | ||
269 | /* PLA_CFG_WOL */ | |
270 | #define MAGIC_EN 0x0001 | |
271 | ||
43779f8d | 272 | /* PLA_TEREDO_CFG */ |
273 | #define TEREDO_SEL 0x8000 | |
274 | #define TEREDO_WAKE_MASK 0x7f00 | |
275 | #define TEREDO_RS_EVENT_MASK 0x00fe | |
276 | #define OOB_TEREDO_EN 0x0001 | |
277 | ||
ac718b69 | 278 | /* PAL_BDC_CR */ |
279 | #define ALDPS_PROXY_MODE 0x0001 | |
280 | ||
65b82d69 | 281 | /* PLA_EFUSE_CMD */ |
282 | #define EFUSE_READ_CMD BIT(15) | |
283 | #define EFUSE_DATA_BIT16 BIT(7) | |
284 | ||
21ff2e89 | 285 | /* PLA_CONFIG34 */ |
286 | #define LINK_ON_WAKE_EN 0x0010 | |
287 | #define LINK_OFF_WAKE_EN 0x0008 | |
288 | ||
ac718b69 | 289 | /* PLA_CONFIG5 */ |
21ff2e89 | 290 | #define BWF_EN 0x0040 |
291 | #define MWF_EN 0x0020 | |
292 | #define UWF_EN 0x0010 | |
ac718b69 | 293 | #define LAN_WAKE_EN 0x0002 |
294 | ||
295 | /* PLA_LED_FEATURE */ | |
296 | #define LED_MODE_MASK 0x0700 | |
297 | ||
298 | /* PLA_PHY_PWR */ | |
299 | #define TX_10M_IDLE_EN 0x0080 | |
300 | #define PFM_PWM_SWITCH 0x0040 | |
301 | ||
302 | /* PLA_MAC_PWR_CTRL */ | |
303 | #define D3_CLK_GATED_EN 0x00004000 | |
304 | #define MCU_CLK_RATIO 0x07010f07 | |
305 | #define MCU_CLK_RATIO_MASK 0x0f0f0f0f | |
43779f8d | 306 | #define ALDPS_SPDWN_RATIO 0x0f87 |
307 | ||
308 | /* PLA_MAC_PWR_CTRL2 */ | |
309 | #define EEE_SPDWN_RATIO 0x8007 | |
65b82d69 | 310 | #define MAC_CLK_SPDWN_EN BIT(15) |
43779f8d | 311 | |
312 | /* PLA_MAC_PWR_CTRL3 */ | |
313 | #define PKT_AVAIL_SPDWN_EN 0x0100 | |
314 | #define SUSPEND_SPDWN_EN 0x0004 | |
315 | #define U1U2_SPDWN_EN 0x0002 | |
316 | #define L1_SPDWN_EN 0x0001 | |
317 | ||
318 | /* PLA_MAC_PWR_CTRL4 */ | |
319 | #define PWRSAVE_SPDWN_EN 0x1000 | |
320 | #define RXDV_SPDWN_EN 0x0800 | |
321 | #define TX10MIDLE_EN 0x0100 | |
322 | #define TP100_SPDWN_EN 0x0020 | |
323 | #define TP500_SPDWN_EN 0x0010 | |
324 | #define TP1000_SPDWN_EN 0x0008 | |
325 | #define EEE_SPDWN_EN 0x0001 | |
ac718b69 | 326 | |
327 | /* PLA_GPHY_INTR_IMR */ | |
328 | #define GPHY_STS_MSK 0x0001 | |
329 | #define SPEED_DOWN_MSK 0x0002 | |
330 | #define SPDWN_RXDV_MSK 0x0004 | |
331 | #define SPDWN_LINKCHG_MSK 0x0008 | |
332 | ||
333 | /* PLA_PHYAR */ | |
334 | #define PHYAR_FLAG 0x80000000 | |
335 | ||
336 | /* PLA_EEE_CR */ | |
337 | #define EEE_RX_EN 0x0001 | |
338 | #define EEE_TX_EN 0x0002 | |
339 | ||
43779f8d | 340 | /* PLA_BOOT_CTRL */ |
341 | #define AUTOLOAD_DONE 0x0002 | |
342 | ||
65bab84c | 343 | /* USB_USB2PHY */ |
344 | #define USB2PHY_SUSPEND 0x0001 | |
345 | #define USB2PHY_L1 0x0002 | |
346 | ||
347 | /* USB_SSPHYLINK2 */ | |
348 | #define pwd_dn_scale_mask 0x3ffe | |
349 | #define pwd_dn_scale(x) ((x) << 1) | |
350 | ||
351 | /* USB_CSR_DUMMY1 */ | |
352 | #define DYNAMIC_BURST 0x0001 | |
353 | ||
354 | /* USB_CSR_DUMMY2 */ | |
355 | #define EP4_FULL_FC 0x0001 | |
356 | ||
ac718b69 | 357 | /* USB_DEV_STAT */ |
358 | #define STAT_SPEED_MASK 0x0006 | |
359 | #define STAT_SPEED_HIGH 0x0000 | |
a3cc465d | 360 | #define STAT_SPEED_FULL 0x0002 |
ac718b69 | 361 | |
65b82d69 | 362 | /* USB_LPM_CONFIG */ |
363 | #define LPM_U1U2_EN BIT(0) | |
364 | ||
ac718b69 | 365 | /* USB_TX_AGG */ |
366 | #define TX_AGG_MAX_THRESHOLD 0x03 | |
367 | ||
368 | /* USB_RX_BUF_TH */ | |
43779f8d | 369 | #define RX_THR_SUPPER 0x0c350180 |
8e1f51bd | 370 | #define RX_THR_HIGH 0x7a120180 |
43779f8d | 371 | #define RX_THR_SLOW 0xffff0180 |
65b82d69 | 372 | #define RX_THR_B 0x00010001 |
ac718b69 | 373 | |
374 | /* USB_TX_DMA */ | |
375 | #define TEST_MODE_DISABLE 0x00000001 | |
376 | #define TX_SIZE_ADJUST1 0x00000100 | |
377 | ||
93fe9b18 | 378 | /* USB_BMU_RESET */ |
379 | #define BMU_RESET_EP_IN 0x01 | |
380 | #define BMU_RESET_EP_OUT 0x02 | |
381 | ||
65b82d69 | 382 | /* USB_UPT_RXDMA_OWN */ |
383 | #define OWN_UPDATE BIT(0) | |
384 | #define OWN_CLEAR BIT(1) | |
385 | ||
ac718b69 | 386 | /* USB_UPS_CTRL */ |
387 | #define POWER_CUT 0x0100 | |
388 | ||
389 | /* USB_PM_CTRL_STATUS */ | |
8e1f51bd | 390 | #define RESUME_INDICATE 0x0001 |
ac718b69 | 391 | |
392 | /* USB_USB_CTRL */ | |
393 | #define RX_AGG_DISABLE 0x0010 | |
e90fba8d | 394 | #define RX_ZERO_EN 0x0080 |
ac718b69 | 395 | |
43779f8d | 396 | /* USB_U2P3_CTRL */ |
397 | #define U2P3_ENABLE 0x0001 | |
398 | ||
399 | /* USB_POWER_CUT */ | |
400 | #define PWR_EN 0x0001 | |
401 | #define PHASE2_EN 0x0008 | |
65b82d69 | 402 | #define UPS_EN BIT(4) |
403 | #define USP_PREWAKE BIT(5) | |
43779f8d | 404 | |
405 | /* USB_MISC_0 */ | |
406 | #define PCUT_STATUS 0x0001 | |
407 | ||
464ec10a | 408 | /* USB_RX_EARLY_TIMEOUT */ |
409 | #define COALESCE_SUPER 85000U | |
410 | #define COALESCE_HIGH 250000U | |
411 | #define COALESCE_SLOW 524280U | |
43779f8d | 412 | |
413 | /* USB_WDT11_CTRL */ | |
414 | #define TIMER11_EN 0x0001 | |
415 | ||
416 | /* USB_LPM_CTRL */ | |
65bab84c | 417 | /* bit 4 ~ 5: fifo empty boundary */ |
418 | #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */ | |
419 | /* bit 2 ~ 3: LMP timer */ | |
43779f8d | 420 | #define LPM_TIMER_MASK 0x0c |
421 | #define LPM_TIMER_500MS 0x04 /* 500 ms */ | |
422 | #define LPM_TIMER_500US 0x0c /* 500 us */ | |
65bab84c | 423 | #define ROK_EXIT_LPM 0x02 |
43779f8d | 424 | |
425 | /* USB_AFE_CTRL2 */ | |
426 | #define SEN_VAL_MASK 0xf800 | |
427 | #define SEN_VAL_NORMAL 0xa000 | |
428 | #define SEL_RXIDLE 0x0100 | |
429 | ||
65b82d69 | 430 | /* USB_UPS_CFG */ |
431 | #define SAW_CNT_1MS_MASK 0x0fff | |
432 | ||
433 | /* USB_UPS_FLAGS */ | |
434 | #define UPS_FLAGS_R_TUNE BIT(0) | |
435 | #define UPS_FLAGS_EN_10M_CKDIV BIT(1) | |
436 | #define UPS_FLAGS_250M_CKDIV BIT(2) | |
437 | #define UPS_FLAGS_EN_ALDPS BIT(3) | |
438 | #define UPS_FLAGS_CTAP_SHORT_DIS BIT(4) | |
439 | #define UPS_FLAGS_SPEED_MASK (0xf << 16) | |
440 | #define ups_flags_speed(x) ((x) << 16) | |
441 | #define UPS_FLAGS_EN_EEE BIT(20) | |
442 | #define UPS_FLAGS_EN_500M_EEE BIT(21) | |
443 | #define UPS_FLAGS_EN_EEE_CKDIV BIT(22) | |
444 | #define UPS_FLAGS_EEE_PLLOFF_GIGA BIT(24) | |
445 | #define UPS_FLAGS_EEE_CMOD_LV_EN BIT(25) | |
446 | #define UPS_FLAGS_EN_GREEN BIT(26) | |
447 | #define UPS_FLAGS_EN_FLOW_CTR BIT(27) | |
448 | ||
449 | enum spd_duplex { | |
450 | NWAY_10M_HALF = 1, | |
451 | NWAY_10M_FULL, | |
452 | NWAY_100M_HALF, | |
453 | NWAY_100M_FULL, | |
454 | NWAY_1000M_FULL, | |
455 | FORCE_10M_HALF, | |
456 | FORCE_10M_FULL, | |
457 | FORCE_100M_HALF, | |
458 | FORCE_100M_FULL, | |
459 | }; | |
460 | ||
ac718b69 | 461 | /* OCP_ALDPS_CONFIG */ |
462 | #define ENPWRSAVE 0x8000 | |
463 | #define ENPDNPS 0x0200 | |
464 | #define LINKENA 0x0100 | |
465 | #define DIS_SDSAVE 0x0010 | |
466 | ||
43779f8d | 467 | /* OCP_PHY_STATUS */ |
468 | #define PHY_STAT_MASK 0x0007 | |
c564b871 | 469 | #define PHY_STAT_EXT_INIT 2 |
43779f8d | 470 | #define PHY_STAT_LAN_ON 3 |
471 | #define PHY_STAT_PWRDN 5 | |
472 | ||
65b82d69 | 473 | /* OCP_NCTL_CFG */ |
474 | #define PGA_RETURN_EN BIT(1) | |
475 | ||
43779f8d | 476 | /* OCP_POWER_CFG */ |
477 | #define EEE_CLKDIV_EN 0x8000 | |
478 | #define EN_ALDPS 0x0004 | |
479 | #define EN_10M_PLLOFF 0x0001 | |
480 | ||
ac718b69 | 481 | /* OCP_EEE_CONFIG1 */ |
482 | #define RG_TXLPI_MSK_HFDUP 0x8000 | |
483 | #define RG_MATCLR_EN 0x4000 | |
484 | #define EEE_10_CAP 0x2000 | |
485 | #define EEE_NWAY_EN 0x1000 | |
486 | #define TX_QUIET_EN 0x0200 | |
487 | #define RX_QUIET_EN 0x0100 | |
d24f6134 | 488 | #define sd_rise_time_mask 0x0070 |
4c4a6b1b | 489 | #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */ |
ac718b69 | 490 | #define RG_RXLPI_MSK_HFDUP 0x0008 |
491 | #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */ | |
492 | ||
493 | /* OCP_EEE_CONFIG2 */ | |
494 | #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */ | |
495 | #define RG_DACQUIET_EN 0x0400 | |
496 | #define RG_LDVQUIET_EN 0x0200 | |
497 | #define RG_CKRSEL 0x0020 | |
498 | #define RG_EEEPRG_EN 0x0010 | |
499 | ||
500 | /* OCP_EEE_CONFIG3 */ | |
d24f6134 | 501 | #define fast_snr_mask 0xff80 |
4c4a6b1b | 502 | #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */ |
ac718b69 | 503 | #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */ |
504 | #define MSK_PH 0x0006 /* bit 0 ~ 3 */ | |
505 | ||
506 | /* OCP_EEE_AR */ | |
507 | /* bit[15:14] function */ | |
508 | #define FUN_ADDR 0x0000 | |
509 | #define FUN_DATA 0x4000 | |
510 | /* bit[4:0] device addr */ | |
ac718b69 | 511 | |
43779f8d | 512 | /* OCP_EEE_CFG */ |
513 | #define CTAP_SHORT_EN 0x0040 | |
514 | #define EEE10_EN 0x0010 | |
515 | ||
516 | /* OCP_DOWN_SPEED */ | |
65b82d69 | 517 | #define EN_EEE_CMODE BIT(14) |
518 | #define EN_EEE_1000 BIT(13) | |
519 | #define EN_EEE_100 BIT(12) | |
520 | #define EN_10M_CLKDIV BIT(11) | |
43779f8d | 521 | #define EN_10M_BGOFF 0x0080 |
522 | ||
2dd49e0f | 523 | /* OCP_PHY_STATE */ |
524 | #define TXDIS_STATE 0x01 | |
525 | #define ABD_STATE 0x02 | |
526 | ||
65b82d69 | 527 | /* OCP_PHY_PATCH_STAT */ |
528 | #define PATCH_READY BIT(6) | |
529 | ||
530 | /* OCP_PHY_PATCH_CMD */ | |
531 | #define PATCH_REQUEST BIT(4) | |
532 | ||
43779f8d | 533 | /* OCP_ADC_CFG */ |
534 | #define CKADSEL_L 0x0100 | |
535 | #define ADC_EN 0x0080 | |
536 | #define EN_EMI_L 0x0040 | |
537 | ||
65b82d69 | 538 | /* OCP_SYSCLK_CFG */ |
539 | #define clk_div_expo(x) (min(x, 5) << 8) | |
540 | ||
541 | /* SRAM_GREEN_CFG */ | |
542 | #define GREEN_ETH_EN BIT(15) | |
543 | #define R_TUNE_EN BIT(11) | |
544 | ||
43779f8d | 545 | /* SRAM_LPF_CFG */ |
546 | #define LPF_AUTO_TUNE 0x8000 | |
547 | ||
548 | /* SRAM_10M_AMP1 */ | |
549 | #define GDAC_IB_UPALL 0x0008 | |
550 | ||
551 | /* SRAM_10M_AMP2 */ | |
552 | #define AMP_DN 0x0200 | |
553 | ||
554 | /* SRAM_IMPEDANCE */ | |
555 | #define RX_DRIVING_MASK 0x6000 | |
556 | ||
34ee32c9 ML |
557 | /* MAC PASSTHRU */ |
558 | #define AD_MASK 0xfee0 | |
91891485 | 559 | #define BND_MASK 0x0004 |
3c233a68 | 560 | #define BD_MASK 0x0001 |
34ee32c9 ML |
561 | #define EFUSE 0xcfdb |
562 | #define PASS_THRU_MASK 0x1 | |
563 | ||
ac718b69 | 564 | enum rtl_register_content { |
43779f8d | 565 | _1000bps = 0x10, |
ac718b69 | 566 | _100bps = 0x08, |
567 | _10bps = 0x04, | |
568 | LINK_STATUS = 0x02, | |
569 | FULL_DUP = 0x01, | |
570 | }; | |
571 | ||
1764bcd9 | 572 | #define RTL8152_MAX_TX 4 |
ebc2ec48 | 573 | #define RTL8152_MAX_RX 10 |
40a82917 | 574 | #define INTBUFSIZE 2 |
8e1f51bd | 575 | #define TX_ALIGN 4 |
576 | #define RX_ALIGN 8 | |
40a82917 | 577 | |
578 | #define INTR_LINK 0x0004 | |
ebc2ec48 | 579 | |
ac718b69 | 580 | #define RTL8152_REQT_READ 0xc0 |
581 | #define RTL8152_REQT_WRITE 0x40 | |
582 | #define RTL8152_REQ_GET_REGS 0x05 | |
583 | #define RTL8152_REQ_SET_REGS 0x05 | |
584 | ||
585 | #define BYTE_EN_DWORD 0xff | |
586 | #define BYTE_EN_WORD 0x33 | |
587 | #define BYTE_EN_BYTE 0x11 | |
588 | #define BYTE_EN_SIX_BYTES 0x3f | |
589 | #define BYTE_EN_START_MASK 0x0f | |
590 | #define BYTE_EN_END_MASK 0xf0 | |
591 | ||
69b4b7a4 | 592 | #define RTL8153_MAX_PACKET 9216 /* 9K */ |
b65c0c9b | 593 | #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - \ |
594 | ETH_FCS_LEN) | |
595 | #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN) | |
69b4b7a4 | 596 | #define RTL8153_RMS RTL8153_MAX_PACKET |
b8125404 | 597 | #define RTL8152_TX_TIMEOUT (5 * HZ) |
d823ab68 | 598 | #define RTL8152_NAPI_WEIGHT 64 |
b65c0c9b | 599 | #define rx_reserved_size(x) ((x) + VLAN_ETH_HLEN + ETH_FCS_LEN + \ |
b20cb60e | 600 | sizeof(struct rx_desc) + RX_ALIGN) |
ac718b69 | 601 | |
602 | /* rtl8152 flags */ | |
603 | enum rtl8152_flags { | |
604 | RTL8152_UNPLUG = 0, | |
ac718b69 | 605 | RTL8152_SET_RX_MODE, |
40a82917 | 606 | WORK_ENABLE, |
607 | RTL8152_LINK_CHG, | |
9a4be1bd | 608 | SELECTIVE_SUSPEND, |
aa66a5f1 | 609 | PHY_RESET, |
d823ab68 | 610 | SCHEDULE_NAPI, |
65b82d69 | 611 | GREEN_ETHERNET, |
0b165514 | 612 | DELL_TB_RX_AGG_BUG, |
71512e43 | 613 | LENOVO_MACPASSTHRU, |
ac718b69 | 614 | }; |
615 | ||
616 | /* Define these values to match your device */ | |
617 | #define VENDOR_ID_REALTEK 0x0bda | |
d5b07ccc | 618 | #define VENDOR_ID_MICROSOFT 0x045e |
43779f8d | 619 | #define VENDOR_ID_SAMSUNG 0x04e8 |
347eec34 | 620 | #define VENDOR_ID_LENOVO 0x17ef |
90841047 | 621 | #define VENDOR_ID_LINKSYS 0x13b1 |
d065c3c1 | 622 | #define VENDOR_ID_NVIDIA 0x0955 |
9d11b066 | 623 | #define VENDOR_ID_TPLINK 0x2357 |
ac718b69 | 624 | |
625 | #define MCU_TYPE_PLA 0x0100 | |
626 | #define MCU_TYPE_USB 0x0000 | |
627 | ||
4f1d4d54 | 628 | struct tally_counter { |
629 | __le64 tx_packets; | |
630 | __le64 rx_packets; | |
631 | __le64 tx_errors; | |
632 | __le32 rx_errors; | |
633 | __le16 rx_missed; | |
634 | __le16 align_errors; | |
635 | __le32 tx_one_collision; | |
636 | __le32 tx_multi_collision; | |
637 | __le64 rx_unicast; | |
638 | __le64 rx_broadcast; | |
639 | __le32 rx_multicast; | |
640 | __le16 tx_aborted; | |
f37119c5 | 641 | __le16 tx_underrun; |
4f1d4d54 | 642 | }; |
643 | ||
ac718b69 | 644 | struct rx_desc { |
500b6d7e | 645 | __le32 opts1; |
ac718b69 | 646 | #define RX_LEN_MASK 0x7fff |
565cab0a | 647 | |
500b6d7e | 648 | __le32 opts2; |
f5aaaa6d | 649 | #define RD_UDP_CS BIT(23) |
650 | #define RD_TCP_CS BIT(22) | |
651 | #define RD_IPV6_CS BIT(20) | |
652 | #define RD_IPV4_CS BIT(19) | |
565cab0a | 653 | |
500b6d7e | 654 | __le32 opts3; |
f5aaaa6d | 655 | #define IPF BIT(23) /* IP checksum fail */ |
656 | #define UDPF BIT(22) /* UDP checksum fail */ | |
657 | #define TCPF BIT(21) /* TCP checksum fail */ | |
658 | #define RX_VLAN_TAG BIT(16) | |
565cab0a | 659 | |
500b6d7e | 660 | __le32 opts4; |
661 | __le32 opts5; | |
662 | __le32 opts6; | |
ac718b69 | 663 | }; |
664 | ||
665 | struct tx_desc { | |
500b6d7e | 666 | __le32 opts1; |
f5aaaa6d | 667 | #define TX_FS BIT(31) /* First segment of a packet */ |
668 | #define TX_LS BIT(30) /* Final segment of a packet */ | |
669 | #define GTSENDV4 BIT(28) | |
670 | #define GTSENDV6 BIT(27) | |
60c89071 | 671 | #define GTTCPHO_SHIFT 18 |
6128d1bb | 672 | #define GTTCPHO_MAX 0x7fU |
60c89071 | 673 | #define TX_LEN_MAX 0x3ffffU |
5bd23881 | 674 | |
500b6d7e | 675 | __le32 opts2; |
f5aaaa6d | 676 | #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */ |
677 | #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */ | |
678 | #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */ | |
679 | #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */ | |
60c89071 | 680 | #define MSS_SHIFT 17 |
681 | #define MSS_MAX 0x7ffU | |
682 | #define TCPHO_SHIFT 17 | |
6128d1bb | 683 | #define TCPHO_MAX 0x7ffU |
f5aaaa6d | 684 | #define TX_VLAN_TAG BIT(16) |
ac718b69 | 685 | }; |
686 | ||
dff4e8ad | 687 | struct r8152; |
688 | ||
ebc2ec48 | 689 | struct rx_agg { |
690 | struct list_head list; | |
691 | struct urb *urb; | |
dff4e8ad | 692 | struct r8152 *context; |
ebc2ec48 | 693 | void *buffer; |
694 | void *head; | |
695 | }; | |
696 | ||
697 | struct tx_agg { | |
698 | struct list_head list; | |
699 | struct urb *urb; | |
dff4e8ad | 700 | struct r8152 *context; |
ebc2ec48 | 701 | void *buffer; |
702 | void *head; | |
703 | u32 skb_num; | |
704 | u32 skb_len; | |
705 | }; | |
706 | ||
ac718b69 | 707 | struct r8152 { |
708 | unsigned long flags; | |
709 | struct usb_device *udev; | |
d823ab68 | 710 | struct napi_struct napi; |
40a82917 | 711 | struct usb_interface *intf; |
ac718b69 | 712 | struct net_device *netdev; |
40a82917 | 713 | struct urb *intr_urb; |
ebc2ec48 | 714 | struct tx_agg tx_info[RTL8152_MAX_TX]; |
715 | struct rx_agg rx_info[RTL8152_MAX_RX]; | |
716 | struct list_head rx_done, tx_free; | |
d823ab68 | 717 | struct sk_buff_head tx_queue, rx_queue; |
ebc2ec48 | 718 | spinlock_t rx_lock, tx_lock; |
a028a9e0 | 719 | struct delayed_work schedule, hw_phy_work; |
ac718b69 | 720 | struct mii_if_info mii; |
b5403273 | 721 | struct mutex control; /* use for hw setting */ |
5ee3c60c | 722 | #ifdef CONFIG_PM_SLEEP |
723 | struct notifier_block pm_notifier; | |
724 | #endif | |
c81229c9 | 725 | |
726 | struct rtl_ops { | |
727 | void (*init)(struct r8152 *); | |
728 | int (*enable)(struct r8152 *); | |
729 | void (*disable)(struct r8152 *); | |
7e9da481 | 730 | void (*up)(struct r8152 *); |
c81229c9 | 731 | void (*down)(struct r8152 *); |
732 | void (*unload)(struct r8152 *); | |
df35d283 | 733 | int (*eee_get)(struct r8152 *, struct ethtool_eee *); |
734 | int (*eee_set)(struct r8152 *, struct ethtool_eee *); | |
2dd49e0f | 735 | bool (*in_nway)(struct r8152 *); |
a028a9e0 | 736 | void (*hw_phy_cfg)(struct r8152 *); |
2609af19 | 737 | void (*autosuspend_en)(struct r8152 *tp, bool enable); |
c81229c9 | 738 | } rtl_ops; |
739 | ||
40a82917 | 740 | int intr_interval; |
21ff2e89 | 741 | u32 saved_wolopts; |
ac718b69 | 742 | u32 msg_enable; |
dd1b119c | 743 | u32 tx_qlen; |
464ec10a | 744 | u32 coalesce; |
ac718b69 | 745 | u16 ocp_base; |
aa7e26b6 | 746 | u16 speed; |
40a82917 | 747 | u8 *intr_buff; |
ac718b69 | 748 | u8 version; |
aa7e26b6 | 749 | u8 duplex; |
750 | u8 autoneg; | |
ac718b69 | 751 | }; |
752 | ||
753 | enum rtl_version { | |
754 | RTL_VER_UNKNOWN = 0, | |
755 | RTL_VER_01, | |
43779f8d | 756 | RTL_VER_02, |
757 | RTL_VER_03, | |
758 | RTL_VER_04, | |
759 | RTL_VER_05, | |
fb02eb4a | 760 | RTL_VER_06, |
c27b32c2 | 761 | RTL_VER_07, |
65b82d69 | 762 | RTL_VER_08, |
763 | RTL_VER_09, | |
43779f8d | 764 | RTL_VER_MAX |
ac718b69 | 765 | }; |
766 | ||
60c89071 | 767 | enum tx_csum_stat { |
768 | TX_CSUM_SUCCESS = 0, | |
769 | TX_CSUM_TSO, | |
770 | TX_CSUM_NONE | |
771 | }; | |
772 | ||
ac718b69 | 773 | /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). |
774 | * The RTL chips use a 64 element hash table based on the Ethernet CRC. | |
775 | */ | |
776 | static const int multicast_filter_limit = 32; | |
52aec126 | 777 | static unsigned int agg_buf_sz = 16384; |
ac718b69 | 778 | |
52aec126 | 779 | #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \ |
b65c0c9b | 780 | VLAN_ETH_HLEN - ETH_FCS_LEN) |
60c89071 | 781 | |
ac718b69 | 782 | static |
783 | int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) | |
784 | { | |
31787f53 | 785 | int ret; |
786 | void *tmp; | |
787 | ||
788 | tmp = kmalloc(size, GFP_KERNEL); | |
789 | if (!tmp) | |
790 | return -ENOMEM; | |
791 | ||
792 | ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0), | |
b209af99 | 793 | RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, |
794 | value, index, tmp, size, 500); | |
297a7fc9 PM |
795 | if (ret < 0) |
796 | memset(data, 0xff, size); | |
797 | else | |
798 | memcpy(data, tmp, size); | |
31787f53 | 799 | |
31787f53 | 800 | kfree(tmp); |
801 | ||
802 | return ret; | |
ac718b69 | 803 | } |
804 | ||
805 | static | |
806 | int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) | |
807 | { | |
31787f53 | 808 | int ret; |
809 | void *tmp; | |
810 | ||
c4438f03 | 811 | tmp = kmemdup(data, size, GFP_KERNEL); |
31787f53 | 812 | if (!tmp) |
813 | return -ENOMEM; | |
814 | ||
31787f53 | 815 | ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0), |
b209af99 | 816 | RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE, |
817 | value, index, tmp, size, 500); | |
31787f53 | 818 | |
819 | kfree(tmp); | |
db8515ef | 820 | |
31787f53 | 821 | return ret; |
ac718b69 | 822 | } |
823 | ||
824 | static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size, | |
b209af99 | 825 | void *data, u16 type) |
ac718b69 | 826 | { |
45f4a19f | 827 | u16 limit = 64; |
828 | int ret = 0; | |
ac718b69 | 829 | |
830 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
831 | return -ENODEV; | |
832 | ||
833 | /* both size and indix must be 4 bytes align */ | |
834 | if ((size & 3) || !size || (index & 3) || !data) | |
835 | return -EPERM; | |
836 | ||
837 | if ((u32)index + (u32)size > 0xffff) | |
838 | return -EPERM; | |
839 | ||
840 | while (size) { | |
841 | if (size > limit) { | |
842 | ret = get_registers(tp, index, type, limit, data); | |
843 | if (ret < 0) | |
844 | break; | |
845 | ||
846 | index += limit; | |
847 | data += limit; | |
848 | size -= limit; | |
849 | } else { | |
850 | ret = get_registers(tp, index, type, size, data); | |
851 | if (ret < 0) | |
852 | break; | |
853 | ||
854 | index += size; | |
855 | data += size; | |
856 | size = 0; | |
857 | break; | |
858 | } | |
859 | } | |
860 | ||
67610496 | 861 | if (ret == -ENODEV) |
862 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
863 | ||
ac718b69 | 864 | return ret; |
865 | } | |
866 | ||
867 | static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, | |
b209af99 | 868 | u16 size, void *data, u16 type) |
ac718b69 | 869 | { |
45f4a19f | 870 | int ret; |
871 | u16 byteen_start, byteen_end, byen; | |
872 | u16 limit = 512; | |
ac718b69 | 873 | |
874 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
875 | return -ENODEV; | |
876 | ||
877 | /* both size and indix must be 4 bytes align */ | |
878 | if ((size & 3) || !size || (index & 3) || !data) | |
879 | return -EPERM; | |
880 | ||
881 | if ((u32)index + (u32)size > 0xffff) | |
882 | return -EPERM; | |
883 | ||
884 | byteen_start = byteen & BYTE_EN_START_MASK; | |
885 | byteen_end = byteen & BYTE_EN_END_MASK; | |
886 | ||
887 | byen = byteen_start | (byteen_start << 4); | |
888 | ret = set_registers(tp, index, type | byen, 4, data); | |
889 | if (ret < 0) | |
890 | goto error1; | |
891 | ||
892 | index += 4; | |
893 | data += 4; | |
894 | size -= 4; | |
895 | ||
896 | if (size) { | |
897 | size -= 4; | |
898 | ||
899 | while (size) { | |
900 | if (size > limit) { | |
901 | ret = set_registers(tp, index, | |
b209af99 | 902 | type | BYTE_EN_DWORD, |
903 | limit, data); | |
ac718b69 | 904 | if (ret < 0) |
905 | goto error1; | |
906 | ||
907 | index += limit; | |
908 | data += limit; | |
909 | size -= limit; | |
910 | } else { | |
911 | ret = set_registers(tp, index, | |
b209af99 | 912 | type | BYTE_EN_DWORD, |
913 | size, data); | |
ac718b69 | 914 | if (ret < 0) |
915 | goto error1; | |
916 | ||
917 | index += size; | |
918 | data += size; | |
919 | size = 0; | |
920 | break; | |
921 | } | |
922 | } | |
923 | ||
924 | byen = byteen_end | (byteen_end >> 4); | |
925 | ret = set_registers(tp, index, type | byen, 4, data); | |
926 | if (ret < 0) | |
927 | goto error1; | |
928 | } | |
929 | ||
930 | error1: | |
67610496 | 931 | if (ret == -ENODEV) |
932 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
933 | ||
ac718b69 | 934 | return ret; |
935 | } | |
936 | ||
937 | static inline | |
938 | int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) | |
939 | { | |
940 | return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA); | |
941 | } | |
942 | ||
943 | static inline | |
944 | int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) | |
945 | { | |
946 | return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA); | |
947 | } | |
948 | ||
ac718b69 | 949 | static inline |
950 | int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) | |
951 | { | |
952 | return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB); | |
953 | } | |
954 | ||
955 | static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index) | |
956 | { | |
c8826de8 | 957 | __le32 data; |
ac718b69 | 958 | |
c8826de8 | 959 | generic_ocp_read(tp, index, sizeof(data), &data, type); |
ac718b69 | 960 | |
961 | return __le32_to_cpu(data); | |
962 | } | |
963 | ||
964 | static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data) | |
965 | { | |
c8826de8 | 966 | __le32 tmp = __cpu_to_le32(data); |
967 | ||
968 | generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type); | |
ac718b69 | 969 | } |
970 | ||
971 | static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index) | |
972 | { | |
973 | u32 data; | |
c8826de8 | 974 | __le32 tmp; |
d8fbd274 | 975 | u16 byen = BYTE_EN_WORD; |
ac718b69 | 976 | u8 shift = index & 2; |
977 | ||
978 | index &= ~3; | |
d8fbd274 | 979 | byen <<= shift; |
ac718b69 | 980 | |
d8fbd274 | 981 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen); |
ac718b69 | 982 | |
c8826de8 | 983 | data = __le32_to_cpu(tmp); |
ac718b69 | 984 | data >>= (shift * 8); |
985 | data &= 0xffff; | |
986 | ||
987 | return (u16)data; | |
988 | } | |
989 | ||
990 | static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data) | |
991 | { | |
c8826de8 | 992 | u32 mask = 0xffff; |
993 | __le32 tmp; | |
ac718b69 | 994 | u16 byen = BYTE_EN_WORD; |
995 | u8 shift = index & 2; | |
996 | ||
997 | data &= mask; | |
998 | ||
999 | if (index & 2) { | |
1000 | byen <<= shift; | |
1001 | mask <<= (shift * 8); | |
1002 | data <<= (shift * 8); | |
1003 | index &= ~3; | |
1004 | } | |
1005 | ||
c8826de8 | 1006 | tmp = __cpu_to_le32(data); |
ac718b69 | 1007 | |
c8826de8 | 1008 | generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); |
ac718b69 | 1009 | } |
1010 | ||
1011 | static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index) | |
1012 | { | |
1013 | u32 data; | |
c8826de8 | 1014 | __le32 tmp; |
ac718b69 | 1015 | u8 shift = index & 3; |
1016 | ||
1017 | index &= ~3; | |
1018 | ||
c8826de8 | 1019 | generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); |
ac718b69 | 1020 | |
c8826de8 | 1021 | data = __le32_to_cpu(tmp); |
ac718b69 | 1022 | data >>= (shift * 8); |
1023 | data &= 0xff; | |
1024 | ||
1025 | return (u8)data; | |
1026 | } | |
1027 | ||
1028 | static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data) | |
1029 | { | |
c8826de8 | 1030 | u32 mask = 0xff; |
1031 | __le32 tmp; | |
ac718b69 | 1032 | u16 byen = BYTE_EN_BYTE; |
1033 | u8 shift = index & 3; | |
1034 | ||
1035 | data &= mask; | |
1036 | ||
1037 | if (index & 3) { | |
1038 | byen <<= shift; | |
1039 | mask <<= (shift * 8); | |
1040 | data <<= (shift * 8); | |
1041 | index &= ~3; | |
1042 | } | |
1043 | ||
c8826de8 | 1044 | tmp = __cpu_to_le32(data); |
ac718b69 | 1045 | |
c8826de8 | 1046 | generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); |
ac718b69 | 1047 | } |
1048 | ||
ac244d3e | 1049 | static u16 ocp_reg_read(struct r8152 *tp, u16 addr) |
e3fe0b1a | 1050 | { |
1051 | u16 ocp_base, ocp_index; | |
1052 | ||
1053 | ocp_base = addr & 0xf000; | |
1054 | if (ocp_base != tp->ocp_base) { | |
1055 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); | |
1056 | tp->ocp_base = ocp_base; | |
1057 | } | |
1058 | ||
1059 | ocp_index = (addr & 0x0fff) | 0xb000; | |
ac244d3e | 1060 | return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index); |
e3fe0b1a | 1061 | } |
1062 | ||
ac244d3e | 1063 | static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) |
ac718b69 | 1064 | { |
ac244d3e | 1065 | u16 ocp_base, ocp_index; |
ac718b69 | 1066 | |
ac244d3e | 1067 | ocp_base = addr & 0xf000; |
1068 | if (ocp_base != tp->ocp_base) { | |
1069 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); | |
1070 | tp->ocp_base = ocp_base; | |
ac718b69 | 1071 | } |
ac244d3e | 1072 | |
1073 | ocp_index = (addr & 0x0fff) | 0xb000; | |
1074 | ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data); | |
ac718b69 | 1075 | } |
1076 | ||
ac244d3e | 1077 | static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value) |
ac718b69 | 1078 | { |
ac244d3e | 1079 | ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value); |
1080 | } | |
ac718b69 | 1081 | |
ac244d3e | 1082 | static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr) |
1083 | { | |
1084 | return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2); | |
ac718b69 | 1085 | } |
1086 | ||
43779f8d | 1087 | static void sram_write(struct r8152 *tp, u16 addr, u16 data) |
1088 | { | |
1089 | ocp_reg_write(tp, OCP_SRAM_ADDR, addr); | |
1090 | ocp_reg_write(tp, OCP_SRAM_DATA, data); | |
1091 | } | |
1092 | ||
65b82d69 | 1093 | static u16 sram_read(struct r8152 *tp, u16 addr) |
1094 | { | |
1095 | ocp_reg_write(tp, OCP_SRAM_ADDR, addr); | |
1096 | return ocp_reg_read(tp, OCP_SRAM_DATA); | |
1097 | } | |
1098 | ||
ac718b69 | 1099 | static int read_mii_word(struct net_device *netdev, int phy_id, int reg) |
1100 | { | |
1101 | struct r8152 *tp = netdev_priv(netdev); | |
9a4be1bd | 1102 | int ret; |
ac718b69 | 1103 | |
6871438c | 1104 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
1105 | return -ENODEV; | |
1106 | ||
ac718b69 | 1107 | if (phy_id != R8152_PHY_ID) |
1108 | return -EINVAL; | |
1109 | ||
9a4be1bd | 1110 | ret = r8152_mdio_read(tp, reg); |
1111 | ||
9a4be1bd | 1112 | return ret; |
ac718b69 | 1113 | } |
1114 | ||
1115 | static | |
1116 | void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val) | |
1117 | { | |
1118 | struct r8152 *tp = netdev_priv(netdev); | |
1119 | ||
6871438c | 1120 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
1121 | return; | |
1122 | ||
ac718b69 | 1123 | if (phy_id != R8152_PHY_ID) |
1124 | return; | |
1125 | ||
1126 | r8152_mdio_write(tp, reg, val); | |
1127 | } | |
1128 | ||
b209af99 | 1129 | static int |
1130 | r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags); | |
ebc2ec48 | 1131 | |
8ba789ab | 1132 | static int rtl8152_set_mac_address(struct net_device *netdev, void *p) |
1133 | { | |
1134 | struct r8152 *tp = netdev_priv(netdev); | |
1135 | struct sockaddr *addr = p; | |
ea6a7112 | 1136 | int ret = -EADDRNOTAVAIL; |
8ba789ab | 1137 | |
1138 | if (!is_valid_ether_addr(addr->sa_data)) | |
ea6a7112 | 1139 | goto out1; |
1140 | ||
1141 | ret = usb_autopm_get_interface(tp->intf); | |
1142 | if (ret < 0) | |
1143 | goto out1; | |
8ba789ab | 1144 | |
b5403273 | 1145 | mutex_lock(&tp->control); |
1146 | ||
8ba789ab | 1147 | memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); |
1148 | ||
1149 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
1150 | pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data); | |
1151 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
1152 | ||
b5403273 | 1153 | mutex_unlock(&tp->control); |
1154 | ||
ea6a7112 | 1155 | usb_autopm_put_interface(tp->intf); |
1156 | out1: | |
1157 | return ret; | |
8ba789ab | 1158 | } |
1159 | ||
91891485 | 1160 | /* Devices containing proper chips can support a persistent |
34ee32c9 ML |
1161 | * host system provided MAC address. |
1162 | * Examples of this are Dell TB15 and Dell WD15 docks | |
1163 | */ | |
1164 | static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa) | |
1165 | { | |
1166 | acpi_status status; | |
1167 | struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; | |
1168 | union acpi_object *obj; | |
1169 | int ret = -EINVAL; | |
1170 | u32 ocp_data; | |
1171 | unsigned char buf[6]; | |
71512e43 KHF |
1172 | char *mac_obj_name; |
1173 | acpi_object_type mac_obj_type; | |
1174 | int mac_strlen; | |
1175 | ||
1176 | if (test_bit(LENOVO_MACPASSTHRU, &tp->flags)) { | |
1177 | mac_obj_name = "\\MACA"; | |
1178 | mac_obj_type = ACPI_TYPE_STRING; | |
1179 | mac_strlen = 0x16; | |
91891485 | 1180 | } else { |
71512e43 KHF |
1181 | /* test for -AD variant of RTL8153 */ |
1182 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); | |
1183 | if ((ocp_data & AD_MASK) == 0x1000) { | |
1184 | /* test for MAC address pass-through bit */ | |
1185 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE); | |
1186 | if ((ocp_data & PASS_THRU_MASK) != 1) { | |
1187 | netif_dbg(tp, probe, tp->netdev, | |
1188 | "No efuse for RTL8153-AD MAC pass through\n"); | |
1189 | return -ENODEV; | |
1190 | } | |
1191 | } else { | |
1192 | /* test for RTL8153-BND and RTL8153-BD */ | |
1193 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1); | |
1194 | if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK) == 0) { | |
1195 | netif_dbg(tp, probe, tp->netdev, | |
1196 | "Invalid variant for MAC pass through\n"); | |
1197 | return -ENODEV; | |
1198 | } | |
91891485 | 1199 | } |
71512e43 KHF |
1200 | |
1201 | mac_obj_name = "\\_SB.AMAC"; | |
1202 | mac_obj_type = ACPI_TYPE_BUFFER; | |
1203 | mac_strlen = 0x17; | |
91891485 | 1204 | } |
34ee32c9 ML |
1205 | |
1206 | /* returns _AUXMAC_#AABBCCDDEEFF# */ | |
71512e43 | 1207 | status = acpi_evaluate_object(NULL, mac_obj_name, NULL, &buffer); |
34ee32c9 ML |
1208 | obj = (union acpi_object *)buffer.pointer; |
1209 | if (!ACPI_SUCCESS(status)) | |
1210 | return -ENODEV; | |
71512e43 | 1211 | if (obj->type != mac_obj_type || obj->string.length != mac_strlen) { |
34ee32c9 | 1212 | netif_warn(tp, probe, tp->netdev, |
53700f0c | 1213 | "Invalid buffer for pass-thru MAC addr: (%d, %d)\n", |
34ee32c9 ML |
1214 | obj->type, obj->string.length); |
1215 | goto amacout; | |
1216 | } | |
71512e43 | 1217 | |
34ee32c9 ML |
1218 | if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 || |
1219 | strncmp(obj->string.pointer + 0x15, "#", 1) != 0) { | |
1220 | netif_warn(tp, probe, tp->netdev, | |
1221 | "Invalid header when reading pass-thru MAC addr\n"); | |
1222 | goto amacout; | |
1223 | } | |
1224 | ret = hex2bin(buf, obj->string.pointer + 9, 6); | |
1225 | if (!(ret == 0 && is_valid_ether_addr(buf))) { | |
1226 | netif_warn(tp, probe, tp->netdev, | |
53700f0c | 1227 | "Invalid MAC for pass-thru MAC addr: %d, %pM\n", |
1228 | ret, buf); | |
34ee32c9 ML |
1229 | ret = -EINVAL; |
1230 | goto amacout; | |
1231 | } | |
1232 | memcpy(sa->sa_data, buf, 6); | |
34ee32c9 ML |
1233 | netif_info(tp, probe, tp->netdev, |
1234 | "Using pass-thru MAC addr %pM\n", sa->sa_data); | |
1235 | ||
1236 | amacout: | |
1237 | kfree(obj); | |
1238 | return ret; | |
1239 | } | |
1240 | ||
102e0592 | 1241 | static int determine_ethernet_addr(struct r8152 *tp, struct sockaddr *sa) |
ac718b69 | 1242 | { |
1243 | struct net_device *dev = tp->netdev; | |
8a91c824 | 1244 | int ret; |
ac718b69 | 1245 | |
53700f0c | 1246 | if (tp->version == RTL_VER_01) { |
102e0592 | 1247 | ret = pla_ocp_read(tp, PLA_IDR, 8, sa->sa_data); |
53700f0c | 1248 | } else { |
91891485 ML |
1249 | /* if device doesn't support MAC pass through this will |
1250 | * be expected to be non-zero | |
34ee32c9 | 1251 | */ |
102e0592 | 1252 | ret = vendor_mac_passthru_addr_read(tp, sa); |
34ee32c9 | 1253 | if (ret < 0) |
102e0592 | 1254 | ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa->sa_data); |
34ee32c9 | 1255 | } |
8a91c824 | 1256 | |
1257 | if (ret < 0) { | |
179bb6d7 | 1258 | netif_err(tp, probe, dev, "Get ether addr fail\n"); |
102e0592 | 1259 | } else if (!is_valid_ether_addr(sa->sa_data)) { |
179bb6d7 | 1260 | netif_err(tp, probe, dev, "Invalid ether addr %pM\n", |
102e0592 | 1261 | sa->sa_data); |
179bb6d7 | 1262 | eth_hw_addr_random(dev); |
102e0592 | 1263 | ether_addr_copy(sa->sa_data, dev->dev_addr); |
179bb6d7 | 1264 | netif_info(tp, probe, dev, "Random ether addr %pM\n", |
102e0592 ML |
1265 | sa->sa_data); |
1266 | return 0; | |
ac718b69 | 1267 | } |
179bb6d7 | 1268 | |
1269 | return ret; | |
ac718b69 | 1270 | } |
1271 | ||
102e0592 ML |
1272 | static int set_ethernet_addr(struct r8152 *tp) |
1273 | { | |
1274 | struct net_device *dev = tp->netdev; | |
1275 | struct sockaddr sa; | |
1276 | int ret; | |
1277 | ||
1278 | ret = determine_ethernet_addr(tp, &sa); | |
1279 | if (ret < 0) | |
1280 | return ret; | |
1281 | ||
1282 | if (tp->version == RTL_VER_01) | |
1283 | ether_addr_copy(dev->dev_addr, sa.sa_data); | |
1284 | else | |
1285 | ret = rtl8152_set_mac_address(dev, &sa); | |
1286 | ||
1287 | return ret; | |
1288 | } | |
1289 | ||
ac718b69 | 1290 | static void read_bulk_callback(struct urb *urb) |
1291 | { | |
ac718b69 | 1292 | struct net_device *netdev; |
ac718b69 | 1293 | int status = urb->status; |
ebc2ec48 | 1294 | struct rx_agg *agg; |
1295 | struct r8152 *tp; | |
ac718b69 | 1296 | |
ebc2ec48 | 1297 | agg = urb->context; |
1298 | if (!agg) | |
1299 | return; | |
1300 | ||
1301 | tp = agg->context; | |
ac718b69 | 1302 | if (!tp) |
1303 | return; | |
ebc2ec48 | 1304 | |
ac718b69 | 1305 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
1306 | return; | |
ebc2ec48 | 1307 | |
1308 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
1309 | return; | |
1310 | ||
ac718b69 | 1311 | netdev = tp->netdev; |
7559fb2f | 1312 | |
1313 | /* When link down, the driver would cancel all bulks. */ | |
1314 | /* This avoid the re-submitting bulk */ | |
ebc2ec48 | 1315 | if (!netif_carrier_ok(netdev)) |
ac718b69 | 1316 | return; |
1317 | ||
9a4be1bd | 1318 | usb_mark_last_busy(tp->udev); |
1319 | ||
ac718b69 | 1320 | switch (status) { |
1321 | case 0: | |
ebc2ec48 | 1322 | if (urb->actual_length < ETH_ZLEN) |
1323 | break; | |
1324 | ||
2685d410 | 1325 | spin_lock(&tp->rx_lock); |
ebc2ec48 | 1326 | list_add_tail(&agg->list, &tp->rx_done); |
2685d410 | 1327 | spin_unlock(&tp->rx_lock); |
d823ab68 | 1328 | napi_schedule(&tp->napi); |
ebc2ec48 | 1329 | return; |
ac718b69 | 1330 | case -ESHUTDOWN: |
1331 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
1332 | netif_device_detach(tp->netdev); | |
ebc2ec48 | 1333 | return; |
ac718b69 | 1334 | case -ENOENT: |
1335 | return; /* the urb is in unlink state */ | |
1336 | case -ETIME: | |
4a8deae2 HW |
1337 | if (net_ratelimit()) |
1338 | netdev_warn(netdev, "maybe reset is needed?\n"); | |
ebc2ec48 | 1339 | break; |
ac718b69 | 1340 | default: |
4a8deae2 HW |
1341 | if (net_ratelimit()) |
1342 | netdev_warn(netdev, "Rx status %d\n", status); | |
ebc2ec48 | 1343 | break; |
ac718b69 | 1344 | } |
1345 | ||
a0fccd48 | 1346 | r8152_submit_rx(tp, agg, GFP_ATOMIC); |
ac718b69 | 1347 | } |
1348 | ||
ebc2ec48 | 1349 | static void write_bulk_callback(struct urb *urb) |
ac718b69 | 1350 | { |
ebc2ec48 | 1351 | struct net_device_stats *stats; |
d104eafa | 1352 | struct net_device *netdev; |
ebc2ec48 | 1353 | struct tx_agg *agg; |
ac718b69 | 1354 | struct r8152 *tp; |
ebc2ec48 | 1355 | int status = urb->status; |
ac718b69 | 1356 | |
ebc2ec48 | 1357 | agg = urb->context; |
1358 | if (!agg) | |
ac718b69 | 1359 | return; |
1360 | ||
ebc2ec48 | 1361 | tp = agg->context; |
1362 | if (!tp) | |
1363 | return; | |
1364 | ||
d104eafa | 1365 | netdev = tp->netdev; |
05e0f1aa | 1366 | stats = &netdev->stats; |
ebc2ec48 | 1367 | if (status) { |
4a8deae2 | 1368 | if (net_ratelimit()) |
d104eafa | 1369 | netdev_warn(netdev, "Tx status %d\n", status); |
ebc2ec48 | 1370 | stats->tx_errors += agg->skb_num; |
ac718b69 | 1371 | } else { |
ebc2ec48 | 1372 | stats->tx_packets += agg->skb_num; |
1373 | stats->tx_bytes += agg->skb_len; | |
ac718b69 | 1374 | } |
1375 | ||
2685d410 | 1376 | spin_lock(&tp->tx_lock); |
ebc2ec48 | 1377 | list_add_tail(&agg->list, &tp->tx_free); |
2685d410 | 1378 | spin_unlock(&tp->tx_lock); |
ebc2ec48 | 1379 | |
9a4be1bd | 1380 | usb_autopm_put_interface_async(tp->intf); |
1381 | ||
d104eafa | 1382 | if (!netif_carrier_ok(netdev)) |
ebc2ec48 | 1383 | return; |
1384 | ||
1385 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
1386 | return; | |
1387 | ||
1388 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
1389 | return; | |
1390 | ||
1391 | if (!skb_queue_empty(&tp->tx_queue)) | |
d823ab68 | 1392 | napi_schedule(&tp->napi); |
ac718b69 | 1393 | } |
1394 | ||
40a82917 | 1395 | static void intr_callback(struct urb *urb) |
1396 | { | |
1397 | struct r8152 *tp; | |
500b6d7e | 1398 | __le16 *d; |
40a82917 | 1399 | int status = urb->status; |
1400 | int res; | |
1401 | ||
1402 | tp = urb->context; | |
1403 | if (!tp) | |
1404 | return; | |
1405 | ||
1406 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
1407 | return; | |
1408 | ||
1409 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
1410 | return; | |
1411 | ||
1412 | switch (status) { | |
1413 | case 0: /* success */ | |
1414 | break; | |
1415 | case -ECONNRESET: /* unlink */ | |
1416 | case -ESHUTDOWN: | |
1417 | netif_device_detach(tp->netdev); | |
1418 | case -ENOENT: | |
d59c876d | 1419 | case -EPROTO: |
1420 | netif_info(tp, intr, tp->netdev, | |
1421 | "Stop submitting intr, status %d\n", status); | |
40a82917 | 1422 | return; |
1423 | case -EOVERFLOW: | |
1424 | netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n"); | |
1425 | goto resubmit; | |
1426 | /* -EPIPE: should clear the halt */ | |
1427 | default: | |
1428 | netif_info(tp, intr, tp->netdev, "intr status %d\n", status); | |
1429 | goto resubmit; | |
1430 | } | |
1431 | ||
1432 | d = urb->transfer_buffer; | |
1433 | if (INTR_LINK & __le16_to_cpu(d[0])) { | |
51d979fa | 1434 | if (!netif_carrier_ok(tp->netdev)) { |
40a82917 | 1435 | set_bit(RTL8152_LINK_CHG, &tp->flags); |
1436 | schedule_delayed_work(&tp->schedule, 0); | |
1437 | } | |
1438 | } else { | |
51d979fa | 1439 | if (netif_carrier_ok(tp->netdev)) { |
2f25abe6 | 1440 | netif_stop_queue(tp->netdev); |
40a82917 | 1441 | set_bit(RTL8152_LINK_CHG, &tp->flags); |
1442 | schedule_delayed_work(&tp->schedule, 0); | |
1443 | } | |
1444 | } | |
1445 | ||
1446 | resubmit: | |
1447 | res = usb_submit_urb(urb, GFP_ATOMIC); | |
67610496 | 1448 | if (res == -ENODEV) { |
1449 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
40a82917 | 1450 | netif_device_detach(tp->netdev); |
67610496 | 1451 | } else if (res) { |
40a82917 | 1452 | netif_err(tp, intr, tp->netdev, |
4a8deae2 | 1453 | "can't resubmit intr, status %d\n", res); |
67610496 | 1454 | } |
40a82917 | 1455 | } |
1456 | ||
ebc2ec48 | 1457 | static inline void *rx_agg_align(void *data) |
1458 | { | |
8e1f51bd | 1459 | return (void *)ALIGN((uintptr_t)data, RX_ALIGN); |
ebc2ec48 | 1460 | } |
1461 | ||
1462 | static inline void *tx_agg_align(void *data) | |
1463 | { | |
8e1f51bd | 1464 | return (void *)ALIGN((uintptr_t)data, TX_ALIGN); |
ebc2ec48 | 1465 | } |
1466 | ||
1467 | static void free_all_mem(struct r8152 *tp) | |
1468 | { | |
1469 | int i; | |
1470 | ||
1471 | for (i = 0; i < RTL8152_MAX_RX; i++) { | |
9629e3c0 | 1472 | usb_free_urb(tp->rx_info[i].urb); |
1473 | tp->rx_info[i].urb = NULL; | |
ebc2ec48 | 1474 | |
9629e3c0 | 1475 | kfree(tp->rx_info[i].buffer); |
1476 | tp->rx_info[i].buffer = NULL; | |
1477 | tp->rx_info[i].head = NULL; | |
ebc2ec48 | 1478 | } |
1479 | ||
1480 | for (i = 0; i < RTL8152_MAX_TX; i++) { | |
9629e3c0 | 1481 | usb_free_urb(tp->tx_info[i].urb); |
1482 | tp->tx_info[i].urb = NULL; | |
ebc2ec48 | 1483 | |
9629e3c0 | 1484 | kfree(tp->tx_info[i].buffer); |
1485 | tp->tx_info[i].buffer = NULL; | |
1486 | tp->tx_info[i].head = NULL; | |
ebc2ec48 | 1487 | } |
40a82917 | 1488 | |
9629e3c0 | 1489 | usb_free_urb(tp->intr_urb); |
1490 | tp->intr_urb = NULL; | |
40a82917 | 1491 | |
9629e3c0 | 1492 | kfree(tp->intr_buff); |
1493 | tp->intr_buff = NULL; | |
ebc2ec48 | 1494 | } |
1495 | ||
1496 | static int alloc_all_mem(struct r8152 *tp) | |
1497 | { | |
1498 | struct net_device *netdev = tp->netdev; | |
40a82917 | 1499 | struct usb_interface *intf = tp->intf; |
1500 | struct usb_host_interface *alt = intf->cur_altsetting; | |
1501 | struct usb_host_endpoint *ep_intr = alt->endpoint + 2; | |
ebc2ec48 | 1502 | struct urb *urb; |
1503 | int node, i; | |
1504 | u8 *buf; | |
1505 | ||
1506 | node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; | |
1507 | ||
1508 | spin_lock_init(&tp->rx_lock); | |
1509 | spin_lock_init(&tp->tx_lock); | |
ebc2ec48 | 1510 | INIT_LIST_HEAD(&tp->tx_free); |
98d068ab | 1511 | INIT_LIST_HEAD(&tp->rx_done); |
ebc2ec48 | 1512 | skb_queue_head_init(&tp->tx_queue); |
d823ab68 | 1513 | skb_queue_head_init(&tp->rx_queue); |
ebc2ec48 | 1514 | |
1515 | for (i = 0; i < RTL8152_MAX_RX; i++) { | |
52aec126 | 1516 | buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); |
ebc2ec48 | 1517 | if (!buf) |
1518 | goto err1; | |
1519 | ||
1520 | if (buf != rx_agg_align(buf)) { | |
1521 | kfree(buf); | |
52aec126 | 1522 | buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL, |
8e1f51bd | 1523 | node); |
ebc2ec48 | 1524 | if (!buf) |
1525 | goto err1; | |
1526 | } | |
1527 | ||
1528 | urb = usb_alloc_urb(0, GFP_KERNEL); | |
1529 | if (!urb) { | |
1530 | kfree(buf); | |
1531 | goto err1; | |
1532 | } | |
1533 | ||
1534 | INIT_LIST_HEAD(&tp->rx_info[i].list); | |
1535 | tp->rx_info[i].context = tp; | |
1536 | tp->rx_info[i].urb = urb; | |
1537 | tp->rx_info[i].buffer = buf; | |
1538 | tp->rx_info[i].head = rx_agg_align(buf); | |
1539 | } | |
1540 | ||
1541 | for (i = 0; i < RTL8152_MAX_TX; i++) { | |
52aec126 | 1542 | buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); |
ebc2ec48 | 1543 | if (!buf) |
1544 | goto err1; | |
1545 | ||
1546 | if (buf != tx_agg_align(buf)) { | |
1547 | kfree(buf); | |
52aec126 | 1548 | buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL, |
8e1f51bd | 1549 | node); |
ebc2ec48 | 1550 | if (!buf) |
1551 | goto err1; | |
1552 | } | |
1553 | ||
1554 | urb = usb_alloc_urb(0, GFP_KERNEL); | |
1555 | if (!urb) { | |
1556 | kfree(buf); | |
1557 | goto err1; | |
1558 | } | |
1559 | ||
1560 | INIT_LIST_HEAD(&tp->tx_info[i].list); | |
1561 | tp->tx_info[i].context = tp; | |
1562 | tp->tx_info[i].urb = urb; | |
1563 | tp->tx_info[i].buffer = buf; | |
1564 | tp->tx_info[i].head = tx_agg_align(buf); | |
1565 | ||
1566 | list_add_tail(&tp->tx_info[i].list, &tp->tx_free); | |
1567 | } | |
1568 | ||
40a82917 | 1569 | tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL); |
1570 | if (!tp->intr_urb) | |
1571 | goto err1; | |
1572 | ||
1573 | tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL); | |
1574 | if (!tp->intr_buff) | |
1575 | goto err1; | |
1576 | ||
1577 | tp->intr_interval = (int)ep_intr->desc.bInterval; | |
1578 | usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3), | |
b209af99 | 1579 | tp->intr_buff, INTBUFSIZE, intr_callback, |
1580 | tp, tp->intr_interval); | |
40a82917 | 1581 | |
ebc2ec48 | 1582 | return 0; |
1583 | ||
1584 | err1: | |
1585 | free_all_mem(tp); | |
1586 | return -ENOMEM; | |
1587 | } | |
1588 | ||
0de98f6c | 1589 | static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp) |
1590 | { | |
1591 | struct tx_agg *agg = NULL; | |
1592 | unsigned long flags; | |
1593 | ||
21949ab7 | 1594 | if (list_empty(&tp->tx_free)) |
1595 | return NULL; | |
1596 | ||
0de98f6c | 1597 | spin_lock_irqsave(&tp->tx_lock, flags); |
1598 | if (!list_empty(&tp->tx_free)) { | |
1599 | struct list_head *cursor; | |
1600 | ||
1601 | cursor = tp->tx_free.next; | |
1602 | list_del_init(cursor); | |
1603 | agg = list_entry(cursor, struct tx_agg, list); | |
1604 | } | |
1605 | spin_unlock_irqrestore(&tp->tx_lock, flags); | |
1606 | ||
1607 | return agg; | |
1608 | } | |
1609 | ||
b209af99 | 1610 | /* r8152_csum_workaround() |
6128d1bb | 1611 | * The hw limites the value the transport offset. When the offset is out of the |
1612 | * range, calculate the checksum by sw. | |
1613 | */ | |
1614 | static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb, | |
1615 | struct sk_buff_head *list) | |
1616 | { | |
1617 | if (skb_shinfo(skb)->gso_size) { | |
1618 | netdev_features_t features = tp->netdev->features; | |
1619 | struct sk_buff_head seg_list; | |
1620 | struct sk_buff *segs, *nskb; | |
1621 | ||
a91d45f1 | 1622 | features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6); |
6128d1bb | 1623 | segs = skb_gso_segment(skb, features); |
1624 | if (IS_ERR(segs) || !segs) | |
1625 | goto drop; | |
1626 | ||
1627 | __skb_queue_head_init(&seg_list); | |
1628 | ||
1629 | do { | |
1630 | nskb = segs; | |
1631 | segs = segs->next; | |
1632 | nskb->next = NULL; | |
1633 | __skb_queue_tail(&seg_list, nskb); | |
1634 | } while (segs); | |
1635 | ||
1636 | skb_queue_splice(&seg_list, list); | |
1637 | dev_kfree_skb(skb); | |
1638 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
1639 | if (skb_checksum_help(skb) < 0) | |
1640 | goto drop; | |
1641 | ||
1642 | __skb_queue_head(list, skb); | |
1643 | } else { | |
1644 | struct net_device_stats *stats; | |
1645 | ||
1646 | drop: | |
1647 | stats = &tp->netdev->stats; | |
1648 | stats->tx_dropped++; | |
1649 | dev_kfree_skb(skb); | |
1650 | } | |
1651 | } | |
1652 | ||
b209af99 | 1653 | /* msdn_giant_send_check() |
6128d1bb | 1654 | * According to the document of microsoft, the TCP Pseudo Header excludes the |
1655 | * packet length for IPv6 TCP large packets. | |
1656 | */ | |
1657 | static int msdn_giant_send_check(struct sk_buff *skb) | |
1658 | { | |
1659 | const struct ipv6hdr *ipv6h; | |
1660 | struct tcphdr *th; | |
fcb308d5 | 1661 | int ret; |
1662 | ||
1663 | ret = skb_cow_head(skb, 0); | |
1664 | if (ret) | |
1665 | return ret; | |
6128d1bb | 1666 | |
1667 | ipv6h = ipv6_hdr(skb); | |
1668 | th = tcp_hdr(skb); | |
1669 | ||
1670 | th->check = 0; | |
1671 | th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0); | |
1672 | ||
fcb308d5 | 1673 | return ret; |
6128d1bb | 1674 | } |
1675 | ||
c5554298 | 1676 | static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb) |
1677 | { | |
df8a39de | 1678 | if (skb_vlan_tag_present(skb)) { |
c5554298 | 1679 | u32 opts2; |
1680 | ||
df8a39de | 1681 | opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb)); |
c5554298 | 1682 | desc->opts2 |= cpu_to_le32(opts2); |
1683 | } | |
1684 | } | |
1685 | ||
1686 | static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb) | |
1687 | { | |
1688 | u32 opts2 = le32_to_cpu(desc->opts2); | |
1689 | ||
1690 | if (opts2 & RX_VLAN_TAG) | |
1691 | __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), | |
1692 | swab16(opts2 & 0xffff)); | |
1693 | } | |
1694 | ||
60c89071 | 1695 | static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, |
1696 | struct sk_buff *skb, u32 len, u32 transport_offset) | |
1697 | { | |
1698 | u32 mss = skb_shinfo(skb)->gso_size; | |
1699 | u32 opts1, opts2 = 0; | |
1700 | int ret = TX_CSUM_SUCCESS; | |
1701 | ||
1702 | WARN_ON_ONCE(len > TX_LEN_MAX); | |
1703 | ||
1704 | opts1 = len | TX_FS | TX_LS; | |
1705 | ||
1706 | if (mss) { | |
6128d1bb | 1707 | if (transport_offset > GTTCPHO_MAX) { |
1708 | netif_warn(tp, tx_err, tp->netdev, | |
1709 | "Invalid transport offset 0x%x for TSO\n", | |
1710 | transport_offset); | |
1711 | ret = TX_CSUM_TSO; | |
1712 | goto unavailable; | |
1713 | } | |
1714 | ||
6e74d174 | 1715 | switch (vlan_get_protocol(skb)) { |
60c89071 | 1716 | case htons(ETH_P_IP): |
1717 | opts1 |= GTSENDV4; | |
1718 | break; | |
1719 | ||
6128d1bb | 1720 | case htons(ETH_P_IPV6): |
fcb308d5 | 1721 | if (msdn_giant_send_check(skb)) { |
1722 | ret = TX_CSUM_TSO; | |
1723 | goto unavailable; | |
1724 | } | |
6128d1bb | 1725 | opts1 |= GTSENDV6; |
6128d1bb | 1726 | break; |
1727 | ||
60c89071 | 1728 | default: |
1729 | WARN_ON_ONCE(1); | |
1730 | break; | |
1731 | } | |
1732 | ||
1733 | opts1 |= transport_offset << GTTCPHO_SHIFT; | |
1734 | opts2 |= min(mss, MSS_MAX) << MSS_SHIFT; | |
1735 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
1736 | u8 ip_protocol; | |
5bd23881 | 1737 | |
6128d1bb | 1738 | if (transport_offset > TCPHO_MAX) { |
1739 | netif_warn(tp, tx_err, tp->netdev, | |
1740 | "Invalid transport offset 0x%x\n", | |
1741 | transport_offset); | |
1742 | ret = TX_CSUM_NONE; | |
1743 | goto unavailable; | |
1744 | } | |
1745 | ||
6e74d174 | 1746 | switch (vlan_get_protocol(skb)) { |
5bd23881 | 1747 | case htons(ETH_P_IP): |
1748 | opts2 |= IPV4_CS; | |
1749 | ip_protocol = ip_hdr(skb)->protocol; | |
1750 | break; | |
1751 | ||
1752 | case htons(ETH_P_IPV6): | |
1753 | opts2 |= IPV6_CS; | |
1754 | ip_protocol = ipv6_hdr(skb)->nexthdr; | |
1755 | break; | |
1756 | ||
1757 | default: | |
1758 | ip_protocol = IPPROTO_RAW; | |
1759 | break; | |
1760 | } | |
1761 | ||
60c89071 | 1762 | if (ip_protocol == IPPROTO_TCP) |
5bd23881 | 1763 | opts2 |= TCP_CS; |
60c89071 | 1764 | else if (ip_protocol == IPPROTO_UDP) |
5bd23881 | 1765 | opts2 |= UDP_CS; |
60c89071 | 1766 | else |
5bd23881 | 1767 | WARN_ON_ONCE(1); |
5bd23881 | 1768 | |
60c89071 | 1769 | opts2 |= transport_offset << TCPHO_SHIFT; |
5bd23881 | 1770 | } |
60c89071 | 1771 | |
1772 | desc->opts2 = cpu_to_le32(opts2); | |
1773 | desc->opts1 = cpu_to_le32(opts1); | |
1774 | ||
6128d1bb | 1775 | unavailable: |
60c89071 | 1776 | return ret; |
5bd23881 | 1777 | } |
1778 | ||
b1379d9a | 1779 | static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg) |
1780 | { | |
d84130a1 | 1781 | struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; |
9a4be1bd | 1782 | int remain, ret; |
b1379d9a | 1783 | u8 *tx_data; |
1784 | ||
d84130a1 | 1785 | __skb_queue_head_init(&skb_head); |
0c3121fc | 1786 | spin_lock(&tx_queue->lock); |
d84130a1 | 1787 | skb_queue_splice_init(tx_queue, &skb_head); |
0c3121fc | 1788 | spin_unlock(&tx_queue->lock); |
d84130a1 | 1789 | |
b1379d9a | 1790 | tx_data = agg->head; |
b209af99 | 1791 | agg->skb_num = 0; |
1792 | agg->skb_len = 0; | |
52aec126 | 1793 | remain = agg_buf_sz; |
b1379d9a | 1794 | |
7937f9e5 | 1795 | while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) { |
b1379d9a | 1796 | struct tx_desc *tx_desc; |
1797 | struct sk_buff *skb; | |
1798 | unsigned int len; | |
60c89071 | 1799 | u32 offset; |
b1379d9a | 1800 | |
d84130a1 | 1801 | skb = __skb_dequeue(&skb_head); |
b1379d9a | 1802 | if (!skb) |
1803 | break; | |
1804 | ||
60c89071 | 1805 | len = skb->len + sizeof(*tx_desc); |
1806 | ||
1807 | if (len > remain) { | |
d84130a1 | 1808 | __skb_queue_head(&skb_head, skb); |
b1379d9a | 1809 | break; |
1810 | } | |
1811 | ||
7937f9e5 | 1812 | tx_data = tx_agg_align(tx_data); |
b1379d9a | 1813 | tx_desc = (struct tx_desc *)tx_data; |
60c89071 | 1814 | |
1815 | offset = (u32)skb_transport_offset(skb); | |
1816 | ||
6128d1bb | 1817 | if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) { |
1818 | r8152_csum_workaround(tp, skb, &skb_head); | |
1819 | continue; | |
1820 | } | |
60c89071 | 1821 | |
c5554298 | 1822 | rtl_tx_vlan_tag(tx_desc, skb); |
1823 | ||
b1379d9a | 1824 | tx_data += sizeof(*tx_desc); |
1825 | ||
60c89071 | 1826 | len = skb->len; |
1827 | if (skb_copy_bits(skb, 0, tx_data, len) < 0) { | |
1828 | struct net_device_stats *stats = &tp->netdev->stats; | |
1829 | ||
1830 | stats->tx_dropped++; | |
1831 | dev_kfree_skb_any(skb); | |
1832 | tx_data -= sizeof(*tx_desc); | |
1833 | continue; | |
1834 | } | |
1835 | ||
1836 | tx_data += len; | |
b1379d9a | 1837 | agg->skb_len += len; |
b4899897 | 1838 | agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1; |
60c89071 | 1839 | |
b1379d9a | 1840 | dev_kfree_skb_any(skb); |
1841 | ||
52aec126 | 1842 | remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head); |
0b165514 KHF |
1843 | |
1844 | if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags)) | |
1845 | break; | |
b1379d9a | 1846 | } |
1847 | ||
d84130a1 | 1848 | if (!skb_queue_empty(&skb_head)) { |
0c3121fc | 1849 | spin_lock(&tx_queue->lock); |
d84130a1 | 1850 | skb_queue_splice(&skb_head, tx_queue); |
0c3121fc | 1851 | spin_unlock(&tx_queue->lock); |
d84130a1 | 1852 | } |
1853 | ||
0c3121fc | 1854 | netif_tx_lock(tp->netdev); |
dd1b119c | 1855 | |
1856 | if (netif_queue_stopped(tp->netdev) && | |
1857 | skb_queue_len(&tp->tx_queue) < tp->tx_qlen) | |
1858 | netif_wake_queue(tp->netdev); | |
1859 | ||
0c3121fc | 1860 | netif_tx_unlock(tp->netdev); |
9a4be1bd | 1861 | |
0c3121fc | 1862 | ret = usb_autopm_get_interface_async(tp->intf); |
9a4be1bd | 1863 | if (ret < 0) |
1864 | goto out_tx_fill; | |
dd1b119c | 1865 | |
b1379d9a | 1866 | usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2), |
1867 | agg->head, (int)(tx_data - (u8 *)agg->head), | |
1868 | (usb_complete_t)write_bulk_callback, agg); | |
1869 | ||
0c3121fc | 1870 | ret = usb_submit_urb(agg->urb, GFP_ATOMIC); |
9a4be1bd | 1871 | if (ret < 0) |
0c3121fc | 1872 | usb_autopm_put_interface_async(tp->intf); |
9a4be1bd | 1873 | |
1874 | out_tx_fill: | |
1875 | return ret; | |
b1379d9a | 1876 | } |
1877 | ||
565cab0a | 1878 | static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc) |
1879 | { | |
1880 | u8 checksum = CHECKSUM_NONE; | |
1881 | u32 opts2, opts3; | |
1882 | ||
19c0f40d | 1883 | if (!(tp->netdev->features & NETIF_F_RXCSUM)) |
565cab0a | 1884 | goto return_result; |
1885 | ||
1886 | opts2 = le32_to_cpu(rx_desc->opts2); | |
1887 | opts3 = le32_to_cpu(rx_desc->opts3); | |
1888 | ||
1889 | if (opts2 & RD_IPV4_CS) { | |
1890 | if (opts3 & IPF) | |
1891 | checksum = CHECKSUM_NONE; | |
1892 | else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF)) | |
1893 | checksum = CHECKSUM_NONE; | |
1894 | else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF)) | |
1895 | checksum = CHECKSUM_NONE; | |
1896 | else | |
1897 | checksum = CHECKSUM_UNNECESSARY; | |
b9a321b4 | 1898 | } else if (opts2 & RD_IPV6_CS) { |
6128d1bb | 1899 | if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF)) |
1900 | checksum = CHECKSUM_UNNECESSARY; | |
1901 | else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF)) | |
1902 | checksum = CHECKSUM_UNNECESSARY; | |
565cab0a | 1903 | } |
1904 | ||
1905 | return_result: | |
1906 | return checksum; | |
1907 | } | |
1908 | ||
d823ab68 | 1909 | static int rx_bottom(struct r8152 *tp, int budget) |
ebc2ec48 | 1910 | { |
a5a4f468 | 1911 | unsigned long flags; |
d84130a1 | 1912 | struct list_head *cursor, *next, rx_queue; |
e1a2ca92 | 1913 | int ret = 0, work_done = 0; |
ce594e98 | 1914 | struct napi_struct *napi = &tp->napi; |
d823ab68 | 1915 | |
1916 | if (!skb_queue_empty(&tp->rx_queue)) { | |
1917 | while (work_done < budget) { | |
1918 | struct sk_buff *skb = __skb_dequeue(&tp->rx_queue); | |
1919 | struct net_device *netdev = tp->netdev; | |
1920 | struct net_device_stats *stats = &netdev->stats; | |
1921 | unsigned int pkt_len; | |
1922 | ||
1923 | if (!skb) | |
1924 | break; | |
1925 | ||
1926 | pkt_len = skb->len; | |
ce594e98 | 1927 | napi_gro_receive(napi, skb); |
d823ab68 | 1928 | work_done++; |
1929 | stats->rx_packets++; | |
1930 | stats->rx_bytes += pkt_len; | |
1931 | } | |
1932 | } | |
ebc2ec48 | 1933 | |
d84130a1 | 1934 | if (list_empty(&tp->rx_done)) |
d823ab68 | 1935 | goto out1; |
d84130a1 | 1936 | |
1937 | INIT_LIST_HEAD(&rx_queue); | |
a5a4f468 | 1938 | spin_lock_irqsave(&tp->rx_lock, flags); |
d84130a1 | 1939 | list_splice_init(&tp->rx_done, &rx_queue); |
1940 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
1941 | ||
1942 | list_for_each_safe(cursor, next, &rx_queue) { | |
43a4478d | 1943 | struct rx_desc *rx_desc; |
1944 | struct rx_agg *agg; | |
43a4478d | 1945 | int len_used = 0; |
1946 | struct urb *urb; | |
1947 | u8 *rx_data; | |
43a4478d | 1948 | |
ebc2ec48 | 1949 | list_del_init(cursor); |
ebc2ec48 | 1950 | |
1951 | agg = list_entry(cursor, struct rx_agg, list); | |
1952 | urb = agg->urb; | |
0de98f6c | 1953 | if (urb->actual_length < ETH_ZLEN) |
1954 | goto submit; | |
ebc2ec48 | 1955 | |
ebc2ec48 | 1956 | rx_desc = agg->head; |
1957 | rx_data = agg->head; | |
7937f9e5 | 1958 | len_used += sizeof(struct rx_desc); |
ebc2ec48 | 1959 | |
7937f9e5 | 1960 | while (urb->actual_length > len_used) { |
43a4478d | 1961 | struct net_device *netdev = tp->netdev; |
05e0f1aa | 1962 | struct net_device_stats *stats = &netdev->stats; |
7937f9e5 | 1963 | unsigned int pkt_len; |
43a4478d | 1964 | struct sk_buff *skb; |
1965 | ||
74544458 | 1966 | /* limite the skb numbers for rx_queue */ |
1967 | if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000)) | |
1968 | break; | |
1969 | ||
7937f9e5 | 1970 | pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; |
ebc2ec48 | 1971 | if (pkt_len < ETH_ZLEN) |
1972 | break; | |
1973 | ||
7937f9e5 | 1974 | len_used += pkt_len; |
1975 | if (urb->actual_length < len_used) | |
1976 | break; | |
1977 | ||
b65c0c9b | 1978 | pkt_len -= ETH_FCS_LEN; |
ebc2ec48 | 1979 | rx_data += sizeof(struct rx_desc); |
1980 | ||
ce594e98 | 1981 | skb = napi_alloc_skb(napi, pkt_len); |
ebc2ec48 | 1982 | if (!skb) { |
1983 | stats->rx_dropped++; | |
5e2f7485 | 1984 | goto find_next_rx; |
ebc2ec48 | 1985 | } |
565cab0a | 1986 | |
1987 | skb->ip_summed = r8152_rx_csum(tp, rx_desc); | |
ebc2ec48 | 1988 | memcpy(skb->data, rx_data, pkt_len); |
1989 | skb_put(skb, pkt_len); | |
1990 | skb->protocol = eth_type_trans(skb, netdev); | |
c5554298 | 1991 | rtl_rx_vlan_tag(rx_desc, skb); |
d823ab68 | 1992 | if (work_done < budget) { |
ce594e98 | 1993 | napi_gro_receive(napi, skb); |
d823ab68 | 1994 | work_done++; |
1995 | stats->rx_packets++; | |
1996 | stats->rx_bytes += pkt_len; | |
1997 | } else { | |
1998 | __skb_queue_tail(&tp->rx_queue, skb); | |
1999 | } | |
ebc2ec48 | 2000 | |
5e2f7485 | 2001 | find_next_rx: |
b65c0c9b | 2002 | rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN); |
ebc2ec48 | 2003 | rx_desc = (struct rx_desc *)rx_data; |
ebc2ec48 | 2004 | len_used = (int)(rx_data - (u8 *)agg->head); |
7937f9e5 | 2005 | len_used += sizeof(struct rx_desc); |
ebc2ec48 | 2006 | } |
2007 | ||
0de98f6c | 2008 | submit: |
e1a2ca92 | 2009 | if (!ret) { |
2010 | ret = r8152_submit_rx(tp, agg, GFP_ATOMIC); | |
2011 | } else { | |
2012 | urb->actual_length = 0; | |
2013 | list_add_tail(&agg->list, next); | |
2014 | } | |
2015 | } | |
2016 | ||
2017 | if (!list_empty(&rx_queue)) { | |
2018 | spin_lock_irqsave(&tp->rx_lock, flags); | |
2019 | list_splice_tail(&rx_queue, &tp->rx_done); | |
2020 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
ebc2ec48 | 2021 | } |
d823ab68 | 2022 | |
2023 | out1: | |
2024 | return work_done; | |
ebc2ec48 | 2025 | } |
2026 | ||
2027 | static void tx_bottom(struct r8152 *tp) | |
2028 | { | |
ebc2ec48 | 2029 | int res; |
2030 | ||
b1379d9a | 2031 | do { |
2032 | struct tx_agg *agg; | |
ebc2ec48 | 2033 | |
b1379d9a | 2034 | if (skb_queue_empty(&tp->tx_queue)) |
ebc2ec48 | 2035 | break; |
2036 | ||
b1379d9a | 2037 | agg = r8152_get_tx_agg(tp); |
2038 | if (!agg) | |
ebc2ec48 | 2039 | break; |
ebc2ec48 | 2040 | |
b1379d9a | 2041 | res = r8152_tx_agg_fill(tp, agg); |
2042 | if (res) { | |
05e0f1aa | 2043 | struct net_device *netdev = tp->netdev; |
ebc2ec48 | 2044 | |
b1379d9a | 2045 | if (res == -ENODEV) { |
67610496 | 2046 | set_bit(RTL8152_UNPLUG, &tp->flags); |
b1379d9a | 2047 | netif_device_detach(netdev); |
2048 | } else { | |
05e0f1aa | 2049 | struct net_device_stats *stats = &netdev->stats; |
2050 | unsigned long flags; | |
2051 | ||
b1379d9a | 2052 | netif_warn(tp, tx_err, netdev, |
2053 | "failed tx_urb %d\n", res); | |
2054 | stats->tx_dropped += agg->skb_num; | |
db8515ef | 2055 | |
b1379d9a | 2056 | spin_lock_irqsave(&tp->tx_lock, flags); |
2057 | list_add_tail(&agg->list, &tp->tx_free); | |
2058 | spin_unlock_irqrestore(&tp->tx_lock, flags); | |
2059 | } | |
ebc2ec48 | 2060 | } |
b1379d9a | 2061 | } while (res == 0); |
ebc2ec48 | 2062 | } |
2063 | ||
d823ab68 | 2064 | static void bottom_half(struct r8152 *tp) |
ac718b69 | 2065 | { |
ebc2ec48 | 2066 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
2067 | return; | |
2068 | ||
2069 | if (!test_bit(WORK_ENABLE, &tp->flags)) | |
ac718b69 | 2070 | return; |
ebc2ec48 | 2071 | |
7559fb2f | 2072 | /* When link down, the driver would cancel all bulks. */ |
2073 | /* This avoid the re-submitting bulk */ | |
ebc2ec48 | 2074 | if (!netif_carrier_ok(tp->netdev)) |
ac718b69 | 2075 | return; |
ebc2ec48 | 2076 | |
d823ab68 | 2077 | clear_bit(SCHEDULE_NAPI, &tp->flags); |
9451a11c | 2078 | |
0c3121fc | 2079 | tx_bottom(tp); |
ebc2ec48 | 2080 | } |
2081 | ||
d823ab68 | 2082 | static int r8152_poll(struct napi_struct *napi, int budget) |
2083 | { | |
2084 | struct r8152 *tp = container_of(napi, struct r8152, napi); | |
2085 | int work_done; | |
2086 | ||
2087 | work_done = rx_bottom(tp, budget); | |
2088 | bottom_half(tp); | |
2089 | ||
2090 | if (work_done < budget) { | |
a3307f9b | 2091 | if (!napi_complete_done(napi, work_done)) |
2092 | goto out; | |
d823ab68 | 2093 | if (!list_empty(&tp->rx_done)) |
2094 | napi_schedule(napi); | |
248b213a | 2095 | else if (!skb_queue_empty(&tp->tx_queue) && |
2096 | !list_empty(&tp->tx_free)) | |
2097 | napi_schedule(napi); | |
d823ab68 | 2098 | } |
2099 | ||
a3307f9b | 2100 | out: |
d823ab68 | 2101 | return work_done; |
2102 | } | |
2103 | ||
ebc2ec48 | 2104 | static |
2105 | int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags) | |
2106 | { | |
a0fccd48 | 2107 | int ret; |
2108 | ||
ef827a5b | 2109 | /* The rx would be stopped, so skip submitting */ |
2110 | if (test_bit(RTL8152_UNPLUG, &tp->flags) || | |
2111 | !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev)) | |
2112 | return 0; | |
2113 | ||
ebc2ec48 | 2114 | usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1), |
52aec126 | 2115 | agg->head, agg_buf_sz, |
b209af99 | 2116 | (usb_complete_t)read_bulk_callback, agg); |
ebc2ec48 | 2117 | |
a0fccd48 | 2118 | ret = usb_submit_urb(agg->urb, mem_flags); |
2119 | if (ret == -ENODEV) { | |
2120 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
2121 | netif_device_detach(tp->netdev); | |
2122 | } else if (ret) { | |
2123 | struct urb *urb = agg->urb; | |
2124 | unsigned long flags; | |
2125 | ||
2126 | urb->actual_length = 0; | |
2127 | spin_lock_irqsave(&tp->rx_lock, flags); | |
2128 | list_add_tail(&agg->list, &tp->rx_done); | |
2129 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
d823ab68 | 2130 | |
2131 | netif_err(tp, rx_err, tp->netdev, | |
2132 | "Couldn't submit rx[%p], ret = %d\n", agg, ret); | |
2133 | ||
2134 | napi_schedule(&tp->napi); | |
a0fccd48 | 2135 | } |
2136 | ||
2137 | return ret; | |
ac718b69 | 2138 | } |
2139 | ||
00a5e360 | 2140 | static void rtl_drop_queued_tx(struct r8152 *tp) |
2141 | { | |
2142 | struct net_device_stats *stats = &tp->netdev->stats; | |
d84130a1 | 2143 | struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; |
00a5e360 | 2144 | struct sk_buff *skb; |
2145 | ||
d84130a1 | 2146 | if (skb_queue_empty(tx_queue)) |
2147 | return; | |
2148 | ||
2149 | __skb_queue_head_init(&skb_head); | |
2685d410 | 2150 | spin_lock_bh(&tx_queue->lock); |
d84130a1 | 2151 | skb_queue_splice_init(tx_queue, &skb_head); |
2685d410 | 2152 | spin_unlock_bh(&tx_queue->lock); |
d84130a1 | 2153 | |
2154 | while ((skb = __skb_dequeue(&skb_head))) { | |
00a5e360 | 2155 | dev_kfree_skb(skb); |
2156 | stats->tx_dropped++; | |
2157 | } | |
2158 | } | |
2159 | ||
ac718b69 | 2160 | static void rtl8152_tx_timeout(struct net_device *netdev) |
2161 | { | |
2162 | struct r8152 *tp = netdev_priv(netdev); | |
ebc2ec48 | 2163 | |
4a8deae2 | 2164 | netif_warn(tp, tx_err, netdev, "Tx timeout\n"); |
37608f3e | 2165 | |
2166 | usb_queue_reset_device(tp->intf); | |
ac718b69 | 2167 | } |
2168 | ||
2169 | static void rtl8152_set_rx_mode(struct net_device *netdev) | |
2170 | { | |
2171 | struct r8152 *tp = netdev_priv(netdev); | |
2172 | ||
51d979fa | 2173 | if (netif_carrier_ok(netdev)) { |
ac718b69 | 2174 | set_bit(RTL8152_SET_RX_MODE, &tp->flags); |
40a82917 | 2175 | schedule_delayed_work(&tp->schedule, 0); |
2176 | } | |
ac718b69 | 2177 | } |
2178 | ||
2179 | static void _rtl8152_set_rx_mode(struct net_device *netdev) | |
2180 | { | |
2181 | struct r8152 *tp = netdev_priv(netdev); | |
31787f53 | 2182 | u32 mc_filter[2]; /* Multicast hash filter */ |
2183 | __le32 tmp[2]; | |
ac718b69 | 2184 | u32 ocp_data; |
2185 | ||
ac718b69 | 2186 | netif_stop_queue(netdev); |
2187 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
2188 | ocp_data &= ~RCR_ACPT_ALL; | |
2189 | ocp_data |= RCR_AB | RCR_APM; | |
2190 | ||
2191 | if (netdev->flags & IFF_PROMISC) { | |
2192 | /* Unconditionally log net taps. */ | |
2193 | netif_notice(tp, link, netdev, "Promiscuous mode enabled\n"); | |
2194 | ocp_data |= RCR_AM | RCR_AAP; | |
b209af99 | 2195 | mc_filter[1] = 0xffffffff; |
2196 | mc_filter[0] = 0xffffffff; | |
ac718b69 | 2197 | } else if ((netdev_mc_count(netdev) > multicast_filter_limit) || |
2198 | (netdev->flags & IFF_ALLMULTI)) { | |
2199 | /* Too many to filter perfectly -- accept all multicasts. */ | |
2200 | ocp_data |= RCR_AM; | |
b209af99 | 2201 | mc_filter[1] = 0xffffffff; |
2202 | mc_filter[0] = 0xffffffff; | |
ac718b69 | 2203 | } else { |
2204 | struct netdev_hw_addr *ha; | |
2205 | ||
b209af99 | 2206 | mc_filter[1] = 0; |
2207 | mc_filter[0] = 0; | |
ac718b69 | 2208 | netdev_for_each_mc_addr(ha, netdev) { |
2209 | int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; | |
b209af99 | 2210 | |
ac718b69 | 2211 | mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); |
2212 | ocp_data |= RCR_AM; | |
2213 | } | |
2214 | } | |
2215 | ||
31787f53 | 2216 | tmp[0] = __cpu_to_le32(swab32(mc_filter[1])); |
2217 | tmp[1] = __cpu_to_le32(swab32(mc_filter[0])); | |
ac718b69 | 2218 | |
31787f53 | 2219 | pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp); |
ac718b69 | 2220 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); |
2221 | netif_wake_queue(netdev); | |
ac718b69 | 2222 | } |
2223 | ||
a5e31255 | 2224 | static netdev_features_t |
2225 | rtl8152_features_check(struct sk_buff *skb, struct net_device *dev, | |
2226 | netdev_features_t features) | |
2227 | { | |
2228 | u32 mss = skb_shinfo(skb)->gso_size; | |
2229 | int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX; | |
2230 | int offset = skb_transport_offset(skb); | |
2231 | ||
2232 | if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset) | |
a188222b | 2233 | features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); |
a5e31255 | 2234 | else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz) |
2235 | features &= ~NETIF_F_GSO_MASK; | |
2236 | ||
2237 | return features; | |
2238 | } | |
2239 | ||
ac718b69 | 2240 | static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb, |
b209af99 | 2241 | struct net_device *netdev) |
ac718b69 | 2242 | { |
2243 | struct r8152 *tp = netdev_priv(netdev); | |
ac718b69 | 2244 | |
ebc2ec48 | 2245 | skb_tx_timestamp(skb); |
ac718b69 | 2246 | |
61598788 | 2247 | skb_queue_tail(&tp->tx_queue, skb); |
ebc2ec48 | 2248 | |
0c3121fc | 2249 | if (!list_empty(&tp->tx_free)) { |
2250 | if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { | |
d823ab68 | 2251 | set_bit(SCHEDULE_NAPI, &tp->flags); |
0c3121fc | 2252 | schedule_delayed_work(&tp->schedule, 0); |
2253 | } else { | |
2254 | usb_mark_last_busy(tp->udev); | |
d823ab68 | 2255 | napi_schedule(&tp->napi); |
0c3121fc | 2256 | } |
b209af99 | 2257 | } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) { |
dd1b119c | 2258 | netif_stop_queue(netdev); |
b209af99 | 2259 | } |
dd1b119c | 2260 | |
ac718b69 | 2261 | return NETDEV_TX_OK; |
2262 | } | |
2263 | ||
2264 | static void r8152b_reset_packet_filter(struct r8152 *tp) | |
2265 | { | |
2266 | u32 ocp_data; | |
2267 | ||
2268 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); | |
2269 | ocp_data &= ~FMC_FCR_MCU_EN; | |
2270 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); | |
2271 | ocp_data |= FMC_FCR_MCU_EN; | |
2272 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); | |
2273 | } | |
2274 | ||
2275 | static void rtl8152_nic_reset(struct r8152 *tp) | |
2276 | { | |
2277 | int i; | |
2278 | ||
2279 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST); | |
2280 | ||
2281 | for (i = 0; i < 1000; i++) { | |
2282 | if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST)) | |
2283 | break; | |
b209af99 | 2284 | usleep_range(100, 400); |
ac718b69 | 2285 | } |
2286 | } | |
2287 | ||
dd1b119c | 2288 | static void set_tx_qlen(struct r8152 *tp) |
2289 | { | |
2290 | struct net_device *netdev = tp->netdev; | |
2291 | ||
b65c0c9b | 2292 | tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN + |
52aec126 | 2293 | sizeof(struct tx_desc)); |
dd1b119c | 2294 | } |
2295 | ||
ac718b69 | 2296 | static inline u8 rtl8152_get_speed(struct r8152 *tp) |
2297 | { | |
2298 | return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); | |
2299 | } | |
2300 | ||
507605a8 | 2301 | static void rtl_set_eee_plus(struct r8152 *tp) |
ac718b69 | 2302 | { |
ebc2ec48 | 2303 | u32 ocp_data; |
ac718b69 | 2304 | u8 speed; |
2305 | ||
2306 | speed = rtl8152_get_speed(tp); | |
ebc2ec48 | 2307 | if (speed & _10bps) { |
ac718b69 | 2308 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); |
ebc2ec48 | 2309 | ocp_data |= EEEP_CR_EEEP_TX; |
ac718b69 | 2310 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); |
2311 | } else { | |
2312 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); | |
ebc2ec48 | 2313 | ocp_data &= ~EEEP_CR_EEEP_TX; |
ac718b69 | 2314 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); |
2315 | } | |
507605a8 | 2316 | } |
2317 | ||
00a5e360 | 2318 | static void rxdy_gated_en(struct r8152 *tp, bool enable) |
2319 | { | |
2320 | u32 ocp_data; | |
2321 | ||
2322 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); | |
2323 | if (enable) | |
2324 | ocp_data |= RXDY_GATED_EN; | |
2325 | else | |
2326 | ocp_data &= ~RXDY_GATED_EN; | |
2327 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); | |
2328 | } | |
2329 | ||
445f7f4d | 2330 | static int rtl_start_rx(struct r8152 *tp) |
2331 | { | |
2332 | int i, ret = 0; | |
2333 | ||
2334 | INIT_LIST_HEAD(&tp->rx_done); | |
2335 | for (i = 0; i < RTL8152_MAX_RX; i++) { | |
2336 | INIT_LIST_HEAD(&tp->rx_info[i].list); | |
2337 | ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL); | |
2338 | if (ret) | |
2339 | break; | |
2340 | } | |
2341 | ||
7bcf4f60 | 2342 | if (ret && ++i < RTL8152_MAX_RX) { |
2343 | struct list_head rx_queue; | |
2344 | unsigned long flags; | |
2345 | ||
2346 | INIT_LIST_HEAD(&rx_queue); | |
2347 | ||
2348 | do { | |
2349 | struct rx_agg *agg = &tp->rx_info[i++]; | |
2350 | struct urb *urb = agg->urb; | |
2351 | ||
2352 | urb->actual_length = 0; | |
2353 | list_add_tail(&agg->list, &rx_queue); | |
2354 | } while (i < RTL8152_MAX_RX); | |
2355 | ||
2356 | spin_lock_irqsave(&tp->rx_lock, flags); | |
2357 | list_splice_tail(&rx_queue, &tp->rx_done); | |
2358 | spin_unlock_irqrestore(&tp->rx_lock, flags); | |
2359 | } | |
2360 | ||
445f7f4d | 2361 | return ret; |
2362 | } | |
2363 | ||
2364 | static int rtl_stop_rx(struct r8152 *tp) | |
2365 | { | |
2366 | int i; | |
2367 | ||
2368 | for (i = 0; i < RTL8152_MAX_RX; i++) | |
2369 | usb_kill_urb(tp->rx_info[i].urb); | |
2370 | ||
d823ab68 | 2371 | while (!skb_queue_empty(&tp->rx_queue)) |
2372 | dev_kfree_skb(__skb_dequeue(&tp->rx_queue)); | |
2373 | ||
445f7f4d | 2374 | return 0; |
2375 | } | |
2376 | ||
507605a8 | 2377 | static int rtl_enable(struct r8152 *tp) |
2378 | { | |
2379 | u32 ocp_data; | |
ac718b69 | 2380 | |
2381 | r8152b_reset_packet_filter(tp); | |
2382 | ||
2383 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); | |
2384 | ocp_data |= CR_RE | CR_TE; | |
2385 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); | |
2386 | ||
00a5e360 | 2387 | rxdy_gated_en(tp, false); |
ac718b69 | 2388 | |
aa2e0926 | 2389 | return 0; |
ac718b69 | 2390 | } |
2391 | ||
507605a8 | 2392 | static int rtl8152_enable(struct r8152 *tp) |
2393 | { | |
6871438c | 2394 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
2395 | return -ENODEV; | |
2396 | ||
507605a8 | 2397 | set_tx_qlen(tp); |
2398 | rtl_set_eee_plus(tp); | |
2399 | ||
2400 | return rtl_enable(tp); | |
2401 | } | |
2402 | ||
65b82d69 | 2403 | static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp) |
2404 | { | |
2405 | ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN, | |
2406 | OWN_UPDATE | OWN_CLEAR); | |
2407 | } | |
2408 | ||
464ec10a | 2409 | static void r8153_set_rx_early_timeout(struct r8152 *tp) |
43779f8d | 2410 | { |
464ec10a | 2411 | u32 ocp_data = tp->coalesce / 8; |
43779f8d | 2412 | |
65b82d69 | 2413 | switch (tp->version) { |
2414 | case RTL_VER_03: | |
2415 | case RTL_VER_04: | |
2416 | case RTL_VER_05: | |
2417 | case RTL_VER_06: | |
2418 | ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, | |
2419 | ocp_data); | |
2420 | break; | |
2421 | ||
2422 | case RTL_VER_08: | |
2423 | case RTL_VER_09: | |
2424 | /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout | |
2425 | * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns. | |
2426 | */ | |
2427 | ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, | |
2428 | 128 / 8); | |
2429 | ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR, | |
2430 | ocp_data); | |
2431 | r8153b_rx_agg_chg_indicate(tp); | |
2432 | break; | |
2433 | ||
2434 | default: | |
2435 | break; | |
2436 | } | |
464ec10a | 2437 | } |
2438 | ||
2439 | static void r8153_set_rx_early_size(struct r8152 *tp) | |
2440 | { | |
65b82d69 | 2441 | u32 ocp_data = agg_buf_sz - rx_reserved_size(tp->netdev->mtu); |
464ec10a | 2442 | |
65b82d69 | 2443 | switch (tp->version) { |
2444 | case RTL_VER_03: | |
2445 | case RTL_VER_04: | |
2446 | case RTL_VER_05: | |
2447 | case RTL_VER_06: | |
2448 | ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, | |
2449 | ocp_data / 4); | |
2450 | break; | |
2451 | case RTL_VER_08: | |
2452 | case RTL_VER_09: | |
2453 | ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, | |
2454 | ocp_data / 8); | |
2455 | r8153b_rx_agg_chg_indicate(tp); | |
2456 | break; | |
2457 | default: | |
2458 | WARN_ON_ONCE(1); | |
2459 | break; | |
2460 | } | |
43779f8d | 2461 | } |
2462 | ||
2463 | static int rtl8153_enable(struct r8152 *tp) | |
2464 | { | |
6871438c | 2465 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
2466 | return -ENODEV; | |
2467 | ||
43779f8d | 2468 | set_tx_qlen(tp); |
2469 | rtl_set_eee_plus(tp); | |
464ec10a | 2470 | r8153_set_rx_early_timeout(tp); |
2471 | r8153_set_rx_early_size(tp); | |
43779f8d | 2472 | |
2473 | return rtl_enable(tp); | |
2474 | } | |
2475 | ||
d70b1137 | 2476 | static void rtl_disable(struct r8152 *tp) |
ac718b69 | 2477 | { |
ebc2ec48 | 2478 | u32 ocp_data; |
2479 | int i; | |
ac718b69 | 2480 | |
6871438c | 2481 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) { |
2482 | rtl_drop_queued_tx(tp); | |
2483 | return; | |
2484 | } | |
2485 | ||
ac718b69 | 2486 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); |
2487 | ocp_data &= ~RCR_ACPT_ALL; | |
2488 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
2489 | ||
00a5e360 | 2490 | rtl_drop_queued_tx(tp); |
ebc2ec48 | 2491 | |
2492 | for (i = 0; i < RTL8152_MAX_TX; i++) | |
2493 | usb_kill_urb(tp->tx_info[i].urb); | |
ac718b69 | 2494 | |
00a5e360 | 2495 | rxdy_gated_en(tp, true); |
ac718b69 | 2496 | |
2497 | for (i = 0; i < 1000; i++) { | |
2498 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
2499 | if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY) | |
2500 | break; | |
8ddfa077 | 2501 | usleep_range(1000, 2000); |
ac718b69 | 2502 | } |
2503 | ||
2504 | for (i = 0; i < 1000; i++) { | |
2505 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY) | |
2506 | break; | |
8ddfa077 | 2507 | usleep_range(1000, 2000); |
ac718b69 | 2508 | } |
2509 | ||
445f7f4d | 2510 | rtl_stop_rx(tp); |
ac718b69 | 2511 | |
2512 | rtl8152_nic_reset(tp); | |
2513 | } | |
2514 | ||
00a5e360 | 2515 | static void r8152_power_cut_en(struct r8152 *tp, bool enable) |
2516 | { | |
2517 | u32 ocp_data; | |
2518 | ||
2519 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); | |
2520 | if (enable) | |
2521 | ocp_data |= POWER_CUT; | |
2522 | else | |
2523 | ocp_data &= ~POWER_CUT; | |
2524 | ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); | |
2525 | ||
2526 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); | |
2527 | ocp_data &= ~RESUME_INDICATE; | |
2528 | ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); | |
00a5e360 | 2529 | } |
2530 | ||
c5554298 | 2531 | static void rtl_rx_vlan_en(struct r8152 *tp, bool enable) |
2532 | { | |
2533 | u32 ocp_data; | |
2534 | ||
2535 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); | |
2536 | if (enable) | |
2537 | ocp_data |= CPCR_RX_VLAN; | |
2538 | else | |
2539 | ocp_data &= ~CPCR_RX_VLAN; | |
2540 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); | |
2541 | } | |
2542 | ||
2543 | static int rtl8152_set_features(struct net_device *dev, | |
2544 | netdev_features_t features) | |
2545 | { | |
2546 | netdev_features_t changed = features ^ dev->features; | |
2547 | struct r8152 *tp = netdev_priv(dev); | |
405f8a0e | 2548 | int ret; |
2549 | ||
2550 | ret = usb_autopm_get_interface(tp->intf); | |
2551 | if (ret < 0) | |
2552 | goto out; | |
c5554298 | 2553 | |
b5403273 | 2554 | mutex_lock(&tp->control); |
2555 | ||
c5554298 | 2556 | if (changed & NETIF_F_HW_VLAN_CTAG_RX) { |
2557 | if (features & NETIF_F_HW_VLAN_CTAG_RX) | |
2558 | rtl_rx_vlan_en(tp, true); | |
2559 | else | |
2560 | rtl_rx_vlan_en(tp, false); | |
2561 | } | |
2562 | ||
b5403273 | 2563 | mutex_unlock(&tp->control); |
2564 | ||
405f8a0e | 2565 | usb_autopm_put_interface(tp->intf); |
2566 | ||
2567 | out: | |
2568 | return ret; | |
c5554298 | 2569 | } |
2570 | ||
21ff2e89 | 2571 | #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) |
2572 | ||
2573 | static u32 __rtl_get_wol(struct r8152 *tp) | |
2574 | { | |
2575 | u32 ocp_data; | |
2576 | u32 wolopts = 0; | |
2577 | ||
21ff2e89 | 2578 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); |
2579 | if (ocp_data & LINK_ON_WAKE_EN) | |
2580 | wolopts |= WAKE_PHY; | |
2581 | ||
2582 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); | |
2583 | if (ocp_data & UWF_EN) | |
2584 | wolopts |= WAKE_UCAST; | |
2585 | if (ocp_data & BWF_EN) | |
2586 | wolopts |= WAKE_BCAST; | |
2587 | if (ocp_data & MWF_EN) | |
2588 | wolopts |= WAKE_MCAST; | |
2589 | ||
2590 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); | |
2591 | if (ocp_data & MAGIC_EN) | |
2592 | wolopts |= WAKE_MAGIC; | |
2593 | ||
2594 | return wolopts; | |
2595 | } | |
2596 | ||
2597 | static void __rtl_set_wol(struct r8152 *tp, u32 wolopts) | |
2598 | { | |
2599 | u32 ocp_data; | |
2600 | ||
2601 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
2602 | ||
2603 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); | |
2604 | ocp_data &= ~LINK_ON_WAKE_EN; | |
2605 | if (wolopts & WAKE_PHY) | |
2606 | ocp_data |= LINK_ON_WAKE_EN; | |
2607 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); | |
2608 | ||
2609 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); | |
92f7d07d | 2610 | ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN); |
21ff2e89 | 2611 | if (wolopts & WAKE_UCAST) |
2612 | ocp_data |= UWF_EN; | |
2613 | if (wolopts & WAKE_BCAST) | |
2614 | ocp_data |= BWF_EN; | |
2615 | if (wolopts & WAKE_MCAST) | |
2616 | ocp_data |= MWF_EN; | |
21ff2e89 | 2617 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data); |
2618 | ||
2619 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
2620 | ||
2621 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); | |
2622 | ocp_data &= ~MAGIC_EN; | |
2623 | if (wolopts & WAKE_MAGIC) | |
2624 | ocp_data |= MAGIC_EN; | |
2625 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data); | |
2626 | ||
2627 | if (wolopts & WAKE_ANY) | |
2628 | device_set_wakeup_enable(&tp->udev->dev, true); | |
2629 | else | |
2630 | device_set_wakeup_enable(&tp->udev->dev, false); | |
2631 | } | |
2632 | ||
134f98bc | 2633 | static void r8153_mac_clk_spd(struct r8152 *tp, bool enable) |
2634 | { | |
2635 | /* MAC clock speed down */ | |
2636 | if (enable) { | |
2637 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, | |
2638 | ALDPS_SPDWN_RATIO); | |
2639 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, | |
2640 | EEE_SPDWN_RATIO); | |
2641 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, | |
2642 | PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN | | |
2643 | U1U2_SPDWN_EN | L1_SPDWN_EN); | |
2644 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, | |
2645 | PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN | | |
2646 | TP100_SPDWN_EN | TP500_SPDWN_EN | EEE_SPDWN_EN | | |
2647 | TP1000_SPDWN_EN); | |
2648 | } else { | |
2649 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0); | |
2650 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0); | |
2651 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0); | |
2652 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0); | |
2653 | } | |
2654 | } | |
2655 | ||
b214396f | 2656 | static void r8153_u1u2en(struct r8152 *tp, bool enable) |
2657 | { | |
2658 | u8 u1u2[8]; | |
2659 | ||
2660 | if (enable) | |
2661 | memset(u1u2, 0xff, sizeof(u1u2)); | |
2662 | else | |
2663 | memset(u1u2, 0x00, sizeof(u1u2)); | |
2664 | ||
2665 | usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2); | |
2666 | } | |
2667 | ||
65b82d69 | 2668 | static void r8153b_u1u2en(struct r8152 *tp, bool enable) |
2669 | { | |
2670 | u32 ocp_data; | |
2671 | ||
2672 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG); | |
2673 | if (enable) | |
2674 | ocp_data |= LPM_U1U2_EN; | |
2675 | else | |
2676 | ocp_data &= ~LPM_U1U2_EN; | |
2677 | ||
2678 | ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data); | |
2679 | } | |
2680 | ||
b214396f | 2681 | static void r8153_u2p3en(struct r8152 *tp, bool enable) |
2682 | { | |
2683 | u32 ocp_data; | |
2684 | ||
2685 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); | |
3cb3234e | 2686 | if (enable) |
b214396f | 2687 | ocp_data |= U2P3_ENABLE; |
2688 | else | |
2689 | ocp_data &= ~U2P3_ENABLE; | |
2690 | ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); | |
2691 | } | |
2692 | ||
65b82d69 | 2693 | static void r8153b_ups_flags_w1w0(struct r8152 *tp, u32 set, u32 clear) |
2694 | { | |
2695 | u32 ocp_data; | |
2696 | ||
2697 | ocp_data = ocp_read_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS); | |
2698 | ocp_data &= ~clear; | |
2699 | ocp_data |= set; | |
2700 | ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ocp_data); | |
2701 | } | |
2702 | ||
2703 | static void r8153b_green_en(struct r8152 *tp, bool enable) | |
2704 | { | |
2705 | u16 data; | |
2706 | ||
2707 | if (enable) { | |
2708 | sram_write(tp, 0x8045, 0); /* 10M abiq&ldvbias */ | |
2709 | sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */ | |
2710 | sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */ | |
2711 | } else { | |
2712 | sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */ | |
2713 | sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */ | |
2714 | sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */ | |
2715 | } | |
2716 | ||
2717 | data = sram_read(tp, SRAM_GREEN_CFG); | |
2718 | data |= GREEN_ETH_EN; | |
2719 | sram_write(tp, SRAM_GREEN_CFG, data); | |
2720 | ||
2721 | r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_GREEN, 0); | |
2722 | } | |
2723 | ||
c564b871 | 2724 | static u16 r8153_phy_status(struct r8152 *tp, u16 desired) |
2725 | { | |
2726 | u16 data; | |
2727 | int i; | |
2728 | ||
2729 | for (i = 0; i < 500; i++) { | |
2730 | data = ocp_reg_read(tp, OCP_PHY_STATUS); | |
2731 | data &= PHY_STAT_MASK; | |
2732 | if (desired) { | |
2733 | if (data == desired) | |
2734 | break; | |
2735 | } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN || | |
2736 | data == PHY_STAT_EXT_INIT) { | |
2737 | break; | |
2738 | } | |
2739 | ||
2740 | msleep(20); | |
44350abc YSY |
2741 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
2742 | break; | |
c564b871 | 2743 | } |
2744 | ||
2745 | return data; | |
2746 | } | |
2747 | ||
65b82d69 | 2748 | static void r8153b_ups_en(struct r8152 *tp, bool enable) |
2749 | { | |
2750 | u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT); | |
2751 | ||
2752 | if (enable) { | |
2753 | ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN; | |
2754 | ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); | |
2755 | ||
2756 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff); | |
2757 | ocp_data |= BIT(0); | |
2758 | ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data); | |
2759 | } else { | |
2760 | u16 data; | |
2761 | ||
2762 | ocp_data &= ~(UPS_EN | USP_PREWAKE); | |
2763 | ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); | |
2764 | ||
2765 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff); | |
2766 | ocp_data &= ~BIT(0); | |
2767 | ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data); | |
2768 | ||
2769 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); | |
2770 | ocp_data &= ~PCUT_STATUS; | |
2771 | ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); | |
2772 | ||
2773 | data = r8153_phy_status(tp, 0); | |
2774 | ||
2775 | switch (data) { | |
2776 | case PHY_STAT_PWRDN: | |
2777 | case PHY_STAT_EXT_INIT: | |
2778 | r8153b_green_en(tp, | |
2779 | test_bit(GREEN_ETHERNET, &tp->flags)); | |
2780 | ||
2781 | data = r8152_mdio_read(tp, MII_BMCR); | |
2782 | data &= ~BMCR_PDOWN; | |
2783 | data |= BMCR_RESET; | |
2784 | r8152_mdio_write(tp, MII_BMCR, data); | |
2785 | ||
2786 | data = r8153_phy_status(tp, PHY_STAT_LAN_ON); | |
2787 | ||
2788 | default: | |
2789 | if (data != PHY_STAT_LAN_ON) | |
2790 | netif_warn(tp, link, tp->netdev, | |
2791 | "PHY not ready"); | |
2792 | break; | |
2793 | } | |
2794 | } | |
2795 | } | |
2796 | ||
b214396f | 2797 | static void r8153_power_cut_en(struct r8152 *tp, bool enable) |
2798 | { | |
2799 | u32 ocp_data; | |
2800 | ||
2801 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); | |
2802 | if (enable) | |
2803 | ocp_data |= PWR_EN | PHASE2_EN; | |
2804 | else | |
2805 | ocp_data &= ~(PWR_EN | PHASE2_EN); | |
2806 | ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); | |
2807 | ||
2808 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); | |
2809 | ocp_data &= ~PCUT_STATUS; | |
2810 | ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); | |
2811 | } | |
2812 | ||
65b82d69 | 2813 | static void r8153b_power_cut_en(struct r8152 *tp, bool enable) |
2814 | { | |
2815 | u32 ocp_data; | |
2816 | ||
2817 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); | |
2818 | if (enable) | |
2819 | ocp_data |= PWR_EN | PHASE2_EN; | |
2820 | else | |
2821 | ocp_data &= ~PWR_EN; | |
2822 | ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); | |
2823 | ||
2824 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); | |
2825 | ocp_data &= ~PCUT_STATUS; | |
2826 | ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); | |
2827 | } | |
2828 | ||
2829 | static void r8153b_queue_wake(struct r8152 *tp, bool enable) | |
2830 | { | |
2831 | u32 ocp_data; | |
2832 | ||
2833 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 0xd38a); | |
2834 | if (enable) | |
2835 | ocp_data |= BIT(0); | |
2836 | else | |
2837 | ocp_data &= ~BIT(0); | |
2838 | ocp_write_byte(tp, MCU_TYPE_PLA, 0xd38a, ocp_data); | |
2839 | ||
2840 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 0xd38c); | |
2841 | ocp_data &= ~BIT(0); | |
2842 | ocp_write_byte(tp, MCU_TYPE_PLA, 0xd38c, ocp_data); | |
2843 | } | |
2844 | ||
7daed8dc | 2845 | static bool rtl_can_wakeup(struct r8152 *tp) |
2846 | { | |
2847 | struct usb_device *udev = tp->udev; | |
2848 | ||
2849 | return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP); | |
2850 | } | |
2851 | ||
9a4be1bd | 2852 | static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable) |
2853 | { | |
2854 | if (enable) { | |
2855 | u32 ocp_data; | |
2856 | ||
2857 | __rtl_set_wol(tp, WAKE_ANY); | |
2858 | ||
2859 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
2860 | ||
2861 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); | |
2862 | ocp_data |= LINK_OFF_WAKE_EN; | |
2863 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); | |
2864 | ||
2865 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
2866 | } else { | |
f95ae8a0 | 2867 | u32 ocp_data; |
2868 | ||
9a4be1bd | 2869 | __rtl_set_wol(tp, tp->saved_wolopts); |
f95ae8a0 | 2870 | |
2871 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); | |
2872 | ||
2873 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); | |
2874 | ocp_data &= ~LINK_OFF_WAKE_EN; | |
2875 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); | |
2876 | ||
2877 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); | |
2609af19 | 2878 | } |
2879 | } | |
f95ae8a0 | 2880 | |
2609af19 | 2881 | static void rtl8153_runtime_enable(struct r8152 *tp, bool enable) |
2882 | { | |
2609af19 | 2883 | if (enable) { |
2884 | r8153_u1u2en(tp, false); | |
2885 | r8153_u2p3en(tp, false); | |
134f98bc | 2886 | r8153_mac_clk_spd(tp, true); |
02552754 | 2887 | rtl_runtime_suspend_enable(tp, true); |
2609af19 | 2888 | } else { |
02552754 | 2889 | rtl_runtime_suspend_enable(tp, false); |
134f98bc | 2890 | r8153_mac_clk_spd(tp, false); |
3cb3234e | 2891 | |
2892 | switch (tp->version) { | |
2893 | case RTL_VER_03: | |
2894 | case RTL_VER_04: | |
2895 | break; | |
2896 | case RTL_VER_05: | |
2897 | case RTL_VER_06: | |
2898 | default: | |
2899 | r8153_u2p3en(tp, true); | |
2900 | break; | |
2901 | } | |
2902 | ||
b214396f | 2903 | r8153_u1u2en(tp, true); |
9a4be1bd | 2904 | } |
2905 | } | |
2906 | ||
65b82d69 | 2907 | static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable) |
2908 | { | |
2909 | if (enable) { | |
2910 | r8153b_queue_wake(tp, true); | |
2911 | r8153b_u1u2en(tp, false); | |
2912 | r8153_u2p3en(tp, false); | |
2913 | rtl_runtime_suspend_enable(tp, true); | |
2914 | r8153b_ups_en(tp, true); | |
2915 | } else { | |
2916 | r8153b_ups_en(tp, false); | |
2917 | r8153b_queue_wake(tp, false); | |
2918 | rtl_runtime_suspend_enable(tp, false); | |
2919 | r8153_u2p3en(tp, true); | |
2920 | r8153b_u1u2en(tp, true); | |
2921 | } | |
2922 | } | |
2923 | ||
4349968a | 2924 | static void r8153_teredo_off(struct r8152 *tp) |
2925 | { | |
2926 | u32 ocp_data; | |
2927 | ||
65b82d69 | 2928 | switch (tp->version) { |
2929 | case RTL_VER_01: | |
2930 | case RTL_VER_02: | |
2931 | case RTL_VER_03: | |
2932 | case RTL_VER_04: | |
2933 | case RTL_VER_05: | |
2934 | case RTL_VER_06: | |
2935 | case RTL_VER_07: | |
2936 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); | |
2937 | ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | | |
2938 | OOB_TEREDO_EN); | |
2939 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); | |
2940 | break; | |
2941 | ||
2942 | case RTL_VER_08: | |
2943 | case RTL_VER_09: | |
2944 | /* The bit 0 ~ 7 are relative with teredo settings. They are | |
2945 | * W1C (write 1 to clear), so set all 1 to disable it. | |
2946 | */ | |
2947 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff); | |
2948 | break; | |
2949 | ||
2950 | default: | |
2951 | break; | |
2952 | } | |
4349968a | 2953 | |
2954 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE); | |
2955 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0); | |
2956 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0); | |
2957 | } | |
2958 | ||
93fe9b18 | 2959 | static void rtl_reset_bmu(struct r8152 *tp) |
2960 | { | |
2961 | u32 ocp_data; | |
2962 | ||
2963 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET); | |
2964 | ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT); | |
2965 | ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); | |
2966 | ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT; | |
2967 | ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); | |
2968 | } | |
2969 | ||
cda9fb01 | 2970 | static void r8152_aldps_en(struct r8152 *tp, bool enable) |
4349968a | 2971 | { |
cda9fb01 | 2972 | if (enable) { |
2973 | ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS | | |
2974 | LINKENA | DIS_SDSAVE); | |
2975 | } else { | |
2976 | ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | | |
2977 | DIS_SDSAVE); | |
2978 | msleep(20); | |
2979 | } | |
4349968a | 2980 | } |
2981 | ||
e6449539 | 2982 | static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg) |
2983 | { | |
2984 | ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev); | |
2985 | ocp_reg_write(tp, OCP_EEE_DATA, reg); | |
2986 | ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev); | |
2987 | } | |
2988 | ||
2989 | static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg) | |
2990 | { | |
2991 | u16 data; | |
2992 | ||
2993 | r8152_mmd_indirect(tp, dev, reg); | |
2994 | data = ocp_reg_read(tp, OCP_EEE_DATA); | |
2995 | ocp_reg_write(tp, OCP_EEE_AR, 0x0000); | |
2996 | ||
2997 | return data; | |
2998 | } | |
2999 | ||
3000 | static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data) | |
3001 | { | |
3002 | r8152_mmd_indirect(tp, dev, reg); | |
3003 | ocp_reg_write(tp, OCP_EEE_DATA, data); | |
3004 | ocp_reg_write(tp, OCP_EEE_AR, 0x0000); | |
3005 | } | |
3006 | ||
3007 | static void r8152_eee_en(struct r8152 *tp, bool enable) | |
3008 | { | |
3009 | u16 config1, config2, config3; | |
3010 | u32 ocp_data; | |
3011 | ||
3012 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); | |
3013 | config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask; | |
3014 | config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2); | |
3015 | config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask; | |
3016 | ||
3017 | if (enable) { | |
3018 | ocp_data |= EEE_RX_EN | EEE_TX_EN; | |
3019 | config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN; | |
3020 | config1 |= sd_rise_time(1); | |
3021 | config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN; | |
3022 | config3 |= fast_snr(42); | |
3023 | } else { | |
3024 | ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); | |
3025 | config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | | |
3026 | RX_QUIET_EN); | |
3027 | config1 |= sd_rise_time(7); | |
3028 | config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN); | |
3029 | config3 |= fast_snr(511); | |
3030 | } | |
3031 | ||
3032 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); | |
3033 | ocp_reg_write(tp, OCP_EEE_CONFIG1, config1); | |
3034 | ocp_reg_write(tp, OCP_EEE_CONFIG2, config2); | |
3035 | ocp_reg_write(tp, OCP_EEE_CONFIG3, config3); | |
3036 | } | |
3037 | ||
3038 | static void r8152b_enable_eee(struct r8152 *tp) | |
3039 | { | |
3040 | r8152_eee_en(tp, true); | |
3041 | r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX); | |
3042 | } | |
3043 | ||
3044 | static void r8152b_enable_fc(struct r8152 *tp) | |
3045 | { | |
3046 | u16 anar; | |
3047 | ||
3048 | anar = r8152_mdio_read(tp, MII_ADVERTISE); | |
3049 | anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; | |
3050 | r8152_mdio_write(tp, MII_ADVERTISE, anar); | |
3051 | } | |
3052 | ||
d70b1137 | 3053 | static void rtl8152_disable(struct r8152 *tp) |
3054 | { | |
cda9fb01 | 3055 | r8152_aldps_en(tp, false); |
d70b1137 | 3056 | rtl_disable(tp); |
cda9fb01 | 3057 | r8152_aldps_en(tp, true); |
d70b1137 | 3058 | } |
3059 | ||
4349968a | 3060 | static void r8152b_hw_phy_cfg(struct r8152 *tp) |
3061 | { | |
ef39df8e | 3062 | r8152b_enable_eee(tp); |
3063 | r8152_aldps_en(tp, true); | |
3064 | r8152b_enable_fc(tp); | |
f0cbe0ac | 3065 | |
aa66a5f1 | 3066 | set_bit(PHY_RESET, &tp->flags); |
4349968a | 3067 | } |
3068 | ||
ac718b69 | 3069 | static void r8152b_exit_oob(struct r8152 *tp) |
3070 | { | |
db8515ef | 3071 | u32 ocp_data; |
3072 | int i; | |
ac718b69 | 3073 | |
3074 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
3075 | ocp_data &= ~RCR_ACPT_ALL; | |
3076 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
3077 | ||
00a5e360 | 3078 | rxdy_gated_en(tp, true); |
da9bd117 | 3079 | r8153_teredo_off(tp); |
ac718b69 | 3080 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); |
3081 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); | |
3082 | ||
3083 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
3084 | ocp_data &= ~NOW_IS_OOB; | |
3085 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
3086 | ||
3087 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
3088 | ocp_data &= ~MCU_BORW_EN; | |
3089 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
3090 | ||
3091 | for (i = 0; i < 1000; i++) { | |
3092 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
3093 | if (ocp_data & LINK_LIST_READY) | |
3094 | break; | |
8ddfa077 | 3095 | usleep_range(1000, 2000); |
ac718b69 | 3096 | } |
3097 | ||
3098 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
3099 | ocp_data |= RE_INIT_LL; | |
3100 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
3101 | ||
3102 | for (i = 0; i < 1000; i++) { | |
3103 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
3104 | if (ocp_data & LINK_LIST_READY) | |
3105 | break; | |
8ddfa077 | 3106 | usleep_range(1000, 2000); |
ac718b69 | 3107 | } |
3108 | ||
3109 | rtl8152_nic_reset(tp); | |
3110 | ||
3111 | /* rx share fifo credit full threshold */ | |
3112 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); | |
3113 | ||
a3cc465d | 3114 | if (tp->udev->speed == USB_SPEED_FULL || |
3115 | tp->udev->speed == USB_SPEED_LOW) { | |
ac718b69 | 3116 | /* rx share fifo credit near full threshold */ |
3117 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, | |
3118 | RXFIFO_THR2_FULL); | |
3119 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, | |
3120 | RXFIFO_THR3_FULL); | |
3121 | } else { | |
3122 | /* rx share fifo credit near full threshold */ | |
3123 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, | |
3124 | RXFIFO_THR2_HIGH); | |
3125 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, | |
3126 | RXFIFO_THR3_HIGH); | |
3127 | } | |
3128 | ||
3129 | /* TX share fifo free credit full threshold */ | |
3130 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL); | |
3131 | ||
3132 | ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD); | |
8e1f51bd | 3133 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH); |
ac718b69 | 3134 | ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA, |
3135 | TEST_MODE_DISABLE | TX_SIZE_ADJUST1); | |
3136 | ||
c5554298 | 3137 | rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); |
ac718b69 | 3138 | |
3139 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); | |
3140 | ||
3141 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); | |
3142 | ocp_data |= TCR0_AUTO_FIFO; | |
3143 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); | |
3144 | } | |
3145 | ||
3146 | static void r8152b_enter_oob(struct r8152 *tp) | |
3147 | { | |
45f4a19f | 3148 | u32 ocp_data; |
3149 | int i; | |
ac718b69 | 3150 | |
3151 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
3152 | ocp_data &= ~NOW_IS_OOB; | |
3153 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
3154 | ||
3155 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); | |
3156 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); | |
3157 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB); | |
3158 | ||
d70b1137 | 3159 | rtl_disable(tp); |
ac718b69 | 3160 | |
3161 | for (i = 0; i < 1000; i++) { | |
3162 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
3163 | if (ocp_data & LINK_LIST_READY) | |
3164 | break; | |
8ddfa077 | 3165 | usleep_range(1000, 2000); |
ac718b69 | 3166 | } |
3167 | ||
3168 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
3169 | ocp_data |= RE_INIT_LL; | |
3170 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
3171 | ||
3172 | for (i = 0; i < 1000; i++) { | |
3173 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
3174 | if (ocp_data & LINK_LIST_READY) | |
3175 | break; | |
8ddfa077 | 3176 | usleep_range(1000, 2000); |
ac718b69 | 3177 | } |
3178 | ||
3179 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); | |
3180 | ||
c5554298 | 3181 | rtl_rx_vlan_en(tp, true); |
ac718b69 | 3182 | |
3183 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); | |
3184 | ocp_data |= ALDPS_PROXY_MODE; | |
3185 | ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); | |
3186 | ||
3187 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
3188 | ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; | |
3189 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
3190 | ||
00a5e360 | 3191 | rxdy_gated_en(tp, false); |
ac718b69 | 3192 | |
3193 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
3194 | ocp_data |= RCR_APM | RCR_AM | RCR_AB; | |
3195 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
3196 | } | |
3197 | ||
65b82d69 | 3198 | static int r8153_patch_request(struct r8152 *tp, bool request) |
3199 | { | |
3200 | u16 data; | |
3201 | int i; | |
3202 | ||
3203 | data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD); | |
3204 | if (request) | |
3205 | data |= PATCH_REQUEST; | |
3206 | else | |
3207 | data &= ~PATCH_REQUEST; | |
3208 | ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data); | |
3209 | ||
3210 | for (i = 0; request && i < 5000; i++) { | |
3211 | usleep_range(1000, 2000); | |
3212 | if (ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY) | |
3213 | break; | |
3214 | } | |
3215 | ||
3216 | if (request && !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) { | |
3217 | netif_err(tp, drv, tp->netdev, "patch request fail\n"); | |
3218 | r8153_patch_request(tp, false); | |
3219 | return -ETIME; | |
3220 | } else { | |
3221 | return 0; | |
3222 | } | |
3223 | } | |
3224 | ||
e6449539 | 3225 | static void r8153_aldps_en(struct r8152 *tp, bool enable) |
3226 | { | |
3227 | u16 data; | |
3228 | ||
3229 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
3230 | if (enable) { | |
3231 | data |= EN_ALDPS; | |
3232 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
3233 | } else { | |
4214cc55 | 3234 | int i; |
3235 | ||
e6449539 | 3236 | data &= ~EN_ALDPS; |
3237 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
4214cc55 | 3238 | for (i = 0; i < 20; i++) { |
3239 | usleep_range(1000, 2000); | |
3240 | if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100) | |
3241 | break; | |
3242 | } | |
e6449539 | 3243 | } |
3244 | } | |
3245 | ||
65b82d69 | 3246 | static void r8153b_aldps_en(struct r8152 *tp, bool enable) |
3247 | { | |
3248 | r8153_aldps_en(tp, enable); | |
3249 | ||
3250 | if (enable) | |
3251 | r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_ALDPS, 0); | |
3252 | else | |
3253 | r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_ALDPS); | |
3254 | } | |
3255 | ||
e6449539 | 3256 | static void r8153_eee_en(struct r8152 *tp, bool enable) |
3257 | { | |
3258 | u32 ocp_data; | |
3259 | u16 config; | |
3260 | ||
3261 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); | |
3262 | config = ocp_reg_read(tp, OCP_EEE_CFG); | |
3263 | ||
3264 | if (enable) { | |
3265 | ocp_data |= EEE_RX_EN | EEE_TX_EN; | |
3266 | config |= EEE10_EN; | |
3267 | } else { | |
3268 | ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); | |
3269 | config &= ~EEE10_EN; | |
3270 | } | |
3271 | ||
3272 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); | |
3273 | ocp_reg_write(tp, OCP_EEE_CFG, config); | |
3274 | } | |
3275 | ||
65b82d69 | 3276 | static void r8153b_eee_en(struct r8152 *tp, bool enable) |
3277 | { | |
3278 | r8153_eee_en(tp, enable); | |
3279 | ||
3280 | if (enable) | |
3281 | r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_EEE, 0); | |
3282 | else | |
3283 | r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_EEE); | |
3284 | } | |
3285 | ||
3286 | static void r8153b_enable_fc(struct r8152 *tp) | |
3287 | { | |
3288 | r8152b_enable_fc(tp); | |
3289 | r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_FLOW_CTR, 0); | |
3290 | } | |
3291 | ||
43779f8d | 3292 | static void r8153_hw_phy_cfg(struct r8152 *tp) |
3293 | { | |
3294 | u32 ocp_data; | |
3295 | u16 data; | |
3296 | ||
d768c61b | 3297 | /* disable ALDPS before updating the PHY parameters */ |
3298 | r8153_aldps_en(tp, false); | |
fb02eb4a | 3299 | |
d768c61b | 3300 | /* disable EEE before updating the PHY parameters */ |
3301 | r8153_eee_en(tp, false); | |
3302 | ocp_reg_write(tp, OCP_EEE_ADV, 0); | |
43779f8d | 3303 | |
3304 | if (tp->version == RTL_VER_03) { | |
3305 | data = ocp_reg_read(tp, OCP_EEE_CFG); | |
3306 | data &= ~CTAP_SHORT_EN; | |
3307 | ocp_reg_write(tp, OCP_EEE_CFG, data); | |
3308 | } | |
3309 | ||
3310 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
3311 | data |= EEE_CLKDIV_EN; | |
3312 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
3313 | ||
3314 | data = ocp_reg_read(tp, OCP_DOWN_SPEED); | |
3315 | data |= EN_10M_BGOFF; | |
3316 | ocp_reg_write(tp, OCP_DOWN_SPEED, data); | |
3317 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
3318 | data |= EN_10M_PLLOFF; | |
3319 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
b4d99def | 3320 | sram_write(tp, SRAM_IMPEDANCE, 0x0b13); |
43779f8d | 3321 | |
3322 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); | |
3323 | ocp_data |= PFM_PWM_SWITCH; | |
3324 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); | |
3325 | ||
b4d99def | 3326 | /* Enable LPF corner auto tune */ |
3327 | sram_write(tp, SRAM_LPF_CFG, 0xf70f); | |
43779f8d | 3328 | |
b4d99def | 3329 | /* Adjust 10M Amplitude */ |
3330 | sram_write(tp, SRAM_10M_AMP1, 0x00af); | |
3331 | sram_write(tp, SRAM_10M_AMP2, 0x0208); | |
aa66a5f1 | 3332 | |
af0287ec | 3333 | r8153_eee_en(tp, true); |
3334 | ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX); | |
3335 | ||
ef39df8e | 3336 | r8153_aldps_en(tp, true); |
3337 | r8152b_enable_fc(tp); | |
3338 | ||
3cb3234e | 3339 | switch (tp->version) { |
3340 | case RTL_VER_03: | |
3341 | case RTL_VER_04: | |
3342 | break; | |
3343 | case RTL_VER_05: | |
3344 | case RTL_VER_06: | |
3345 | default: | |
3346 | r8153_u2p3en(tp, true); | |
3347 | break; | |
3348 | } | |
3349 | ||
aa66a5f1 | 3350 | set_bit(PHY_RESET, &tp->flags); |
43779f8d | 3351 | } |
3352 | ||
65b82d69 | 3353 | static u32 r8152_efuse_read(struct r8152 *tp, u8 addr) |
3354 | { | |
3355 | u32 ocp_data; | |
3356 | ||
3357 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr); | |
3358 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD); | |
3359 | ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9; /* data of bit16 */ | |
3360 | ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA); | |
3361 | ||
3362 | return ocp_data; | |
3363 | } | |
3364 | ||
3365 | static void r8153b_hw_phy_cfg(struct r8152 *tp) | |
3366 | { | |
3367 | u32 ocp_data, ups_flags = 0; | |
3368 | u16 data; | |
3369 | ||
3370 | /* disable ALDPS before updating the PHY parameters */ | |
3371 | r8153b_aldps_en(tp, false); | |
3372 | ||
3373 | /* disable EEE before updating the PHY parameters */ | |
3374 | r8153b_eee_en(tp, false); | |
3375 | ocp_reg_write(tp, OCP_EEE_ADV, 0); | |
3376 | ||
3377 | r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags)); | |
3378 | ||
3379 | data = sram_read(tp, SRAM_GREEN_CFG); | |
3380 | data |= R_TUNE_EN; | |
3381 | sram_write(tp, SRAM_GREEN_CFG, data); | |
3382 | data = ocp_reg_read(tp, OCP_NCTL_CFG); | |
3383 | data |= PGA_RETURN_EN; | |
3384 | ocp_reg_write(tp, OCP_NCTL_CFG, data); | |
3385 | ||
3386 | /* ADC Bias Calibration: | |
3387 | * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake | |
3388 | * bit (bit3) to rebuild the real 16-bit data. Write the data to the | |
3389 | * ADC ioffset. | |
3390 | */ | |
3391 | ocp_data = r8152_efuse_read(tp, 0x7d); | |
3392 | data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7)); | |
3393 | if (data != 0xffff) | |
3394 | ocp_reg_write(tp, OCP_ADC_IOFFSET, data); | |
3395 | ||
3396 | /* ups mode tx-link-pulse timing adjustment: | |
3397 | * rg_saw_cnt = OCP reg 0xC426 Bit[13:0] | |
3398 | * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt | |
3399 | */ | |
3400 | ocp_data = ocp_reg_read(tp, 0xc426); | |
3401 | ocp_data &= 0x3fff; | |
3402 | if (ocp_data) { | |
3403 | u32 swr_cnt_1ms_ini; | |
3404 | ||
3405 | swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK; | |
3406 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG); | |
3407 | ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini; | |
3408 | ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data); | |
3409 | } | |
3410 | ||
3411 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); | |
3412 | ocp_data |= PFM_PWM_SWITCH; | |
3413 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); | |
3414 | ||
3415 | /* Advnace EEE */ | |
3416 | if (!r8153_patch_request(tp, true)) { | |
3417 | data = ocp_reg_read(tp, OCP_POWER_CFG); | |
3418 | data |= EEE_CLKDIV_EN; | |
3419 | ocp_reg_write(tp, OCP_POWER_CFG, data); | |
3420 | ||
3421 | data = ocp_reg_read(tp, OCP_DOWN_SPEED); | |
3422 | data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV; | |
3423 | ocp_reg_write(tp, OCP_DOWN_SPEED, data); | |
3424 | ||
3425 | ocp_reg_write(tp, OCP_SYSCLK_CFG, 0); | |
3426 | ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5)); | |
3427 | ||
3428 | ups_flags |= UPS_FLAGS_EN_10M_CKDIV | UPS_FLAGS_250M_CKDIV | | |
3429 | UPS_FLAGS_EN_EEE_CKDIV | UPS_FLAGS_EEE_CMOD_LV_EN | | |
3430 | UPS_FLAGS_EEE_PLLOFF_GIGA; | |
3431 | ||
3432 | r8153_patch_request(tp, false); | |
3433 | } | |
3434 | ||
3435 | r8153b_ups_flags_w1w0(tp, ups_flags, 0); | |
3436 | ||
3437 | r8153b_eee_en(tp, true); | |
3438 | ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX); | |
3439 | ||
3440 | r8153b_aldps_en(tp, true); | |
3441 | r8153b_enable_fc(tp); | |
3442 | r8153_u2p3en(tp, true); | |
3443 | ||
3444 | set_bit(PHY_RESET, &tp->flags); | |
3445 | } | |
3446 | ||
43779f8d | 3447 | static void r8153_first_init(struct r8152 *tp) |
3448 | { | |
3449 | u32 ocp_data; | |
3450 | int i; | |
3451 | ||
134f98bc | 3452 | r8153_mac_clk_spd(tp, false); |
00a5e360 | 3453 | rxdy_gated_en(tp, true); |
43779f8d | 3454 | r8153_teredo_off(tp); |
3455 | ||
3456 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
3457 | ocp_data &= ~RCR_ACPT_ALL; | |
3458 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
3459 | ||
43779f8d | 3460 | rtl8152_nic_reset(tp); |
93fe9b18 | 3461 | rtl_reset_bmu(tp); |
43779f8d | 3462 | |
3463 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
3464 | ocp_data &= ~NOW_IS_OOB; | |
3465 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
3466 | ||
3467 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
3468 | ocp_data &= ~MCU_BORW_EN; | |
3469 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
3470 | ||
3471 | for (i = 0; i < 1000; i++) { | |
3472 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
3473 | if (ocp_data & LINK_LIST_READY) | |
3474 | break; | |
8ddfa077 | 3475 | usleep_range(1000, 2000); |
43779f8d | 3476 | } |
3477 | ||
3478 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
3479 | ocp_data |= RE_INIT_LL; | |
3480 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
3481 | ||
3482 | for (i = 0; i < 1000; i++) { | |
3483 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
3484 | if (ocp_data & LINK_LIST_READY) | |
3485 | break; | |
8ddfa077 | 3486 | usleep_range(1000, 2000); |
43779f8d | 3487 | } |
3488 | ||
c5554298 | 3489 | rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); |
43779f8d | 3490 | |
b65c0c9b | 3491 | ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; |
210c4f70 | 3492 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data); |
69b4b7a4 | 3493 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO); |
43779f8d | 3494 | |
3495 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); | |
3496 | ocp_data |= TCR0_AUTO_FIFO; | |
3497 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); | |
3498 | ||
3499 | rtl8152_nic_reset(tp); | |
3500 | ||
3501 | /* rx share fifo credit full threshold */ | |
3502 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); | |
3503 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL); | |
3504 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL); | |
3505 | /* TX share fifo free credit full threshold */ | |
3506 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2); | |
43779f8d | 3507 | } |
3508 | ||
3509 | static void r8153_enter_oob(struct r8152 *tp) | |
3510 | { | |
3511 | u32 ocp_data; | |
3512 | int i; | |
3513 | ||
134f98bc | 3514 | r8153_mac_clk_spd(tp, true); |
3515 | ||
43779f8d | 3516 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); |
3517 | ocp_data &= ~NOW_IS_OOB; | |
3518 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
3519 | ||
d70b1137 | 3520 | rtl_disable(tp); |
93fe9b18 | 3521 | rtl_reset_bmu(tp); |
43779f8d | 3522 | |
3523 | for (i = 0; i < 1000; i++) { | |
3524 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
3525 | if (ocp_data & LINK_LIST_READY) | |
3526 | break; | |
8ddfa077 | 3527 | usleep_range(1000, 2000); |
43779f8d | 3528 | } |
3529 | ||
3530 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); | |
3531 | ocp_data |= RE_INIT_LL; | |
3532 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); | |
3533 | ||
3534 | for (i = 0; i < 1000; i++) { | |
3535 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
3536 | if (ocp_data & LINK_LIST_READY) | |
3537 | break; | |
8ddfa077 | 3538 | usleep_range(1000, 2000); |
43779f8d | 3539 | } |
3540 | ||
b65c0c9b | 3541 | ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; |
210c4f70 | 3542 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data); |
43779f8d | 3543 | |
65b82d69 | 3544 | switch (tp->version) { |
3545 | case RTL_VER_03: | |
3546 | case RTL_VER_04: | |
3547 | case RTL_VER_05: | |
3548 | case RTL_VER_06: | |
3549 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); | |
3550 | ocp_data &= ~TEREDO_WAKE_MASK; | |
3551 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); | |
3552 | break; | |
3553 | ||
3554 | case RTL_VER_08: | |
3555 | case RTL_VER_09: | |
3556 | /* Clear teredo wake event. bit[15:8] is the teredo wakeup | |
3557 | * type. Set it to zero. bits[7:0] are the W1C bits about | |
3558 | * the events. Set them to all 1 to clear them. | |
3559 | */ | |
3560 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff); | |
3561 | break; | |
3562 | ||
3563 | default: | |
3564 | break; | |
3565 | } | |
43779f8d | 3566 | |
c5554298 | 3567 | rtl_rx_vlan_en(tp, true); |
43779f8d | 3568 | |
3569 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR); | |
3570 | ocp_data |= ALDPS_PROXY_MODE; | |
3571 | ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data); | |
3572 | ||
3573 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); | |
3574 | ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; | |
3575 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); | |
3576 | ||
00a5e360 | 3577 | rxdy_gated_en(tp, false); |
43779f8d | 3578 | |
3579 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
3580 | ocp_data |= RCR_APM | RCR_AM | RCR_AB; | |
3581 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
3582 | } | |
3583 | ||
d70b1137 | 3584 | static void rtl8153_disable(struct r8152 *tp) |
3585 | { | |
cda9fb01 | 3586 | r8153_aldps_en(tp, false); |
d70b1137 | 3587 | rtl_disable(tp); |
93fe9b18 | 3588 | rtl_reset_bmu(tp); |
cda9fb01 | 3589 | r8153_aldps_en(tp, true); |
d70b1137 | 3590 | } |
3591 | ||
65b82d69 | 3592 | static void rtl8153b_disable(struct r8152 *tp) |
3593 | { | |
3594 | r8153b_aldps_en(tp, false); | |
3595 | rtl_disable(tp); | |
3596 | rtl_reset_bmu(tp); | |
3597 | r8153b_aldps_en(tp, true); | |
3598 | } | |
3599 | ||
ac718b69 | 3600 | static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex) |
3601 | { | |
43779f8d | 3602 | u16 bmcr, anar, gbcr; |
65b82d69 | 3603 | enum spd_duplex speed_duplex; |
ac718b69 | 3604 | int ret = 0; |
3605 | ||
ac718b69 | 3606 | anar = r8152_mdio_read(tp, MII_ADVERTISE); |
3607 | anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | | |
3608 | ADVERTISE_100HALF | ADVERTISE_100FULL); | |
43779f8d | 3609 | if (tp->mii.supports_gmii) { |
3610 | gbcr = r8152_mdio_read(tp, MII_CTRL1000); | |
3611 | gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); | |
3612 | } else { | |
3613 | gbcr = 0; | |
3614 | } | |
ac718b69 | 3615 | |
3616 | if (autoneg == AUTONEG_DISABLE) { | |
3617 | if (speed == SPEED_10) { | |
3618 | bmcr = 0; | |
3619 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
65b82d69 | 3620 | speed_duplex = FORCE_10M_HALF; |
ac718b69 | 3621 | } else if (speed == SPEED_100) { |
3622 | bmcr = BMCR_SPEED100; | |
3623 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; | |
65b82d69 | 3624 | speed_duplex = FORCE_100M_HALF; |
43779f8d | 3625 | } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { |
3626 | bmcr = BMCR_SPEED1000; | |
3627 | gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; | |
65b82d69 | 3628 | speed_duplex = NWAY_1000M_FULL; |
ac718b69 | 3629 | } else { |
3630 | ret = -EINVAL; | |
3631 | goto out; | |
3632 | } | |
3633 | ||
65b82d69 | 3634 | if (duplex == DUPLEX_FULL) { |
ac718b69 | 3635 | bmcr |= BMCR_FULLDPLX; |
65b82d69 | 3636 | if (speed != SPEED_1000) |
3637 | speed_duplex++; | |
3638 | } | |
ac718b69 | 3639 | } else { |
3640 | if (speed == SPEED_10) { | |
65b82d69 | 3641 | if (duplex == DUPLEX_FULL) { |
ac718b69 | 3642 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; |
65b82d69 | 3643 | speed_duplex = NWAY_10M_FULL; |
3644 | } else { | |
ac718b69 | 3645 | anar |= ADVERTISE_10HALF; |
65b82d69 | 3646 | speed_duplex = NWAY_10M_HALF; |
3647 | } | |
ac718b69 | 3648 | } else if (speed == SPEED_100) { |
3649 | if (duplex == DUPLEX_FULL) { | |
3650 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
3651 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; | |
65b82d69 | 3652 | speed_duplex = NWAY_100M_FULL; |
ac718b69 | 3653 | } else { |
3654 | anar |= ADVERTISE_10HALF; | |
3655 | anar |= ADVERTISE_100HALF; | |
65b82d69 | 3656 | speed_duplex = NWAY_100M_HALF; |
ac718b69 | 3657 | } |
43779f8d | 3658 | } else if (speed == SPEED_1000 && tp->mii.supports_gmii) { |
3659 | if (duplex == DUPLEX_FULL) { | |
3660 | anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; | |
3661 | anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; | |
3662 | gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; | |
3663 | } else { | |
3664 | anar |= ADVERTISE_10HALF; | |
3665 | anar |= ADVERTISE_100HALF; | |
3666 | gbcr |= ADVERTISE_1000HALF; | |
3667 | } | |
65b82d69 | 3668 | speed_duplex = NWAY_1000M_FULL; |
ac718b69 | 3669 | } else { |
3670 | ret = -EINVAL; | |
3671 | goto out; | |
3672 | } | |
3673 | ||
3674 | bmcr = BMCR_ANENABLE | BMCR_ANRESTART; | |
3675 | } | |
3676 | ||
fae56178 | 3677 | if (test_and_clear_bit(PHY_RESET, &tp->flags)) |
aa66a5f1 | 3678 | bmcr |= BMCR_RESET; |
3679 | ||
43779f8d | 3680 | if (tp->mii.supports_gmii) |
3681 | r8152_mdio_write(tp, MII_CTRL1000, gbcr); | |
3682 | ||
ac718b69 | 3683 | r8152_mdio_write(tp, MII_ADVERTISE, anar); |
3684 | r8152_mdio_write(tp, MII_BMCR, bmcr); | |
3685 | ||
65b82d69 | 3686 | switch (tp->version) { |
3687 | case RTL_VER_08: | |
3688 | case RTL_VER_09: | |
3689 | r8153b_ups_flags_w1w0(tp, ups_flags_speed(speed_duplex), | |
3690 | UPS_FLAGS_SPEED_MASK); | |
3691 | break; | |
3692 | ||
3693 | default: | |
3694 | break; | |
3695 | } | |
3696 | ||
fae56178 | 3697 | if (bmcr & BMCR_RESET) { |
aa66a5f1 | 3698 | int i; |
3699 | ||
aa66a5f1 | 3700 | for (i = 0; i < 50; i++) { |
3701 | msleep(20); | |
3702 | if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) | |
3703 | break; | |
3704 | } | |
3705 | } | |
3706 | ||
ac718b69 | 3707 | out: |
ac718b69 | 3708 | return ret; |
3709 | } | |
3710 | ||
d70b1137 | 3711 | static void rtl8152_up(struct r8152 *tp) |
3712 | { | |
3713 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
3714 | return; | |
3715 | ||
cda9fb01 | 3716 | r8152_aldps_en(tp, false); |
d70b1137 | 3717 | r8152b_exit_oob(tp); |
cda9fb01 | 3718 | r8152_aldps_en(tp, true); |
d70b1137 | 3719 | } |
3720 | ||
ac718b69 | 3721 | static void rtl8152_down(struct r8152 *tp) |
3722 | { | |
6871438c | 3723 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) { |
3724 | rtl_drop_queued_tx(tp); | |
3725 | return; | |
3726 | } | |
3727 | ||
00a5e360 | 3728 | r8152_power_cut_en(tp, false); |
cda9fb01 | 3729 | r8152_aldps_en(tp, false); |
ac718b69 | 3730 | r8152b_enter_oob(tp); |
cda9fb01 | 3731 | r8152_aldps_en(tp, true); |
ac718b69 | 3732 | } |
3733 | ||
d70b1137 | 3734 | static void rtl8153_up(struct r8152 *tp) |
3735 | { | |
3736 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
3737 | return; | |
3738 | ||
b214396f | 3739 | r8153_u1u2en(tp, false); |
3cb3234e | 3740 | r8153_u2p3en(tp, false); |
cda9fb01 | 3741 | r8153_aldps_en(tp, false); |
d70b1137 | 3742 | r8153_first_init(tp); |
cda9fb01 | 3743 | r8153_aldps_en(tp, true); |
3cb3234e | 3744 | |
3745 | switch (tp->version) { | |
3746 | case RTL_VER_03: | |
3747 | case RTL_VER_04: | |
3748 | break; | |
3749 | case RTL_VER_05: | |
3750 | case RTL_VER_06: | |
3751 | default: | |
3752 | r8153_u2p3en(tp, true); | |
3753 | break; | |
3754 | } | |
3755 | ||
b214396f | 3756 | r8153_u1u2en(tp, true); |
d70b1137 | 3757 | } |
3758 | ||
43779f8d | 3759 | static void rtl8153_down(struct r8152 *tp) |
3760 | { | |
6871438c | 3761 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) { |
3762 | rtl_drop_queued_tx(tp); | |
3763 | return; | |
3764 | } | |
3765 | ||
b9702723 | 3766 | r8153_u1u2en(tp, false); |
b214396f | 3767 | r8153_u2p3en(tp, false); |
b9702723 | 3768 | r8153_power_cut_en(tp, false); |
cda9fb01 | 3769 | r8153_aldps_en(tp, false); |
43779f8d | 3770 | r8153_enter_oob(tp); |
cda9fb01 | 3771 | r8153_aldps_en(tp, true); |
43779f8d | 3772 | } |
3773 | ||
65b82d69 | 3774 | static void rtl8153b_up(struct r8152 *tp) |
3775 | { | |
3776 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
3777 | return; | |
3778 | ||
3779 | r8153b_u1u2en(tp, false); | |
3780 | r8153_u2p3en(tp, false); | |
3781 | r8153b_aldps_en(tp, false); | |
3782 | ||
3783 | r8153_first_init(tp); | |
3784 | ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B); | |
3785 | ||
3786 | r8153b_aldps_en(tp, true); | |
3787 | r8153_u2p3en(tp, true); | |
3788 | r8153b_u1u2en(tp, true); | |
3789 | } | |
3790 | ||
3791 | static void rtl8153b_down(struct r8152 *tp) | |
3792 | { | |
3793 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) { | |
3794 | rtl_drop_queued_tx(tp); | |
3795 | return; | |
3796 | } | |
3797 | ||
3798 | r8153b_u1u2en(tp, false); | |
3799 | r8153_u2p3en(tp, false); | |
3800 | r8153b_power_cut_en(tp, false); | |
3801 | r8153b_aldps_en(tp, false); | |
3802 | r8153_enter_oob(tp); | |
3803 | r8153b_aldps_en(tp, true); | |
3804 | } | |
3805 | ||
2dd49e0f | 3806 | static bool rtl8152_in_nway(struct r8152 *tp) |
3807 | { | |
3808 | u16 nway_state; | |
3809 | ||
3810 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000); | |
3811 | tp->ocp_base = 0x2000; | |
3812 | ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */ | |
3813 | nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a); | |
3814 | ||
3815 | /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */ | |
3816 | if (nway_state & 0xc000) | |
3817 | return false; | |
3818 | else | |
3819 | return true; | |
3820 | } | |
3821 | ||
3822 | static bool rtl8153_in_nway(struct r8152 *tp) | |
3823 | { | |
3824 | u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff; | |
3825 | ||
3826 | if (phy_state == TXDIS_STATE || phy_state == ABD_STATE) | |
3827 | return false; | |
3828 | else | |
3829 | return true; | |
3830 | } | |
3831 | ||
ac718b69 | 3832 | static void set_carrier(struct r8152 *tp) |
3833 | { | |
3834 | struct net_device *netdev = tp->netdev; | |
ce594e98 | 3835 | struct napi_struct *napi = &tp->napi; |
ac718b69 | 3836 | u8 speed; |
3837 | ||
3838 | speed = rtl8152_get_speed(tp); | |
3839 | ||
3840 | if (speed & LINK_STATUS) { | |
51d979fa | 3841 | if (!netif_carrier_ok(netdev)) { |
c81229c9 | 3842 | tp->rtl_ops.enable(tp); |
ac718b69 | 3843 | set_bit(RTL8152_SET_RX_MODE, &tp->flags); |
de9bf29d | 3844 | netif_stop_queue(netdev); |
ce594e98 | 3845 | napi_disable(napi); |
ac718b69 | 3846 | netif_carrier_on(netdev); |
aa2e0926 | 3847 | rtl_start_rx(tp); |
41cec84c | 3848 | napi_enable(&tp->napi); |
de9bf29d | 3849 | netif_wake_queue(netdev); |
3850 | netif_info(tp, link, netdev, "carrier on\n"); | |
2f25abe6 | 3851 | } else if (netif_queue_stopped(netdev) && |
3852 | skb_queue_len(&tp->tx_queue) < tp->tx_qlen) { | |
3853 | netif_wake_queue(netdev); | |
ac718b69 | 3854 | } |
3855 | } else { | |
51d979fa | 3856 | if (netif_carrier_ok(netdev)) { |
ac718b69 | 3857 | netif_carrier_off(netdev); |
ce594e98 | 3858 | napi_disable(napi); |
c81229c9 | 3859 | tp->rtl_ops.disable(tp); |
ce594e98 | 3860 | napi_enable(napi); |
de9bf29d | 3861 | netif_info(tp, link, netdev, "carrier off\n"); |
ac718b69 | 3862 | } |
3863 | } | |
ac718b69 | 3864 | } |
3865 | ||
3866 | static void rtl_work_func_t(struct work_struct *work) | |
3867 | { | |
3868 | struct r8152 *tp = container_of(work, struct r8152, schedule.work); | |
3869 | ||
a1f83fee | 3870 | /* If the device is unplugged or !netif_running(), the workqueue |
3871 | * doesn't need to wake the device, and could return directly. | |
3872 | */ | |
3873 | if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev)) | |
3874 | return; | |
3875 | ||
9a4be1bd | 3876 | if (usb_autopm_get_interface(tp->intf) < 0) |
3877 | return; | |
3878 | ||
ac718b69 | 3879 | if (!test_bit(WORK_ENABLE, &tp->flags)) |
3880 | goto out1; | |
3881 | ||
b5403273 | 3882 | if (!mutex_trylock(&tp->control)) { |
3883 | schedule_delayed_work(&tp->schedule, 0); | |
3884 | goto out1; | |
3885 | } | |
3886 | ||
216a8349 | 3887 | if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags)) |
40a82917 | 3888 | set_carrier(tp); |
ac718b69 | 3889 | |
216a8349 | 3890 | if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags)) |
ac718b69 | 3891 | _rtl8152_set_rx_mode(tp->netdev); |
3892 | ||
d823ab68 | 3893 | /* don't schedule napi before linking */ |
216a8349 | 3894 | if (test_and_clear_bit(SCHEDULE_NAPI, &tp->flags) && |
3895 | netif_carrier_ok(tp->netdev)) | |
d823ab68 | 3896 | napi_schedule(&tp->napi); |
aa66a5f1 | 3897 | |
b5403273 | 3898 | mutex_unlock(&tp->control); |
3899 | ||
ac718b69 | 3900 | out1: |
9a4be1bd | 3901 | usb_autopm_put_interface(tp->intf); |
ac718b69 | 3902 | } |
3903 | ||
a028a9e0 | 3904 | static void rtl_hw_phy_work_func_t(struct work_struct *work) |
3905 | { | |
3906 | struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work); | |
3907 | ||
3908 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
3909 | return; | |
3910 | ||
3911 | if (usb_autopm_get_interface(tp->intf) < 0) | |
3912 | return; | |
3913 | ||
3914 | mutex_lock(&tp->control); | |
3915 | ||
3916 | tp->rtl_ops.hw_phy_cfg(tp); | |
3917 | ||
aa7e26b6 | 3918 | rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex); |
9d21c0d8 | 3919 | |
a028a9e0 | 3920 | mutex_unlock(&tp->control); |
3921 | ||
3922 | usb_autopm_put_interface(tp->intf); | |
3923 | } | |
3924 | ||
5ee3c60c | 3925 | #ifdef CONFIG_PM_SLEEP |
3926 | static int rtl_notifier(struct notifier_block *nb, unsigned long action, | |
3927 | void *data) | |
3928 | { | |
3929 | struct r8152 *tp = container_of(nb, struct r8152, pm_notifier); | |
3930 | ||
3931 | switch (action) { | |
3932 | case PM_HIBERNATION_PREPARE: | |
3933 | case PM_SUSPEND_PREPARE: | |
3934 | usb_autopm_get_interface(tp->intf); | |
3935 | break; | |
3936 | ||
3937 | case PM_POST_HIBERNATION: | |
3938 | case PM_POST_SUSPEND: | |
3939 | usb_autopm_put_interface(tp->intf); | |
3940 | break; | |
3941 | ||
3942 | case PM_POST_RESTORE: | |
3943 | case PM_RESTORE_PREPARE: | |
3944 | default: | |
3945 | break; | |
3946 | } | |
3947 | ||
3948 | return NOTIFY_DONE; | |
3949 | } | |
3950 | #endif | |
3951 | ||
ac718b69 | 3952 | static int rtl8152_open(struct net_device *netdev) |
3953 | { | |
3954 | struct r8152 *tp = netdev_priv(netdev); | |
3955 | int res = 0; | |
3956 | ||
7e9da481 | 3957 | res = alloc_all_mem(tp); |
3958 | if (res) | |
3959 | goto out; | |
3960 | ||
9a4be1bd | 3961 | res = usb_autopm_get_interface(tp->intf); |
ca0a7531 GR |
3962 | if (res < 0) |
3963 | goto out_free; | |
9a4be1bd | 3964 | |
b5403273 | 3965 | mutex_lock(&tp->control); |
3966 | ||
7e9da481 | 3967 | tp->rtl_ops.up(tp); |
3968 | ||
3d55f44f | 3969 | netif_carrier_off(netdev); |
3970 | netif_start_queue(netdev); | |
3971 | set_bit(WORK_ENABLE, &tp->flags); | |
db8515ef | 3972 | |
40a82917 | 3973 | res = usb_submit_urb(tp->intr_urb, GFP_KERNEL); |
3974 | if (res) { | |
3975 | if (res == -ENODEV) | |
3976 | netif_device_detach(tp->netdev); | |
4a8deae2 HW |
3977 | netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n", |
3978 | res); | |
ca0a7531 | 3979 | goto out_unlock; |
ac718b69 | 3980 | } |
ca0a7531 | 3981 | napi_enable(&tp->napi); |
ac718b69 | 3982 | |
b5403273 | 3983 | mutex_unlock(&tp->control); |
3984 | ||
9a4be1bd | 3985 | usb_autopm_put_interface(tp->intf); |
5ee3c60c | 3986 | #ifdef CONFIG_PM_SLEEP |
3987 | tp->pm_notifier.notifier_call = rtl_notifier; | |
3988 | register_pm_notifier(&tp->pm_notifier); | |
3989 | #endif | |
ca0a7531 | 3990 | return 0; |
ac718b69 | 3991 | |
ca0a7531 GR |
3992 | out_unlock: |
3993 | mutex_unlock(&tp->control); | |
3994 | usb_autopm_put_interface(tp->intf); | |
3995 | out_free: | |
3996 | free_all_mem(tp); | |
7e9da481 | 3997 | out: |
ac718b69 | 3998 | return res; |
3999 | } | |
4000 | ||
4001 | static int rtl8152_close(struct net_device *netdev) | |
4002 | { | |
4003 | struct r8152 *tp = netdev_priv(netdev); | |
4004 | int res = 0; | |
4005 | ||
5ee3c60c | 4006 | #ifdef CONFIG_PM_SLEEP |
4007 | unregister_pm_notifier(&tp->pm_notifier); | |
4008 | #endif | |
2e3c9c82 JS |
4009 | if (!test_bit(RTL8152_UNPLUG, &tp->flags)) |
4010 | napi_disable(&tp->napi); | |
ac718b69 | 4011 | clear_bit(WORK_ENABLE, &tp->flags); |
3d55f44f | 4012 | usb_kill_urb(tp->intr_urb); |
ac718b69 | 4013 | cancel_delayed_work_sync(&tp->schedule); |
4014 | netif_stop_queue(netdev); | |
9a4be1bd | 4015 | |
4016 | res = usb_autopm_get_interface(tp->intf); | |
53543db5 | 4017 | if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) { |
9a4be1bd | 4018 | rtl_drop_queued_tx(tp); |
d823ab68 | 4019 | rtl_stop_rx(tp); |
9a4be1bd | 4020 | } else { |
b5403273 | 4021 | mutex_lock(&tp->control); |
4022 | ||
9a4be1bd | 4023 | tp->rtl_ops.down(tp); |
b5403273 | 4024 | |
4025 | mutex_unlock(&tp->control); | |
4026 | ||
9a4be1bd | 4027 | usb_autopm_put_interface(tp->intf); |
4028 | } | |
ac718b69 | 4029 | |
7e9da481 | 4030 | free_all_mem(tp); |
4031 | ||
ac718b69 | 4032 | return res; |
4033 | } | |
4034 | ||
4f1d4d54 | 4035 | static void rtl_tally_reset(struct r8152 *tp) |
4036 | { | |
4037 | u32 ocp_data; | |
4038 | ||
4039 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY); | |
4040 | ocp_data |= TALLY_RESET; | |
4041 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data); | |
4042 | } | |
4043 | ||
ac718b69 | 4044 | static void r8152b_init(struct r8152 *tp) |
4045 | { | |
ebc2ec48 | 4046 | u32 ocp_data; |
2dd436da | 4047 | u16 data; |
ac718b69 | 4048 | |
6871438c | 4049 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
4050 | return; | |
4051 | ||
2dd436da | 4052 | data = r8152_mdio_read(tp, MII_BMCR); |
4053 | if (data & BMCR_PDOWN) { | |
4054 | data &= ~BMCR_PDOWN; | |
4055 | r8152_mdio_write(tp, MII_BMCR, data); | |
4056 | } | |
4057 | ||
cda9fb01 | 4058 | r8152_aldps_en(tp, false); |
d70b1137 | 4059 | |
ac718b69 | 4060 | if (tp->version == RTL_VER_01) { |
4061 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); | |
4062 | ocp_data &= ~LED_MODE_MASK; | |
4063 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); | |
4064 | } | |
4065 | ||
00a5e360 | 4066 | r8152_power_cut_en(tp, false); |
ac718b69 | 4067 | |
ac718b69 | 4068 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); |
4069 | ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH; | |
4070 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); | |
4071 | ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL); | |
4072 | ocp_data &= ~MCU_CLK_RATIO_MASK; | |
4073 | ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN; | |
4074 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data); | |
4075 | ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK | | |
4076 | SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK; | |
4077 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data); | |
4078 | ||
4f1d4d54 | 4079 | rtl_tally_reset(tp); |
ac718b69 | 4080 | |
ebc2ec48 | 4081 | /* enable rx aggregation */ |
ac718b69 | 4082 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); |
e90fba8d | 4083 | ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); |
ac718b69 | 4084 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); |
4085 | } | |
4086 | ||
43779f8d | 4087 | static void r8153_init(struct r8152 *tp) |
4088 | { | |
4089 | u32 ocp_data; | |
2dd436da | 4090 | u16 data; |
43779f8d | 4091 | int i; |
4092 | ||
6871438c | 4093 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
4094 | return; | |
4095 | ||
b9702723 | 4096 | r8153_u1u2en(tp, false); |
43779f8d | 4097 | |
4098 | for (i = 0; i < 500; i++) { | |
4099 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & | |
4100 | AUTOLOAD_DONE) | |
4101 | break; | |
44350abc | 4102 | |
43779f8d | 4103 | msleep(20); |
44350abc YSY |
4104 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
4105 | break; | |
43779f8d | 4106 | } |
4107 | ||
c564b871 | 4108 | data = r8153_phy_status(tp, 0); |
43779f8d | 4109 | |
2dd436da | 4110 | if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 || |
4111 | tp->version == RTL_VER_05) | |
4112 | ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L); | |
4113 | ||
4114 | data = r8152_mdio_read(tp, MII_BMCR); | |
4115 | if (data & BMCR_PDOWN) { | |
4116 | data &= ~BMCR_PDOWN; | |
4117 | r8152_mdio_write(tp, MII_BMCR, data); | |
4118 | } | |
4119 | ||
c564b871 | 4120 | data = r8153_phy_status(tp, PHY_STAT_LAN_ON); |
2dd436da | 4121 | |
b9702723 | 4122 | r8153_u2p3en(tp, false); |
43779f8d | 4123 | |
65bab84c | 4124 | if (tp->version == RTL_VER_04) { |
4125 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2); | |
4126 | ocp_data &= ~pwd_dn_scale_mask; | |
4127 | ocp_data |= pwd_dn_scale(96); | |
4128 | ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data); | |
4129 | ||
4130 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY); | |
4131 | ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND; | |
4132 | ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data); | |
4133 | } else if (tp->version == RTL_VER_05) { | |
4134 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0); | |
4135 | ocp_data &= ~ECM_ALDPS; | |
4136 | ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data); | |
4137 | ||
fb02eb4a | 4138 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); |
4139 | if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) | |
4140 | ocp_data &= ~DYNAMIC_BURST; | |
4141 | else | |
4142 | ocp_data |= DYNAMIC_BURST; | |
4143 | ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); | |
4144 | } else if (tp->version == RTL_VER_06) { | |
65bab84c | 4145 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); |
4146 | if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) | |
4147 | ocp_data &= ~DYNAMIC_BURST; | |
4148 | else | |
4149 | ocp_data |= DYNAMIC_BURST; | |
4150 | ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); | |
4151 | } | |
4152 | ||
4153 | ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2); | |
4154 | ocp_data |= EP4_FULL_FC; | |
4155 | ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data); | |
4156 | ||
43779f8d | 4157 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL); |
4158 | ocp_data &= ~TIMER11_EN; | |
4159 | ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data); | |
4160 | ||
43779f8d | 4161 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); |
4162 | ocp_data &= ~LED_MODE_MASK; | |
4163 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); | |
4164 | ||
65bab84c | 4165 | ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM; |
2b84af94 | 4166 | if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER) |
43779f8d | 4167 | ocp_data |= LPM_TIMER_500MS; |
34203e25 | 4168 | else |
4169 | ocp_data |= LPM_TIMER_500US; | |
43779f8d | 4170 | ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data); |
4171 | ||
4172 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2); | |
4173 | ocp_data &= ~SEN_VAL_MASK; | |
4174 | ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE; | |
4175 | ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data); | |
4176 | ||
65bab84c | 4177 | ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001); |
4178 | ||
b9702723 | 4179 | r8153_power_cut_en(tp, false); |
4180 | r8153_u1u2en(tp, true); | |
134f98bc | 4181 | r8153_mac_clk_spd(tp, false); |
ee4761c1 | 4182 | usb_enable_lpm(tp->udev); |
43779f8d | 4183 | |
e31f6367 | 4184 | /* rx aggregation */ |
4185 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); | |
4186 | ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); | |
0b165514 KHF |
4187 | if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags)) |
4188 | ocp_data |= RX_AGG_DISABLE; | |
4189 | ||
e31f6367 | 4190 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); |
43779f8d | 4191 | |
4f1d4d54 | 4192 | rtl_tally_reset(tp); |
49d10347 | 4193 | |
4194 | switch (tp->udev->speed) { | |
4195 | case USB_SPEED_SUPER: | |
4196 | case USB_SPEED_SUPER_PLUS: | |
4197 | tp->coalesce = COALESCE_SUPER; | |
4198 | break; | |
4199 | case USB_SPEED_HIGH: | |
4200 | tp->coalesce = COALESCE_HIGH; | |
4201 | break; | |
4202 | default: | |
4203 | tp->coalesce = COALESCE_SLOW; | |
4204 | break; | |
4205 | } | |
43779f8d | 4206 | } |
4207 | ||
65b82d69 | 4208 | static void r8153b_init(struct r8152 *tp) |
4209 | { | |
4210 | u32 ocp_data; | |
4211 | u16 data; | |
4212 | int i; | |
4213 | ||
4214 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
4215 | return; | |
4216 | ||
4217 | r8153b_u1u2en(tp, false); | |
4218 | ||
4219 | for (i = 0; i < 500; i++) { | |
4220 | if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & | |
4221 | AUTOLOAD_DONE) | |
4222 | break; | |
44350abc | 4223 | |
65b82d69 | 4224 | msleep(20); |
44350abc YSY |
4225 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
4226 | break; | |
65b82d69 | 4227 | } |
4228 | ||
4229 | data = r8153_phy_status(tp, 0); | |
4230 | ||
4231 | data = r8152_mdio_read(tp, MII_BMCR); | |
4232 | if (data & BMCR_PDOWN) { | |
4233 | data &= ~BMCR_PDOWN; | |
4234 | r8152_mdio_write(tp, MII_BMCR, data); | |
4235 | } | |
4236 | ||
4237 | data = r8153_phy_status(tp, PHY_STAT_LAN_ON); | |
4238 | ||
4239 | r8153_u2p3en(tp, false); | |
4240 | ||
4241 | /* MSC timer = 0xfff * 8ms = 32760 ms */ | |
4242 | ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff); | |
4243 | ||
4244 | /* U1/U2/L1 idle timer. 500 us */ | |
4245 | ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500); | |
4246 | ||
4247 | r8153b_power_cut_en(tp, false); | |
4248 | r8153b_ups_en(tp, false); | |
4249 | r8153b_queue_wake(tp, false); | |
4250 | rtl_runtime_suspend_enable(tp, false); | |
4251 | r8153b_u1u2en(tp, true); | |
4252 | usb_enable_lpm(tp->udev); | |
4253 | ||
4254 | /* MAC clock speed down */ | |
4255 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2); | |
4256 | ocp_data |= MAC_CLK_SPDWN_EN; | |
4257 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data); | |
4258 | ||
4259 | set_bit(GREEN_ETHERNET, &tp->flags); | |
4260 | ||
4261 | /* rx aggregation */ | |
4262 | ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); | |
4263 | ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); | |
4264 | ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); | |
4265 | ||
4266 | rtl_tally_reset(tp); | |
4267 | ||
4268 | tp->coalesce = 15000; /* 15 us */ | |
4269 | } | |
4270 | ||
e501139a | 4271 | static int rtl8152_pre_reset(struct usb_interface *intf) |
4272 | { | |
4273 | struct r8152 *tp = usb_get_intfdata(intf); | |
4274 | struct net_device *netdev; | |
4275 | ||
4276 | if (!tp) | |
4277 | return 0; | |
4278 | ||
4279 | netdev = tp->netdev; | |
4280 | if (!netif_running(netdev)) | |
4281 | return 0; | |
4282 | ||
de9bf29d | 4283 | netif_stop_queue(netdev); |
e501139a | 4284 | napi_disable(&tp->napi); |
4285 | clear_bit(WORK_ENABLE, &tp->flags); | |
4286 | usb_kill_urb(tp->intr_urb); | |
4287 | cancel_delayed_work_sync(&tp->schedule); | |
4288 | if (netif_carrier_ok(netdev)) { | |
e501139a | 4289 | mutex_lock(&tp->control); |
4290 | tp->rtl_ops.disable(tp); | |
4291 | mutex_unlock(&tp->control); | |
4292 | } | |
4293 | ||
4294 | return 0; | |
4295 | } | |
4296 | ||
4297 | static int rtl8152_post_reset(struct usb_interface *intf) | |
4298 | { | |
4299 | struct r8152 *tp = usb_get_intfdata(intf); | |
4300 | struct net_device *netdev; | |
102e0592 | 4301 | struct sockaddr sa; |
e501139a | 4302 | |
4303 | if (!tp) | |
4304 | return 0; | |
4305 | ||
102e0592 ML |
4306 | /* reset the MAC adddress in case of policy change */ |
4307 | if (determine_ethernet_addr(tp, &sa) >= 0) { | |
4308 | rtnl_lock(); | |
4309 | dev_set_mac_address (tp->netdev, &sa); | |
4310 | rtnl_unlock(); | |
4311 | } | |
4312 | ||
e501139a | 4313 | netdev = tp->netdev; |
4314 | if (!netif_running(netdev)) | |
4315 | return 0; | |
4316 | ||
4317 | set_bit(WORK_ENABLE, &tp->flags); | |
4318 | if (netif_carrier_ok(netdev)) { | |
4319 | mutex_lock(&tp->control); | |
4320 | tp->rtl_ops.enable(tp); | |
2c561b2b | 4321 | rtl_start_rx(tp); |
e501139a | 4322 | rtl8152_set_rx_mode(netdev); |
4323 | mutex_unlock(&tp->control); | |
e501139a | 4324 | } |
4325 | ||
4326 | napi_enable(&tp->napi); | |
de9bf29d | 4327 | netif_wake_queue(netdev); |
2c561b2b | 4328 | usb_submit_urb(tp->intr_urb, GFP_KERNEL); |
e501139a | 4329 | |
7489bdad | 4330 | if (!list_empty(&tp->rx_done)) |
4331 | napi_schedule(&tp->napi); | |
e501139a | 4332 | |
4333 | return 0; | |
43779f8d | 4334 | } |
4335 | ||
2dd49e0f | 4336 | static bool delay_autosuspend(struct r8152 *tp) |
4337 | { | |
4338 | bool sw_linking = !!netif_carrier_ok(tp->netdev); | |
4339 | bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS); | |
4340 | ||
4341 | /* This means a linking change occurs and the driver doesn't detect it, | |
4342 | * yet. If the driver has disabled tx/rx and hw is linking on, the | |
4343 | * device wouldn't wake up by receiving any packet. | |
4344 | */ | |
4345 | if (work_busy(&tp->schedule.work) || sw_linking != hw_linking) | |
4346 | return true; | |
4347 | ||
4348 | /* If the linking down is occurred by nway, the device may miss the | |
4349 | * linking change event. And it wouldn't wake when linking on. | |
4350 | */ | |
4351 | if (!sw_linking && tp->rtl_ops.in_nway(tp)) | |
4352 | return true; | |
6a0b76c0 | 4353 | else if (!skb_queue_empty(&tp->tx_queue)) |
4354 | return true; | |
2dd49e0f | 4355 | else |
4356 | return false; | |
4357 | } | |
4358 | ||
21cbd0ec | 4359 | static int rtl8152_runtime_resume(struct r8152 *tp) |
4360 | { | |
4361 | struct net_device *netdev = tp->netdev; | |
4362 | ||
4363 | if (netif_running(netdev) && netdev->flags & IFF_UP) { | |
4364 | struct napi_struct *napi = &tp->napi; | |
4365 | ||
4366 | tp->rtl_ops.autosuspend_en(tp, false); | |
4367 | napi_disable(napi); | |
4368 | set_bit(WORK_ENABLE, &tp->flags); | |
4369 | ||
4370 | if (netif_carrier_ok(netdev)) { | |
4371 | if (rtl8152_get_speed(tp) & LINK_STATUS) { | |
4372 | rtl_start_rx(tp); | |
4373 | } else { | |
4374 | netif_carrier_off(netdev); | |
4375 | tp->rtl_ops.disable(tp); | |
4376 | netif_info(tp, link, netdev, "linking down\n"); | |
4377 | } | |
4378 | } | |
4379 | ||
4380 | napi_enable(napi); | |
4381 | clear_bit(SELECTIVE_SUSPEND, &tp->flags); | |
4382 | smp_mb__after_atomic(); | |
4383 | ||
4384 | if (!list_empty(&tp->rx_done)) | |
4385 | napi_schedule(&tp->napi); | |
4386 | ||
4387 | usb_submit_urb(tp->intr_urb, GFP_NOIO); | |
4388 | } else { | |
4389 | if (netdev->flags & IFF_UP) | |
4390 | tp->rtl_ops.autosuspend_en(tp, false); | |
4391 | ||
4392 | clear_bit(SELECTIVE_SUSPEND, &tp->flags); | |
4393 | } | |
4394 | ||
4395 | return 0; | |
4396 | } | |
4397 | ||
4398 | static int rtl8152_system_resume(struct r8152 *tp) | |
4399 | { | |
4400 | struct net_device *netdev = tp->netdev; | |
4401 | ||
4402 | netif_device_attach(netdev); | |
4403 | ||
4404 | if (netif_running(netdev) && netdev->flags & IFF_UP) { | |
4405 | tp->rtl_ops.up(tp); | |
4406 | netif_carrier_off(netdev); | |
4407 | set_bit(WORK_ENABLE, &tp->flags); | |
4408 | usb_submit_urb(tp->intr_urb, GFP_NOIO); | |
4409 | } | |
4410 | ||
4411 | return 0; | |
4412 | } | |
4413 | ||
a9c54ad2 | 4414 | static int rtl8152_runtime_suspend(struct r8152 *tp) |
ac718b69 | 4415 | { |
6cc69f2a | 4416 | struct net_device *netdev = tp->netdev; |
4417 | int ret = 0; | |
ac718b69 | 4418 | |
26afec39 | 4419 | set_bit(SELECTIVE_SUSPEND, &tp->flags); |
4420 | smp_mb__after_atomic(); | |
4421 | ||
8fb28061 | 4422 | if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) { |
75dc692e | 4423 | u32 rcr = 0; |
4424 | ||
75dc692e | 4425 | if (netif_carrier_ok(netdev)) { |
4426 | u32 ocp_data; | |
4427 | ||
4428 | rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); | |
4429 | ocp_data = rcr & ~RCR_ACPT_ALL; | |
4430 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); | |
4431 | rxdy_gated_en(tp, true); | |
4432 | ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, | |
4433 | PLA_OOB_CTRL); | |
4434 | if (!(ocp_data & RXFIFO_EMPTY)) { | |
4435 | rxdy_gated_en(tp, false); | |
4436 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr); | |
26afec39 | 4437 | clear_bit(SELECTIVE_SUSPEND, &tp->flags); |
4438 | smp_mb__after_atomic(); | |
75dc692e | 4439 | ret = -EBUSY; |
4440 | goto out1; | |
4441 | } | |
4442 | } | |
4443 | ||
8fb28061 | 4444 | clear_bit(WORK_ENABLE, &tp->flags); |
4445 | usb_kill_urb(tp->intr_urb); | |
75dc692e | 4446 | |
8fb28061 | 4447 | tp->rtl_ops.autosuspend_en(tp, true); |
75dc692e | 4448 | |
4449 | if (netif_carrier_ok(netdev)) { | |
ce594e98 | 4450 | struct napi_struct *napi = &tp->napi; |
4451 | ||
4452 | napi_disable(napi); | |
75dc692e | 4453 | rtl_stop_rx(tp); |
4454 | rxdy_gated_en(tp, false); | |
4455 | ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr); | |
ce594e98 | 4456 | napi_enable(napi); |
75dc692e | 4457 | } |
bd882982 | 4458 | |
4459 | if (delay_autosuspend(tp)) { | |
4460 | rtl8152_runtime_resume(tp); | |
4461 | ret = -EBUSY; | |
4462 | } | |
6cc69f2a | 4463 | } |
ac718b69 | 4464 | |
8fb28061 | 4465 | out1: |
4466 | return ret; | |
4467 | } | |
4468 | ||
4469 | static int rtl8152_system_suspend(struct r8152 *tp) | |
4470 | { | |
4471 | struct net_device *netdev = tp->netdev; | |
4472 | int ret = 0; | |
4473 | ||
4474 | netif_device_detach(netdev); | |
4475 | ||
e3bd1a81 | 4476 | if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) { |
ce594e98 | 4477 | struct napi_struct *napi = &tp->napi; |
4478 | ||
ac718b69 | 4479 | clear_bit(WORK_ENABLE, &tp->flags); |
40a82917 | 4480 | usb_kill_urb(tp->intr_urb); |
ce594e98 | 4481 | napi_disable(napi); |
8fb28061 | 4482 | cancel_delayed_work_sync(&tp->schedule); |
4483 | tp->rtl_ops.down(tp); | |
ce594e98 | 4484 | napi_enable(napi); |
ac718b69 | 4485 | } |
8fb28061 | 4486 | |
4487 | return ret; | |
4488 | } | |
4489 | ||
4490 | static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message) | |
4491 | { | |
4492 | struct r8152 *tp = usb_get_intfdata(intf); | |
4493 | int ret; | |
4494 | ||
4495 | mutex_lock(&tp->control); | |
4496 | ||
4497 | if (PMSG_IS_AUTO(message)) | |
a9c54ad2 | 4498 | ret = rtl8152_runtime_suspend(tp); |
8fb28061 | 4499 | else |
4500 | ret = rtl8152_system_suspend(tp); | |
4501 | ||
b5403273 | 4502 | mutex_unlock(&tp->control); |
4503 | ||
6cc69f2a | 4504 | return ret; |
ac718b69 | 4505 | } |
4506 | ||
4507 | static int rtl8152_resume(struct usb_interface *intf) | |
4508 | { | |
4509 | struct r8152 *tp = usb_get_intfdata(intf); | |
21cbd0ec | 4510 | int ret; |
ac718b69 | 4511 | |
b5403273 | 4512 | mutex_lock(&tp->control); |
4513 | ||
21cbd0ec | 4514 | if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) |
4515 | ret = rtl8152_runtime_resume(tp); | |
4516 | else | |
4517 | ret = rtl8152_system_resume(tp); | |
ac718b69 | 4518 | |
b5403273 | 4519 | mutex_unlock(&tp->control); |
4520 | ||
21cbd0ec | 4521 | return ret; |
ac718b69 | 4522 | } |
4523 | ||
7ec2541a | 4524 | static int rtl8152_reset_resume(struct usb_interface *intf) |
4525 | { | |
4526 | struct r8152 *tp = usb_get_intfdata(intf); | |
4527 | ||
4528 | clear_bit(SELECTIVE_SUSPEND, &tp->flags); | |
befb2de1 | 4529 | tp->rtl_ops.init(tp); |
4530 | queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0); | |
492b3709 | 4531 | set_ethernet_addr(tp); |
7ec2541a | 4532 | return rtl8152_resume(intf); |
4533 | } | |
4534 | ||
21ff2e89 | 4535 | static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
4536 | { | |
4537 | struct r8152 *tp = netdev_priv(dev); | |
4538 | ||
9a4be1bd | 4539 | if (usb_autopm_get_interface(tp->intf) < 0) |
4540 | return; | |
4541 | ||
7daed8dc | 4542 | if (!rtl_can_wakeup(tp)) { |
4543 | wol->supported = 0; | |
4544 | wol->wolopts = 0; | |
4545 | } else { | |
4546 | mutex_lock(&tp->control); | |
4547 | wol->supported = WAKE_ANY; | |
4548 | wol->wolopts = __rtl_get_wol(tp); | |
4549 | mutex_unlock(&tp->control); | |
4550 | } | |
b5403273 | 4551 | |
9a4be1bd | 4552 | usb_autopm_put_interface(tp->intf); |
21ff2e89 | 4553 | } |
4554 | ||
4555 | static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
4556 | { | |
4557 | struct r8152 *tp = netdev_priv(dev); | |
9a4be1bd | 4558 | int ret; |
4559 | ||
7daed8dc | 4560 | if (!rtl_can_wakeup(tp)) |
4561 | return -EOPNOTSUPP; | |
4562 | ||
3b7a5a9a FF |
4563 | if (wol->wolopts & ~WAKE_ANY) |
4564 | return -EINVAL; | |
4565 | ||
9a4be1bd | 4566 | ret = usb_autopm_get_interface(tp->intf); |
4567 | if (ret < 0) | |
4568 | goto out_set_wol; | |
21ff2e89 | 4569 | |
b5403273 | 4570 | mutex_lock(&tp->control); |
4571 | ||
21ff2e89 | 4572 | __rtl_set_wol(tp, wol->wolopts); |
4573 | tp->saved_wolopts = wol->wolopts & WAKE_ANY; | |
4574 | ||
b5403273 | 4575 | mutex_unlock(&tp->control); |
4576 | ||
9a4be1bd | 4577 | usb_autopm_put_interface(tp->intf); |
4578 | ||
4579 | out_set_wol: | |
4580 | return ret; | |
21ff2e89 | 4581 | } |
4582 | ||
a5ec27c1 | 4583 | static u32 rtl8152_get_msglevel(struct net_device *dev) |
4584 | { | |
4585 | struct r8152 *tp = netdev_priv(dev); | |
4586 | ||
4587 | return tp->msg_enable; | |
4588 | } | |
4589 | ||
4590 | static void rtl8152_set_msglevel(struct net_device *dev, u32 value) | |
4591 | { | |
4592 | struct r8152 *tp = netdev_priv(dev); | |
4593 | ||
4594 | tp->msg_enable = value; | |
4595 | } | |
4596 | ||
ac718b69 | 4597 | static void rtl8152_get_drvinfo(struct net_device *netdev, |
4598 | struct ethtool_drvinfo *info) | |
4599 | { | |
4600 | struct r8152 *tp = netdev_priv(netdev); | |
4601 | ||
b0b46c77 | 4602 | strlcpy(info->driver, MODULENAME, sizeof(info->driver)); |
4603 | strlcpy(info->version, DRIVER_VERSION, sizeof(info->version)); | |
ac718b69 | 4604 | usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info)); |
4605 | } | |
4606 | ||
4607 | static | |
06144dcf PR |
4608 | int rtl8152_get_link_ksettings(struct net_device *netdev, |
4609 | struct ethtool_link_ksettings *cmd) | |
ac718b69 | 4610 | { |
4611 | struct r8152 *tp = netdev_priv(netdev); | |
8d4a4d72 | 4612 | int ret; |
ac718b69 | 4613 | |
4614 | if (!tp->mii.mdio_read) | |
4615 | return -EOPNOTSUPP; | |
4616 | ||
8d4a4d72 | 4617 | ret = usb_autopm_get_interface(tp->intf); |
4618 | if (ret < 0) | |
4619 | goto out; | |
4620 | ||
b5403273 | 4621 | mutex_lock(&tp->control); |
4622 | ||
82c01a84 | 4623 | mii_ethtool_get_link_ksettings(&tp->mii, cmd); |
8d4a4d72 | 4624 | |
b5403273 | 4625 | mutex_unlock(&tp->control); |
4626 | ||
8d4a4d72 | 4627 | usb_autopm_put_interface(tp->intf); |
4628 | ||
4629 | out: | |
4630 | return ret; | |
ac718b69 | 4631 | } |
4632 | ||
06144dcf PR |
4633 | static int rtl8152_set_link_ksettings(struct net_device *dev, |
4634 | const struct ethtool_link_ksettings *cmd) | |
ac718b69 | 4635 | { |
4636 | struct r8152 *tp = netdev_priv(dev); | |
9a4be1bd | 4637 | int ret; |
4638 | ||
4639 | ret = usb_autopm_get_interface(tp->intf); | |
4640 | if (ret < 0) | |
4641 | goto out; | |
ac718b69 | 4642 | |
b5403273 | 4643 | mutex_lock(&tp->control); |
4644 | ||
06144dcf PR |
4645 | ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed, |
4646 | cmd->base.duplex); | |
aa7e26b6 | 4647 | if (!ret) { |
06144dcf PR |
4648 | tp->autoneg = cmd->base.autoneg; |
4649 | tp->speed = cmd->base.speed; | |
4650 | tp->duplex = cmd->base.duplex; | |
aa7e26b6 | 4651 | } |
9a4be1bd | 4652 | |
b5403273 | 4653 | mutex_unlock(&tp->control); |
4654 | ||
9a4be1bd | 4655 | usb_autopm_put_interface(tp->intf); |
4656 | ||
4657 | out: | |
4658 | return ret; | |
ac718b69 | 4659 | } |
4660 | ||
4f1d4d54 | 4661 | static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = { |
4662 | "tx_packets", | |
4663 | "rx_packets", | |
4664 | "tx_errors", | |
4665 | "rx_errors", | |
4666 | "rx_missed", | |
4667 | "align_errors", | |
4668 | "tx_single_collisions", | |
4669 | "tx_multi_collisions", | |
4670 | "rx_unicast", | |
4671 | "rx_broadcast", | |
4672 | "rx_multicast", | |
4673 | "tx_aborted", | |
4674 | "tx_underrun", | |
4675 | }; | |
4676 | ||
4677 | static int rtl8152_get_sset_count(struct net_device *dev, int sset) | |
4678 | { | |
4679 | switch (sset) { | |
4680 | case ETH_SS_STATS: | |
4681 | return ARRAY_SIZE(rtl8152_gstrings); | |
4682 | default: | |
4683 | return -EOPNOTSUPP; | |
4684 | } | |
4685 | } | |
4686 | ||
4687 | static void rtl8152_get_ethtool_stats(struct net_device *dev, | |
4688 | struct ethtool_stats *stats, u64 *data) | |
4689 | { | |
4690 | struct r8152 *tp = netdev_priv(dev); | |
4691 | struct tally_counter tally; | |
4692 | ||
0b030244 | 4693 | if (usb_autopm_get_interface(tp->intf) < 0) |
4694 | return; | |
4695 | ||
4f1d4d54 | 4696 | generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA); |
4697 | ||
0b030244 | 4698 | usb_autopm_put_interface(tp->intf); |
4699 | ||
4f1d4d54 | 4700 | data[0] = le64_to_cpu(tally.tx_packets); |
4701 | data[1] = le64_to_cpu(tally.rx_packets); | |
4702 | data[2] = le64_to_cpu(tally.tx_errors); | |
4703 | data[3] = le32_to_cpu(tally.rx_errors); | |
4704 | data[4] = le16_to_cpu(tally.rx_missed); | |
4705 | data[5] = le16_to_cpu(tally.align_errors); | |
4706 | data[6] = le32_to_cpu(tally.tx_one_collision); | |
4707 | data[7] = le32_to_cpu(tally.tx_multi_collision); | |
4708 | data[8] = le64_to_cpu(tally.rx_unicast); | |
4709 | data[9] = le64_to_cpu(tally.rx_broadcast); | |
4710 | data[10] = le32_to_cpu(tally.rx_multicast); | |
4711 | data[11] = le16_to_cpu(tally.tx_aborted); | |
f37119c5 | 4712 | data[12] = le16_to_cpu(tally.tx_underrun); |
4f1d4d54 | 4713 | } |
4714 | ||
4715 | static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data) | |
4716 | { | |
4717 | switch (stringset) { | |
4718 | case ETH_SS_STATS: | |
4719 | memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings)); | |
4720 | break; | |
4721 | } | |
4722 | } | |
4723 | ||
df35d283 | 4724 | static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee) |
4725 | { | |
4726 | u32 ocp_data, lp, adv, supported = 0; | |
4727 | u16 val; | |
4728 | ||
4729 | val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); | |
4730 | supported = mmd_eee_cap_to_ethtool_sup_t(val); | |
4731 | ||
4732 | val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV); | |
4733 | adv = mmd_eee_adv_to_ethtool_adv_t(val); | |
4734 | ||
4735 | val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE); | |
4736 | lp = mmd_eee_adv_to_ethtool_adv_t(val); | |
4737 | ||
4738 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); | |
4739 | ocp_data &= EEE_RX_EN | EEE_TX_EN; | |
4740 | ||
4741 | eee->eee_enabled = !!ocp_data; | |
4742 | eee->eee_active = !!(supported & adv & lp); | |
4743 | eee->supported = supported; | |
4744 | eee->advertised = adv; | |
4745 | eee->lp_advertised = lp; | |
4746 | ||
4747 | return 0; | |
4748 | } | |
4749 | ||
4750 | static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee) | |
4751 | { | |
4752 | u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); | |
4753 | ||
4754 | r8152_eee_en(tp, eee->eee_enabled); | |
4755 | ||
4756 | if (!eee->eee_enabled) | |
4757 | val = 0; | |
4758 | ||
4759 | r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val); | |
4760 | ||
4761 | return 0; | |
4762 | } | |
4763 | ||
4764 | static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee) | |
4765 | { | |
4766 | u32 ocp_data, lp, adv, supported = 0; | |
4767 | u16 val; | |
4768 | ||
4769 | val = ocp_reg_read(tp, OCP_EEE_ABLE); | |
4770 | supported = mmd_eee_cap_to_ethtool_sup_t(val); | |
4771 | ||
4772 | val = ocp_reg_read(tp, OCP_EEE_ADV); | |
4773 | adv = mmd_eee_adv_to_ethtool_adv_t(val); | |
4774 | ||
4775 | val = ocp_reg_read(tp, OCP_EEE_LPABLE); | |
4776 | lp = mmd_eee_adv_to_ethtool_adv_t(val); | |
4777 | ||
4778 | ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); | |
4779 | ocp_data &= EEE_RX_EN | EEE_TX_EN; | |
4780 | ||
4781 | eee->eee_enabled = !!ocp_data; | |
4782 | eee->eee_active = !!(supported & adv & lp); | |
4783 | eee->supported = supported; | |
4784 | eee->advertised = adv; | |
4785 | eee->lp_advertised = lp; | |
4786 | ||
4787 | return 0; | |
4788 | } | |
4789 | ||
4790 | static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee) | |
4791 | { | |
4792 | u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); | |
4793 | ||
4794 | r8153_eee_en(tp, eee->eee_enabled); | |
4795 | ||
4796 | if (!eee->eee_enabled) | |
4797 | val = 0; | |
4798 | ||
4799 | ocp_reg_write(tp, OCP_EEE_ADV, val); | |
4800 | ||
4801 | return 0; | |
4802 | } | |
4803 | ||
65b82d69 | 4804 | static int r8153b_set_eee(struct r8152 *tp, struct ethtool_eee *eee) |
4805 | { | |
4806 | u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); | |
4807 | ||
4808 | r8153b_eee_en(tp, eee->eee_enabled); | |
4809 | ||
4810 | if (!eee->eee_enabled) | |
4811 | val = 0; | |
4812 | ||
4813 | ocp_reg_write(tp, OCP_EEE_ADV, val); | |
4814 | ||
4815 | return 0; | |
4816 | } | |
4817 | ||
df35d283 | 4818 | static int |
4819 | rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata) | |
4820 | { | |
4821 | struct r8152 *tp = netdev_priv(net); | |
4822 | int ret; | |
4823 | ||
4824 | ret = usb_autopm_get_interface(tp->intf); | |
4825 | if (ret < 0) | |
4826 | goto out; | |
4827 | ||
b5403273 | 4828 | mutex_lock(&tp->control); |
4829 | ||
df35d283 | 4830 | ret = tp->rtl_ops.eee_get(tp, edata); |
4831 | ||
b5403273 | 4832 | mutex_unlock(&tp->control); |
4833 | ||
df35d283 | 4834 | usb_autopm_put_interface(tp->intf); |
4835 | ||
4836 | out: | |
4837 | return ret; | |
4838 | } | |
4839 | ||
4840 | static int | |
4841 | rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata) | |
4842 | { | |
4843 | struct r8152 *tp = netdev_priv(net); | |
4844 | int ret; | |
4845 | ||
4846 | ret = usb_autopm_get_interface(tp->intf); | |
4847 | if (ret < 0) | |
4848 | goto out; | |
4849 | ||
b5403273 | 4850 | mutex_lock(&tp->control); |
4851 | ||
df35d283 | 4852 | ret = tp->rtl_ops.eee_set(tp, edata); |
9d31a7b9 | 4853 | if (!ret) |
4854 | ret = mii_nway_restart(&tp->mii); | |
df35d283 | 4855 | |
b5403273 | 4856 | mutex_unlock(&tp->control); |
4857 | ||
df35d283 | 4858 | usb_autopm_put_interface(tp->intf); |
4859 | ||
4860 | out: | |
4861 | return ret; | |
4862 | } | |
4863 | ||
8884f507 | 4864 | static int rtl8152_nway_reset(struct net_device *dev) |
4865 | { | |
4866 | struct r8152 *tp = netdev_priv(dev); | |
4867 | int ret; | |
4868 | ||
4869 | ret = usb_autopm_get_interface(tp->intf); | |
4870 | if (ret < 0) | |
4871 | goto out; | |
4872 | ||
4873 | mutex_lock(&tp->control); | |
4874 | ||
4875 | ret = mii_nway_restart(&tp->mii); | |
4876 | ||
4877 | mutex_unlock(&tp->control); | |
4878 | ||
4879 | usb_autopm_put_interface(tp->intf); | |
4880 | ||
4881 | out: | |
4882 | return ret; | |
4883 | } | |
4884 | ||
efb3dd88 | 4885 | static int rtl8152_get_coalesce(struct net_device *netdev, |
4886 | struct ethtool_coalesce *coalesce) | |
4887 | { | |
4888 | struct r8152 *tp = netdev_priv(netdev); | |
4889 | ||
4890 | switch (tp->version) { | |
4891 | case RTL_VER_01: | |
4892 | case RTL_VER_02: | |
c27b32c2 | 4893 | case RTL_VER_07: |
efb3dd88 | 4894 | return -EOPNOTSUPP; |
4895 | default: | |
4896 | break; | |
4897 | } | |
4898 | ||
4899 | coalesce->rx_coalesce_usecs = tp->coalesce; | |
4900 | ||
4901 | return 0; | |
4902 | } | |
4903 | ||
4904 | static int rtl8152_set_coalesce(struct net_device *netdev, | |
4905 | struct ethtool_coalesce *coalesce) | |
4906 | { | |
4907 | struct r8152 *tp = netdev_priv(netdev); | |
4908 | int ret; | |
4909 | ||
4910 | switch (tp->version) { | |
4911 | case RTL_VER_01: | |
4912 | case RTL_VER_02: | |
c27b32c2 | 4913 | case RTL_VER_07: |
efb3dd88 | 4914 | return -EOPNOTSUPP; |
4915 | default: | |
4916 | break; | |
4917 | } | |
4918 | ||
4919 | if (coalesce->rx_coalesce_usecs > COALESCE_SLOW) | |
4920 | return -EINVAL; | |
4921 | ||
4922 | ret = usb_autopm_get_interface(tp->intf); | |
4923 | if (ret < 0) | |
4924 | return ret; | |
4925 | ||
4926 | mutex_lock(&tp->control); | |
4927 | ||
4928 | if (tp->coalesce != coalesce->rx_coalesce_usecs) { | |
4929 | tp->coalesce = coalesce->rx_coalesce_usecs; | |
4930 | ||
4931 | if (netif_running(tp->netdev) && netif_carrier_ok(netdev)) | |
4932 | r8153_set_rx_early_timeout(tp); | |
4933 | } | |
4934 | ||
4935 | mutex_unlock(&tp->control); | |
4936 | ||
4937 | usb_autopm_put_interface(tp->intf); | |
4938 | ||
4939 | return ret; | |
4940 | } | |
4941 | ||
407a471d | 4942 | static const struct ethtool_ops ops = { |
ac718b69 | 4943 | .get_drvinfo = rtl8152_get_drvinfo, |
ac718b69 | 4944 | .get_link = ethtool_op_get_link, |
8884f507 | 4945 | .nway_reset = rtl8152_nway_reset, |
a5ec27c1 | 4946 | .get_msglevel = rtl8152_get_msglevel, |
4947 | .set_msglevel = rtl8152_set_msglevel, | |
21ff2e89 | 4948 | .get_wol = rtl8152_get_wol, |
4949 | .set_wol = rtl8152_set_wol, | |
4f1d4d54 | 4950 | .get_strings = rtl8152_get_strings, |
4951 | .get_sset_count = rtl8152_get_sset_count, | |
4952 | .get_ethtool_stats = rtl8152_get_ethtool_stats, | |
efb3dd88 | 4953 | .get_coalesce = rtl8152_get_coalesce, |
4954 | .set_coalesce = rtl8152_set_coalesce, | |
df35d283 | 4955 | .get_eee = rtl_ethtool_get_eee, |
4956 | .set_eee = rtl_ethtool_set_eee, | |
06144dcf PR |
4957 | .get_link_ksettings = rtl8152_get_link_ksettings, |
4958 | .set_link_ksettings = rtl8152_set_link_ksettings, | |
ac718b69 | 4959 | }; |
4960 | ||
4961 | static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) | |
4962 | { | |
4963 | struct r8152 *tp = netdev_priv(netdev); | |
4964 | struct mii_ioctl_data *data = if_mii(rq); | |
9a4be1bd | 4965 | int res; |
4966 | ||
6871438c | 4967 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
4968 | return -ENODEV; | |
4969 | ||
9a4be1bd | 4970 | res = usb_autopm_get_interface(tp->intf); |
4971 | if (res < 0) | |
4972 | goto out; | |
ac718b69 | 4973 | |
4974 | switch (cmd) { | |
4975 | case SIOCGMIIPHY: | |
4976 | data->phy_id = R8152_PHY_ID; /* Internal PHY */ | |
4977 | break; | |
4978 | ||
4979 | case SIOCGMIIREG: | |
b5403273 | 4980 | mutex_lock(&tp->control); |
ac718b69 | 4981 | data->val_out = r8152_mdio_read(tp, data->reg_num); |
b5403273 | 4982 | mutex_unlock(&tp->control); |
ac718b69 | 4983 | break; |
4984 | ||
4985 | case SIOCSMIIREG: | |
4986 | if (!capable(CAP_NET_ADMIN)) { | |
4987 | res = -EPERM; | |
4988 | break; | |
4989 | } | |
b5403273 | 4990 | mutex_lock(&tp->control); |
ac718b69 | 4991 | r8152_mdio_write(tp, data->reg_num, data->val_in); |
b5403273 | 4992 | mutex_unlock(&tp->control); |
ac718b69 | 4993 | break; |
4994 | ||
4995 | default: | |
4996 | res = -EOPNOTSUPP; | |
4997 | } | |
4998 | ||
9a4be1bd | 4999 | usb_autopm_put_interface(tp->intf); |
5000 | ||
5001 | out: | |
ac718b69 | 5002 | return res; |
5003 | } | |
5004 | ||
69b4b7a4 | 5005 | static int rtl8152_change_mtu(struct net_device *dev, int new_mtu) |
5006 | { | |
5007 | struct r8152 *tp = netdev_priv(dev); | |
396e2e23 | 5008 | int ret; |
69b4b7a4 | 5009 | |
5010 | switch (tp->version) { | |
5011 | case RTL_VER_01: | |
5012 | case RTL_VER_02: | |
c27b32c2 | 5013 | case RTL_VER_07: |
a52ad514 JW |
5014 | dev->mtu = new_mtu; |
5015 | return 0; | |
69b4b7a4 | 5016 | default: |
5017 | break; | |
5018 | } | |
5019 | ||
396e2e23 | 5020 | ret = usb_autopm_get_interface(tp->intf); |
5021 | if (ret < 0) | |
5022 | return ret; | |
5023 | ||
5024 | mutex_lock(&tp->control); | |
5025 | ||
69b4b7a4 | 5026 | dev->mtu = new_mtu; |
5027 | ||
210c4f70 | 5028 | if (netif_running(dev)) { |
b65c0c9b | 5029 | u32 rms = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN; |
210c4f70 | 5030 | |
5031 | ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rms); | |
5032 | ||
5033 | if (netif_carrier_ok(dev)) | |
5034 | r8153_set_rx_early_size(tp); | |
5035 | } | |
396e2e23 | 5036 | |
5037 | mutex_unlock(&tp->control); | |
5038 | ||
5039 | usb_autopm_put_interface(tp->intf); | |
5040 | ||
5041 | return ret; | |
69b4b7a4 | 5042 | } |
5043 | ||
ac718b69 | 5044 | static const struct net_device_ops rtl8152_netdev_ops = { |
5045 | .ndo_open = rtl8152_open, | |
5046 | .ndo_stop = rtl8152_close, | |
5047 | .ndo_do_ioctl = rtl8152_ioctl, | |
5048 | .ndo_start_xmit = rtl8152_start_xmit, | |
5049 | .ndo_tx_timeout = rtl8152_tx_timeout, | |
c5554298 | 5050 | .ndo_set_features = rtl8152_set_features, |
ac718b69 | 5051 | .ndo_set_rx_mode = rtl8152_set_rx_mode, |
5052 | .ndo_set_mac_address = rtl8152_set_mac_address, | |
69b4b7a4 | 5053 | .ndo_change_mtu = rtl8152_change_mtu, |
ac718b69 | 5054 | .ndo_validate_addr = eth_validate_addr, |
a5e31255 | 5055 | .ndo_features_check = rtl8152_features_check, |
ac718b69 | 5056 | }; |
5057 | ||
e3fe0b1a | 5058 | static void rtl8152_unload(struct r8152 *tp) |
5059 | { | |
6871438c | 5060 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
5061 | return; | |
5062 | ||
00a5e360 | 5063 | if (tp->version != RTL_VER_01) |
5064 | r8152_power_cut_en(tp, true); | |
e3fe0b1a | 5065 | } |
5066 | ||
43779f8d | 5067 | static void rtl8153_unload(struct r8152 *tp) |
5068 | { | |
6871438c | 5069 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) |
5070 | return; | |
5071 | ||
49be1723 | 5072 | r8153_power_cut_en(tp, false); |
43779f8d | 5073 | } |
5074 | ||
65b82d69 | 5075 | static void rtl8153b_unload(struct r8152 *tp) |
5076 | { | |
5077 | if (test_bit(RTL8152_UNPLUG, &tp->flags)) | |
5078 | return; | |
5079 | ||
5080 | r8153b_power_cut_en(tp, false); | |
5081 | } | |
5082 | ||
55b65475 | 5083 | static int rtl_ops_init(struct r8152 *tp) |
c81229c9 | 5084 | { |
5085 | struct rtl_ops *ops = &tp->rtl_ops; | |
55b65475 | 5086 | int ret = 0; |
5087 | ||
5088 | switch (tp->version) { | |
5089 | case RTL_VER_01: | |
5090 | case RTL_VER_02: | |
c27b32c2 | 5091 | case RTL_VER_07: |
55b65475 | 5092 | ops->init = r8152b_init; |
5093 | ops->enable = rtl8152_enable; | |
5094 | ops->disable = rtl8152_disable; | |
5095 | ops->up = rtl8152_up; | |
5096 | ops->down = rtl8152_down; | |
5097 | ops->unload = rtl8152_unload; | |
5098 | ops->eee_get = r8152_get_eee; | |
5099 | ops->eee_set = r8152_set_eee; | |
2dd49e0f | 5100 | ops->in_nway = rtl8152_in_nway; |
a028a9e0 | 5101 | ops->hw_phy_cfg = r8152b_hw_phy_cfg; |
2609af19 | 5102 | ops->autosuspend_en = rtl_runtime_suspend_enable; |
43779f8d | 5103 | break; |
5104 | ||
55b65475 | 5105 | case RTL_VER_03: |
5106 | case RTL_VER_04: | |
5107 | case RTL_VER_05: | |
fb02eb4a | 5108 | case RTL_VER_06: |
55b65475 | 5109 | ops->init = r8153_init; |
5110 | ops->enable = rtl8153_enable; | |
5111 | ops->disable = rtl8153_disable; | |
5112 | ops->up = rtl8153_up; | |
5113 | ops->down = rtl8153_down; | |
5114 | ops->unload = rtl8153_unload; | |
5115 | ops->eee_get = r8153_get_eee; | |
5116 | ops->eee_set = r8153_set_eee; | |
2dd49e0f | 5117 | ops->in_nway = rtl8153_in_nway; |
a028a9e0 | 5118 | ops->hw_phy_cfg = r8153_hw_phy_cfg; |
2609af19 | 5119 | ops->autosuspend_en = rtl8153_runtime_enable; |
c81229c9 | 5120 | break; |
5121 | ||
65b82d69 | 5122 | case RTL_VER_08: |
5123 | case RTL_VER_09: | |
5124 | ops->init = r8153b_init; | |
5125 | ops->enable = rtl8153_enable; | |
5126 | ops->disable = rtl8153b_disable; | |
5127 | ops->up = rtl8153b_up; | |
5128 | ops->down = rtl8153b_down; | |
5129 | ops->unload = rtl8153b_unload; | |
5130 | ops->eee_get = r8153_get_eee; | |
5131 | ops->eee_set = r8153b_set_eee; | |
5132 | ops->in_nway = rtl8153_in_nway; | |
5133 | ops->hw_phy_cfg = r8153b_hw_phy_cfg; | |
5134 | ops->autosuspend_en = rtl8153b_runtime_enable; | |
5135 | break; | |
5136 | ||
c81229c9 | 5137 | default: |
55b65475 | 5138 | ret = -ENODEV; |
5139 | netif_err(tp, probe, tp->netdev, "Unknown Device\n"); | |
c81229c9 | 5140 | break; |
5141 | } | |
5142 | ||
5143 | return ret; | |
5144 | } | |
5145 | ||
33928eed | 5146 | static u8 rtl_get_version(struct usb_interface *intf) |
5147 | { | |
5148 | struct usb_device *udev = interface_to_usbdev(intf); | |
5149 | u32 ocp_data = 0; | |
5150 | __le32 *tmp; | |
5151 | u8 version; | |
5152 | int ret; | |
5153 | ||
5154 | tmp = kmalloc(sizeof(*tmp), GFP_KERNEL); | |
5155 | if (!tmp) | |
5156 | return 0; | |
5157 | ||
5158 | ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), | |
5159 | RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, | |
5160 | PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 500); | |
5161 | if (ret > 0) | |
5162 | ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK; | |
5163 | ||
5164 | kfree(tmp); | |
5165 | ||
5166 | switch (ocp_data) { | |
5167 | case 0x4c00: | |
5168 | version = RTL_VER_01; | |
5169 | break; | |
5170 | case 0x4c10: | |
5171 | version = RTL_VER_02; | |
5172 | break; | |
5173 | case 0x5c00: | |
5174 | version = RTL_VER_03; | |
5175 | break; | |
5176 | case 0x5c10: | |
5177 | version = RTL_VER_04; | |
5178 | break; | |
5179 | case 0x5c20: | |
5180 | version = RTL_VER_05; | |
5181 | break; | |
5182 | case 0x5c30: | |
5183 | version = RTL_VER_06; | |
5184 | break; | |
c27b32c2 | 5185 | case 0x4800: |
5186 | version = RTL_VER_07; | |
5187 | break; | |
65b82d69 | 5188 | case 0x6000: |
5189 | version = RTL_VER_08; | |
5190 | break; | |
5191 | case 0x6010: | |
5192 | version = RTL_VER_09; | |
5193 | break; | |
33928eed | 5194 | default: |
5195 | version = RTL_VER_UNKNOWN; | |
5196 | dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data); | |
5197 | break; | |
5198 | } | |
5199 | ||
eb3c28c1 ON |
5200 | dev_dbg(&intf->dev, "Detected version 0x%04x\n", version); |
5201 | ||
33928eed | 5202 | return version; |
5203 | } | |
5204 | ||
ac718b69 | 5205 | static int rtl8152_probe(struct usb_interface *intf, |
5206 | const struct usb_device_id *id) | |
5207 | { | |
5208 | struct usb_device *udev = interface_to_usbdev(intf); | |
33928eed | 5209 | u8 version = rtl_get_version(intf); |
ac718b69 | 5210 | struct r8152 *tp; |
5211 | struct net_device *netdev; | |
ebc2ec48 | 5212 | int ret; |
ac718b69 | 5213 | |
33928eed | 5214 | if (version == RTL_VER_UNKNOWN) |
5215 | return -ENODEV; | |
5216 | ||
10c32717 | 5217 | if (udev->actconfig->desc.bConfigurationValue != 1) { |
5218 | usb_driver_set_configuration(udev, 1); | |
5219 | return -ENODEV; | |
5220 | } | |
5221 | ||
66f6c658 JH |
5222 | if (intf->cur_altsetting->desc.bNumEndpoints < 3) |
5223 | return -ENODEV; | |
5224 | ||
10c32717 | 5225 | usb_reset_device(udev); |
ac718b69 | 5226 | netdev = alloc_etherdev(sizeof(struct r8152)); |
5227 | if (!netdev) { | |
4a8deae2 | 5228 | dev_err(&intf->dev, "Out of memory\n"); |
ac718b69 | 5229 | return -ENOMEM; |
5230 | } | |
5231 | ||
ebc2ec48 | 5232 | SET_NETDEV_DEV(netdev, &intf->dev); |
ac718b69 | 5233 | tp = netdev_priv(netdev); |
5234 | tp->msg_enable = 0x7FFF; | |
5235 | ||
e3ad412a | 5236 | tp->udev = udev; |
5237 | tp->netdev = netdev; | |
5238 | tp->intf = intf; | |
33928eed | 5239 | tp->version = version; |
5240 | ||
5241 | switch (version) { | |
5242 | case RTL_VER_01: | |
5243 | case RTL_VER_02: | |
c27b32c2 | 5244 | case RTL_VER_07: |
33928eed | 5245 | tp->mii.supports_gmii = 0; |
5246 | break; | |
5247 | default: | |
5248 | tp->mii.supports_gmii = 1; | |
5249 | break; | |
5250 | } | |
e3ad412a | 5251 | |
55b65475 | 5252 | ret = rtl_ops_init(tp); |
31ca1dec | 5253 | if (ret) |
5254 | goto out; | |
c81229c9 | 5255 | |
b5403273 | 5256 | mutex_init(&tp->control); |
ac718b69 | 5257 | INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t); |
a028a9e0 | 5258 | INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t); |
ac718b69 | 5259 | |
ac718b69 | 5260 | netdev->netdev_ops = &rtl8152_netdev_ops; |
5261 | netdev->watchdog_timeo = RTL8152_TX_TIMEOUT; | |
5bd23881 | 5262 | |
60c89071 | 5263 | netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | |
6128d1bb | 5264 | NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM | |
c5554298 | 5265 | NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX | |
5266 | NETIF_F_HW_VLAN_CTAG_TX; | |
60c89071 | 5267 | netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | |
6128d1bb | 5268 | NETIF_F_TSO | NETIF_F_FRAGLIST | |
c5554298 | 5269 | NETIF_F_IPV6_CSUM | NETIF_F_TSO6 | |
ccc39faf | 5270 | NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX; |
c5554298 | 5271 | netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | |
5272 | NETIF_F_HIGHDMA | NETIF_F_FRAGLIST | | |
5273 | NETIF_F_IPV6_CSUM | NETIF_F_TSO6; | |
db8515ef | 5274 | |
19c0f40d | 5275 | if (tp->version == RTL_VER_01) { |
5276 | netdev->features &= ~NETIF_F_RXCSUM; | |
5277 | netdev->hw_features &= ~NETIF_F_RXCSUM; | |
5278 | } | |
5279 | ||
71512e43 KHF |
5280 | if (le16_to_cpu(udev->descriptor.idVendor) == VENDOR_ID_LENOVO && |
5281 | le16_to_cpu(udev->descriptor.idProduct) == 0x3082) | |
5282 | set_bit(LENOVO_MACPASSTHRU, &tp->flags); | |
5283 | ||
544e07cc KHF |
5284 | if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial && |
5285 | (!strcmp(udev->serial, "000001000000") || !strcmp(udev->serial, "000002000000"))) { | |
0b165514 KHF |
5286 | dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation"); |
5287 | set_bit(DELL_TB_RX_AGG_BUG, &tp->flags); | |
5288 | } | |
5289 | ||
7ad24ea4 | 5290 | netdev->ethtool_ops = &ops; |
60c89071 | 5291 | netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE); |
ac718b69 | 5292 | |
f77f0aee JW |
5293 | /* MTU range: 68 - 1500 or 9194 */ |
5294 | netdev->min_mtu = ETH_MIN_MTU; | |
5295 | switch (tp->version) { | |
5296 | case RTL_VER_01: | |
5297 | case RTL_VER_02: | |
5298 | netdev->max_mtu = ETH_DATA_LEN; | |
5299 | break; | |
5300 | default: | |
5301 | netdev->max_mtu = RTL8153_MAX_MTU; | |
5302 | break; | |
5303 | } | |
5304 | ||
ac718b69 | 5305 | tp->mii.dev = netdev; |
5306 | tp->mii.mdio_read = read_mii_word; | |
5307 | tp->mii.mdio_write = write_mii_word; | |
5308 | tp->mii.phy_id_mask = 0x3f; | |
5309 | tp->mii.reg_num_mask = 0x1f; | |
5310 | tp->mii.phy_id = R8152_PHY_ID; | |
ac718b69 | 5311 | |
aa7e26b6 | 5312 | tp->autoneg = AUTONEG_ENABLE; |
5313 | tp->speed = tp->mii.supports_gmii ? SPEED_1000 : SPEED_100; | |
5314 | tp->duplex = DUPLEX_FULL; | |
5315 | ||
9a4be1bd | 5316 | intf->needs_remote_wakeup = 1; |
5317 | ||
d654a40f HW |
5318 | if (!rtl_can_wakeup(tp)) |
5319 | __rtl_set_wol(tp, 0); | |
5320 | else | |
5321 | tp->saved_wolopts = __rtl_get_wol(tp); | |
5322 | ||
c81229c9 | 5323 | tp->rtl_ops.init(tp); |
a028a9e0 | 5324 | queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0); |
ac718b69 | 5325 | set_ethernet_addr(tp); |
5326 | ||
ac718b69 | 5327 | usb_set_intfdata(intf, tp); |
d823ab68 | 5328 | netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT); |
ac718b69 | 5329 | |
ebc2ec48 | 5330 | ret = register_netdev(netdev); |
5331 | if (ret != 0) { | |
4a8deae2 | 5332 | netif_err(tp, probe, netdev, "couldn't register the device\n"); |
ebc2ec48 | 5333 | goto out1; |
ac718b69 | 5334 | } |
5335 | ||
21ff2e89 | 5336 | if (tp->saved_wolopts) |
5337 | device_set_wakeup_enable(&udev->dev, true); | |
5338 | else | |
5339 | device_set_wakeup_enable(&udev->dev, false); | |
5340 | ||
4a8deae2 | 5341 | netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION); |
ac718b69 | 5342 | |
5343 | return 0; | |
5344 | ||
ac718b69 | 5345 | out1: |
d823ab68 | 5346 | netif_napi_del(&tp->napi); |
ebc2ec48 | 5347 | usb_set_intfdata(intf, NULL); |
ac718b69 | 5348 | out: |
5349 | free_netdev(netdev); | |
ebc2ec48 | 5350 | return ret; |
ac718b69 | 5351 | } |
5352 | ||
ac718b69 | 5353 | static void rtl8152_disconnect(struct usb_interface *intf) |
5354 | { | |
5355 | struct r8152 *tp = usb_get_intfdata(intf); | |
5356 | ||
5357 | usb_set_intfdata(intf, NULL); | |
5358 | if (tp) { | |
f561de33 | 5359 | struct usb_device *udev = tp->udev; |
5360 | ||
5361 | if (udev->state == USB_STATE_NOTATTACHED) | |
5362 | set_bit(RTL8152_UNPLUG, &tp->flags); | |
5363 | ||
d823ab68 | 5364 | netif_napi_del(&tp->napi); |
ac718b69 | 5365 | unregister_netdev(tp->netdev); |
a028a9e0 | 5366 | cancel_delayed_work_sync(&tp->hw_phy_work); |
c81229c9 | 5367 | tp->rtl_ops.unload(tp); |
ac718b69 | 5368 | free_netdev(tp->netdev); |
5369 | } | |
5370 | } | |
5371 | ||
d9a28c5b | 5372 | #define REALTEK_USB_DEVICE(vend, prod) \ |
5373 | .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \ | |
5374 | USB_DEVICE_ID_MATCH_INT_CLASS, \ | |
5375 | .idVendor = (vend), \ | |
5376 | .idProduct = (prod), \ | |
5377 | .bInterfaceClass = USB_CLASS_VENDOR_SPEC \ | |
5378 | }, \ | |
5379 | { \ | |
5380 | .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \ | |
5381 | USB_DEVICE_ID_MATCH_DEVICE, \ | |
5382 | .idVendor = (vend), \ | |
5383 | .idProduct = (prod), \ | |
5384 | .bInterfaceClass = USB_CLASS_COMM, \ | |
5385 | .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \ | |
5386 | .bInterfaceProtocol = USB_CDC_PROTO_NONE | |
5387 | ||
ac718b69 | 5388 | /* table of devices that work with this driver */ |
9b4355fb | 5389 | static const struct usb_device_id rtl8152_table[] = { |
c27b32c2 | 5390 | {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050)}, |
d9a28c5b | 5391 | {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)}, |
5392 | {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)}, | |
d5b07ccc RR |
5393 | {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab)}, |
5394 | {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6)}, | |
d9a28c5b | 5395 | {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)}, |
1006da19 | 5396 | {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)}, |
d248cafc | 5397 | {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3062)}, |
5398 | {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3069)}, | |
71512e43 | 5399 | {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x3082)}, |
d248cafc | 5400 | {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)}, |
5401 | {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x720c)}, | |
5402 | {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7214)}, | |
932e40d8 | 5403 | {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0xa387)}, |
90841047 | 5404 | {REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041)}, |
d065c3c1 | 5405 | {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)}, |
9d11b066 | 5406 | {REALTEK_USB_DEVICE(VENDOR_ID_TPLINK, 0x0601)}, |
ac718b69 | 5407 | {} |
5408 | }; | |
5409 | ||
5410 | MODULE_DEVICE_TABLE(usb, rtl8152_table); | |
5411 | ||
5412 | static struct usb_driver rtl8152_driver = { | |
5413 | .name = MODULENAME, | |
ebc2ec48 | 5414 | .id_table = rtl8152_table, |
ac718b69 | 5415 | .probe = rtl8152_probe, |
5416 | .disconnect = rtl8152_disconnect, | |
ac718b69 | 5417 | .suspend = rtl8152_suspend, |
ebc2ec48 | 5418 | .resume = rtl8152_resume, |
7ec2541a | 5419 | .reset_resume = rtl8152_reset_resume, |
e501139a | 5420 | .pre_reset = rtl8152_pre_reset, |
5421 | .post_reset = rtl8152_post_reset, | |
9a4be1bd | 5422 | .supports_autosuspend = 1, |
a634782f | 5423 | .disable_hub_initiated_lpm = 1, |
ac718b69 | 5424 | }; |
5425 | ||
b4236daa | 5426 | module_usb_driver(rtl8152_driver); |
ac718b69 | 5427 | |
5428 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
5429 | MODULE_DESCRIPTION(DRIVER_DESC); | |
5430 | MODULE_LICENSE("GPL"); | |
c961e877 | 5431 | MODULE_VERSION(DRIVER_VERSION); |