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[mirror_ubuntu-bionic-kernel.git] / drivers / net / usb / smsc75xx.c
CommitLineData
d0cad871
SG
1 /***************************************************************************
2 *
3 * Copyright (C) 2007-2010 SMSC
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
9cb00073 16 * along with this program; if not, see <http://www.gnu.org/licenses/>.
d0cad871
SG
17 *
18 *****************************************************************************/
19
20#include <linux/module.h>
21#include <linux/kmod.h>
d0cad871
SG
22#include <linux/netdevice.h>
23#include <linux/etherdevice.h>
24#include <linux/ethtool.h>
25#include <linux/mii.h>
26#include <linux/usb.h>
899a391b
SG
27#include <linux/bitrev.h>
28#include <linux/crc16.h>
d0cad871
SG
29#include <linux/crc32.h>
30#include <linux/usb/usbnet.h>
5a0e3ad6 31#include <linux/slab.h>
c489565b 32#include <linux/of_net.h>
d0cad871
SG
33#include "smsc75xx.h"
34
35#define SMSC_CHIPNAME "smsc75xx"
36#define SMSC_DRIVER_VERSION "1.0.0"
37#define HS_USB_PKT_SIZE (512)
38#define FS_USB_PKT_SIZE (64)
39#define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE)
40#define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE)
41#define DEFAULT_BULK_IN_DELAY (0x00002000)
42#define MAX_SINGLE_PACKET_SIZE (9000)
43#define LAN75XX_EEPROM_MAGIC (0x7500)
44#define EEPROM_MAC_OFFSET (0x01)
45#define DEFAULT_TX_CSUM_ENABLE (true)
46#define DEFAULT_RX_CSUM_ENABLE (true)
d0cad871
SG
47#define SMSC75XX_INTERNAL_PHY_ID (1)
48#define SMSC75XX_TX_OVERHEAD (8)
49#define MAX_RX_FIFO_SIZE (20 * 1024)
50#define MAX_TX_FIFO_SIZE (12 * 1024)
51#define USB_VENDOR_ID_SMSC (0x0424)
52#define USB_PRODUCT_ID_LAN7500 (0x7500)
53#define USB_PRODUCT_ID_LAN7505 (0x7505)
ea1649de 54#define RXW_PADDING 2
f329ccdc 55#define SUPPORTED_WAKE (WAKE_PHY | WAKE_UCAST | WAKE_BCAST | \
899a391b 56 WAKE_MCAST | WAKE_ARP | WAKE_MAGIC)
d0cad871 57
b4cdea9c
SG
58#define SUSPEND_SUSPEND0 (0x01)
59#define SUSPEND_SUSPEND1 (0x02)
60#define SUSPEND_SUSPEND2 (0x04)
61#define SUSPEND_SUSPEND3 (0x08)
b4cdea9c
SG
62#define SUSPEND_ALLMODES (SUSPEND_SUSPEND0 | SUSPEND_SUSPEND1 | \
63 SUSPEND_SUSPEND2 | SUSPEND_SUSPEND3)
64
d0cad871
SG
65struct smsc75xx_priv {
66 struct usbnet *dev;
67 u32 rfe_ctl;
6c636503 68 u32 wolopts;
d0cad871 69 u32 multicast_hash_table[DP_SEL_VHF_HASH_LEN];
d0cad871
SG
70 struct mutex dataport_mutex;
71 spinlock_t rfe_ctl_lock;
72 struct work_struct set_multicast;
b4cdea9c 73 u8 suspend_flags;
d0cad871
SG
74};
75
76struct usb_context {
77 struct usb_ctrlrequest req;
78 struct usbnet *dev;
79};
80
eb939922 81static bool turbo_mode = true;
d0cad871
SG
82module_param(turbo_mode, bool, 0644);
83MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction");
84
1dd973c2
YO
85static int smsc75xx_link_ok_nopm(struct usbnet *dev);
86static int smsc75xx_phy_gig_workaround(struct usbnet *dev);
87
47bbea41
ML
88static int __must_check __smsc75xx_read_reg(struct usbnet *dev, u32 index,
89 u32 *data, int in_pm)
d0cad871 90{
2b2e41e3 91 u32 buf;
d0cad871 92 int ret;
47bbea41 93 int (*fn)(struct usbnet *, u8, u8, u16, u16, void *, u16);
d0cad871
SG
94
95 BUG_ON(!dev);
96
47bbea41
ML
97 if (!in_pm)
98 fn = usbnet_read_cmd;
99 else
100 fn = usbnet_read_cmd_nopm;
101
102 ret = fn(dev, USB_VENDOR_REQUEST_READ_REGISTER, USB_DIR_IN
103 | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
104 0, index, &buf, 4);
58ef6a3f 105 if (unlikely(ret < 0)) {
1e1d7412
JP
106 netdev_warn(dev->net, "Failed to read reg index 0x%08x: %d\n",
107 index, ret);
58ef6a3f
DC
108 return ret;
109 }
d0cad871 110
2b2e41e3
ML
111 le32_to_cpus(&buf);
112 *data = buf;
d0cad871
SG
113
114 return ret;
115}
116
47bbea41
ML
117static int __must_check __smsc75xx_write_reg(struct usbnet *dev, u32 index,
118 u32 data, int in_pm)
d0cad871 119{
2b2e41e3 120 u32 buf;
d0cad871 121 int ret;
47bbea41 122 int (*fn)(struct usbnet *, u8, u8, u16, u16, const void *, u16);
d0cad871
SG
123
124 BUG_ON(!dev);
125
47bbea41
ML
126 if (!in_pm)
127 fn = usbnet_write_cmd;
128 else
129 fn = usbnet_write_cmd_nopm;
130
2b2e41e3
ML
131 buf = data;
132 cpu_to_le32s(&buf);
d0cad871 133
47bbea41
ML
134 ret = fn(dev, USB_VENDOR_REQUEST_WRITE_REGISTER, USB_DIR_OUT
135 | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
136 0, index, &buf, 4);
d0cad871 137 if (unlikely(ret < 0))
1e1d7412
JP
138 netdev_warn(dev->net, "Failed to write reg index 0x%08x: %d\n",
139 index, ret);
d0cad871 140
d0cad871
SG
141 return ret;
142}
143
47bbea41
ML
144static int __must_check smsc75xx_read_reg_nopm(struct usbnet *dev, u32 index,
145 u32 *data)
146{
147 return __smsc75xx_read_reg(dev, index, data, 1);
148}
149
150static int __must_check smsc75xx_write_reg_nopm(struct usbnet *dev, u32 index,
151 u32 data)
152{
153 return __smsc75xx_write_reg(dev, index, data, 1);
154}
155
156static int __must_check smsc75xx_read_reg(struct usbnet *dev, u32 index,
157 u32 *data)
158{
159 return __smsc75xx_read_reg(dev, index, data, 0);
160}
161
162static int __must_check smsc75xx_write_reg(struct usbnet *dev, u32 index,
163 u32 data)
164{
165 return __smsc75xx_write_reg(dev, index, data, 0);
166}
167
d0cad871
SG
168/* Loop until the read is completed with timeout
169 * called with phy_mutex held */
f329ccdc
SG
170static __must_check int __smsc75xx_phy_wait_not_busy(struct usbnet *dev,
171 int in_pm)
d0cad871
SG
172{
173 unsigned long start_time = jiffies;
174 u32 val;
175 int ret;
176
177 do {
f329ccdc 178 ret = __smsc75xx_read_reg(dev, MII_ACCESS, &val, in_pm);
e3c678e6
SG
179 if (ret < 0) {
180 netdev_warn(dev->net, "Error reading MII_ACCESS\n");
181 return ret;
182 }
d0cad871
SG
183
184 if (!(val & MII_ACCESS_BUSY))
185 return 0;
186 } while (!time_after(jiffies, start_time + HZ));
187
188 return -EIO;
189}
190
f329ccdc
SG
191static int __smsc75xx_mdio_read(struct net_device *netdev, int phy_id, int idx,
192 int in_pm)
d0cad871
SG
193{
194 struct usbnet *dev = netdev_priv(netdev);
195 u32 val, addr;
196 int ret;
197
198 mutex_lock(&dev->phy_mutex);
199
200 /* confirm MII not busy */
f329ccdc 201 ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
e3c678e6
SG
202 if (ret < 0) {
203 netdev_warn(dev->net, "MII is busy in smsc75xx_mdio_read\n");
204 goto done;
205 }
d0cad871
SG
206
207 /* set the address, index & direction (read from PHY) */
208 phy_id &= dev->mii.phy_id_mask;
209 idx &= dev->mii.reg_num_mask;
210 addr = ((phy_id << MII_ACCESS_PHY_ADDR_SHIFT) & MII_ACCESS_PHY_ADDR)
211 | ((idx << MII_ACCESS_REG_ADDR_SHIFT) & MII_ACCESS_REG_ADDR)
cb8722d3 212 | MII_ACCESS_READ | MII_ACCESS_BUSY;
f329ccdc 213 ret = __smsc75xx_write_reg(dev, MII_ACCESS, addr, in_pm);
e3c678e6
SG
214 if (ret < 0) {
215 netdev_warn(dev->net, "Error writing MII_ACCESS\n");
216 goto done;
217 }
d0cad871 218
f329ccdc 219 ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
e3c678e6
SG
220 if (ret < 0) {
221 netdev_warn(dev->net, "Timed out reading MII reg %02X\n", idx);
222 goto done;
223 }
d0cad871 224
f329ccdc 225 ret = __smsc75xx_read_reg(dev, MII_DATA, &val, in_pm);
e3c678e6
SG
226 if (ret < 0) {
227 netdev_warn(dev->net, "Error reading MII_DATA\n");
228 goto done;
229 }
d0cad871
SG
230
231 ret = (u16)(val & 0xFFFF);
232
233done:
234 mutex_unlock(&dev->phy_mutex);
235 return ret;
236}
237
f329ccdc
SG
238static void __smsc75xx_mdio_write(struct net_device *netdev, int phy_id,
239 int idx, int regval, int in_pm)
d0cad871
SG
240{
241 struct usbnet *dev = netdev_priv(netdev);
242 u32 val, addr;
243 int ret;
244
245 mutex_lock(&dev->phy_mutex);
246
247 /* confirm MII not busy */
f329ccdc 248 ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
e3c678e6
SG
249 if (ret < 0) {
250 netdev_warn(dev->net, "MII is busy in smsc75xx_mdio_write\n");
251 goto done;
252 }
d0cad871
SG
253
254 val = regval;
f329ccdc 255 ret = __smsc75xx_write_reg(dev, MII_DATA, val, in_pm);
e3c678e6
SG
256 if (ret < 0) {
257 netdev_warn(dev->net, "Error writing MII_DATA\n");
258 goto done;
259 }
d0cad871
SG
260
261 /* set the address, index & direction (write to PHY) */
262 phy_id &= dev->mii.phy_id_mask;
263 idx &= dev->mii.reg_num_mask;
264 addr = ((phy_id << MII_ACCESS_PHY_ADDR_SHIFT) & MII_ACCESS_PHY_ADDR)
265 | ((idx << MII_ACCESS_REG_ADDR_SHIFT) & MII_ACCESS_REG_ADDR)
cb8722d3 266 | MII_ACCESS_WRITE | MII_ACCESS_BUSY;
f329ccdc 267 ret = __smsc75xx_write_reg(dev, MII_ACCESS, addr, in_pm);
e3c678e6
SG
268 if (ret < 0) {
269 netdev_warn(dev->net, "Error writing MII_ACCESS\n");
270 goto done;
271 }
d0cad871 272
f329ccdc 273 ret = __smsc75xx_phy_wait_not_busy(dev, in_pm);
e3c678e6
SG
274 if (ret < 0) {
275 netdev_warn(dev->net, "Timed out writing MII reg %02X\n", idx);
276 goto done;
277 }
d0cad871
SG
278
279done:
280 mutex_unlock(&dev->phy_mutex);
281}
282
f329ccdc
SG
283static int smsc75xx_mdio_read_nopm(struct net_device *netdev, int phy_id,
284 int idx)
285{
286 return __smsc75xx_mdio_read(netdev, phy_id, idx, 1);
287}
288
289static void smsc75xx_mdio_write_nopm(struct net_device *netdev, int phy_id,
290 int idx, int regval)
291{
292 __smsc75xx_mdio_write(netdev, phy_id, idx, regval, 1);
293}
294
295static int smsc75xx_mdio_read(struct net_device *netdev, int phy_id, int idx)
296{
297 return __smsc75xx_mdio_read(netdev, phy_id, idx, 0);
298}
299
300static void smsc75xx_mdio_write(struct net_device *netdev, int phy_id, int idx,
301 int regval)
302{
303 __smsc75xx_mdio_write(netdev, phy_id, idx, regval, 0);
304}
305
d0cad871
SG
306static int smsc75xx_wait_eeprom(struct usbnet *dev)
307{
308 unsigned long start_time = jiffies;
309 u32 val;
310 int ret;
311
312 do {
313 ret = smsc75xx_read_reg(dev, E2P_CMD, &val);
e3c678e6
SG
314 if (ret < 0) {
315 netdev_warn(dev->net, "Error reading E2P_CMD\n");
316 return ret;
317 }
d0cad871
SG
318
319 if (!(val & E2P_CMD_BUSY) || (val & E2P_CMD_TIMEOUT))
320 break;
321 udelay(40);
322 } while (!time_after(jiffies, start_time + HZ));
323
324 if (val & (E2P_CMD_TIMEOUT | E2P_CMD_BUSY)) {
1e1d7412 325 netdev_warn(dev->net, "EEPROM read operation timeout\n");
d0cad871
SG
326 return -EIO;
327 }
328
329 return 0;
330}
331
332static int smsc75xx_eeprom_confirm_not_busy(struct usbnet *dev)
333{
334 unsigned long start_time = jiffies;
335 u32 val;
336 int ret;
337
338 do {
339 ret = smsc75xx_read_reg(dev, E2P_CMD, &val);
e3c678e6
SG
340 if (ret < 0) {
341 netdev_warn(dev->net, "Error reading E2P_CMD\n");
342 return ret;
343 }
d0cad871
SG
344
345 if (!(val & E2P_CMD_BUSY))
346 return 0;
347
348 udelay(40);
349 } while (!time_after(jiffies, start_time + HZ));
350
1e1d7412 351 netdev_warn(dev->net, "EEPROM is busy\n");
d0cad871
SG
352 return -EIO;
353}
354
355static int smsc75xx_read_eeprom(struct usbnet *dev, u32 offset, u32 length,
356 u8 *data)
357{
358 u32 val;
359 int i, ret;
360
361 BUG_ON(!dev);
362 BUG_ON(!data);
363
364 ret = smsc75xx_eeprom_confirm_not_busy(dev);
365 if (ret)
366 return ret;
367
368 for (i = 0; i < length; i++) {
369 val = E2P_CMD_BUSY | E2P_CMD_READ | (offset & E2P_CMD_ADDR);
370 ret = smsc75xx_write_reg(dev, E2P_CMD, val);
e3c678e6
SG
371 if (ret < 0) {
372 netdev_warn(dev->net, "Error writing E2P_CMD\n");
373 return ret;
374 }
d0cad871
SG
375
376 ret = smsc75xx_wait_eeprom(dev);
377 if (ret < 0)
378 return ret;
379
380 ret = smsc75xx_read_reg(dev, E2P_DATA, &val);
e3c678e6
SG
381 if (ret < 0) {
382 netdev_warn(dev->net, "Error reading E2P_DATA\n");
383 return ret;
384 }
d0cad871
SG
385
386 data[i] = val & 0xFF;
387 offset++;
388 }
389
390 return 0;
391}
392
393static int smsc75xx_write_eeprom(struct usbnet *dev, u32 offset, u32 length,
394 u8 *data)
395{
396 u32 val;
397 int i, ret;
398
399 BUG_ON(!dev);
400 BUG_ON(!data);
401
402 ret = smsc75xx_eeprom_confirm_not_busy(dev);
403 if (ret)
404 return ret;
405
406 /* Issue write/erase enable command */
407 val = E2P_CMD_BUSY | E2P_CMD_EWEN;
408 ret = smsc75xx_write_reg(dev, E2P_CMD, val);
e3c678e6
SG
409 if (ret < 0) {
410 netdev_warn(dev->net, "Error writing E2P_CMD\n");
411 return ret;
412 }
d0cad871
SG
413
414 ret = smsc75xx_wait_eeprom(dev);
415 if (ret < 0)
416 return ret;
417
418 for (i = 0; i < length; i++) {
419
420 /* Fill data register */
421 val = data[i];
422 ret = smsc75xx_write_reg(dev, E2P_DATA, val);
e3c678e6
SG
423 if (ret < 0) {
424 netdev_warn(dev->net, "Error writing E2P_DATA\n");
425 return ret;
426 }
d0cad871
SG
427
428 /* Send "write" command */
429 val = E2P_CMD_BUSY | E2P_CMD_WRITE | (offset & E2P_CMD_ADDR);
430 ret = smsc75xx_write_reg(dev, E2P_CMD, val);
e3c678e6
SG
431 if (ret < 0) {
432 netdev_warn(dev->net, "Error writing E2P_CMD\n");
433 return ret;
434 }
d0cad871
SG
435
436 ret = smsc75xx_wait_eeprom(dev);
437 if (ret < 0)
438 return ret;
439
440 offset++;
441 }
442
443 return 0;
444}
445
446static int smsc75xx_dataport_wait_not_busy(struct usbnet *dev)
447{
448 int i, ret;
449
450 for (i = 0; i < 100; i++) {
451 u32 dp_sel;
452 ret = smsc75xx_read_reg(dev, DP_SEL, &dp_sel);
e3c678e6
SG
453 if (ret < 0) {
454 netdev_warn(dev->net, "Error reading DP_SEL\n");
455 return ret;
456 }
d0cad871
SG
457
458 if (dp_sel & DP_SEL_DPRDY)
459 return 0;
460
461 udelay(40);
462 }
463
1e1d7412 464 netdev_warn(dev->net, "smsc75xx_dataport_wait_not_busy timed out\n");
d0cad871
SG
465
466 return -EIO;
467}
468
469static int smsc75xx_dataport_write(struct usbnet *dev, u32 ram_select, u32 addr,
470 u32 length, u32 *buf)
471{
472 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
473 u32 dp_sel;
474 int i, ret;
475
476 mutex_lock(&pdata->dataport_mutex);
477
478 ret = smsc75xx_dataport_wait_not_busy(dev);
e3c678e6
SG
479 if (ret < 0) {
480 netdev_warn(dev->net, "smsc75xx_dataport_write busy on entry\n");
481 goto done;
482 }
d0cad871
SG
483
484 ret = smsc75xx_read_reg(dev, DP_SEL, &dp_sel);
e3c678e6
SG
485 if (ret < 0) {
486 netdev_warn(dev->net, "Error reading DP_SEL\n");
487 goto done;
488 }
d0cad871
SG
489
490 dp_sel &= ~DP_SEL_RSEL;
491 dp_sel |= ram_select;
492 ret = smsc75xx_write_reg(dev, DP_SEL, dp_sel);
e3c678e6
SG
493 if (ret < 0) {
494 netdev_warn(dev->net, "Error writing DP_SEL\n");
495 goto done;
496 }
d0cad871
SG
497
498 for (i = 0; i < length; i++) {
499 ret = smsc75xx_write_reg(dev, DP_ADDR, addr + i);
e3c678e6
SG
500 if (ret < 0) {
501 netdev_warn(dev->net, "Error writing DP_ADDR\n");
502 goto done;
503 }
d0cad871
SG
504
505 ret = smsc75xx_write_reg(dev, DP_DATA, buf[i]);
e3c678e6
SG
506 if (ret < 0) {
507 netdev_warn(dev->net, "Error writing DP_DATA\n");
508 goto done;
509 }
d0cad871
SG
510
511 ret = smsc75xx_write_reg(dev, DP_CMD, DP_CMD_WRITE);
e3c678e6
SG
512 if (ret < 0) {
513 netdev_warn(dev->net, "Error writing DP_CMD\n");
514 goto done;
515 }
d0cad871
SG
516
517 ret = smsc75xx_dataport_wait_not_busy(dev);
e3c678e6
SG
518 if (ret < 0) {
519 netdev_warn(dev->net, "smsc75xx_dataport_write timeout\n");
520 goto done;
521 }
d0cad871
SG
522 }
523
524done:
525 mutex_unlock(&pdata->dataport_mutex);
526 return ret;
527}
528
529/* returns hash bit number for given MAC address */
530static u32 smsc75xx_hash(char addr[ETH_ALEN])
531{
532 return (ether_crc(ETH_ALEN, addr) >> 23) & 0x1ff;
533}
534
535static void smsc75xx_deferred_multicast_write(struct work_struct *param)
536{
537 struct smsc75xx_priv *pdata =
538 container_of(param, struct smsc75xx_priv, set_multicast);
539 struct usbnet *dev = pdata->dev;
540 int ret;
541
1e1d7412
JP
542 netif_dbg(dev, drv, dev->net, "deferred multicast write 0x%08x\n",
543 pdata->rfe_ctl);
d0cad871
SG
544
545 smsc75xx_dataport_write(dev, DP_SEL_VHF, DP_SEL_VHF_VLAN_LEN,
546 DP_SEL_VHF_HASH_LEN, pdata->multicast_hash_table);
547
548 ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
e3c678e6
SG
549 if (ret < 0)
550 netdev_warn(dev->net, "Error writing RFE_CRL\n");
d0cad871
SG
551}
552
553static void smsc75xx_set_multicast(struct net_device *netdev)
554{
555 struct usbnet *dev = netdev_priv(netdev);
556 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
557 unsigned long flags;
558 int i;
559
560 spin_lock_irqsave(&pdata->rfe_ctl_lock, flags);
561
562 pdata->rfe_ctl &=
563 ~(RFE_CTL_AU | RFE_CTL_AM | RFE_CTL_DPF | RFE_CTL_MHF);
564 pdata->rfe_ctl |= RFE_CTL_AB;
565
566 for (i = 0; i < DP_SEL_VHF_HASH_LEN; i++)
567 pdata->multicast_hash_table[i] = 0;
568
569 if (dev->net->flags & IFF_PROMISC) {
1e1d7412 570 netif_dbg(dev, drv, dev->net, "promiscuous mode enabled\n");
d0cad871
SG
571 pdata->rfe_ctl |= RFE_CTL_AM | RFE_CTL_AU;
572 } else if (dev->net->flags & IFF_ALLMULTI) {
1e1d7412 573 netif_dbg(dev, drv, dev->net, "receive all multicast enabled\n");
d0cad871
SG
574 pdata->rfe_ctl |= RFE_CTL_AM | RFE_CTL_DPF;
575 } else if (!netdev_mc_empty(dev->net)) {
22bedad3 576 struct netdev_hw_addr *ha;
d0cad871 577
1e1d7412 578 netif_dbg(dev, drv, dev->net, "receive multicast hash filter\n");
d0cad871
SG
579
580 pdata->rfe_ctl |= RFE_CTL_MHF | RFE_CTL_DPF;
581
22bedad3
JP
582 netdev_for_each_mc_addr(ha, netdev) {
583 u32 bitnum = smsc75xx_hash(ha->addr);
d0cad871
SG
584 pdata->multicast_hash_table[bitnum / 32] |=
585 (1 << (bitnum % 32));
586 }
587 } else {
1e1d7412 588 netif_dbg(dev, drv, dev->net, "receive own packets only\n");
d0cad871
SG
589 pdata->rfe_ctl |= RFE_CTL_DPF;
590 }
591
592 spin_unlock_irqrestore(&pdata->rfe_ctl_lock, flags);
593
594 /* defer register writes to a sleepable context */
595 schedule_work(&pdata->set_multicast);
596}
597
598static int smsc75xx_update_flowcontrol(struct usbnet *dev, u8 duplex,
599 u16 lcladv, u16 rmtadv)
600{
601 u32 flow = 0, fct_flow = 0;
602 int ret;
603
604 if (duplex == DUPLEX_FULL) {
605 u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
606
607 if (cap & FLOW_CTRL_TX) {
608 flow = (FLOW_TX_FCEN | 0xFFFF);
609 /* set fct_flow thresholds to 20% and 80% */
610 fct_flow = (8 << 8) | 32;
611 }
612
613 if (cap & FLOW_CTRL_RX)
614 flow |= FLOW_RX_FCEN;
615
1e1d7412
JP
616 netif_dbg(dev, link, dev->net, "rx pause %s, tx pause %s\n",
617 (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
618 (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
d0cad871 619 } else {
1e1d7412 620 netif_dbg(dev, link, dev->net, "half duplex\n");
d0cad871
SG
621 }
622
623 ret = smsc75xx_write_reg(dev, FLOW, flow);
e3c678e6
SG
624 if (ret < 0) {
625 netdev_warn(dev->net, "Error writing FLOW\n");
626 return ret;
627 }
d0cad871
SG
628
629 ret = smsc75xx_write_reg(dev, FCT_FLOW, fct_flow);
e3c678e6
SG
630 if (ret < 0) {
631 netdev_warn(dev->net, "Error writing FCT_FLOW\n");
632 return ret;
633 }
d0cad871
SG
634
635 return 0;
636}
637
638static int smsc75xx_link_reset(struct usbnet *dev)
639{
640 struct mii_if_info *mii = &dev->mii;
8ae6daca 641 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
d0cad871
SG
642 u16 lcladv, rmtadv;
643 int ret;
644
4f94a929 645 /* write to clear phy interrupt status */
7749622d
SG
646 smsc75xx_mdio_write(dev->net, mii->phy_id, PHY_INT_SRC,
647 PHY_INT_SRC_CLEAR_ALL);
d0cad871
SG
648
649 ret = smsc75xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL);
e3c678e6
SG
650 if (ret < 0) {
651 netdev_warn(dev->net, "Error writing INT_STS\n");
652 return ret;
653 }
d0cad871
SG
654
655 mii_check_media(mii, 1, 1);
656 mii_ethtool_gset(&dev->mii, &ecmd);
657 lcladv = smsc75xx_mdio_read(dev->net, mii->phy_id, MII_ADVERTISE);
658 rmtadv = smsc75xx_mdio_read(dev->net, mii->phy_id, MII_LPA);
659
1e1d7412
JP
660 netif_dbg(dev, link, dev->net, "speed: %u duplex: %d lcladv: %04x rmtadv: %04x\n",
661 ethtool_cmd_speed(&ecmd), ecmd.duplex, lcladv, rmtadv);
d0cad871
SG
662
663 return smsc75xx_update_flowcontrol(dev, ecmd.duplex, lcladv, rmtadv);
664}
665
666static void smsc75xx_status(struct usbnet *dev, struct urb *urb)
667{
668 u32 intdata;
669
670 if (urb->actual_length != 4) {
1e1d7412
JP
671 netdev_warn(dev->net, "unexpected urb length %d\n",
672 urb->actual_length);
d0cad871
SG
673 return;
674 }
675
676 memcpy(&intdata, urb->transfer_buffer, 4);
677 le32_to_cpus(&intdata);
678
1e1d7412 679 netif_dbg(dev, link, dev->net, "intdata: 0x%08X\n", intdata);
d0cad871
SG
680
681 if (intdata & INT_ENP_PHY_INT)
682 usbnet_defer_kevent(dev, EVENT_LINK_RESET);
683 else
1e1d7412
JP
684 netdev_warn(dev->net, "unexpected interrupt, intdata=0x%08X\n",
685 intdata);
d0cad871
SG
686}
687
d0cad871
SG
688static int smsc75xx_ethtool_get_eeprom_len(struct net_device *net)
689{
690 return MAX_EEPROM_SIZE;
691}
692
693static int smsc75xx_ethtool_get_eeprom(struct net_device *netdev,
694 struct ethtool_eeprom *ee, u8 *data)
695{
696 struct usbnet *dev = netdev_priv(netdev);
697
698 ee->magic = LAN75XX_EEPROM_MAGIC;
699
700 return smsc75xx_read_eeprom(dev, ee->offset, ee->len, data);
701}
702
703static int smsc75xx_ethtool_set_eeprom(struct net_device *netdev,
704 struct ethtool_eeprom *ee, u8 *data)
705{
706 struct usbnet *dev = netdev_priv(netdev);
707
708 if (ee->magic != LAN75XX_EEPROM_MAGIC) {
1e1d7412
JP
709 netdev_warn(dev->net, "EEPROM: magic value mismatch: 0x%x\n",
710 ee->magic);
d0cad871
SG
711 return -EINVAL;
712 }
713
714 return smsc75xx_write_eeprom(dev, ee->offset, ee->len, data);
715}
716
6c636503
SG
717static void smsc75xx_ethtool_get_wol(struct net_device *net,
718 struct ethtool_wolinfo *wolinfo)
719{
720 struct usbnet *dev = netdev_priv(net);
721 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
722
723 wolinfo->supported = SUPPORTED_WAKE;
724 wolinfo->wolopts = pdata->wolopts;
725}
726
727static int smsc75xx_ethtool_set_wol(struct net_device *net,
728 struct ethtool_wolinfo *wolinfo)
729{
730 struct usbnet *dev = netdev_priv(net);
731 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
351f33d9 732 int ret;
6c636503 733
5376412b
FF
734 if (wolinfo->wolopts & ~SUPPORTED_WAKE)
735 return -EINVAL;
736
6c636503 737 pdata->wolopts = wolinfo->wolopts & SUPPORTED_WAKE;
351f33d9
SG
738
739 ret = device_set_wakeup_enable(&dev->udev->dev, pdata->wolopts);
e3c678e6
SG
740 if (ret < 0)
741 netdev_warn(dev->net, "device_set_wakeup_enable error %d\n", ret);
351f33d9 742
e3c678e6 743 return ret;
6c636503
SG
744}
745
d0cad871
SG
746static const struct ethtool_ops smsc75xx_ethtool_ops = {
747 .get_link = usbnet_get_link,
748 .nway_reset = usbnet_nway_reset,
749 .get_drvinfo = usbnet_get_drvinfo,
750 .get_msglevel = usbnet_get_msglevel,
751 .set_msglevel = usbnet_set_msglevel,
d0cad871
SG
752 .get_eeprom_len = smsc75xx_ethtool_get_eeprom_len,
753 .get_eeprom = smsc75xx_ethtool_get_eeprom,
754 .set_eeprom = smsc75xx_ethtool_set_eeprom,
6c636503
SG
755 .get_wol = smsc75xx_ethtool_get_wol,
756 .set_wol = smsc75xx_ethtool_set_wol,
a44017a5
PR
757 .get_link_ksettings = usbnet_get_link_ksettings,
758 .set_link_ksettings = usbnet_set_link_ksettings,
d0cad871
SG
759};
760
761static int smsc75xx_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
762{
763 struct usbnet *dev = netdev_priv(netdev);
764
765 if (!netif_running(netdev))
766 return -EINVAL;
767
768 return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
769}
770
771static void smsc75xx_init_mac_address(struct usbnet *dev)
772{
c489565b
AB
773 const u8 *mac_addr;
774
775 /* maybe the boot loader passed the MAC address in devicetree */
776 mac_addr = of_get_mac_address(dev->udev->dev.of_node);
777 if (mac_addr) {
778 memcpy(dev->net->dev_addr, mac_addr, ETH_ALEN);
779 return;
780 }
781
d0cad871
SG
782 /* try reading mac address from EEPROM */
783 if (smsc75xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN,
784 dev->net->dev_addr) == 0) {
785 if (is_valid_ether_addr(dev->net->dev_addr)) {
786 /* eeprom values are valid so use them */
787 netif_dbg(dev, ifup, dev->net,
1e1d7412 788 "MAC address read from EEPROM\n");
d0cad871
SG
789 return;
790 }
791 }
792
c489565b 793 /* no useful static MAC address found. generate a random one */
f2cedb63 794 eth_hw_addr_random(dev->net);
1e1d7412 795 netif_dbg(dev, ifup, dev->net, "MAC address set to eth_random_addr\n");
d0cad871
SG
796}
797
798static int smsc75xx_set_mac_address(struct usbnet *dev)
799{
800 u32 addr_lo = dev->net->dev_addr[0] | dev->net->dev_addr[1] << 8 |
801 dev->net->dev_addr[2] << 16 | dev->net->dev_addr[3] << 24;
802 u32 addr_hi = dev->net->dev_addr[4] | dev->net->dev_addr[5] << 8;
803
804 int ret = smsc75xx_write_reg(dev, RX_ADDRH, addr_hi);
e3c678e6
SG
805 if (ret < 0) {
806 netdev_warn(dev->net, "Failed to write RX_ADDRH: %d\n", ret);
807 return ret;
808 }
d0cad871
SG
809
810 ret = smsc75xx_write_reg(dev, RX_ADDRL, addr_lo);
e3c678e6
SG
811 if (ret < 0) {
812 netdev_warn(dev->net, "Failed to write RX_ADDRL: %d\n", ret);
813 return ret;
814 }
d0cad871
SG
815
816 addr_hi |= ADDR_FILTX_FB_VALID;
817 ret = smsc75xx_write_reg(dev, ADDR_FILTX, addr_hi);
e3c678e6
SG
818 if (ret < 0) {
819 netdev_warn(dev->net, "Failed to write ADDR_FILTX: %d\n", ret);
820 return ret;
821 }
d0cad871
SG
822
823 ret = smsc75xx_write_reg(dev, ADDR_FILTX + 4, addr_lo);
e3c678e6
SG
824 if (ret < 0)
825 netdev_warn(dev->net, "Failed to write ADDR_FILTX+4: %d\n", ret);
d0cad871 826
e3c678e6 827 return ret;
d0cad871
SG
828}
829
830static int smsc75xx_phy_initialize(struct usbnet *dev)
831{
b140504a 832 int bmcr, ret, timeout = 0;
d0cad871
SG
833
834 /* Initialize MII structure */
835 dev->mii.dev = dev->net;
836 dev->mii.mdio_read = smsc75xx_mdio_read;
837 dev->mii.mdio_write = smsc75xx_mdio_write;
838 dev->mii.phy_id_mask = 0x1f;
839 dev->mii.reg_num_mask = 0x1f;
c0b92e4d 840 dev->mii.supports_gmii = 1;
d0cad871
SG
841 dev->mii.phy_id = SMSC75XX_INTERNAL_PHY_ID;
842
843 /* reset phy and wait for reset to complete */
844 smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
845
846 do {
847 msleep(10);
848 bmcr = smsc75xx_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR);
e3c678e6
SG
849 if (bmcr < 0) {
850 netdev_warn(dev->net, "Error reading MII_BMCR\n");
851 return bmcr;
852 }
d0cad871 853 timeout++;
8a1d59d7 854 } while ((bmcr & BMCR_RESET) && (timeout < 100));
d0cad871
SG
855
856 if (timeout >= 100) {
1e1d7412 857 netdev_warn(dev->net, "timeout on PHY Reset\n");
d0cad871
SG
858 return -EIO;
859 }
860
1dd973c2
YO
861 /* phy workaround for gig link */
862 smsc75xx_phy_gig_workaround(dev);
863
d0cad871
SG
864 smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
865 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP |
866 ADVERTISE_PAUSE_ASYM);
c0b92e4d
SG
867 smsc75xx_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,
868 ADVERTISE_1000FULL);
d0cad871 869
b140504a
SG
870 /* read and write to clear phy interrupt status */
871 ret = smsc75xx_mdio_read(dev->net, dev->mii.phy_id, PHY_INT_SRC);
e3c678e6
SG
872 if (ret < 0) {
873 netdev_warn(dev->net, "Error reading PHY_INT_SRC\n");
874 return ret;
875 }
876
b140504a 877 smsc75xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_SRC, 0xffff);
d0cad871
SG
878
879 smsc75xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_MASK,
880 PHY_INT_MASK_DEFAULT);
881 mii_nway_restart(&dev->mii);
882
1e1d7412 883 netif_dbg(dev, ifup, dev->net, "phy initialised successfully\n");
d0cad871
SG
884 return 0;
885}
886
887static int smsc75xx_set_rx_max_frame_length(struct usbnet *dev, int size)
888{
889 int ret = 0;
890 u32 buf;
891 bool rxenabled;
892
893 ret = smsc75xx_read_reg(dev, MAC_RX, &buf);
e3c678e6
SG
894 if (ret < 0) {
895 netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
896 return ret;
897 }
d0cad871
SG
898
899 rxenabled = ((buf & MAC_RX_RXEN) != 0);
900
901 if (rxenabled) {
902 buf &= ~MAC_RX_RXEN;
903 ret = smsc75xx_write_reg(dev, MAC_RX, buf);
e3c678e6
SG
904 if (ret < 0) {
905 netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
906 return ret;
907 }
d0cad871
SG
908 }
909
910 /* add 4 to size for FCS */
911 buf &= ~MAC_RX_MAX_SIZE;
912 buf |= (((size + 4) << MAC_RX_MAX_SIZE_SHIFT) & MAC_RX_MAX_SIZE);
913
914 ret = smsc75xx_write_reg(dev, MAC_RX, buf);
e3c678e6
SG
915 if (ret < 0) {
916 netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
917 return ret;
918 }
d0cad871
SG
919
920 if (rxenabled) {
921 buf |= MAC_RX_RXEN;
922 ret = smsc75xx_write_reg(dev, MAC_RX, buf);
e3c678e6
SG
923 if (ret < 0) {
924 netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
925 return ret;
926 }
d0cad871
SG
927 }
928
929 return 0;
930}
931
932static int smsc75xx_change_mtu(struct net_device *netdev, int new_mtu)
933{
934 struct usbnet *dev = netdev_priv(netdev);
4c51e536
SG
935 int ret;
936
4c51e536 937 ret = smsc75xx_set_rx_max_frame_length(dev, new_mtu + ETH_HLEN);
e3c678e6
SG
938 if (ret < 0) {
939 netdev_warn(dev->net, "Failed to set mac rx frame length\n");
940 return ret;
941 }
d0cad871
SG
942
943 return usbnet_change_mtu(netdev, new_mtu);
944}
945
78e47fe4 946/* Enable or disable Rx checksum offload engine */
c8f44aff
MM
947static int smsc75xx_set_features(struct net_device *netdev,
948 netdev_features_t features)
78e47fe4
MM
949{
950 struct usbnet *dev = netdev_priv(netdev);
951 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
952 unsigned long flags;
953 int ret;
954
955 spin_lock_irqsave(&pdata->rfe_ctl_lock, flags);
956
957 if (features & NETIF_F_RXCSUM)
958 pdata->rfe_ctl |= RFE_CTL_TCPUDP_CKM | RFE_CTL_IP_CKM;
959 else
960 pdata->rfe_ctl &= ~(RFE_CTL_TCPUDP_CKM | RFE_CTL_IP_CKM);
961
962 spin_unlock_irqrestore(&pdata->rfe_ctl_lock, flags);
963 /* it's racing here! */
964
965 ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
17a64e30 966 if (ret < 0) {
e3c678e6 967 netdev_warn(dev->net, "Error writing RFE_CTL\n");
17a64e30
ED
968 return ret;
969 }
970 return 0;
78e47fe4
MM
971}
972
47bbea41 973static int smsc75xx_wait_ready(struct usbnet *dev, int in_pm)
8762cec8
SG
974{
975 int timeout = 0;
976
977 do {
978 u32 buf;
47bbea41
ML
979 int ret;
980
981 ret = __smsc75xx_read_reg(dev, PMT_CTL, &buf, in_pm);
982
e3c678e6
SG
983 if (ret < 0) {
984 netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
985 return ret;
986 }
8762cec8
SG
987
988 if (buf & PMT_CTL_DEV_RDY)
989 return 0;
990
991 msleep(10);
992 timeout++;
993 } while (timeout < 100);
994
1e1d7412 995 netdev_warn(dev->net, "timeout waiting for device ready\n");
8762cec8
SG
996 return -EIO;
997}
998
1dd973c2
YO
999static int smsc75xx_phy_gig_workaround(struct usbnet *dev)
1000{
1001 struct mii_if_info *mii = &dev->mii;
1002 int ret = 0, timeout = 0;
1003 u32 buf, link_up = 0;
1004
1005 /* Set the phy in Gig loopback */
1006 smsc75xx_mdio_write(dev->net, mii->phy_id, MII_BMCR, 0x4040);
1007
1008 /* Wait for the link up */
1009 do {
1010 link_up = smsc75xx_link_ok_nopm(dev);
1011 usleep_range(10000, 20000);
1012 timeout++;
1013 } while ((!link_up) && (timeout < 1000));
1014
1015 if (timeout >= 1000) {
1016 netdev_warn(dev->net, "Timeout waiting for PHY link up\n");
1017 return -EIO;
1018 }
1019
1020 /* phy reset */
1021 ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
1022 if (ret < 0) {
1023 netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
1024 return ret;
1025 }
1026
1027 buf |= PMT_CTL_PHY_RST;
1028
1029 ret = smsc75xx_write_reg(dev, PMT_CTL, buf);
1030 if (ret < 0) {
1031 netdev_warn(dev->net, "Failed to write PMT_CTL: %d\n", ret);
1032 return ret;
1033 }
1034
1035 timeout = 0;
1036 do {
1037 usleep_range(10000, 20000);
1038 ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
1039 if (ret < 0) {
1040 netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n",
1041 ret);
1042 return ret;
1043 }
1044 timeout++;
1045 } while ((buf & PMT_CTL_PHY_RST) && (timeout < 100));
1046
1047 if (timeout >= 100) {
1048 netdev_warn(dev->net, "timeout waiting for PHY Reset\n");
1049 return -EIO;
1050 }
1051
1052 return 0;
1053}
1054
d0cad871
SG
1055static int smsc75xx_reset(struct usbnet *dev)
1056{
1057 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
1058 u32 buf;
1059 int ret = 0, timeout;
1060
1e1d7412 1061 netif_dbg(dev, ifup, dev->net, "entering smsc75xx_reset\n");
d0cad871 1062
47bbea41 1063 ret = smsc75xx_wait_ready(dev, 0);
e3c678e6
SG
1064 if (ret < 0) {
1065 netdev_warn(dev->net, "device not ready in smsc75xx_reset\n");
1066 return ret;
1067 }
8762cec8 1068
d0cad871 1069 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
e3c678e6
SG
1070 if (ret < 0) {
1071 netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
1072 return ret;
1073 }
d0cad871
SG
1074
1075 buf |= HW_CFG_LRST;
1076
1077 ret = smsc75xx_write_reg(dev, HW_CFG, buf);
e3c678e6
SG
1078 if (ret < 0) {
1079 netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
1080 return ret;
1081 }
d0cad871
SG
1082
1083 timeout = 0;
1084 do {
1085 msleep(10);
1086 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
e3c678e6
SG
1087 if (ret < 0) {
1088 netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
1089 return ret;
1090 }
d0cad871
SG
1091 timeout++;
1092 } while ((buf & HW_CFG_LRST) && (timeout < 100));
1093
1094 if (timeout >= 100) {
1e1d7412 1095 netdev_warn(dev->net, "timeout on completion of Lite Reset\n");
d0cad871
SG
1096 return -EIO;
1097 }
1098
1e1d7412 1099 netif_dbg(dev, ifup, dev->net, "Lite reset complete, resetting PHY\n");
d0cad871
SG
1100
1101 ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
e3c678e6
SG
1102 if (ret < 0) {
1103 netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
1104 return ret;
1105 }
d0cad871
SG
1106
1107 buf |= PMT_CTL_PHY_RST;
1108
1109 ret = smsc75xx_write_reg(dev, PMT_CTL, buf);
e3c678e6
SG
1110 if (ret < 0) {
1111 netdev_warn(dev->net, "Failed to write PMT_CTL: %d\n", ret);
1112 return ret;
1113 }
d0cad871
SG
1114
1115 timeout = 0;
1116 do {
1117 msleep(10);
1118 ret = smsc75xx_read_reg(dev, PMT_CTL, &buf);
e3c678e6
SG
1119 if (ret < 0) {
1120 netdev_warn(dev->net, "Failed to read PMT_CTL: %d\n", ret);
1121 return ret;
1122 }
d0cad871
SG
1123 timeout++;
1124 } while ((buf & PMT_CTL_PHY_RST) && (timeout < 100));
1125
1126 if (timeout >= 100) {
1e1d7412 1127 netdev_warn(dev->net, "timeout waiting for PHY Reset\n");
d0cad871
SG
1128 return -EIO;
1129 }
1130
1e1d7412 1131 netif_dbg(dev, ifup, dev->net, "PHY reset complete\n");
d0cad871 1132
d0cad871 1133 ret = smsc75xx_set_mac_address(dev);
e3c678e6
SG
1134 if (ret < 0) {
1135 netdev_warn(dev->net, "Failed to set mac address\n");
1136 return ret;
1137 }
d0cad871 1138
1e1d7412
JP
1139 netif_dbg(dev, ifup, dev->net, "MAC Address: %pM\n",
1140 dev->net->dev_addr);
d0cad871
SG
1141
1142 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
e3c678e6
SG
1143 if (ret < 0) {
1144 netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
1145 return ret;
1146 }
d0cad871 1147
1e1d7412
JP
1148 netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG : 0x%08x\n",
1149 buf);
d0cad871
SG
1150
1151 buf |= HW_CFG_BIR;
1152
1153 ret = smsc75xx_write_reg(dev, HW_CFG, buf);
e3c678e6
SG
1154 if (ret < 0) {
1155 netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
1156 return ret;
1157 }
d0cad871
SG
1158
1159 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
e3c678e6
SG
1160 if (ret < 0) {
1161 netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
1162 return ret;
1163 }
d0cad871 1164
1e1d7412
JP
1165 netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG after writing HW_CFG_BIR: 0x%08x\n",
1166 buf);
d0cad871
SG
1167
1168 if (!turbo_mode) {
1169 buf = 0;
1170 dev->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
1171 } else if (dev->udev->speed == USB_SPEED_HIGH) {
1172 buf = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
1173 dev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
1174 } else {
1175 buf = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
1176 dev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
1177 }
1178
1e1d7412
JP
1179 netif_dbg(dev, ifup, dev->net, "rx_urb_size=%ld\n",
1180 (ulong)dev->rx_urb_size);
d0cad871
SG
1181
1182 ret = smsc75xx_write_reg(dev, BURST_CAP, buf);
e3c678e6
SG
1183 if (ret < 0) {
1184 netdev_warn(dev->net, "Failed to write BURST_CAP: %d\n", ret);
1185 return ret;
1186 }
d0cad871
SG
1187
1188 ret = smsc75xx_read_reg(dev, BURST_CAP, &buf);
e3c678e6
SG
1189 if (ret < 0) {
1190 netdev_warn(dev->net, "Failed to read BURST_CAP: %d\n", ret);
1191 return ret;
1192 }
d0cad871
SG
1193
1194 netif_dbg(dev, ifup, dev->net,
1e1d7412 1195 "Read Value from BURST_CAP after writing: 0x%08x\n", buf);
d0cad871
SG
1196
1197 ret = smsc75xx_write_reg(dev, BULK_IN_DLY, DEFAULT_BULK_IN_DELAY);
e3c678e6
SG
1198 if (ret < 0) {
1199 netdev_warn(dev->net, "Failed to write BULK_IN_DLY: %d\n", ret);
1200 return ret;
1201 }
d0cad871
SG
1202
1203 ret = smsc75xx_read_reg(dev, BULK_IN_DLY, &buf);
e3c678e6
SG
1204 if (ret < 0) {
1205 netdev_warn(dev->net, "Failed to read BULK_IN_DLY: %d\n", ret);
1206 return ret;
1207 }
d0cad871
SG
1208
1209 netif_dbg(dev, ifup, dev->net,
1e1d7412 1210 "Read Value from BULK_IN_DLY after writing: 0x%08x\n", buf);
d0cad871
SG
1211
1212 if (turbo_mode) {
1213 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
e3c678e6
SG
1214 if (ret < 0) {
1215 netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
1216 return ret;
1217 }
d0cad871 1218
1e1d7412 1219 netif_dbg(dev, ifup, dev->net, "HW_CFG: 0x%08x\n", buf);
d0cad871
SG
1220
1221 buf |= (HW_CFG_MEF | HW_CFG_BCE);
1222
1223 ret = smsc75xx_write_reg(dev, HW_CFG, buf);
e3c678e6
SG
1224 if (ret < 0) {
1225 netdev_warn(dev->net, "Failed to write HW_CFG: %d\n", ret);
1226 return ret;
1227 }
d0cad871
SG
1228
1229 ret = smsc75xx_read_reg(dev, HW_CFG, &buf);
e3c678e6
SG
1230 if (ret < 0) {
1231 netdev_warn(dev->net, "Failed to read HW_CFG: %d\n", ret);
1232 return ret;
1233 }
d0cad871 1234
1e1d7412 1235 netif_dbg(dev, ifup, dev->net, "HW_CFG: 0x%08x\n", buf);
d0cad871
SG
1236 }
1237
1238 /* set FIFO sizes */
1239 buf = (MAX_RX_FIFO_SIZE - 512) / 512;
1240 ret = smsc75xx_write_reg(dev, FCT_RX_FIFO_END, buf);
e3c678e6
SG
1241 if (ret < 0) {
1242 netdev_warn(dev->net, "Failed to write FCT_RX_FIFO_END: %d\n", ret);
1243 return ret;
1244 }
d0cad871 1245
1e1d7412 1246 netif_dbg(dev, ifup, dev->net, "FCT_RX_FIFO_END set to 0x%08x\n", buf);
d0cad871
SG
1247
1248 buf = (MAX_TX_FIFO_SIZE - 512) / 512;
1249 ret = smsc75xx_write_reg(dev, FCT_TX_FIFO_END, buf);
e3c678e6
SG
1250 if (ret < 0) {
1251 netdev_warn(dev->net, "Failed to write FCT_TX_FIFO_END: %d\n", ret);
1252 return ret;
1253 }
d0cad871 1254
1e1d7412 1255 netif_dbg(dev, ifup, dev->net, "FCT_TX_FIFO_END set to 0x%08x\n", buf);
d0cad871
SG
1256
1257 ret = smsc75xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL);
e3c678e6
SG
1258 if (ret < 0) {
1259 netdev_warn(dev->net, "Failed to write INT_STS: %d\n", ret);
1260 return ret;
1261 }
d0cad871
SG
1262
1263 ret = smsc75xx_read_reg(dev, ID_REV, &buf);
e3c678e6
SG
1264 if (ret < 0) {
1265 netdev_warn(dev->net, "Failed to read ID_REV: %d\n", ret);
1266 return ret;
1267 }
d0cad871 1268
1e1d7412 1269 netif_dbg(dev, ifup, dev->net, "ID_REV = 0x%08x\n", buf);
d0cad871 1270
97138a1c 1271 ret = smsc75xx_read_reg(dev, E2P_CMD, &buf);
e3c678e6
SG
1272 if (ret < 0) {
1273 netdev_warn(dev->net, "Failed to read E2P_CMD: %d\n", ret);
1274 return ret;
1275 }
d0cad871 1276
97138a1c
SG
1277 /* only set default GPIO/LED settings if no EEPROM is detected */
1278 if (!(buf & E2P_CMD_LOADED)) {
1279 ret = smsc75xx_read_reg(dev, LED_GPIO_CFG, &buf);
e3c678e6
SG
1280 if (ret < 0) {
1281 netdev_warn(dev->net, "Failed to read LED_GPIO_CFG: %d\n", ret);
1282 return ret;
1283 }
d0cad871 1284
97138a1c
SG
1285 buf &= ~(LED_GPIO_CFG_LED2_FUN_SEL | LED_GPIO_CFG_LED10_FUN_SEL);
1286 buf |= LED_GPIO_CFG_LEDGPIO_EN | LED_GPIO_CFG_LED2_FUN_SEL;
1287
1288 ret = smsc75xx_write_reg(dev, LED_GPIO_CFG, buf);
e3c678e6
SG
1289 if (ret < 0) {
1290 netdev_warn(dev->net, "Failed to write LED_GPIO_CFG: %d\n", ret);
1291 return ret;
1292 }
97138a1c 1293 }
d0cad871
SG
1294
1295 ret = smsc75xx_write_reg(dev, FLOW, 0);
e3c678e6
SG
1296 if (ret < 0) {
1297 netdev_warn(dev->net, "Failed to write FLOW: %d\n", ret);
1298 return ret;
1299 }
d0cad871
SG
1300
1301 ret = smsc75xx_write_reg(dev, FCT_FLOW, 0);
e3c678e6
SG
1302 if (ret < 0) {
1303 netdev_warn(dev->net, "Failed to write FCT_FLOW: %d\n", ret);
1304 return ret;
1305 }
d0cad871
SG
1306
1307 /* Don't need rfe_ctl_lock during initialisation */
1308 ret = smsc75xx_read_reg(dev, RFE_CTL, &pdata->rfe_ctl);
e3c678e6
SG
1309 if (ret < 0) {
1310 netdev_warn(dev->net, "Failed to read RFE_CTL: %d\n", ret);
1311 return ret;
1312 }
d0cad871
SG
1313
1314 pdata->rfe_ctl |= RFE_CTL_AB | RFE_CTL_DPF;
1315
1316 ret = smsc75xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
e3c678e6
SG
1317 if (ret < 0) {
1318 netdev_warn(dev->net, "Failed to write RFE_CTL: %d\n", ret);
1319 return ret;
1320 }
d0cad871
SG
1321
1322 ret = smsc75xx_read_reg(dev, RFE_CTL, &pdata->rfe_ctl);
e3c678e6
SG
1323 if (ret < 0) {
1324 netdev_warn(dev->net, "Failed to read RFE_CTL: %d\n", ret);
1325 return ret;
1326 }
d0cad871 1327
1e1d7412
JP
1328 netif_dbg(dev, ifup, dev->net, "RFE_CTL set to 0x%08x\n",
1329 pdata->rfe_ctl);
d0cad871
SG
1330
1331 /* Enable or disable checksum offload engines */
78e47fe4 1332 smsc75xx_set_features(dev->net, dev->net->features);
d0cad871
SG
1333
1334 smsc75xx_set_multicast(dev->net);
1335
1336 ret = smsc75xx_phy_initialize(dev);
e3c678e6
SG
1337 if (ret < 0) {
1338 netdev_warn(dev->net, "Failed to initialize PHY: %d\n", ret);
1339 return ret;
1340 }
d0cad871
SG
1341
1342 ret = smsc75xx_read_reg(dev, INT_EP_CTL, &buf);
e3c678e6
SG
1343 if (ret < 0) {
1344 netdev_warn(dev->net, "Failed to read INT_EP_CTL: %d\n", ret);
1345 return ret;
1346 }
d0cad871
SG
1347
1348 /* enable PHY interrupts */
1349 buf |= INT_ENP_PHY_INT;
1350
1351 ret = smsc75xx_write_reg(dev, INT_EP_CTL, buf);
e3c678e6
SG
1352 if (ret < 0) {
1353 netdev_warn(dev->net, "Failed to write INT_EP_CTL: %d\n", ret);
1354 return ret;
1355 }
d0cad871 1356
2f3a081e
SG
1357 /* allow mac to detect speed and duplex from phy */
1358 ret = smsc75xx_read_reg(dev, MAC_CR, &buf);
e3c678e6
SG
1359 if (ret < 0) {
1360 netdev_warn(dev->net, "Failed to read MAC_CR: %d\n", ret);
1361 return ret;
1362 }
2f3a081e
SG
1363
1364 buf |= (MAC_CR_ADD | MAC_CR_ASD);
1365 ret = smsc75xx_write_reg(dev, MAC_CR, buf);
e3c678e6
SG
1366 if (ret < 0) {
1367 netdev_warn(dev->net, "Failed to write MAC_CR: %d\n", ret);
1368 return ret;
1369 }
2f3a081e 1370
d0cad871 1371 ret = smsc75xx_read_reg(dev, MAC_TX, &buf);
e3c678e6
SG
1372 if (ret < 0) {
1373 netdev_warn(dev->net, "Failed to read MAC_TX: %d\n", ret);
1374 return ret;
1375 }
d0cad871
SG
1376
1377 buf |= MAC_TX_TXEN;
1378
1379 ret = smsc75xx_write_reg(dev, MAC_TX, buf);
e3c678e6
SG
1380 if (ret < 0) {
1381 netdev_warn(dev->net, "Failed to write MAC_TX: %d\n", ret);
1382 return ret;
1383 }
d0cad871 1384
1e1d7412 1385 netif_dbg(dev, ifup, dev->net, "MAC_TX set to 0x%08x\n", buf);
d0cad871
SG
1386
1387 ret = smsc75xx_read_reg(dev, FCT_TX_CTL, &buf);
e3c678e6
SG
1388 if (ret < 0) {
1389 netdev_warn(dev->net, "Failed to read FCT_TX_CTL: %d\n", ret);
1390 return ret;
1391 }
d0cad871
SG
1392
1393 buf |= FCT_TX_CTL_EN;
1394
1395 ret = smsc75xx_write_reg(dev, FCT_TX_CTL, buf);
e3c678e6
SG
1396 if (ret < 0) {
1397 netdev_warn(dev->net, "Failed to write FCT_TX_CTL: %d\n", ret);
1398 return ret;
1399 }
d0cad871 1400
1e1d7412 1401 netif_dbg(dev, ifup, dev->net, "FCT_TX_CTL set to 0x%08x\n", buf);
d0cad871 1402
4c51e536 1403 ret = smsc75xx_set_rx_max_frame_length(dev, dev->net->mtu + ETH_HLEN);
e3c678e6
SG
1404 if (ret < 0) {
1405 netdev_warn(dev->net, "Failed to set max rx frame length\n");
1406 return ret;
1407 }
d0cad871
SG
1408
1409 ret = smsc75xx_read_reg(dev, MAC_RX, &buf);
e3c678e6
SG
1410 if (ret < 0) {
1411 netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
1412 return ret;
1413 }
d0cad871
SG
1414
1415 buf |= MAC_RX_RXEN;
1416
1417 ret = smsc75xx_write_reg(dev, MAC_RX, buf);
e3c678e6
SG
1418 if (ret < 0) {
1419 netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
1420 return ret;
1421 }
d0cad871 1422
1e1d7412 1423 netif_dbg(dev, ifup, dev->net, "MAC_RX set to 0x%08x\n", buf);
d0cad871
SG
1424
1425 ret = smsc75xx_read_reg(dev, FCT_RX_CTL, &buf);
e3c678e6
SG
1426 if (ret < 0) {
1427 netdev_warn(dev->net, "Failed to read FCT_RX_CTL: %d\n", ret);
1428 return ret;
1429 }
d0cad871
SG
1430
1431 buf |= FCT_RX_CTL_EN;
1432
1433 ret = smsc75xx_write_reg(dev, FCT_RX_CTL, buf);
e3c678e6
SG
1434 if (ret < 0) {
1435 netdev_warn(dev->net, "Failed to write FCT_RX_CTL: %d\n", ret);
1436 return ret;
1437 }
d0cad871 1438
1e1d7412 1439 netif_dbg(dev, ifup, dev->net, "FCT_RX_CTL set to 0x%08x\n", buf);
d0cad871 1440
1e1d7412 1441 netif_dbg(dev, ifup, dev->net, "smsc75xx_reset, return 0\n");
d0cad871
SG
1442 return 0;
1443}
1444
1445static const struct net_device_ops smsc75xx_netdev_ops = {
1446 .ndo_open = usbnet_open,
1447 .ndo_stop = usbnet_stop,
1448 .ndo_start_xmit = usbnet_start_xmit,
1449 .ndo_tx_timeout = usbnet_tx_timeout,
c8b5d129 1450 .ndo_get_stats64 = usbnet_get_stats64,
d0cad871
SG
1451 .ndo_change_mtu = smsc75xx_change_mtu,
1452 .ndo_set_mac_address = eth_mac_addr,
1453 .ndo_validate_addr = eth_validate_addr,
1454 .ndo_do_ioctl = smsc75xx_ioctl,
afc4b13d 1455 .ndo_set_rx_mode = smsc75xx_set_multicast,
78e47fe4 1456 .ndo_set_features = smsc75xx_set_features,
d0cad871
SG
1457};
1458
1459static int smsc75xx_bind(struct usbnet *dev, struct usb_interface *intf)
1460{
1461 struct smsc75xx_priv *pdata = NULL;
1462 int ret;
1463
1464 printk(KERN_INFO SMSC_CHIPNAME " v" SMSC_DRIVER_VERSION "\n");
1465
1466 ret = usbnet_get_endpoints(dev, intf);
e3c678e6
SG
1467 if (ret < 0) {
1468 netdev_warn(dev->net, "usbnet_get_endpoints failed: %d\n", ret);
1469 return ret;
1470 }
d0cad871
SG
1471
1472 dev->data[0] = (unsigned long)kzalloc(sizeof(struct smsc75xx_priv),
38673c82 1473 GFP_KERNEL);
d0cad871
SG
1474
1475 pdata = (struct smsc75xx_priv *)(dev->data[0]);
38673c82 1476 if (!pdata)
d0cad871 1477 return -ENOMEM;
d0cad871
SG
1478
1479 pdata->dev = dev;
1480
1481 spin_lock_init(&pdata->rfe_ctl_lock);
1482 mutex_init(&pdata->dataport_mutex);
1483
1484 INIT_WORK(&pdata->set_multicast, smsc75xx_deferred_multicast_write);
1485
20f01703 1486 if (DEFAULT_TX_CSUM_ENABLE)
78e47fe4 1487 dev->net->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
20f01703 1488
78e47fe4
MM
1489 if (DEFAULT_RX_CSUM_ENABLE)
1490 dev->net->features |= NETIF_F_RXCSUM;
d0cad871 1491
78e47fe4 1492 dev->net->hw_features = NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
20f01703 1493 NETIF_F_RXCSUM;
d0cad871 1494
481705a1
SG
1495 ret = smsc75xx_wait_ready(dev, 0);
1496 if (ret < 0) {
1497 netdev_warn(dev->net, "device not ready in smsc75xx_bind\n");
1498 return ret;
1499 }
1500
1501 smsc75xx_init_mac_address(dev);
1502
d0cad871
SG
1503 /* Init all registers */
1504 ret = smsc75xx_reset(dev);
e3c678e6
SG
1505 if (ret < 0) {
1506 netdev_warn(dev->net, "smsc75xx_reset error %d\n", ret);
1507 return ret;
1508 }
d0cad871
SG
1509
1510 dev->net->netdev_ops = &smsc75xx_netdev_ops;
1511 dev->net->ethtool_ops = &smsc75xx_ethtool_ops;
1512 dev->net->flags |= IFF_MULTICAST;
1513 dev->net->hard_header_len += SMSC75XX_TX_OVERHEAD;
a99ff7d0 1514 dev->hard_mtu = dev->net->mtu + dev->net->hard_header_len;
f77f0aee 1515 dev->net->max_mtu = MAX_SINGLE_PACKET_SIZE;
d0cad871
SG
1516 return 0;
1517}
1518
1519static void smsc75xx_unbind(struct usbnet *dev, struct usb_interface *intf)
1520{
1521 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
1522 if (pdata) {
1a6f6c26 1523 cancel_work_sync(&pdata->set_multicast);
1e1d7412 1524 netif_dbg(dev, ifdown, dev->net, "free pdata\n");
d0cad871
SG
1525 kfree(pdata);
1526 pdata = NULL;
1527 dev->data[0] = 0;
1528 }
1529}
1530
899a391b
SG
1531static u16 smsc_crc(const u8 *buffer, size_t len)
1532{
1533 return bitrev16(crc16(0xFFFF, buffer, len));
1534}
1535
1536static int smsc75xx_write_wuff(struct usbnet *dev, int filter, u32 wuf_cfg,
1537 u32 wuf_mask1)
1538{
1539 int cfg_base = WUF_CFGX + filter * 4;
1540 int mask_base = WUF_MASKX + filter * 16;
1541 int ret;
1542
1543 ret = smsc75xx_write_reg(dev, cfg_base, wuf_cfg);
e3c678e6
SG
1544 if (ret < 0) {
1545 netdev_warn(dev->net, "Error writing WUF_CFGX\n");
1546 return ret;
1547 }
899a391b
SG
1548
1549 ret = smsc75xx_write_reg(dev, mask_base, wuf_mask1);
e3c678e6
SG
1550 if (ret < 0) {
1551 netdev_warn(dev->net, "Error writing WUF_MASKX\n");
1552 return ret;
1553 }
899a391b
SG
1554
1555 ret = smsc75xx_write_reg(dev, mask_base + 4, 0);
e3c678e6
SG
1556 if (ret < 0) {
1557 netdev_warn(dev->net, "Error writing WUF_MASKX\n");
1558 return ret;
1559 }
899a391b
SG
1560
1561 ret = smsc75xx_write_reg(dev, mask_base + 8, 0);
e3c678e6
SG
1562 if (ret < 0) {
1563 netdev_warn(dev->net, "Error writing WUF_MASKX\n");
1564 return ret;
1565 }
899a391b
SG
1566
1567 ret = smsc75xx_write_reg(dev, mask_base + 12, 0);
e3c678e6
SG
1568 if (ret < 0) {
1569 netdev_warn(dev->net, "Error writing WUF_MASKX\n");
1570 return ret;
1571 }
899a391b
SG
1572
1573 return 0;
1574}
1575
9deb2757
SG
1576static int smsc75xx_enter_suspend0(struct usbnet *dev)
1577{
b4cdea9c 1578 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
9deb2757
SG
1579 u32 val;
1580 int ret;
1581
1582 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
e3c678e6
SG
1583 if (ret < 0) {
1584 netdev_warn(dev->net, "Error reading PMT_CTL\n");
1585 return ret;
1586 }
9deb2757
SG
1587
1588 val &= (~(PMT_CTL_SUS_MODE | PMT_CTL_PHY_RST));
1589 val |= PMT_CTL_SUS_MODE_0 | PMT_CTL_WOL_EN | PMT_CTL_WUPS;
1590
1591 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
e3c678e6
SG
1592 if (ret < 0) {
1593 netdev_warn(dev->net, "Error writing PMT_CTL\n");
1594 return ret;
1595 }
9deb2757 1596
351f33d9 1597 pdata->suspend_flags |= SUSPEND_SUSPEND0;
b4cdea9c 1598
9deb2757
SG
1599 return 0;
1600}
1601
f329ccdc
SG
1602static int smsc75xx_enter_suspend1(struct usbnet *dev)
1603{
b4cdea9c 1604 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
f329ccdc
SG
1605 u32 val;
1606 int ret;
1607
1608 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
e3c678e6
SG
1609 if (ret < 0) {
1610 netdev_warn(dev->net, "Error reading PMT_CTL\n");
1611 return ret;
1612 }
f329ccdc
SG
1613
1614 val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
1615 val |= PMT_CTL_SUS_MODE_1;
1616
1617 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
e3c678e6
SG
1618 if (ret < 0) {
1619 netdev_warn(dev->net, "Error writing PMT_CTL\n");
1620 return ret;
1621 }
f329ccdc
SG
1622
1623 /* clear wol status, enable energy detection */
1624 val &= ~PMT_CTL_WUPS;
1625 val |= (PMT_CTL_WUPS_ED | PMT_CTL_ED_EN);
1626
1627 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
e3c678e6
SG
1628 if (ret < 0) {
1629 netdev_warn(dev->net, "Error writing PMT_CTL\n");
1630 return ret;
1631 }
f329ccdc 1632
351f33d9 1633 pdata->suspend_flags |= SUSPEND_SUSPEND1;
b4cdea9c 1634
f329ccdc
SG
1635 return 0;
1636}
1637
9deb2757
SG
1638static int smsc75xx_enter_suspend2(struct usbnet *dev)
1639{
b4cdea9c 1640 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
9deb2757
SG
1641 u32 val;
1642 int ret;
1643
1644 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
e3c678e6
SG
1645 if (ret < 0) {
1646 netdev_warn(dev->net, "Error reading PMT_CTL\n");
1647 return ret;
1648 }
9deb2757
SG
1649
1650 val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
1651 val |= PMT_CTL_SUS_MODE_2;
1652
1653 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
e3c678e6
SG
1654 if (ret < 0) {
1655 netdev_warn(dev->net, "Error writing PMT_CTL\n");
1656 return ret;
1657 }
9deb2757 1658
b4cdea9c
SG
1659 pdata->suspend_flags |= SUSPEND_SUSPEND2;
1660
1661 return 0;
1662}
1663
1664static int smsc75xx_enter_suspend3(struct usbnet *dev)
1665{
1666 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
1667 u32 val;
1668 int ret;
1669
1670 ret = smsc75xx_read_reg_nopm(dev, FCT_RX_CTL, &val);
e3c678e6
SG
1671 if (ret < 0) {
1672 netdev_warn(dev->net, "Error reading FCT_RX_CTL\n");
1673 return ret;
1674 }
b4cdea9c
SG
1675
1676 if (val & FCT_RX_CTL_RXUSED) {
1677 netdev_dbg(dev->net, "rx fifo not empty in autosuspend\n");
1678 return -EBUSY;
1679 }
1680
1681 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
e3c678e6
SG
1682 if (ret < 0) {
1683 netdev_warn(dev->net, "Error reading PMT_CTL\n");
1684 return ret;
1685 }
b4cdea9c
SG
1686
1687 val &= ~(PMT_CTL_SUS_MODE | PMT_CTL_WUPS | PMT_CTL_PHY_RST);
1688 val |= PMT_CTL_SUS_MODE_3 | PMT_CTL_RES_CLR_WKP_EN;
1689
1690 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
e3c678e6
SG
1691 if (ret < 0) {
1692 netdev_warn(dev->net, "Error writing PMT_CTL\n");
1693 return ret;
1694 }
b4cdea9c
SG
1695
1696 /* clear wol status */
1697 val &= ~PMT_CTL_WUPS;
1698 val |= PMT_CTL_WUPS_WOL;
1699
1700 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
e3c678e6
SG
1701 if (ret < 0) {
1702 netdev_warn(dev->net, "Error writing PMT_CTL\n");
1703 return ret;
1704 }
b4cdea9c 1705
351f33d9 1706 pdata->suspend_flags |= SUSPEND_SUSPEND3;
b4cdea9c 1707
9deb2757
SG
1708 return 0;
1709}
1710
f329ccdc
SG
1711static int smsc75xx_enable_phy_wakeup_interrupts(struct usbnet *dev, u16 mask)
1712{
1713 struct mii_if_info *mii = &dev->mii;
1714 int ret;
1715
1716 netdev_dbg(dev->net, "enabling PHY wakeup interrupts\n");
1717
1718 /* read to clear */
1719 ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_SRC);
e3c678e6
SG
1720 if (ret < 0) {
1721 netdev_warn(dev->net, "Error reading PHY_INT_SRC\n");
1722 return ret;
1723 }
f329ccdc
SG
1724
1725 /* enable interrupt source */
1726 ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_MASK);
e3c678e6
SG
1727 if (ret < 0) {
1728 netdev_warn(dev->net, "Error reading PHY_INT_MASK\n");
1729 return ret;
1730 }
f329ccdc
SG
1731
1732 ret |= mask;
1733
1734 smsc75xx_mdio_write_nopm(dev->net, mii->phy_id, PHY_INT_MASK, ret);
1735
1736 return 0;
1737}
1738
1739static int smsc75xx_link_ok_nopm(struct usbnet *dev)
1740{
1741 struct mii_if_info *mii = &dev->mii;
1742 int ret;
1743
1744 /* first, a dummy read, needed to latch some MII phys */
1745 ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR);
e3c678e6
SG
1746 if (ret < 0) {
1747 netdev_warn(dev->net, "Error reading MII_BMSR\n");
1748 return ret;
1749 }
f329ccdc
SG
1750
1751 ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR);
e3c678e6
SG
1752 if (ret < 0) {
1753 netdev_warn(dev->net, "Error reading MII_BMSR\n");
1754 return ret;
1755 }
f329ccdc
SG
1756
1757 return !!(ret & BMSR_LSTATUS);
1758}
1759
b4cdea9c
SG
1760static int smsc75xx_autosuspend(struct usbnet *dev, u32 link_up)
1761{
1762 int ret;
1763
1764 if (!netif_running(dev->net)) {
1765 /* interface is ifconfig down so fully power down hw */
1766 netdev_dbg(dev->net, "autosuspend entering SUSPEND2\n");
1767 return smsc75xx_enter_suspend2(dev);
1768 }
1769
1770 if (!link_up) {
1771 /* link is down so enter EDPD mode */
1772 netdev_dbg(dev->net, "autosuspend entering SUSPEND1\n");
1773
1774 /* enable PHY wakeup events for if cable is attached */
1775 ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
1776 PHY_INT_MASK_ANEG_COMP);
e3c678e6
SG
1777 if (ret < 0) {
1778 netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
1779 return ret;
1780 }
b4cdea9c
SG
1781
1782 netdev_info(dev->net, "entering SUSPEND1 mode\n");
1783 return smsc75xx_enter_suspend1(dev);
1784 }
1785
1786 /* enable PHY wakeup events so we remote wakeup if cable is pulled */
1787 ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
1788 PHY_INT_MASK_LINK_DOWN);
e3c678e6
SG
1789 if (ret < 0) {
1790 netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
1791 return ret;
1792 }
b4cdea9c
SG
1793
1794 netdev_dbg(dev->net, "autosuspend entering SUSPEND3\n");
1795 return smsc75xx_enter_suspend3(dev);
1796}
1797
16c79a04
SG
1798static int smsc75xx_suspend(struct usb_interface *intf, pm_message_t message)
1799{
1800 struct usbnet *dev = usb_get_intfdata(intf);
6c636503 1801 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
f329ccdc 1802 u32 val, link_up;
16c79a04 1803 int ret;
16c79a04 1804
16c79a04 1805 ret = usbnet_suspend(intf, message);
e3c678e6
SG
1806 if (ret < 0) {
1807 netdev_warn(dev->net, "usbnet_suspend error\n");
1808 return ret;
1809 }
16c79a04 1810
b4cdea9c
SG
1811 if (pdata->suspend_flags) {
1812 netdev_warn(dev->net, "error during last resume\n");
1813 pdata->suspend_flags = 0;
1814 }
1815
f329ccdc
SG
1816 /* determine if link is up using only _nopm functions */
1817 link_up = smsc75xx_link_ok_nopm(dev);
1818
b4cdea9c
SG
1819 if (message.event == PM_EVENT_AUTO_SUSPEND) {
1820 ret = smsc75xx_autosuspend(dev, link_up);
1821 goto done;
1822 }
1823
1824 /* if we get this far we're not autosuspending */
f329ccdc
SG
1825 /* if no wol options set, or if link is down and we're not waking on
1826 * PHY activity, enter lowest power SUSPEND2 mode
1827 */
1828 if (!(pdata->wolopts & SUPPORTED_WAKE) ||
1829 !(link_up || (pdata->wolopts & WAKE_PHY))) {
1e1d7412 1830 netdev_info(dev->net, "entering SUSPEND2 mode\n");
6c636503
SG
1831
1832 /* disable energy detect (link up) & wake up events */
47bbea41 1833 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
e3c678e6
SG
1834 if (ret < 0) {
1835 netdev_warn(dev->net, "Error reading WUCSR\n");
1836 goto done;
1837 }
6c636503
SG
1838
1839 val &= ~(WUCSR_MPEN | WUCSR_WUEN);
1840
47bbea41 1841 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
e3c678e6
SG
1842 if (ret < 0) {
1843 netdev_warn(dev->net, "Error writing WUCSR\n");
1844 goto done;
1845 }
6c636503 1846
47bbea41 1847 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
e3c678e6
SG
1848 if (ret < 0) {
1849 netdev_warn(dev->net, "Error reading PMT_CTL\n");
1850 goto done;
1851 }
6c636503
SG
1852
1853 val &= ~(PMT_CTL_ED_EN | PMT_CTL_WOL_EN);
1854
47bbea41 1855 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
e3c678e6
SG
1856 if (ret < 0) {
1857 netdev_warn(dev->net, "Error writing PMT_CTL\n");
1858 goto done;
1859 }
6c636503 1860
eacdd6c2
SG
1861 ret = smsc75xx_enter_suspend2(dev);
1862 goto done;
6c636503
SG
1863 }
1864
f329ccdc
SG
1865 if (pdata->wolopts & WAKE_PHY) {
1866 ret = smsc75xx_enable_phy_wakeup_interrupts(dev,
1867 (PHY_INT_MASK_ANEG_COMP | PHY_INT_MASK_LINK_DOWN));
e3c678e6
SG
1868 if (ret < 0) {
1869 netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
1870 goto done;
1871 }
f329ccdc
SG
1872
1873 /* if link is down then configure EDPD and enter SUSPEND1,
1874 * otherwise enter SUSPEND0 below
1875 */
1876 if (!link_up) {
1877 struct mii_if_info *mii = &dev->mii;
1878 netdev_info(dev->net, "entering SUSPEND1 mode\n");
1879
1880 /* enable energy detect power-down mode */
1881 ret = smsc75xx_mdio_read_nopm(dev->net, mii->phy_id,
1882 PHY_MODE_CTRL_STS);
e3c678e6
SG
1883 if (ret < 0) {
1884 netdev_warn(dev->net, "Error reading PHY_MODE_CTRL_STS\n");
1885 goto done;
1886 }
f329ccdc
SG
1887
1888 ret |= MODE_CTRL_STS_EDPWRDOWN;
1889
1890 smsc75xx_mdio_write_nopm(dev->net, mii->phy_id,
1891 PHY_MODE_CTRL_STS, ret);
1892
1893 /* enter SUSPEND1 mode */
eacdd6c2
SG
1894 ret = smsc75xx_enter_suspend1(dev);
1895 goto done;
f329ccdc
SG
1896 }
1897 }
1898
899a391b
SG
1899 if (pdata->wolopts & (WAKE_MCAST | WAKE_ARP)) {
1900 int i, filter = 0;
1901
1902 /* disable all filters */
1903 for (i = 0; i < WUF_NUM; i++) {
47bbea41 1904 ret = smsc75xx_write_reg_nopm(dev, WUF_CFGX + i * 4, 0);
e3c678e6
SG
1905 if (ret < 0) {
1906 netdev_warn(dev->net, "Error writing WUF_CFGX\n");
1907 goto done;
1908 }
899a391b
SG
1909 }
1910
1911 if (pdata->wolopts & WAKE_MCAST) {
1912 const u8 mcast[] = {0x01, 0x00, 0x5E};
1e1d7412 1913 netdev_info(dev->net, "enabling multicast detection\n");
899a391b
SG
1914
1915 val = WUF_CFGX_EN | WUF_CFGX_ATYPE_MULTICAST
1916 | smsc_crc(mcast, 3);
1917 ret = smsc75xx_write_wuff(dev, filter++, val, 0x0007);
e3c678e6
SG
1918 if (ret < 0) {
1919 netdev_warn(dev->net, "Error writing wakeup filter\n");
1920 goto done;
1921 }
899a391b
SG
1922 }
1923
1924 if (pdata->wolopts & WAKE_ARP) {
1925 const u8 arp[] = {0x08, 0x06};
1e1d7412 1926 netdev_info(dev->net, "enabling ARP detection\n");
899a391b
SG
1927
1928 val = WUF_CFGX_EN | WUF_CFGX_ATYPE_ALL | (0x0C << 16)
1929 | smsc_crc(arp, 2);
1930 ret = smsc75xx_write_wuff(dev, filter++, val, 0x0003);
e3c678e6
SG
1931 if (ret < 0) {
1932 netdev_warn(dev->net, "Error writing wakeup filter\n");
1933 goto done;
1934 }
899a391b
SG
1935 }
1936
1937 /* clear any pending pattern match packet status */
47bbea41 1938 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
e3c678e6
SG
1939 if (ret < 0) {
1940 netdev_warn(dev->net, "Error reading WUCSR\n");
1941 goto done;
1942 }
899a391b
SG
1943
1944 val |= WUCSR_WUFR;
1945
47bbea41 1946 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
e3c678e6
SG
1947 if (ret < 0) {
1948 netdev_warn(dev->net, "Error writing WUCSR\n");
1949 goto done;
1950 }
899a391b 1951
1e1d7412 1952 netdev_info(dev->net, "enabling packet match detection\n");
47bbea41 1953 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
e3c678e6
SG
1954 if (ret < 0) {
1955 netdev_warn(dev->net, "Error reading WUCSR\n");
1956 goto done;
1957 }
899a391b
SG
1958
1959 val |= WUCSR_WUEN;
1960
47bbea41 1961 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
e3c678e6
SG
1962 if (ret < 0) {
1963 netdev_warn(dev->net, "Error writing WUCSR\n");
1964 goto done;
1965 }
899a391b 1966 } else {
1e1d7412 1967 netdev_info(dev->net, "disabling packet match detection\n");
47bbea41 1968 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
e3c678e6
SG
1969 if (ret < 0) {
1970 netdev_warn(dev->net, "Error reading WUCSR\n");
1971 goto done;
1972 }
6c636503 1973
899a391b 1974 val &= ~WUCSR_WUEN;
16c79a04 1975
47bbea41 1976 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
e3c678e6
SG
1977 if (ret < 0) {
1978 netdev_warn(dev->net, "Error writing WUCSR\n");
1979 goto done;
1980 }
6c636503
SG
1981 }
1982
899a391b 1983 /* disable magic, bcast & unicast wakeup sources */
47bbea41 1984 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
e3c678e6
SG
1985 if (ret < 0) {
1986 netdev_warn(dev->net, "Error reading WUCSR\n");
1987 goto done;
1988 }
6c636503 1989
899a391b
SG
1990 val &= ~(WUCSR_MPEN | WUCSR_BCST_EN | WUCSR_PFDA_EN);
1991
47bbea41 1992 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
e3c678e6
SG
1993 if (ret < 0) {
1994 netdev_warn(dev->net, "Error writing WUCSR\n");
1995 goto done;
1996 }
899a391b 1997
f329ccdc
SG
1998 if (pdata->wolopts & WAKE_PHY) {
1999 netdev_info(dev->net, "enabling PHY wakeup\n");
2000
2001 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
e3c678e6
SG
2002 if (ret < 0) {
2003 netdev_warn(dev->net, "Error reading PMT_CTL\n");
2004 goto done;
2005 }
f329ccdc
SG
2006
2007 /* clear wol status, enable energy detection */
2008 val &= ~PMT_CTL_WUPS;
2009 val |= (PMT_CTL_WUPS_ED | PMT_CTL_ED_EN);
2010
2011 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
e3c678e6
SG
2012 if (ret < 0) {
2013 netdev_warn(dev->net, "Error writing PMT_CTL\n");
2014 goto done;
2015 }
f329ccdc
SG
2016 }
2017
6c636503 2018 if (pdata->wolopts & WAKE_MAGIC) {
1e1d7412 2019 netdev_info(dev->net, "enabling magic packet wakeup\n");
47bbea41 2020 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
e3c678e6
SG
2021 if (ret < 0) {
2022 netdev_warn(dev->net, "Error reading WUCSR\n");
2023 goto done;
2024 }
899a391b
SG
2025
2026 /* clear any pending magic packet status */
2027 val |= WUCSR_MPR | WUCSR_MPEN;
2028
47bbea41 2029 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
e3c678e6
SG
2030 if (ret < 0) {
2031 netdev_warn(dev->net, "Error writing WUCSR\n");
2032 goto done;
2033 }
6c636503
SG
2034 }
2035
899a391b 2036 if (pdata->wolopts & WAKE_BCAST) {
1e1d7412 2037 netdev_info(dev->net, "enabling broadcast detection\n");
47bbea41 2038 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
e3c678e6
SG
2039 if (ret < 0) {
2040 netdev_warn(dev->net, "Error reading WUCSR\n");
2041 goto done;
2042 }
6c636503 2043
899a391b 2044 val |= WUCSR_BCAST_FR | WUCSR_BCST_EN;
16c79a04 2045
47bbea41 2046 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
e3c678e6
SG
2047 if (ret < 0) {
2048 netdev_warn(dev->net, "Error writing WUCSR\n");
2049 goto done;
2050 }
899a391b 2051 }
6c636503 2052
899a391b 2053 if (pdata->wolopts & WAKE_UCAST) {
1e1d7412 2054 netdev_info(dev->net, "enabling unicast detection\n");
47bbea41 2055 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
e3c678e6
SG
2056 if (ret < 0) {
2057 netdev_warn(dev->net, "Error reading WUCSR\n");
2058 goto done;
2059 }
899a391b
SG
2060
2061 val |= WUCSR_WUFR | WUCSR_PFDA_EN;
6c636503 2062
47bbea41 2063 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
e3c678e6
SG
2064 if (ret < 0) {
2065 netdev_warn(dev->net, "Error writing WUCSR\n");
2066 goto done;
2067 }
899a391b
SG
2068 }
2069
2070 /* enable receiver to enable frame reception */
47bbea41 2071 ret = smsc75xx_read_reg_nopm(dev, MAC_RX, &val);
e3c678e6
SG
2072 if (ret < 0) {
2073 netdev_warn(dev->net, "Failed to read MAC_RX: %d\n", ret);
2074 goto done;
2075 }
6c636503
SG
2076
2077 val |= MAC_RX_RXEN;
2078
47bbea41 2079 ret = smsc75xx_write_reg_nopm(dev, MAC_RX, val);
e3c678e6
SG
2080 if (ret < 0) {
2081 netdev_warn(dev->net, "Failed to write MAC_RX: %d\n", ret);
2082 goto done;
2083 }
6c636503
SG
2084
2085 /* some wol options are enabled, so enter SUSPEND0 */
1e1d7412 2086 netdev_info(dev->net, "entering SUSPEND0 mode\n");
eacdd6c2
SG
2087 ret = smsc75xx_enter_suspend0(dev);
2088
2089done:
5410a473
ML
2090 /*
2091 * TODO: resume() might need to handle the suspend failure
2092 * in system sleep
2093 */
2094 if (ret && PMSG_IS_AUTO(message))
eacdd6c2
SG
2095 usbnet_resume(intf);
2096 return ret;
16c79a04
SG
2097}
2098
2099static int smsc75xx_resume(struct usb_interface *intf)
2100{
2101 struct usbnet *dev = usb_get_intfdata(intf);
6c636503 2102 struct smsc75xx_priv *pdata = (struct smsc75xx_priv *)(dev->data[0]);
b4cdea9c 2103 u8 suspend_flags = pdata->suspend_flags;
16c79a04
SG
2104 int ret;
2105 u32 val;
2106
b4cdea9c 2107 netdev_dbg(dev->net, "resume suspend_flags=0x%02x\n", suspend_flags);
16c79a04 2108
b4cdea9c
SG
2109 /* do this first to ensure it's cleared even in error case */
2110 pdata->suspend_flags = 0;
2111
b4cdea9c 2112 if (suspend_flags & SUSPEND_ALLMODES) {
899a391b 2113 /* Disable wakeup sources */
47bbea41 2114 ret = smsc75xx_read_reg_nopm(dev, WUCSR, &val);
e3c678e6
SG
2115 if (ret < 0) {
2116 netdev_warn(dev->net, "Error reading WUCSR\n");
2117 return ret;
2118 }
16c79a04 2119
899a391b
SG
2120 val &= ~(WUCSR_WUEN | WUCSR_MPEN | WUCSR_PFDA_EN
2121 | WUCSR_BCST_EN);
16c79a04 2122
47bbea41 2123 ret = smsc75xx_write_reg_nopm(dev, WUCSR, val);
e3c678e6
SG
2124 if (ret < 0) {
2125 netdev_warn(dev->net, "Error writing WUCSR\n");
2126 return ret;
2127 }
6c636503
SG
2128
2129 /* clear wake-up status */
47bbea41 2130 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
e3c678e6
SG
2131 if (ret < 0) {
2132 netdev_warn(dev->net, "Error reading PMT_CTL\n");
2133 return ret;
2134 }
6c636503
SG
2135
2136 val &= ~PMT_CTL_WOL_EN;
2137 val |= PMT_CTL_WUPS;
2138
47bbea41 2139 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
e3c678e6
SG
2140 if (ret < 0) {
2141 netdev_warn(dev->net, "Error writing PMT_CTL\n");
2142 return ret;
2143 }
b4cdea9c
SG
2144 }
2145
2146 if (suspend_flags & SUSPEND_SUSPEND2) {
1e1d7412 2147 netdev_info(dev->net, "resuming from SUSPEND2\n");
6c636503 2148
47bbea41 2149 ret = smsc75xx_read_reg_nopm(dev, PMT_CTL, &val);
e3c678e6
SG
2150 if (ret < 0) {
2151 netdev_warn(dev->net, "Error reading PMT_CTL\n");
2152 return ret;
2153 }
6c636503
SG
2154
2155 val |= PMT_CTL_PHY_PWRUP;
2156
47bbea41 2157 ret = smsc75xx_write_reg_nopm(dev, PMT_CTL, val);
e3c678e6
SG
2158 if (ret < 0) {
2159 netdev_warn(dev->net, "Error writing PMT_CTL\n");
2160 return ret;
2161 }
6c636503 2162 }
16c79a04 2163
47bbea41 2164 ret = smsc75xx_wait_ready(dev, 1);
e3c678e6
SG
2165 if (ret < 0) {
2166 netdev_warn(dev->net, "device not ready in smsc75xx_resume\n");
2167 return ret;
2168 }
16c79a04
SG
2169
2170 return usbnet_resume(intf);
2171}
2172
78e47fe4
MM
2173static void smsc75xx_rx_csum_offload(struct usbnet *dev, struct sk_buff *skb,
2174 u32 rx_cmd_a, u32 rx_cmd_b)
d0cad871 2175{
78e47fe4
MM
2176 if (!(dev->net->features & NETIF_F_RXCSUM) ||
2177 unlikely(rx_cmd_a & RX_CMD_A_LCSM)) {
d0cad871
SG
2178 skb->ip_summed = CHECKSUM_NONE;
2179 } else {
2180 skb->csum = ntohs((u16)(rx_cmd_b >> RX_CMD_B_CSUM_SHIFT));
2181 skb->ip_summed = CHECKSUM_COMPLETE;
2182 }
2183}
2184
2185static int smsc75xx_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
2186{
eb85569f
EG
2187 /* This check is no longer done by usbnet */
2188 if (skb->len < dev->net->hard_header_len)
2189 return 0;
2190
d0cad871
SG
2191 while (skb->len > 0) {
2192 u32 rx_cmd_a, rx_cmd_b, align_count, size;
2193 struct sk_buff *ax_skb;
2194 unsigned char *packet;
2195
2196 memcpy(&rx_cmd_a, skb->data, sizeof(rx_cmd_a));
2197 le32_to_cpus(&rx_cmd_a);
2198 skb_pull(skb, 4);
2199
2200 memcpy(&rx_cmd_b, skb->data, sizeof(rx_cmd_b));
2201 le32_to_cpus(&rx_cmd_b);
ea1649de 2202 skb_pull(skb, 4 + RXW_PADDING);
d0cad871
SG
2203
2204 packet = skb->data;
2205
2206 /* get the packet length */
ea1649de
NE
2207 size = (rx_cmd_a & RX_CMD_A_LEN) - RXW_PADDING;
2208 align_count = (4 - ((size + RXW_PADDING) % 4)) % 4;
d0cad871
SG
2209
2210 if (unlikely(rx_cmd_a & RX_CMD_A_RED)) {
2211 netif_dbg(dev, rx_err, dev->net,
1e1d7412 2212 "Error rx_cmd_a=0x%08x\n", rx_cmd_a);
d0cad871
SG
2213 dev->net->stats.rx_errors++;
2214 dev->net->stats.rx_dropped++;
2215
2216 if (rx_cmd_a & RX_CMD_A_FCS)
2217 dev->net->stats.rx_crc_errors++;
2218 else if (rx_cmd_a & (RX_CMD_A_LONG | RX_CMD_A_RUNT))
2219 dev->net->stats.rx_frame_errors++;
2220 } else {
4c51e536
SG
2221 /* MAX_SINGLE_PACKET_SIZE + 4(CRC) + 2(COE) + 4(Vlan) */
2222 if (unlikely(size > (MAX_SINGLE_PACKET_SIZE + ETH_HLEN + 12))) {
d0cad871 2223 netif_dbg(dev, rx_err, dev->net,
1e1d7412
JP
2224 "size err rx_cmd_a=0x%08x\n",
2225 rx_cmd_a);
d0cad871
SG
2226 return 0;
2227 }
2228
2229 /* last frame in this batch */
2230 if (skb->len == size) {
78e47fe4
MM
2231 smsc75xx_rx_csum_offload(dev, skb, rx_cmd_a,
2232 rx_cmd_b);
d0cad871
SG
2233
2234 skb_trim(skb, skb->len - 4); /* remove fcs */
2235 skb->truesize = size + sizeof(struct sk_buff);
2236
2237 return 1;
2238 }
2239
2240 ax_skb = skb_clone(skb, GFP_ATOMIC);
2241 if (unlikely(!ax_skb)) {
1e1d7412 2242 netdev_warn(dev->net, "Error allocating skb\n");
d0cad871
SG
2243 return 0;
2244 }
2245
2246 ax_skb->len = size;
2247 ax_skb->data = packet;
2248 skb_set_tail_pointer(ax_skb, size);
2249
78e47fe4
MM
2250 smsc75xx_rx_csum_offload(dev, ax_skb, rx_cmd_a,
2251 rx_cmd_b);
d0cad871
SG
2252
2253 skb_trim(ax_skb, ax_skb->len - 4); /* remove fcs */
2254 ax_skb->truesize = size + sizeof(struct sk_buff);
2255
2256 usbnet_skb_return(dev, ax_skb);
2257 }
2258
2259 skb_pull(skb, size);
2260
2261 /* padding bytes before the next frame starts */
2262 if (skb->len)
2263 skb_pull(skb, align_count);
2264 }
2265
d0cad871
SG
2266 return 1;
2267}
2268
2269static struct sk_buff *smsc75xx_tx_fixup(struct usbnet *dev,
2270 struct sk_buff *skb, gfp_t flags)
2271{
2272 u32 tx_cmd_a, tx_cmd_b;
2273
b7c6d267 2274 if (skb_cow_head(skb, SMSC75XX_TX_OVERHEAD)) {
d0cad871 2275 dev_kfree_skb_any(skb);
b7c6d267 2276 return NULL;
d0cad871
SG
2277 }
2278
2279 tx_cmd_a = (u32)(skb->len & TX_CMD_A_LEN) | TX_CMD_A_FCS;
2280
2281 if (skb->ip_summed == CHECKSUM_PARTIAL)
2282 tx_cmd_a |= TX_CMD_A_IPE | TX_CMD_A_TPE;
2283
2284 if (skb_is_gso(skb)) {
2285 u16 mss = max(skb_shinfo(skb)->gso_size, TX_MSS_MIN);
2286 tx_cmd_b = (mss << TX_CMD_B_MSS_SHIFT) & TX_CMD_B_MSS;
2287
2288 tx_cmd_a |= TX_CMD_A_LSO;
2289 } else {
2290 tx_cmd_b = 0;
2291 }
2292
2293 skb_push(skb, 4);
2294 cpu_to_le32s(&tx_cmd_b);
2295 memcpy(skb->data, &tx_cmd_b, 4);
2296
2297 skb_push(skb, 4);
2298 cpu_to_le32s(&tx_cmd_a);
2299 memcpy(skb->data, &tx_cmd_a, 4);
2300
2301 return skb;
2302}
2303
b4cdea9c
SG
2304static int smsc75xx_manage_power(struct usbnet *dev, int on)
2305{
2306 dev->intf->needs_remote_wakeup = on;
2307 return 0;
2308}
2309
d0cad871
SG
2310static const struct driver_info smsc75xx_info = {
2311 .description = "smsc75xx USB 2.0 Gigabit Ethernet",
2312 .bind = smsc75xx_bind,
2313 .unbind = smsc75xx_unbind,
2314 .link_reset = smsc75xx_link_reset,
2315 .reset = smsc75xx_reset,
2316 .rx_fixup = smsc75xx_rx_fixup,
2317 .tx_fixup = smsc75xx_tx_fixup,
2318 .status = smsc75xx_status,
b4cdea9c 2319 .manage_power = smsc75xx_manage_power,
7bdd305e 2320 .flags = FLAG_ETHER | FLAG_SEND_ZLP | FLAG_LINK_INTR,
d0cad871
SG
2321};
2322
2323static const struct usb_device_id products[] = {
2324 {
2325 /* SMSC7500 USB Gigabit Ethernet Device */
2326 USB_DEVICE(USB_VENDOR_ID_SMSC, USB_PRODUCT_ID_LAN7500),
2327 .driver_info = (unsigned long) &smsc75xx_info,
2328 },
2329 {
2330 /* SMSC7500 USB Gigabit Ethernet Device */
2331 USB_DEVICE(USB_VENDOR_ID_SMSC, USB_PRODUCT_ID_LAN7505),
2332 .driver_info = (unsigned long) &smsc75xx_info,
2333 },
2334 { }, /* END */
2335};
2336MODULE_DEVICE_TABLE(usb, products);
2337
2338static struct usb_driver smsc75xx_driver = {
2339 .name = SMSC_CHIPNAME,
2340 .id_table = products,
2341 .probe = usbnet_probe,
16c79a04
SG
2342 .suspend = smsc75xx_suspend,
2343 .resume = smsc75xx_resume,
2344 .reset_resume = smsc75xx_resume,
d0cad871 2345 .disconnect = usbnet_disconnect,
e1f12eb6 2346 .disable_hub_initiated_lpm = 1,
b4cdea9c 2347 .supports_autosuspend = 1,
d0cad871
SG
2348};
2349
d632eb1b 2350module_usb_driver(smsc75xx_driver);
d0cad871
SG
2351
2352MODULE_AUTHOR("Nancy Lin");
90b24cfb 2353MODULE_AUTHOR("Steve Glendinning <steve.glendinning@shawell.net>");
d0cad871
SG
2354MODULE_DESCRIPTION("SMSC75XX USB 2.0 Gigabit Ethernet Devices");
2355MODULE_LICENSE("GPL");