]> git.proxmox.com Git - mirror_ubuntu-eoan-kernel.git/blame - drivers/net/usb/smsc95xx.c
smsc95xx: fix suspend buffer overflow
[mirror_ubuntu-eoan-kernel.git] / drivers / net / usb / smsc95xx.c
CommitLineData
2f7ca802
SG
1 /***************************************************************************
2 *
3 * Copyright (C) 2007-2008 SMSC
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 *
19 *****************************************************************************/
20
21#include <linux/module.h>
22#include <linux/kmod.h>
23#include <linux/init.h>
24#include <linux/netdevice.h>
25#include <linux/etherdevice.h>
26#include <linux/ethtool.h>
27#include <linux/mii.h>
28#include <linux/usb.h>
bbd9f9ee
SG
29#include <linux/bitrev.h>
30#include <linux/crc16.h>
2f7ca802
SG
31#include <linux/crc32.h>
32#include <linux/usb/usbnet.h>
5a0e3ad6 33#include <linux/slab.h>
2f7ca802
SG
34#include "smsc95xx.h"
35
36#define SMSC_CHIPNAME "smsc95xx"
f7b29271 37#define SMSC_DRIVER_VERSION "1.0.4"
2f7ca802
SG
38#define HS_USB_PKT_SIZE (512)
39#define FS_USB_PKT_SIZE (64)
40#define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE)
41#define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE)
42#define DEFAULT_BULK_IN_DELAY (0x00002000)
43#define MAX_SINGLE_PACKET_SIZE (2048)
44#define LAN95XX_EEPROM_MAGIC (0x9500)
45#define EEPROM_MAC_OFFSET (0x01)
f7b29271 46#define DEFAULT_TX_CSUM_ENABLE (true)
2f7ca802
SG
47#define DEFAULT_RX_CSUM_ENABLE (true)
48#define SMSC95XX_INTERNAL_PHY_ID (1)
49#define SMSC95XX_TX_OVERHEAD (8)
f7b29271 50#define SMSC95XX_TX_OVERHEAD_CSUM (12)
e5e3af83 51#define SUPPORTED_WAKE (WAKE_PHY | WAKE_UCAST | WAKE_BCAST | \
bbd9f9ee 52 WAKE_MCAST | WAKE_ARP | WAKE_MAGIC)
2f7ca802 53
9ebca507
SG
54#define FEATURE_8_WAKEUP_FILTERS (0x01)
55#define FEATURE_PHY_NLP_CROSSOVER (0x02)
56#define FEATURE_AUTOSUSPEND (0x04)
57
769ea6d8
SG
58#define check_warn(ret, fmt, args...) \
59 ({ if (ret < 0) netdev_warn(dev->net, fmt, ##args); })
60
61#define check_warn_return(ret, fmt, args...) \
62 ({ if (ret < 0) { netdev_warn(dev->net, fmt, ##args); return ret; } })
63
64#define check_warn_goto_done(ret, fmt, args...) \
65 ({ if (ret < 0) { netdev_warn(dev->net, fmt, ##args); goto done; } })
66
2f7ca802
SG
67struct smsc95xx_priv {
68 u32 mac_cr;
3c0f3c60
MZ
69 u32 hash_hi;
70 u32 hash_lo;
e0e474a8 71 u32 wolopts;
2f7ca802 72 spinlock_t mac_cr_lock;
9ebca507 73 u8 features;
2f7ca802
SG
74};
75
eb939922 76static bool turbo_mode = true;
2f7ca802
SG
77module_param(turbo_mode, bool, 0644);
78MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction");
79
ec32115d
ML
80static int __must_check __smsc95xx_read_reg(struct usbnet *dev, u32 index,
81 u32 *data, int in_pm)
2f7ca802 82{
72108fd2 83 u32 buf;
2f7ca802 84 int ret;
ec32115d 85 int (*fn)(struct usbnet *, u8, u8, u16, u16, void *, u16);
2f7ca802
SG
86
87 BUG_ON(!dev);
88
ec32115d
ML
89 if (!in_pm)
90 fn = usbnet_read_cmd;
91 else
92 fn = usbnet_read_cmd_nopm;
93
94 ret = fn(dev, USB_VENDOR_REQUEST_READ_REGISTER, USB_DIR_IN
95 | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
96 0, index, &buf, 4);
2f7ca802 97 if (unlikely(ret < 0))
1e1d7412
JP
98 netdev_warn(dev->net, "Failed to read reg index 0x%08x: %d\n",
99 index, ret);
2f7ca802 100
72108fd2
ML
101 le32_to_cpus(&buf);
102 *data = buf;
2f7ca802
SG
103
104 return ret;
105}
106
ec32115d
ML
107static int __must_check __smsc95xx_write_reg(struct usbnet *dev, u32 index,
108 u32 data, int in_pm)
2f7ca802 109{
72108fd2 110 u32 buf;
2f7ca802 111 int ret;
ec32115d 112 int (*fn)(struct usbnet *, u8, u8, u16, u16, const void *, u16);
2f7ca802
SG
113
114 BUG_ON(!dev);
115
ec32115d
ML
116 if (!in_pm)
117 fn = usbnet_write_cmd;
118 else
119 fn = usbnet_write_cmd_nopm;
120
72108fd2
ML
121 buf = data;
122 cpu_to_le32s(&buf);
2f7ca802 123
ec32115d
ML
124 ret = fn(dev, USB_VENDOR_REQUEST_WRITE_REGISTER, USB_DIR_OUT
125 | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
126 0, index, &buf, 4);
2f7ca802 127 if (unlikely(ret < 0))
1e1d7412
JP
128 netdev_warn(dev->net, "Failed to write reg index 0x%08x: %d\n",
129 index, ret);
2f7ca802 130
2f7ca802
SG
131 return ret;
132}
133
ec32115d
ML
134static int __must_check smsc95xx_read_reg_nopm(struct usbnet *dev, u32 index,
135 u32 *data)
136{
137 return __smsc95xx_read_reg(dev, index, data, 1);
138}
139
140static int __must_check smsc95xx_write_reg_nopm(struct usbnet *dev, u32 index,
141 u32 data)
142{
143 return __smsc95xx_write_reg(dev, index, data, 1);
144}
145
146static int __must_check smsc95xx_read_reg(struct usbnet *dev, u32 index,
147 u32 *data)
148{
149 return __smsc95xx_read_reg(dev, index, data, 0);
150}
151
152static int __must_check smsc95xx_write_reg(struct usbnet *dev, u32 index,
153 u32 data)
154{
155 return __smsc95xx_write_reg(dev, index, data, 0);
156}
e0e474a8
SG
157static int smsc95xx_set_feature(struct usbnet *dev, u32 feature)
158{
159 if (WARN_ON_ONCE(!dev))
160 return -EINVAL;
161
ec32115d
ML
162 return usbnet_write_cmd_nopm(dev, USB_REQ_SET_FEATURE,
163 USB_RECIP_DEVICE, feature, 0,
164 NULL, 0);
e0e474a8
SG
165}
166
167static int smsc95xx_clear_feature(struct usbnet *dev, u32 feature)
168{
169 if (WARN_ON_ONCE(!dev))
170 return -EINVAL;
171
ec32115d
ML
172 return usbnet_write_cmd_nopm(dev, USB_REQ_CLEAR_FEATURE,
173 USB_RECIP_DEVICE, feature,
174 0, NULL, 0);
e0e474a8
SG
175}
176
2f7ca802
SG
177/* Loop until the read is completed with timeout
178 * called with phy_mutex held */
e5e3af83
SG
179static int __must_check __smsc95xx_phy_wait_not_busy(struct usbnet *dev,
180 int in_pm)
2f7ca802
SG
181{
182 unsigned long start_time = jiffies;
183 u32 val;
769ea6d8 184 int ret;
2f7ca802
SG
185
186 do {
e5e3af83 187 ret = __smsc95xx_read_reg(dev, MII_ADDR, &val, in_pm);
1e1d7412 188 check_warn_return(ret, "Error reading MII_ACCESS\n");
2f7ca802
SG
189 if (!(val & MII_BUSY_))
190 return 0;
191 } while (!time_after(jiffies, start_time + HZ));
192
193 return -EIO;
194}
195
e5e3af83
SG
196static int __smsc95xx_mdio_read(struct net_device *netdev, int phy_id, int idx,
197 int in_pm)
2f7ca802
SG
198{
199 struct usbnet *dev = netdev_priv(netdev);
200 u32 val, addr;
769ea6d8 201 int ret;
2f7ca802
SG
202
203 mutex_lock(&dev->phy_mutex);
204
205 /* confirm MII not busy */
e5e3af83 206 ret = __smsc95xx_phy_wait_not_busy(dev, in_pm);
1e1d7412 207 check_warn_goto_done(ret, "MII is busy in smsc95xx_mdio_read\n");
2f7ca802
SG
208
209 /* set the address, index & direction (read from PHY) */
210 phy_id &= dev->mii.phy_id_mask;
211 idx &= dev->mii.reg_num_mask;
80928805 212 addr = (phy_id << 11) | (idx << 6) | MII_READ_ | MII_BUSY_;
e5e3af83 213 ret = __smsc95xx_write_reg(dev, MII_ADDR, addr, in_pm);
1e1d7412 214 check_warn_goto_done(ret, "Error writing MII_ADDR\n");
2f7ca802 215
e5e3af83 216 ret = __smsc95xx_phy_wait_not_busy(dev, in_pm);
1e1d7412 217 check_warn_goto_done(ret, "Timed out reading MII reg %02X\n", idx);
2f7ca802 218
e5e3af83 219 ret = __smsc95xx_read_reg(dev, MII_DATA, &val, in_pm);
1e1d7412 220 check_warn_goto_done(ret, "Error reading MII_DATA\n");
2f7ca802 221
769ea6d8 222 ret = (u16)(val & 0xFFFF);
2f7ca802 223
769ea6d8
SG
224done:
225 mutex_unlock(&dev->phy_mutex);
226 return ret;
2f7ca802
SG
227}
228
e5e3af83
SG
229static void __smsc95xx_mdio_write(struct net_device *netdev, int phy_id,
230 int idx, int regval, int in_pm)
2f7ca802
SG
231{
232 struct usbnet *dev = netdev_priv(netdev);
233 u32 val, addr;
769ea6d8 234 int ret;
2f7ca802
SG
235
236 mutex_lock(&dev->phy_mutex);
237
238 /* confirm MII not busy */
e5e3af83 239 ret = __smsc95xx_phy_wait_not_busy(dev, in_pm);
1e1d7412 240 check_warn_goto_done(ret, "MII is busy in smsc95xx_mdio_write\n");
2f7ca802
SG
241
242 val = regval;
e5e3af83 243 ret = __smsc95xx_write_reg(dev, MII_DATA, val, in_pm);
1e1d7412 244 check_warn_goto_done(ret, "Error writing MII_DATA\n");
2f7ca802
SG
245
246 /* set the address, index & direction (write to PHY) */
247 phy_id &= dev->mii.phy_id_mask;
248 idx &= dev->mii.reg_num_mask;
80928805 249 addr = (phy_id << 11) | (idx << 6) | MII_WRITE_ | MII_BUSY_;
e5e3af83 250 ret = __smsc95xx_write_reg(dev, MII_ADDR, addr, in_pm);
1e1d7412 251 check_warn_goto_done(ret, "Error writing MII_ADDR\n");
2f7ca802 252
e5e3af83 253 ret = __smsc95xx_phy_wait_not_busy(dev, in_pm);
1e1d7412 254 check_warn_goto_done(ret, "Timed out writing MII reg %02X\n", idx);
2f7ca802 255
769ea6d8 256done:
2f7ca802
SG
257 mutex_unlock(&dev->phy_mutex);
258}
259
e5e3af83
SG
260static int smsc95xx_mdio_read_nopm(struct net_device *netdev, int phy_id,
261 int idx)
262{
263 return __smsc95xx_mdio_read(netdev, phy_id, idx, 1);
264}
265
266static void smsc95xx_mdio_write_nopm(struct net_device *netdev, int phy_id,
267 int idx, int regval)
268{
269 __smsc95xx_mdio_write(netdev, phy_id, idx, regval, 1);
270}
271
272static int smsc95xx_mdio_read(struct net_device *netdev, int phy_id, int idx)
273{
274 return __smsc95xx_mdio_read(netdev, phy_id, idx, 0);
275}
276
277static void smsc95xx_mdio_write(struct net_device *netdev, int phy_id, int idx,
278 int regval)
279{
280 __smsc95xx_mdio_write(netdev, phy_id, idx, regval, 0);
281}
282
769ea6d8 283static int __must_check smsc95xx_wait_eeprom(struct usbnet *dev)
2f7ca802
SG
284{
285 unsigned long start_time = jiffies;
286 u32 val;
769ea6d8 287 int ret;
2f7ca802
SG
288
289 do {
769ea6d8 290 ret = smsc95xx_read_reg(dev, E2P_CMD, &val);
1e1d7412 291 check_warn_return(ret, "Error reading E2P_CMD\n");
2f7ca802
SG
292 if (!(val & E2P_CMD_BUSY_) || (val & E2P_CMD_TIMEOUT_))
293 break;
294 udelay(40);
295 } while (!time_after(jiffies, start_time + HZ));
296
297 if (val & (E2P_CMD_TIMEOUT_ | E2P_CMD_BUSY_)) {
60b86755 298 netdev_warn(dev->net, "EEPROM read operation timeout\n");
2f7ca802
SG
299 return -EIO;
300 }
301
302 return 0;
303}
304
769ea6d8 305static int __must_check smsc95xx_eeprom_confirm_not_busy(struct usbnet *dev)
2f7ca802
SG
306{
307 unsigned long start_time = jiffies;
308 u32 val;
769ea6d8 309 int ret;
2f7ca802
SG
310
311 do {
769ea6d8 312 ret = smsc95xx_read_reg(dev, E2P_CMD, &val);
1e1d7412 313 check_warn_return(ret, "Error reading E2P_CMD\n");
2f7ca802 314
2f7ca802
SG
315 if (!(val & E2P_CMD_BUSY_))
316 return 0;
317
318 udelay(40);
319 } while (!time_after(jiffies, start_time + HZ));
320
60b86755 321 netdev_warn(dev->net, "EEPROM is busy\n");
2f7ca802
SG
322 return -EIO;
323}
324
325static int smsc95xx_read_eeprom(struct usbnet *dev, u32 offset, u32 length,
326 u8 *data)
327{
328 u32 val;
329 int i, ret;
330
331 BUG_ON(!dev);
332 BUG_ON(!data);
333
334 ret = smsc95xx_eeprom_confirm_not_busy(dev);
335 if (ret)
336 return ret;
337
338 for (i = 0; i < length; i++) {
339 val = E2P_CMD_BUSY_ | E2P_CMD_READ_ | (offset & E2P_CMD_ADDR_);
769ea6d8 340 ret = smsc95xx_write_reg(dev, E2P_CMD, val);
1e1d7412 341 check_warn_return(ret, "Error writing E2P_CMD\n");
2f7ca802
SG
342
343 ret = smsc95xx_wait_eeprom(dev);
344 if (ret < 0)
345 return ret;
346
769ea6d8 347 ret = smsc95xx_read_reg(dev, E2P_DATA, &val);
1e1d7412 348 check_warn_return(ret, "Error reading E2P_DATA\n");
2f7ca802
SG
349
350 data[i] = val & 0xFF;
351 offset++;
352 }
353
354 return 0;
355}
356
357static int smsc95xx_write_eeprom(struct usbnet *dev, u32 offset, u32 length,
358 u8 *data)
359{
360 u32 val;
361 int i, ret;
362
363 BUG_ON(!dev);
364 BUG_ON(!data);
365
366 ret = smsc95xx_eeprom_confirm_not_busy(dev);
367 if (ret)
368 return ret;
369
370 /* Issue write/erase enable command */
371 val = E2P_CMD_BUSY_ | E2P_CMD_EWEN_;
769ea6d8 372 ret = smsc95xx_write_reg(dev, E2P_CMD, val);
1e1d7412 373 check_warn_return(ret, "Error writing E2P_DATA\n");
2f7ca802
SG
374
375 ret = smsc95xx_wait_eeprom(dev);
376 if (ret < 0)
377 return ret;
378
379 for (i = 0; i < length; i++) {
380
381 /* Fill data register */
382 val = data[i];
769ea6d8 383 ret = smsc95xx_write_reg(dev, E2P_DATA, val);
1e1d7412 384 check_warn_return(ret, "Error writing E2P_DATA\n");
2f7ca802
SG
385
386 /* Send "write" command */
387 val = E2P_CMD_BUSY_ | E2P_CMD_WRITE_ | (offset & E2P_CMD_ADDR_);
769ea6d8 388 ret = smsc95xx_write_reg(dev, E2P_CMD, val);
1e1d7412 389 check_warn_return(ret, "Error writing E2P_CMD\n");
2f7ca802
SG
390
391 ret = smsc95xx_wait_eeprom(dev);
392 if (ret < 0)
393 return ret;
394
395 offset++;
396 }
397
398 return 0;
399}
400
769ea6d8
SG
401static int __must_check smsc95xx_write_reg_async(struct usbnet *dev, u16 index,
402 u32 *data)
2f7ca802 403{
1d74a6bd 404 const u16 size = 4;
72108fd2 405 int ret;
2f7ca802 406
72108fd2
ML
407 ret = usbnet_write_cmd_async(dev, USB_VENDOR_REQUEST_WRITE_REGISTER,
408 USB_DIR_OUT | USB_TYPE_VENDOR |
409 USB_RECIP_DEVICE,
410 0, index, data, size);
411 if (ret < 0)
412 netdev_warn(dev->net, "Error write async cmd, sts=%d\n",
413 ret);
414 return ret;
2f7ca802
SG
415}
416
417/* returns hash bit number for given MAC address
418 * example:
419 * 01 00 5E 00 00 01 -> returns bit number 31 */
420static unsigned int smsc95xx_hash(char addr[ETH_ALEN])
421{
422 return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
423}
424
425static void smsc95xx_set_multicast(struct net_device *netdev)
426{
427 struct usbnet *dev = netdev_priv(netdev);
428 struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
2f7ca802 429 unsigned long flags;
769ea6d8 430 int ret;
2f7ca802 431
3c0f3c60
MZ
432 pdata->hash_hi = 0;
433 pdata->hash_lo = 0;
434
2f7ca802
SG
435 spin_lock_irqsave(&pdata->mac_cr_lock, flags);
436
437 if (dev->net->flags & IFF_PROMISC) {
a475f603 438 netif_dbg(dev, drv, dev->net, "promiscuous mode enabled\n");
2f7ca802
SG
439 pdata->mac_cr |= MAC_CR_PRMS_;
440 pdata->mac_cr &= ~(MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
441 } else if (dev->net->flags & IFF_ALLMULTI) {
a475f603 442 netif_dbg(dev, drv, dev->net, "receive all multicast enabled\n");
2f7ca802
SG
443 pdata->mac_cr |= MAC_CR_MCPAS_;
444 pdata->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_HPFILT_);
4cd24eaf 445 } else if (!netdev_mc_empty(dev->net)) {
22bedad3 446 struct netdev_hw_addr *ha;
2f7ca802
SG
447
448 pdata->mac_cr |= MAC_CR_HPFILT_;
449 pdata->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_);
450
22bedad3
JP
451 netdev_for_each_mc_addr(ha, netdev) {
452 u32 bitnum = smsc95xx_hash(ha->addr);
a92635dc
JP
453 u32 mask = 0x01 << (bitnum & 0x1F);
454 if (bitnum & 0x20)
3c0f3c60 455 pdata->hash_hi |= mask;
a92635dc 456 else
3c0f3c60 457 pdata->hash_lo |= mask;
2f7ca802
SG
458 }
459
a475f603 460 netif_dbg(dev, drv, dev->net, "HASHH=0x%08X, HASHL=0x%08X\n",
3c0f3c60 461 pdata->hash_hi, pdata->hash_lo);
2f7ca802 462 } else {
a475f603 463 netif_dbg(dev, drv, dev->net, "receive own packets only\n");
2f7ca802
SG
464 pdata->mac_cr &=
465 ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
466 }
467
468 spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
469
470 /* Initiate async writes, as we can't wait for completion here */
769ea6d8 471 ret = smsc95xx_write_reg_async(dev, HASHH, &pdata->hash_hi);
1e1d7412 472 check_warn(ret, "failed to initiate async write to HASHH\n");
769ea6d8
SG
473
474 ret = smsc95xx_write_reg_async(dev, HASHL, &pdata->hash_lo);
1e1d7412 475 check_warn(ret, "failed to initiate async write to HASHL\n");
769ea6d8
SG
476
477 ret = smsc95xx_write_reg_async(dev, MAC_CR, &pdata->mac_cr);
1e1d7412 478 check_warn(ret, "failed to initiate async write to MAC_CR\n");
2f7ca802
SG
479}
480
769ea6d8
SG
481static int smsc95xx_phy_update_flowcontrol(struct usbnet *dev, u8 duplex,
482 u16 lcladv, u16 rmtadv)
2f7ca802
SG
483{
484 u32 flow, afc_cfg = 0;
485
486 int ret = smsc95xx_read_reg(dev, AFC_CFG, &afc_cfg);
1e1d7412 487 check_warn_return(ret, "Error reading AFC_CFG\n");
2f7ca802
SG
488
489 if (duplex == DUPLEX_FULL) {
bc02ff95 490 u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
2f7ca802
SG
491
492 if (cap & FLOW_CTRL_RX)
493 flow = 0xFFFF0002;
494 else
495 flow = 0;
496
497 if (cap & FLOW_CTRL_TX)
498 afc_cfg |= 0xF;
499 else
500 afc_cfg &= ~0xF;
501
a475f603 502 netif_dbg(dev, link, dev->net, "rx pause %s, tx pause %s\n",
60b86755
JP
503 cap & FLOW_CTRL_RX ? "enabled" : "disabled",
504 cap & FLOW_CTRL_TX ? "enabled" : "disabled");
2f7ca802 505 } else {
a475f603 506 netif_dbg(dev, link, dev->net, "half duplex\n");
2f7ca802
SG
507 flow = 0;
508 afc_cfg |= 0xF;
509 }
510
769ea6d8 511 ret = smsc95xx_write_reg(dev, FLOW, flow);
1e1d7412 512 check_warn_return(ret, "Error writing FLOW\n");
769ea6d8
SG
513
514 ret = smsc95xx_write_reg(dev, AFC_CFG, afc_cfg);
1e1d7412 515 check_warn_return(ret, "Error writing AFC_CFG\n");
769ea6d8
SG
516
517 return 0;
2f7ca802
SG
518}
519
520static int smsc95xx_link_reset(struct usbnet *dev)
521{
522 struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
523 struct mii_if_info *mii = &dev->mii;
8ae6daca 524 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
2f7ca802
SG
525 unsigned long flags;
526 u16 lcladv, rmtadv;
769ea6d8 527 int ret;
2f7ca802
SG
528
529 /* clear interrupt status */
769ea6d8 530 ret = smsc95xx_mdio_read(dev->net, mii->phy_id, PHY_INT_SRC);
1e1d7412 531 check_warn_return(ret, "Error reading PHY_INT_SRC\n");
769ea6d8
SG
532
533 ret = smsc95xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL_);
1e1d7412 534 check_warn_return(ret, "Error writing INT_STS\n");
2f7ca802
SG
535
536 mii_check_media(mii, 1, 1);
537 mii_ethtool_gset(&dev->mii, &ecmd);
538 lcladv = smsc95xx_mdio_read(dev->net, mii->phy_id, MII_ADVERTISE);
539 rmtadv = smsc95xx_mdio_read(dev->net, mii->phy_id, MII_LPA);
540
8ae6daca
DD
541 netif_dbg(dev, link, dev->net,
542 "speed: %u duplex: %d lcladv: %04x rmtadv: %04x\n",
543 ethtool_cmd_speed(&ecmd), ecmd.duplex, lcladv, rmtadv);
2f7ca802
SG
544
545 spin_lock_irqsave(&pdata->mac_cr_lock, flags);
546 if (ecmd.duplex != DUPLEX_FULL) {
547 pdata->mac_cr &= ~MAC_CR_FDPX_;
548 pdata->mac_cr |= MAC_CR_RCVOWN_;
549 } else {
550 pdata->mac_cr &= ~MAC_CR_RCVOWN_;
551 pdata->mac_cr |= MAC_CR_FDPX_;
552 }
553 spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
554
769ea6d8 555 ret = smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr);
1e1d7412 556 check_warn_return(ret, "Error writing MAC_CR\n");
2f7ca802 557
769ea6d8 558 ret = smsc95xx_phy_update_flowcontrol(dev, ecmd.duplex, lcladv, rmtadv);
1e1d7412 559 check_warn_return(ret, "Error updating PHY flow control\n");
2f7ca802
SG
560
561 return 0;
562}
563
564static void smsc95xx_status(struct usbnet *dev, struct urb *urb)
565{
566 u32 intdata;
567
568 if (urb->actual_length != 4) {
60b86755
JP
569 netdev_warn(dev->net, "unexpected urb length %d\n",
570 urb->actual_length);
2f7ca802
SG
571 return;
572 }
573
574 memcpy(&intdata, urb->transfer_buffer, 4);
1d74a6bd 575 le32_to_cpus(&intdata);
2f7ca802 576
a475f603 577 netif_dbg(dev, link, dev->net, "intdata: 0x%08X\n", intdata);
2f7ca802
SG
578
579 if (intdata & INT_ENP_PHY_INT_)
580 usbnet_defer_kevent(dev, EVENT_LINK_RESET);
581 else
60b86755
JP
582 netdev_warn(dev->net, "unexpected interrupt, intdata=0x%08X\n",
583 intdata);
2f7ca802
SG
584}
585
f7b29271 586/* Enable or disable Tx & Rx checksum offload engines */
c8f44aff
MM
587static int smsc95xx_set_features(struct net_device *netdev,
588 netdev_features_t features)
2f7ca802 589{
78e47fe4 590 struct usbnet *dev = netdev_priv(netdev);
2f7ca802 591 u32 read_buf;
78e47fe4
MM
592 int ret;
593
594 ret = smsc95xx_read_reg(dev, COE_CR, &read_buf);
769ea6d8 595 check_warn_return(ret, "Failed to read COE_CR: %d\n", ret);
2f7ca802 596
78e47fe4 597 if (features & NETIF_F_HW_CSUM)
f7b29271
SG
598 read_buf |= Tx_COE_EN_;
599 else
600 read_buf &= ~Tx_COE_EN_;
601
78e47fe4 602 if (features & NETIF_F_RXCSUM)
2f7ca802
SG
603 read_buf |= Rx_COE_EN_;
604 else
605 read_buf &= ~Rx_COE_EN_;
606
607 ret = smsc95xx_write_reg(dev, COE_CR, read_buf);
769ea6d8 608 check_warn_return(ret, "Failed to write COE_CR: %d\n", ret);
2f7ca802 609
a475f603 610 netif_dbg(dev, hw, dev->net, "COE_CR = 0x%08x\n", read_buf);
2f7ca802
SG
611 return 0;
612}
613
614static int smsc95xx_ethtool_get_eeprom_len(struct net_device *net)
615{
616 return MAX_EEPROM_SIZE;
617}
618
619static int smsc95xx_ethtool_get_eeprom(struct net_device *netdev,
620 struct ethtool_eeprom *ee, u8 *data)
621{
622 struct usbnet *dev = netdev_priv(netdev);
623
624 ee->magic = LAN95XX_EEPROM_MAGIC;
625
626 return smsc95xx_read_eeprom(dev, ee->offset, ee->len, data);
627}
628
629static int smsc95xx_ethtool_set_eeprom(struct net_device *netdev,
630 struct ethtool_eeprom *ee, u8 *data)
631{
632 struct usbnet *dev = netdev_priv(netdev);
633
634 if (ee->magic != LAN95XX_EEPROM_MAGIC) {
60b86755
JP
635 netdev_warn(dev->net, "EEPROM: magic value mismatch, magic = 0x%x\n",
636 ee->magic);
2f7ca802
SG
637 return -EINVAL;
638 }
639
640 return smsc95xx_write_eeprom(dev, ee->offset, ee->len, data);
641}
642
9fa32e94
EV
643static int smsc95xx_ethtool_getregslen(struct net_device *netdev)
644{
645 /* all smsc95xx registers */
646 return COE_CR - ID_REV + 1;
647}
648
649static void
650smsc95xx_ethtool_getregs(struct net_device *netdev, struct ethtool_regs *regs,
651 void *buf)
652{
653 struct usbnet *dev = netdev_priv(netdev);
d348446b
DC
654 unsigned int i, j;
655 int retval;
9fa32e94
EV
656 u32 *data = buf;
657
658 retval = smsc95xx_read_reg(dev, ID_REV, &regs->version);
659 if (retval < 0) {
660 netdev_warn(netdev, "REGS: cannot read ID_REV\n");
661 return;
662 }
663
664 for (i = ID_REV, j = 0; i <= COE_CR; i += (sizeof(u32)), j++) {
665 retval = smsc95xx_read_reg(dev, i, &data[j]);
666 if (retval < 0) {
667 netdev_warn(netdev, "REGS: cannot read reg[%x]\n", i);
668 return;
669 }
670 }
671}
672
e0e474a8
SG
673static void smsc95xx_ethtool_get_wol(struct net_device *net,
674 struct ethtool_wolinfo *wolinfo)
675{
676 struct usbnet *dev = netdev_priv(net);
677 struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
678
679 wolinfo->supported = SUPPORTED_WAKE;
680 wolinfo->wolopts = pdata->wolopts;
681}
682
683static int smsc95xx_ethtool_set_wol(struct net_device *net,
684 struct ethtool_wolinfo *wolinfo)
685{
686 struct usbnet *dev = netdev_priv(net);
687 struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
688
689 pdata->wolopts = wolinfo->wolopts & SUPPORTED_WAKE;
690 return 0;
691}
692
0fc0b732 693static const struct ethtool_ops smsc95xx_ethtool_ops = {
2f7ca802
SG
694 .get_link = usbnet_get_link,
695 .nway_reset = usbnet_nway_reset,
696 .get_drvinfo = usbnet_get_drvinfo,
697 .get_msglevel = usbnet_get_msglevel,
698 .set_msglevel = usbnet_set_msglevel,
699 .get_settings = usbnet_get_settings,
700 .set_settings = usbnet_set_settings,
701 .get_eeprom_len = smsc95xx_ethtool_get_eeprom_len,
702 .get_eeprom = smsc95xx_ethtool_get_eeprom,
703 .set_eeprom = smsc95xx_ethtool_set_eeprom,
9fa32e94
EV
704 .get_regs_len = smsc95xx_ethtool_getregslen,
705 .get_regs = smsc95xx_ethtool_getregs,
e0e474a8
SG
706 .get_wol = smsc95xx_ethtool_get_wol,
707 .set_wol = smsc95xx_ethtool_set_wol,
2f7ca802
SG
708};
709
710static int smsc95xx_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
711{
712 struct usbnet *dev = netdev_priv(netdev);
713
714 if (!netif_running(netdev))
715 return -EINVAL;
716
717 return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
718}
719
720static void smsc95xx_init_mac_address(struct usbnet *dev)
721{
722 /* try reading mac address from EEPROM */
723 if (smsc95xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN,
724 dev->net->dev_addr) == 0) {
725 if (is_valid_ether_addr(dev->net->dev_addr)) {
726 /* eeprom values are valid so use them */
a475f603 727 netif_dbg(dev, ifup, dev->net, "MAC address read from EEPROM\n");
2f7ca802
SG
728 return;
729 }
730 }
731
732 /* no eeprom, or eeprom values are invalid. generate random MAC */
f2cedb63 733 eth_hw_addr_random(dev->net);
c7e12ead 734 netif_dbg(dev, ifup, dev->net, "MAC address set to eth_random_addr\n");
2f7ca802
SG
735}
736
737static int smsc95xx_set_mac_address(struct usbnet *dev)
738{
739 u32 addr_lo = dev->net->dev_addr[0] | dev->net->dev_addr[1] << 8 |
740 dev->net->dev_addr[2] << 16 | dev->net->dev_addr[3] << 24;
741 u32 addr_hi = dev->net->dev_addr[4] | dev->net->dev_addr[5] << 8;
742 int ret;
743
744 ret = smsc95xx_write_reg(dev, ADDRL, addr_lo);
769ea6d8 745 check_warn_return(ret, "Failed to write ADDRL: %d\n", ret);
2f7ca802
SG
746
747 ret = smsc95xx_write_reg(dev, ADDRH, addr_hi);
769ea6d8 748 check_warn_return(ret, "Failed to write ADDRH: %d\n", ret);
2f7ca802
SG
749
750 return 0;
751}
752
753/* starts the TX path */
769ea6d8 754static int smsc95xx_start_tx_path(struct usbnet *dev)
2f7ca802
SG
755{
756 struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
757 unsigned long flags;
769ea6d8 758 int ret;
2f7ca802
SG
759
760 /* Enable Tx at MAC */
761 spin_lock_irqsave(&pdata->mac_cr_lock, flags);
762 pdata->mac_cr |= MAC_CR_TXEN_;
763 spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
764
769ea6d8
SG
765 ret = smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr);
766 check_warn_return(ret, "Failed to write MAC_CR: %d\n", ret);
2f7ca802
SG
767
768 /* Enable Tx at SCSRs */
769ea6d8
SG
769 ret = smsc95xx_write_reg(dev, TX_CFG, TX_CFG_ON_);
770 check_warn_return(ret, "Failed to write TX_CFG: %d\n", ret);
771
772 return 0;
2f7ca802
SG
773}
774
775/* Starts the Receive path */
ec32115d 776static int smsc95xx_start_rx_path(struct usbnet *dev, int in_pm)
2f7ca802
SG
777{
778 struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
779 unsigned long flags;
769ea6d8 780 int ret;
2f7ca802
SG
781
782 spin_lock_irqsave(&pdata->mac_cr_lock, flags);
783 pdata->mac_cr |= MAC_CR_RXEN_;
784 spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
785
ec32115d 786 ret = __smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr, in_pm);
769ea6d8
SG
787 check_warn_return(ret, "Failed to write MAC_CR: %d\n", ret);
788
789 return 0;
2f7ca802
SG
790}
791
792static int smsc95xx_phy_initialize(struct usbnet *dev)
793{
769ea6d8 794 int bmcr, ret, timeout = 0;
db443c44 795
2f7ca802
SG
796 /* Initialize MII structure */
797 dev->mii.dev = dev->net;
798 dev->mii.mdio_read = smsc95xx_mdio_read;
799 dev->mii.mdio_write = smsc95xx_mdio_write;
800 dev->mii.phy_id_mask = 0x1f;
801 dev->mii.reg_num_mask = 0x1f;
802 dev->mii.phy_id = SMSC95XX_INTERNAL_PHY_ID;
803
db443c44 804 /* reset phy and wait for reset to complete */
2f7ca802 805 smsc95xx_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
db443c44
SG
806
807 do {
808 msleep(10);
809 bmcr = smsc95xx_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR);
810 timeout++;
d9460920 811 } while ((bmcr & BMCR_RESET) && (timeout < 100));
db443c44
SG
812
813 if (timeout >= 100) {
814 netdev_warn(dev->net, "timeout on PHY Reset");
815 return -EIO;
816 }
817
2f7ca802
SG
818 smsc95xx_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
819 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP |
820 ADVERTISE_PAUSE_ASYM);
821
822 /* read to clear */
769ea6d8 823 ret = smsc95xx_mdio_read(dev->net, dev->mii.phy_id, PHY_INT_SRC);
1e1d7412 824 check_warn_return(ret, "Failed to read PHY_INT_SRC during init\n");
2f7ca802
SG
825
826 smsc95xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_MASK,
827 PHY_INT_MASK_DEFAULT_);
828 mii_nway_restart(&dev->mii);
829
a475f603 830 netif_dbg(dev, ifup, dev->net, "phy initialised successfully\n");
2f7ca802
SG
831 return 0;
832}
833
834static int smsc95xx_reset(struct usbnet *dev)
835{
836 struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
837 u32 read_buf, write_buf, burst_cap;
838 int ret = 0, timeout;
2f7ca802 839
a475f603 840 netif_dbg(dev, ifup, dev->net, "entering smsc95xx_reset\n");
2f7ca802 841
4436761b 842 ret = smsc95xx_write_reg(dev, HW_CFG, HW_CFG_LRST_);
769ea6d8 843 check_warn_return(ret, "Failed to write HW_CFG_LRST_ bit in HW_CFG\n");
2f7ca802
SG
844
845 timeout = 0;
846 do {
cf2acec2 847 msleep(10);
2f7ca802 848 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
769ea6d8 849 check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret);
2f7ca802
SG
850 timeout++;
851 } while ((read_buf & HW_CFG_LRST_) && (timeout < 100));
852
853 if (timeout >= 100) {
60b86755 854 netdev_warn(dev->net, "timeout waiting for completion of Lite Reset\n");
2f7ca802
SG
855 return ret;
856 }
857
4436761b 858 ret = smsc95xx_write_reg(dev, PM_CTRL, PM_CTL_PHY_RST_);
769ea6d8 859 check_warn_return(ret, "Failed to write PM_CTRL: %d\n", ret);
2f7ca802
SG
860
861 timeout = 0;
862 do {
cf2acec2 863 msleep(10);
2f7ca802 864 ret = smsc95xx_read_reg(dev, PM_CTRL, &read_buf);
769ea6d8 865 check_warn_return(ret, "Failed to read PM_CTRL: %d\n", ret);
2f7ca802
SG
866 timeout++;
867 } while ((read_buf & PM_CTL_PHY_RST_) && (timeout < 100));
868
869 if (timeout >= 100) {
60b86755 870 netdev_warn(dev->net, "timeout waiting for PHY Reset\n");
2f7ca802
SG
871 return ret;
872 }
873
2f7ca802
SG
874 ret = smsc95xx_set_mac_address(dev);
875 if (ret < 0)
876 return ret;
877
1e1d7412
JP
878 netif_dbg(dev, ifup, dev->net, "MAC Address: %pM\n",
879 dev->net->dev_addr);
2f7ca802
SG
880
881 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
769ea6d8 882 check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret);
2f7ca802 883
1e1d7412
JP
884 netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG : 0x%08x\n",
885 read_buf);
2f7ca802
SG
886
887 read_buf |= HW_CFG_BIR_;
888
889 ret = smsc95xx_write_reg(dev, HW_CFG, read_buf);
769ea6d8 890 check_warn_return(ret, "Failed to write HW_CFG_BIR_ bit in HW_CFG\n");
2f7ca802
SG
891
892 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
769ea6d8 893 check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret);
a475f603
JP
894 netif_dbg(dev, ifup, dev->net,
895 "Read Value from HW_CFG after writing HW_CFG_BIR_: 0x%08x\n",
896 read_buf);
2f7ca802
SG
897
898 if (!turbo_mode) {
899 burst_cap = 0;
900 dev->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
901 } else if (dev->udev->speed == USB_SPEED_HIGH) {
902 burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
903 dev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
904 } else {
905 burst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
906 dev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
907 }
908
1e1d7412
JP
909 netif_dbg(dev, ifup, dev->net, "rx_urb_size=%ld\n",
910 (ulong)dev->rx_urb_size);
2f7ca802
SG
911
912 ret = smsc95xx_write_reg(dev, BURST_CAP, burst_cap);
769ea6d8 913 check_warn_return(ret, "Failed to write BURST_CAP: %d\n", ret);
2f7ca802
SG
914
915 ret = smsc95xx_read_reg(dev, BURST_CAP, &read_buf);
769ea6d8
SG
916 check_warn_return(ret, "Failed to read BURST_CAP: %d\n", ret);
917
a475f603
JP
918 netif_dbg(dev, ifup, dev->net,
919 "Read Value from BURST_CAP after writing: 0x%08x\n",
920 read_buf);
2f7ca802 921
4436761b 922 ret = smsc95xx_write_reg(dev, BULK_IN_DLY, DEFAULT_BULK_IN_DELAY);
769ea6d8 923 check_warn_return(ret, "Failed to write BULK_IN_DLY: %d\n", ret);
2f7ca802
SG
924
925 ret = smsc95xx_read_reg(dev, BULK_IN_DLY, &read_buf);
769ea6d8
SG
926 check_warn_return(ret, "Failed to read BULK_IN_DLY: %d\n", ret);
927
a475f603
JP
928 netif_dbg(dev, ifup, dev->net,
929 "Read Value from BULK_IN_DLY after writing: 0x%08x\n",
930 read_buf);
2f7ca802
SG
931
932 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
769ea6d8
SG
933 check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret);
934
1e1d7412
JP
935 netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG: 0x%08x\n",
936 read_buf);
2f7ca802
SG
937
938 if (turbo_mode)
939 read_buf |= (HW_CFG_MEF_ | HW_CFG_BCE_);
940
941 read_buf &= ~HW_CFG_RXDOFF_;
942
943 /* set Rx data offset=2, Make IP header aligns on word boundary. */
944 read_buf |= NET_IP_ALIGN << 9;
945
946 ret = smsc95xx_write_reg(dev, HW_CFG, read_buf);
769ea6d8 947 check_warn_return(ret, "Failed to write HW_CFG: %d\n", ret);
2f7ca802
SG
948
949 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
769ea6d8
SG
950 check_warn_return(ret, "Failed to read HW_CFG: %d\n", ret);
951
a475f603
JP
952 netif_dbg(dev, ifup, dev->net,
953 "Read Value from HW_CFG after writing: 0x%08x\n", read_buf);
2f7ca802 954
4436761b 955 ret = smsc95xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL_);
769ea6d8 956 check_warn_return(ret, "Failed to write INT_STS: %d\n", ret);
2f7ca802
SG
957
958 ret = smsc95xx_read_reg(dev, ID_REV, &read_buf);
769ea6d8 959 check_warn_return(ret, "Failed to read ID_REV: %d\n", ret);
a475f603 960 netif_dbg(dev, ifup, dev->net, "ID_REV = 0x%08x\n", read_buf);
2f7ca802 961
f293501c
SG
962 /* Configure GPIO pins as LED outputs */
963 write_buf = LED_GPIO_CFG_SPD_LED | LED_GPIO_CFG_LNK_LED |
964 LED_GPIO_CFG_FDX_LED;
965 ret = smsc95xx_write_reg(dev, LED_GPIO_CFG, write_buf);
769ea6d8 966 check_warn_return(ret, "Failed to write LED_GPIO_CFG: %d\n", ret);
f293501c 967
2f7ca802 968 /* Init Tx */
4436761b 969 ret = smsc95xx_write_reg(dev, FLOW, 0);
769ea6d8 970 check_warn_return(ret, "Failed to write FLOW: %d\n", ret);
2f7ca802 971
4436761b 972 ret = smsc95xx_write_reg(dev, AFC_CFG, AFC_CFG_DEFAULT);
769ea6d8 973 check_warn_return(ret, "Failed to write AFC_CFG: %d\n", ret);
2f7ca802
SG
974
975 /* Don't need mac_cr_lock during initialisation */
976 ret = smsc95xx_read_reg(dev, MAC_CR, &pdata->mac_cr);
769ea6d8 977 check_warn_return(ret, "Failed to read MAC_CR: %d\n", ret);
2f7ca802
SG
978
979 /* Init Rx */
980 /* Set Vlan */
4436761b 981 ret = smsc95xx_write_reg(dev, VLAN1, (u32)ETH_P_8021Q);
769ea6d8 982 check_warn_return(ret, "Failed to write VLAN1: %d\n", ret);
2f7ca802 983
f7b29271 984 /* Enable or disable checksum offload engines */
769ea6d8 985 ret = smsc95xx_set_features(dev->net, dev->net->features);
1e1d7412 986 check_warn_return(ret, "Failed to set checksum offload features\n");
2f7ca802
SG
987
988 smsc95xx_set_multicast(dev->net);
989
769ea6d8 990 ret = smsc95xx_phy_initialize(dev);
1e1d7412 991 check_warn_return(ret, "Failed to init PHY\n");
2f7ca802
SG
992
993 ret = smsc95xx_read_reg(dev, INT_EP_CTL, &read_buf);
769ea6d8 994 check_warn_return(ret, "Failed to read INT_EP_CTL: %d\n", ret);
2f7ca802
SG
995
996 /* enable PHY interrupts */
997 read_buf |= INT_EP_CTL_PHY_INT_;
998
999 ret = smsc95xx_write_reg(dev, INT_EP_CTL, read_buf);
769ea6d8 1000 check_warn_return(ret, "Failed to write INT_EP_CTL: %d\n", ret);
2f7ca802 1001
769ea6d8 1002 ret = smsc95xx_start_tx_path(dev);
1e1d7412 1003 check_warn_return(ret, "Failed to start TX path\n");
769ea6d8 1004
ec32115d 1005 ret = smsc95xx_start_rx_path(dev, 0);
1e1d7412 1006 check_warn_return(ret, "Failed to start RX path\n");
2f7ca802 1007
a475f603 1008 netif_dbg(dev, ifup, dev->net, "smsc95xx_reset, return 0\n");
2f7ca802
SG
1009 return 0;
1010}
1011
63e77b39
SH
1012static const struct net_device_ops smsc95xx_netdev_ops = {
1013 .ndo_open = usbnet_open,
1014 .ndo_stop = usbnet_stop,
1015 .ndo_start_xmit = usbnet_start_xmit,
1016 .ndo_tx_timeout = usbnet_tx_timeout,
1017 .ndo_change_mtu = usbnet_change_mtu,
1018 .ndo_set_mac_address = eth_mac_addr,
1019 .ndo_validate_addr = eth_validate_addr,
1020 .ndo_do_ioctl = smsc95xx_ioctl,
afc4b13d 1021 .ndo_set_rx_mode = smsc95xx_set_multicast,
78e47fe4 1022 .ndo_set_features = smsc95xx_set_features,
63e77b39
SH
1023};
1024
2f7ca802
SG
1025static int smsc95xx_bind(struct usbnet *dev, struct usb_interface *intf)
1026{
1027 struct smsc95xx_priv *pdata = NULL;
bbd9f9ee 1028 u32 val;
2f7ca802
SG
1029 int ret;
1030
1031 printk(KERN_INFO SMSC_CHIPNAME " v" SMSC_DRIVER_VERSION "\n");
1032
1033 ret = usbnet_get_endpoints(dev, intf);
769ea6d8 1034 check_warn_return(ret, "usbnet_get_endpoints failed: %d\n", ret);
2f7ca802
SG
1035
1036 dev->data[0] = (unsigned long)kzalloc(sizeof(struct smsc95xx_priv),
1037 GFP_KERNEL);
1038
1039 pdata = (struct smsc95xx_priv *)(dev->data[0]);
1040 if (!pdata) {
60b86755 1041 netdev_warn(dev->net, "Unable to allocate struct smsc95xx_priv\n");
2f7ca802
SG
1042 return -ENOMEM;
1043 }
1044
1045 spin_lock_init(&pdata->mac_cr_lock);
1046
78e47fe4
MM
1047 if (DEFAULT_TX_CSUM_ENABLE)
1048 dev->net->features |= NETIF_F_HW_CSUM;
1049 if (DEFAULT_RX_CSUM_ENABLE)
1050 dev->net->features |= NETIF_F_RXCSUM;
1051
1052 dev->net->hw_features = NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
2f7ca802 1053
f4e8ab7c
BB
1054 smsc95xx_init_mac_address(dev);
1055
2f7ca802
SG
1056 /* Init all registers */
1057 ret = smsc95xx_reset(dev);
1058
bbd9f9ee
SG
1059 /* detect device revision as different features may be available */
1060 ret = smsc95xx_read_reg(dev, ID_REV, &val);
1061 check_warn_return(ret, "Failed to read ID_REV: %d\n", ret);
1062 val >>= 16;
9ebca507
SG
1063
1064 if ((val == ID_REV_CHIP_ID_9500A_) || (val == ID_REV_CHIP_ID_9530_) ||
1065 (val == ID_REV_CHIP_ID_89530_) || (val == ID_REV_CHIP_ID_9730_))
1066 pdata->features = (FEATURE_8_WAKEUP_FILTERS |
1067 FEATURE_PHY_NLP_CROSSOVER |
1068 FEATURE_AUTOSUSPEND);
1069 else if (val == ID_REV_CHIP_ID_9512_)
1070 pdata->features = FEATURE_8_WAKEUP_FILTERS;
bbd9f9ee 1071
63e77b39 1072 dev->net->netdev_ops = &smsc95xx_netdev_ops;
2f7ca802 1073 dev->net->ethtool_ops = &smsc95xx_ethtool_ops;
2f7ca802 1074 dev->net->flags |= IFF_MULTICAST;
78e47fe4 1075 dev->net->hard_header_len += SMSC95XX_TX_OVERHEAD_CSUM;
9bbf5660 1076 dev->hard_mtu = dev->net->mtu + dev->net->hard_header_len;
2f7ca802
SG
1077 return 0;
1078}
1079
1080static void smsc95xx_unbind(struct usbnet *dev, struct usb_interface *intf)
1081{
1082 struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
1083 if (pdata) {
a475f603 1084 netif_dbg(dev, ifdown, dev->net, "free pdata\n");
2f7ca802
SG
1085 kfree(pdata);
1086 pdata = NULL;
1087 dev->data[0] = 0;
1088 }
1089}
1090
bbd9f9ee
SG
1091static u16 smsc_crc(const u8 *buffer, size_t len, int filter)
1092{
1093 return bitrev16(crc16(0xFFFF, buffer, len)) << ((filter % 2) * 16);
1094}
1095
e5e3af83
SG
1096static int smsc95xx_enable_phy_wakeup_interrupts(struct usbnet *dev, u16 mask)
1097{
1098 struct mii_if_info *mii = &dev->mii;
1099 int ret;
1100
1e1d7412 1101 netdev_dbg(dev->net, "enabling PHY wakeup interrupts\n");
e5e3af83
SG
1102
1103 /* read to clear */
1104 ret = smsc95xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_SRC);
1e1d7412 1105 check_warn_return(ret, "Error reading PHY_INT_SRC\n");
e5e3af83
SG
1106
1107 /* enable interrupt source */
1108 ret = smsc95xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_MASK);
1e1d7412 1109 check_warn_return(ret, "Error reading PHY_INT_MASK\n");
e5e3af83
SG
1110
1111 ret |= mask;
1112
1113 smsc95xx_mdio_write_nopm(dev->net, mii->phy_id, PHY_INT_MASK, ret);
1114
1115 return 0;
1116}
1117
1118static int smsc95xx_link_ok_nopm(struct usbnet *dev)
1119{
1120 struct mii_if_info *mii = &dev->mii;
1121 int ret;
1122
1123 /* first, a dummy read, needed to latch some MII phys */
1124 ret = smsc95xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR);
1e1d7412 1125 check_warn_return(ret, "Error reading MII_BMSR\n");
e5e3af83
SG
1126
1127 ret = smsc95xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR);
1e1d7412 1128 check_warn_return(ret, "Error reading MII_BMSR\n");
e5e3af83
SG
1129
1130 return !!(ret & BMSR_LSTATUS);
1131}
1132
319b95b5
SG
1133static int smsc95xx_enter_suspend0(struct usbnet *dev)
1134{
1135 struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
1136 u32 val;
1137 int ret;
1138
1139 ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val);
1e1d7412 1140 check_warn_return(ret, "Error reading PM_CTRL\n");
319b95b5
SG
1141
1142 val &= (~(PM_CTL_SUS_MODE_ | PM_CTL_WUPS_ | PM_CTL_PHY_RST_));
1143 val |= PM_CTL_SUS_MODE_0;
1144
1145 ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
1e1d7412 1146 check_warn_return(ret, "Error writing PM_CTRL\n");
319b95b5
SG
1147
1148 /* clear wol status */
1149 val &= ~PM_CTL_WUPS_;
1150 val |= PM_CTL_WUPS_WOL_;
1151
1152 /* enable energy detection */
1153 if (pdata->wolopts & WAKE_PHY)
1154 val |= PM_CTL_WUPS_ED_;
1155
1156 ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
1e1d7412 1157 check_warn_return(ret, "Error writing PM_CTRL\n");
319b95b5
SG
1158
1159 /* read back PM_CTRL */
1160 ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val);
1e1d7412 1161 check_warn_return(ret, "Error reading PM_CTRL\n");
319b95b5
SG
1162
1163 smsc95xx_set_feature(dev, USB_DEVICE_REMOTE_WAKEUP);
1164
1165 return 0;
1166}
1167
1168static int smsc95xx_enter_suspend1(struct usbnet *dev)
1169{
1170 struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
1171 struct mii_if_info *mii = &dev->mii;
1172 u32 val;
1173 int ret;
1174
1175 /* reconfigure link pulse detection timing for
1176 * compatibility with non-standard link partners
1177 */
1178 if (pdata->features & FEATURE_PHY_NLP_CROSSOVER)
1179 smsc95xx_mdio_write_nopm(dev->net, mii->phy_id, PHY_EDPD_CONFIG,
1180 PHY_EDPD_CONFIG_DEFAULT);
1181
1182 /* enable energy detect power-down mode */
1183 ret = smsc95xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_MODE_CTRL_STS);
1e1d7412 1184 check_warn_return(ret, "Error reading PHY_MODE_CTRL_STS\n");
319b95b5
SG
1185
1186 ret |= MODE_CTRL_STS_EDPWRDOWN_;
1187
1188 smsc95xx_mdio_write_nopm(dev->net, mii->phy_id, PHY_MODE_CTRL_STS, ret);
1189
1190 /* enter SUSPEND1 mode */
1191 ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val);
1e1d7412 1192 check_warn_return(ret, "Error reading PM_CTRL\n");
319b95b5
SG
1193
1194 val &= ~(PM_CTL_SUS_MODE_ | PM_CTL_WUPS_ | PM_CTL_PHY_RST_);
1195 val |= PM_CTL_SUS_MODE_1;
1196
1197 ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
1e1d7412 1198 check_warn_return(ret, "Error writing PM_CTRL\n");
319b95b5
SG
1199
1200 /* clear wol status, enable energy detection */
1201 val &= ~PM_CTL_WUPS_;
1202 val |= (PM_CTL_WUPS_ED_ | PM_CTL_ED_EN_);
1203
1204 ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
1e1d7412 1205 check_warn_return(ret, "Error writing PM_CTRL\n");
319b95b5
SG
1206
1207 smsc95xx_set_feature(dev, USB_DEVICE_REMOTE_WAKEUP);
1208
1209 return 0;
1210}
1211
1212static int smsc95xx_enter_suspend2(struct usbnet *dev)
1213{
1214 u32 val;
1215 int ret;
1216
1217 ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val);
1e1d7412 1218 check_warn_return(ret, "Error reading PM_CTRL\n");
319b95b5
SG
1219
1220 val &= ~(PM_CTL_SUS_MODE_ | PM_CTL_WUPS_ | PM_CTL_PHY_RST_);
1221 val |= PM_CTL_SUS_MODE_2;
1222
1223 ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
1e1d7412 1224 check_warn_return(ret, "Error writing PM_CTRL\n");
319b95b5
SG
1225
1226 return 0;
1227}
1228
b5a04475
SG
1229static int smsc95xx_suspend(struct usb_interface *intf, pm_message_t message)
1230{
1231 struct usbnet *dev = usb_get_intfdata(intf);
e0e474a8 1232 struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
e5e3af83 1233 u32 val, link_up;
b5a04475 1234 int ret;
b5a04475 1235
b5a04475 1236 ret = usbnet_suspend(intf, message);
1e1d7412 1237 check_warn_return(ret, "usbnet_suspend error\n");
b5a04475 1238
e5e3af83
SG
1239 /* determine if link is up using only _nopm functions */
1240 link_up = smsc95xx_link_ok_nopm(dev);
1241
1242 /* if no wol options set, or if link is down and we're not waking on
1243 * PHY activity, enter lowest power SUSPEND2 mode
1244 */
1245 if (!(pdata->wolopts & SUPPORTED_WAKE) ||
1246 !(link_up || (pdata->wolopts & WAKE_PHY))) {
1e1d7412 1247 netdev_info(dev->net, "entering SUSPEND2 mode\n");
e0e474a8
SG
1248
1249 /* disable energy detect (link up) & wake up events */
ec32115d 1250 ret = smsc95xx_read_reg_nopm(dev, WUCSR, &val);
1e1d7412 1251 check_warn_return(ret, "Error reading WUCSR\n");
e0e474a8
SG
1252
1253 val &= ~(WUCSR_MPEN_ | WUCSR_WAKE_EN_);
1254
ec32115d 1255 ret = smsc95xx_write_reg_nopm(dev, WUCSR, val);
1e1d7412 1256 check_warn_return(ret, "Error writing WUCSR\n");
e0e474a8 1257
ec32115d 1258 ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val);
1e1d7412 1259 check_warn_return(ret, "Error reading PM_CTRL\n");
e0e474a8
SG
1260
1261 val &= ~(PM_CTL_ED_EN_ | PM_CTL_WOL_EN_);
1262
ec32115d 1263 ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
1e1d7412 1264 check_warn_return(ret, "Error writing PM_CTRL\n");
e0e474a8 1265
319b95b5 1266 return smsc95xx_enter_suspend2(dev);
e0e474a8
SG
1267 }
1268
e5e3af83
SG
1269 if (pdata->wolopts & WAKE_PHY) {
1270 ret = smsc95xx_enable_phy_wakeup_interrupts(dev,
1271 (PHY_INT_MASK_ANEG_COMP_ | PHY_INT_MASK_LINK_DOWN_));
1e1d7412 1272 check_warn_return(ret, "error enabling PHY wakeup ints\n");
e5e3af83
SG
1273
1274 /* if link is down then configure EDPD and enter SUSPEND1,
1275 * otherwise enter SUSPEND0 below
1276 */
1277 if (!link_up) {
1e1d7412 1278 netdev_info(dev->net, "entering SUSPEND1 mode\n");
319b95b5 1279 return smsc95xx_enter_suspend1(dev);
e5e3af83
SG
1280 }
1281 }
1282
bbd9f9ee 1283 if (pdata->wolopts & (WAKE_BCAST | WAKE_MCAST | WAKE_ARP | WAKE_UCAST)) {
eed9a729 1284 u32 *filter_mask = kzalloc(sizeof(u32) * 32, GFP_KERNEL);
06a221be
ML
1285 u32 command[2];
1286 u32 offset[2];
1287 u32 crc[4];
9ebca507
SG
1288 int wuff_filter_count =
1289 (pdata->features & FEATURE_8_WAKEUP_FILTERS) ?
1290 LAN9500A_WUFF_NUM : LAN9500_WUFF_NUM;
bbd9f9ee
SG
1291 int i, filter = 0;
1292
eed9a729
SG
1293 if (!filter_mask) {
1294 netdev_warn(dev->net, "Unable to allocate filter_mask\n");
1295 return -ENOMEM;
1296 }
1297
06a221be
ML
1298 memset(command, 0, sizeof(command));
1299 memset(offset, 0, sizeof(offset));
1300 memset(crc, 0, sizeof(crc));
1301
bbd9f9ee
SG
1302 if (pdata->wolopts & WAKE_BCAST) {
1303 const u8 bcast[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
1e1d7412 1304 netdev_info(dev->net, "enabling broadcast detection\n");
bbd9f9ee
SG
1305 filter_mask[filter * 4] = 0x003F;
1306 filter_mask[filter * 4 + 1] = 0x00;
1307 filter_mask[filter * 4 + 2] = 0x00;
1308 filter_mask[filter * 4 + 3] = 0x00;
1309 command[filter/4] |= 0x05UL << ((filter % 4) * 8);
1310 offset[filter/4] |= 0x00 << ((filter % 4) * 8);
1311 crc[filter/2] |= smsc_crc(bcast, 6, filter);
1312 filter++;
1313 }
1314
1315 if (pdata->wolopts & WAKE_MCAST) {
1316 const u8 mcast[] = {0x01, 0x00, 0x5E};
1e1d7412 1317 netdev_info(dev->net, "enabling multicast detection\n");
bbd9f9ee
SG
1318 filter_mask[filter * 4] = 0x0007;
1319 filter_mask[filter * 4 + 1] = 0x00;
1320 filter_mask[filter * 4 + 2] = 0x00;
1321 filter_mask[filter * 4 + 3] = 0x00;
1322 command[filter/4] |= 0x09UL << ((filter % 4) * 8);
1323 offset[filter/4] |= 0x00 << ((filter % 4) * 8);
1324 crc[filter/2] |= smsc_crc(mcast, 3, filter);
1325 filter++;
1326 }
1327
1328 if (pdata->wolopts & WAKE_ARP) {
1329 const u8 arp[] = {0x08, 0x06};
1e1d7412 1330 netdev_info(dev->net, "enabling ARP detection\n");
bbd9f9ee
SG
1331 filter_mask[filter * 4] = 0x0003;
1332 filter_mask[filter * 4 + 1] = 0x00;
1333 filter_mask[filter * 4 + 2] = 0x00;
1334 filter_mask[filter * 4 + 3] = 0x00;
1335 command[filter/4] |= 0x05UL << ((filter % 4) * 8);
1336 offset[filter/4] |= 0x0C << ((filter % 4) * 8);
1337 crc[filter/2] |= smsc_crc(arp, 2, filter);
1338 filter++;
1339 }
1340
1341 if (pdata->wolopts & WAKE_UCAST) {
1e1d7412 1342 netdev_info(dev->net, "enabling unicast detection\n");
bbd9f9ee
SG
1343 filter_mask[filter * 4] = 0x003F;
1344 filter_mask[filter * 4 + 1] = 0x00;
1345 filter_mask[filter * 4 + 2] = 0x00;
1346 filter_mask[filter * 4 + 3] = 0x00;
1347 command[filter/4] |= 0x01UL << ((filter % 4) * 8);
1348 offset[filter/4] |= 0x00 << ((filter % 4) * 8);
1349 crc[filter/2] |= smsc_crc(dev->net->dev_addr, ETH_ALEN, filter);
1350 filter++;
1351 }
1352
9ebca507 1353 for (i = 0; i < (wuff_filter_count * 4); i++) {
ec32115d 1354 ret = smsc95xx_write_reg_nopm(dev, WUFF, filter_mask[i]);
06a221be
ML
1355 if (ret < 0)
1356 kfree(filter_mask);
1e1d7412 1357 check_warn_return(ret, "Error writing WUFF\n");
bbd9f9ee 1358 }
06a221be 1359 kfree(filter_mask);
bbd9f9ee 1360
9ebca507 1361 for (i = 0; i < (wuff_filter_count / 4); i++) {
ec32115d 1362 ret = smsc95xx_write_reg_nopm(dev, WUFF, command[i]);
1e1d7412 1363 check_warn_return(ret, "Error writing WUFF\n");
bbd9f9ee
SG
1364 }
1365
9ebca507 1366 for (i = 0; i < (wuff_filter_count / 4); i++) {
ec32115d 1367 ret = smsc95xx_write_reg_nopm(dev, WUFF, offset[i]);
1e1d7412 1368 check_warn_return(ret, "Error writing WUFF\n");
bbd9f9ee
SG
1369 }
1370
9ebca507 1371 for (i = 0; i < (wuff_filter_count / 2); i++) {
ec32115d 1372 ret = smsc95xx_write_reg_nopm(dev, WUFF, crc[i]);
1e1d7412 1373 check_warn_return(ret, "Error writing WUFF\n");
bbd9f9ee
SG
1374 }
1375
1376 /* clear any pending pattern match packet status */
ec32115d 1377 ret = smsc95xx_read_reg_nopm(dev, WUCSR, &val);
1e1d7412 1378 check_warn_return(ret, "Error reading WUCSR\n");
bbd9f9ee
SG
1379
1380 val |= WUCSR_WUFR_;
1381
ec32115d 1382 ret = smsc95xx_write_reg_nopm(dev, WUCSR, val);
1e1d7412 1383 check_warn_return(ret, "Error writing WUCSR\n");
bbd9f9ee
SG
1384 }
1385
e0e474a8
SG
1386 if (pdata->wolopts & WAKE_MAGIC) {
1387 /* clear any pending magic packet status */
ec32115d 1388 ret = smsc95xx_read_reg_nopm(dev, WUCSR, &val);
1e1d7412 1389 check_warn_return(ret, "Error reading WUCSR\n");
e0e474a8
SG
1390
1391 val |= WUCSR_MPR_;
1392
ec32115d 1393 ret = smsc95xx_write_reg_nopm(dev, WUCSR, val);
1e1d7412 1394 check_warn_return(ret, "Error writing WUCSR\n");
e0e474a8
SG
1395 }
1396
bbd9f9ee 1397 /* enable/disable wakeup sources */
ec32115d 1398 ret = smsc95xx_read_reg_nopm(dev, WUCSR, &val);
1e1d7412 1399 check_warn_return(ret, "Error reading WUCSR\n");
e0e474a8 1400
bbd9f9ee 1401 if (pdata->wolopts & (WAKE_BCAST | WAKE_MCAST | WAKE_ARP | WAKE_UCAST)) {
1e1d7412 1402 netdev_info(dev->net, "enabling pattern match wakeup\n");
bbd9f9ee
SG
1403 val |= WUCSR_WAKE_EN_;
1404 } else {
1e1d7412 1405 netdev_info(dev->net, "disabling pattern match wakeup\n");
bbd9f9ee
SG
1406 val &= ~WUCSR_WAKE_EN_;
1407 }
1408
e0e474a8 1409 if (pdata->wolopts & WAKE_MAGIC) {
1e1d7412 1410 netdev_info(dev->net, "enabling magic packet wakeup\n");
e0e474a8
SG
1411 val |= WUCSR_MPEN_;
1412 } else {
1e1d7412 1413 netdev_info(dev->net, "disabling magic packet wakeup\n");
e0e474a8
SG
1414 val &= ~WUCSR_MPEN_;
1415 }
1416
ec32115d 1417 ret = smsc95xx_write_reg_nopm(dev, WUCSR, val);
1e1d7412 1418 check_warn_return(ret, "Error writing WUCSR\n");
e0e474a8
SG
1419
1420 /* enable wol wakeup source */
ec32115d 1421 ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val);
1e1d7412 1422 check_warn_return(ret, "Error reading PM_CTRL\n");
e0e474a8
SG
1423
1424 val |= PM_CTL_WOL_EN_;
1425
e5e3af83
SG
1426 /* phy energy detect wakeup source */
1427 if (pdata->wolopts & WAKE_PHY)
1428 val |= PM_CTL_ED_EN_;
1429
ec32115d 1430 ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
1e1d7412 1431 check_warn_return(ret, "Error writing PM_CTRL\n");
e0e474a8 1432
bbd9f9ee 1433 /* enable receiver to enable frame reception */
ec32115d 1434 smsc95xx_start_rx_path(dev, 1);
e0e474a8
SG
1435
1436 /* some wol options are enabled, so enter SUSPEND0 */
1e1d7412 1437 netdev_info(dev->net, "entering SUSPEND0 mode\n");
319b95b5 1438 return smsc95xx_enter_suspend0(dev);
e0e474a8
SG
1439}
1440
1441static int smsc95xx_resume(struct usb_interface *intf)
1442{
1443 struct usbnet *dev = usb_get_intfdata(intf);
1444 struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
1445 int ret;
1446 u32 val;
1447
1448 BUG_ON(!dev);
1449
bbd9f9ee 1450 if (pdata->wolopts) {
e0e474a8
SG
1451 smsc95xx_clear_feature(dev, USB_DEVICE_REMOTE_WAKEUP);
1452
bbd9f9ee 1453 /* clear wake-up sources */
ec32115d 1454 ret = smsc95xx_read_reg_nopm(dev, WUCSR, &val);
1e1d7412 1455 check_warn_return(ret, "Error reading WUCSR\n");
e0e474a8 1456
bbd9f9ee 1457 val &= ~(WUCSR_WAKE_EN_ | WUCSR_MPEN_);
e0e474a8 1458
ec32115d 1459 ret = smsc95xx_write_reg_nopm(dev, WUCSR, val);
1e1d7412 1460 check_warn_return(ret, "Error writing WUCSR\n");
e0e474a8
SG
1461
1462 /* clear wake-up status */
ec32115d 1463 ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val);
1e1d7412 1464 check_warn_return(ret, "Error reading PM_CTRL\n");
e0e474a8
SG
1465
1466 val &= ~PM_CTL_WOL_EN_;
1467 val |= PM_CTL_WUPS_;
1468
ec32115d 1469 ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
1e1d7412 1470 check_warn_return(ret, "Error writing PM_CTRL\n");
e0e474a8
SG
1471 }
1472
af3d7c1e 1473 ret = usbnet_resume(intf);
1e1d7412 1474 check_warn_return(ret, "usbnet_resume error\n");
e0e474a8 1475
b5a04475
SG
1476 return 0;
1477}
1478
2f7ca802
SG
1479static void smsc95xx_rx_csum_offload(struct sk_buff *skb)
1480{
1481 skb->csum = *(u16 *)(skb_tail_pointer(skb) - 2);
1482 skb->ip_summed = CHECKSUM_COMPLETE;
1483 skb_trim(skb, skb->len - 2);
1484}
1485
1486static int smsc95xx_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
1487{
2f7ca802
SG
1488 while (skb->len > 0) {
1489 u32 header, align_count;
1490 struct sk_buff *ax_skb;
1491 unsigned char *packet;
1492 u16 size;
1493
1494 memcpy(&header, skb->data, sizeof(header));
1495 le32_to_cpus(&header);
1496 skb_pull(skb, 4 + NET_IP_ALIGN);
1497 packet = skb->data;
1498
1499 /* get the packet length */
1500 size = (u16)((header & RX_STS_FL_) >> 16);
1501 align_count = (4 - ((size + NET_IP_ALIGN) % 4)) % 4;
1502
1503 if (unlikely(header & RX_STS_ES_)) {
a475f603
JP
1504 netif_dbg(dev, rx_err, dev->net,
1505 "Error header=0x%08x\n", header);
80667ac1
HX
1506 dev->net->stats.rx_errors++;
1507 dev->net->stats.rx_dropped++;
2f7ca802
SG
1508
1509 if (header & RX_STS_CRC_) {
80667ac1 1510 dev->net->stats.rx_crc_errors++;
2f7ca802
SG
1511 } else {
1512 if (header & (RX_STS_TL_ | RX_STS_RF_))
80667ac1 1513 dev->net->stats.rx_frame_errors++;
2f7ca802
SG
1514
1515 if ((header & RX_STS_LE_) &&
1516 (!(header & RX_STS_FT_)))
80667ac1 1517 dev->net->stats.rx_length_errors++;
2f7ca802
SG
1518 }
1519 } else {
1520 /* ETH_FRAME_LEN + 4(CRC) + 2(COE) + 4(Vlan) */
1521 if (unlikely(size > (ETH_FRAME_LEN + 12))) {
a475f603
JP
1522 netif_dbg(dev, rx_err, dev->net,
1523 "size err header=0x%08x\n", header);
2f7ca802
SG
1524 return 0;
1525 }
1526
1527 /* last frame in this batch */
1528 if (skb->len == size) {
78e47fe4 1529 if (dev->net->features & NETIF_F_RXCSUM)
2f7ca802 1530 smsc95xx_rx_csum_offload(skb);
df18acca 1531 skb_trim(skb, skb->len - 4); /* remove fcs */
2f7ca802
SG
1532 skb->truesize = size + sizeof(struct sk_buff);
1533
1534 return 1;
1535 }
1536
1537 ax_skb = skb_clone(skb, GFP_ATOMIC);
1538 if (unlikely(!ax_skb)) {
60b86755 1539 netdev_warn(dev->net, "Error allocating skb\n");
2f7ca802
SG
1540 return 0;
1541 }
1542
1543 ax_skb->len = size;
1544 ax_skb->data = packet;
1545 skb_set_tail_pointer(ax_skb, size);
1546
78e47fe4 1547 if (dev->net->features & NETIF_F_RXCSUM)
2f7ca802 1548 smsc95xx_rx_csum_offload(ax_skb);
df18acca 1549 skb_trim(ax_skb, ax_skb->len - 4); /* remove fcs */
2f7ca802
SG
1550 ax_skb->truesize = size + sizeof(struct sk_buff);
1551
1552 usbnet_skb_return(dev, ax_skb);
1553 }
1554
1555 skb_pull(skb, size);
1556
1557 /* padding bytes before the next frame starts */
1558 if (skb->len)
1559 skb_pull(skb, align_count);
1560 }
1561
1562 if (unlikely(skb->len < 0)) {
60b86755 1563 netdev_warn(dev->net, "invalid rx length<0 %d\n", skb->len);
2f7ca802
SG
1564 return 0;
1565 }
1566
1567 return 1;
1568}
1569
f7b29271
SG
1570static u32 smsc95xx_calc_csum_preamble(struct sk_buff *skb)
1571{
55508d60
MM
1572 u16 low_16 = (u16)skb_checksum_start_offset(skb);
1573 u16 high_16 = low_16 + skb->csum_offset;
f7b29271
SG
1574 return (high_16 << 16) | low_16;
1575}
1576
2f7ca802
SG
1577static struct sk_buff *smsc95xx_tx_fixup(struct usbnet *dev,
1578 struct sk_buff *skb, gfp_t flags)
1579{
78e47fe4 1580 bool csum = skb->ip_summed == CHECKSUM_PARTIAL;
f7b29271 1581 int overhead = csum ? SMSC95XX_TX_OVERHEAD_CSUM : SMSC95XX_TX_OVERHEAD;
2f7ca802
SG
1582 u32 tx_cmd_a, tx_cmd_b;
1583
f7b29271
SG
1584 /* We do not advertise SG, so skbs should be already linearized */
1585 BUG_ON(skb_shinfo(skb)->nr_frags);
1586
1587 if (skb_headroom(skb) < overhead) {
2f7ca802 1588 struct sk_buff *skb2 = skb_copy_expand(skb,
f7b29271 1589 overhead, 0, flags);
2f7ca802
SG
1590 dev_kfree_skb_any(skb);
1591 skb = skb2;
1592 if (!skb)
1593 return NULL;
1594 }
1595
f7b29271 1596 if (csum) {
11bc3088
SG
1597 if (skb->len <= 45) {
1598 /* workaround - hardware tx checksum does not work
1599 * properly with extremely small packets */
55508d60 1600 long csstart = skb_checksum_start_offset(skb);
11bc3088
SG
1601 __wsum calc = csum_partial(skb->data + csstart,
1602 skb->len - csstart, 0);
1603 *((__sum16 *)(skb->data + csstart
1604 + skb->csum_offset)) = csum_fold(calc);
1605
1606 csum = false;
1607 } else {
1608 u32 csum_preamble = smsc95xx_calc_csum_preamble(skb);
1609 skb_push(skb, 4);
00acda68 1610 cpu_to_le32s(&csum_preamble);
11bc3088
SG
1611 memcpy(skb->data, &csum_preamble, 4);
1612 }
f7b29271
SG
1613 }
1614
2f7ca802
SG
1615 skb_push(skb, 4);
1616 tx_cmd_b = (u32)(skb->len - 4);
f7b29271
SG
1617 if (csum)
1618 tx_cmd_b |= TX_CMD_B_CSUM_ENABLE;
2f7ca802
SG
1619 cpu_to_le32s(&tx_cmd_b);
1620 memcpy(skb->data, &tx_cmd_b, 4);
1621
1622 skb_push(skb, 4);
1623 tx_cmd_a = (u32)(skb->len - 8) | TX_CMD_A_FIRST_SEG_ |
1624 TX_CMD_A_LAST_SEG_;
1625 cpu_to_le32s(&tx_cmd_a);
1626 memcpy(skb->data, &tx_cmd_a, 4);
1627
1628 return skb;
1629}
1630
1631static const struct driver_info smsc95xx_info = {
1632 .description = "smsc95xx USB 2.0 Ethernet",
1633 .bind = smsc95xx_bind,
1634 .unbind = smsc95xx_unbind,
1635 .link_reset = smsc95xx_link_reset,
1636 .reset = smsc95xx_reset,
1637 .rx_fixup = smsc95xx_rx_fixup,
1638 .tx_fixup = smsc95xx_tx_fixup,
1639 .status = smsc95xx_status,
07d69d42 1640 .flags = FLAG_ETHER | FLAG_SEND_ZLP | FLAG_LINK_INTR,
2f7ca802
SG
1641};
1642
1643static const struct usb_device_id products[] = {
1644 {
1645 /* SMSC9500 USB Ethernet Device */
1646 USB_DEVICE(0x0424, 0x9500),
1647 .driver_info = (unsigned long) &smsc95xx_info,
1648 },
6f41d12b
SG
1649 {
1650 /* SMSC9505 USB Ethernet Device */
1651 USB_DEVICE(0x0424, 0x9505),
1652 .driver_info = (unsigned long) &smsc95xx_info,
1653 },
1654 {
1655 /* SMSC9500A USB Ethernet Device */
1656 USB_DEVICE(0x0424, 0x9E00),
1657 .driver_info = (unsigned long) &smsc95xx_info,
1658 },
1659 {
1660 /* SMSC9505A USB Ethernet Device */
1661 USB_DEVICE(0x0424, 0x9E01),
1662 .driver_info = (unsigned long) &smsc95xx_info,
1663 },
726474b8
SG
1664 {
1665 /* SMSC9512/9514 USB Hub & Ethernet Device */
1666 USB_DEVICE(0x0424, 0xec00),
1667 .driver_info = (unsigned long) &smsc95xx_info,
1668 },
6f41d12b
SG
1669 {
1670 /* SMSC9500 USB Ethernet Device (SAL10) */
1671 USB_DEVICE(0x0424, 0x9900),
1672 .driver_info = (unsigned long) &smsc95xx_info,
1673 },
1674 {
1675 /* SMSC9505 USB Ethernet Device (SAL10) */
1676 USB_DEVICE(0x0424, 0x9901),
1677 .driver_info = (unsigned long) &smsc95xx_info,
1678 },
1679 {
1680 /* SMSC9500A USB Ethernet Device (SAL10) */
1681 USB_DEVICE(0x0424, 0x9902),
1682 .driver_info = (unsigned long) &smsc95xx_info,
1683 },
1684 {
1685 /* SMSC9505A USB Ethernet Device (SAL10) */
1686 USB_DEVICE(0x0424, 0x9903),
1687 .driver_info = (unsigned long) &smsc95xx_info,
1688 },
1689 {
1690 /* SMSC9512/9514 USB Hub & Ethernet Device (SAL10) */
1691 USB_DEVICE(0x0424, 0x9904),
1692 .driver_info = (unsigned long) &smsc95xx_info,
1693 },
1694 {
1695 /* SMSC9500A USB Ethernet Device (HAL) */
1696 USB_DEVICE(0x0424, 0x9905),
1697 .driver_info = (unsigned long) &smsc95xx_info,
1698 },
1699 {
1700 /* SMSC9505A USB Ethernet Device (HAL) */
1701 USB_DEVICE(0x0424, 0x9906),
1702 .driver_info = (unsigned long) &smsc95xx_info,
1703 },
1704 {
1705 /* SMSC9500 USB Ethernet Device (Alternate ID) */
1706 USB_DEVICE(0x0424, 0x9907),
1707 .driver_info = (unsigned long) &smsc95xx_info,
1708 },
1709 {
1710 /* SMSC9500A USB Ethernet Device (Alternate ID) */
1711 USB_DEVICE(0x0424, 0x9908),
1712 .driver_info = (unsigned long) &smsc95xx_info,
1713 },
1714 {
1715 /* SMSC9512/9514 USB Hub & Ethernet Device (Alternate ID) */
1716 USB_DEVICE(0x0424, 0x9909),
1717 .driver_info = (unsigned long) &smsc95xx_info,
1718 },
88edaa41
SG
1719 {
1720 /* SMSC LAN9530 USB Ethernet Device */
1721 USB_DEVICE(0x0424, 0x9530),
1722 .driver_info = (unsigned long) &smsc95xx_info,
1723 },
1724 {
1725 /* SMSC LAN9730 USB Ethernet Device */
1726 USB_DEVICE(0x0424, 0x9730),
1727 .driver_info = (unsigned long) &smsc95xx_info,
1728 },
1729 {
1730 /* SMSC LAN89530 USB Ethernet Device */
1731 USB_DEVICE(0x0424, 0x9E08),
1732 .driver_info = (unsigned long) &smsc95xx_info,
1733 },
2f7ca802
SG
1734 { }, /* END */
1735};
1736MODULE_DEVICE_TABLE(usb, products);
1737
1738static struct usb_driver smsc95xx_driver = {
1739 .name = "smsc95xx",
1740 .id_table = products,
1741 .probe = usbnet_probe,
b5a04475 1742 .suspend = smsc95xx_suspend,
e0e474a8
SG
1743 .resume = smsc95xx_resume,
1744 .reset_resume = smsc95xx_resume,
2f7ca802 1745 .disconnect = usbnet_disconnect,
e1f12eb6 1746 .disable_hub_initiated_lpm = 1,
2f7ca802
SG
1747};
1748
d632eb1b 1749module_usb_driver(smsc95xx_driver);
2f7ca802
SG
1750
1751MODULE_AUTHOR("Nancy Lin");
90b24cfb 1752MODULE_AUTHOR("Steve Glendinning <steve.glendinning@shawell.net>");
2f7ca802
SG
1753MODULE_DESCRIPTION("SMSC95XX USB 2.0 Ethernet Devices");
1754MODULE_LICENSE("GPL");