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vmxnet3: add receive data ring support
[mirror_ubuntu-eoan-kernel.git] / drivers / net / vmxnet3 / vmxnet3_drv.c
CommitLineData
d1a890fa
SB		 1/*
2 * Linux driver for VMware's vmxnet3 ethernet NIC.
3 *
190af10f 4 * Copyright (C) 2008-2016, VMware, Inc. All Rights Reserved.
d1a890fa
SB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; version 2 of the License and no later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
13 * NON INFRINGEMENT. See the GNU General Public License for more
14 * details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * The full GNU General Public License is included in this distribution in
21 * the file called "COPYING".
22 *
190af10f 23 * Maintained by: pv-drivers@vmware.com
d1a890fa
SB		 24 *
25 */
26
9d9779e7 27#include <linux/module.h>
b038b040
SR		 28#include <net/ip6_checksum.h>
29
d1a890fa
SB		 30#include "vmxnet3_int.h"
31
32char vmxnet3_driver_name[] = "vmxnet3";
33#define VMXNET3_DRIVER_DESC "VMware vmxnet3 virtual NIC driver"
34
d1a890fa
SB		 35/*
36 * PCI Device ID Table
37 * Last entry must be all 0s
38 */
9baa3c34 39static const struct pci_device_id vmxnet3_pciid_table[] = {
d1a890fa
SB		 40 {PCI_VDEVICE(VMWARE, PCI_DEVICE_ID_VMWARE_VMXNET3)},
41 {0}
42};
43
44MODULE_DEVICE_TABLE(pci, vmxnet3_pciid_table);
45
09c5088e 46static int enable_mq = 1;
d1a890fa 47
f9f25026
SB		 48static void
49vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac);
50
d1a890fa
SB		 51/*
52 * Enable/Disable the given intr
53 */
54static void
55vmxnet3_enable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx)
56{
57 VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 0);
58}
59
60
61static void
62vmxnet3_disable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx)
63{
64 VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 1);
65}
66
67
68/*
69 * Enable/Disable all intrs used by the device
70 */
71static void
72vmxnet3_enable_all_intrs(struct vmxnet3_adapter *adapter)
73{
74 int i;
75
76 for (i = 0; i < adapter->intr.num_intrs; i++)
77 vmxnet3_enable_intr(adapter, i);
6929fe8a
RZ		 78 adapter->shared->devRead.intrConf.intrCtrl &=
79 cpu_to_le32(~VMXNET3_IC_DISABLE_ALL);
d1a890fa
SB		 80}
81
82
83static void
84vmxnet3_disable_all_intrs(struct vmxnet3_adapter *adapter)
85{
86 int i;
87
6929fe8a
RZ		 88 adapter->shared->devRead.intrConf.intrCtrl |=
89 cpu_to_le32(VMXNET3_IC_DISABLE_ALL);
d1a890fa
SB		 90 for (i = 0; i < adapter->intr.num_intrs; i++)
91 vmxnet3_disable_intr(adapter, i);
92}
93
94
95static void
96vmxnet3_ack_events(struct vmxnet3_adapter *adapter, u32 events)
97{
98 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_ECR, events);
99}
100
101
102static bool
103vmxnet3_tq_stopped(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
104{
09c5088e 105 return tq->stopped;
d1a890fa
SB		 106}
107
108
109static void
110vmxnet3_tq_start(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
111{
112 tq->stopped = false;
09c5088e 113 netif_start_subqueue(adapter->netdev, tq - adapter->tx_queue);
d1a890fa
SB		 114}
115
116
117static void
118vmxnet3_tq_wake(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
119{
120 tq->stopped = false;
09c5088e 121 netif_wake_subqueue(adapter->netdev, (tq - adapter->tx_queue));
d1a890fa
SB		 122}
123
124
125static void
126vmxnet3_tq_stop(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
127{
128 tq->stopped = true;
129 tq->num_stop++;
09c5088e 130 netif_stop_subqueue(adapter->netdev, (tq - adapter->tx_queue));
d1a890fa
SB		 131}
132
133
134/*
135 * Check the link state. This may start or stop the tx queue.
136 */
137static void
4a1745fc 138vmxnet3_check_link(struct vmxnet3_adapter *adapter, bool affectTxQueue)
d1a890fa
SB		 139{
140 u32 ret;
09c5088e 141 int i;
83d0feff 142 unsigned long flags;
d1a890fa 143
83d0feff 144 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa
SB		 145 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK);
146 ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
83d0feff
SB		 147 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
148
d1a890fa
SB		 149 adapter->link_speed = ret >> 16;
150 if (ret & 1) { /* Link is up. */
204a6e65
SH		 151 netdev_info(adapter->netdev, "NIC Link is Up %d Mbps\n",
152 adapter->link_speed);
6cdd20c3 153 netif_carrier_on(adapter->netdev);
d1a890fa 154
09c5088e
SB		 155 if (affectTxQueue) {
156 for (i = 0; i < adapter->num_tx_queues; i++)
157 vmxnet3_tq_start(&adapter->tx_queue[i],
158 adapter);
159 }
d1a890fa 160 } else {
204a6e65 161 netdev_info(adapter->netdev, "NIC Link is Down\n");
6cdd20c3 162 netif_carrier_off(adapter->netdev);
d1a890fa 163
09c5088e
SB		 164 if (affectTxQueue) {
165 for (i = 0; i < adapter->num_tx_queues; i++)
166 vmxnet3_tq_stop(&adapter->tx_queue[i], adapter);
167 }
d1a890fa
SB		 168 }
169}
170
d1a890fa
SB		 171static void
172vmxnet3_process_events(struct vmxnet3_adapter *adapter)
173{
09c5088e 174 int i;
e328d410 175 unsigned long flags;
115924b6 176 u32 events = le32_to_cpu(adapter->shared->ecr);
d1a890fa
SB		 177 if (!events)
178 return;
179
180 vmxnet3_ack_events(adapter, events);
181
182 /* Check if link state has changed */
183 if (events & VMXNET3_ECR_LINK)
4a1745fc 184 vmxnet3_check_link(adapter, true);
d1a890fa
SB		 185
186 /* Check if there is an error on xmit/recv queues */
187 if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) {
e328d410 188 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa
SB		 189 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
190 VMXNET3_CMD_GET_QUEUE_STATUS);
e328d410 191 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
d1a890fa 192
09c5088e
SB		 193 for (i = 0; i < adapter->num_tx_queues; i++)
194 if (adapter->tqd_start[i].status.stopped)
195 dev_err(&adapter->netdev->dev,
196 "%s: tq[%d] error 0x%x\n",
197 adapter->netdev->name, i, le32_to_cpu(
198 adapter->tqd_start[i].status.error));
199 for (i = 0; i < adapter->num_rx_queues; i++)
200 if (adapter->rqd_start[i].status.stopped)
201 dev_err(&adapter->netdev->dev,
202 "%s: rq[%d] error 0x%x\n",
203 adapter->netdev->name, i,
204 adapter->rqd_start[i].status.error);
d1a890fa
SB		 205
206 schedule_work(&adapter->work);
207 }
208}
209
115924b6
SB		 210#ifdef __BIG_ENDIAN_BITFIELD
211/*
212 * The device expects the bitfields in shared structures to be written in
213 * little endian. When CPU is big endian, the following routines are used to
214 * correctly read and write into ABI.
215 * The general technique used here is : double word bitfields are defined in
216 * opposite order for big endian architecture. Then before reading them in
217 * driver the complete double word is translated using le32_to_cpu. Similarly
218 * After the driver writes into bitfields, cpu_to_le32 is used to translate the
219 * double words into required format.
220 * In order to avoid touching bits in shared structure more than once, temporary
221 * descriptors are used. These are passed as srcDesc to following functions.
222 */
223static void vmxnet3_RxDescToCPU(const struct Vmxnet3_RxDesc *srcDesc,
224 struct Vmxnet3_RxDesc *dstDesc)
225{
226 u32 *src = (u32 *)srcDesc + 2;
227 u32 *dst = (u32 *)dstDesc + 2;
228 dstDesc->addr = le64_to_cpu(srcDesc->addr);
229 *dst = le32_to_cpu(*src);
230 dstDesc->ext1 = le32_to_cpu(srcDesc->ext1);
231}
232
233static void vmxnet3_TxDescToLe(const struct Vmxnet3_TxDesc *srcDesc,
234 struct Vmxnet3_TxDesc *dstDesc)
235{
236 int i;
237 u32 *src = (u32 *)(srcDesc + 1);
238 u32 *dst = (u32 *)(dstDesc + 1);
239
240 /* Working backwards so that the gen bit is set at the end. */
241 for (i = 2; i > 0; i--) {
242 src--;
243 dst--;
244 *dst = cpu_to_le32(*src);
245 }
246}
247
248
249static void vmxnet3_RxCompToCPU(const struct Vmxnet3_RxCompDesc *srcDesc,
250 struct Vmxnet3_RxCompDesc *dstDesc)
251{
252 int i = 0;
253 u32 *src = (u32 *)srcDesc;
254 u32 *dst = (u32 *)dstDesc;
255 for (i = 0; i < sizeof(struct Vmxnet3_RxCompDesc) / sizeof(u32); i++) {
256 *dst = le32_to_cpu(*src);
257 src++;
258 dst++;
259 }
260}
261
262
263/* Used to read bitfield values from double words. */
264static u32 get_bitfield32(const __le32 *bitfield, u32 pos, u32 size)
265{
266 u32 temp = le32_to_cpu(*bitfield);
267 u32 mask = ((1 << size) - 1) << pos;
268 temp &= mask;
269 temp >>= pos;
270 return temp;
271}
272
273
274
275#endif /* __BIG_ENDIAN_BITFIELD */
276
277#ifdef __BIG_ENDIAN_BITFIELD
278
279# define VMXNET3_TXDESC_GET_GEN(txdesc) get_bitfield32(((const __le32 *) \
280 txdesc) + VMXNET3_TXD_GEN_DWORD_SHIFT, \
281 VMXNET3_TXD_GEN_SHIFT, VMXNET3_TXD_GEN_SIZE)
282# define VMXNET3_TXDESC_GET_EOP(txdesc) get_bitfield32(((const __le32 *) \
283 txdesc) + VMXNET3_TXD_EOP_DWORD_SHIFT, \
284 VMXNET3_TXD_EOP_SHIFT, VMXNET3_TXD_EOP_SIZE)
285# define VMXNET3_TCD_GET_GEN(tcd) get_bitfield32(((const __le32 *)tcd) + \
286 VMXNET3_TCD_GEN_DWORD_SHIFT, VMXNET3_TCD_GEN_SHIFT, \
287 VMXNET3_TCD_GEN_SIZE)
288# define VMXNET3_TCD_GET_TXIDX(tcd) get_bitfield32((const __le32 *)tcd, \
289 VMXNET3_TCD_TXIDX_SHIFT, VMXNET3_TCD_TXIDX_SIZE)
290# define vmxnet3_getRxComp(dstrcd, rcd, tmp) do { \
291 (dstrcd) = (tmp); \
292 vmxnet3_RxCompToCPU((rcd), (tmp)); \
293 } while (0)
294# define vmxnet3_getRxDesc(dstrxd, rxd, tmp) do { \
295 (dstrxd) = (tmp); \
296 vmxnet3_RxDescToCPU((rxd), (tmp)); \
297 } while (0)
298
299#else
300
301# define VMXNET3_TXDESC_GET_GEN(txdesc) ((txdesc)->gen)
302# define VMXNET3_TXDESC_GET_EOP(txdesc) ((txdesc)->eop)
303# define VMXNET3_TCD_GET_GEN(tcd) ((tcd)->gen)
304# define VMXNET3_TCD_GET_TXIDX(tcd) ((tcd)->txdIdx)
305# define vmxnet3_getRxComp(dstrcd, rcd, tmp) (dstrcd) = (rcd)
306# define vmxnet3_getRxDesc(dstrxd, rxd, tmp) (dstrxd) = (rxd)
307
308#endif /* __BIG_ENDIAN_BITFIELD */
309
d1a890fa
SB		 310
311static void
312vmxnet3_unmap_tx_buf(struct vmxnet3_tx_buf_info *tbi,
313 struct pci_dev *pdev)
314{
315 if (tbi->map_type == VMXNET3_MAP_SINGLE)
b0eb57cb 316 dma_unmap_single(&pdev->dev, tbi->dma_addr, tbi->len,
d1a890fa
SB		 317 PCI_DMA_TODEVICE);
318 else if (tbi->map_type == VMXNET3_MAP_PAGE)
b0eb57cb 319 dma_unmap_page(&pdev->dev, tbi->dma_addr, tbi->len,
d1a890fa
SB		 320 PCI_DMA_TODEVICE);
321 else
322 BUG_ON(tbi->map_type != VMXNET3_MAP_NONE);
323
324 tbi->map_type = VMXNET3_MAP_NONE; /* to help debugging */
325}
326
327
328static int
329vmxnet3_unmap_pkt(u32 eop_idx, struct vmxnet3_tx_queue *tq,
330 struct pci_dev *pdev, struct vmxnet3_adapter *adapter)
331{
332 struct sk_buff *skb;
333 int entries = 0;
334
335 /* no out of order completion */
336 BUG_ON(tq->buf_info[eop_idx].sop_idx != tq->tx_ring.next2comp);
115924b6 337 BUG_ON(VMXNET3_TXDESC_GET_EOP(&(tq->tx_ring.base[eop_idx].txd)) != 1);
d1a890fa
SB		 338
339 skb = tq->buf_info[eop_idx].skb;
340 BUG_ON(skb == NULL);
341 tq->buf_info[eop_idx].skb = NULL;
342
343 VMXNET3_INC_RING_IDX_ONLY(eop_idx, tq->tx_ring.size);
344
345 while (tq->tx_ring.next2comp != eop_idx) {
346 vmxnet3_unmap_tx_buf(tq->buf_info + tq->tx_ring.next2comp,
347 pdev);
348
349 /* update next2comp w/o tx_lock. Since we are marking more,
350 * instead of less, tx ring entries avail, the worst case is
351 * that the tx routine incorrectly re-queues a pkt due to
352 * insufficient tx ring entries.
353 */
354 vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring);
355 entries++;
356 }
357
358 dev_kfree_skb_any(skb);
359 return entries;
360}
361
362
363static int
364vmxnet3_tq_tx_complete(struct vmxnet3_tx_queue *tq,
365 struct vmxnet3_adapter *adapter)
366{
367 int completed = 0;
368 union Vmxnet3_GenericDesc *gdesc;
369
370 gdesc = tq->comp_ring.base + tq->comp_ring.next2proc;
115924b6
SB		 371 while (VMXNET3_TCD_GET_GEN(&gdesc->tcd) == tq->comp_ring.gen) {
372 completed += vmxnet3_unmap_pkt(VMXNET3_TCD_GET_TXIDX(
373 &gdesc->tcd), tq, adapter->pdev,
374 adapter);
d1a890fa
SB		 375
376 vmxnet3_comp_ring_adv_next2proc(&tq->comp_ring);
377 gdesc = tq->comp_ring.base + tq->comp_ring.next2proc;
378 }
379
380 if (completed) {
381 spin_lock(&tq->tx_lock);
382 if (unlikely(vmxnet3_tq_stopped(tq, adapter) &&
383 vmxnet3_cmd_ring_desc_avail(&tq->tx_ring) >
384 VMXNET3_WAKE_QUEUE_THRESHOLD(tq) &&
385 netif_carrier_ok(adapter->netdev))) {
386 vmxnet3_tq_wake(tq, adapter);
387 }
388 spin_unlock(&tq->tx_lock);
389 }
390 return completed;
391}
392
393
394static void
395vmxnet3_tq_cleanup(struct vmxnet3_tx_queue *tq,
396 struct vmxnet3_adapter *adapter)
397{
398 int i;
399
400 while (tq->tx_ring.next2comp != tq->tx_ring.next2fill) {
401 struct vmxnet3_tx_buf_info *tbi;
d1a890fa
SB		 402
403 tbi = tq->buf_info + tq->tx_ring.next2comp;
d1a890fa
SB		 404
405 vmxnet3_unmap_tx_buf(tbi, adapter->pdev);
406 if (tbi->skb) {
407 dev_kfree_skb_any(tbi->skb);
408 tbi->skb = NULL;
409 }
410 vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring);
411 }
412
413 /* sanity check, verify all buffers are indeed unmapped and freed */
414 for (i = 0; i < tq->tx_ring.size; i++) {
415 BUG_ON(tq->buf_info[i].skb != NULL ||
416 tq->buf_info[i].map_type != VMXNET3_MAP_NONE);
417 }
418
419 tq->tx_ring.gen = VMXNET3_INIT_GEN;
420 tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0;
421
422 tq->comp_ring.gen = VMXNET3_INIT_GEN;
423 tq->comp_ring.next2proc = 0;
424}
425
426
09c5088e 427static void
d1a890fa
SB		 428vmxnet3_tq_destroy(struct vmxnet3_tx_queue *tq,
429 struct vmxnet3_adapter *adapter)
430{
431 if (tq->tx_ring.base) {
b0eb57cb
AK		 432 dma_free_coherent(&adapter->pdev->dev, tq->tx_ring.size *
433 sizeof(struct Vmxnet3_TxDesc),
434 tq->tx_ring.base, tq->tx_ring.basePA);
d1a890fa
SB		 435 tq->tx_ring.base = NULL;
436 }
437 if (tq->data_ring.base) {
3c8b3efc
SK		 438 dma_free_coherent(&adapter->pdev->dev,
439 tq->data_ring.size * tq->txdata_desc_size,
b0eb57cb 440 tq->data_ring.base, tq->data_ring.basePA);
d1a890fa
SB		 441 tq->data_ring.base = NULL;
442 }
443 if (tq->comp_ring.base) {
b0eb57cb
AK		 444 dma_free_coherent(&adapter->pdev->dev, tq->comp_ring.size *
445 sizeof(struct Vmxnet3_TxCompDesc),
446 tq->comp_ring.base, tq->comp_ring.basePA);
d1a890fa
SB		 447 tq->comp_ring.base = NULL;
448 }
b0eb57cb
AK		 449 if (tq->buf_info) {
450 dma_free_coherent(&adapter->pdev->dev,
451 tq->tx_ring.size * sizeof(tq->buf_info[0]),
452 tq->buf_info, tq->buf_info_pa);
453 tq->buf_info = NULL;
454 }
d1a890fa
SB		 455}
456
457
09c5088e
SB		 458/* Destroy all tx queues */
459void
460vmxnet3_tq_destroy_all(struct vmxnet3_adapter *adapter)
461{
462 int i;
463
464 for (i = 0; i < adapter->num_tx_queues; i++)
465 vmxnet3_tq_destroy(&adapter->tx_queue[i], adapter);
466}
467
468
d1a890fa
SB		 469static void
470vmxnet3_tq_init(struct vmxnet3_tx_queue *tq,
471 struct vmxnet3_adapter *adapter)
472{
473 int i;
474
475 /* reset the tx ring contents to 0 and reset the tx ring states */
476 memset(tq->tx_ring.base, 0, tq->tx_ring.size *
477 sizeof(struct Vmxnet3_TxDesc));
478 tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0;
479 tq->tx_ring.gen = VMXNET3_INIT_GEN;
480
3c8b3efc
SK		 481 memset(tq->data_ring.base, 0,
482 tq->data_ring.size * tq->txdata_desc_size);
d1a890fa
SB		 483
484 /* reset the tx comp ring contents to 0 and reset comp ring states */
485 memset(tq->comp_ring.base, 0, tq->comp_ring.size *
486 sizeof(struct Vmxnet3_TxCompDesc));
487 tq->comp_ring.next2proc = 0;
488 tq->comp_ring.gen = VMXNET3_INIT_GEN;
489
490 /* reset the bookkeeping data */
491 memset(tq->buf_info, 0, sizeof(tq->buf_info[0]) * tq->tx_ring.size);
492 for (i = 0; i < tq->tx_ring.size; i++)
493 tq->buf_info[i].map_type = VMXNET3_MAP_NONE;
494
495 /* stats are not reset */
496}
497
498
499static int
500vmxnet3_tq_create(struct vmxnet3_tx_queue *tq,
501 struct vmxnet3_adapter *adapter)
502{
b0eb57cb
AK		 503 size_t sz;
504
d1a890fa
SB		 505 BUG_ON(tq->tx_ring.base || tq->data_ring.base ||
506 tq->comp_ring.base || tq->buf_info);
507
b0eb57cb
AK		 508 tq->tx_ring.base = dma_alloc_coherent(&adapter->pdev->dev,
509 tq->tx_ring.size * sizeof(struct Vmxnet3_TxDesc),
510 &tq->tx_ring.basePA, GFP_KERNEL);
d1a890fa 511 if (!tq->tx_ring.base) {
204a6e65 512 netdev_err(adapter->netdev, "failed to allocate tx ring\n");
d1a890fa
SB		 513 goto err;
514 }
515
b0eb57cb 516 tq->data_ring.base = dma_alloc_coherent(&adapter->pdev->dev,
3c8b3efc 517 tq->data_ring.size * tq->txdata_desc_size,
b0eb57cb 518 &tq->data_ring.basePA, GFP_KERNEL);
d1a890fa 519 if (!tq->data_ring.base) {
3c8b3efc 520 netdev_err(adapter->netdev, "failed to allocate tx data ring\n");
d1a890fa
SB		 521 goto err;
522 }
523
b0eb57cb
AK		 524 tq->comp_ring.base = dma_alloc_coherent(&adapter->pdev->dev,
525 tq->comp_ring.size * sizeof(struct Vmxnet3_TxCompDesc),
526 &tq->comp_ring.basePA, GFP_KERNEL);
d1a890fa 527 if (!tq->comp_ring.base) {
204a6e65 528 netdev_err(adapter->netdev, "failed to allocate tx comp ring\n");
d1a890fa
SB		 529 goto err;
530 }
531
b0eb57cb
AK		 532 sz = tq->tx_ring.size * sizeof(tq->buf_info[0]);
533 tq->buf_info = dma_zalloc_coherent(&adapter->pdev->dev, sz,
534 &tq->buf_info_pa, GFP_KERNEL);
e404decb 535 if (!tq->buf_info)
d1a890fa 536 goto err;
d1a890fa
SB		 537
538 return 0;
539
540err:
541 vmxnet3_tq_destroy(tq, adapter);
542 return -ENOMEM;
543}
544
09c5088e
SB		 545static void
546vmxnet3_tq_cleanup_all(struct vmxnet3_adapter *adapter)
547{
548 int i;
549
550 for (i = 0; i < adapter->num_tx_queues; i++)
551 vmxnet3_tq_cleanup(&adapter->tx_queue[i], adapter);
552}
d1a890fa
SB		 553
554/*
555 * starting from ring->next2fill, allocate rx buffers for the given ring
556 * of the rx queue and update the rx desc. stop after @num_to_alloc buffers
557 * are allocated or allocation fails
558 */
559
560static int
561vmxnet3_rq_alloc_rx_buf(struct vmxnet3_rx_queue *rq, u32 ring_idx,
562 int num_to_alloc, struct vmxnet3_adapter *adapter)
563{
564 int num_allocated = 0;
565 struct vmxnet3_rx_buf_info *rbi_base = rq->buf_info[ring_idx];
566 struct vmxnet3_cmd_ring *ring = &rq->rx_ring[ring_idx];
567 u32 val;
568
5318d809 569 while (num_allocated <= num_to_alloc) {
d1a890fa
SB		 570 struct vmxnet3_rx_buf_info *rbi;
571 union Vmxnet3_GenericDesc *gd;
572
573 rbi = rbi_base + ring->next2fill;
574 gd = ring->base + ring->next2fill;
575
576 if (rbi->buf_type == VMXNET3_RX_BUF_SKB) {
577 if (rbi->skb == NULL) {
0d735f13
SH		 578 rbi->skb = __netdev_alloc_skb_ip_align(adapter->netdev,
579 rbi->len,
580 GFP_KERNEL);
d1a890fa
SB		 581 if (unlikely(rbi->skb == NULL)) {
582 rq->stats.rx_buf_alloc_failure++;
583 break;
584 }
d1a890fa 585
b0eb57cb
AK		 586 rbi->dma_addr = dma_map_single(
587 &adapter->pdev->dev,
d1a890fa
SB		 588 rbi->skb->data, rbi->len,
589 PCI_DMA_FROMDEVICE);
5738a09d
AK		 590 if (dma_mapping_error(&adapter->pdev->dev,
591 rbi->dma_addr)) {
592 dev_kfree_skb_any(rbi->skb);
593 rq->stats.rx_buf_alloc_failure++;
594 break;
595 }
d1a890fa
SB		 596 } else {
597 /* rx buffer skipped by the device */
598 }
599 val = VMXNET3_RXD_BTYPE_HEAD << VMXNET3_RXD_BTYPE_SHIFT;
600 } else {
601 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE ||
602 rbi->len != PAGE_SIZE);
603
604 if (rbi->page == NULL) {
605 rbi->page = alloc_page(GFP_ATOMIC);
606 if (unlikely(rbi->page == NULL)) {
607 rq->stats.rx_buf_alloc_failure++;
608 break;
609 }
b0eb57cb
AK		 610 rbi->dma_addr = dma_map_page(
611 &adapter->pdev->dev,
d1a890fa
SB		 612 rbi->page, 0, PAGE_SIZE,
613 PCI_DMA_FROMDEVICE);
5738a09d
AK		 614 if (dma_mapping_error(&adapter->pdev->dev,
615 rbi->dma_addr)) {
616 put_page(rbi->page);
617 rq->stats.rx_buf_alloc_failure++;
618 break;
619 }
d1a890fa
SB		 620 } else {
621 /* rx buffers skipped by the device */
622 }
623 val = VMXNET3_RXD_BTYPE_BODY << VMXNET3_RXD_BTYPE_SHIFT;
624 }
625
115924b6 626 gd->rxd.addr = cpu_to_le64(rbi->dma_addr);
5318d809 627 gd->dword[2] = cpu_to_le32((!ring->gen << VMXNET3_RXD_GEN_SHIFT)
115924b6 628 | val | rbi->len);
d1a890fa 629
5318d809
SB		 630 /* Fill the last buffer but dont mark it ready, or else the
631 * device will think that the queue is full */
632 if (num_allocated == num_to_alloc)
633 break;
634
635 gd->dword[2] |= cpu_to_le32(ring->gen << VMXNET3_RXD_GEN_SHIFT);
d1a890fa
SB		 636 num_allocated++;
637 vmxnet3_cmd_ring_adv_next2fill(ring);
638 }
d1a890fa 639
fdcd79b9 640 netdev_dbg(adapter->netdev,
69b9a712
SH		 641 "alloc_rx_buf: %d allocated, next2fill %u, next2comp %u\n",
642 num_allocated, ring->next2fill, ring->next2comp);
d1a890fa
SB		 643
644 /* so that the device can distinguish a full ring and an empty ring */
645 BUG_ON(num_allocated != 0 && ring->next2fill == ring->next2comp);
646
647 return num_allocated;
648}
649
650
651static void
652vmxnet3_append_frag(struct sk_buff *skb, struct Vmxnet3_RxCompDesc *rcd,
653 struct vmxnet3_rx_buf_info *rbi)
654{
655 struct skb_frag_struct *frag = skb_shinfo(skb)->frags +
656 skb_shinfo(skb)->nr_frags;
657
658 BUG_ON(skb_shinfo(skb)->nr_frags >= MAX_SKB_FRAGS);
659
0e0634d2 660 __skb_frag_set_page(frag, rbi->page);
d1a890fa 661 frag->page_offset = 0;
9e903e08
ED		 662 skb_frag_size_set(frag, rcd->len);
663 skb->data_len += rcd->len;
5e6c355c 664 skb->truesize += PAGE_SIZE;
d1a890fa
SB		 665 skb_shinfo(skb)->nr_frags++;
666}
667
668
5738a09d 669static int
d1a890fa
SB		 670vmxnet3_map_pkt(struct sk_buff *skb, struct vmxnet3_tx_ctx *ctx,
671 struct vmxnet3_tx_queue *tq, struct pci_dev *pdev,
672 struct vmxnet3_adapter *adapter)
673{
674 u32 dw2, len;
675 unsigned long buf_offset;
676 int i;
677 union Vmxnet3_GenericDesc *gdesc;
678 struct vmxnet3_tx_buf_info *tbi = NULL;
679
680 BUG_ON(ctx->copy_size > skb_headlen(skb));
681
682 /* use the previous gen bit for the SOP desc */
683 dw2 = (tq->tx_ring.gen ^ 0x1) << VMXNET3_TXD_GEN_SHIFT;
684
685 ctx->sop_txd = tq->tx_ring.base + tq->tx_ring.next2fill;
686 gdesc = ctx->sop_txd; /* both loops below can be skipped */
687
688 /* no need to map the buffer if headers are copied */
689 if (ctx->copy_size) {
115924b6 690 ctx->sop_txd->txd.addr = cpu_to_le64(tq->data_ring.basePA +
d1a890fa 691 tq->tx_ring.next2fill *
3c8b3efc 692 tq->txdata_desc_size);
115924b6 693 ctx->sop_txd->dword[2] = cpu_to_le32(dw2 | ctx->copy_size);
d1a890fa
SB		 694 ctx->sop_txd->dword[3] = 0;
695
696 tbi = tq->buf_info + tq->tx_ring.next2fill;
697 tbi->map_type = VMXNET3_MAP_NONE;
698
fdcd79b9 699 netdev_dbg(adapter->netdev,
f6965582 700 "txd[%u]: 0x%Lx 0x%x 0x%x\n",
115924b6
SB		 701 tq->tx_ring.next2fill,
702 le64_to_cpu(ctx->sop_txd->txd.addr),
d1a890fa
SB		 703 ctx->sop_txd->dword[2], ctx->sop_txd->dword[3]);
704 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
705
706 /* use the right gen for non-SOP desc */
707 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
708 }
709
710 /* linear part can use multiple tx desc if it's big */
711 len = skb_headlen(skb) - ctx->copy_size;
712 buf_offset = ctx->copy_size;
713 while (len) {
714 u32 buf_size;
715
1f4b1612
BD		 716 if (len < VMXNET3_MAX_TX_BUF_SIZE) {
717 buf_size = len;
718 dw2 |= len;
719 } else {
720 buf_size = VMXNET3_MAX_TX_BUF_SIZE;
721 /* spec says that for TxDesc.len, 0 == 2^14 */
722 }
d1a890fa
SB		 723
724 tbi = tq->buf_info + tq->tx_ring.next2fill;
725 tbi->map_type = VMXNET3_MAP_SINGLE;
b0eb57cb 726 tbi->dma_addr = dma_map_single(&adapter->pdev->dev,
d1a890fa
SB		 727 skb->data + buf_offset, buf_size,
728 PCI_DMA_TODEVICE);
5738a09d
AK		 729 if (dma_mapping_error(&adapter->pdev->dev, tbi->dma_addr))
730 return -EFAULT;
d1a890fa 731
1f4b1612 732 tbi->len = buf_size;
d1a890fa
SB		 733
734 gdesc = tq->tx_ring.base + tq->tx_ring.next2fill;
735 BUG_ON(gdesc->txd.gen == tq->tx_ring.gen);
736
115924b6 737 gdesc->txd.addr = cpu_to_le64(tbi->dma_addr);
1f4b1612 738 gdesc->dword[2] = cpu_to_le32(dw2);
d1a890fa
SB		 739 gdesc->dword[3] = 0;
740
fdcd79b9 741 netdev_dbg(adapter->netdev,
f6965582 742 "txd[%u]: 0x%Lx 0x%x 0x%x\n",
115924b6
SB		 743 tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr),
744 le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]);
d1a890fa
SB		 745 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
746 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
747
748 len -= buf_size;
749 buf_offset += buf_size;
750 }
751
752 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
9e903e08 753 const struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
a4d7e485 754 u32 buf_size;
d1a890fa 755
a4d7e485
ED		 756 buf_offset = 0;
757 len = skb_frag_size(frag);
758 while (len) {
759 tbi = tq->buf_info + tq->tx_ring.next2fill;
760 if (len < VMXNET3_MAX_TX_BUF_SIZE) {
761 buf_size = len;
762 dw2 |= len;
763 } else {
764 buf_size = VMXNET3_MAX_TX_BUF_SIZE;
765 /* spec says that for TxDesc.len, 0 == 2^14 */
766 }
767 tbi->map_type = VMXNET3_MAP_PAGE;
768 tbi->dma_addr = skb_frag_dma_map(&adapter->pdev->dev, frag,
769 buf_offset, buf_size,
770 DMA_TO_DEVICE);
5738a09d
AK		 771 if (dma_mapping_error(&adapter->pdev->dev, tbi->dma_addr))
772 return -EFAULT;
d1a890fa 773
a4d7e485 774 tbi->len = buf_size;
d1a890fa 775
a4d7e485
ED		 776 gdesc = tq->tx_ring.base + tq->tx_ring.next2fill;
777 BUG_ON(gdesc->txd.gen == tq->tx_ring.gen);
d1a890fa 778
a4d7e485
ED		 779 gdesc->txd.addr = cpu_to_le64(tbi->dma_addr);
780 gdesc->dword[2] = cpu_to_le32(dw2);
781 gdesc->dword[3] = 0;
d1a890fa 782
fdcd79b9 783 netdev_dbg(adapter->netdev,
8b429468 784 "txd[%u]: 0x%llx %u %u\n",
a4d7e485
ED		 785 tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr),
786 le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]);
787 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
788 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
789
790 len -= buf_size;
791 buf_offset += buf_size;
792 }
d1a890fa
SB		 793 }
794
795 ctx->eop_txd = gdesc;
796
797 /* set the last buf_info for the pkt */
798 tbi->skb = skb;
799 tbi->sop_idx = ctx->sop_txd - tq->tx_ring.base;
5738a09d
AK		 800
801 return 0;
d1a890fa
SB		 802}
803
804
09c5088e
SB		 805/* Init all tx queues */
806static void
807vmxnet3_tq_init_all(struct vmxnet3_adapter *adapter)
808{
809 int i;
810
811 for (i = 0; i < adapter->num_tx_queues; i++)
812 vmxnet3_tq_init(&adapter->tx_queue[i], adapter);
813}
814
815
d1a890fa 816/*
cec05562 817 * parse relevant protocol headers:
d1a890fa
SB		 818 * For a tso pkt, relevant headers are L2/3/4 including options
819 * For a pkt requesting csum offloading, they are L2/3 and may include L4
820 * if it's a TCP/UDP pkt
821 *
822 * Returns:
823 * -1: error happens during parsing
824 * 0: protocol headers parsed, but too big to be copied
825 * 1: protocol headers parsed and copied
826 *
827 * Other effects:
828 * 1. related *ctx fields are updated.
829 * 2. ctx->copy_size is # of bytes copied
cec05562 830 * 3. the portion to be copied is guaranteed to be in the linear part
d1a890fa
SB		 831 *
832 */
833static int
cec05562
NH		 834vmxnet3_parse_hdr(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
835 struct vmxnet3_tx_ctx *ctx,
836 struct vmxnet3_adapter *adapter)
d1a890fa 837{
759c9359 838 u8 protocol = 0;
d1a890fa 839
0d0b1672 840 if (ctx->mss) { /* TSO */
d1a890fa 841 ctx->eth_ip_hdr_size = skb_transport_offset(skb);
8bca5d1e 842 ctx->l4_hdr_size = tcp_hdrlen(skb);
d1a890fa
SB		 843 ctx->copy_size = ctx->eth_ip_hdr_size + ctx->l4_hdr_size;
844 } else {
d1a890fa 845 if (skb->ip_summed == CHECKSUM_PARTIAL) {
0d0b1672 846 ctx->eth_ip_hdr_size = skb_checksum_start_offset(skb);
d1a890fa
SB		 847
848 if (ctx->ipv4) {
8bca5d1e
ED		 849 const struct iphdr *iph = ip_hdr(skb);
850
759c9359
SK		 851 protocol = iph->protocol;
852 } else if (ctx->ipv6) {
853 const struct ipv6hdr *ipv6h = ipv6_hdr(skb);
854
855 protocol = ipv6h->nexthdr;
856 }
857
858 switch (protocol) {
859 case IPPROTO_TCP:
860 ctx->l4_hdr_size = tcp_hdrlen(skb);
861 break;
862 case IPPROTO_UDP:
863 ctx->l4_hdr_size = sizeof(struct udphdr);
864 break;
865 default:
d1a890fa 866 ctx->l4_hdr_size = 0;
759c9359 867 break;
d1a890fa 868 }
759c9359 869
b203262d
NH		 870 ctx->copy_size = min(ctx->eth_ip_hdr_size +
871 ctx->l4_hdr_size, skb->len);
d1a890fa
SB		 872 } else {
873 ctx->eth_ip_hdr_size = 0;
874 ctx->l4_hdr_size = 0;
875 /* copy as much as allowed */
3c8b3efc
SK		 876 ctx->copy_size = min_t(unsigned int,
877 tq->txdata_desc_size,
878 skb_headlen(skb));
d1a890fa
SB		 879 }
880
c41fcce9
SB		 881 if (skb->len <= VMXNET3_HDR_COPY_SIZE)
882 ctx->copy_size = skb->len;
883
d1a890fa
SB		 884 /* make sure headers are accessible directly */
885 if (unlikely(!pskb_may_pull(skb, ctx->copy_size)))
886 goto err;
887 }
888
3c8b3efc 889 if (unlikely(ctx->copy_size > tq->txdata_desc_size)) {
d1a890fa
SB		 890 tq->stats.oversized_hdr++;
891 ctx->copy_size = 0;
892 return 0;
893 }
894
cec05562
NH		 895 return 1;
896err:
897 return -1;
898}
899
900/*
901 * copy relevant protocol headers to the transmit ring:
902 * For a tso pkt, relevant headers are L2/3/4 including options
903 * For a pkt requesting csum offloading, they are L2/3 and may include L4
904 * if it's a TCP/UDP pkt
905 *
906 *
907 * Note that this requires that vmxnet3_parse_hdr be called first to set the
908 * appropriate bits in ctx first
909 */
910static void
911vmxnet3_copy_hdr(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
912 struct vmxnet3_tx_ctx *ctx,
913 struct vmxnet3_adapter *adapter)
914{
915 struct Vmxnet3_TxDataDesc *tdd;
916
d1a890fa
SB		 917 tdd = tq->data_ring.base + tq->tx_ring.next2fill;
918
919 memcpy(tdd->data, skb->data, ctx->copy_size);
fdcd79b9 920 netdev_dbg(adapter->netdev,
f6965582 921 "copy %u bytes to dataRing[%u]\n",
d1a890fa 922 ctx->copy_size, tq->tx_ring.next2fill);
d1a890fa
SB		 923}
924
925
926static void
927vmxnet3_prepare_tso(struct sk_buff *skb,
928 struct vmxnet3_tx_ctx *ctx)
929{
8bca5d1e
ED		 930 struct tcphdr *tcph = tcp_hdr(skb);
931
d1a890fa 932 if (ctx->ipv4) {
8bca5d1e
ED		 933 struct iphdr *iph = ip_hdr(skb);
934
d1a890fa
SB		 935 iph->check = 0;
936 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0,
937 IPPROTO_TCP, 0);
759c9359 938 } else if (ctx->ipv6) {
8bca5d1e
ED		 939 struct ipv6hdr *iph = ipv6_hdr(skb);
940
d1a890fa
SB		 941 tcph->check = ~csum_ipv6_magic(&iph->saddr, &iph->daddr, 0,
942 IPPROTO_TCP, 0);
943 }
944}
945
a4d7e485
ED		 946static int txd_estimate(const struct sk_buff *skb)
947{
948 int count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 1;
949 int i;
950
951 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
952 const struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
953
954 count += VMXNET3_TXD_NEEDED(skb_frag_size(frag));
955 }
956 return count;
957}
d1a890fa
SB		 958
959/*
960 * Transmits a pkt thru a given tq
961 * Returns:
962 * NETDEV_TX_OK: descriptors are setup successfully
25985edc 963 * NETDEV_TX_OK: error occurred, the pkt is dropped
d1a890fa
SB		 964 * NETDEV_TX_BUSY: tx ring is full, queue is stopped
965 *
966 * Side-effects:
967 * 1. tx ring may be changed
968 * 2. tq stats may be updated accordingly
969 * 3. shared->txNumDeferred may be updated
970 */
971
972static int
973vmxnet3_tq_xmit(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
974 struct vmxnet3_adapter *adapter, struct net_device *netdev)
975{
976 int ret;
977 u32 count;
978 unsigned long flags;
979 struct vmxnet3_tx_ctx ctx;
980 union Vmxnet3_GenericDesc *gdesc;
115924b6
SB		 981#ifdef __BIG_ENDIAN_BITFIELD
982 /* Use temporary descriptor to avoid touching bits multiple times */
983 union Vmxnet3_GenericDesc tempTxDesc;
984#endif
d1a890fa 985
a4d7e485 986 count = txd_estimate(skb);
d1a890fa 987
72e85c45 988 ctx.ipv4 = (vlan_get_protocol(skb) == cpu_to_be16(ETH_P_IP));
759c9359 989 ctx.ipv6 = (vlan_get_protocol(skb) == cpu_to_be16(ETH_P_IPV6));
d1a890fa
SB		 990
991 ctx.mss = skb_shinfo(skb)->gso_size;
992 if (ctx.mss) {
993 if (skb_header_cloned(skb)) {
994 if (unlikely(pskb_expand_head(skb, 0, 0,
995 GFP_ATOMIC) != 0)) {
996 tq->stats.drop_tso++;
997 goto drop_pkt;
998 }
999 tq->stats.copy_skb_header++;
1000 }
1001 vmxnet3_prepare_tso(skb, &ctx);
1002 } else {
1003 if (unlikely(count > VMXNET3_MAX_TXD_PER_PKT)) {
1004
1005 /* non-tso pkts must not use more than
1006 * VMXNET3_MAX_TXD_PER_PKT entries
1007 */
1008 if (skb_linearize(skb) != 0) {
1009 tq->stats.drop_too_many_frags++;
1010 goto drop_pkt;
1011 }
1012 tq->stats.linearized++;
1013
1014 /* recalculate the # of descriptors to use */
1015 count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 1;
1016 }
1017 }
1018
cec05562 1019 ret = vmxnet3_parse_hdr(skb, tq, &ctx, adapter);
d1a890fa
SB		 1020 if (ret >= 0) {
1021 BUG_ON(ret <= 0 && ctx.copy_size != 0);
1022 /* hdrs parsed, check against other limits */
1023 if (ctx.mss) {
1024 if (unlikely(ctx.eth_ip_hdr_size + ctx.l4_hdr_size >
1025 VMXNET3_MAX_TX_BUF_SIZE)) {
efc21d95
AB		 1026 tq->stats.drop_oversized_hdr++;
1027 goto drop_pkt;
d1a890fa
SB		 1028 }
1029 } else {
1030 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1031 if (unlikely(ctx.eth_ip_hdr_size +
1032 skb->csum_offset >
1033 VMXNET3_MAX_CSUM_OFFSET)) {
efc21d95
AB		 1034 tq->stats.drop_oversized_hdr++;
1035 goto drop_pkt;
d1a890fa
SB		 1036 }
1037 }
1038 }
1039 } else {
1040 tq->stats.drop_hdr_inspect_err++;
cec05562 1041 goto drop_pkt;
d1a890fa
SB		 1042 }
1043
cec05562
NH		 1044 spin_lock_irqsave(&tq->tx_lock, flags);
1045
1046 if (count > vmxnet3_cmd_ring_desc_avail(&tq->tx_ring)) {
1047 tq->stats.tx_ring_full++;
1048 netdev_dbg(adapter->netdev,
1049 "tx queue stopped on %s, next2comp %u"
1050 " next2fill %u\n", adapter->netdev->name,
1051 tq->tx_ring.next2comp, tq->tx_ring.next2fill);
1052
1053 vmxnet3_tq_stop(tq, adapter);
1054 spin_unlock_irqrestore(&tq->tx_lock, flags);
1055 return NETDEV_TX_BUSY;
1056 }
1057
1058
1059 vmxnet3_copy_hdr(skb, tq, &ctx, adapter);
1060
d1a890fa 1061 /* fill tx descs related to addr & len */
5738a09d
AK		 1062 if (vmxnet3_map_pkt(skb, &ctx, tq, adapter->pdev, adapter))
1063 goto unlock_drop_pkt;
d1a890fa
SB		 1064
1065 /* setup the EOP desc */
115924b6 1066 ctx.eop_txd->dword[3] = cpu_to_le32(VMXNET3_TXD_CQ | VMXNET3_TXD_EOP);
d1a890fa
SB		 1067
1068 /* setup the SOP desc */
115924b6
SB		 1069#ifdef __BIG_ENDIAN_BITFIELD
1070 gdesc = &tempTxDesc;
1071 gdesc->dword[2] = ctx.sop_txd->dword[2];
1072 gdesc->dword[3] = ctx.sop_txd->dword[3];
1073#else
d1a890fa 1074 gdesc = ctx.sop_txd;
115924b6 1075#endif
d1a890fa
SB		 1076 if (ctx.mss) {
1077 gdesc->txd.hlen = ctx.eth_ip_hdr_size + ctx.l4_hdr_size;
1078 gdesc->txd.om = VMXNET3_OM_TSO;
1079 gdesc->txd.msscof = ctx.mss;
115924b6
SB		 1080 le32_add_cpu(&tq->shared->txNumDeferred, (skb->len -
1081 gdesc->txd.hlen + ctx.mss - 1) / ctx.mss);
d1a890fa
SB		 1082 } else {
1083 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1084 gdesc->txd.hlen = ctx.eth_ip_hdr_size;
1085 gdesc->txd.om = VMXNET3_OM_CSUM;
1086 gdesc->txd.msscof = ctx.eth_ip_hdr_size +
1087 skb->csum_offset;
1088 } else {
1089 gdesc->txd.om = 0;
1090 gdesc->txd.msscof = 0;
1091 }
115924b6 1092 le32_add_cpu(&tq->shared->txNumDeferred, 1);
d1a890fa
SB		 1093 }
1094
df8a39de 1095 if (skb_vlan_tag_present(skb)) {
d1a890fa 1096 gdesc->txd.ti = 1;
df8a39de 1097 gdesc->txd.tci = skb_vlan_tag_get(skb);
d1a890fa
SB		 1098 }
1099
115924b6
SB		 1100 /* finally flips the GEN bit of the SOP desc. */
1101 gdesc->dword[2] = cpu_to_le32(le32_to_cpu(gdesc->dword[2]) ^
1102 VMXNET3_TXD_GEN);
1103#ifdef __BIG_ENDIAN_BITFIELD
1104 /* Finished updating in bitfields of Tx Desc, so write them in original
1105 * place.
1106 */
1107 vmxnet3_TxDescToLe((struct Vmxnet3_TxDesc *)gdesc,
1108 (struct Vmxnet3_TxDesc *)ctx.sop_txd);
1109 gdesc = ctx.sop_txd;
1110#endif
fdcd79b9 1111 netdev_dbg(adapter->netdev,
f6965582 1112 "txd[%u]: SOP 0x%Lx 0x%x 0x%x\n",
c2fd03a0 1113 (u32)(ctx.sop_txd -
115924b6
SB		 1114 tq->tx_ring.base), le64_to_cpu(gdesc->txd.addr),
1115 le32_to_cpu(gdesc->dword[2]), le32_to_cpu(gdesc->dword[3]));
d1a890fa
SB		 1116
1117 spin_unlock_irqrestore(&tq->tx_lock, flags);
1118
115924b6
SB		 1119 if (le32_to_cpu(tq->shared->txNumDeferred) >=
1120 le32_to_cpu(tq->shared->txThreshold)) {
d1a890fa 1121 tq->shared->txNumDeferred = 0;
09c5088e
SB		 1122 VMXNET3_WRITE_BAR0_REG(adapter,
1123 VMXNET3_REG_TXPROD + tq->qid * 8,
d1a890fa
SB		 1124 tq->tx_ring.next2fill);
1125 }
d1a890fa
SB		 1126
1127 return NETDEV_TX_OK;
1128
f955e141
DC		 1129unlock_drop_pkt:
1130 spin_unlock_irqrestore(&tq->tx_lock, flags);
d1a890fa
SB		 1131drop_pkt:
1132 tq->stats.drop_total++;
b1b71817 1133 dev_kfree_skb_any(skb);
d1a890fa
SB		 1134 return NETDEV_TX_OK;
1135}
1136
1137
1138static netdev_tx_t
1139vmxnet3_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1140{
1141 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
d1a890fa 1142
96800ee7 1143 BUG_ON(skb->queue_mapping > adapter->num_tx_queues);
1144 return vmxnet3_tq_xmit(skb,
1145 &adapter->tx_queue[skb->queue_mapping],
1146 adapter, netdev);
d1a890fa
SB		 1147}
1148
1149
1150static void
1151vmxnet3_rx_csum(struct vmxnet3_adapter *adapter,
1152 struct sk_buff *skb,
1153 union Vmxnet3_GenericDesc *gdesc)
1154{
a0d2730c 1155 if (!gdesc->rcd.cnc && adapter->netdev->features & NETIF_F_RXCSUM) {
f0d43780
SK		 1156 if (gdesc->rcd.v4 &&
1157 (le32_to_cpu(gdesc->dword[3]) &
1158 VMXNET3_RCD_CSUM_OK) == VMXNET3_RCD_CSUM_OK) {
1159 skb->ip_summed = CHECKSUM_UNNECESSARY;
1160 BUG_ON(!(gdesc->rcd.tcp || gdesc->rcd.udp));
1161 BUG_ON(gdesc->rcd.frg);
1162 } else if (gdesc->rcd.v6 && (le32_to_cpu(gdesc->dword[3]) &
1163 (1 << VMXNET3_RCD_TUC_SHIFT))) {
d1a890fa
SB		 1164 skb->ip_summed = CHECKSUM_UNNECESSARY;
1165 BUG_ON(!(gdesc->rcd.tcp || gdesc->rcd.udp));
d1a890fa
SB		 1166 BUG_ON(gdesc->rcd.frg);
1167 } else {
1168 if (gdesc->rcd.csum) {
1169 skb->csum = htons(gdesc->rcd.csum);
1170 skb->ip_summed = CHECKSUM_PARTIAL;
1171 } else {
bc8acf2c 1172 skb_checksum_none_assert(skb);
d1a890fa
SB		 1173 }
1174 }
1175 } else {
bc8acf2c 1176 skb_checksum_none_assert(skb);
d1a890fa
SB		 1177 }
1178}
1179
1180
1181static void
1182vmxnet3_rx_error(struct vmxnet3_rx_queue *rq, struct Vmxnet3_RxCompDesc *rcd,
1183 struct vmxnet3_rx_ctx *ctx, struct vmxnet3_adapter *adapter)
1184{
1185 rq->stats.drop_err++;
1186 if (!rcd->fcs)
1187 rq->stats.drop_fcs++;
1188
1189 rq->stats.drop_total++;
1190
1191 /*
1192 * We do not unmap and chain the rx buffer to the skb.
1193 * We basically pretend this buffer is not used and will be recycled
1194 * by vmxnet3_rq_alloc_rx_buf()
1195 */
1196
1197 /*
1198 * ctx->skb may be NULL if this is the first and the only one
1199 * desc for the pkt
1200 */
1201 if (ctx->skb)
1202 dev_kfree_skb_irq(ctx->skb);
1203
1204 ctx->skb = NULL;
1205}
1206
1207
45dac1d6
SB		 1208static u32
1209vmxnet3_get_hdr_len(struct vmxnet3_adapter *adapter, struct sk_buff *skb,
1210 union Vmxnet3_GenericDesc *gdesc)
1211{
1212 u32 hlen, maplen;
1213 union {
1214 void *ptr;
1215 struct ethhdr *eth;
1216 struct iphdr *ipv4;
1217 struct ipv6hdr *ipv6;
1218 struct tcphdr *tcp;
1219 } hdr;
1220 BUG_ON(gdesc->rcd.tcp == 0);
1221
1222 maplen = skb_headlen(skb);
1223 if (unlikely(sizeof(struct iphdr) + sizeof(struct tcphdr) > maplen))
1224 return 0;
1225
1226 hdr.eth = eth_hdr(skb);
1227 if (gdesc->rcd.v4) {
1228 BUG_ON(hdr.eth->h_proto != htons(ETH_P_IP));
1229 hdr.ptr += sizeof(struct ethhdr);
1230 BUG_ON(hdr.ipv4->protocol != IPPROTO_TCP);
1231 hlen = hdr.ipv4->ihl << 2;
1232 hdr.ptr += hdr.ipv4->ihl << 2;
1233 } else if (gdesc->rcd.v6) {
1234 BUG_ON(hdr.eth->h_proto != htons(ETH_P_IPV6));
1235 hdr.ptr += sizeof(struct ethhdr);
1236 /* Use an estimated value, since we also need to handle
1237 * TSO case.
1238 */
1239 if (hdr.ipv6->nexthdr != IPPROTO_TCP)
1240 return sizeof(struct ipv6hdr) + sizeof(struct tcphdr);
1241 hlen = sizeof(struct ipv6hdr);
1242 hdr.ptr += sizeof(struct ipv6hdr);
1243 } else {
1244 /* Non-IP pkt, dont estimate header length */
1245 return 0;
1246 }
1247
1248 if (hlen + sizeof(struct tcphdr) > maplen)
1249 return 0;
1250
1251 return (hlen + (hdr.tcp->doff << 2));
1252}
1253
d1a890fa
SB		 1254static int
1255vmxnet3_rq_rx_complete(struct vmxnet3_rx_queue *rq,
1256 struct vmxnet3_adapter *adapter, int quota)
1257{
215faf9c
JP		 1258 static const u32 rxprod_reg[2] = {
1259 VMXNET3_REG_RXPROD, VMXNET3_REG_RXPROD2
1260 };
0769636c 1261 u32 num_pkts = 0;
5318d809 1262 bool skip_page_frags = false;
d1a890fa
SB		 1263 struct Vmxnet3_RxCompDesc *rcd;
1264 struct vmxnet3_rx_ctx *ctx = &rq->rx_ctx;
45dac1d6 1265 u16 segCnt = 0, mss = 0;
115924b6
SB		 1266#ifdef __BIG_ENDIAN_BITFIELD
1267 struct Vmxnet3_RxDesc rxCmdDesc;
1268 struct Vmxnet3_RxCompDesc rxComp;
1269#endif
1270 vmxnet3_getRxComp(rcd, &rq->comp_ring.base[rq->comp_ring.next2proc].rcd,
1271 &rxComp);
d1a890fa
SB		 1272 while (rcd->gen == rq->comp_ring.gen) {
1273 struct vmxnet3_rx_buf_info *rbi;
5318d809
SB		 1274 struct sk_buff *skb, *new_skb = NULL;
1275 struct page *new_page = NULL;
5738a09d 1276 dma_addr_t new_dma_addr;
d1a890fa
SB		 1277 int num_to_alloc;
1278 struct Vmxnet3_RxDesc *rxd;
1279 u32 idx, ring_idx;
5318d809 1280 struct vmxnet3_cmd_ring *ring = NULL;
0769636c 1281 if (num_pkts >= quota) {
d1a890fa
SB		 1282 /* we may stop even before we see the EOP desc of
1283 * the current pkt
1284 */
1285 break;
1286 }
50a5ce3e
SK		 1287 BUG_ON(rcd->rqID != rq->qid && rcd->rqID != rq->qid2 &&
1288 rcd->rqID != rq->dataRingQid);
d1a890fa 1289 idx = rcd->rxdIdx;
50a5ce3e 1290 ring_idx = VMXNET3_GET_RING_IDX(adapter, rcd->rqID);
5318d809 1291 ring = rq->rx_ring + ring_idx;
115924b6
SB		 1292 vmxnet3_getRxDesc(rxd, &rq->rx_ring[ring_idx].base[idx].rxd,
1293 &rxCmdDesc);
d1a890fa
SB		 1294 rbi = rq->buf_info[ring_idx] + idx;
1295
115924b6
SB		 1296 BUG_ON(rxd->addr != rbi->dma_addr ||
1297 rxd->len != rbi->len);
d1a890fa
SB		 1298
1299 if (unlikely(rcd->eop && rcd->err)) {
1300 vmxnet3_rx_error(rq, rcd, ctx, adapter);
1301 goto rcd_done;
1302 }
1303
1304 if (rcd->sop) { /* first buf of the pkt */
50a5ce3e
SK		 1305 bool rxDataRingUsed;
1306 u16 len;
1307
d1a890fa 1308 BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_HEAD ||
50a5ce3e
SK		 1309 (rcd->rqID != rq->qid &&
1310 rcd->rqID != rq->dataRingQid));
d1a890fa
SB		 1311
1312 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_SKB);
1313 BUG_ON(ctx->skb != NULL || rbi->skb == NULL);
1314
1315 if (unlikely(rcd->len == 0)) {
1316 /* Pretend the rx buffer is skipped. */
1317 BUG_ON(!(rcd->sop && rcd->eop));
fdcd79b9 1318 netdev_dbg(adapter->netdev,
f6965582 1319 "rxRing[%u][%u] 0 length\n",
d1a890fa
SB		 1320 ring_idx, idx);
1321 goto rcd_done;
1322 }
1323
5318d809 1324 skip_page_frags = false;
d1a890fa 1325 ctx->skb = rbi->skb;
50a5ce3e
SK		 1326
1327 rxDataRingUsed =
1328 VMXNET3_RX_DATA_RING(adapter, rcd->rqID);
1329 len = rxDataRingUsed ? rcd->len : rbi->len;
0d735f13 1330 new_skb = netdev_alloc_skb_ip_align(adapter->netdev,
50a5ce3e 1331 len);
5318d809
SB		 1332 if (new_skb == NULL) {
1333 /* Skb allocation failed, do not handover this
1334 * skb to stack. Reuse it. Drop the existing pkt
1335 */
1336 rq->stats.rx_buf_alloc_failure++;
1337 ctx->skb = NULL;
1338 rq->stats.drop_total++;
1339 skip_page_frags = true;
1340 goto rcd_done;
1341 }
d1a890fa 1342
50a5ce3e
SK		 1343 if (rxDataRingUsed) {
1344 size_t sz;
1345
1346 BUG_ON(rcd->len > rq->data_ring.desc_size);
1347
1348 ctx->skb = new_skb;
1349 sz = rcd->rxdIdx * rq->data_ring.desc_size;
1350 memcpy(new_skb->data,
1351 &rq->data_ring.base[sz], rcd->len);
1352 } else {
1353 ctx->skb = rbi->skb;
1354
1355 new_dma_addr =
1356 dma_map_single(&adapter->pdev->dev,
1357 new_skb->data, rbi->len,
1358 PCI_DMA_FROMDEVICE);
1359 if (dma_mapping_error(&adapter->pdev->dev,
1360 new_dma_addr)) {
1361 dev_kfree_skb(new_skb);
1362 /* Skb allocation failed, do not
1363 * handover this skb to stack. Reuse
1364 * it. Drop the existing pkt.
1365 */
1366 rq->stats.rx_buf_alloc_failure++;
1367 ctx->skb = NULL;
1368 rq->stats.drop_total++;
1369 skip_page_frags = true;
1370 goto rcd_done;
1371 }
1372
1373 dma_unmap_single(&adapter->pdev->dev,
1374 rbi->dma_addr,
1375 rbi->len,
1376 PCI_DMA_FROMDEVICE);
1377
1378 /* Immediate refill */
1379 rbi->skb = new_skb;
1380 rbi->dma_addr = new_dma_addr;
1381 rxd->addr = cpu_to_le64(rbi->dma_addr);
1382 rxd->len = rbi->len;
1383 }
d1a890fa 1384
7db11f75
SH		 1385#ifdef VMXNET3_RSS
1386 if (rcd->rssType != VMXNET3_RCD_RSS_TYPE_NONE &&
1387 (adapter->netdev->features & NETIF_F_RXHASH))
2c15a154
MS		 1388 skb_set_hash(ctx->skb,
1389 le32_to_cpu(rcd->rssHash),
0b680703 1390 PKT_HASH_TYPE_L3);
7db11f75 1391#endif
d1a890fa 1392 skb_put(ctx->skb, rcd->len);
5318d809 1393
190af10f 1394 if (VMXNET3_VERSION_GE_2(adapter) &&
45dac1d6
SB		 1395 rcd->type == VMXNET3_CDTYPE_RXCOMP_LRO) {
1396 struct Vmxnet3_RxCompDescExt *rcdlro;
1397 rcdlro = (struct Vmxnet3_RxCompDescExt *)rcd;
1398
1399 segCnt = rcdlro->segCnt;
50219538 1400 WARN_ON_ONCE(segCnt == 0);
45dac1d6
SB		 1401 mss = rcdlro->mss;
1402 if (unlikely(segCnt <= 1))
1403 segCnt = 0;
1404 } else {
1405 segCnt = 0;
1406 }
d1a890fa 1407 } else {
5318d809
SB		 1408 BUG_ON(ctx->skb == NULL && !skip_page_frags);
1409
d1a890fa 1410 /* non SOP buffer must be type 1 in most cases */
5318d809
SB		 1411 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE);
1412 BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_BODY);
d1a890fa 1413
5318d809
SB		 1414 /* If an sop buffer was dropped, skip all
1415 * following non-sop fragments. They will be reused.
1416 */
1417 if (skip_page_frags)
1418 goto rcd_done;
d1a890fa 1419
c41fcce9
SB		 1420 if (rcd->len) {
1421 new_page = alloc_page(GFP_ATOMIC);
5318d809
SB		 1422 /* Replacement page frag could not be allocated.
1423 * Reuse this page. Drop the pkt and free the
1424 * skb which contained this page as a frag. Skip
1425 * processing all the following non-sop frags.
d1a890fa 1426 */
c41fcce9
SB		 1427 if (unlikely(!new_page)) {
1428 rq->stats.rx_buf_alloc_failure++;
1429 dev_kfree_skb(ctx->skb);
1430 ctx->skb = NULL;
1431 skip_page_frags = true;
1432 goto rcd_done;
1433 }
58caf637
SK		 1434 new_dma_addr = dma_map_page(&adapter->pdev->dev,
1435 new_page,
1436 0, PAGE_SIZE,
1437 PCI_DMA_FROMDEVICE);
5738a09d
AK		 1438 if (dma_mapping_error(&adapter->pdev->dev,
1439 new_dma_addr)) {
1440 put_page(new_page);
1441 rq->stats.rx_buf_alloc_failure++;
1442 dev_kfree_skb(ctx->skb);
1443 ctx->skb = NULL;
1444 skip_page_frags = true;
1445 goto rcd_done;
1446 }
5318d809 1447
b0eb57cb 1448 dma_unmap_page(&adapter->pdev->dev,
5318d809
SB		 1449 rbi->dma_addr, rbi->len,
1450 PCI_DMA_FROMDEVICE);
1451
1452 vmxnet3_append_frag(ctx->skb, rcd, rbi);
5318d809 1453
c41fcce9
SB		 1454 /* Immediate refill */
1455 rbi->page = new_page;
5738a09d 1456 rbi->dma_addr = new_dma_addr;
c41fcce9
SB		 1457 rxd->addr = cpu_to_le64(rbi->dma_addr);
1458 rxd->len = rbi->len;
1459 }
d1a890fa
SB		 1460 }
1461
5318d809 1462
d1a890fa
SB		 1463 skb = ctx->skb;
1464 if (rcd->eop) {
45dac1d6 1465 u32 mtu = adapter->netdev->mtu;
d1a890fa 1466 skb->len += skb->data_len;
d1a890fa
SB		 1467
1468 vmxnet3_rx_csum(adapter, skb,
1469 (union Vmxnet3_GenericDesc *)rcd);
1470 skb->protocol = eth_type_trans(skb, adapter->netdev);
45dac1d6
SB		 1471 if (!rcd->tcp || !adapter->lro)
1472 goto not_lro;
1473
1474 if (segCnt != 0 && mss != 0) {
1475 skb_shinfo(skb)->gso_type = rcd->v4 ?
1476 SKB_GSO_TCPV4 : SKB_GSO_TCPV6;
1477 skb_shinfo(skb)->gso_size = mss;
1478 skb_shinfo(skb)->gso_segs = segCnt;
1479 } else if (segCnt != 0 || skb->len > mtu) {
1480 u32 hlen;
1481
1482 hlen = vmxnet3_get_hdr_len(adapter, skb,
1483 (union Vmxnet3_GenericDesc *)rcd);
1484 if (hlen == 0)
1485 goto not_lro;
1486
1487 skb_shinfo(skb)->gso_type =
1488 rcd->v4 ? SKB_GSO_TCPV4 : SKB_GSO_TCPV6;
1489 if (segCnt != 0) {
1490 skb_shinfo(skb)->gso_segs = segCnt;
1491 skb_shinfo(skb)->gso_size =
1492 DIV_ROUND_UP(skb->len -
1493 hlen, segCnt);
1494 } else {
1495 skb_shinfo(skb)->gso_size = mtu - hlen;
1496 }
1497 }
1498not_lro:
72e85c45 1499 if (unlikely(rcd->ts))
86a9bad3 1500 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), rcd->tci);
72e85c45 1501
213ade8c
JG		 1502 if (adapter->netdev->features & NETIF_F_LRO)
1503 netif_receive_skb(skb);
1504 else
1505 napi_gro_receive(&rq->napi, skb);
d1a890fa 1506
d1a890fa 1507 ctx->skb = NULL;
0769636c 1508 num_pkts++;
d1a890fa
SB		 1509 }
1510
1511rcd_done:
5318d809
SB		 1512 /* device may have skipped some rx descs */
1513 ring->next2comp = idx;
1514 num_to_alloc = vmxnet3_cmd_ring_desc_avail(ring);
1515 ring = rq->rx_ring + ring_idx;
1516 while (num_to_alloc) {
1517 vmxnet3_getRxDesc(rxd, &ring->base[ring->next2fill].rxd,
1518 &rxCmdDesc);
1519 BUG_ON(!rxd->addr);
1520
1521 /* Recv desc is ready to be used by the device */
1522 rxd->gen = ring->gen;
1523 vmxnet3_cmd_ring_adv_next2fill(ring);
1524 num_to_alloc--;
1525 }
1526
1527 /* if needed, update the register */
1528 if (unlikely(rq->shared->updateRxProd)) {
1529 VMXNET3_WRITE_BAR0_REG(adapter,
96800ee7 1530 rxprod_reg[ring_idx] + rq->qid * 8,
1531 ring->next2fill);
d1a890fa
SB		 1532 }
1533
1534 vmxnet3_comp_ring_adv_next2proc(&rq->comp_ring);
115924b6 1535 vmxnet3_getRxComp(rcd,
96800ee7 1536 &rq->comp_ring.base[rq->comp_ring.next2proc].rcd, &rxComp);
d1a890fa
SB		 1537 }
1538
0769636c 1539 return num_pkts;
d1a890fa
SB		 1540}
1541
1542
1543static void
1544vmxnet3_rq_cleanup(struct vmxnet3_rx_queue *rq,
1545 struct vmxnet3_adapter *adapter)
1546{
1547 u32 i, ring_idx;
1548 struct Vmxnet3_RxDesc *rxd;
1549
1550 for (ring_idx = 0; ring_idx < 2; ring_idx++) {
1551 for (i = 0; i < rq->rx_ring[ring_idx].size; i++) {
115924b6
SB		 1552#ifdef __BIG_ENDIAN_BITFIELD
1553 struct Vmxnet3_RxDesc rxDesc;
1554#endif
1555 vmxnet3_getRxDesc(rxd,
1556 &rq->rx_ring[ring_idx].base[i].rxd, &rxDesc);
d1a890fa
SB		 1557
1558 if (rxd->btype == VMXNET3_RXD_BTYPE_HEAD &&
1559 rq->buf_info[ring_idx][i].skb) {
b0eb57cb 1560 dma_unmap_single(&adapter->pdev->dev, rxd->addr,
d1a890fa
SB		 1561 rxd->len, PCI_DMA_FROMDEVICE);
1562 dev_kfree_skb(rq->buf_info[ring_idx][i].skb);
1563 rq->buf_info[ring_idx][i].skb = NULL;
1564 } else if (rxd->btype == VMXNET3_RXD_BTYPE_BODY &&
1565 rq->buf_info[ring_idx][i].page) {
b0eb57cb 1566 dma_unmap_page(&adapter->pdev->dev, rxd->addr,
d1a890fa
SB		 1567 rxd->len, PCI_DMA_FROMDEVICE);
1568 put_page(rq->buf_info[ring_idx][i].page);
1569 rq->buf_info[ring_idx][i].page = NULL;
1570 }
1571 }
1572
1573 rq->rx_ring[ring_idx].gen = VMXNET3_INIT_GEN;
1574 rq->rx_ring[ring_idx].next2fill =
1575 rq->rx_ring[ring_idx].next2comp = 0;
d1a890fa
SB		 1576 }
1577
1578 rq->comp_ring.gen = VMXNET3_INIT_GEN;
1579 rq->comp_ring.next2proc = 0;
1580}
1581
1582
09c5088e
SB		 1583static void
1584vmxnet3_rq_cleanup_all(struct vmxnet3_adapter *adapter)
1585{
1586 int i;
1587
1588 for (i = 0; i < adapter->num_rx_queues; i++)
1589 vmxnet3_rq_cleanup(&adapter->rx_queue[i], adapter);
1590}
1591
1592
280b74f7 1593static void vmxnet3_rq_destroy(struct vmxnet3_rx_queue *rq,
1594 struct vmxnet3_adapter *adapter)
d1a890fa
SB		 1595{
1596 int i;
1597 int j;
1598
1599 /* all rx buffers must have already been freed */
1600 for (i = 0; i < 2; i++) {
1601 if (rq->buf_info[i]) {
1602 for (j = 0; j < rq->rx_ring[i].size; j++)
1603 BUG_ON(rq->buf_info[i][j].page != NULL);
1604 }
1605 }
1606
1607
d1a890fa
SB		 1608 for (i = 0; i < 2; i++) {
1609 if (rq->rx_ring[i].base) {
b0eb57cb
AK		 1610 dma_free_coherent(&adapter->pdev->dev,
1611 rq->rx_ring[i].size
1612 * sizeof(struct Vmxnet3_RxDesc),
1613 rq->rx_ring[i].base,
1614 rq->rx_ring[i].basePA);
d1a890fa
SB		 1615 rq->rx_ring[i].base = NULL;
1616 }
1617 rq->buf_info[i] = NULL;
1618 }
1619
50a5ce3e
SK		 1620 if (rq->data_ring.base) {
1621 dma_free_coherent(&adapter->pdev->dev,
1622 rq->rx_ring[0].size * rq->data_ring.desc_size,
1623 rq->data_ring.base, rq->data_ring.basePA);
1624 rq->data_ring.base = NULL;
1625 }
1626
d1a890fa 1627 if (rq->comp_ring.base) {
b0eb57cb
AK		 1628 dma_free_coherent(&adapter->pdev->dev, rq->comp_ring.size
1629 * sizeof(struct Vmxnet3_RxCompDesc),
1630 rq->comp_ring.base, rq->comp_ring.basePA);
d1a890fa
SB		 1631 rq->comp_ring.base = NULL;
1632 }
b0eb57cb
AK		 1633
1634 if (rq->buf_info[0]) {
1635 size_t sz = sizeof(struct vmxnet3_rx_buf_info) *
1636 (rq->rx_ring[0].size + rq->rx_ring[1].size);
1637 dma_free_coherent(&adapter->pdev->dev, sz, rq->buf_info[0],
1638 rq->buf_info_pa);
1639 }
d1a890fa
SB		 1640}
1641
50a5ce3e
SK		 1642void
1643vmxnet3_rq_destroy_all_rxdataring(struct vmxnet3_adapter *adapter)
1644{
1645 int i;
1646
1647 for (i = 0; i < adapter->num_rx_queues; i++) {
1648 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
1649
1650 if (rq->data_ring.base) {
1651 dma_free_coherent(&adapter->pdev->dev,
1652 (rq->rx_ring[0].size *
1653 rq->data_ring.desc_size),
1654 rq->data_ring.base,
1655 rq->data_ring.basePA);
1656 rq->data_ring.base = NULL;
1657 rq->data_ring.desc_size = 0;
1658 }
1659 }
1660}
d1a890fa
SB		 1661
1662static int
1663vmxnet3_rq_init(struct vmxnet3_rx_queue *rq,
1664 struct vmxnet3_adapter *adapter)
1665{
1666 int i;
1667
1668 /* initialize buf_info */
1669 for (i = 0; i < rq->rx_ring[0].size; i++) {
1670
1671 /* 1st buf for a pkt is skbuff */
1672 if (i % adapter->rx_buf_per_pkt == 0) {
1673 rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_SKB;
1674 rq->buf_info[0][i].len = adapter->skb_buf_size;
1675 } else { /* subsequent bufs for a pkt is frag */
1676 rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_PAGE;
1677 rq->buf_info[0][i].len = PAGE_SIZE;
1678 }
1679 }
1680 for (i = 0; i < rq->rx_ring[1].size; i++) {
1681 rq->buf_info[1][i].buf_type = VMXNET3_RX_BUF_PAGE;
1682 rq->buf_info[1][i].len = PAGE_SIZE;
1683 }
1684
1685 /* reset internal state and allocate buffers for both rings */
1686 for (i = 0; i < 2; i++) {
1687 rq->rx_ring[i].next2fill = rq->rx_ring[i].next2comp = 0;
d1a890fa
SB		 1688
1689 memset(rq->rx_ring[i].base, 0, rq->rx_ring[i].size *
1690 sizeof(struct Vmxnet3_RxDesc));
1691 rq->rx_ring[i].gen = VMXNET3_INIT_GEN;
1692 }
1693 if (vmxnet3_rq_alloc_rx_buf(rq, 0, rq->rx_ring[0].size - 1,
1694 adapter) == 0) {
1695 /* at least has 1 rx buffer for the 1st ring */
1696 return -ENOMEM;
1697 }
1698 vmxnet3_rq_alloc_rx_buf(rq, 1, rq->rx_ring[1].size - 1, adapter);
1699
1700 /* reset the comp ring */
1701 rq->comp_ring.next2proc = 0;
1702 memset(rq->comp_ring.base, 0, rq->comp_ring.size *
1703 sizeof(struct Vmxnet3_RxCompDesc));
1704 rq->comp_ring.gen = VMXNET3_INIT_GEN;
1705
1706 /* reset rxctx */
1707 rq->rx_ctx.skb = NULL;
1708
1709 /* stats are not reset */
1710 return 0;
1711}
1712
1713
09c5088e
SB		 1714static int
1715vmxnet3_rq_init_all(struct vmxnet3_adapter *adapter)
1716{
1717 int i, err = 0;
1718
1719 for (i = 0; i < adapter->num_rx_queues; i++) {
1720 err = vmxnet3_rq_init(&adapter->rx_queue[i], adapter);
1721 if (unlikely(err)) {
1722 dev_err(&adapter->netdev->dev, "%s: failed to "
1723 "initialize rx queue%i\n",
1724 adapter->netdev->name, i);
1725 break;
1726 }
1727 }
1728 return err;
1729
1730}
1731
1732
d1a890fa
SB		 1733static int
1734vmxnet3_rq_create(struct vmxnet3_rx_queue *rq, struct vmxnet3_adapter *adapter)
1735{
1736 int i;
1737 size_t sz;
1738 struct vmxnet3_rx_buf_info *bi;
1739
1740 for (i = 0; i < 2; i++) {
1741
1742 sz = rq->rx_ring[i].size * sizeof(struct Vmxnet3_RxDesc);
b0eb57cb
AK		 1743 rq->rx_ring[i].base = dma_alloc_coherent(
1744 &adapter->pdev->dev, sz,
1745 &rq->rx_ring[i].basePA,
1746 GFP_KERNEL);
d1a890fa 1747 if (!rq->rx_ring[i].base) {
204a6e65
SH		 1748 netdev_err(adapter->netdev,
1749 "failed to allocate rx ring %d\n", i);
d1a890fa
SB		 1750 goto err;
1751 }
1752 }
1753
50a5ce3e
SK		 1754 if ((adapter->rxdataring_enabled) && (rq->data_ring.desc_size != 0)) {
1755 sz = rq->rx_ring[0].size * rq->data_ring.desc_size;
1756 rq->data_ring.base =
1757 dma_alloc_coherent(&adapter->pdev->dev, sz,
1758 &rq->data_ring.basePA,
1759 GFP_KERNEL);
1760 if (!rq->data_ring.base) {
1761 netdev_err(adapter->netdev,
1762 "rx data ring will be disabled\n");
1763 adapter->rxdataring_enabled = false;
1764 }
1765 } else {
1766 rq->data_ring.base = NULL;
1767 rq->data_ring.desc_size = 0;
1768 }
1769
d1a890fa 1770 sz = rq->comp_ring.size * sizeof(struct Vmxnet3_RxCompDesc);
b0eb57cb
AK		 1771 rq->comp_ring.base = dma_alloc_coherent(&adapter->pdev->dev, sz,
1772 &rq->comp_ring.basePA,
1773 GFP_KERNEL);
d1a890fa 1774 if (!rq->comp_ring.base) {
204a6e65 1775 netdev_err(adapter->netdev, "failed to allocate rx comp ring\n");
d1a890fa
SB		 1776 goto err;
1777 }
1778
1779 sz = sizeof(struct vmxnet3_rx_buf_info) * (rq->rx_ring[0].size +
1780 rq->rx_ring[1].size);
b0eb57cb
AK		 1781 bi = dma_zalloc_coherent(&adapter->pdev->dev, sz, &rq->buf_info_pa,
1782 GFP_KERNEL);
e404decb 1783 if (!bi)
d1a890fa 1784 goto err;
e404decb 1785
d1a890fa
SB		 1786 rq->buf_info[0] = bi;
1787 rq->buf_info[1] = bi + rq->rx_ring[0].size;
1788
1789 return 0;
1790
1791err:
1792 vmxnet3_rq_destroy(rq, adapter);
1793 return -ENOMEM;
1794}
1795
1796
09c5088e
SB		 1797static int
1798vmxnet3_rq_create_all(struct vmxnet3_adapter *adapter)
1799{
1800 int i, err = 0;
1801
50a5ce3e
SK		 1802 adapter->rxdataring_enabled = VMXNET3_VERSION_GE_3(adapter);
1803
09c5088e
SB		 1804 for (i = 0; i < adapter->num_rx_queues; i++) {
1805 err = vmxnet3_rq_create(&adapter->rx_queue[i], adapter);
1806 if (unlikely(err)) {
1807 dev_err(&adapter->netdev->dev,
1808 "%s: failed to create rx queue%i\n",
1809 adapter->netdev->name, i);
1810 goto err_out;
1811 }
1812 }
50a5ce3e
SK		 1813
1814 if (!adapter->rxdataring_enabled)
1815 vmxnet3_rq_destroy_all_rxdataring(adapter);
1816
09c5088e
SB		 1817 return err;
1818err_out:
1819 vmxnet3_rq_destroy_all(adapter);
1820 return err;
1821
1822}
1823
1824/* Multiple queue aware polling function for tx and rx */
1825
d1a890fa
SB		 1826static int
1827vmxnet3_do_poll(struct vmxnet3_adapter *adapter, int budget)
1828{
09c5088e 1829 int rcd_done = 0, i;
d1a890fa
SB		 1830 if (unlikely(adapter->shared->ecr))
1831 vmxnet3_process_events(adapter);
09c5088e
SB		 1832 for (i = 0; i < adapter->num_tx_queues; i++)
1833 vmxnet3_tq_tx_complete(&adapter->tx_queue[i], adapter);
d1a890fa 1834
09c5088e
SB		 1835 for (i = 0; i < adapter->num_rx_queues; i++)
1836 rcd_done += vmxnet3_rq_rx_complete(&adapter->rx_queue[i],
1837 adapter, budget);
1838 return rcd_done;
d1a890fa
SB		 1839}
1840
1841
1842static int
1843vmxnet3_poll(struct napi_struct *napi, int budget)
1844{
09c5088e
SB		 1845 struct vmxnet3_rx_queue *rx_queue = container_of(napi,
1846 struct vmxnet3_rx_queue, napi);
1847 int rxd_done;
1848
1849 rxd_done = vmxnet3_do_poll(rx_queue->adapter, budget);
1850
1851 if (rxd_done < budget) {
1852 napi_complete(napi);
1853 vmxnet3_enable_all_intrs(rx_queue->adapter);
1854 }
1855 return rxd_done;
1856}
1857
1858/*
1859 * NAPI polling function for MSI-X mode with multiple Rx queues
1860 * Returns the # of the NAPI credit consumed (# of rx descriptors processed)
1861 */
1862
1863static int
1864vmxnet3_poll_rx_only(struct napi_struct *napi, int budget)
1865{
1866 struct vmxnet3_rx_queue *rq = container_of(napi,
1867 struct vmxnet3_rx_queue, napi);
1868 struct vmxnet3_adapter *adapter = rq->adapter;
d1a890fa
SB		 1869 int rxd_done;
1870
09c5088e
SB		 1871 /* When sharing interrupt with corresponding tx queue, process
1872 * tx completions in that queue as well
1873 */
1874 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE) {
1875 struct vmxnet3_tx_queue *tq =
1876 &adapter->tx_queue[rq - adapter->rx_queue];
1877 vmxnet3_tq_tx_complete(tq, adapter);
1878 }
1879
1880 rxd_done = vmxnet3_rq_rx_complete(rq, adapter, budget);
d1a890fa
SB		 1881
1882 if (rxd_done < budget) {
1883 napi_complete(napi);
09c5088e 1884 vmxnet3_enable_intr(adapter, rq->comp_ring.intr_idx);
d1a890fa
SB		 1885 }
1886 return rxd_done;
1887}
1888
1889
09c5088e
SB		 1890#ifdef CONFIG_PCI_MSI
1891
1892/*
1893 * Handle completion interrupts on tx queues
1894 * Returns whether or not the intr is handled
1895 */
1896
1897static irqreturn_t
1898vmxnet3_msix_tx(int irq, void *data)
1899{
1900 struct vmxnet3_tx_queue *tq = data;
1901 struct vmxnet3_adapter *adapter = tq->adapter;
1902
1903 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
1904 vmxnet3_disable_intr(adapter, tq->comp_ring.intr_idx);
1905
1906 /* Handle the case where only one irq is allocate for all tx queues */
1907 if (adapter->share_intr == VMXNET3_INTR_TXSHARE) {
1908 int i;
1909 for (i = 0; i < adapter->num_tx_queues; i++) {
1910 struct vmxnet3_tx_queue *txq = &adapter->tx_queue[i];
1911 vmxnet3_tq_tx_complete(txq, adapter);
1912 }
1913 } else {
1914 vmxnet3_tq_tx_complete(tq, adapter);
1915 }
1916 vmxnet3_enable_intr(adapter, tq->comp_ring.intr_idx);
1917
1918 return IRQ_HANDLED;
1919}
1920
1921
1922/*
1923 * Handle completion interrupts on rx queues. Returns whether or not the
1924 * intr is handled
1925 */
1926
1927static irqreturn_t
1928vmxnet3_msix_rx(int irq, void *data)
1929{
1930 struct vmxnet3_rx_queue *rq = data;
1931 struct vmxnet3_adapter *adapter = rq->adapter;
1932
1933 /* disable intr if needed */
1934 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
1935 vmxnet3_disable_intr(adapter, rq->comp_ring.intr_idx);
1936 napi_schedule(&rq->napi);
1937
1938 return IRQ_HANDLED;
1939}
1940
1941/*
1942 *----------------------------------------------------------------------------
1943 *
1944 * vmxnet3_msix_event --
1945 *
1946 * vmxnet3 msix event intr handler
1947 *
1948 * Result:
1949 * whether or not the intr is handled
1950 *
1951 *----------------------------------------------------------------------------
1952 */
1953
1954static irqreturn_t
1955vmxnet3_msix_event(int irq, void *data)
1956{
1957 struct net_device *dev = data;
1958 struct vmxnet3_adapter *adapter = netdev_priv(dev);
1959
1960 /* disable intr if needed */
1961 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
1962 vmxnet3_disable_intr(adapter, adapter->intr.event_intr_idx);
1963
1964 if (adapter->shared->ecr)
1965 vmxnet3_process_events(adapter);
1966
1967 vmxnet3_enable_intr(adapter, adapter->intr.event_intr_idx);
1968
1969 return IRQ_HANDLED;
1970}
1971
1972#endif /* CONFIG_PCI_MSI */
1973
1974
d1a890fa
SB		 1975/* Interrupt handler for vmxnet3 */
1976static irqreturn_t
1977vmxnet3_intr(int irq, void *dev_id)
1978{
1979 struct net_device *dev = dev_id;
1980 struct vmxnet3_adapter *adapter = netdev_priv(dev);
1981
09c5088e 1982 if (adapter->intr.type == VMXNET3_IT_INTX) {
d1a890fa
SB		 1983 u32 icr = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_ICR);
1984 if (unlikely(icr == 0))
1985 /* not ours */
1986 return IRQ_NONE;
1987 }
1988
1989
1990 /* disable intr if needed */
1991 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
09c5088e 1992 vmxnet3_disable_all_intrs(adapter);
d1a890fa 1993
09c5088e 1994 napi_schedule(&adapter->rx_queue[0].napi);
d1a890fa
SB		 1995
1996 return IRQ_HANDLED;
1997}
1998
1999#ifdef CONFIG_NET_POLL_CONTROLLER
2000
d1a890fa
SB		 2001/* netpoll callback. */
2002static void
2003vmxnet3_netpoll(struct net_device *netdev)
2004{
2005 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
d1a890fa 2006
d25f06ea 2007 switch (adapter->intr.type) {
0a8d8c44
AB		 2008#ifdef CONFIG_PCI_MSI
2009 case VMXNET3_IT_MSIX: {
2010 int i;
d25f06ea
NH		 2011 for (i = 0; i < adapter->num_rx_queues; i++)
2012 vmxnet3_msix_rx(0, &adapter->rx_queue[i]);
2013 break;
0a8d8c44
AB		 2014 }
2015#endif
d25f06ea
NH		 2016 case VMXNET3_IT_MSI:
2017 default:
2018 vmxnet3_intr(0, adapter->netdev);
2019 break;
2020 }
d1a890fa 2021
d1a890fa 2022}
09c5088e 2023#endif /* CONFIG_NET_POLL_CONTROLLER */
d1a890fa
SB		 2024
2025static int
2026vmxnet3_request_irqs(struct vmxnet3_adapter *adapter)
2027{
09c5088e
SB		 2028 struct vmxnet3_intr *intr = &adapter->intr;
2029 int err = 0, i;
2030 int vector = 0;
d1a890fa 2031
8f7e524c 2032#ifdef CONFIG_PCI_MSI
d1a890fa 2033 if (adapter->intr.type == VMXNET3_IT_MSIX) {
09c5088e
SB		 2034 for (i = 0; i < adapter->num_tx_queues; i++) {
2035 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) {
2036 sprintf(adapter->tx_queue[i].name, "%s-tx-%d",
2037 adapter->netdev->name, vector);
2038 err = request_irq(
2039 intr->msix_entries[vector].vector,
2040 vmxnet3_msix_tx, 0,
2041 adapter->tx_queue[i].name,
2042 &adapter->tx_queue[i]);
2043 } else {
2044 sprintf(adapter->tx_queue[i].name, "%s-rxtx-%d",
2045 adapter->netdev->name, vector);
2046 }
2047 if (err) {
2048 dev_err(&adapter->netdev->dev,
2049 "Failed to request irq for MSIX, %s, "
2050 "error %d\n",
2051 adapter->tx_queue[i].name, err);
2052 return err;
2053 }
2054
2055 /* Handle the case where only 1 MSIx was allocated for
2056 * all tx queues */
2057 if (adapter->share_intr == VMXNET3_INTR_TXSHARE) {
2058 for (; i < adapter->num_tx_queues; i++)
2059 adapter->tx_queue[i].comp_ring.intr_idx
2060 = vector;
2061 vector++;
2062 break;
2063 } else {
2064 adapter->tx_queue[i].comp_ring.intr_idx
2065 = vector++;
2066 }
2067 }
2068 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE)
2069 vector = 0;
2070
2071 for (i = 0; i < adapter->num_rx_queues; i++) {
2072 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE)
2073 sprintf(adapter->rx_queue[i].name, "%s-rx-%d",
2074 adapter->netdev->name, vector);
2075 else
2076 sprintf(adapter->rx_queue[i].name, "%s-rxtx-%d",
2077 adapter->netdev->name, vector);
2078 err = request_irq(intr->msix_entries[vector].vector,
2079 vmxnet3_msix_rx, 0,
2080 adapter->rx_queue[i].name,
2081 &(adapter->rx_queue[i]));
2082 if (err) {
204a6e65
SH		 2083 netdev_err(adapter->netdev,
2084 "Failed to request irq for MSIX, "
2085 "%s, error %d\n",
2086 adapter->rx_queue[i].name, err);
09c5088e
SB		 2087 return err;
2088 }
2089
2090 adapter->rx_queue[i].comp_ring.intr_idx = vector++;
2091 }
2092
2093 sprintf(intr->event_msi_vector_name, "%s-event-%d",
2094 adapter->netdev->name, vector);
2095 err = request_irq(intr->msix_entries[vector].vector,
2096 vmxnet3_msix_event, 0,
2097 intr->event_msi_vector_name, adapter->netdev);
2098 intr->event_intr_idx = vector;
2099
2100 } else if (intr->type == VMXNET3_IT_MSI) {
2101 adapter->num_rx_queues = 1;
d1a890fa
SB		 2102 err = request_irq(adapter->pdev->irq, vmxnet3_intr, 0,
2103 adapter->netdev->name, adapter->netdev);
09c5088e 2104 } else {
115924b6 2105#endif
09c5088e 2106 adapter->num_rx_queues = 1;
d1a890fa
SB		 2107 err = request_irq(adapter->pdev->irq, vmxnet3_intr,
2108 IRQF_SHARED, adapter->netdev->name,
2109 adapter->netdev);
09c5088e 2110#ifdef CONFIG_PCI_MSI
d1a890fa 2111 }
09c5088e
SB		 2112#endif
2113 intr->num_intrs = vector + 1;
2114 if (err) {
204a6e65
SH		 2115 netdev_err(adapter->netdev,
2116 "Failed to request irq (intr type:%d), error %d\n",
2117 intr->type, err);
09c5088e
SB		 2118 } else {
2119 /* Number of rx queues will not change after this */
2120 for (i = 0; i < adapter->num_rx_queues; i++) {
2121 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
2122 rq->qid = i;
2123 rq->qid2 = i + adapter->num_rx_queues;
50a5ce3e 2124 rq->dataRingQid = i + 2 * adapter->num_rx_queues;
09c5088e 2125 }
d1a890fa 2126
09c5088e
SB		 2127 /* init our intr settings */
2128 for (i = 0; i < intr->num_intrs; i++)
2129 intr->mod_levels[i] = UPT1_IML_ADAPTIVE;
2130 if (adapter->intr.type != VMXNET3_IT_MSIX) {
2131 adapter->intr.event_intr_idx = 0;
2132 for (i = 0; i < adapter->num_tx_queues; i++)
2133 adapter->tx_queue[i].comp_ring.intr_idx = 0;
2134 adapter->rx_queue[0].comp_ring.intr_idx = 0;
2135 }
d1a890fa 2136
204a6e65
SH		 2137 netdev_info(adapter->netdev,
2138 "intr type %u, mode %u, %u vectors allocated\n",
2139 intr->type, intr->mask_mode, intr->num_intrs);
d1a890fa
SB		 2140 }
2141
2142 return err;
2143}
2144
2145
2146static void
2147vmxnet3_free_irqs(struct vmxnet3_adapter *adapter)
2148{
09c5088e
SB		 2149 struct vmxnet3_intr *intr = &adapter->intr;
2150 BUG_ON(intr->type == VMXNET3_IT_AUTO || intr->num_intrs <= 0);
d1a890fa 2151
09c5088e 2152 switch (intr->type) {
8f7e524c 2153#ifdef CONFIG_PCI_MSI
d1a890fa
SB		 2154 case VMXNET3_IT_MSIX:
2155 {
09c5088e 2156 int i, vector = 0;
d1a890fa 2157
09c5088e
SB		 2158 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) {
2159 for (i = 0; i < adapter->num_tx_queues; i++) {
2160 free_irq(intr->msix_entries[vector++].vector,
2161 &(adapter->tx_queue[i]));
2162 if (adapter->share_intr == VMXNET3_INTR_TXSHARE)
2163 break;
2164 }
2165 }
2166
2167 for (i = 0; i < adapter->num_rx_queues; i++) {
2168 free_irq(intr->msix_entries[vector++].vector,
2169 &(adapter->rx_queue[i]));
2170 }
2171
2172 free_irq(intr->msix_entries[vector].vector,
2173 adapter->netdev);
2174 BUG_ON(vector >= intr->num_intrs);
d1a890fa
SB		 2175 break;
2176 }
8f7e524c 2177#endif
d1a890fa
SB		 2178 case VMXNET3_IT_MSI:
2179 free_irq(adapter->pdev->irq, adapter->netdev);
2180 break;
2181 case VMXNET3_IT_INTX:
2182 free_irq(adapter->pdev->irq, adapter->netdev);
2183 break;
2184 default:
c068e777 2185 BUG();
d1a890fa
SB		 2186 }
2187}
2188
d1a890fa
SB		 2189
2190static void
2191vmxnet3_restore_vlan(struct vmxnet3_adapter *adapter)
2192{
72e85c45
JG		 2193 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
2194 u16 vid;
d1a890fa 2195
72e85c45
JG		 2196 /* allow untagged pkts */
2197 VMXNET3_SET_VFTABLE_ENTRY(vfTable, 0);
2198
2199 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
2200 VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid);
d1a890fa
SB		 2201}
2202
2203
8e586137 2204static int
80d5c368 2205vmxnet3_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, u16 vid)
d1a890fa
SB		 2206{
2207 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
d1a890fa 2208
f6957f88
JG		 2209 if (!(netdev->flags & IFF_PROMISC)) {
2210 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
2211 unsigned long flags;
2212
2213 VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid);
2214 spin_lock_irqsave(&adapter->cmd_lock, flags);
2215 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2216 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
2217 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2218 }
72e85c45
JG		 2219
2220 set_bit(vid, adapter->active_vlans);
8e586137
JP		 2221
2222 return 0;
d1a890fa
SB		 2223}
2224
2225
8e586137 2226static int
80d5c368 2227vmxnet3_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, u16 vid)
d1a890fa
SB		 2228{
2229 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
d1a890fa 2230
f6957f88
JG		 2231 if (!(netdev->flags & IFF_PROMISC)) {
2232 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
2233 unsigned long flags;
2234
2235 VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid);
2236 spin_lock_irqsave(&adapter->cmd_lock, flags);
2237 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2238 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
2239 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2240 }
72e85c45
JG		 2241
2242 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 2243
2244 return 0;
d1a890fa
SB		 2245}
2246
2247
2248static u8 *
2249vmxnet3_copy_mc(struct net_device *netdev)
2250{
2251 u8 *buf = NULL;
4cd24eaf 2252 u32 sz = netdev_mc_count(netdev) * ETH_ALEN;
d1a890fa
SB		 2253
2254 /* struct Vmxnet3_RxFilterConf.mfTableLen is u16. */
2255 if (sz <= 0xffff) {
2256 /* We may be called with BH disabled */
2257 buf = kmalloc(sz, GFP_ATOMIC);
2258 if (buf) {
22bedad3 2259 struct netdev_hw_addr *ha;
567ec874 2260 int i = 0;
d1a890fa 2261
22bedad3
JP		 2262 netdev_for_each_mc_addr(ha, netdev)
2263 memcpy(buf + i++ * ETH_ALEN, ha->addr,
d1a890fa 2264 ETH_ALEN);
d1a890fa
SB		 2265 }
2266 }
2267 return buf;
2268}
2269
2270
2271static void
2272vmxnet3_set_mc(struct net_device *netdev)
2273{
2274 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
83d0feff 2275 unsigned long flags;
d1a890fa
SB		 2276 struct Vmxnet3_RxFilterConf *rxConf =
2277 &adapter->shared->devRead.rxFilterConf;
2278 u8 *new_table = NULL;
b0eb57cb 2279 dma_addr_t new_table_pa = 0;
d1a890fa
SB		 2280 u32 new_mode = VMXNET3_RXM_UCAST;
2281
72e85c45
JG		 2282 if (netdev->flags & IFF_PROMISC) {
2283 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
2284 memset(vfTable, 0, VMXNET3_VFT_SIZE * sizeof(*vfTable));
2285
d1a890fa 2286 new_mode |= VMXNET3_RXM_PROMISC;
72e85c45
JG		 2287 } else {
2288 vmxnet3_restore_vlan(adapter);
2289 }
d1a890fa
SB		 2290
2291 if (netdev->flags & IFF_BROADCAST)
2292 new_mode |= VMXNET3_RXM_BCAST;
2293
2294 if (netdev->flags & IFF_ALLMULTI)
2295 new_mode |= VMXNET3_RXM_ALL_MULTI;
2296 else
4cd24eaf 2297 if (!netdev_mc_empty(netdev)) {
d1a890fa
SB		 2298 new_table = vmxnet3_copy_mc(netdev);
2299 if (new_table) {
d37d5ec8
SK		 2300 size_t sz = netdev_mc_count(netdev) * ETH_ALEN;
2301
2302 rxConf->mfTableLen = cpu_to_le16(sz);
b0eb57cb
AK		 2303 new_table_pa = dma_map_single(
2304 &adapter->pdev->dev,
2305 new_table,
d37d5ec8 2306 sz,
b0eb57cb 2307 PCI_DMA_TODEVICE);
4ad9a64f
AK		 2308 }
2309
5738a09d
AK		 2310 if (!dma_mapping_error(&adapter->pdev->dev,
2311 new_table_pa)) {
4ad9a64f 2312 new_mode |= VMXNET3_RXM_MCAST;
b0eb57cb 2313 rxConf->mfTablePA = cpu_to_le64(new_table_pa);
d1a890fa 2314 } else {
4ad9a64f
AK		 2315 netdev_info(netdev,
2316 "failed to copy mcast list, setting ALL_MULTI\n");
d1a890fa
SB		 2317 new_mode |= VMXNET3_RXM_ALL_MULTI;
2318 }
2319 }
2320
d1a890fa
SB		 2321 if (!(new_mode & VMXNET3_RXM_MCAST)) {
2322 rxConf->mfTableLen = 0;
2323 rxConf->mfTablePA = 0;
2324 }
2325
83d0feff 2326 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa 2327 if (new_mode != rxConf->rxMode) {
115924b6 2328 rxConf->rxMode = cpu_to_le32(new_mode);
d1a890fa
SB		 2329 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2330 VMXNET3_CMD_UPDATE_RX_MODE);
72e85c45
JG		 2331 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2332 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
d1a890fa
SB		 2333 }
2334
2335 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2336 VMXNET3_CMD_UPDATE_MAC_FILTERS);
83d0feff 2337 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
d1a890fa 2338
4ad9a64f 2339 if (new_table_pa)
b0eb57cb
AK		 2340 dma_unmap_single(&adapter->pdev->dev, new_table_pa,
2341 rxConf->mfTableLen, PCI_DMA_TODEVICE);
4ad9a64f 2342 kfree(new_table);
d1a890fa
SB		 2343}
2344
09c5088e
SB		 2345void
2346vmxnet3_rq_destroy_all(struct vmxnet3_adapter *adapter)
2347{
2348 int i;
2349
2350 for (i = 0; i < adapter->num_rx_queues; i++)
2351 vmxnet3_rq_destroy(&adapter->rx_queue[i], adapter);
2352}
2353
d1a890fa
SB		 2354
2355/*
2356 * Set up driver_shared based on settings in adapter.
2357 */
2358
2359static void
2360vmxnet3_setup_driver_shared(struct vmxnet3_adapter *adapter)
2361{
2362 struct Vmxnet3_DriverShared *shared = adapter->shared;
2363 struct Vmxnet3_DSDevRead *devRead = &shared->devRead;
2364 struct Vmxnet3_TxQueueConf *tqc;
2365 struct Vmxnet3_RxQueueConf *rqc;
2366 int i;
2367
2368 memset(shared, 0, sizeof(*shared));
2369
2370 /* driver settings */
115924b6
SB		 2371 shared->magic = cpu_to_le32(VMXNET3_REV1_MAGIC);
2372 devRead->misc.driverInfo.version = cpu_to_le32(
2373 VMXNET3_DRIVER_VERSION_NUM);
d1a890fa
SB		 2374 devRead->misc.driverInfo.gos.gosBits = (sizeof(void *) == 4 ?
2375 VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64);
2376 devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX;
115924b6
SB		 2377 *((u32 *)&devRead->misc.driverInfo.gos) = cpu_to_le32(
2378 *((u32 *)&devRead->misc.driverInfo.gos));
2379 devRead->misc.driverInfo.vmxnet3RevSpt = cpu_to_le32(1);
2380 devRead->misc.driverInfo.uptVerSpt = cpu_to_le32(1);
d1a890fa 2381
b0eb57cb 2382 devRead->misc.ddPA = cpu_to_le64(adapter->adapter_pa);
115924b6 2383 devRead->misc.ddLen = cpu_to_le32(sizeof(struct vmxnet3_adapter));
d1a890fa
SB		 2384
2385 /* set up feature flags */
a0d2730c 2386 if (adapter->netdev->features & NETIF_F_RXCSUM)
3843e515 2387 devRead->misc.uptFeatures |= UPT1_F_RXCSUM;
d1a890fa 2388
a0d2730c 2389 if (adapter->netdev->features & NETIF_F_LRO) {
3843e515 2390 devRead->misc.uptFeatures |= UPT1_F_LRO;
115924b6 2391 devRead->misc.maxNumRxSG = cpu_to_le16(1 + MAX_SKB_FRAGS);
d1a890fa 2392 }
f646968f 2393 if (adapter->netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
3843e515 2394 devRead->misc.uptFeatures |= UPT1_F_RXVLAN;
d1a890fa 2395
115924b6
SB		 2396 devRead->misc.mtu = cpu_to_le32(adapter->netdev->mtu);
2397 devRead->misc.queueDescPA = cpu_to_le64(adapter->queue_desc_pa);
2398 devRead->misc.queueDescLen = cpu_to_le32(
09c5088e
SB		 2399 adapter->num_tx_queues * sizeof(struct Vmxnet3_TxQueueDesc) +
2400 adapter->num_rx_queues * sizeof(struct Vmxnet3_RxQueueDesc));
d1a890fa
SB		 2401
2402 /* tx queue settings */
09c5088e
SB		 2403 devRead->misc.numTxQueues = adapter->num_tx_queues;
2404 for (i = 0; i < adapter->num_tx_queues; i++) {
2405 struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i];
2406 BUG_ON(adapter->tx_queue[i].tx_ring.base == NULL);
2407 tqc = &adapter->tqd_start[i].conf;
2408 tqc->txRingBasePA = cpu_to_le64(tq->tx_ring.basePA);
2409 tqc->dataRingBasePA = cpu_to_le64(tq->data_ring.basePA);
2410 tqc->compRingBasePA = cpu_to_le64(tq->comp_ring.basePA);
b0eb57cb 2411 tqc->ddPA = cpu_to_le64(tq->buf_info_pa);
09c5088e
SB		 2412 tqc->txRingSize = cpu_to_le32(tq->tx_ring.size);
2413 tqc->dataRingSize = cpu_to_le32(tq->data_ring.size);
3c8b3efc 2414 tqc->txDataRingDescSize = cpu_to_le32(tq->txdata_desc_size);
09c5088e
SB		 2415 tqc->compRingSize = cpu_to_le32(tq->comp_ring.size);
2416 tqc->ddLen = cpu_to_le32(
2417 sizeof(struct vmxnet3_tx_buf_info) *
2418 tqc->txRingSize);
2419 tqc->intrIdx = tq->comp_ring.intr_idx;
2420 }
d1a890fa
SB		 2421
2422 /* rx queue settings */
09c5088e
SB		 2423 devRead->misc.numRxQueues = adapter->num_rx_queues;
2424 for (i = 0; i < adapter->num_rx_queues; i++) {
2425 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
2426 rqc = &adapter->rqd_start[i].conf;
2427 rqc->rxRingBasePA[0] = cpu_to_le64(rq->rx_ring[0].basePA);
2428 rqc->rxRingBasePA[1] = cpu_to_le64(rq->rx_ring[1].basePA);
2429 rqc->compRingBasePA = cpu_to_le64(rq->comp_ring.basePA);
b0eb57cb 2430 rqc->ddPA = cpu_to_le64(rq->buf_info_pa);
09c5088e
SB		 2431 rqc->rxRingSize[0] = cpu_to_le32(rq->rx_ring[0].size);
2432 rqc->rxRingSize[1] = cpu_to_le32(rq->rx_ring[1].size);
2433 rqc->compRingSize = cpu_to_le32(rq->comp_ring.size);
2434 rqc->ddLen = cpu_to_le32(
2435 sizeof(struct vmxnet3_rx_buf_info) *
2436 (rqc->rxRingSize[0] +
2437 rqc->rxRingSize[1]));
2438 rqc->intrIdx = rq->comp_ring.intr_idx;
50a5ce3e
SK		 2439 if (VMXNET3_VERSION_GE_3(adapter)) {
2440 rqc->rxDataRingBasePA =
2441 cpu_to_le64(rq->data_ring.basePA);
2442 rqc->rxDataRingDescSize =
2443 cpu_to_le16(rq->data_ring.desc_size);
2444 }
09c5088e
SB		 2445 }
2446
2447#ifdef VMXNET3_RSS
2448 memset(adapter->rss_conf, 0, sizeof(*adapter->rss_conf));
2449
2450 if (adapter->rss) {
2451 struct UPT1_RSSConf *rssConf = adapter->rss_conf;
66d35910 2452
09c5088e
SB		 2453 devRead->misc.uptFeatures |= UPT1_F_RSS;
2454 devRead->misc.numRxQueues = adapter->num_rx_queues;
2455 rssConf->hashType = UPT1_RSS_HASH_TYPE_TCP_IPV4 |
2456 UPT1_RSS_HASH_TYPE_IPV4 |
2457 UPT1_RSS_HASH_TYPE_TCP_IPV6 |
2458 UPT1_RSS_HASH_TYPE_IPV6;
2459 rssConf->hashFunc = UPT1_RSS_HASH_FUNC_TOEPLITZ;
2460 rssConf->hashKeySize = UPT1_RSS_MAX_KEY_SIZE;
2461 rssConf->indTableSize = VMXNET3_RSS_IND_TABLE_SIZE;
6bf79cdd 2462 netdev_rss_key_fill(rssConf->hashKey, sizeof(rssConf->hashKey));
66d35910 2463
09c5088e 2464 for (i = 0; i < rssConf->indTableSize; i++)
278bc429
BH		 2465 rssConf->indTable[i] = ethtool_rxfh_indir_default(
2466 i, adapter->num_rx_queues);
09c5088e
SB		 2467
2468 devRead->rssConfDesc.confVer = 1;
b0eb57cb
AK		 2469 devRead->rssConfDesc.confLen = cpu_to_le32(sizeof(*rssConf));
2470 devRead->rssConfDesc.confPA =
2471 cpu_to_le64(adapter->rss_conf_pa);
09c5088e
SB		 2472 }
2473
2474#endif /* VMXNET3_RSS */
d1a890fa
SB		 2475
2476 /* intr settings */
2477 devRead->intrConf.autoMask = adapter->intr.mask_mode ==
2478 VMXNET3_IMM_AUTO;
2479 devRead->intrConf.numIntrs = adapter->intr.num_intrs;
2480 for (i = 0; i < adapter->intr.num_intrs; i++)
2481 devRead->intrConf.modLevels[i] = adapter->intr.mod_levels[i];
2482
2483 devRead->intrConf.eventIntrIdx = adapter->intr.event_intr_idx;
6929fe8a 2484 devRead->intrConf.intrCtrl |= cpu_to_le32(VMXNET3_IC_DISABLE_ALL);
d1a890fa
SB		 2485
2486 /* rx filter settings */
2487 devRead->rxFilterConf.rxMode = 0;
2488 vmxnet3_restore_vlan(adapter);
f9f25026
SB		 2489 vmxnet3_write_mac_addr(adapter, adapter->netdev->dev_addr);
2490
d1a890fa
SB		 2491 /* the rest are already zeroed */
2492}
2493
2494
2495int
2496vmxnet3_activate_dev(struct vmxnet3_adapter *adapter)
2497{
09c5088e 2498 int err, i;
d1a890fa 2499 u32 ret;
83d0feff 2500 unsigned long flags;
d1a890fa 2501
fdcd79b9 2502 netdev_dbg(adapter->netdev, "%s: skb_buf_size %d, rx_buf_per_pkt %d,"
09c5088e
SB		 2503 " ring sizes %u %u %u\n", adapter->netdev->name,
2504 adapter->skb_buf_size, adapter->rx_buf_per_pkt,
2505 adapter->tx_queue[0].tx_ring.size,
2506 adapter->rx_queue[0].rx_ring[0].size,
2507 adapter->rx_queue[0].rx_ring[1].size);
2508
2509 vmxnet3_tq_init_all(adapter);
2510 err = vmxnet3_rq_init_all(adapter);
d1a890fa 2511 if (err) {
204a6e65
SH		 2512 netdev_err(adapter->netdev,
2513 "Failed to init rx queue error %d\n", err);
d1a890fa
SB		 2514 goto rq_err;
2515 }
2516
2517 err = vmxnet3_request_irqs(adapter);
2518 if (err) {
204a6e65
SH		 2519 netdev_err(adapter->netdev,
2520 "Failed to setup irq for error %d\n", err);
d1a890fa
SB		 2521 goto irq_err;
2522 }
2523
2524 vmxnet3_setup_driver_shared(adapter);
2525
115924b6
SB		 2526 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, VMXNET3_GET_ADDR_LO(
2527 adapter->shared_pa));
2528 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, VMXNET3_GET_ADDR_HI(
2529 adapter->shared_pa));
83d0feff 2530 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa
SB		 2531 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2532 VMXNET3_CMD_ACTIVATE_DEV);
2533 ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
83d0feff 2534 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
d1a890fa
SB		 2535
2536 if (ret != 0) {
204a6e65
SH		 2537 netdev_err(adapter->netdev,
2538 "Failed to activate dev: error %u\n", ret);
d1a890fa
SB		 2539 err = -EINVAL;
2540 goto activate_err;
2541 }
09c5088e
SB		 2542
2543 for (i = 0; i < adapter->num_rx_queues; i++) {
2544 VMXNET3_WRITE_BAR0_REG(adapter,
2545 VMXNET3_REG_RXPROD + i * VMXNET3_REG_ALIGN,
2546 adapter->rx_queue[i].rx_ring[0].next2fill);
2547 VMXNET3_WRITE_BAR0_REG(adapter, (VMXNET3_REG_RXPROD2 +
2548 (i * VMXNET3_REG_ALIGN)),
2549 adapter->rx_queue[i].rx_ring[1].next2fill);
2550 }
d1a890fa
SB		 2551
2552 /* Apply the rx filter settins last. */
2553 vmxnet3_set_mc(adapter->netdev);
2554
2555 /*
2556 * Check link state when first activating device. It will start the
2557 * tx queue if the link is up.
2558 */
4a1745fc 2559 vmxnet3_check_link(adapter, true);
09c5088e
SB		 2560 for (i = 0; i < adapter->num_rx_queues; i++)
2561 napi_enable(&adapter->rx_queue[i].napi);
d1a890fa
SB		 2562 vmxnet3_enable_all_intrs(adapter);
2563 clear_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state);
2564 return 0;
2565
2566activate_err:
2567 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, 0);
2568 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, 0);
2569 vmxnet3_free_irqs(adapter);
2570irq_err:
2571rq_err:
2572 /* free up buffers we allocated */
09c5088e 2573 vmxnet3_rq_cleanup_all(adapter);
d1a890fa
SB		 2574 return err;
2575}
2576
2577
2578void
2579vmxnet3_reset_dev(struct vmxnet3_adapter *adapter)
2580{
83d0feff
SB		 2581 unsigned long flags;
2582 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa 2583 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV);
83d0feff 2584 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
d1a890fa
SB		 2585}
2586
2587
2588int
2589vmxnet3_quiesce_dev(struct vmxnet3_adapter *adapter)
2590{
09c5088e 2591 int i;
83d0feff 2592 unsigned long flags;
d1a890fa
SB		 2593 if (test_and_set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state))
2594 return 0;
2595
2596
83d0feff 2597 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa
SB		 2598 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2599 VMXNET3_CMD_QUIESCE_DEV);
83d0feff 2600 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
d1a890fa
SB		 2601 vmxnet3_disable_all_intrs(adapter);
2602
09c5088e
SB		 2603 for (i = 0; i < adapter->num_rx_queues; i++)
2604 napi_disable(&adapter->rx_queue[i].napi);
d1a890fa
SB		 2605 netif_tx_disable(adapter->netdev);
2606 adapter->link_speed = 0;
2607 netif_carrier_off(adapter->netdev);
2608
09c5088e
SB		 2609 vmxnet3_tq_cleanup_all(adapter);
2610 vmxnet3_rq_cleanup_all(adapter);
d1a890fa
SB		 2611 vmxnet3_free_irqs(adapter);
2612 return 0;
2613}
2614
2615
2616static void
2617vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac)
2618{
2619 u32 tmp;
2620
2621 tmp = *(u32 *)mac;
2622 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACL, tmp);
2623
2624 tmp = (mac[5] << 8) | mac[4];
2625 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACH, tmp);
2626}
2627
2628
2629static int
2630vmxnet3_set_mac_addr(struct net_device *netdev, void *p)
2631{
2632 struct sockaddr *addr = p;
2633 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2634
2635 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2636 vmxnet3_write_mac_addr(adapter, addr->sa_data);
2637
2638 return 0;
2639}
2640
2641
2642/* ==================== initialization and cleanup routines ============ */
2643
2644static int
2645vmxnet3_alloc_pci_resources(struct vmxnet3_adapter *adapter, bool *dma64)
2646{
2647 int err;
2648 unsigned long mmio_start, mmio_len;
2649 struct pci_dev *pdev = adapter->pdev;
2650
2651 err = pci_enable_device(pdev);
2652 if (err) {
204a6e65 2653 dev_err(&pdev->dev, "Failed to enable adapter: error %d\n", err);
d1a890fa
SB		 2654 return err;
2655 }
2656
2657 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) == 0) {
2658 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) {
204a6e65
SH		 2659 dev_err(&pdev->dev,
2660 "pci_set_consistent_dma_mask failed\n");
d1a890fa
SB		 2661 err = -EIO;
2662 goto err_set_mask;
2663 }
2664 *dma64 = true;
2665 } else {
2666 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) {
204a6e65
SH		 2667 dev_err(&pdev->dev,
2668 "pci_set_dma_mask failed\n");
d1a890fa
SB		 2669 err = -EIO;
2670 goto err_set_mask;
2671 }
2672 *dma64 = false;
2673 }
2674
2675 err = pci_request_selected_regions(pdev, (1 << 2) - 1,
2676 vmxnet3_driver_name);
2677 if (err) {
204a6e65
SH		 2678 dev_err(&pdev->dev,
2679 "Failed to request region for adapter: error %d\n", err);
d1a890fa
SB		 2680 goto err_set_mask;
2681 }
2682
2683 pci_set_master(pdev);
2684
2685 mmio_start = pci_resource_start(pdev, 0);
2686 mmio_len = pci_resource_len(pdev, 0);
2687 adapter->hw_addr0 = ioremap(mmio_start, mmio_len);
2688 if (!adapter->hw_addr0) {
204a6e65 2689 dev_err(&pdev->dev, "Failed to map bar0\n");
d1a890fa
SB		 2690 err = -EIO;
2691 goto err_ioremap;
2692 }
2693
2694 mmio_start = pci_resource_start(pdev, 1);
2695 mmio_len = pci_resource_len(pdev, 1);
2696 adapter->hw_addr1 = ioremap(mmio_start, mmio_len);
2697 if (!adapter->hw_addr1) {
204a6e65 2698 dev_err(&pdev->dev, "Failed to map bar1\n");
d1a890fa
SB		 2699 err = -EIO;
2700 goto err_bar1;
2701 }
2702 return 0;
2703
2704err_bar1:
2705 iounmap(adapter->hw_addr0);
2706err_ioremap:
2707 pci_release_selected_regions(pdev, (1 << 2) - 1);
2708err_set_mask:
2709 pci_disable_device(pdev);
2710 return err;
2711}
2712
2713
2714static void
2715vmxnet3_free_pci_resources(struct vmxnet3_adapter *adapter)
2716{
2717 BUG_ON(!adapter->pdev);
2718
2719 iounmap(adapter->hw_addr0);
2720 iounmap(adapter->hw_addr1);
2721 pci_release_selected_regions(adapter->pdev, (1 << 2) - 1);
2722 pci_disable_device(adapter->pdev);
2723}
2724
2725
2726static void
2727vmxnet3_adjust_rx_ring_size(struct vmxnet3_adapter *adapter)
2728{
09c5088e
SB		 2729 size_t sz, i, ring0_size, ring1_size, comp_size;
2730 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[0];
2731
d1a890fa
SB		 2732
2733 if (adapter->netdev->mtu <= VMXNET3_MAX_SKB_BUF_SIZE -
2734 VMXNET3_MAX_ETH_HDR_SIZE) {
2735 adapter->skb_buf_size = adapter->netdev->mtu +
2736 VMXNET3_MAX_ETH_HDR_SIZE;
2737 if (adapter->skb_buf_size < VMXNET3_MIN_T0_BUF_SIZE)
2738 adapter->skb_buf_size = VMXNET3_MIN_T0_BUF_SIZE;
2739
2740 adapter->rx_buf_per_pkt = 1;
2741 } else {
2742 adapter->skb_buf_size = VMXNET3_MAX_SKB_BUF_SIZE;
2743 sz = adapter->netdev->mtu - VMXNET3_MAX_SKB_BUF_SIZE +
2744 VMXNET3_MAX_ETH_HDR_SIZE;
2745 adapter->rx_buf_per_pkt = 1 + (sz + PAGE_SIZE - 1) / PAGE_SIZE;
2746 }
2747
2748 /*
2749 * for simplicity, force the ring0 size to be a multiple of
2750 * rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN
2751 */
2752 sz = adapter->rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN;
09c5088e
SB		 2753 ring0_size = adapter->rx_queue[0].rx_ring[0].size;
2754 ring0_size = (ring0_size + sz - 1) / sz * sz;
a53255d3 2755 ring0_size = min_t(u32, ring0_size, VMXNET3_RX_RING_MAX_SIZE /
09c5088e
SB		 2756 sz * sz);
2757 ring1_size = adapter->rx_queue[0].rx_ring[1].size;
53831aa1
SK		 2758 ring1_size = (ring1_size + sz - 1) / sz * sz;
2759 ring1_size = min_t(u32, ring1_size, VMXNET3_RX_RING2_MAX_SIZE /
2760 sz * sz);
09c5088e
SB		 2761 comp_size = ring0_size + ring1_size;
2762
2763 for (i = 0; i < adapter->num_rx_queues; i++) {
2764 rq = &adapter->rx_queue[i];
2765 rq->rx_ring[0].size = ring0_size;
2766 rq->rx_ring[1].size = ring1_size;
2767 rq->comp_ring.size = comp_size;
2768 }
d1a890fa
SB		 2769}
2770
2771
2772int
2773vmxnet3_create_queues(struct vmxnet3_adapter *adapter, u32 tx_ring_size,
3c8b3efc 2774 u32 rx_ring_size, u32 rx_ring2_size,
50a5ce3e 2775 u16 txdata_desc_size, u16 rxdata_desc_size)
d1a890fa 2776{
09c5088e
SB		 2777 int err = 0, i;
2778
2779 for (i = 0; i < adapter->num_tx_queues; i++) {
2780 struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i];
2781 tq->tx_ring.size = tx_ring_size;
2782 tq->data_ring.size = tx_ring_size;
2783 tq->comp_ring.size = tx_ring_size;
3c8b3efc 2784 tq->txdata_desc_size = txdata_desc_size;
09c5088e
SB		 2785 tq->shared = &adapter->tqd_start[i].ctrl;
2786 tq->stopped = true;
2787 tq->adapter = adapter;
2788 tq->qid = i;
2789 err = vmxnet3_tq_create(tq, adapter);
2790 /*
2791 * Too late to change num_tx_queues. We cannot do away with
2792 * lesser number of queues than what we asked for
2793 */
2794 if (err)
2795 goto queue_err;
2796 }
d1a890fa 2797
09c5088e
SB		 2798 adapter->rx_queue[0].rx_ring[0].size = rx_ring_size;
2799 adapter->rx_queue[0].rx_ring[1].size = rx_ring2_size;
d1a890fa 2800 vmxnet3_adjust_rx_ring_size(adapter);
50a5ce3e
SK		 2801
2802 adapter->rxdataring_enabled = VMXNET3_VERSION_GE_3(adapter);
09c5088e
SB		 2803 for (i = 0; i < adapter->num_rx_queues; i++) {
2804 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
2805 /* qid and qid2 for rx queues will be assigned later when num
2806 * of rx queues is finalized after allocating intrs */
2807 rq->shared = &adapter->rqd_start[i].ctrl;
2808 rq->adapter = adapter;
50a5ce3e 2809 rq->data_ring.desc_size = rxdata_desc_size;
09c5088e
SB		 2810 err = vmxnet3_rq_create(rq, adapter);
2811 if (err) {
2812 if (i == 0) {
204a6e65
SH		 2813 netdev_err(adapter->netdev,
2814 "Could not allocate any rx queues. "
2815 "Aborting.\n");
09c5088e
SB		 2816 goto queue_err;
2817 } else {
204a6e65
SH		 2818 netdev_info(adapter->netdev,
2819 "Number of rx queues changed "
2820 "to : %d.\n", i);
09c5088e
SB		 2821 adapter->num_rx_queues = i;
2822 err = 0;
2823 break;
2824 }
2825 }
2826 }
50a5ce3e
SK		 2827
2828 if (!adapter->rxdataring_enabled)
2829 vmxnet3_rq_destroy_all_rxdataring(adapter);
2830
09c5088e
SB		 2831 return err;
2832queue_err:
2833 vmxnet3_tq_destroy_all(adapter);
d1a890fa
SB		 2834 return err;
2835}
2836
2837static int
2838vmxnet3_open(struct net_device *netdev)
2839{
2840 struct vmxnet3_adapter *adapter;
09c5088e 2841 int err, i;
d1a890fa
SB		 2842
2843 adapter = netdev_priv(netdev);
2844
09c5088e
SB		 2845 for (i = 0; i < adapter->num_tx_queues; i++)
2846 spin_lock_init(&adapter->tx_queue[i].tx_lock);
d1a890fa 2847
3c8b3efc
SK		 2848 if (VMXNET3_VERSION_GE_3(adapter)) {
2849 unsigned long flags;
2850 u16 txdata_desc_size;
2851
2852 spin_lock_irqsave(&adapter->cmd_lock, flags);
2853 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2854 VMXNET3_CMD_GET_TXDATA_DESC_SIZE);
2855 txdata_desc_size = VMXNET3_READ_BAR1_REG(adapter,
2856 VMXNET3_REG_CMD);
2857 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2858
2859 if ((txdata_desc_size < VMXNET3_TXDATA_DESC_MIN_SIZE) ||
2860 (txdata_desc_size > VMXNET3_TXDATA_DESC_MAX_SIZE) ||
2861 (txdata_desc_size & VMXNET3_TXDATA_DESC_SIZE_MASK)) {
2862 adapter->txdata_desc_size =
2863 sizeof(struct Vmxnet3_TxDataDesc);
2864 } else {
2865 adapter->txdata_desc_size = txdata_desc_size;
2866 }
2867 } else {
2868 adapter->txdata_desc_size = sizeof(struct Vmxnet3_TxDataDesc);
2869 }
2870
2871 err = vmxnet3_create_queues(adapter,
2872 adapter->tx_ring_size,
f00e2b0a 2873 adapter->rx_ring_size,
3c8b3efc 2874 adapter->rx_ring2_size,
50a5ce3e
SK		 2875 adapter->txdata_desc_size,
2876 adapter->rxdata_desc_size);
d1a890fa
SB		 2877 if (err)
2878 goto queue_err;
2879
2880 err = vmxnet3_activate_dev(adapter);
2881 if (err)
2882 goto activate_err;
2883
2884 return 0;
2885
2886activate_err:
09c5088e
SB		 2887 vmxnet3_rq_destroy_all(adapter);
2888 vmxnet3_tq_destroy_all(adapter);
d1a890fa
SB		 2889queue_err:
2890 return err;
2891}
2892
2893
2894static int
2895vmxnet3_close(struct net_device *netdev)
2896{
2897 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2898
2899 /*
2900 * Reset_work may be in the middle of resetting the device, wait for its
2901 * completion.
2902 */
2903 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
2904 msleep(1);
2905
2906 vmxnet3_quiesce_dev(adapter);
2907
09c5088e
SB		 2908 vmxnet3_rq_destroy_all(adapter);
2909 vmxnet3_tq_destroy_all(adapter);
d1a890fa
SB		 2910
2911 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
2912
2913
2914 return 0;
2915}
2916
2917
2918void
2919vmxnet3_force_close(struct vmxnet3_adapter *adapter)
2920{
09c5088e
SB		 2921 int i;
2922
d1a890fa
SB		 2923 /*
2924 * we must clear VMXNET3_STATE_BIT_RESETTING, otherwise
2925 * vmxnet3_close() will deadlock.
2926 */
2927 BUG_ON(test_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state));
2928
2929 /* we need to enable NAPI, otherwise dev_close will deadlock */
09c5088e
SB		 2930 for (i = 0; i < adapter->num_rx_queues; i++)
2931 napi_enable(&adapter->rx_queue[i].napi);
d1a890fa
SB		 2932 dev_close(adapter->netdev);
2933}
2934
2935
2936static int
2937vmxnet3_change_mtu(struct net_device *netdev, int new_mtu)
2938{
2939 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2940 int err = 0;
2941
2942 if (new_mtu < VMXNET3_MIN_MTU || new_mtu > VMXNET3_MAX_MTU)
2943 return -EINVAL;
2944
d1a890fa
SB		 2945 netdev->mtu = new_mtu;
2946
2947 /*
2948 * Reset_work may be in the middle of resetting the device, wait for its
2949 * completion.
2950 */
2951 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
2952 msleep(1);
2953
2954 if (netif_running(netdev)) {
2955 vmxnet3_quiesce_dev(adapter);
2956 vmxnet3_reset_dev(adapter);
2957
2958 /* we need to re-create the rx queue based on the new mtu */
09c5088e 2959 vmxnet3_rq_destroy_all(adapter);
d1a890fa 2960 vmxnet3_adjust_rx_ring_size(adapter);
09c5088e 2961 err = vmxnet3_rq_create_all(adapter);
d1a890fa 2962 if (err) {
204a6e65
SH		 2963 netdev_err(netdev,
2964 "failed to re-create rx queues, "
2965 " error %d. Closing it.\n", err);
d1a890fa
SB		 2966 goto out;
2967 }
2968
2969 err = vmxnet3_activate_dev(adapter);
2970 if (err) {
204a6e65
SH		 2971 netdev_err(netdev,
2972 "failed to re-activate, error %d. "
2973 "Closing it\n", err);
d1a890fa
SB		 2974 goto out;
2975 }
2976 }
2977
2978out:
2979 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
2980 if (err)
2981 vmxnet3_force_close(adapter);
2982
2983 return err;
2984}
2985
2986
2987static void
2988vmxnet3_declare_features(struct vmxnet3_adapter *adapter, bool dma64)
2989{
2990 struct net_device *netdev = adapter->netdev;
2991
a0d2730c 2992 netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM |
f646968f
PM		 2993 NETIF_F_HW_CSUM | NETIF_F_HW_VLAN_CTAG_TX |
2994 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_TSO | NETIF_F_TSO6 |
72e85c45 2995 NETIF_F_LRO;
a0d2730c 2996 if (dma64)
ebbf9295 2997 netdev->hw_features |= NETIF_F_HIGHDMA;
72e85c45 2998 netdev->vlan_features = netdev->hw_features &
f646968f
PM		 2999 ~(NETIF_F_HW_VLAN_CTAG_TX |
3000 NETIF_F_HW_VLAN_CTAG_RX);
3001 netdev->features = netdev->hw_features | NETIF_F_HW_VLAN_CTAG_FILTER;
d1a890fa
SB		 3002}
3003
3004
3005static void
3006vmxnet3_read_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac)
3007{
3008 u32 tmp;
3009
3010 tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACL);
3011 *(u32 *)mac = tmp;
3012
3013 tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACH);
3014 mac[4] = tmp & 0xff;
3015 mac[5] = (tmp >> 8) & 0xff;
3016}
3017
09c5088e
SB		 3018#ifdef CONFIG_PCI_MSI
3019
3020/*
3021 * Enable MSIx vectors.
3022 * Returns :
25985edc 3023 * VMXNET3_LINUX_MIN_MSIX_VECT when only minimum number of vectors required
b60b869d
AG		 3024 * were enabled.
3025 * number of vectors which were enabled otherwise (this number is greater
09c5088e
SB		 3026 * than VMXNET3_LINUX_MIN_MSIX_VECT)
3027 */
3028
3029static int
b60b869d 3030vmxnet3_acquire_msix_vectors(struct vmxnet3_adapter *adapter, int nvec)
09c5088e 3031{
c0a1be38
AG		 3032 int ret = pci_enable_msix_range(adapter->pdev,
3033 adapter->intr.msix_entries, nvec, nvec);
09c5088e 3034
c0a1be38
AG		 3035 if (ret == -ENOSPC && nvec > VMXNET3_LINUX_MIN_MSIX_VECT) {
3036 dev_err(&adapter->netdev->dev,
3037 "Failed to enable %d MSI-X, trying %d\n",
3038 nvec, VMXNET3_LINUX_MIN_MSIX_VECT);
3039
3040 ret = pci_enable_msix_range(adapter->pdev,
3041 adapter->intr.msix_entries,
3042 VMXNET3_LINUX_MIN_MSIX_VECT,
3043 VMXNET3_LINUX_MIN_MSIX_VECT);
3044 }
3045
3046 if (ret < 0) {
3047 dev_err(&adapter->netdev->dev,
3048 "Failed to enable MSI-X, error: %d\n", ret);
3049 }
3050
3051 return ret;
09c5088e
SB		 3052}
3053
3054
3055#endif /* CONFIG_PCI_MSI */
d1a890fa
SB		 3056
3057static void
3058vmxnet3_alloc_intr_resources(struct vmxnet3_adapter *adapter)
3059{
3060 u32 cfg;
e328d410 3061 unsigned long flags;
d1a890fa
SB		 3062
3063 /* intr settings */
e328d410 3064 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa
SB		 3065 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3066 VMXNET3_CMD_GET_CONF_INTR);
3067 cfg = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
e328d410 3068 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
d1a890fa
SB		 3069 adapter->intr.type = cfg & 0x3;
3070 adapter->intr.mask_mode = (cfg >> 2) & 0x3;
3071
3072 if (adapter->intr.type == VMXNET3_IT_AUTO) {
0bdc0d70
SB		 3073 adapter->intr.type = VMXNET3_IT_MSIX;
3074 }
d1a890fa 3075
8f7e524c 3076#ifdef CONFIG_PCI_MSI
0bdc0d70 3077 if (adapter->intr.type == VMXNET3_IT_MSIX) {
b60b869d
AG		 3078 int i, nvec;
3079
3080 nvec = adapter->share_intr == VMXNET3_INTR_TXSHARE ?
3081 1 : adapter->num_tx_queues;
3082 nvec += adapter->share_intr == VMXNET3_INTR_BUDDYSHARE ?
3083 0 : adapter->num_rx_queues;
3084 nvec += 1; /* for link event */
3085 nvec = nvec > VMXNET3_LINUX_MIN_MSIX_VECT ?
3086 nvec : VMXNET3_LINUX_MIN_MSIX_VECT;
3087
3088 for (i = 0; i < nvec; i++)
3089 adapter->intr.msix_entries[i].entry = i;
3090
3091 nvec = vmxnet3_acquire_msix_vectors(adapter, nvec);
3092 if (nvec < 0)
3093 goto msix_err;
3094
09c5088e
SB		 3095 /* If we cannot allocate one MSIx vector per queue
3096 * then limit the number of rx queues to 1
3097 */
b60b869d 3098 if (nvec == VMXNET3_LINUX_MIN_MSIX_VECT) {
09c5088e 3099 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE
7e96fbf2 3100 || adapter->num_rx_queues != 1) {
09c5088e 3101 adapter->share_intr = VMXNET3_INTR_TXSHARE;
204a6e65
SH		 3102 netdev_err(adapter->netdev,
3103 "Number of rx queues : 1\n");
09c5088e 3104 adapter->num_rx_queues = 1;
09c5088e 3105 }
d1a890fa 3106 }
09c5088e 3107
b60b869d
AG		 3108 adapter->intr.num_intrs = nvec;
3109 return;
3110
3111msix_err:
09c5088e 3112 /* If we cannot allocate MSIx vectors use only one rx queue */
4bad25fa
SH		 3113 dev_info(&adapter->pdev->dev,
3114 "Failed to enable MSI-X, error %d. "
b60b869d 3115 "Limiting #rx queues to 1, try MSI.\n", nvec);
09c5088e 3116
0bdc0d70
SB		 3117 adapter->intr.type = VMXNET3_IT_MSI;
3118 }
d1a890fa 3119
0bdc0d70 3120 if (adapter->intr.type == VMXNET3_IT_MSI) {
b60b869d 3121 if (!pci_enable_msi(adapter->pdev)) {
09c5088e 3122 adapter->num_rx_queues = 1;
d1a890fa 3123 adapter->intr.num_intrs = 1;
d1a890fa
SB		 3124 return;
3125 }
3126 }
0bdc0d70 3127#endif /* CONFIG_PCI_MSI */
d1a890fa 3128
09c5088e 3129 adapter->num_rx_queues = 1;
204a6e65
SH		 3130 dev_info(&adapter->netdev->dev,
3131 "Using INTx interrupt, #Rx queues: 1.\n");
d1a890fa
SB		 3132 adapter->intr.type = VMXNET3_IT_INTX;
3133
3134 /* INT-X related setting */
3135 adapter->intr.num_intrs = 1;
3136}
3137
3138
3139static void
3140vmxnet3_free_intr_resources(struct vmxnet3_adapter *adapter)
3141{
3142 if (adapter->intr.type == VMXNET3_IT_MSIX)
3143 pci_disable_msix(adapter->pdev);
3144 else if (adapter->intr.type == VMXNET3_IT_MSI)
3145 pci_disable_msi(adapter->pdev);
3146 else
3147 BUG_ON(adapter->intr.type != VMXNET3_IT_INTX);
3148}
3149
3150
3151static void
3152vmxnet3_tx_timeout(struct net_device *netdev)
3153{
3154 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3155 adapter->tx_timeout_count++;
3156
204a6e65 3157 netdev_err(adapter->netdev, "tx hang\n");
d1a890fa 3158 schedule_work(&adapter->work);
09c5088e 3159 netif_wake_queue(adapter->netdev);
d1a890fa
SB		 3160}
3161
3162
3163static void
3164vmxnet3_reset_work(struct work_struct *data)
3165{
3166 struct vmxnet3_adapter *adapter;
3167
3168 adapter = container_of(data, struct vmxnet3_adapter, work);
3169
3170 /* if another thread is resetting the device, no need to proceed */
3171 if (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
3172 return;
3173
3174 /* if the device is closed, we must leave it alone */
d9a5f210 3175 rtnl_lock();
d1a890fa 3176 if (netif_running(adapter->netdev)) {
204a6e65 3177 netdev_notice(adapter->netdev, "resetting\n");
d1a890fa
SB		 3178 vmxnet3_quiesce_dev(adapter);
3179 vmxnet3_reset_dev(adapter);
3180 vmxnet3_activate_dev(adapter);
3181 } else {
204a6e65 3182 netdev_info(adapter->netdev, "already closed\n");
d1a890fa 3183 }
d9a5f210 3184 rtnl_unlock();
d1a890fa
SB		 3185
3186 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
3187}
3188
3189
3a4751a3 3190static int
d1a890fa
SB		 3191vmxnet3_probe_device(struct pci_dev *pdev,
3192 const struct pci_device_id *id)
3193{
3194 static const struct net_device_ops vmxnet3_netdev_ops = {
3195 .ndo_open = vmxnet3_open,
3196 .ndo_stop = vmxnet3_close,
3197 .ndo_start_xmit = vmxnet3_xmit_frame,
3198 .ndo_set_mac_address = vmxnet3_set_mac_addr,
3199 .ndo_change_mtu = vmxnet3_change_mtu,
a0d2730c 3200 .ndo_set_features = vmxnet3_set_features,
95305f6c 3201 .ndo_get_stats64 = vmxnet3_get_stats64,
d1a890fa 3202 .ndo_tx_timeout = vmxnet3_tx_timeout,
afc4b13d 3203 .ndo_set_rx_mode = vmxnet3_set_mc,
d1a890fa
SB		 3204 .ndo_vlan_rx_add_vid = vmxnet3_vlan_rx_add_vid,
3205 .ndo_vlan_rx_kill_vid = vmxnet3_vlan_rx_kill_vid,
3206#ifdef CONFIG_NET_POLL_CONTROLLER
3207 .ndo_poll_controller = vmxnet3_netpoll,
3208#endif
3209 };
3210 int err;
3211 bool dma64 = false; /* stupid gcc */
3212 u32 ver;
3213 struct net_device *netdev;
3214 struct vmxnet3_adapter *adapter;
3215 u8 mac[ETH_ALEN];
09c5088e
SB		 3216 int size;
3217 int num_tx_queues;
3218 int num_rx_queues;
3219
e154b639
SB		 3220 if (!pci_msi_enabled())
3221 enable_mq = 0;
3222
09c5088e
SB		 3223#ifdef VMXNET3_RSS
3224 if (enable_mq)
3225 num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES,
3226 (int)num_online_cpus());
3227 else
3228#endif
3229 num_rx_queues = 1;
eebb02b1 3230 num_rx_queues = rounddown_pow_of_two(num_rx_queues);
09c5088e
SB		 3231
3232 if (enable_mq)
3233 num_tx_queues = min(VMXNET3_DEVICE_MAX_TX_QUEUES,
3234 (int)num_online_cpus());
3235 else
3236 num_tx_queues = 1;
3237
eebb02b1 3238 num_tx_queues = rounddown_pow_of_two(num_tx_queues);
09c5088e
SB		 3239 netdev = alloc_etherdev_mq(sizeof(struct vmxnet3_adapter),
3240 max(num_tx_queues, num_rx_queues));
204a6e65
SH		 3241 dev_info(&pdev->dev,
3242 "# of Tx queues : %d, # of Rx queues : %d\n",
3243 num_tx_queues, num_rx_queues);
d1a890fa 3244
41de8d4c 3245 if (!netdev)
d1a890fa 3246 return -ENOMEM;
d1a890fa
SB		 3247
3248 pci_set_drvdata(pdev, netdev);
3249 adapter = netdev_priv(netdev);
3250 adapter->netdev = netdev;
3251 adapter->pdev = pdev;
3252
f00e2b0a
NH		 3253 adapter->tx_ring_size = VMXNET3_DEF_TX_RING_SIZE;
3254 adapter->rx_ring_size = VMXNET3_DEF_RX_RING_SIZE;
53831aa1 3255 adapter->rx_ring2_size = VMXNET3_DEF_RX_RING2_SIZE;
f00e2b0a 3256
83d0feff 3257 spin_lock_init(&adapter->cmd_lock);
b0eb57cb
AK		 3258 adapter->adapter_pa = dma_map_single(&adapter->pdev->dev, adapter,
3259 sizeof(struct vmxnet3_adapter),
3260 PCI_DMA_TODEVICE);
5738a09d
AK		 3261 if (dma_mapping_error(&adapter->pdev->dev, adapter->adapter_pa)) {
3262 dev_err(&pdev->dev, "Failed to map dma\n");
3263 err = -EFAULT;
3264 goto err_dma_map;
3265 }
b0eb57cb
AK		 3266 adapter->shared = dma_alloc_coherent(
3267 &adapter->pdev->dev,
3268 sizeof(struct Vmxnet3_DriverShared),
3269 &adapter->shared_pa, GFP_KERNEL);
d1a890fa 3270 if (!adapter->shared) {
204a6e65 3271 dev_err(&pdev->dev, "Failed to allocate memory\n");
d1a890fa
SB		 3272 err = -ENOMEM;
3273 goto err_alloc_shared;
3274 }
3275
09c5088e
SB		 3276 adapter->num_rx_queues = num_rx_queues;
3277 adapter->num_tx_queues = num_tx_queues;
e4fabf2b 3278 adapter->rx_buf_per_pkt = 1;
09c5088e
SB		 3279
3280 size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues;
3281 size += sizeof(struct Vmxnet3_RxQueueDesc) * adapter->num_rx_queues;
b0eb57cb
AK		 3282 adapter->tqd_start = dma_alloc_coherent(&adapter->pdev->dev, size,
3283 &adapter->queue_desc_pa,
3284 GFP_KERNEL);
d1a890fa
SB		 3285
3286 if (!adapter->tqd_start) {
204a6e65 3287 dev_err(&pdev->dev, "Failed to allocate memory\n");
d1a890fa
SB		 3288 err = -ENOMEM;
3289 goto err_alloc_queue_desc;
3290 }
09c5088e 3291 adapter->rqd_start = (struct Vmxnet3_RxQueueDesc *)(adapter->tqd_start +
96800ee7 3292 adapter->num_tx_queues);
d1a890fa 3293
b0eb57cb
AK		 3294 adapter->pm_conf = dma_alloc_coherent(&adapter->pdev->dev,
3295 sizeof(struct Vmxnet3_PMConf),
3296 &adapter->pm_conf_pa,
3297 GFP_KERNEL);
d1a890fa 3298 if (adapter->pm_conf == NULL) {
d1a890fa
SB		 3299 err = -ENOMEM;
3300 goto err_alloc_pm;
3301 }
3302
09c5088e
SB		 3303#ifdef VMXNET3_RSS
3304
b0eb57cb
AK		 3305 adapter->rss_conf = dma_alloc_coherent(&adapter->pdev->dev,
3306 sizeof(struct UPT1_RSSConf),
3307 &adapter->rss_conf_pa,
3308 GFP_KERNEL);
09c5088e 3309 if (adapter->rss_conf == NULL) {
09c5088e
SB		 3310 err = -ENOMEM;
3311 goto err_alloc_rss;
3312 }
3313#endif /* VMXNET3_RSS */
3314
d1a890fa
SB		 3315 err = vmxnet3_alloc_pci_resources(adapter, &dma64);
3316 if (err < 0)
3317 goto err_alloc_pci;
3318
3319 ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_VRRS);
190af10f
SK		 3320 if (ver & (1 << VMXNET3_REV_2)) {
3321 VMXNET3_WRITE_BAR1_REG(adapter,
3322 VMXNET3_REG_VRRS,
3323 1 << VMXNET3_REV_2);
3324 adapter->version = VMXNET3_REV_2 + 1;
3325 } else if (ver & (1 << VMXNET3_REV_1)) {
3326 VMXNET3_WRITE_BAR1_REG(adapter,
3327 VMXNET3_REG_VRRS,
3328 1 << VMXNET3_REV_1);
3329 adapter->version = VMXNET3_REV_1 + 1;
d1a890fa 3330 } else {
204a6e65
SH		 3331 dev_err(&pdev->dev,
3332 "Incompatible h/w version (0x%x) for adapter\n", ver);
d1a890fa
SB		 3333 err = -EBUSY;
3334 goto err_ver;
3335 }
45dac1d6 3336 dev_dbg(&pdev->dev, "Using device version %d\n", adapter->version);
d1a890fa
SB		 3337
3338 ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_UVRS);
3339 if (ver & 1) {
3340 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_UVRS, 1);
3341 } else {
204a6e65
SH		 3342 dev_err(&pdev->dev,
3343 "Incompatible upt version (0x%x) for adapter\n", ver);
d1a890fa
SB		 3344 err = -EBUSY;
3345 goto err_ver;
3346 }
3347
e101e7dd 3348 SET_NETDEV_DEV(netdev, &pdev->dev);
d1a890fa
SB		 3349 vmxnet3_declare_features(adapter, dma64);
3350
50a5ce3e
SK		 3351 adapter->rxdata_desc_size = VMXNET3_VERSION_GE_3(adapter) ?
3352 VMXNET3_DEF_RXDATA_DESC_SIZE : 0;
3353
4db37a78
SH		 3354 if (adapter->num_tx_queues == adapter->num_rx_queues)
3355 adapter->share_intr = VMXNET3_INTR_BUDDYSHARE;
3356 else
09c5088e
SB		 3357 adapter->share_intr = VMXNET3_INTR_DONTSHARE;
3358
d1a890fa
SB		 3359 vmxnet3_alloc_intr_resources(adapter);
3360
09c5088e
SB		 3361#ifdef VMXNET3_RSS
3362 if (adapter->num_rx_queues > 1 &&
3363 adapter->intr.type == VMXNET3_IT_MSIX) {
3364 adapter->rss = true;
7db11f75
SH		 3365 netdev->hw_features |= NETIF_F_RXHASH;
3366 netdev->features |= NETIF_F_RXHASH;
204a6e65 3367 dev_dbg(&pdev->dev, "RSS is enabled.\n");
09c5088e
SB		 3368 } else {
3369 adapter->rss = false;
3370 }
3371#endif
3372
d1a890fa
SB		 3373 vmxnet3_read_mac_addr(adapter, mac);
3374 memcpy(netdev->dev_addr, mac, netdev->addr_len);
3375
3376 netdev->netdev_ops = &vmxnet3_netdev_ops;
d1a890fa 3377 vmxnet3_set_ethtool_ops(netdev);
09c5088e 3378 netdev->watchdog_timeo = 5 * HZ;
d1a890fa
SB		 3379
3380 INIT_WORK(&adapter->work, vmxnet3_reset_work);
e3bc4ffb 3381 set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state);
d1a890fa 3382
09c5088e
SB		 3383 if (adapter->intr.type == VMXNET3_IT_MSIX) {
3384 int i;
3385 for (i = 0; i < adapter->num_rx_queues; i++) {
3386 netif_napi_add(adapter->netdev,
3387 &adapter->rx_queue[i].napi,
3388 vmxnet3_poll_rx_only, 64);
3389 }
3390 } else {
3391 netif_napi_add(adapter->netdev, &adapter->rx_queue[0].napi,
3392 vmxnet3_poll, 64);
3393 }
3394
3395 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
3396 netif_set_real_num_rx_queues(adapter->netdev, adapter->num_rx_queues);
3397
6cdd20c3 3398 netif_carrier_off(netdev);
d1a890fa
SB		 3399 err = register_netdev(netdev);
3400
3401 if (err) {
204a6e65 3402 dev_err(&pdev->dev, "Failed to register adapter\n");
d1a890fa
SB		 3403 goto err_register;
3404 }
3405
4a1745fc 3406 vmxnet3_check_link(adapter, false);
d1a890fa
SB		 3407 return 0;
3408
3409err_register:
3410 vmxnet3_free_intr_resources(adapter);
3411err_ver:
3412 vmxnet3_free_pci_resources(adapter);
3413err_alloc_pci:
09c5088e 3414#ifdef VMXNET3_RSS
b0eb57cb
AK		 3415 dma_free_coherent(&adapter->pdev->dev, sizeof(struct UPT1_RSSConf),
3416 adapter->rss_conf, adapter->rss_conf_pa);
09c5088e
SB		 3417err_alloc_rss:
3418#endif
b0eb57cb
AK		 3419 dma_free_coherent(&adapter->pdev->dev, sizeof(struct Vmxnet3_PMConf),
3420 adapter->pm_conf, adapter->pm_conf_pa);
d1a890fa 3421err_alloc_pm:
b0eb57cb
AK		 3422 dma_free_coherent(&adapter->pdev->dev, size, adapter->tqd_start,
3423 adapter->queue_desc_pa);
d1a890fa 3424err_alloc_queue_desc:
b0eb57cb
AK		 3425 dma_free_coherent(&adapter->pdev->dev,
3426 sizeof(struct Vmxnet3_DriverShared),
3427 adapter->shared, adapter->shared_pa);
d1a890fa 3428err_alloc_shared:
b0eb57cb
AK		 3429 dma_unmap_single(&adapter->pdev->dev, adapter->adapter_pa,
3430 sizeof(struct vmxnet3_adapter), PCI_DMA_TODEVICE);
5738a09d 3431err_dma_map:
d1a890fa
SB		 3432 free_netdev(netdev);
3433 return err;
3434}
3435
3436
3a4751a3 3437static void
d1a890fa
SB		 3438vmxnet3_remove_device(struct pci_dev *pdev)
3439{
3440 struct net_device *netdev = pci_get_drvdata(pdev);
3441 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
09c5088e
SB		 3442 int size = 0;
3443 int num_rx_queues;
3444
3445#ifdef VMXNET3_RSS
3446 if (enable_mq)
3447 num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES,
3448 (int)num_online_cpus());
3449 else
3450#endif
3451 num_rx_queues = 1;
eebb02b1 3452 num_rx_queues = rounddown_pow_of_two(num_rx_queues);
d1a890fa 3453
23f333a2 3454 cancel_work_sync(&adapter->work);
d1a890fa
SB		 3455
3456 unregister_netdev(netdev);
3457
3458 vmxnet3_free_intr_resources(adapter);
3459 vmxnet3_free_pci_resources(adapter);
09c5088e 3460#ifdef VMXNET3_RSS
b0eb57cb
AK		 3461 dma_free_coherent(&adapter->pdev->dev, sizeof(struct UPT1_RSSConf),
3462 adapter->rss_conf, adapter->rss_conf_pa);
09c5088e 3463#endif
b0eb57cb
AK		 3464 dma_free_coherent(&adapter->pdev->dev, sizeof(struct Vmxnet3_PMConf),
3465 adapter->pm_conf, adapter->pm_conf_pa);
09c5088e
SB		 3466
3467 size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues;
3468 size += sizeof(struct Vmxnet3_RxQueueDesc) * num_rx_queues;
b0eb57cb
AK		 3469 dma_free_coherent(&adapter->pdev->dev, size, adapter->tqd_start,
3470 adapter->queue_desc_pa);
3471 dma_free_coherent(&adapter->pdev->dev,
3472 sizeof(struct Vmxnet3_DriverShared),
3473 adapter->shared, adapter->shared_pa);
3474 dma_unmap_single(&adapter->pdev->dev, adapter->adapter_pa,
3475 sizeof(struct vmxnet3_adapter), PCI_DMA_TODEVICE);
d1a890fa
SB		 3476 free_netdev(netdev);
3477}
3478
e9ba47bf
SB		 3479static void vmxnet3_shutdown_device(struct pci_dev *pdev)
3480{
3481 struct net_device *netdev = pci_get_drvdata(pdev);
3482 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3483 unsigned long flags;
3484
3485 /* Reset_work may be in the middle of resetting the device, wait for its
3486 * completion.
3487 */
3488 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
3489 msleep(1);
3490
3491 if (test_and_set_bit(VMXNET3_STATE_BIT_QUIESCED,
3492 &adapter->state)) {
3493 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
3494 return;
3495 }
3496 spin_lock_irqsave(&adapter->cmd_lock, flags);
3497 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3498 VMXNET3_CMD_QUIESCE_DEV);
3499 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
3500 vmxnet3_disable_all_intrs(adapter);
3501
3502 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
3503}
3504
d1a890fa
SB		 3505
3506#ifdef CONFIG_PM
3507
3508static int
3509vmxnet3_suspend(struct device *device)
3510{
3511 struct pci_dev *pdev = to_pci_dev(device);
3512 struct net_device *netdev = pci_get_drvdata(pdev);
3513 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3514 struct Vmxnet3_PMConf *pmConf;
3515 struct ethhdr *ehdr;
3516 struct arphdr *ahdr;
3517 u8 *arpreq;
3518 struct in_device *in_dev;
3519 struct in_ifaddr *ifa;
83d0feff 3520 unsigned long flags;
d1a890fa
SB		 3521 int i = 0;
3522
3523 if (!netif_running(netdev))
3524 return 0;
3525
51956cd6
SB		 3526 for (i = 0; i < adapter->num_rx_queues; i++)
3527 napi_disable(&adapter->rx_queue[i].napi);
3528
d1a890fa
SB		 3529 vmxnet3_disable_all_intrs(adapter);
3530 vmxnet3_free_irqs(adapter);
3531 vmxnet3_free_intr_resources(adapter);
3532
3533 netif_device_detach(netdev);
09c5088e 3534 netif_tx_stop_all_queues(netdev);
d1a890fa
SB		 3535
3536 /* Create wake-up filters. */
3537 pmConf = adapter->pm_conf;
3538 memset(pmConf, 0, sizeof(*pmConf));
3539
3540 if (adapter->wol & WAKE_UCAST) {
3541 pmConf->filters[i].patternSize = ETH_ALEN;
3542 pmConf->filters[i].maskSize = 1;
3543 memcpy(pmConf->filters[i].pattern, netdev->dev_addr, ETH_ALEN);
3544 pmConf->filters[i].mask[0] = 0x3F; /* LSB ETH_ALEN bits */
3545
3843e515 3546 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER;
d1a890fa
SB		 3547 i++;
3548 }
3549
3550 if (adapter->wol & WAKE_ARP) {
3551 in_dev = in_dev_get(netdev);
3552 if (!in_dev)
3553 goto skip_arp;
3554
3555 ifa = (struct in_ifaddr *)in_dev->ifa_list;
3556 if (!ifa)
3557 goto skip_arp;
3558
3559 pmConf->filters[i].patternSize = ETH_HLEN + /* Ethernet header*/
3560 sizeof(struct arphdr) + /* ARP header */
3561 2 * ETH_ALEN + /* 2 Ethernet addresses*/
3562 2 * sizeof(u32); /*2 IPv4 addresses */
3563 pmConf->filters[i].maskSize =
3564 (pmConf->filters[i].patternSize - 1) / 8 + 1;
3565
3566 /* ETH_P_ARP in Ethernet header. */
3567 ehdr = (struct ethhdr *)pmConf->filters[i].pattern;
3568 ehdr->h_proto = htons(ETH_P_ARP);
3569
3570 /* ARPOP_REQUEST in ARP header. */
3571 ahdr = (struct arphdr *)&pmConf->filters[i].pattern[ETH_HLEN];
3572 ahdr->ar_op = htons(ARPOP_REQUEST);
3573 arpreq = (u8 *)(ahdr + 1);
3574
3575 /* The Unicast IPv4 address in 'tip' field. */
3576 arpreq += 2 * ETH_ALEN + sizeof(u32);
3577 *(u32 *)arpreq = ifa->ifa_address;
3578
3579 /* The mask for the relevant bits. */
3580 pmConf->filters[i].mask[0] = 0x00;
3581 pmConf->filters[i].mask[1] = 0x30; /* ETH_P_ARP */
3582 pmConf->filters[i].mask[2] = 0x30; /* ARPOP_REQUEST */
3583 pmConf->filters[i].mask[3] = 0x00;
3584 pmConf->filters[i].mask[4] = 0xC0; /* IPv4 TIP */
3585 pmConf->filters[i].mask[5] = 0x03; /* IPv4 TIP */
3586 in_dev_put(in_dev);
3587
3843e515 3588 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER;
d1a890fa
SB		 3589 i++;
3590 }
3591
3592skip_arp:
3593 if (adapter->wol & WAKE_MAGIC)
3843e515 3594 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_MAGIC;
d1a890fa
SB		 3595
3596 pmConf->numFilters = i;
3597
115924b6
SB		 3598 adapter->shared->devRead.pmConfDesc.confVer = cpu_to_le32(1);
3599 adapter->shared->devRead.pmConfDesc.confLen = cpu_to_le32(sizeof(
3600 *pmConf));
b0eb57cb
AK		 3601 adapter->shared->devRead.pmConfDesc.confPA =
3602 cpu_to_le64(adapter->pm_conf_pa);
d1a890fa 3603
83d0feff 3604 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa
SB		 3605 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3606 VMXNET3_CMD_UPDATE_PMCFG);
83d0feff 3607 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
d1a890fa
SB		 3608
3609 pci_save_state(pdev);
3610 pci_enable_wake(pdev, pci_choose_state(pdev, PMSG_SUSPEND),
3611 adapter->wol);
3612 pci_disable_device(pdev);
3613 pci_set_power_state(pdev, pci_choose_state(pdev, PMSG_SUSPEND));
3614
3615 return 0;
3616}
3617
3618
3619static int
3620vmxnet3_resume(struct device *device)
3621{
5ec82c1e 3622 int err;
83d0feff 3623 unsigned long flags;
d1a890fa
SB		 3624 struct pci_dev *pdev = to_pci_dev(device);
3625 struct net_device *netdev = pci_get_drvdata(pdev);
3626 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
d1a890fa
SB		 3627
3628 if (!netif_running(netdev))
3629 return 0;
3630
d1a890fa
SB		 3631 pci_set_power_state(pdev, PCI_D0);
3632 pci_restore_state(pdev);
3633 err = pci_enable_device_mem(pdev);
3634 if (err != 0)
3635 return err;
3636
3637 pci_enable_wake(pdev, PCI_D0, 0);
3638
5ec82c1e
SK		 3639 vmxnet3_alloc_intr_resources(adapter);
3640
3641 /* During hibernate and suspend, device has to be reinitialized as the
3642 * device state need not be preserved.
3643 */
3644
3645 /* Need not check adapter state as other reset tasks cannot run during
3646 * device resume.
3647 */
83d0feff 3648 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa 3649 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
5ec82c1e 3650 VMXNET3_CMD_QUIESCE_DEV);
83d0feff 3651 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
5ec82c1e
SK		 3652 vmxnet3_tq_cleanup_all(adapter);
3653 vmxnet3_rq_cleanup_all(adapter);
3654
3655 vmxnet3_reset_dev(adapter);
3656 err = vmxnet3_activate_dev(adapter);
3657 if (err != 0) {
3658 netdev_err(netdev,
3659 "failed to re-activate on resume, error: %d", err);
3660 vmxnet3_force_close(adapter);
3661 return err;
3662 }
3663 netif_device_attach(netdev);
d1a890fa
SB		 3664
3665 return 0;
3666}
3667
47145210 3668static const struct dev_pm_ops vmxnet3_pm_ops = {
d1a890fa
SB		 3669 .suspend = vmxnet3_suspend,
3670 .resume = vmxnet3_resume,
5ec82c1e
SK		 3671 .freeze = vmxnet3_suspend,
3672 .restore = vmxnet3_resume,
d1a890fa
SB		 3673};
3674#endif
3675
3676static struct pci_driver vmxnet3_driver = {
3677 .name = vmxnet3_driver_name,
3678 .id_table = vmxnet3_pciid_table,
3679 .probe = vmxnet3_probe_device,
3a4751a3 3680 .remove = vmxnet3_remove_device,
e9ba47bf 3681 .shutdown = vmxnet3_shutdown_device,
d1a890fa
SB		 3682#ifdef CONFIG_PM
3683 .driver.pm = &vmxnet3_pm_ops,
3684#endif
3685};
3686
3687
3688static int __init
3689vmxnet3_init_module(void)
3690{
204a6e65 3691 pr_info("%s - version %s\n", VMXNET3_DRIVER_DESC,
d1a890fa
SB		 3692 VMXNET3_DRIVER_VERSION_REPORT);
3693 return pci_register_driver(&vmxnet3_driver);
3694}
3695
3696module_init(vmxnet3_init_module);
3697
3698
3699static void
3700vmxnet3_exit_module(void)
3701{
3702 pci_unregister_driver(&vmxnet3_driver);
3703}
3704
3705module_exit(vmxnet3_exit_module);
3706
3707MODULE_AUTHOR("VMware, Inc.");
3708MODULE_DESCRIPTION(VMXNET3_DRIVER_DESC);
3709MODULE_LICENSE("GPL v2");
3710MODULE_VERSION(VMXNET3_DRIVER_VERSION_STRING);
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