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[mirror_ubuntu-hirsute-kernel.git] / drivers / net / vmxnet3 / vmxnet3_drv.c
CommitLineData
d1a890fa
SB		 1/*
2 * Linux driver for VMware's vmxnet3 ethernet NIC.
3 *
4 * Copyright (C) 2008-2009, VMware, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; version 2 of the License and no later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
13 * NON INFRINGEMENT. See the GNU General Public License for more
14 * details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * The full GNU General Public License is included in this distribution in
21 * the file called "COPYING".
22 *
23 * Maintained by: Shreyas Bhatewara <pv-drivers@vmware.com>
24 *
25 */
26
9d9779e7 27#include <linux/module.h>
b038b040
SR		 28#include <net/ip6_checksum.h>
29
d1a890fa
SB		 30#include "vmxnet3_int.h"
31
32char vmxnet3_driver_name[] = "vmxnet3";
33#define VMXNET3_DRIVER_DESC "VMware vmxnet3 virtual NIC driver"
34
d1a890fa
SB		 35/*
36 * PCI Device ID Table
37 * Last entry must be all 0s
38 */
9baa3c34 39static const struct pci_device_id vmxnet3_pciid_table[] = {
d1a890fa
SB		 40 {PCI_VDEVICE(VMWARE, PCI_DEVICE_ID_VMWARE_VMXNET3)},
41 {0}
42};
43
44MODULE_DEVICE_TABLE(pci, vmxnet3_pciid_table);
45
09c5088e 46static int enable_mq = 1;
d1a890fa 47
f9f25026
SB		 48static void
49vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac);
50
d1a890fa
SB		 51/*
52 * Enable/Disable the given intr
53 */
54static void
55vmxnet3_enable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx)
56{
57 VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 0);
58}
59
60
61static void
62vmxnet3_disable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx)
63{
64 VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 1);
65}
66
67
68/*
69 * Enable/Disable all intrs used by the device
70 */
71static void
72vmxnet3_enable_all_intrs(struct vmxnet3_adapter *adapter)
73{
74 int i;
75
76 for (i = 0; i < adapter->intr.num_intrs; i++)
77 vmxnet3_enable_intr(adapter, i);
6929fe8a
RZ		 78 adapter->shared->devRead.intrConf.intrCtrl &=
79 cpu_to_le32(~VMXNET3_IC_DISABLE_ALL);
d1a890fa
SB		 80}
81
82
83static void
84vmxnet3_disable_all_intrs(struct vmxnet3_adapter *adapter)
85{
86 int i;
87
6929fe8a
RZ		 88 adapter->shared->devRead.intrConf.intrCtrl |=
89 cpu_to_le32(VMXNET3_IC_DISABLE_ALL);
d1a890fa
SB		 90 for (i = 0; i < adapter->intr.num_intrs; i++)
91 vmxnet3_disable_intr(adapter, i);
92}
93
94
95static void
96vmxnet3_ack_events(struct vmxnet3_adapter *adapter, u32 events)
97{
98 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_ECR, events);
99}
100
101
102static bool
103vmxnet3_tq_stopped(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
104{
09c5088e 105 return tq->stopped;
d1a890fa
SB		 106}
107
108
109static void
110vmxnet3_tq_start(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
111{
112 tq->stopped = false;
09c5088e 113 netif_start_subqueue(adapter->netdev, tq - adapter->tx_queue);
d1a890fa
SB		 114}
115
116
117static void
118vmxnet3_tq_wake(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
119{
120 tq->stopped = false;
09c5088e 121 netif_wake_subqueue(adapter->netdev, (tq - adapter->tx_queue));
d1a890fa
SB		 122}
123
124
125static void
126vmxnet3_tq_stop(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
127{
128 tq->stopped = true;
129 tq->num_stop++;
09c5088e 130 netif_stop_subqueue(adapter->netdev, (tq - adapter->tx_queue));
d1a890fa
SB		 131}
132
133
134/*
135 * Check the link state. This may start or stop the tx queue.
136 */
137static void
4a1745fc 138vmxnet3_check_link(struct vmxnet3_adapter *adapter, bool affectTxQueue)
d1a890fa
SB		 139{
140 u32 ret;
09c5088e 141 int i;
83d0feff 142 unsigned long flags;
d1a890fa 143
83d0feff 144 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa
SB		 145 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK);
146 ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
83d0feff
SB		 147 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
148
d1a890fa
SB		 149 adapter->link_speed = ret >> 16;
150 if (ret & 1) { /* Link is up. */
204a6e65
SH		 151 netdev_info(adapter->netdev, "NIC Link is Up %d Mbps\n",
152 adapter->link_speed);
6cdd20c3 153 netif_carrier_on(adapter->netdev);
d1a890fa 154
09c5088e
SB		 155 if (affectTxQueue) {
156 for (i = 0; i < adapter->num_tx_queues; i++)
157 vmxnet3_tq_start(&adapter->tx_queue[i],
158 adapter);
159 }
d1a890fa 160 } else {
204a6e65 161 netdev_info(adapter->netdev, "NIC Link is Down\n");
6cdd20c3 162 netif_carrier_off(adapter->netdev);
d1a890fa 163
09c5088e
SB		 164 if (affectTxQueue) {
165 for (i = 0; i < adapter->num_tx_queues; i++)
166 vmxnet3_tq_stop(&adapter->tx_queue[i], adapter);
167 }
d1a890fa
SB		 168 }
169}
170
d1a890fa
SB		 171static void
172vmxnet3_process_events(struct vmxnet3_adapter *adapter)
173{
09c5088e 174 int i;
e328d410 175 unsigned long flags;
115924b6 176 u32 events = le32_to_cpu(adapter->shared->ecr);
d1a890fa
SB		 177 if (!events)
178 return;
179
180 vmxnet3_ack_events(adapter, events);
181
182 /* Check if link state has changed */
183 if (events & VMXNET3_ECR_LINK)
4a1745fc 184 vmxnet3_check_link(adapter, true);
d1a890fa
SB		 185
186 /* Check if there is an error on xmit/recv queues */
187 if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) {
e328d410 188 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa
SB		 189 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
190 VMXNET3_CMD_GET_QUEUE_STATUS);
e328d410 191 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
d1a890fa 192
09c5088e
SB		 193 for (i = 0; i < adapter->num_tx_queues; i++)
194 if (adapter->tqd_start[i].status.stopped)
195 dev_err(&adapter->netdev->dev,
196 "%s: tq[%d] error 0x%x\n",
197 adapter->netdev->name, i, le32_to_cpu(
198 adapter->tqd_start[i].status.error));
199 for (i = 0; i < adapter->num_rx_queues; i++)
200 if (adapter->rqd_start[i].status.stopped)
201 dev_err(&adapter->netdev->dev,
202 "%s: rq[%d] error 0x%x\n",
203 adapter->netdev->name, i,
204 adapter->rqd_start[i].status.error);
d1a890fa
SB		 205
206 schedule_work(&adapter->work);
207 }
208}
209
115924b6
SB		 210#ifdef __BIG_ENDIAN_BITFIELD
211/*
212 * The device expects the bitfields in shared structures to be written in
213 * little endian. When CPU is big endian, the following routines are used to
214 * correctly read and write into ABI.
215 * The general technique used here is : double word bitfields are defined in
216 * opposite order for big endian architecture. Then before reading them in
217 * driver the complete double word is translated using le32_to_cpu. Similarly
218 * After the driver writes into bitfields, cpu_to_le32 is used to translate the
219 * double words into required format.
220 * In order to avoid touching bits in shared structure more than once, temporary
221 * descriptors are used. These are passed as srcDesc to following functions.
222 */
223static void vmxnet3_RxDescToCPU(const struct Vmxnet3_RxDesc *srcDesc,
224 struct Vmxnet3_RxDesc *dstDesc)
225{
226 u32 *src = (u32 *)srcDesc + 2;
227 u32 *dst = (u32 *)dstDesc + 2;
228 dstDesc->addr = le64_to_cpu(srcDesc->addr);
229 *dst = le32_to_cpu(*src);
230 dstDesc->ext1 = le32_to_cpu(srcDesc->ext1);
231}
232
233static void vmxnet3_TxDescToLe(const struct Vmxnet3_TxDesc *srcDesc,
234 struct Vmxnet3_TxDesc *dstDesc)
235{
236 int i;
237 u32 *src = (u32 *)(srcDesc + 1);
238 u32 *dst = (u32 *)(dstDesc + 1);
239
240 /* Working backwards so that the gen bit is set at the end. */
241 for (i = 2; i > 0; i--) {
242 src--;
243 dst--;
244 *dst = cpu_to_le32(*src);
245 }
246}
247
248
249static void vmxnet3_RxCompToCPU(const struct Vmxnet3_RxCompDesc *srcDesc,
250 struct Vmxnet3_RxCompDesc *dstDesc)
251{
252 int i = 0;
253 u32 *src = (u32 *)srcDesc;
254 u32 *dst = (u32 *)dstDesc;
255 for (i = 0; i < sizeof(struct Vmxnet3_RxCompDesc) / sizeof(u32); i++) {
256 *dst = le32_to_cpu(*src);
257 src++;
258 dst++;
259 }
260}
261
262
263/* Used to read bitfield values from double words. */
264static u32 get_bitfield32(const __le32 *bitfield, u32 pos, u32 size)
265{
266 u32 temp = le32_to_cpu(*bitfield);
267 u32 mask = ((1 << size) - 1) << pos;
268 temp &= mask;
269 temp >>= pos;
270 return temp;
271}
272
273
274
275#endif /* __BIG_ENDIAN_BITFIELD */
276
277#ifdef __BIG_ENDIAN_BITFIELD
278
279# define VMXNET3_TXDESC_GET_GEN(txdesc) get_bitfield32(((const __le32 *) \
280 txdesc) + VMXNET3_TXD_GEN_DWORD_SHIFT, \
281 VMXNET3_TXD_GEN_SHIFT, VMXNET3_TXD_GEN_SIZE)
282# define VMXNET3_TXDESC_GET_EOP(txdesc) get_bitfield32(((const __le32 *) \
283 txdesc) + VMXNET3_TXD_EOP_DWORD_SHIFT, \
284 VMXNET3_TXD_EOP_SHIFT, VMXNET3_TXD_EOP_SIZE)
285# define VMXNET3_TCD_GET_GEN(tcd) get_bitfield32(((const __le32 *)tcd) + \
286 VMXNET3_TCD_GEN_DWORD_SHIFT, VMXNET3_TCD_GEN_SHIFT, \
287 VMXNET3_TCD_GEN_SIZE)
288# define VMXNET3_TCD_GET_TXIDX(tcd) get_bitfield32((const __le32 *)tcd, \
289 VMXNET3_TCD_TXIDX_SHIFT, VMXNET3_TCD_TXIDX_SIZE)
290# define vmxnet3_getRxComp(dstrcd, rcd, tmp) do { \
291 (dstrcd) = (tmp); \
292 vmxnet3_RxCompToCPU((rcd), (tmp)); \
293 } while (0)
294# define vmxnet3_getRxDesc(dstrxd, rxd, tmp) do { \
295 (dstrxd) = (tmp); \
296 vmxnet3_RxDescToCPU((rxd), (tmp)); \
297 } while (0)
298
299#else
300
301# define VMXNET3_TXDESC_GET_GEN(txdesc) ((txdesc)->gen)
302# define VMXNET3_TXDESC_GET_EOP(txdesc) ((txdesc)->eop)
303# define VMXNET3_TCD_GET_GEN(tcd) ((tcd)->gen)
304# define VMXNET3_TCD_GET_TXIDX(tcd) ((tcd)->txdIdx)
305# define vmxnet3_getRxComp(dstrcd, rcd, tmp) (dstrcd) = (rcd)
306# define vmxnet3_getRxDesc(dstrxd, rxd, tmp) (dstrxd) = (rxd)
307
308#endif /* __BIG_ENDIAN_BITFIELD */
309
d1a890fa
SB		 310
311static void
312vmxnet3_unmap_tx_buf(struct vmxnet3_tx_buf_info *tbi,
313 struct pci_dev *pdev)
314{
315 if (tbi->map_type == VMXNET3_MAP_SINGLE)
b0eb57cb 316 dma_unmap_single(&pdev->dev, tbi->dma_addr, tbi->len,
d1a890fa
SB		 317 PCI_DMA_TODEVICE);
318 else if (tbi->map_type == VMXNET3_MAP_PAGE)
b0eb57cb 319 dma_unmap_page(&pdev->dev, tbi->dma_addr, tbi->len,
d1a890fa
SB		 320 PCI_DMA_TODEVICE);
321 else
322 BUG_ON(tbi->map_type != VMXNET3_MAP_NONE);
323
324 tbi->map_type = VMXNET3_MAP_NONE; /* to help debugging */
325}
326
327
328static int
329vmxnet3_unmap_pkt(u32 eop_idx, struct vmxnet3_tx_queue *tq,
330 struct pci_dev *pdev, struct vmxnet3_adapter *adapter)
331{
332 struct sk_buff *skb;
333 int entries = 0;
334
335 /* no out of order completion */
336 BUG_ON(tq->buf_info[eop_idx].sop_idx != tq->tx_ring.next2comp);
115924b6 337 BUG_ON(VMXNET3_TXDESC_GET_EOP(&(tq->tx_ring.base[eop_idx].txd)) != 1);
d1a890fa
SB		 338
339 skb = tq->buf_info[eop_idx].skb;
340 BUG_ON(skb == NULL);
341 tq->buf_info[eop_idx].skb = NULL;
342
343 VMXNET3_INC_RING_IDX_ONLY(eop_idx, tq->tx_ring.size);
344
345 while (tq->tx_ring.next2comp != eop_idx) {
346 vmxnet3_unmap_tx_buf(tq->buf_info + tq->tx_ring.next2comp,
347 pdev);
348
349 /* update next2comp w/o tx_lock. Since we are marking more,
350 * instead of less, tx ring entries avail, the worst case is
351 * that the tx routine incorrectly re-queues a pkt due to
352 * insufficient tx ring entries.
353 */
354 vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring);
355 entries++;
356 }
357
358 dev_kfree_skb_any(skb);
359 return entries;
360}
361
362
363static int
364vmxnet3_tq_tx_complete(struct vmxnet3_tx_queue *tq,
365 struct vmxnet3_adapter *adapter)
366{
367 int completed = 0;
368 union Vmxnet3_GenericDesc *gdesc;
369
370 gdesc = tq->comp_ring.base + tq->comp_ring.next2proc;
115924b6
SB		 371 while (VMXNET3_TCD_GET_GEN(&gdesc->tcd) == tq->comp_ring.gen) {
372 completed += vmxnet3_unmap_pkt(VMXNET3_TCD_GET_TXIDX(
373 &gdesc->tcd), tq, adapter->pdev,
374 adapter);
d1a890fa
SB		 375
376 vmxnet3_comp_ring_adv_next2proc(&tq->comp_ring);
377 gdesc = tq->comp_ring.base + tq->comp_ring.next2proc;
378 }
379
380 if (completed) {
381 spin_lock(&tq->tx_lock);
382 if (unlikely(vmxnet3_tq_stopped(tq, adapter) &&
383 vmxnet3_cmd_ring_desc_avail(&tq->tx_ring) >
384 VMXNET3_WAKE_QUEUE_THRESHOLD(tq) &&
385 netif_carrier_ok(adapter->netdev))) {
386 vmxnet3_tq_wake(tq, adapter);
387 }
388 spin_unlock(&tq->tx_lock);
389 }
390 return completed;
391}
392
393
394static void
395vmxnet3_tq_cleanup(struct vmxnet3_tx_queue *tq,
396 struct vmxnet3_adapter *adapter)
397{
398 int i;
399
400 while (tq->tx_ring.next2comp != tq->tx_ring.next2fill) {
401 struct vmxnet3_tx_buf_info *tbi;
d1a890fa
SB		 402
403 tbi = tq->buf_info + tq->tx_ring.next2comp;
d1a890fa
SB		 404
405 vmxnet3_unmap_tx_buf(tbi, adapter->pdev);
406 if (tbi->skb) {
407 dev_kfree_skb_any(tbi->skb);
408 tbi->skb = NULL;
409 }
410 vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring);
411 }
412
413 /* sanity check, verify all buffers are indeed unmapped and freed */
414 for (i = 0; i < tq->tx_ring.size; i++) {
415 BUG_ON(tq->buf_info[i].skb != NULL ||
416 tq->buf_info[i].map_type != VMXNET3_MAP_NONE);
417 }
418
419 tq->tx_ring.gen = VMXNET3_INIT_GEN;
420 tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0;
421
422 tq->comp_ring.gen = VMXNET3_INIT_GEN;
423 tq->comp_ring.next2proc = 0;
424}
425
426
09c5088e 427static void
d1a890fa
SB		 428vmxnet3_tq_destroy(struct vmxnet3_tx_queue *tq,
429 struct vmxnet3_adapter *adapter)
430{
431 if (tq->tx_ring.base) {
b0eb57cb
AK		 432 dma_free_coherent(&adapter->pdev->dev, tq->tx_ring.size *
433 sizeof(struct Vmxnet3_TxDesc),
434 tq->tx_ring.base, tq->tx_ring.basePA);
d1a890fa
SB		 435 tq->tx_ring.base = NULL;
436 }
437 if (tq->data_ring.base) {
b0eb57cb
AK		 438 dma_free_coherent(&adapter->pdev->dev, tq->data_ring.size *
439 sizeof(struct Vmxnet3_TxDataDesc),
440 tq->data_ring.base, tq->data_ring.basePA);
d1a890fa
SB		 441 tq->data_ring.base = NULL;
442 }
443 if (tq->comp_ring.base) {
b0eb57cb
AK		 444 dma_free_coherent(&adapter->pdev->dev, tq->comp_ring.size *
445 sizeof(struct Vmxnet3_TxCompDesc),
446 tq->comp_ring.base, tq->comp_ring.basePA);
d1a890fa
SB		 447 tq->comp_ring.base = NULL;
448 }
b0eb57cb
AK		 449 if (tq->buf_info) {
450 dma_free_coherent(&adapter->pdev->dev,
451 tq->tx_ring.size * sizeof(tq->buf_info[0]),
452 tq->buf_info, tq->buf_info_pa);
453 tq->buf_info = NULL;
454 }
d1a890fa
SB		 455}
456
457
09c5088e
SB		 458/* Destroy all tx queues */
459void
460vmxnet3_tq_destroy_all(struct vmxnet3_adapter *adapter)
461{
462 int i;
463
464 for (i = 0; i < adapter->num_tx_queues; i++)
465 vmxnet3_tq_destroy(&adapter->tx_queue[i], adapter);
466}
467
468
d1a890fa
SB		 469static void
470vmxnet3_tq_init(struct vmxnet3_tx_queue *tq,
471 struct vmxnet3_adapter *adapter)
472{
473 int i;
474
475 /* reset the tx ring contents to 0 and reset the tx ring states */
476 memset(tq->tx_ring.base, 0, tq->tx_ring.size *
477 sizeof(struct Vmxnet3_TxDesc));
478 tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0;
479 tq->tx_ring.gen = VMXNET3_INIT_GEN;
480
481 memset(tq->data_ring.base, 0, tq->data_ring.size *
482 sizeof(struct Vmxnet3_TxDataDesc));
483
484 /* reset the tx comp ring contents to 0 and reset comp ring states */
485 memset(tq->comp_ring.base, 0, tq->comp_ring.size *
486 sizeof(struct Vmxnet3_TxCompDesc));
487 tq->comp_ring.next2proc = 0;
488 tq->comp_ring.gen = VMXNET3_INIT_GEN;
489
490 /* reset the bookkeeping data */
491 memset(tq->buf_info, 0, sizeof(tq->buf_info[0]) * tq->tx_ring.size);
492 for (i = 0; i < tq->tx_ring.size; i++)
493 tq->buf_info[i].map_type = VMXNET3_MAP_NONE;
494
495 /* stats are not reset */
496}
497
498
499static int
500vmxnet3_tq_create(struct vmxnet3_tx_queue *tq,
501 struct vmxnet3_adapter *adapter)
502{
b0eb57cb
AK		 503 size_t sz;
504
d1a890fa
SB		 505 BUG_ON(tq->tx_ring.base || tq->data_ring.base ||
506 tq->comp_ring.base || tq->buf_info);
507
b0eb57cb
AK		 508 tq->tx_ring.base = dma_alloc_coherent(&adapter->pdev->dev,
509 tq->tx_ring.size * sizeof(struct Vmxnet3_TxDesc),
510 &tq->tx_ring.basePA, GFP_KERNEL);
d1a890fa 511 if (!tq->tx_ring.base) {
204a6e65 512 netdev_err(adapter->netdev, "failed to allocate tx ring\n");
d1a890fa
SB		 513 goto err;
514 }
515
b0eb57cb
AK		 516 tq->data_ring.base = dma_alloc_coherent(&adapter->pdev->dev,
517 tq->data_ring.size * sizeof(struct Vmxnet3_TxDataDesc),
518 &tq->data_ring.basePA, GFP_KERNEL);
d1a890fa 519 if (!tq->data_ring.base) {
204a6e65 520 netdev_err(adapter->netdev, "failed to allocate data ring\n");
d1a890fa
SB		 521 goto err;
522 }
523
b0eb57cb
AK		 524 tq->comp_ring.base = dma_alloc_coherent(&adapter->pdev->dev,
525 tq->comp_ring.size * sizeof(struct Vmxnet3_TxCompDesc),
526 &tq->comp_ring.basePA, GFP_KERNEL);
d1a890fa 527 if (!tq->comp_ring.base) {
204a6e65 528 netdev_err(adapter->netdev, "failed to allocate tx comp ring\n");
d1a890fa
SB		 529 goto err;
530 }
531
b0eb57cb
AK		 532 sz = tq->tx_ring.size * sizeof(tq->buf_info[0]);
533 tq->buf_info = dma_zalloc_coherent(&adapter->pdev->dev, sz,
534 &tq->buf_info_pa, GFP_KERNEL);
e404decb 535 if (!tq->buf_info)
d1a890fa 536 goto err;
d1a890fa
SB		 537
538 return 0;
539
540err:
541 vmxnet3_tq_destroy(tq, adapter);
542 return -ENOMEM;
543}
544
09c5088e
SB		 545static void
546vmxnet3_tq_cleanup_all(struct vmxnet3_adapter *adapter)
547{
548 int i;
549
550 for (i = 0; i < adapter->num_tx_queues; i++)
551 vmxnet3_tq_cleanup(&adapter->tx_queue[i], adapter);
552}
d1a890fa
SB		 553
554/*
555 * starting from ring->next2fill, allocate rx buffers for the given ring
556 * of the rx queue and update the rx desc. stop after @num_to_alloc buffers
557 * are allocated or allocation fails
558 */
559
560static int
561vmxnet3_rq_alloc_rx_buf(struct vmxnet3_rx_queue *rq, u32 ring_idx,
562 int num_to_alloc, struct vmxnet3_adapter *adapter)
563{
564 int num_allocated = 0;
565 struct vmxnet3_rx_buf_info *rbi_base = rq->buf_info[ring_idx];
566 struct vmxnet3_cmd_ring *ring = &rq->rx_ring[ring_idx];
567 u32 val;
568
5318d809 569 while (num_allocated <= num_to_alloc) {
d1a890fa
SB		 570 struct vmxnet3_rx_buf_info *rbi;
571 union Vmxnet3_GenericDesc *gd;
572
573 rbi = rbi_base + ring->next2fill;
574 gd = ring->base + ring->next2fill;
575
576 if (rbi->buf_type == VMXNET3_RX_BUF_SKB) {
577 if (rbi->skb == NULL) {
0d735f13
SH		 578 rbi->skb = __netdev_alloc_skb_ip_align(adapter->netdev,
579 rbi->len,
580 GFP_KERNEL);
d1a890fa
SB		 581 if (unlikely(rbi->skb == NULL)) {
582 rq->stats.rx_buf_alloc_failure++;
583 break;
584 }
d1a890fa 585
b0eb57cb
AK		 586 rbi->dma_addr = dma_map_single(
587 &adapter->pdev->dev,
d1a890fa
SB		 588 rbi->skb->data, rbi->len,
589 PCI_DMA_FROMDEVICE);
5738a09d
AK		 590 if (dma_mapping_error(&adapter->pdev->dev,
591 rbi->dma_addr)) {
592 dev_kfree_skb_any(rbi->skb);
593 rq->stats.rx_buf_alloc_failure++;
594 break;
595 }
d1a890fa
SB		 596 } else {
597 /* rx buffer skipped by the device */
598 }
599 val = VMXNET3_RXD_BTYPE_HEAD << VMXNET3_RXD_BTYPE_SHIFT;
600 } else {
601 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE ||
602 rbi->len != PAGE_SIZE);
603
604 if (rbi->page == NULL) {
605 rbi->page = alloc_page(GFP_ATOMIC);
606 if (unlikely(rbi->page == NULL)) {
607 rq->stats.rx_buf_alloc_failure++;
608 break;
609 }
b0eb57cb
AK		 610 rbi->dma_addr = dma_map_page(
611 &adapter->pdev->dev,
d1a890fa
SB		 612 rbi->page, 0, PAGE_SIZE,
613 PCI_DMA_FROMDEVICE);
5738a09d
AK		 614 if (dma_mapping_error(&adapter->pdev->dev,
615 rbi->dma_addr)) {
616 put_page(rbi->page);
617 rq->stats.rx_buf_alloc_failure++;
618 break;
619 }
d1a890fa
SB		 620 } else {
621 /* rx buffers skipped by the device */
622 }
623 val = VMXNET3_RXD_BTYPE_BODY << VMXNET3_RXD_BTYPE_SHIFT;
624 }
625
115924b6 626 gd->rxd.addr = cpu_to_le64(rbi->dma_addr);
5318d809 627 gd->dword[2] = cpu_to_le32((!ring->gen << VMXNET3_RXD_GEN_SHIFT)
115924b6 628 | val | rbi->len);
d1a890fa 629
5318d809
SB		 630 /* Fill the last buffer but dont mark it ready, or else the
631 * device will think that the queue is full */
632 if (num_allocated == num_to_alloc)
633 break;
634
635 gd->dword[2] |= cpu_to_le32(ring->gen << VMXNET3_RXD_GEN_SHIFT);
d1a890fa
SB		 636 num_allocated++;
637 vmxnet3_cmd_ring_adv_next2fill(ring);
638 }
d1a890fa 639
fdcd79b9 640 netdev_dbg(adapter->netdev,
69b9a712
SH		 641 "alloc_rx_buf: %d allocated, next2fill %u, next2comp %u\n",
642 num_allocated, ring->next2fill, ring->next2comp);
d1a890fa
SB		 643
644 /* so that the device can distinguish a full ring and an empty ring */
645 BUG_ON(num_allocated != 0 && ring->next2fill == ring->next2comp);
646
647 return num_allocated;
648}
649
650
651static void
652vmxnet3_append_frag(struct sk_buff *skb, struct Vmxnet3_RxCompDesc *rcd,
653 struct vmxnet3_rx_buf_info *rbi)
654{
655 struct skb_frag_struct *frag = skb_shinfo(skb)->frags +
656 skb_shinfo(skb)->nr_frags;
657
658 BUG_ON(skb_shinfo(skb)->nr_frags >= MAX_SKB_FRAGS);
659
0e0634d2 660 __skb_frag_set_page(frag, rbi->page);
d1a890fa 661 frag->page_offset = 0;
9e903e08
ED		 662 skb_frag_size_set(frag, rcd->len);
663 skb->data_len += rcd->len;
5e6c355c 664 skb->truesize += PAGE_SIZE;
d1a890fa
SB		 665 skb_shinfo(skb)->nr_frags++;
666}
667
668
5738a09d 669static int
d1a890fa
SB		 670vmxnet3_map_pkt(struct sk_buff *skb, struct vmxnet3_tx_ctx *ctx,
671 struct vmxnet3_tx_queue *tq, struct pci_dev *pdev,
672 struct vmxnet3_adapter *adapter)
673{
674 u32 dw2, len;
675 unsigned long buf_offset;
676 int i;
677 union Vmxnet3_GenericDesc *gdesc;
678 struct vmxnet3_tx_buf_info *tbi = NULL;
679
680 BUG_ON(ctx->copy_size > skb_headlen(skb));
681
682 /* use the previous gen bit for the SOP desc */
683 dw2 = (tq->tx_ring.gen ^ 0x1) << VMXNET3_TXD_GEN_SHIFT;
684
685 ctx->sop_txd = tq->tx_ring.base + tq->tx_ring.next2fill;
686 gdesc = ctx->sop_txd; /* both loops below can be skipped */
687
688 /* no need to map the buffer if headers are copied */
689 if (ctx->copy_size) {
115924b6 690 ctx->sop_txd->txd.addr = cpu_to_le64(tq->data_ring.basePA +
d1a890fa 691 tq->tx_ring.next2fill *
115924b6
SB		 692 sizeof(struct Vmxnet3_TxDataDesc));
693 ctx->sop_txd->dword[2] = cpu_to_le32(dw2 | ctx->copy_size);
d1a890fa
SB		 694 ctx->sop_txd->dword[3] = 0;
695
696 tbi = tq->buf_info + tq->tx_ring.next2fill;
697 tbi->map_type = VMXNET3_MAP_NONE;
698
fdcd79b9 699 netdev_dbg(adapter->netdev,
f6965582 700 "txd[%u]: 0x%Lx 0x%x 0x%x\n",
115924b6
SB		 701 tq->tx_ring.next2fill,
702 le64_to_cpu(ctx->sop_txd->txd.addr),
d1a890fa
SB		 703 ctx->sop_txd->dword[2], ctx->sop_txd->dword[3]);
704 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
705
706 /* use the right gen for non-SOP desc */
707 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
708 }
709
710 /* linear part can use multiple tx desc if it's big */
711 len = skb_headlen(skb) - ctx->copy_size;
712 buf_offset = ctx->copy_size;
713 while (len) {
714 u32 buf_size;
715
1f4b1612
BD		 716 if (len < VMXNET3_MAX_TX_BUF_SIZE) {
717 buf_size = len;
718 dw2 |= len;
719 } else {
720 buf_size = VMXNET3_MAX_TX_BUF_SIZE;
721 /* spec says that for TxDesc.len, 0 == 2^14 */
722 }
d1a890fa
SB		 723
724 tbi = tq->buf_info + tq->tx_ring.next2fill;
725 tbi->map_type = VMXNET3_MAP_SINGLE;
b0eb57cb 726 tbi->dma_addr = dma_map_single(&adapter->pdev->dev,
d1a890fa
SB		 727 skb->data + buf_offset, buf_size,
728 PCI_DMA_TODEVICE);
5738a09d
AK		 729 if (dma_mapping_error(&adapter->pdev->dev, tbi->dma_addr))
730 return -EFAULT;
d1a890fa 731
1f4b1612 732 tbi->len = buf_size;
d1a890fa
SB		 733
734 gdesc = tq->tx_ring.base + tq->tx_ring.next2fill;
735 BUG_ON(gdesc->txd.gen == tq->tx_ring.gen);
736
115924b6 737 gdesc->txd.addr = cpu_to_le64(tbi->dma_addr);
1f4b1612 738 gdesc->dword[2] = cpu_to_le32(dw2);
d1a890fa
SB		 739 gdesc->dword[3] = 0;
740
fdcd79b9 741 netdev_dbg(adapter->netdev,
f6965582 742 "txd[%u]: 0x%Lx 0x%x 0x%x\n",
115924b6
SB		 743 tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr),
744 le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]);
d1a890fa
SB		 745 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
746 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
747
748 len -= buf_size;
749 buf_offset += buf_size;
750 }
751
752 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
9e903e08 753 const struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
a4d7e485 754 u32 buf_size;
d1a890fa 755
a4d7e485
ED		 756 buf_offset = 0;
757 len = skb_frag_size(frag);
758 while (len) {
759 tbi = tq->buf_info + tq->tx_ring.next2fill;
760 if (len < VMXNET3_MAX_TX_BUF_SIZE) {
761 buf_size = len;
762 dw2 |= len;
763 } else {
764 buf_size = VMXNET3_MAX_TX_BUF_SIZE;
765 /* spec says that for TxDesc.len, 0 == 2^14 */
766 }
767 tbi->map_type = VMXNET3_MAP_PAGE;
768 tbi->dma_addr = skb_frag_dma_map(&adapter->pdev->dev, frag,
769 buf_offset, buf_size,
770 DMA_TO_DEVICE);
5738a09d
AK		 771 if (dma_mapping_error(&adapter->pdev->dev, tbi->dma_addr))
772 return -EFAULT;
d1a890fa 773
a4d7e485 774 tbi->len = buf_size;
d1a890fa 775
a4d7e485
ED		 776 gdesc = tq->tx_ring.base + tq->tx_ring.next2fill;
777 BUG_ON(gdesc->txd.gen == tq->tx_ring.gen);
d1a890fa 778
a4d7e485
ED		 779 gdesc->txd.addr = cpu_to_le64(tbi->dma_addr);
780 gdesc->dword[2] = cpu_to_le32(dw2);
781 gdesc->dword[3] = 0;
d1a890fa 782
fdcd79b9 783 netdev_dbg(adapter->netdev,
8b429468 784 "txd[%u]: 0x%llx %u %u\n",
a4d7e485
ED		 785 tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr),
786 le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]);
787 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
788 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
789
790 len -= buf_size;
791 buf_offset += buf_size;
792 }
d1a890fa
SB		 793 }
794
795 ctx->eop_txd = gdesc;
796
797 /* set the last buf_info for the pkt */
798 tbi->skb = skb;
799 tbi->sop_idx = ctx->sop_txd - tq->tx_ring.base;
5738a09d
AK		 800
801 return 0;
d1a890fa
SB		 802}
803
804
09c5088e
SB		 805/* Init all tx queues */
806static void
807vmxnet3_tq_init_all(struct vmxnet3_adapter *adapter)
808{
809 int i;
810
811 for (i = 0; i < adapter->num_tx_queues; i++)
812 vmxnet3_tq_init(&adapter->tx_queue[i], adapter);
813}
814
815
d1a890fa
SB		 816/*
817 * parse and copy relevant protocol headers:
818 * For a tso pkt, relevant headers are L2/3/4 including options
819 * For a pkt requesting csum offloading, they are L2/3 and may include L4
820 * if it's a TCP/UDP pkt
821 *
822 * Returns:
823 * -1: error happens during parsing
824 * 0: protocol headers parsed, but too big to be copied
825 * 1: protocol headers parsed and copied
826 *
827 * Other effects:
828 * 1. related *ctx fields are updated.
829 * 2. ctx->copy_size is # of bytes copied
830 * 3. the portion copied is guaranteed to be in the linear part
831 *
832 */
833static int
834vmxnet3_parse_and_copy_hdr(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
835 struct vmxnet3_tx_ctx *ctx,
836 struct vmxnet3_adapter *adapter)
837{
838 struct Vmxnet3_TxDataDesc *tdd;
759c9359 839 u8 protocol = 0;
d1a890fa 840
0d0b1672 841 if (ctx->mss) { /* TSO */
d1a890fa 842 ctx->eth_ip_hdr_size = skb_transport_offset(skb);
8bca5d1e 843 ctx->l4_hdr_size = tcp_hdrlen(skb);
d1a890fa
SB		 844 ctx->copy_size = ctx->eth_ip_hdr_size + ctx->l4_hdr_size;
845 } else {
d1a890fa 846 if (skb->ip_summed == CHECKSUM_PARTIAL) {
0d0b1672 847 ctx->eth_ip_hdr_size = skb_checksum_start_offset(skb);
d1a890fa
SB		 848
849 if (ctx->ipv4) {
8bca5d1e
ED		 850 const struct iphdr *iph = ip_hdr(skb);
851
759c9359
SK		 852 protocol = iph->protocol;
853 } else if (ctx->ipv6) {
854 const struct ipv6hdr *ipv6h = ipv6_hdr(skb);
855
856 protocol = ipv6h->nexthdr;
857 }
858
859 switch (protocol) {
860 case IPPROTO_TCP:
861 ctx->l4_hdr_size = tcp_hdrlen(skb);
862 break;
863 case IPPROTO_UDP:
864 ctx->l4_hdr_size = sizeof(struct udphdr);
865 break;
866 default:
d1a890fa 867 ctx->l4_hdr_size = 0;
759c9359 868 break;
d1a890fa 869 }
759c9359 870
b203262d
NH		 871 ctx->copy_size = min(ctx->eth_ip_hdr_size +
872 ctx->l4_hdr_size, skb->len);
d1a890fa
SB		 873 } else {
874 ctx->eth_ip_hdr_size = 0;
875 ctx->l4_hdr_size = 0;
876 /* copy as much as allowed */
877 ctx->copy_size = min((unsigned int)VMXNET3_HDR_COPY_SIZE
878 , skb_headlen(skb));
879 }
880
c41fcce9
SB		 881 if (skb->len <= VMXNET3_HDR_COPY_SIZE)
882 ctx->copy_size = skb->len;
883
d1a890fa
SB		 884 /* make sure headers are accessible directly */
885 if (unlikely(!pskb_may_pull(skb, ctx->copy_size)))
886 goto err;
887 }
888
889 if (unlikely(ctx->copy_size > VMXNET3_HDR_COPY_SIZE)) {
890 tq->stats.oversized_hdr++;
891 ctx->copy_size = 0;
892 return 0;
893 }
894
895 tdd = tq->data_ring.base + tq->tx_ring.next2fill;
896
897 memcpy(tdd->data, skb->data, ctx->copy_size);
fdcd79b9 898 netdev_dbg(adapter->netdev,
f6965582 899 "copy %u bytes to dataRing[%u]\n",
d1a890fa
SB		 900 ctx->copy_size, tq->tx_ring.next2fill);
901 return 1;
902
903err:
904 return -1;
905}
906
907
908static void
909vmxnet3_prepare_tso(struct sk_buff *skb,
910 struct vmxnet3_tx_ctx *ctx)
911{
8bca5d1e
ED		 912 struct tcphdr *tcph = tcp_hdr(skb);
913
d1a890fa 914 if (ctx->ipv4) {
8bca5d1e
ED		 915 struct iphdr *iph = ip_hdr(skb);
916
d1a890fa
SB		 917 iph->check = 0;
918 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0,
919 IPPROTO_TCP, 0);
759c9359 920 } else if (ctx->ipv6) {
8bca5d1e
ED		 921 struct ipv6hdr *iph = ipv6_hdr(skb);
922
d1a890fa
SB		 923 tcph->check = ~csum_ipv6_magic(&iph->saddr, &iph->daddr, 0,
924 IPPROTO_TCP, 0);
925 }
926}
927
a4d7e485
ED		 928static int txd_estimate(const struct sk_buff *skb)
929{
930 int count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 1;
931 int i;
932
933 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
934 const struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
935
936 count += VMXNET3_TXD_NEEDED(skb_frag_size(frag));
937 }
938 return count;
939}
d1a890fa
SB		 940
941/*
942 * Transmits a pkt thru a given tq
943 * Returns:
944 * NETDEV_TX_OK: descriptors are setup successfully
25985edc 945 * NETDEV_TX_OK: error occurred, the pkt is dropped
d1a890fa
SB		 946 * NETDEV_TX_BUSY: tx ring is full, queue is stopped
947 *
948 * Side-effects:
949 * 1. tx ring may be changed
950 * 2. tq stats may be updated accordingly
951 * 3. shared->txNumDeferred may be updated
952 */
953
954static int
955vmxnet3_tq_xmit(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
956 struct vmxnet3_adapter *adapter, struct net_device *netdev)
957{
958 int ret;
959 u32 count;
960 unsigned long flags;
961 struct vmxnet3_tx_ctx ctx;
962 union Vmxnet3_GenericDesc *gdesc;
115924b6
SB		 963#ifdef __BIG_ENDIAN_BITFIELD
964 /* Use temporary descriptor to avoid touching bits multiple times */
965 union Vmxnet3_GenericDesc tempTxDesc;
966#endif
d1a890fa 967
a4d7e485 968 count = txd_estimate(skb);
d1a890fa 969
72e85c45 970 ctx.ipv4 = (vlan_get_protocol(skb) == cpu_to_be16(ETH_P_IP));
759c9359 971 ctx.ipv6 = (vlan_get_protocol(skb) == cpu_to_be16(ETH_P_IPV6));
d1a890fa
SB		 972
973 ctx.mss = skb_shinfo(skb)->gso_size;
974 if (ctx.mss) {
975 if (skb_header_cloned(skb)) {
976 if (unlikely(pskb_expand_head(skb, 0, 0,
977 GFP_ATOMIC) != 0)) {
978 tq->stats.drop_tso++;
979 goto drop_pkt;
980 }
981 tq->stats.copy_skb_header++;
982 }
983 vmxnet3_prepare_tso(skb, &ctx);
984 } else {
985 if (unlikely(count > VMXNET3_MAX_TXD_PER_PKT)) {
986
987 /* non-tso pkts must not use more than
988 * VMXNET3_MAX_TXD_PER_PKT entries
989 */
990 if (skb_linearize(skb) != 0) {
991 tq->stats.drop_too_many_frags++;
992 goto drop_pkt;
993 }
994 tq->stats.linearized++;
995
996 /* recalculate the # of descriptors to use */
997 count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 1;
998 }
999 }
1000
09c5088e
SB		 1001 spin_lock_irqsave(&tq->tx_lock, flags);
1002
1003 if (count > vmxnet3_cmd_ring_desc_avail(&tq->tx_ring)) {
1004 tq->stats.tx_ring_full++;
fdcd79b9 1005 netdev_dbg(adapter->netdev,
09c5088e
SB		 1006 "tx queue stopped on %s, next2comp %u"
1007 " next2fill %u\n", adapter->netdev->name,
1008 tq->tx_ring.next2comp, tq->tx_ring.next2fill);
1009
1010 vmxnet3_tq_stop(tq, adapter);
1011 spin_unlock_irqrestore(&tq->tx_lock, flags);
1012 return NETDEV_TX_BUSY;
1013 }
1014
1015
d1a890fa
SB		 1016 ret = vmxnet3_parse_and_copy_hdr(skb, tq, &ctx, adapter);
1017 if (ret >= 0) {
1018 BUG_ON(ret <= 0 && ctx.copy_size != 0);
1019 /* hdrs parsed, check against other limits */
1020 if (ctx.mss) {
1021 if (unlikely(ctx.eth_ip_hdr_size + ctx.l4_hdr_size >
1022 VMXNET3_MAX_TX_BUF_SIZE)) {
1023 goto hdr_too_big;
1024 }
1025 } else {
1026 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1027 if (unlikely(ctx.eth_ip_hdr_size +
1028 skb->csum_offset >
1029 VMXNET3_MAX_CSUM_OFFSET)) {
1030 goto hdr_too_big;
1031 }
1032 }
1033 }
1034 } else {
1035 tq->stats.drop_hdr_inspect_err++;
f955e141 1036 goto unlock_drop_pkt;
d1a890fa
SB		 1037 }
1038
d1a890fa 1039 /* fill tx descs related to addr & len */
5738a09d
AK		 1040 if (vmxnet3_map_pkt(skb, &ctx, tq, adapter->pdev, adapter))
1041 goto unlock_drop_pkt;
d1a890fa
SB		 1042
1043 /* setup the EOP desc */
115924b6 1044 ctx.eop_txd->dword[3] = cpu_to_le32(VMXNET3_TXD_CQ | VMXNET3_TXD_EOP);
d1a890fa
SB		 1045
1046 /* setup the SOP desc */
115924b6
SB		 1047#ifdef __BIG_ENDIAN_BITFIELD
1048 gdesc = &tempTxDesc;
1049 gdesc->dword[2] = ctx.sop_txd->dword[2];
1050 gdesc->dword[3] = ctx.sop_txd->dword[3];
1051#else
d1a890fa 1052 gdesc = ctx.sop_txd;
115924b6 1053#endif
d1a890fa
SB		 1054 if (ctx.mss) {
1055 gdesc->txd.hlen = ctx.eth_ip_hdr_size + ctx.l4_hdr_size;
1056 gdesc->txd.om = VMXNET3_OM_TSO;
1057 gdesc->txd.msscof = ctx.mss;
115924b6
SB		 1058 le32_add_cpu(&tq->shared->txNumDeferred, (skb->len -
1059 gdesc->txd.hlen + ctx.mss - 1) / ctx.mss);
d1a890fa
SB		 1060 } else {
1061 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1062 gdesc->txd.hlen = ctx.eth_ip_hdr_size;
1063 gdesc->txd.om = VMXNET3_OM_CSUM;
1064 gdesc->txd.msscof = ctx.eth_ip_hdr_size +
1065 skb->csum_offset;
1066 } else {
1067 gdesc->txd.om = 0;
1068 gdesc->txd.msscof = 0;
1069 }
115924b6 1070 le32_add_cpu(&tq->shared->txNumDeferred, 1);
d1a890fa
SB		 1071 }
1072
df8a39de 1073 if (skb_vlan_tag_present(skb)) {
d1a890fa 1074 gdesc->txd.ti = 1;
df8a39de 1075 gdesc->txd.tci = skb_vlan_tag_get(skb);
d1a890fa
SB		 1076 }
1077
115924b6
SB		 1078 /* finally flips the GEN bit of the SOP desc. */
1079 gdesc->dword[2] = cpu_to_le32(le32_to_cpu(gdesc->dword[2]) ^
1080 VMXNET3_TXD_GEN);
1081#ifdef __BIG_ENDIAN_BITFIELD
1082 /* Finished updating in bitfields of Tx Desc, so write them in original
1083 * place.
1084 */
1085 vmxnet3_TxDescToLe((struct Vmxnet3_TxDesc *)gdesc,
1086 (struct Vmxnet3_TxDesc *)ctx.sop_txd);
1087 gdesc = ctx.sop_txd;
1088#endif
fdcd79b9 1089 netdev_dbg(adapter->netdev,
f6965582 1090 "txd[%u]: SOP 0x%Lx 0x%x 0x%x\n",
c2fd03a0 1091 (u32)(ctx.sop_txd -
115924b6
SB		 1092 tq->tx_ring.base), le64_to_cpu(gdesc->txd.addr),
1093 le32_to_cpu(gdesc->dword[2]), le32_to_cpu(gdesc->dword[3]));
d1a890fa
SB		 1094
1095 spin_unlock_irqrestore(&tq->tx_lock, flags);
1096
115924b6
SB		 1097 if (le32_to_cpu(tq->shared->txNumDeferred) >=
1098 le32_to_cpu(tq->shared->txThreshold)) {
d1a890fa 1099 tq->shared->txNumDeferred = 0;
09c5088e
SB		 1100 VMXNET3_WRITE_BAR0_REG(adapter,
1101 VMXNET3_REG_TXPROD + tq->qid * 8,
d1a890fa
SB		 1102 tq->tx_ring.next2fill);
1103 }
d1a890fa
SB		 1104
1105 return NETDEV_TX_OK;
1106
1107hdr_too_big:
1108 tq->stats.drop_oversized_hdr++;
f955e141
DC		 1109unlock_drop_pkt:
1110 spin_unlock_irqrestore(&tq->tx_lock, flags);
d1a890fa
SB		 1111drop_pkt:
1112 tq->stats.drop_total++;
b1b71817 1113 dev_kfree_skb_any(skb);
d1a890fa
SB		 1114 return NETDEV_TX_OK;
1115}
1116
1117
1118static netdev_tx_t
1119vmxnet3_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1120{
1121 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
d1a890fa 1122
96800ee7 1123 BUG_ON(skb->queue_mapping > adapter->num_tx_queues);
1124 return vmxnet3_tq_xmit(skb,
1125 &adapter->tx_queue[skb->queue_mapping],
1126 adapter, netdev);
d1a890fa
SB		 1127}
1128
1129
1130static void
1131vmxnet3_rx_csum(struct vmxnet3_adapter *adapter,
1132 struct sk_buff *skb,
1133 union Vmxnet3_GenericDesc *gdesc)
1134{
a0d2730c 1135 if (!gdesc->rcd.cnc && adapter->netdev->features & NETIF_F_RXCSUM) {
d1a890fa 1136 /* typical case: TCP/UDP over IP and both csums are correct */
115924b6 1137 if ((le32_to_cpu(gdesc->dword[3]) & VMXNET3_RCD_CSUM_OK) ==
d1a890fa
SB		 1138 VMXNET3_RCD_CSUM_OK) {
1139 skb->ip_summed = CHECKSUM_UNNECESSARY;
1140 BUG_ON(!(gdesc->rcd.tcp || gdesc->rcd.udp));
1141 BUG_ON(!(gdesc->rcd.v4 || gdesc->rcd.v6));
1142 BUG_ON(gdesc->rcd.frg);
1143 } else {
1144 if (gdesc->rcd.csum) {
1145 skb->csum = htons(gdesc->rcd.csum);
1146 skb->ip_summed = CHECKSUM_PARTIAL;
1147 } else {
bc8acf2c 1148 skb_checksum_none_assert(skb);
d1a890fa
SB		 1149 }
1150 }
1151 } else {
bc8acf2c 1152 skb_checksum_none_assert(skb);
d1a890fa
SB		 1153 }
1154}
1155
1156
1157static void
1158vmxnet3_rx_error(struct vmxnet3_rx_queue *rq, struct Vmxnet3_RxCompDesc *rcd,
1159 struct vmxnet3_rx_ctx *ctx, struct vmxnet3_adapter *adapter)
1160{
1161 rq->stats.drop_err++;
1162 if (!rcd->fcs)
1163 rq->stats.drop_fcs++;
1164
1165 rq->stats.drop_total++;
1166
1167 /*
1168 * We do not unmap and chain the rx buffer to the skb.
1169 * We basically pretend this buffer is not used and will be recycled
1170 * by vmxnet3_rq_alloc_rx_buf()
1171 */
1172
1173 /*
1174 * ctx->skb may be NULL if this is the first and the only one
1175 * desc for the pkt
1176 */
1177 if (ctx->skb)
1178 dev_kfree_skb_irq(ctx->skb);
1179
1180 ctx->skb = NULL;
1181}
1182
1183
45dac1d6
SB		 1184static u32
1185vmxnet3_get_hdr_len(struct vmxnet3_adapter *adapter, struct sk_buff *skb,
1186 union Vmxnet3_GenericDesc *gdesc)
1187{
1188 u32 hlen, maplen;
1189 union {
1190 void *ptr;
1191 struct ethhdr *eth;
1192 struct iphdr *ipv4;
1193 struct ipv6hdr *ipv6;
1194 struct tcphdr *tcp;
1195 } hdr;
1196 BUG_ON(gdesc->rcd.tcp == 0);
1197
1198 maplen = skb_headlen(skb);
1199 if (unlikely(sizeof(struct iphdr) + sizeof(struct tcphdr) > maplen))
1200 return 0;
1201
1202 hdr.eth = eth_hdr(skb);
1203 if (gdesc->rcd.v4) {
1204 BUG_ON(hdr.eth->h_proto != htons(ETH_P_IP));
1205 hdr.ptr += sizeof(struct ethhdr);
1206 BUG_ON(hdr.ipv4->protocol != IPPROTO_TCP);
1207 hlen = hdr.ipv4->ihl << 2;
1208 hdr.ptr += hdr.ipv4->ihl << 2;
1209 } else if (gdesc->rcd.v6) {
1210 BUG_ON(hdr.eth->h_proto != htons(ETH_P_IPV6));
1211 hdr.ptr += sizeof(struct ethhdr);
1212 /* Use an estimated value, since we also need to handle
1213 * TSO case.
1214 */
1215 if (hdr.ipv6->nexthdr != IPPROTO_TCP)
1216 return sizeof(struct ipv6hdr) + sizeof(struct tcphdr);
1217 hlen = sizeof(struct ipv6hdr);
1218 hdr.ptr += sizeof(struct ipv6hdr);
1219 } else {
1220 /* Non-IP pkt, dont estimate header length */
1221 return 0;
1222 }
1223
1224 if (hlen + sizeof(struct tcphdr) > maplen)
1225 return 0;
1226
1227 return (hlen + (hdr.tcp->doff << 2));
1228}
1229
d1a890fa
SB		 1230static int
1231vmxnet3_rq_rx_complete(struct vmxnet3_rx_queue *rq,
1232 struct vmxnet3_adapter *adapter, int quota)
1233{
215faf9c
JP		 1234 static const u32 rxprod_reg[2] = {
1235 VMXNET3_REG_RXPROD, VMXNET3_REG_RXPROD2
1236 };
0769636c 1237 u32 num_pkts = 0;
5318d809 1238 bool skip_page_frags = false;
d1a890fa
SB		 1239 struct Vmxnet3_RxCompDesc *rcd;
1240 struct vmxnet3_rx_ctx *ctx = &rq->rx_ctx;
45dac1d6 1241 u16 segCnt = 0, mss = 0;
115924b6
SB		 1242#ifdef __BIG_ENDIAN_BITFIELD
1243 struct Vmxnet3_RxDesc rxCmdDesc;
1244 struct Vmxnet3_RxCompDesc rxComp;
1245#endif
1246 vmxnet3_getRxComp(rcd, &rq->comp_ring.base[rq->comp_ring.next2proc].rcd,
1247 &rxComp);
d1a890fa
SB		 1248 while (rcd->gen == rq->comp_ring.gen) {
1249 struct vmxnet3_rx_buf_info *rbi;
5318d809
SB		 1250 struct sk_buff *skb, *new_skb = NULL;
1251 struct page *new_page = NULL;
5738a09d 1252 dma_addr_t new_dma_addr;
d1a890fa
SB		 1253 int num_to_alloc;
1254 struct Vmxnet3_RxDesc *rxd;
1255 u32 idx, ring_idx;
5318d809 1256 struct vmxnet3_cmd_ring *ring = NULL;
0769636c 1257 if (num_pkts >= quota) {
d1a890fa
SB		 1258 /* we may stop even before we see the EOP desc of
1259 * the current pkt
1260 */
1261 break;
1262 }
09c5088e 1263 BUG_ON(rcd->rqID != rq->qid && rcd->rqID != rq->qid2);
d1a890fa 1264 idx = rcd->rxdIdx;
09c5088e 1265 ring_idx = rcd->rqID < adapter->num_rx_queues ? 0 : 1;
5318d809 1266 ring = rq->rx_ring + ring_idx;
115924b6
SB		 1267 vmxnet3_getRxDesc(rxd, &rq->rx_ring[ring_idx].base[idx].rxd,
1268 &rxCmdDesc);
d1a890fa
SB		 1269 rbi = rq->buf_info[ring_idx] + idx;
1270
115924b6
SB		 1271 BUG_ON(rxd->addr != rbi->dma_addr ||
1272 rxd->len != rbi->len);
d1a890fa
SB		 1273
1274 if (unlikely(rcd->eop && rcd->err)) {
1275 vmxnet3_rx_error(rq, rcd, ctx, adapter);
1276 goto rcd_done;
1277 }
1278
1279 if (rcd->sop) { /* first buf of the pkt */
1280 BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_HEAD ||
1281 rcd->rqID != rq->qid);
1282
1283 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_SKB);
1284 BUG_ON(ctx->skb != NULL || rbi->skb == NULL);
1285
1286 if (unlikely(rcd->len == 0)) {
1287 /* Pretend the rx buffer is skipped. */
1288 BUG_ON(!(rcd->sop && rcd->eop));
fdcd79b9 1289 netdev_dbg(adapter->netdev,
f6965582 1290 "rxRing[%u][%u] 0 length\n",
d1a890fa
SB		 1291 ring_idx, idx);
1292 goto rcd_done;
1293 }
1294
5318d809 1295 skip_page_frags = false;
d1a890fa 1296 ctx->skb = rbi->skb;
0d735f13
SH		 1297 new_skb = netdev_alloc_skb_ip_align(adapter->netdev,
1298 rbi->len);
5318d809
SB		 1299 if (new_skb == NULL) {
1300 /* Skb allocation failed, do not handover this
1301 * skb to stack. Reuse it. Drop the existing pkt
1302 */
1303 rq->stats.rx_buf_alloc_failure++;
1304 ctx->skb = NULL;
1305 rq->stats.drop_total++;
1306 skip_page_frags = true;
1307 goto rcd_done;
1308 }
5738a09d
AK		 1309 new_dma_addr = dma_map_single(&adapter->pdev->dev,
1310 new_skb->data, rbi->len,
1311 PCI_DMA_FROMDEVICE);
1312 if (dma_mapping_error(&adapter->pdev->dev,
1313 new_dma_addr)) {
1314 dev_kfree_skb(new_skb);
1315 /* Skb allocation failed, do not handover this
1316 * skb to stack. Reuse it. Drop the existing pkt
1317 */
1318 rq->stats.rx_buf_alloc_failure++;
1319 ctx->skb = NULL;
1320 rq->stats.drop_total++;
1321 skip_page_frags = true;
1322 goto rcd_done;
1323 }
d1a890fa 1324
b0eb57cb
AK		 1325 dma_unmap_single(&adapter->pdev->dev, rbi->dma_addr,
1326 rbi->len,
d1a890fa
SB		 1327 PCI_DMA_FROMDEVICE);
1328
7db11f75
SH		 1329#ifdef VMXNET3_RSS
1330 if (rcd->rssType != VMXNET3_RCD_RSS_TYPE_NONE &&
1331 (adapter->netdev->features & NETIF_F_RXHASH))
2c15a154
MS		 1332 skb_set_hash(ctx->skb,
1333 le32_to_cpu(rcd->rssHash),
0b680703 1334 PKT_HASH_TYPE_L3);
7db11f75 1335#endif
d1a890fa 1336 skb_put(ctx->skb, rcd->len);
5318d809
SB		 1337
1338 /* Immediate refill */
5318d809 1339 rbi->skb = new_skb;
5738a09d 1340 rbi->dma_addr = new_dma_addr;
5318d809
SB		 1341 rxd->addr = cpu_to_le64(rbi->dma_addr);
1342 rxd->len = rbi->len;
45dac1d6
SB		 1343 if (adapter->version == 2 &&
1344 rcd->type == VMXNET3_CDTYPE_RXCOMP_LRO) {
1345 struct Vmxnet3_RxCompDescExt *rcdlro;
1346 rcdlro = (struct Vmxnet3_RxCompDescExt *)rcd;
1347
1348 segCnt = rcdlro->segCnt;
1349 BUG_ON(segCnt <= 1);
1350 mss = rcdlro->mss;
1351 if (unlikely(segCnt <= 1))
1352 segCnt = 0;
1353 } else {
1354 segCnt = 0;
1355 }
d1a890fa 1356 } else {
5318d809
SB		 1357 BUG_ON(ctx->skb == NULL && !skip_page_frags);
1358
d1a890fa 1359 /* non SOP buffer must be type 1 in most cases */
5318d809
SB		 1360 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE);
1361 BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_BODY);
d1a890fa 1362
5318d809
SB		 1363 /* If an sop buffer was dropped, skip all
1364 * following non-sop fragments. They will be reused.
1365 */
1366 if (skip_page_frags)
1367 goto rcd_done;
d1a890fa 1368
c41fcce9
SB		 1369 if (rcd->len) {
1370 new_page = alloc_page(GFP_ATOMIC);
5318d809
SB		 1371 /* Replacement page frag could not be allocated.
1372 * Reuse this page. Drop the pkt and free the
1373 * skb which contained this page as a frag. Skip
1374 * processing all the following non-sop frags.
d1a890fa 1375 */
c41fcce9
SB		 1376 if (unlikely(!new_page)) {
1377 rq->stats.rx_buf_alloc_failure++;
1378 dev_kfree_skb(ctx->skb);
1379 ctx->skb = NULL;
1380 skip_page_frags = true;
1381 goto rcd_done;
1382 }
5738a09d
AK		 1383 new_dma_addr = dma_map_page(&adapter->pdev->dev
1384 , rbi->page,
1385 0, PAGE_SIZE,
1386 PCI_DMA_FROMDEVICE);
1387 if (dma_mapping_error(&adapter->pdev->dev,
1388 new_dma_addr)) {
1389 put_page(new_page);
1390 rq->stats.rx_buf_alloc_failure++;
1391 dev_kfree_skb(ctx->skb);
1392 ctx->skb = NULL;
1393 skip_page_frags = true;
1394 goto rcd_done;
1395 }
5318d809 1396
b0eb57cb 1397 dma_unmap_page(&adapter->pdev->dev,
5318d809
SB		 1398 rbi->dma_addr, rbi->len,
1399 PCI_DMA_FROMDEVICE);
1400
1401 vmxnet3_append_frag(ctx->skb, rcd, rbi);
5318d809 1402
c41fcce9
SB		 1403 /* Immediate refill */
1404 rbi->page = new_page;
5738a09d 1405 rbi->dma_addr = new_dma_addr;
c41fcce9
SB		 1406 rxd->addr = cpu_to_le64(rbi->dma_addr);
1407 rxd->len = rbi->len;
1408 }
d1a890fa
SB		 1409 }
1410
5318d809 1411
d1a890fa
SB		 1412 skb = ctx->skb;
1413 if (rcd->eop) {
45dac1d6 1414 u32 mtu = adapter->netdev->mtu;
d1a890fa 1415 skb->len += skb->data_len;
d1a890fa
SB		 1416
1417 vmxnet3_rx_csum(adapter, skb,
1418 (union Vmxnet3_GenericDesc *)rcd);
1419 skb->protocol = eth_type_trans(skb, adapter->netdev);
45dac1d6
SB		 1420 if (!rcd->tcp || !adapter->lro)
1421 goto not_lro;
1422
1423 if (segCnt != 0 && mss != 0) {
1424 skb_shinfo(skb)->gso_type = rcd->v4 ?
1425 SKB_GSO_TCPV4 : SKB_GSO_TCPV6;
1426 skb_shinfo(skb)->gso_size = mss;
1427 skb_shinfo(skb)->gso_segs = segCnt;
1428 } else if (segCnt != 0 || skb->len > mtu) {
1429 u32 hlen;
1430
1431 hlen = vmxnet3_get_hdr_len(adapter, skb,
1432 (union Vmxnet3_GenericDesc *)rcd);
1433 if (hlen == 0)
1434 goto not_lro;
1435
1436 skb_shinfo(skb)->gso_type =
1437 rcd->v4 ? SKB_GSO_TCPV4 : SKB_GSO_TCPV6;
1438 if (segCnt != 0) {
1439 skb_shinfo(skb)->gso_segs = segCnt;
1440 skb_shinfo(skb)->gso_size =
1441 DIV_ROUND_UP(skb->len -
1442 hlen, segCnt);
1443 } else {
1444 skb_shinfo(skb)->gso_size = mtu - hlen;
1445 }
1446 }
1447not_lro:
72e85c45 1448 if (unlikely(rcd->ts))
86a9bad3 1449 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), rcd->tci);
72e85c45 1450
213ade8c
JG		 1451 if (adapter->netdev->features & NETIF_F_LRO)
1452 netif_receive_skb(skb);
1453 else
1454 napi_gro_receive(&rq->napi, skb);
d1a890fa 1455
d1a890fa 1456 ctx->skb = NULL;
0769636c 1457 num_pkts++;
d1a890fa
SB		 1458 }
1459
1460rcd_done:
5318d809
SB		 1461 /* device may have skipped some rx descs */
1462 ring->next2comp = idx;
1463 num_to_alloc = vmxnet3_cmd_ring_desc_avail(ring);
1464 ring = rq->rx_ring + ring_idx;
1465 while (num_to_alloc) {
1466 vmxnet3_getRxDesc(rxd, &ring->base[ring->next2fill].rxd,
1467 &rxCmdDesc);
1468 BUG_ON(!rxd->addr);
1469
1470 /* Recv desc is ready to be used by the device */
1471 rxd->gen = ring->gen;
1472 vmxnet3_cmd_ring_adv_next2fill(ring);
1473 num_to_alloc--;
1474 }
1475
1476 /* if needed, update the register */
1477 if (unlikely(rq->shared->updateRxProd)) {
1478 VMXNET3_WRITE_BAR0_REG(adapter,
96800ee7 1479 rxprod_reg[ring_idx] + rq->qid * 8,
1480 ring->next2fill);
d1a890fa
SB		 1481 }
1482
1483 vmxnet3_comp_ring_adv_next2proc(&rq->comp_ring);
115924b6 1484 vmxnet3_getRxComp(rcd,
96800ee7 1485 &rq->comp_ring.base[rq->comp_ring.next2proc].rcd, &rxComp);
d1a890fa
SB		 1486 }
1487
0769636c 1488 return num_pkts;
d1a890fa
SB		 1489}
1490
1491
1492static void
1493vmxnet3_rq_cleanup(struct vmxnet3_rx_queue *rq,
1494 struct vmxnet3_adapter *adapter)
1495{
1496 u32 i, ring_idx;
1497 struct Vmxnet3_RxDesc *rxd;
1498
1499 for (ring_idx = 0; ring_idx < 2; ring_idx++) {
1500 for (i = 0; i < rq->rx_ring[ring_idx].size; i++) {
115924b6
SB		 1501#ifdef __BIG_ENDIAN_BITFIELD
1502 struct Vmxnet3_RxDesc rxDesc;
1503#endif
1504 vmxnet3_getRxDesc(rxd,
1505 &rq->rx_ring[ring_idx].base[i].rxd, &rxDesc);
d1a890fa
SB		 1506
1507 if (rxd->btype == VMXNET3_RXD_BTYPE_HEAD &&
1508 rq->buf_info[ring_idx][i].skb) {
b0eb57cb 1509 dma_unmap_single(&adapter->pdev->dev, rxd->addr,
d1a890fa
SB		 1510 rxd->len, PCI_DMA_FROMDEVICE);
1511 dev_kfree_skb(rq->buf_info[ring_idx][i].skb);
1512 rq->buf_info[ring_idx][i].skb = NULL;
1513 } else if (rxd->btype == VMXNET3_RXD_BTYPE_BODY &&
1514 rq->buf_info[ring_idx][i].page) {
b0eb57cb 1515 dma_unmap_page(&adapter->pdev->dev, rxd->addr,
d1a890fa
SB		 1516 rxd->len, PCI_DMA_FROMDEVICE);
1517 put_page(rq->buf_info[ring_idx][i].page);
1518 rq->buf_info[ring_idx][i].page = NULL;
1519 }
1520 }
1521
1522 rq->rx_ring[ring_idx].gen = VMXNET3_INIT_GEN;
1523 rq->rx_ring[ring_idx].next2fill =
1524 rq->rx_ring[ring_idx].next2comp = 0;
d1a890fa
SB		 1525 }
1526
1527 rq->comp_ring.gen = VMXNET3_INIT_GEN;
1528 rq->comp_ring.next2proc = 0;
1529}
1530
1531
09c5088e
SB		 1532static void
1533vmxnet3_rq_cleanup_all(struct vmxnet3_adapter *adapter)
1534{
1535 int i;
1536
1537 for (i = 0; i < adapter->num_rx_queues; i++)
1538 vmxnet3_rq_cleanup(&adapter->rx_queue[i], adapter);
1539}
1540
1541
280b74f7 1542static void vmxnet3_rq_destroy(struct vmxnet3_rx_queue *rq,
1543 struct vmxnet3_adapter *adapter)
d1a890fa
SB		 1544{
1545 int i;
1546 int j;
1547
1548 /* all rx buffers must have already been freed */
1549 for (i = 0; i < 2; i++) {
1550 if (rq->buf_info[i]) {
1551 for (j = 0; j < rq->rx_ring[i].size; j++)
1552 BUG_ON(rq->buf_info[i][j].page != NULL);
1553 }
1554 }
1555
1556
d1a890fa
SB		 1557 for (i = 0; i < 2; i++) {
1558 if (rq->rx_ring[i].base) {
b0eb57cb
AK		 1559 dma_free_coherent(&adapter->pdev->dev,
1560 rq->rx_ring[i].size
1561 * sizeof(struct Vmxnet3_RxDesc),
1562 rq->rx_ring[i].base,
1563 rq->rx_ring[i].basePA);
d1a890fa
SB		 1564 rq->rx_ring[i].base = NULL;
1565 }
1566 rq->buf_info[i] = NULL;
1567 }
1568
1569 if (rq->comp_ring.base) {
b0eb57cb
AK		 1570 dma_free_coherent(&adapter->pdev->dev, rq->comp_ring.size
1571 * sizeof(struct Vmxnet3_RxCompDesc),
1572 rq->comp_ring.base, rq->comp_ring.basePA);
d1a890fa
SB		 1573 rq->comp_ring.base = NULL;
1574 }
b0eb57cb
AK		 1575
1576 if (rq->buf_info[0]) {
1577 size_t sz = sizeof(struct vmxnet3_rx_buf_info) *
1578 (rq->rx_ring[0].size + rq->rx_ring[1].size);
1579 dma_free_coherent(&adapter->pdev->dev, sz, rq->buf_info[0],
1580 rq->buf_info_pa);
1581 }
d1a890fa
SB		 1582}
1583
1584
1585static int
1586vmxnet3_rq_init(struct vmxnet3_rx_queue *rq,
1587 struct vmxnet3_adapter *adapter)
1588{
1589 int i;
1590
1591 /* initialize buf_info */
1592 for (i = 0; i < rq->rx_ring[0].size; i++) {
1593
1594 /* 1st buf for a pkt is skbuff */
1595 if (i % adapter->rx_buf_per_pkt == 0) {
1596 rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_SKB;
1597 rq->buf_info[0][i].len = adapter->skb_buf_size;
1598 } else { /* subsequent bufs for a pkt is frag */
1599 rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_PAGE;
1600 rq->buf_info[0][i].len = PAGE_SIZE;
1601 }
1602 }
1603 for (i = 0; i < rq->rx_ring[1].size; i++) {
1604 rq->buf_info[1][i].buf_type = VMXNET3_RX_BUF_PAGE;
1605 rq->buf_info[1][i].len = PAGE_SIZE;
1606 }
1607
1608 /* reset internal state and allocate buffers for both rings */
1609 for (i = 0; i < 2; i++) {
1610 rq->rx_ring[i].next2fill = rq->rx_ring[i].next2comp = 0;
d1a890fa
SB		 1611
1612 memset(rq->rx_ring[i].base, 0, rq->rx_ring[i].size *
1613 sizeof(struct Vmxnet3_RxDesc));
1614 rq->rx_ring[i].gen = VMXNET3_INIT_GEN;
1615 }
1616 if (vmxnet3_rq_alloc_rx_buf(rq, 0, rq->rx_ring[0].size - 1,
1617 adapter) == 0) {
1618 /* at least has 1 rx buffer for the 1st ring */
1619 return -ENOMEM;
1620 }
1621 vmxnet3_rq_alloc_rx_buf(rq, 1, rq->rx_ring[1].size - 1, adapter);
1622
1623 /* reset the comp ring */
1624 rq->comp_ring.next2proc = 0;
1625 memset(rq->comp_ring.base, 0, rq->comp_ring.size *
1626 sizeof(struct Vmxnet3_RxCompDesc));
1627 rq->comp_ring.gen = VMXNET3_INIT_GEN;
1628
1629 /* reset rxctx */
1630 rq->rx_ctx.skb = NULL;
1631
1632 /* stats are not reset */
1633 return 0;
1634}
1635
1636
09c5088e
SB		 1637static int
1638vmxnet3_rq_init_all(struct vmxnet3_adapter *adapter)
1639{
1640 int i, err = 0;
1641
1642 for (i = 0; i < adapter->num_rx_queues; i++) {
1643 err = vmxnet3_rq_init(&adapter->rx_queue[i], adapter);
1644 if (unlikely(err)) {
1645 dev_err(&adapter->netdev->dev, "%s: failed to "
1646 "initialize rx queue%i\n",
1647 adapter->netdev->name, i);
1648 break;
1649 }
1650 }
1651 return err;
1652
1653}
1654
1655
d1a890fa
SB		 1656static int
1657vmxnet3_rq_create(struct vmxnet3_rx_queue *rq, struct vmxnet3_adapter *adapter)
1658{
1659 int i;
1660 size_t sz;
1661 struct vmxnet3_rx_buf_info *bi;
1662
1663 for (i = 0; i < 2; i++) {
1664
1665 sz = rq->rx_ring[i].size * sizeof(struct Vmxnet3_RxDesc);
b0eb57cb
AK		 1666 rq->rx_ring[i].base = dma_alloc_coherent(
1667 &adapter->pdev->dev, sz,
1668 &rq->rx_ring[i].basePA,
1669 GFP_KERNEL);
d1a890fa 1670 if (!rq->rx_ring[i].base) {
204a6e65
SH		 1671 netdev_err(adapter->netdev,
1672 "failed to allocate rx ring %d\n", i);
d1a890fa
SB		 1673 goto err;
1674 }
1675 }
1676
1677 sz = rq->comp_ring.size * sizeof(struct Vmxnet3_RxCompDesc);
b0eb57cb
AK		 1678 rq->comp_ring.base = dma_alloc_coherent(&adapter->pdev->dev, sz,
1679 &rq->comp_ring.basePA,
1680 GFP_KERNEL);
d1a890fa 1681 if (!rq->comp_ring.base) {
204a6e65 1682 netdev_err(adapter->netdev, "failed to allocate rx comp ring\n");
d1a890fa
SB		 1683 goto err;
1684 }
1685
1686 sz = sizeof(struct vmxnet3_rx_buf_info) * (rq->rx_ring[0].size +
1687 rq->rx_ring[1].size);
b0eb57cb
AK		 1688 bi = dma_zalloc_coherent(&adapter->pdev->dev, sz, &rq->buf_info_pa,
1689 GFP_KERNEL);
e404decb 1690 if (!bi)
d1a890fa 1691 goto err;
e404decb 1692
d1a890fa
SB		 1693 rq->buf_info[0] = bi;
1694 rq->buf_info[1] = bi + rq->rx_ring[0].size;
1695
1696 return 0;
1697
1698err:
1699 vmxnet3_rq_destroy(rq, adapter);
1700 return -ENOMEM;
1701}
1702
1703
09c5088e
SB		 1704static int
1705vmxnet3_rq_create_all(struct vmxnet3_adapter *adapter)
1706{
1707 int i, err = 0;
1708
1709 for (i = 0; i < adapter->num_rx_queues; i++) {
1710 err = vmxnet3_rq_create(&adapter->rx_queue[i], adapter);
1711 if (unlikely(err)) {
1712 dev_err(&adapter->netdev->dev,
1713 "%s: failed to create rx queue%i\n",
1714 adapter->netdev->name, i);
1715 goto err_out;
1716 }
1717 }
1718 return err;
1719err_out:
1720 vmxnet3_rq_destroy_all(adapter);
1721 return err;
1722
1723}
1724
1725/* Multiple queue aware polling function for tx and rx */
1726
d1a890fa
SB		 1727static int
1728vmxnet3_do_poll(struct vmxnet3_adapter *adapter, int budget)
1729{
09c5088e 1730 int rcd_done = 0, i;
d1a890fa
SB		 1731 if (unlikely(adapter->shared->ecr))
1732 vmxnet3_process_events(adapter);
09c5088e
SB		 1733 for (i = 0; i < adapter->num_tx_queues; i++)
1734 vmxnet3_tq_tx_complete(&adapter->tx_queue[i], adapter);
d1a890fa 1735
09c5088e
SB		 1736 for (i = 0; i < adapter->num_rx_queues; i++)
1737 rcd_done += vmxnet3_rq_rx_complete(&adapter->rx_queue[i],
1738 adapter, budget);
1739 return rcd_done;
d1a890fa
SB		 1740}
1741
1742
1743static int
1744vmxnet3_poll(struct napi_struct *napi, int budget)
1745{
09c5088e
SB		 1746 struct vmxnet3_rx_queue *rx_queue = container_of(napi,
1747 struct vmxnet3_rx_queue, napi);
1748 int rxd_done;
1749
1750 rxd_done = vmxnet3_do_poll(rx_queue->adapter, budget);
1751
1752 if (rxd_done < budget) {
1753 napi_complete(napi);
1754 vmxnet3_enable_all_intrs(rx_queue->adapter);
1755 }
1756 return rxd_done;
1757}
1758
1759/*
1760 * NAPI polling function for MSI-X mode with multiple Rx queues
1761 * Returns the # of the NAPI credit consumed (# of rx descriptors processed)
1762 */
1763
1764static int
1765vmxnet3_poll_rx_only(struct napi_struct *napi, int budget)
1766{
1767 struct vmxnet3_rx_queue *rq = container_of(napi,
1768 struct vmxnet3_rx_queue, napi);
1769 struct vmxnet3_adapter *adapter = rq->adapter;
d1a890fa
SB		 1770 int rxd_done;
1771
09c5088e
SB		 1772 /* When sharing interrupt with corresponding tx queue, process
1773 * tx completions in that queue as well
1774 */
1775 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE) {
1776 struct vmxnet3_tx_queue *tq =
1777 &adapter->tx_queue[rq - adapter->rx_queue];
1778 vmxnet3_tq_tx_complete(tq, adapter);
1779 }
1780
1781 rxd_done = vmxnet3_rq_rx_complete(rq, adapter, budget);
d1a890fa
SB		 1782
1783 if (rxd_done < budget) {
1784 napi_complete(napi);
09c5088e 1785 vmxnet3_enable_intr(adapter, rq->comp_ring.intr_idx);
d1a890fa
SB		 1786 }
1787 return rxd_done;
1788}
1789
1790
09c5088e
SB		 1791#ifdef CONFIG_PCI_MSI
1792
1793/*
1794 * Handle completion interrupts on tx queues
1795 * Returns whether or not the intr is handled
1796 */
1797
1798static irqreturn_t
1799vmxnet3_msix_tx(int irq, void *data)
1800{
1801 struct vmxnet3_tx_queue *tq = data;
1802 struct vmxnet3_adapter *adapter = tq->adapter;
1803
1804 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
1805 vmxnet3_disable_intr(adapter, tq->comp_ring.intr_idx);
1806
1807 /* Handle the case where only one irq is allocate for all tx queues */
1808 if (adapter->share_intr == VMXNET3_INTR_TXSHARE) {
1809 int i;
1810 for (i = 0; i < adapter->num_tx_queues; i++) {
1811 struct vmxnet3_tx_queue *txq = &adapter->tx_queue[i];
1812 vmxnet3_tq_tx_complete(txq, adapter);
1813 }
1814 } else {
1815 vmxnet3_tq_tx_complete(tq, adapter);
1816 }
1817 vmxnet3_enable_intr(adapter, tq->comp_ring.intr_idx);
1818
1819 return IRQ_HANDLED;
1820}
1821
1822
1823/*
1824 * Handle completion interrupts on rx queues. Returns whether or not the
1825 * intr is handled
1826 */
1827
1828static irqreturn_t
1829vmxnet3_msix_rx(int irq, void *data)
1830{
1831 struct vmxnet3_rx_queue *rq = data;
1832 struct vmxnet3_adapter *adapter = rq->adapter;
1833
1834 /* disable intr if needed */
1835 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
1836 vmxnet3_disable_intr(adapter, rq->comp_ring.intr_idx);
1837 napi_schedule(&rq->napi);
1838
1839 return IRQ_HANDLED;
1840}
1841
1842/*
1843 *----------------------------------------------------------------------------
1844 *
1845 * vmxnet3_msix_event --
1846 *
1847 * vmxnet3 msix event intr handler
1848 *
1849 * Result:
1850 * whether or not the intr is handled
1851 *
1852 *----------------------------------------------------------------------------
1853 */
1854
1855static irqreturn_t
1856vmxnet3_msix_event(int irq, void *data)
1857{
1858 struct net_device *dev = data;
1859 struct vmxnet3_adapter *adapter = netdev_priv(dev);
1860
1861 /* disable intr if needed */
1862 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
1863 vmxnet3_disable_intr(adapter, adapter->intr.event_intr_idx);
1864
1865 if (adapter->shared->ecr)
1866 vmxnet3_process_events(adapter);
1867
1868 vmxnet3_enable_intr(adapter, adapter->intr.event_intr_idx);
1869
1870 return IRQ_HANDLED;
1871}
1872
1873#endif /* CONFIG_PCI_MSI */
1874
1875
d1a890fa
SB		 1876/* Interrupt handler for vmxnet3 */
1877static irqreturn_t
1878vmxnet3_intr(int irq, void *dev_id)
1879{
1880 struct net_device *dev = dev_id;
1881 struct vmxnet3_adapter *adapter = netdev_priv(dev);
1882
09c5088e 1883 if (adapter->intr.type == VMXNET3_IT_INTX) {
d1a890fa
SB		 1884 u32 icr = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_ICR);
1885 if (unlikely(icr == 0))
1886 /* not ours */
1887 return IRQ_NONE;
1888 }
1889
1890
1891 /* disable intr if needed */
1892 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
09c5088e 1893 vmxnet3_disable_all_intrs(adapter);
d1a890fa 1894
09c5088e 1895 napi_schedule(&adapter->rx_queue[0].napi);
d1a890fa
SB		 1896
1897 return IRQ_HANDLED;
1898}
1899
1900#ifdef CONFIG_NET_POLL_CONTROLLER
1901
d1a890fa
SB		 1902/* netpoll callback. */
1903static void
1904vmxnet3_netpoll(struct net_device *netdev)
1905{
1906 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
d1a890fa 1907
d25f06ea 1908 switch (adapter->intr.type) {
0a8d8c44
AB		 1909#ifdef CONFIG_PCI_MSI
1910 case VMXNET3_IT_MSIX: {
1911 int i;
d25f06ea
NH		 1912 for (i = 0; i < adapter->num_rx_queues; i++)
1913 vmxnet3_msix_rx(0, &adapter->rx_queue[i]);
1914 break;
0a8d8c44
AB		 1915 }
1916#endif
d25f06ea
NH		 1917 case VMXNET3_IT_MSI:
1918 default:
1919 vmxnet3_intr(0, adapter->netdev);
1920 break;
1921 }
d1a890fa 1922
d1a890fa 1923}
09c5088e 1924#endif /* CONFIG_NET_POLL_CONTROLLER */
d1a890fa
SB		 1925
1926static int
1927vmxnet3_request_irqs(struct vmxnet3_adapter *adapter)
1928{
09c5088e
SB		 1929 struct vmxnet3_intr *intr = &adapter->intr;
1930 int err = 0, i;
1931 int vector = 0;
d1a890fa 1932
8f7e524c 1933#ifdef CONFIG_PCI_MSI
d1a890fa 1934 if (adapter->intr.type == VMXNET3_IT_MSIX) {
09c5088e
SB		 1935 for (i = 0; i < adapter->num_tx_queues; i++) {
1936 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) {
1937 sprintf(adapter->tx_queue[i].name, "%s-tx-%d",
1938 adapter->netdev->name, vector);
1939 err = request_irq(
1940 intr->msix_entries[vector].vector,
1941 vmxnet3_msix_tx, 0,
1942 adapter->tx_queue[i].name,
1943 &adapter->tx_queue[i]);
1944 } else {
1945 sprintf(adapter->tx_queue[i].name, "%s-rxtx-%d",
1946 adapter->netdev->name, vector);
1947 }
1948 if (err) {
1949 dev_err(&adapter->netdev->dev,
1950 "Failed to request irq for MSIX, %s, "
1951 "error %d\n",
1952 adapter->tx_queue[i].name, err);
1953 return err;
1954 }
1955
1956 /* Handle the case where only 1 MSIx was allocated for
1957 * all tx queues */
1958 if (adapter->share_intr == VMXNET3_INTR_TXSHARE) {
1959 for (; i < adapter->num_tx_queues; i++)
1960 adapter->tx_queue[i].comp_ring.intr_idx
1961 = vector;
1962 vector++;
1963 break;
1964 } else {
1965 adapter->tx_queue[i].comp_ring.intr_idx
1966 = vector++;
1967 }
1968 }
1969 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE)
1970 vector = 0;
1971
1972 for (i = 0; i < adapter->num_rx_queues; i++) {
1973 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE)
1974 sprintf(adapter->rx_queue[i].name, "%s-rx-%d",
1975 adapter->netdev->name, vector);
1976 else
1977 sprintf(adapter->rx_queue[i].name, "%s-rxtx-%d",
1978 adapter->netdev->name, vector);
1979 err = request_irq(intr->msix_entries[vector].vector,
1980 vmxnet3_msix_rx, 0,
1981 adapter->rx_queue[i].name,
1982 &(adapter->rx_queue[i]));
1983 if (err) {
204a6e65
SH		 1984 netdev_err(adapter->netdev,
1985 "Failed to request irq for MSIX, "
1986 "%s, error %d\n",
1987 adapter->rx_queue[i].name, err);
09c5088e
SB		 1988 return err;
1989 }
1990
1991 adapter->rx_queue[i].comp_ring.intr_idx = vector++;
1992 }
1993
1994 sprintf(intr->event_msi_vector_name, "%s-event-%d",
1995 adapter->netdev->name, vector);
1996 err = request_irq(intr->msix_entries[vector].vector,
1997 vmxnet3_msix_event, 0,
1998 intr->event_msi_vector_name, adapter->netdev);
1999 intr->event_intr_idx = vector;
2000
2001 } else if (intr->type == VMXNET3_IT_MSI) {
2002 adapter->num_rx_queues = 1;
d1a890fa
SB		 2003 err = request_irq(adapter->pdev->irq, vmxnet3_intr, 0,
2004 adapter->netdev->name, adapter->netdev);
09c5088e 2005 } else {
115924b6 2006#endif
09c5088e 2007 adapter->num_rx_queues = 1;
d1a890fa
SB		 2008 err = request_irq(adapter->pdev->irq, vmxnet3_intr,
2009 IRQF_SHARED, adapter->netdev->name,
2010 adapter->netdev);
09c5088e 2011#ifdef CONFIG_PCI_MSI
d1a890fa 2012 }
09c5088e
SB		 2013#endif
2014 intr->num_intrs = vector + 1;
2015 if (err) {
204a6e65
SH		 2016 netdev_err(adapter->netdev,
2017 "Failed to request irq (intr type:%d), error %d\n",
2018 intr->type, err);
09c5088e
SB		 2019 } else {
2020 /* Number of rx queues will not change after this */
2021 for (i = 0; i < adapter->num_rx_queues; i++) {
2022 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
2023 rq->qid = i;
2024 rq->qid2 = i + adapter->num_rx_queues;
2025 }
d1a890fa
SB		 2026
2027
d1a890fa 2028
09c5088e
SB		 2029 /* init our intr settings */
2030 for (i = 0; i < intr->num_intrs; i++)
2031 intr->mod_levels[i] = UPT1_IML_ADAPTIVE;
2032 if (adapter->intr.type != VMXNET3_IT_MSIX) {
2033 adapter->intr.event_intr_idx = 0;
2034 for (i = 0; i < adapter->num_tx_queues; i++)
2035 adapter->tx_queue[i].comp_ring.intr_idx = 0;
2036 adapter->rx_queue[0].comp_ring.intr_idx = 0;
2037 }
d1a890fa 2038
204a6e65
SH		 2039 netdev_info(adapter->netdev,
2040 "intr type %u, mode %u, %u vectors allocated\n",
2041 intr->type, intr->mask_mode, intr->num_intrs);
d1a890fa
SB		 2042 }
2043
2044 return err;
2045}
2046
2047
2048static void
2049vmxnet3_free_irqs(struct vmxnet3_adapter *adapter)
2050{
09c5088e
SB		 2051 struct vmxnet3_intr *intr = &adapter->intr;
2052 BUG_ON(intr->type == VMXNET3_IT_AUTO || intr->num_intrs <= 0);
d1a890fa 2053
09c5088e 2054 switch (intr->type) {
8f7e524c 2055#ifdef CONFIG_PCI_MSI
d1a890fa
SB		 2056 case VMXNET3_IT_MSIX:
2057 {
09c5088e 2058 int i, vector = 0;
d1a890fa 2059
09c5088e
SB		 2060 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) {
2061 for (i = 0; i < adapter->num_tx_queues; i++) {
2062 free_irq(intr->msix_entries[vector++].vector,
2063 &(adapter->tx_queue[i]));
2064 if (adapter->share_intr == VMXNET3_INTR_TXSHARE)
2065 break;
2066 }
2067 }
2068
2069 for (i = 0; i < adapter->num_rx_queues; i++) {
2070 free_irq(intr->msix_entries[vector++].vector,
2071 &(adapter->rx_queue[i]));
2072 }
2073
2074 free_irq(intr->msix_entries[vector].vector,
2075 adapter->netdev);
2076 BUG_ON(vector >= intr->num_intrs);
d1a890fa
SB		 2077 break;
2078 }
8f7e524c 2079#endif
d1a890fa
SB		 2080 case VMXNET3_IT_MSI:
2081 free_irq(adapter->pdev->irq, adapter->netdev);
2082 break;
2083 case VMXNET3_IT_INTX:
2084 free_irq(adapter->pdev->irq, adapter->netdev);
2085 break;
2086 default:
c068e777 2087 BUG();
d1a890fa
SB		 2088 }
2089}
2090
d1a890fa
SB		 2091
2092static void
2093vmxnet3_restore_vlan(struct vmxnet3_adapter *adapter)
2094{
72e85c45
JG		 2095 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
2096 u16 vid;
d1a890fa 2097
72e85c45
JG		 2098 /* allow untagged pkts */
2099 VMXNET3_SET_VFTABLE_ENTRY(vfTable, 0);
2100
2101 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
2102 VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid);
d1a890fa
SB		 2103}
2104
2105
8e586137 2106static int
80d5c368 2107vmxnet3_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, u16 vid)
d1a890fa
SB		 2108{
2109 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
d1a890fa 2110
f6957f88
JG		 2111 if (!(netdev->flags & IFF_PROMISC)) {
2112 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
2113 unsigned long flags;
2114
2115 VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid);
2116 spin_lock_irqsave(&adapter->cmd_lock, flags);
2117 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2118 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
2119 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2120 }
72e85c45
JG		 2121
2122 set_bit(vid, adapter->active_vlans);
8e586137
JP		 2123
2124 return 0;
d1a890fa
SB		 2125}
2126
2127
8e586137 2128static int
80d5c368 2129vmxnet3_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, u16 vid)
d1a890fa
SB		 2130{
2131 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
d1a890fa 2132
f6957f88
JG		 2133 if (!(netdev->flags & IFF_PROMISC)) {
2134 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
2135 unsigned long flags;
2136
2137 VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid);
2138 spin_lock_irqsave(&adapter->cmd_lock, flags);
2139 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2140 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
2141 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2142 }
72e85c45
JG		 2143
2144 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 2145
2146 return 0;
d1a890fa
SB		 2147}
2148
2149
2150static u8 *
2151vmxnet3_copy_mc(struct net_device *netdev)
2152{
2153 u8 *buf = NULL;
4cd24eaf 2154 u32 sz = netdev_mc_count(netdev) * ETH_ALEN;
d1a890fa
SB		 2155
2156 /* struct Vmxnet3_RxFilterConf.mfTableLen is u16. */
2157 if (sz <= 0xffff) {
2158 /* We may be called with BH disabled */
2159 buf = kmalloc(sz, GFP_ATOMIC);
2160 if (buf) {
22bedad3 2161 struct netdev_hw_addr *ha;
567ec874 2162 int i = 0;
d1a890fa 2163
22bedad3
JP		 2164 netdev_for_each_mc_addr(ha, netdev)
2165 memcpy(buf + i++ * ETH_ALEN, ha->addr,
d1a890fa 2166 ETH_ALEN);
d1a890fa
SB		 2167 }
2168 }
2169 return buf;
2170}
2171
2172
2173static void
2174vmxnet3_set_mc(struct net_device *netdev)
2175{
2176 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
83d0feff 2177 unsigned long flags;
d1a890fa
SB		 2178 struct Vmxnet3_RxFilterConf *rxConf =
2179 &adapter->shared->devRead.rxFilterConf;
2180 u8 *new_table = NULL;
b0eb57cb 2181 dma_addr_t new_table_pa = 0;
d1a890fa
SB		 2182 u32 new_mode = VMXNET3_RXM_UCAST;
2183
72e85c45
JG		 2184 if (netdev->flags & IFF_PROMISC) {
2185 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
2186 memset(vfTable, 0, VMXNET3_VFT_SIZE * sizeof(*vfTable));
2187
d1a890fa 2188 new_mode |= VMXNET3_RXM_PROMISC;
72e85c45
JG		 2189 } else {
2190 vmxnet3_restore_vlan(adapter);
2191 }
d1a890fa
SB		 2192
2193 if (netdev->flags & IFF_BROADCAST)
2194 new_mode |= VMXNET3_RXM_BCAST;
2195
2196 if (netdev->flags & IFF_ALLMULTI)
2197 new_mode |= VMXNET3_RXM_ALL_MULTI;
2198 else
4cd24eaf 2199 if (!netdev_mc_empty(netdev)) {
d1a890fa
SB		 2200 new_table = vmxnet3_copy_mc(netdev);
2201 if (new_table) {
d37d5ec8
SK		 2202 size_t sz = netdev_mc_count(netdev) * ETH_ALEN;
2203
2204 rxConf->mfTableLen = cpu_to_le16(sz);
b0eb57cb
AK		 2205 new_table_pa = dma_map_single(
2206 &adapter->pdev->dev,
2207 new_table,
d37d5ec8 2208 sz,
b0eb57cb 2209 PCI_DMA_TODEVICE);
4ad9a64f
AK		 2210 }
2211
5738a09d
AK		 2212 if (!dma_mapping_error(&adapter->pdev->dev,
2213 new_table_pa)) {
4ad9a64f 2214 new_mode |= VMXNET3_RXM_MCAST;
b0eb57cb 2215 rxConf->mfTablePA = cpu_to_le64(new_table_pa);
d1a890fa 2216 } else {
4ad9a64f
AK		 2217 netdev_info(netdev,
2218 "failed to copy mcast list, setting ALL_MULTI\n");
d1a890fa
SB		 2219 new_mode |= VMXNET3_RXM_ALL_MULTI;
2220 }
2221 }
2222
d1a890fa
SB		 2223 if (!(new_mode & VMXNET3_RXM_MCAST)) {
2224 rxConf->mfTableLen = 0;
2225 rxConf->mfTablePA = 0;
2226 }
2227
83d0feff 2228 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa 2229 if (new_mode != rxConf->rxMode) {
115924b6 2230 rxConf->rxMode = cpu_to_le32(new_mode);
d1a890fa
SB		 2231 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2232 VMXNET3_CMD_UPDATE_RX_MODE);
72e85c45
JG		 2233 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2234 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
d1a890fa
SB		 2235 }
2236
2237 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2238 VMXNET3_CMD_UPDATE_MAC_FILTERS);
83d0feff 2239 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
d1a890fa 2240
4ad9a64f 2241 if (new_table_pa)
b0eb57cb
AK		 2242 dma_unmap_single(&adapter->pdev->dev, new_table_pa,
2243 rxConf->mfTableLen, PCI_DMA_TODEVICE);
4ad9a64f 2244 kfree(new_table);
d1a890fa
SB		 2245}
2246
09c5088e
SB		 2247void
2248vmxnet3_rq_destroy_all(struct vmxnet3_adapter *adapter)
2249{
2250 int i;
2251
2252 for (i = 0; i < adapter->num_rx_queues; i++)
2253 vmxnet3_rq_destroy(&adapter->rx_queue[i], adapter);
2254}
2255
d1a890fa
SB		 2256
2257/*
2258 * Set up driver_shared based on settings in adapter.
2259 */
2260
2261static void
2262vmxnet3_setup_driver_shared(struct vmxnet3_adapter *adapter)
2263{
2264 struct Vmxnet3_DriverShared *shared = adapter->shared;
2265 struct Vmxnet3_DSDevRead *devRead = &shared->devRead;
2266 struct Vmxnet3_TxQueueConf *tqc;
2267 struct Vmxnet3_RxQueueConf *rqc;
2268 int i;
2269
2270 memset(shared, 0, sizeof(*shared));
2271
2272 /* driver settings */
115924b6
SB		 2273 shared->magic = cpu_to_le32(VMXNET3_REV1_MAGIC);
2274 devRead->misc.driverInfo.version = cpu_to_le32(
2275 VMXNET3_DRIVER_VERSION_NUM);
d1a890fa
SB		 2276 devRead->misc.driverInfo.gos.gosBits = (sizeof(void *) == 4 ?
2277 VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64);
2278 devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX;
115924b6
SB		 2279 *((u32 *)&devRead->misc.driverInfo.gos) = cpu_to_le32(
2280 *((u32 *)&devRead->misc.driverInfo.gos));
2281 devRead->misc.driverInfo.vmxnet3RevSpt = cpu_to_le32(1);
2282 devRead->misc.driverInfo.uptVerSpt = cpu_to_le32(1);
d1a890fa 2283
b0eb57cb 2284 devRead->misc.ddPA = cpu_to_le64(adapter->adapter_pa);
115924b6 2285 devRead->misc.ddLen = cpu_to_le32(sizeof(struct vmxnet3_adapter));
d1a890fa
SB		 2286
2287 /* set up feature flags */
a0d2730c 2288 if (adapter->netdev->features & NETIF_F_RXCSUM)
3843e515 2289 devRead->misc.uptFeatures |= UPT1_F_RXCSUM;
d1a890fa 2290
a0d2730c 2291 if (adapter->netdev->features & NETIF_F_LRO) {
3843e515 2292 devRead->misc.uptFeatures |= UPT1_F_LRO;
115924b6 2293 devRead->misc.maxNumRxSG = cpu_to_le16(1 + MAX_SKB_FRAGS);
d1a890fa 2294 }
f646968f 2295 if (adapter->netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
3843e515 2296 devRead->misc.uptFeatures |= UPT1_F_RXVLAN;
d1a890fa 2297
115924b6
SB		 2298 devRead->misc.mtu = cpu_to_le32(adapter->netdev->mtu);
2299 devRead->misc.queueDescPA = cpu_to_le64(adapter->queue_desc_pa);
2300 devRead->misc.queueDescLen = cpu_to_le32(
09c5088e
SB		 2301 adapter->num_tx_queues * sizeof(struct Vmxnet3_TxQueueDesc) +
2302 adapter->num_rx_queues * sizeof(struct Vmxnet3_RxQueueDesc));
d1a890fa
SB		 2303
2304 /* tx queue settings */
09c5088e
SB		 2305 devRead->misc.numTxQueues = adapter->num_tx_queues;
2306 for (i = 0; i < adapter->num_tx_queues; i++) {
2307 struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i];
2308 BUG_ON(adapter->tx_queue[i].tx_ring.base == NULL);
2309 tqc = &adapter->tqd_start[i].conf;
2310 tqc->txRingBasePA = cpu_to_le64(tq->tx_ring.basePA);
2311 tqc->dataRingBasePA = cpu_to_le64(tq->data_ring.basePA);
2312 tqc->compRingBasePA = cpu_to_le64(tq->comp_ring.basePA);
b0eb57cb 2313 tqc->ddPA = cpu_to_le64(tq->buf_info_pa);
09c5088e
SB		 2314 tqc->txRingSize = cpu_to_le32(tq->tx_ring.size);
2315 tqc->dataRingSize = cpu_to_le32(tq->data_ring.size);
2316 tqc->compRingSize = cpu_to_le32(tq->comp_ring.size);
2317 tqc->ddLen = cpu_to_le32(
2318 sizeof(struct vmxnet3_tx_buf_info) *
2319 tqc->txRingSize);
2320 tqc->intrIdx = tq->comp_ring.intr_idx;
2321 }
d1a890fa
SB		 2322
2323 /* rx queue settings */
09c5088e
SB		 2324 devRead->misc.numRxQueues = adapter->num_rx_queues;
2325 for (i = 0; i < adapter->num_rx_queues; i++) {
2326 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
2327 rqc = &adapter->rqd_start[i].conf;
2328 rqc->rxRingBasePA[0] = cpu_to_le64(rq->rx_ring[0].basePA);
2329 rqc->rxRingBasePA[1] = cpu_to_le64(rq->rx_ring[1].basePA);
2330 rqc->compRingBasePA = cpu_to_le64(rq->comp_ring.basePA);
b0eb57cb 2331 rqc->ddPA = cpu_to_le64(rq->buf_info_pa);
09c5088e
SB		 2332 rqc->rxRingSize[0] = cpu_to_le32(rq->rx_ring[0].size);
2333 rqc->rxRingSize[1] = cpu_to_le32(rq->rx_ring[1].size);
2334 rqc->compRingSize = cpu_to_le32(rq->comp_ring.size);
2335 rqc->ddLen = cpu_to_le32(
2336 sizeof(struct vmxnet3_rx_buf_info) *
2337 (rqc->rxRingSize[0] +
2338 rqc->rxRingSize[1]));
2339 rqc->intrIdx = rq->comp_ring.intr_idx;
2340 }
2341
2342#ifdef VMXNET3_RSS
2343 memset(adapter->rss_conf, 0, sizeof(*adapter->rss_conf));
2344
2345 if (adapter->rss) {
2346 struct UPT1_RSSConf *rssConf = adapter->rss_conf;
66d35910 2347
09c5088e
SB		 2348 devRead->misc.uptFeatures |= UPT1_F_RSS;
2349 devRead->misc.numRxQueues = adapter->num_rx_queues;
2350 rssConf->hashType = UPT1_RSS_HASH_TYPE_TCP_IPV4 |
2351 UPT1_RSS_HASH_TYPE_IPV4 |
2352 UPT1_RSS_HASH_TYPE_TCP_IPV6 |
2353 UPT1_RSS_HASH_TYPE_IPV6;
2354 rssConf->hashFunc = UPT1_RSS_HASH_FUNC_TOEPLITZ;
2355 rssConf->hashKeySize = UPT1_RSS_MAX_KEY_SIZE;
2356 rssConf->indTableSize = VMXNET3_RSS_IND_TABLE_SIZE;
6bf79cdd 2357 netdev_rss_key_fill(rssConf->hashKey, sizeof(rssConf->hashKey));
66d35910 2358
09c5088e 2359 for (i = 0; i < rssConf->indTableSize; i++)
278bc429
BH		 2360 rssConf->indTable[i] = ethtool_rxfh_indir_default(
2361 i, adapter->num_rx_queues);
09c5088e
SB		 2362
2363 devRead->rssConfDesc.confVer = 1;
b0eb57cb
AK		 2364 devRead->rssConfDesc.confLen = cpu_to_le32(sizeof(*rssConf));
2365 devRead->rssConfDesc.confPA =
2366 cpu_to_le64(adapter->rss_conf_pa);
09c5088e
SB		 2367 }
2368
2369#endif /* VMXNET3_RSS */
d1a890fa
SB		 2370
2371 /* intr settings */
2372 devRead->intrConf.autoMask = adapter->intr.mask_mode ==
2373 VMXNET3_IMM_AUTO;
2374 devRead->intrConf.numIntrs = adapter->intr.num_intrs;
2375 for (i = 0; i < adapter->intr.num_intrs; i++)
2376 devRead->intrConf.modLevels[i] = adapter->intr.mod_levels[i];
2377
2378 devRead->intrConf.eventIntrIdx = adapter->intr.event_intr_idx;
6929fe8a 2379 devRead->intrConf.intrCtrl |= cpu_to_le32(VMXNET3_IC_DISABLE_ALL);
d1a890fa
SB		 2380
2381 /* rx filter settings */
2382 devRead->rxFilterConf.rxMode = 0;
2383 vmxnet3_restore_vlan(adapter);
f9f25026
SB		 2384 vmxnet3_write_mac_addr(adapter, adapter->netdev->dev_addr);
2385
d1a890fa
SB		 2386 /* the rest are already zeroed */
2387}
2388
2389
2390int
2391vmxnet3_activate_dev(struct vmxnet3_adapter *adapter)
2392{
09c5088e 2393 int err, i;
d1a890fa 2394 u32 ret;
83d0feff 2395 unsigned long flags;
d1a890fa 2396
fdcd79b9 2397 netdev_dbg(adapter->netdev, "%s: skb_buf_size %d, rx_buf_per_pkt %d,"
09c5088e
SB		 2398 " ring sizes %u %u %u\n", adapter->netdev->name,
2399 adapter->skb_buf_size, adapter->rx_buf_per_pkt,
2400 adapter->tx_queue[0].tx_ring.size,
2401 adapter->rx_queue[0].rx_ring[0].size,
2402 adapter->rx_queue[0].rx_ring[1].size);
2403
2404 vmxnet3_tq_init_all(adapter);
2405 err = vmxnet3_rq_init_all(adapter);
d1a890fa 2406 if (err) {
204a6e65
SH		 2407 netdev_err(adapter->netdev,
2408 "Failed to init rx queue error %d\n", err);
d1a890fa
SB		 2409 goto rq_err;
2410 }
2411
2412 err = vmxnet3_request_irqs(adapter);
2413 if (err) {
204a6e65
SH		 2414 netdev_err(adapter->netdev,
2415 "Failed to setup irq for error %d\n", err);
d1a890fa
SB		 2416 goto irq_err;
2417 }
2418
2419 vmxnet3_setup_driver_shared(adapter);
2420
115924b6
SB		 2421 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, VMXNET3_GET_ADDR_LO(
2422 adapter->shared_pa));
2423 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, VMXNET3_GET_ADDR_HI(
2424 adapter->shared_pa));
83d0feff 2425 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa
SB		 2426 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2427 VMXNET3_CMD_ACTIVATE_DEV);
2428 ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
83d0feff 2429 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
d1a890fa
SB		 2430
2431 if (ret != 0) {
204a6e65
SH		 2432 netdev_err(adapter->netdev,
2433 "Failed to activate dev: error %u\n", ret);
d1a890fa
SB		 2434 err = -EINVAL;
2435 goto activate_err;
2436 }
09c5088e
SB		 2437
2438 for (i = 0; i < adapter->num_rx_queues; i++) {
2439 VMXNET3_WRITE_BAR0_REG(adapter,
2440 VMXNET3_REG_RXPROD + i * VMXNET3_REG_ALIGN,
2441 adapter->rx_queue[i].rx_ring[0].next2fill);
2442 VMXNET3_WRITE_BAR0_REG(adapter, (VMXNET3_REG_RXPROD2 +
2443 (i * VMXNET3_REG_ALIGN)),
2444 adapter->rx_queue[i].rx_ring[1].next2fill);
2445 }
d1a890fa
SB		 2446
2447 /* Apply the rx filter settins last. */
2448 vmxnet3_set_mc(adapter->netdev);
2449
2450 /*
2451 * Check link state when first activating device. It will start the
2452 * tx queue if the link is up.
2453 */
4a1745fc 2454 vmxnet3_check_link(adapter, true);
09c5088e
SB		 2455 for (i = 0; i < adapter->num_rx_queues; i++)
2456 napi_enable(&adapter->rx_queue[i].napi);
d1a890fa
SB		 2457 vmxnet3_enable_all_intrs(adapter);
2458 clear_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state);
2459 return 0;
2460
2461activate_err:
2462 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, 0);
2463 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, 0);
2464 vmxnet3_free_irqs(adapter);
2465irq_err:
2466rq_err:
2467 /* free up buffers we allocated */
09c5088e 2468 vmxnet3_rq_cleanup_all(adapter);
d1a890fa
SB		 2469 return err;
2470}
2471
2472
2473void
2474vmxnet3_reset_dev(struct vmxnet3_adapter *adapter)
2475{
83d0feff
SB		 2476 unsigned long flags;
2477 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa 2478 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV);
83d0feff 2479 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
d1a890fa
SB		 2480}
2481
2482
2483int
2484vmxnet3_quiesce_dev(struct vmxnet3_adapter *adapter)
2485{
09c5088e 2486 int i;
83d0feff 2487 unsigned long flags;
d1a890fa
SB		 2488 if (test_and_set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state))
2489 return 0;
2490
2491
83d0feff 2492 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa
SB		 2493 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2494 VMXNET3_CMD_QUIESCE_DEV);
83d0feff 2495 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
d1a890fa
SB		 2496 vmxnet3_disable_all_intrs(adapter);
2497
09c5088e
SB		 2498 for (i = 0; i < adapter->num_rx_queues; i++)
2499 napi_disable(&adapter->rx_queue[i].napi);
d1a890fa
SB		 2500 netif_tx_disable(adapter->netdev);
2501 adapter->link_speed = 0;
2502 netif_carrier_off(adapter->netdev);
2503
09c5088e
SB		 2504 vmxnet3_tq_cleanup_all(adapter);
2505 vmxnet3_rq_cleanup_all(adapter);
d1a890fa
SB		 2506 vmxnet3_free_irqs(adapter);
2507 return 0;
2508}
2509
2510
2511static void
2512vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac)
2513{
2514 u32 tmp;
2515
2516 tmp = *(u32 *)mac;
2517 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACL, tmp);
2518
2519 tmp = (mac[5] << 8) | mac[4];
2520 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACH, tmp);
2521}
2522
2523
2524static int
2525vmxnet3_set_mac_addr(struct net_device *netdev, void *p)
2526{
2527 struct sockaddr *addr = p;
2528 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2529
2530 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2531 vmxnet3_write_mac_addr(adapter, addr->sa_data);
2532
2533 return 0;
2534}
2535
2536
2537/* ==================== initialization and cleanup routines ============ */
2538
2539static int
2540vmxnet3_alloc_pci_resources(struct vmxnet3_adapter *adapter, bool *dma64)
2541{
2542 int err;
2543 unsigned long mmio_start, mmio_len;
2544 struct pci_dev *pdev = adapter->pdev;
2545
2546 err = pci_enable_device(pdev);
2547 if (err) {
204a6e65 2548 dev_err(&pdev->dev, "Failed to enable adapter: error %d\n", err);
d1a890fa
SB		 2549 return err;
2550 }
2551
2552 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) == 0) {
2553 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) {
204a6e65
SH		 2554 dev_err(&pdev->dev,
2555 "pci_set_consistent_dma_mask failed\n");
d1a890fa
SB		 2556 err = -EIO;
2557 goto err_set_mask;
2558 }
2559 *dma64 = true;
2560 } else {
2561 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) {
204a6e65
SH		 2562 dev_err(&pdev->dev,
2563 "pci_set_dma_mask failed\n");
d1a890fa
SB		 2564 err = -EIO;
2565 goto err_set_mask;
2566 }
2567 *dma64 = false;
2568 }
2569
2570 err = pci_request_selected_regions(pdev, (1 << 2) - 1,
2571 vmxnet3_driver_name);
2572 if (err) {
204a6e65
SH		 2573 dev_err(&pdev->dev,
2574 "Failed to request region for adapter: error %d\n", err);
d1a890fa
SB		 2575 goto err_set_mask;
2576 }
2577
2578 pci_set_master(pdev);
2579
2580 mmio_start = pci_resource_start(pdev, 0);
2581 mmio_len = pci_resource_len(pdev, 0);
2582 adapter->hw_addr0 = ioremap(mmio_start, mmio_len);
2583 if (!adapter->hw_addr0) {
204a6e65 2584 dev_err(&pdev->dev, "Failed to map bar0\n");
d1a890fa
SB		 2585 err = -EIO;
2586 goto err_ioremap;
2587 }
2588
2589 mmio_start = pci_resource_start(pdev, 1);
2590 mmio_len = pci_resource_len(pdev, 1);
2591 adapter->hw_addr1 = ioremap(mmio_start, mmio_len);
2592 if (!adapter->hw_addr1) {
204a6e65 2593 dev_err(&pdev->dev, "Failed to map bar1\n");
d1a890fa
SB		 2594 err = -EIO;
2595 goto err_bar1;
2596 }
2597 return 0;
2598
2599err_bar1:
2600 iounmap(adapter->hw_addr0);
2601err_ioremap:
2602 pci_release_selected_regions(pdev, (1 << 2) - 1);
2603err_set_mask:
2604 pci_disable_device(pdev);
2605 return err;
2606}
2607
2608
2609static void
2610vmxnet3_free_pci_resources(struct vmxnet3_adapter *adapter)
2611{
2612 BUG_ON(!adapter->pdev);
2613
2614 iounmap(adapter->hw_addr0);
2615 iounmap(adapter->hw_addr1);
2616 pci_release_selected_regions(adapter->pdev, (1 << 2) - 1);
2617 pci_disable_device(adapter->pdev);
2618}
2619
2620
2621static void
2622vmxnet3_adjust_rx_ring_size(struct vmxnet3_adapter *adapter)
2623{
09c5088e
SB		 2624 size_t sz, i, ring0_size, ring1_size, comp_size;
2625 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[0];
2626
d1a890fa
SB		 2627
2628 if (adapter->netdev->mtu <= VMXNET3_MAX_SKB_BUF_SIZE -
2629 VMXNET3_MAX_ETH_HDR_SIZE) {
2630 adapter->skb_buf_size = adapter->netdev->mtu +
2631 VMXNET3_MAX_ETH_HDR_SIZE;
2632 if (adapter->skb_buf_size < VMXNET3_MIN_T0_BUF_SIZE)
2633 adapter->skb_buf_size = VMXNET3_MIN_T0_BUF_SIZE;
2634
2635 adapter->rx_buf_per_pkt = 1;
2636 } else {
2637 adapter->skb_buf_size = VMXNET3_MAX_SKB_BUF_SIZE;
2638 sz = adapter->netdev->mtu - VMXNET3_MAX_SKB_BUF_SIZE +
2639 VMXNET3_MAX_ETH_HDR_SIZE;
2640 adapter->rx_buf_per_pkt = 1 + (sz + PAGE_SIZE - 1) / PAGE_SIZE;
2641 }
2642
2643 /*
2644 * for simplicity, force the ring0 size to be a multiple of
2645 * rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN
2646 */
2647 sz = adapter->rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN;
09c5088e
SB		 2648 ring0_size = adapter->rx_queue[0].rx_ring[0].size;
2649 ring0_size = (ring0_size + sz - 1) / sz * sz;
a53255d3 2650 ring0_size = min_t(u32, ring0_size, VMXNET3_RX_RING_MAX_SIZE /
09c5088e
SB		 2651 sz * sz);
2652 ring1_size = adapter->rx_queue[0].rx_ring[1].size;
53831aa1
SK		 2653 ring1_size = (ring1_size + sz - 1) / sz * sz;
2654 ring1_size = min_t(u32, ring1_size, VMXNET3_RX_RING2_MAX_SIZE /
2655 sz * sz);
09c5088e
SB		 2656 comp_size = ring0_size + ring1_size;
2657
2658 for (i = 0; i < adapter->num_rx_queues; i++) {
2659 rq = &adapter->rx_queue[i];
2660 rq->rx_ring[0].size = ring0_size;
2661 rq->rx_ring[1].size = ring1_size;
2662 rq->comp_ring.size = comp_size;
2663 }
d1a890fa
SB		 2664}
2665
2666
2667int
2668vmxnet3_create_queues(struct vmxnet3_adapter *adapter, u32 tx_ring_size,
2669 u32 rx_ring_size, u32 rx_ring2_size)
2670{
09c5088e
SB		 2671 int err = 0, i;
2672
2673 for (i = 0; i < adapter->num_tx_queues; i++) {
2674 struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i];
2675 tq->tx_ring.size = tx_ring_size;
2676 tq->data_ring.size = tx_ring_size;
2677 tq->comp_ring.size = tx_ring_size;
2678 tq->shared = &adapter->tqd_start[i].ctrl;
2679 tq->stopped = true;
2680 tq->adapter = adapter;
2681 tq->qid = i;
2682 err = vmxnet3_tq_create(tq, adapter);
2683 /*
2684 * Too late to change num_tx_queues. We cannot do away with
2685 * lesser number of queues than what we asked for
2686 */
2687 if (err)
2688 goto queue_err;
2689 }
d1a890fa 2690
09c5088e
SB		 2691 adapter->rx_queue[0].rx_ring[0].size = rx_ring_size;
2692 adapter->rx_queue[0].rx_ring[1].size = rx_ring2_size;
d1a890fa 2693 vmxnet3_adjust_rx_ring_size(adapter);
09c5088e
SB		 2694 for (i = 0; i < adapter->num_rx_queues; i++) {
2695 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
2696 /* qid and qid2 for rx queues will be assigned later when num
2697 * of rx queues is finalized after allocating intrs */
2698 rq->shared = &adapter->rqd_start[i].ctrl;
2699 rq->adapter = adapter;
2700 err = vmxnet3_rq_create(rq, adapter);
2701 if (err) {
2702 if (i == 0) {
204a6e65
SH		 2703 netdev_err(adapter->netdev,
2704 "Could not allocate any rx queues. "
2705 "Aborting.\n");
09c5088e
SB		 2706 goto queue_err;
2707 } else {
204a6e65
SH		 2708 netdev_info(adapter->netdev,
2709 "Number of rx queues changed "
2710 "to : %d.\n", i);
09c5088e
SB		 2711 adapter->num_rx_queues = i;
2712 err = 0;
2713 break;
2714 }
2715 }
2716 }
2717 return err;
2718queue_err:
2719 vmxnet3_tq_destroy_all(adapter);
d1a890fa
SB		 2720 return err;
2721}
2722
2723static int
2724vmxnet3_open(struct net_device *netdev)
2725{
2726 struct vmxnet3_adapter *adapter;
09c5088e 2727 int err, i;
d1a890fa
SB		 2728
2729 adapter = netdev_priv(netdev);
2730
09c5088e
SB		 2731 for (i = 0; i < adapter->num_tx_queues; i++)
2732 spin_lock_init(&adapter->tx_queue[i].tx_lock);
d1a890fa 2733
f00e2b0a
NH		 2734 err = vmxnet3_create_queues(adapter, adapter->tx_ring_size,
2735 adapter->rx_ring_size,
53831aa1 2736 adapter->rx_ring2_size);
d1a890fa
SB		 2737 if (err)
2738 goto queue_err;
2739
2740 err = vmxnet3_activate_dev(adapter);
2741 if (err)
2742 goto activate_err;
2743
2744 return 0;
2745
2746activate_err:
09c5088e
SB		 2747 vmxnet3_rq_destroy_all(adapter);
2748 vmxnet3_tq_destroy_all(adapter);
d1a890fa
SB		 2749queue_err:
2750 return err;
2751}
2752
2753
2754static int
2755vmxnet3_close(struct net_device *netdev)
2756{
2757 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2758
2759 /*
2760 * Reset_work may be in the middle of resetting the device, wait for its
2761 * completion.
2762 */
2763 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
2764 msleep(1);
2765
2766 vmxnet3_quiesce_dev(adapter);
2767
09c5088e
SB		 2768 vmxnet3_rq_destroy_all(adapter);
2769 vmxnet3_tq_destroy_all(adapter);
d1a890fa
SB		 2770
2771 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
2772
2773
2774 return 0;
2775}
2776
2777
2778void
2779vmxnet3_force_close(struct vmxnet3_adapter *adapter)
2780{
09c5088e
SB		 2781 int i;
2782
d1a890fa
SB		 2783 /*
2784 * we must clear VMXNET3_STATE_BIT_RESETTING, otherwise
2785 * vmxnet3_close() will deadlock.
2786 */
2787 BUG_ON(test_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state));
2788
2789 /* we need to enable NAPI, otherwise dev_close will deadlock */
09c5088e
SB		 2790 for (i = 0; i < adapter->num_rx_queues; i++)
2791 napi_enable(&adapter->rx_queue[i].napi);
d1a890fa
SB		 2792 dev_close(adapter->netdev);
2793}
2794
2795
2796static int
2797vmxnet3_change_mtu(struct net_device *netdev, int new_mtu)
2798{
2799 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2800 int err = 0;
2801
2802 if (new_mtu < VMXNET3_MIN_MTU || new_mtu > VMXNET3_MAX_MTU)
2803 return -EINVAL;
2804
d1a890fa
SB		 2805 netdev->mtu = new_mtu;
2806
2807 /*
2808 * Reset_work may be in the middle of resetting the device, wait for its
2809 * completion.
2810 */
2811 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
2812 msleep(1);
2813
2814 if (netif_running(netdev)) {
2815 vmxnet3_quiesce_dev(adapter);
2816 vmxnet3_reset_dev(adapter);
2817
2818 /* we need to re-create the rx queue based on the new mtu */
09c5088e 2819 vmxnet3_rq_destroy_all(adapter);
d1a890fa 2820 vmxnet3_adjust_rx_ring_size(adapter);
09c5088e 2821 err = vmxnet3_rq_create_all(adapter);
d1a890fa 2822 if (err) {
204a6e65
SH		 2823 netdev_err(netdev,
2824 "failed to re-create rx queues, "
2825 " error %d. Closing it.\n", err);
d1a890fa
SB		 2826 goto out;
2827 }
2828
2829 err = vmxnet3_activate_dev(adapter);
2830 if (err) {
204a6e65
SH		 2831 netdev_err(netdev,
2832 "failed to re-activate, error %d. "
2833 "Closing it\n", err);
d1a890fa
SB		 2834 goto out;
2835 }
2836 }
2837
2838out:
2839 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
2840 if (err)
2841 vmxnet3_force_close(adapter);
2842
2843 return err;
2844}
2845
2846
2847static void
2848vmxnet3_declare_features(struct vmxnet3_adapter *adapter, bool dma64)
2849{
2850 struct net_device *netdev = adapter->netdev;
2851
a0d2730c 2852 netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM |
f646968f
PM		 2853 NETIF_F_HW_CSUM | NETIF_F_HW_VLAN_CTAG_TX |
2854 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_TSO | NETIF_F_TSO6 |
72e85c45 2855 NETIF_F_LRO;
a0d2730c 2856 if (dma64)
ebbf9295 2857 netdev->hw_features |= NETIF_F_HIGHDMA;
72e85c45 2858 netdev->vlan_features = netdev->hw_features &
f646968f
PM		 2859 ~(NETIF_F_HW_VLAN_CTAG_TX |
2860 NETIF_F_HW_VLAN_CTAG_RX);
2861 netdev->features = netdev->hw_features | NETIF_F_HW_VLAN_CTAG_FILTER;
d1a890fa
SB		 2862}
2863
2864
2865static void
2866vmxnet3_read_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac)
2867{
2868 u32 tmp;
2869
2870 tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACL);
2871 *(u32 *)mac = tmp;
2872
2873 tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACH);
2874 mac[4] = tmp & 0xff;
2875 mac[5] = (tmp >> 8) & 0xff;
2876}
2877
09c5088e
SB		 2878#ifdef CONFIG_PCI_MSI
2879
2880/*
2881 * Enable MSIx vectors.
2882 * Returns :
25985edc 2883 * VMXNET3_LINUX_MIN_MSIX_VECT when only minimum number of vectors required
b60b869d
AG		 2884 * were enabled.
2885 * number of vectors which were enabled otherwise (this number is greater
09c5088e
SB		 2886 * than VMXNET3_LINUX_MIN_MSIX_VECT)
2887 */
2888
2889static int
b60b869d 2890vmxnet3_acquire_msix_vectors(struct vmxnet3_adapter *adapter, int nvec)
09c5088e 2891{
c0a1be38
AG		 2892 int ret = pci_enable_msix_range(adapter->pdev,
2893 adapter->intr.msix_entries, nvec, nvec);
09c5088e 2894
c0a1be38
AG		 2895 if (ret == -ENOSPC && nvec > VMXNET3_LINUX_MIN_MSIX_VECT) {
2896 dev_err(&adapter->netdev->dev,
2897 "Failed to enable %d MSI-X, trying %d\n",
2898 nvec, VMXNET3_LINUX_MIN_MSIX_VECT);
2899
2900 ret = pci_enable_msix_range(adapter->pdev,
2901 adapter->intr.msix_entries,
2902 VMXNET3_LINUX_MIN_MSIX_VECT,
2903 VMXNET3_LINUX_MIN_MSIX_VECT);
2904 }
2905
2906 if (ret < 0) {
2907 dev_err(&adapter->netdev->dev,
2908 "Failed to enable MSI-X, error: %d\n", ret);
2909 }
2910
2911 return ret;
09c5088e
SB		 2912}
2913
2914
2915#endif /* CONFIG_PCI_MSI */
d1a890fa
SB		 2916
2917static void
2918vmxnet3_alloc_intr_resources(struct vmxnet3_adapter *adapter)
2919{
2920 u32 cfg;
e328d410 2921 unsigned long flags;
d1a890fa
SB		 2922
2923 /* intr settings */
e328d410 2924 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa
SB		 2925 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2926 VMXNET3_CMD_GET_CONF_INTR);
2927 cfg = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
e328d410 2928 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
d1a890fa
SB		 2929 adapter->intr.type = cfg & 0x3;
2930 adapter->intr.mask_mode = (cfg >> 2) & 0x3;
2931
2932 if (adapter->intr.type == VMXNET3_IT_AUTO) {
0bdc0d70
SB		 2933 adapter->intr.type = VMXNET3_IT_MSIX;
2934 }
d1a890fa 2935
8f7e524c 2936#ifdef CONFIG_PCI_MSI
0bdc0d70 2937 if (adapter->intr.type == VMXNET3_IT_MSIX) {
b60b869d
AG		 2938 int i, nvec;
2939
2940 nvec = adapter->share_intr == VMXNET3_INTR_TXSHARE ?
2941 1 : adapter->num_tx_queues;
2942 nvec += adapter->share_intr == VMXNET3_INTR_BUDDYSHARE ?
2943 0 : adapter->num_rx_queues;
2944 nvec += 1; /* for link event */
2945 nvec = nvec > VMXNET3_LINUX_MIN_MSIX_VECT ?
2946 nvec : VMXNET3_LINUX_MIN_MSIX_VECT;
2947
2948 for (i = 0; i < nvec; i++)
2949 adapter->intr.msix_entries[i].entry = i;
2950
2951 nvec = vmxnet3_acquire_msix_vectors(adapter, nvec);
2952 if (nvec < 0)
2953 goto msix_err;
2954
09c5088e
SB		 2955 /* If we cannot allocate one MSIx vector per queue
2956 * then limit the number of rx queues to 1
2957 */
b60b869d 2958 if (nvec == VMXNET3_LINUX_MIN_MSIX_VECT) {
09c5088e 2959 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE
7e96fbf2 2960 || adapter->num_rx_queues != 1) {
09c5088e 2961 adapter->share_intr = VMXNET3_INTR_TXSHARE;
204a6e65
SH		 2962 netdev_err(adapter->netdev,
2963 "Number of rx queues : 1\n");
09c5088e 2964 adapter->num_rx_queues = 1;
09c5088e 2965 }
d1a890fa 2966 }
09c5088e 2967
b60b869d
AG		 2968 adapter->intr.num_intrs = nvec;
2969 return;
2970
2971msix_err:
09c5088e 2972 /* If we cannot allocate MSIx vectors use only one rx queue */
4bad25fa
SH		 2973 dev_info(&adapter->pdev->dev,
2974 "Failed to enable MSI-X, error %d. "
b60b869d 2975 "Limiting #rx queues to 1, try MSI.\n", nvec);
09c5088e 2976
0bdc0d70
SB		 2977 adapter->intr.type = VMXNET3_IT_MSI;
2978 }
d1a890fa 2979
0bdc0d70 2980 if (adapter->intr.type == VMXNET3_IT_MSI) {
b60b869d 2981 if (!pci_enable_msi(adapter->pdev)) {
09c5088e 2982 adapter->num_rx_queues = 1;
d1a890fa 2983 adapter->intr.num_intrs = 1;
d1a890fa
SB		 2984 return;
2985 }
2986 }
0bdc0d70 2987#endif /* CONFIG_PCI_MSI */
d1a890fa 2988
09c5088e 2989 adapter->num_rx_queues = 1;
204a6e65
SH		 2990 dev_info(&adapter->netdev->dev,
2991 "Using INTx interrupt, #Rx queues: 1.\n");
d1a890fa
SB		 2992 adapter->intr.type = VMXNET3_IT_INTX;
2993
2994 /* INT-X related setting */
2995 adapter->intr.num_intrs = 1;
2996}
2997
2998
2999static void
3000vmxnet3_free_intr_resources(struct vmxnet3_adapter *adapter)
3001{
3002 if (adapter->intr.type == VMXNET3_IT_MSIX)
3003 pci_disable_msix(adapter->pdev);
3004 else if (adapter->intr.type == VMXNET3_IT_MSI)
3005 pci_disable_msi(adapter->pdev);
3006 else
3007 BUG_ON(adapter->intr.type != VMXNET3_IT_INTX);
3008}
3009
3010
3011static void
3012vmxnet3_tx_timeout(struct net_device *netdev)
3013{
3014 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3015 adapter->tx_timeout_count++;
3016
204a6e65 3017 netdev_err(adapter->netdev, "tx hang\n");
d1a890fa 3018 schedule_work(&adapter->work);
09c5088e 3019 netif_wake_queue(adapter->netdev);
d1a890fa
SB		 3020}
3021
3022
3023static void
3024vmxnet3_reset_work(struct work_struct *data)
3025{
3026 struct vmxnet3_adapter *adapter;
3027
3028 adapter = container_of(data, struct vmxnet3_adapter, work);
3029
3030 /* if another thread is resetting the device, no need to proceed */
3031 if (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
3032 return;
3033
3034 /* if the device is closed, we must leave it alone */
d9a5f210 3035 rtnl_lock();
d1a890fa 3036 if (netif_running(adapter->netdev)) {
204a6e65 3037 netdev_notice(adapter->netdev, "resetting\n");
d1a890fa
SB		 3038 vmxnet3_quiesce_dev(adapter);
3039 vmxnet3_reset_dev(adapter);
3040 vmxnet3_activate_dev(adapter);
3041 } else {
204a6e65 3042 netdev_info(adapter->netdev, "already closed\n");
d1a890fa 3043 }
d9a5f210 3044 rtnl_unlock();
d1a890fa
SB		 3045
3046 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
3047}
3048
3049
3a4751a3 3050static int
d1a890fa
SB		 3051vmxnet3_probe_device(struct pci_dev *pdev,
3052 const struct pci_device_id *id)
3053{
3054 static const struct net_device_ops vmxnet3_netdev_ops = {
3055 .ndo_open = vmxnet3_open,
3056 .ndo_stop = vmxnet3_close,
3057 .ndo_start_xmit = vmxnet3_xmit_frame,
3058 .ndo_set_mac_address = vmxnet3_set_mac_addr,
3059 .ndo_change_mtu = vmxnet3_change_mtu,
a0d2730c 3060 .ndo_set_features = vmxnet3_set_features,
95305f6c 3061 .ndo_get_stats64 = vmxnet3_get_stats64,
d1a890fa 3062 .ndo_tx_timeout = vmxnet3_tx_timeout,
afc4b13d 3063 .ndo_set_rx_mode = vmxnet3_set_mc,
d1a890fa
SB		 3064 .ndo_vlan_rx_add_vid = vmxnet3_vlan_rx_add_vid,
3065 .ndo_vlan_rx_kill_vid = vmxnet3_vlan_rx_kill_vid,
3066#ifdef CONFIG_NET_POLL_CONTROLLER
3067 .ndo_poll_controller = vmxnet3_netpoll,
3068#endif
3069 };
3070 int err;
3071 bool dma64 = false; /* stupid gcc */
3072 u32 ver;
3073 struct net_device *netdev;
3074 struct vmxnet3_adapter *adapter;
3075 u8 mac[ETH_ALEN];
09c5088e
SB		 3076 int size;
3077 int num_tx_queues;
3078 int num_rx_queues;
3079
e154b639
SB		 3080 if (!pci_msi_enabled())
3081 enable_mq = 0;
3082
09c5088e
SB		 3083#ifdef VMXNET3_RSS
3084 if (enable_mq)
3085 num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES,
3086 (int)num_online_cpus());
3087 else
3088#endif
3089 num_rx_queues = 1;
eebb02b1 3090 num_rx_queues = rounddown_pow_of_two(num_rx_queues);
09c5088e
SB		 3091
3092 if (enable_mq)
3093 num_tx_queues = min(VMXNET3_DEVICE_MAX_TX_QUEUES,
3094 (int)num_online_cpus());
3095 else
3096 num_tx_queues = 1;
3097
eebb02b1 3098 num_tx_queues = rounddown_pow_of_two(num_tx_queues);
09c5088e
SB		 3099 netdev = alloc_etherdev_mq(sizeof(struct vmxnet3_adapter),
3100 max(num_tx_queues, num_rx_queues));
204a6e65
SH		 3101 dev_info(&pdev->dev,
3102 "# of Tx queues : %d, # of Rx queues : %d\n",
3103 num_tx_queues, num_rx_queues);
d1a890fa 3104
41de8d4c 3105 if (!netdev)
d1a890fa 3106 return -ENOMEM;
d1a890fa
SB		 3107
3108 pci_set_drvdata(pdev, netdev);
3109 adapter = netdev_priv(netdev);
3110 adapter->netdev = netdev;
3111 adapter->pdev = pdev;
3112
f00e2b0a
NH		 3113 adapter->tx_ring_size = VMXNET3_DEF_TX_RING_SIZE;
3114 adapter->rx_ring_size = VMXNET3_DEF_RX_RING_SIZE;
53831aa1 3115 adapter->rx_ring2_size = VMXNET3_DEF_RX_RING2_SIZE;
f00e2b0a 3116
83d0feff 3117 spin_lock_init(&adapter->cmd_lock);
b0eb57cb
AK		 3118 adapter->adapter_pa = dma_map_single(&adapter->pdev->dev, adapter,
3119 sizeof(struct vmxnet3_adapter),
3120 PCI_DMA_TODEVICE);
5738a09d
AK		 3121 if (dma_mapping_error(&adapter->pdev->dev, adapter->adapter_pa)) {
3122 dev_err(&pdev->dev, "Failed to map dma\n");
3123 err = -EFAULT;
3124 goto err_dma_map;
3125 }
b0eb57cb
AK		 3126 adapter->shared = dma_alloc_coherent(
3127 &adapter->pdev->dev,
3128 sizeof(struct Vmxnet3_DriverShared),
3129 &adapter->shared_pa, GFP_KERNEL);
d1a890fa 3130 if (!adapter->shared) {
204a6e65 3131 dev_err(&pdev->dev, "Failed to allocate memory\n");
d1a890fa
SB		 3132 err = -ENOMEM;
3133 goto err_alloc_shared;
3134 }
3135
09c5088e
SB		 3136 adapter->num_rx_queues = num_rx_queues;
3137 adapter->num_tx_queues = num_tx_queues;
e4fabf2b 3138 adapter->rx_buf_per_pkt = 1;
09c5088e
SB		 3139
3140 size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues;
3141 size += sizeof(struct Vmxnet3_RxQueueDesc) * adapter->num_rx_queues;
b0eb57cb
AK		 3142 adapter->tqd_start = dma_alloc_coherent(&adapter->pdev->dev, size,
3143 &adapter->queue_desc_pa,
3144 GFP_KERNEL);
d1a890fa
SB		 3145
3146 if (!adapter->tqd_start) {
204a6e65 3147 dev_err(&pdev->dev, "Failed to allocate memory\n");
d1a890fa
SB		 3148 err = -ENOMEM;
3149 goto err_alloc_queue_desc;
3150 }
09c5088e 3151 adapter->rqd_start = (struct Vmxnet3_RxQueueDesc *)(adapter->tqd_start +
96800ee7 3152 adapter->num_tx_queues);
d1a890fa 3153
b0eb57cb
AK		 3154 adapter->pm_conf = dma_alloc_coherent(&adapter->pdev->dev,
3155 sizeof(struct Vmxnet3_PMConf),
3156 &adapter->pm_conf_pa,
3157 GFP_KERNEL);
d1a890fa 3158 if (adapter->pm_conf == NULL) {
d1a890fa
SB		 3159 err = -ENOMEM;
3160 goto err_alloc_pm;
3161 }
3162
09c5088e
SB		 3163#ifdef VMXNET3_RSS
3164
b0eb57cb
AK		 3165 adapter->rss_conf = dma_alloc_coherent(&adapter->pdev->dev,
3166 sizeof(struct UPT1_RSSConf),
3167 &adapter->rss_conf_pa,
3168 GFP_KERNEL);
09c5088e 3169 if (adapter->rss_conf == NULL) {
09c5088e
SB		 3170 err = -ENOMEM;
3171 goto err_alloc_rss;
3172 }
3173#endif /* VMXNET3_RSS */
3174
d1a890fa
SB		 3175 err = vmxnet3_alloc_pci_resources(adapter, &dma64);
3176 if (err < 0)
3177 goto err_alloc_pci;
3178
3179 ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_VRRS);
45dac1d6
SB		 3180 if (ver & 2) {
3181 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_VRRS, 2);
3182 adapter->version = 2;
3183 } else if (ver & 1) {
d1a890fa 3184 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_VRRS, 1);
45dac1d6 3185 adapter->version = 1;
d1a890fa 3186 } else {
204a6e65
SH		 3187 dev_err(&pdev->dev,
3188 "Incompatible h/w version (0x%x) for adapter\n", ver);
d1a890fa
SB		 3189 err = -EBUSY;
3190 goto err_ver;
3191 }
45dac1d6 3192 dev_dbg(&pdev->dev, "Using device version %d\n", adapter->version);
d1a890fa
SB		 3193
3194 ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_UVRS);
3195 if (ver & 1) {
3196 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_UVRS, 1);
3197 } else {
204a6e65
SH		 3198 dev_err(&pdev->dev,
3199 "Incompatible upt version (0x%x) for adapter\n", ver);
d1a890fa
SB		 3200 err = -EBUSY;
3201 goto err_ver;
3202 }
3203
e101e7dd 3204 SET_NETDEV_DEV(netdev, &pdev->dev);
d1a890fa
SB		 3205 vmxnet3_declare_features(adapter, dma64);
3206
4db37a78
SH		 3207 if (adapter->num_tx_queues == adapter->num_rx_queues)
3208 adapter->share_intr = VMXNET3_INTR_BUDDYSHARE;
3209 else
09c5088e
SB		 3210 adapter->share_intr = VMXNET3_INTR_DONTSHARE;
3211
d1a890fa
SB		 3212 vmxnet3_alloc_intr_resources(adapter);
3213
09c5088e
SB		 3214#ifdef VMXNET3_RSS
3215 if (adapter->num_rx_queues > 1 &&
3216 adapter->intr.type == VMXNET3_IT_MSIX) {
3217 adapter->rss = true;
7db11f75
SH		 3218 netdev->hw_features |= NETIF_F_RXHASH;
3219 netdev->features |= NETIF_F_RXHASH;
204a6e65 3220 dev_dbg(&pdev->dev, "RSS is enabled.\n");
09c5088e
SB		 3221 } else {
3222 adapter->rss = false;
3223 }
3224#endif
3225
d1a890fa
SB		 3226 vmxnet3_read_mac_addr(adapter, mac);
3227 memcpy(netdev->dev_addr, mac, netdev->addr_len);
3228
3229 netdev->netdev_ops = &vmxnet3_netdev_ops;
d1a890fa 3230 vmxnet3_set_ethtool_ops(netdev);
09c5088e 3231 netdev->watchdog_timeo = 5 * HZ;
d1a890fa
SB		 3232
3233 INIT_WORK(&adapter->work, vmxnet3_reset_work);
e3bc4ffb 3234 set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state);
d1a890fa 3235
09c5088e
SB		 3236 if (adapter->intr.type == VMXNET3_IT_MSIX) {
3237 int i;
3238 for (i = 0; i < adapter->num_rx_queues; i++) {
3239 netif_napi_add(adapter->netdev,
3240 &adapter->rx_queue[i].napi,
3241 vmxnet3_poll_rx_only, 64);
3242 }
3243 } else {
3244 netif_napi_add(adapter->netdev, &adapter->rx_queue[0].napi,
3245 vmxnet3_poll, 64);
3246 }
3247
3248 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
3249 netif_set_real_num_rx_queues(adapter->netdev, adapter->num_rx_queues);
3250
6cdd20c3 3251 netif_carrier_off(netdev);
d1a890fa
SB		 3252 err = register_netdev(netdev);
3253
3254 if (err) {
204a6e65 3255 dev_err(&pdev->dev, "Failed to register adapter\n");
d1a890fa
SB		 3256 goto err_register;
3257 }
3258
4a1745fc 3259 vmxnet3_check_link(adapter, false);
d1a890fa
SB		 3260 return 0;
3261
3262err_register:
3263 vmxnet3_free_intr_resources(adapter);
3264err_ver:
3265 vmxnet3_free_pci_resources(adapter);
3266err_alloc_pci:
09c5088e 3267#ifdef VMXNET3_RSS
b0eb57cb
AK		 3268 dma_free_coherent(&adapter->pdev->dev, sizeof(struct UPT1_RSSConf),
3269 adapter->rss_conf, adapter->rss_conf_pa);
09c5088e
SB		 3270err_alloc_rss:
3271#endif
b0eb57cb
AK		 3272 dma_free_coherent(&adapter->pdev->dev, sizeof(struct Vmxnet3_PMConf),
3273 adapter->pm_conf, adapter->pm_conf_pa);
d1a890fa 3274err_alloc_pm:
b0eb57cb
AK		 3275 dma_free_coherent(&adapter->pdev->dev, size, adapter->tqd_start,
3276 adapter->queue_desc_pa);
d1a890fa 3277err_alloc_queue_desc:
b0eb57cb
AK		 3278 dma_free_coherent(&adapter->pdev->dev,
3279 sizeof(struct Vmxnet3_DriverShared),
3280 adapter->shared, adapter->shared_pa);
d1a890fa 3281err_alloc_shared:
b0eb57cb
AK		 3282 dma_unmap_single(&adapter->pdev->dev, adapter->adapter_pa,
3283 sizeof(struct vmxnet3_adapter), PCI_DMA_TODEVICE);
5738a09d 3284err_dma_map:
d1a890fa
SB		 3285 free_netdev(netdev);
3286 return err;
3287}
3288
3289
3a4751a3 3290static void
d1a890fa
SB		 3291vmxnet3_remove_device(struct pci_dev *pdev)
3292{
3293 struct net_device *netdev = pci_get_drvdata(pdev);
3294 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
09c5088e
SB		 3295 int size = 0;
3296 int num_rx_queues;
3297
3298#ifdef VMXNET3_RSS
3299 if (enable_mq)
3300 num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES,
3301 (int)num_online_cpus());
3302 else
3303#endif
3304 num_rx_queues = 1;
eebb02b1 3305 num_rx_queues = rounddown_pow_of_two(num_rx_queues);
d1a890fa 3306
23f333a2 3307 cancel_work_sync(&adapter->work);
d1a890fa
SB		 3308
3309 unregister_netdev(netdev);
3310
3311 vmxnet3_free_intr_resources(adapter);
3312 vmxnet3_free_pci_resources(adapter);
09c5088e 3313#ifdef VMXNET3_RSS
b0eb57cb
AK		 3314 dma_free_coherent(&adapter->pdev->dev, sizeof(struct UPT1_RSSConf),
3315 adapter->rss_conf, adapter->rss_conf_pa);
09c5088e 3316#endif
b0eb57cb
AK		 3317 dma_free_coherent(&adapter->pdev->dev, sizeof(struct Vmxnet3_PMConf),
3318 adapter->pm_conf, adapter->pm_conf_pa);
09c5088e
SB		 3319
3320 size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues;
3321 size += sizeof(struct Vmxnet3_RxQueueDesc) * num_rx_queues;
b0eb57cb
AK		 3322 dma_free_coherent(&adapter->pdev->dev, size, adapter->tqd_start,
3323 adapter->queue_desc_pa);
3324 dma_free_coherent(&adapter->pdev->dev,
3325 sizeof(struct Vmxnet3_DriverShared),
3326 adapter->shared, adapter->shared_pa);
3327 dma_unmap_single(&adapter->pdev->dev, adapter->adapter_pa,
3328 sizeof(struct vmxnet3_adapter), PCI_DMA_TODEVICE);
d1a890fa
SB		 3329 free_netdev(netdev);
3330}
3331
e9ba47bf
SB		 3332static void vmxnet3_shutdown_device(struct pci_dev *pdev)
3333{
3334 struct net_device *netdev = pci_get_drvdata(pdev);
3335 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3336 unsigned long flags;
3337
3338 /* Reset_work may be in the middle of resetting the device, wait for its
3339 * completion.
3340 */
3341 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
3342 msleep(1);
3343
3344 if (test_and_set_bit(VMXNET3_STATE_BIT_QUIESCED,
3345 &adapter->state)) {
3346 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
3347 return;
3348 }
3349 spin_lock_irqsave(&adapter->cmd_lock, flags);
3350 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3351 VMXNET3_CMD_QUIESCE_DEV);
3352 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
3353 vmxnet3_disable_all_intrs(adapter);
3354
3355 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
3356}
3357
d1a890fa
SB		 3358
3359#ifdef CONFIG_PM
3360
3361static int
3362vmxnet3_suspend(struct device *device)
3363{
3364 struct pci_dev *pdev = to_pci_dev(device);
3365 struct net_device *netdev = pci_get_drvdata(pdev);
3366 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3367 struct Vmxnet3_PMConf *pmConf;
3368 struct ethhdr *ehdr;
3369 struct arphdr *ahdr;
3370 u8 *arpreq;
3371 struct in_device *in_dev;
3372 struct in_ifaddr *ifa;
83d0feff 3373 unsigned long flags;
d1a890fa
SB		 3374 int i = 0;
3375
3376 if (!netif_running(netdev))
3377 return 0;
3378
51956cd6
SB		 3379 for (i = 0; i < adapter->num_rx_queues; i++)
3380 napi_disable(&adapter->rx_queue[i].napi);
3381
d1a890fa
SB		 3382 vmxnet3_disable_all_intrs(adapter);
3383 vmxnet3_free_irqs(adapter);
3384 vmxnet3_free_intr_resources(adapter);
3385
3386 netif_device_detach(netdev);
09c5088e 3387 netif_tx_stop_all_queues(netdev);
d1a890fa
SB		 3388
3389 /* Create wake-up filters. */
3390 pmConf = adapter->pm_conf;
3391 memset(pmConf, 0, sizeof(*pmConf));
3392
3393 if (adapter->wol & WAKE_UCAST) {
3394 pmConf->filters[i].patternSize = ETH_ALEN;
3395 pmConf->filters[i].maskSize = 1;
3396 memcpy(pmConf->filters[i].pattern, netdev->dev_addr, ETH_ALEN);
3397 pmConf->filters[i].mask[0] = 0x3F; /* LSB ETH_ALEN bits */
3398
3843e515 3399 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER;
d1a890fa
SB		 3400 i++;
3401 }
3402
3403 if (adapter->wol & WAKE_ARP) {
3404 in_dev = in_dev_get(netdev);
3405 if (!in_dev)
3406 goto skip_arp;
3407
3408 ifa = (struct in_ifaddr *)in_dev->ifa_list;
3409 if (!ifa)
3410 goto skip_arp;
3411
3412 pmConf->filters[i].patternSize = ETH_HLEN + /* Ethernet header*/
3413 sizeof(struct arphdr) + /* ARP header */
3414 2 * ETH_ALEN + /* 2 Ethernet addresses*/
3415 2 * sizeof(u32); /*2 IPv4 addresses */
3416 pmConf->filters[i].maskSize =
3417 (pmConf->filters[i].patternSize - 1) / 8 + 1;
3418
3419 /* ETH_P_ARP in Ethernet header. */
3420 ehdr = (struct ethhdr *)pmConf->filters[i].pattern;
3421 ehdr->h_proto = htons(ETH_P_ARP);
3422
3423 /* ARPOP_REQUEST in ARP header. */
3424 ahdr = (struct arphdr *)&pmConf->filters[i].pattern[ETH_HLEN];
3425 ahdr->ar_op = htons(ARPOP_REQUEST);
3426 arpreq = (u8 *)(ahdr + 1);
3427
3428 /* The Unicast IPv4 address in 'tip' field. */
3429 arpreq += 2 * ETH_ALEN + sizeof(u32);
3430 *(u32 *)arpreq = ifa->ifa_address;
3431
3432 /* The mask for the relevant bits. */
3433 pmConf->filters[i].mask[0] = 0x00;
3434 pmConf->filters[i].mask[1] = 0x30; /* ETH_P_ARP */
3435 pmConf->filters[i].mask[2] = 0x30; /* ARPOP_REQUEST */
3436 pmConf->filters[i].mask[3] = 0x00;
3437 pmConf->filters[i].mask[4] = 0xC0; /* IPv4 TIP */
3438 pmConf->filters[i].mask[5] = 0x03; /* IPv4 TIP */
3439 in_dev_put(in_dev);
3440
3843e515 3441 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER;
d1a890fa
SB		 3442 i++;
3443 }
3444
3445skip_arp:
3446 if (adapter->wol & WAKE_MAGIC)
3843e515 3447 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_MAGIC;
d1a890fa
SB		 3448
3449 pmConf->numFilters = i;
3450
115924b6
SB		 3451 adapter->shared->devRead.pmConfDesc.confVer = cpu_to_le32(1);
3452 adapter->shared->devRead.pmConfDesc.confLen = cpu_to_le32(sizeof(
3453 *pmConf));
b0eb57cb
AK		 3454 adapter->shared->devRead.pmConfDesc.confPA =
3455 cpu_to_le64(adapter->pm_conf_pa);
d1a890fa 3456
83d0feff 3457 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa
SB		 3458 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3459 VMXNET3_CMD_UPDATE_PMCFG);
83d0feff 3460 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
d1a890fa
SB		 3461
3462 pci_save_state(pdev);
3463 pci_enable_wake(pdev, pci_choose_state(pdev, PMSG_SUSPEND),
3464 adapter->wol);
3465 pci_disable_device(pdev);
3466 pci_set_power_state(pdev, pci_choose_state(pdev, PMSG_SUSPEND));
3467
3468 return 0;
3469}
3470
3471
3472static int
3473vmxnet3_resume(struct device *device)
3474{
5ec82c1e 3475 int err;
83d0feff 3476 unsigned long flags;
d1a890fa
SB		 3477 struct pci_dev *pdev = to_pci_dev(device);
3478 struct net_device *netdev = pci_get_drvdata(pdev);
3479 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
d1a890fa
SB		 3480
3481 if (!netif_running(netdev))
3482 return 0;
3483
d1a890fa
SB		 3484 pci_set_power_state(pdev, PCI_D0);
3485 pci_restore_state(pdev);
3486 err = pci_enable_device_mem(pdev);
3487 if (err != 0)
3488 return err;
3489
3490 pci_enable_wake(pdev, PCI_D0, 0);
3491
5ec82c1e
SK		 3492 vmxnet3_alloc_intr_resources(adapter);
3493
3494 /* During hibernate and suspend, device has to be reinitialized as the
3495 * device state need not be preserved.
3496 */
3497
3498 /* Need not check adapter state as other reset tasks cannot run during
3499 * device resume.
3500 */
83d0feff 3501 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa 3502 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
5ec82c1e 3503 VMXNET3_CMD_QUIESCE_DEV);
83d0feff 3504 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
5ec82c1e
SK		 3505 vmxnet3_tq_cleanup_all(adapter);
3506 vmxnet3_rq_cleanup_all(adapter);
3507
3508 vmxnet3_reset_dev(adapter);
3509 err = vmxnet3_activate_dev(adapter);
3510 if (err != 0) {
3511 netdev_err(netdev,
3512 "failed to re-activate on resume, error: %d", err);
3513 vmxnet3_force_close(adapter);
3514 return err;
3515 }
3516 netif_device_attach(netdev);
d1a890fa
SB		 3517
3518 return 0;
3519}
3520
47145210 3521static const struct dev_pm_ops vmxnet3_pm_ops = {
d1a890fa
SB		 3522 .suspend = vmxnet3_suspend,
3523 .resume = vmxnet3_resume,
5ec82c1e
SK		 3524 .freeze = vmxnet3_suspend,
3525 .restore = vmxnet3_resume,
d1a890fa
SB		 3526};
3527#endif
3528
3529static struct pci_driver vmxnet3_driver = {
3530 .name = vmxnet3_driver_name,
3531 .id_table = vmxnet3_pciid_table,
3532 .probe = vmxnet3_probe_device,
3a4751a3 3533 .remove = vmxnet3_remove_device,
e9ba47bf 3534 .shutdown = vmxnet3_shutdown_device,
d1a890fa
SB		 3535#ifdef CONFIG_PM
3536 .driver.pm = &vmxnet3_pm_ops,
3537#endif
3538};
3539
3540
3541static int __init
3542vmxnet3_init_module(void)
3543{
204a6e65 3544 pr_info("%s - version %s\n", VMXNET3_DRIVER_DESC,
d1a890fa
SB		 3545 VMXNET3_DRIVER_VERSION_REPORT);
3546 return pci_register_driver(&vmxnet3_driver);
3547}
3548
3549module_init(vmxnet3_init_module);
3550
3551
3552static void
3553vmxnet3_exit_module(void)
3554{
3555 pci_unregister_driver(&vmxnet3_driver);
3556}
3557
3558module_exit(vmxnet3_exit_module);
3559
3560MODULE_AUTHOR("VMware, Inc.");
3561MODULE_DESCRIPTION(VMXNET3_DRIVER_DESC);
3562MODULE_LICENSE("GPL v2");
3563MODULE_VERSION(VMXNET3_DRIVER_VERSION_STRING);
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