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[mirror_ubuntu-hirsute-kernel.git] / drivers / net / vmxnet3 / vmxnet3_drv.c
CommitLineData
d1a890fa
SB		 1/*
2 * Linux driver for VMware's vmxnet3 ethernet NIC.
3 *
190af10f 4 * Copyright (C) 2008-2016, VMware, Inc. All Rights Reserved.
d1a890fa
SB		 5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; version 2 of the License and no later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
13 * NON INFRINGEMENT. See the GNU General Public License for more
14 * details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * The full GNU General Public License is included in this distribution in
21 * the file called "COPYING".
22 *
190af10f 23 * Maintained by: pv-drivers@vmware.com
d1a890fa
SB		 24 *
25 */
26
9d9779e7 27#include <linux/module.h>
b038b040
SR		 28#include <net/ip6_checksum.h>
29
d1a890fa
SB		 30#include "vmxnet3_int.h"
31
32char vmxnet3_driver_name[] = "vmxnet3";
33#define VMXNET3_DRIVER_DESC "VMware vmxnet3 virtual NIC driver"
34
d1a890fa
SB		 35/*
36 * PCI Device ID Table
37 * Last entry must be all 0s
38 */
9baa3c34 39static const struct pci_device_id vmxnet3_pciid_table[] = {
d1a890fa
SB		 40 {PCI_VDEVICE(VMWARE, PCI_DEVICE_ID_VMWARE_VMXNET3)},
41 {0}
42};
43
44MODULE_DEVICE_TABLE(pci, vmxnet3_pciid_table);
45
09c5088e 46static int enable_mq = 1;
d1a890fa 47
f9f25026
SB		 48static void
49vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac);
50
d1a890fa
SB		 51/*
52 * Enable/Disable the given intr
53 */
54static void
55vmxnet3_enable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx)
56{
57 VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 0);
58}
59
60
61static void
62vmxnet3_disable_intr(struct vmxnet3_adapter *adapter, unsigned intr_idx)
63{
64 VMXNET3_WRITE_BAR0_REG(adapter, VMXNET3_REG_IMR + intr_idx * 8, 1);
65}
66
67
68/*
69 * Enable/Disable all intrs used by the device
70 */
71static void
72vmxnet3_enable_all_intrs(struct vmxnet3_adapter *adapter)
73{
74 int i;
75
76 for (i = 0; i < adapter->intr.num_intrs; i++)
77 vmxnet3_enable_intr(adapter, i);
6929fe8a
RZ		 78 adapter->shared->devRead.intrConf.intrCtrl &=
79 cpu_to_le32(~VMXNET3_IC_DISABLE_ALL);
d1a890fa
SB		 80}
81
82
83static void
84vmxnet3_disable_all_intrs(struct vmxnet3_adapter *adapter)
85{
86 int i;
87
6929fe8a
RZ		 88 adapter->shared->devRead.intrConf.intrCtrl |=
89 cpu_to_le32(VMXNET3_IC_DISABLE_ALL);
d1a890fa
SB		 90 for (i = 0; i < adapter->intr.num_intrs; i++)
91 vmxnet3_disable_intr(adapter, i);
92}
93
94
95static void
96vmxnet3_ack_events(struct vmxnet3_adapter *adapter, u32 events)
97{
98 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_ECR, events);
99}
100
101
102static bool
103vmxnet3_tq_stopped(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
104{
09c5088e 105 return tq->stopped;
d1a890fa
SB		 106}
107
108
109static void
110vmxnet3_tq_start(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
111{
112 tq->stopped = false;
09c5088e 113 netif_start_subqueue(adapter->netdev, tq - adapter->tx_queue);
d1a890fa
SB		 114}
115
116
117static void
118vmxnet3_tq_wake(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
119{
120 tq->stopped = false;
09c5088e 121 netif_wake_subqueue(adapter->netdev, (tq - adapter->tx_queue));
d1a890fa
SB		 122}
123
124
125static void
126vmxnet3_tq_stop(struct vmxnet3_tx_queue *tq, struct vmxnet3_adapter *adapter)
127{
128 tq->stopped = true;
129 tq->num_stop++;
09c5088e 130 netif_stop_subqueue(adapter->netdev, (tq - adapter->tx_queue));
d1a890fa
SB		 131}
132
133
134/*
135 * Check the link state. This may start or stop the tx queue.
136 */
137static void
4a1745fc 138vmxnet3_check_link(struct vmxnet3_adapter *adapter, bool affectTxQueue)
d1a890fa
SB		 139{
140 u32 ret;
09c5088e 141 int i;
83d0feff 142 unsigned long flags;
d1a890fa 143
83d0feff 144 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa
SB		 145 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_GET_LINK);
146 ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
83d0feff
SB		 147 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
148
d1a890fa
SB		 149 adapter->link_speed = ret >> 16;
150 if (ret & 1) { /* Link is up. */
204a6e65
SH		 151 netdev_info(adapter->netdev, "NIC Link is Up %d Mbps\n",
152 adapter->link_speed);
6cdd20c3 153 netif_carrier_on(adapter->netdev);
d1a890fa 154
09c5088e
SB		 155 if (affectTxQueue) {
156 for (i = 0; i < adapter->num_tx_queues; i++)
157 vmxnet3_tq_start(&adapter->tx_queue[i],
158 adapter);
159 }
d1a890fa 160 } else {
204a6e65 161 netdev_info(adapter->netdev, "NIC Link is Down\n");
6cdd20c3 162 netif_carrier_off(adapter->netdev);
d1a890fa 163
09c5088e
SB		 164 if (affectTxQueue) {
165 for (i = 0; i < adapter->num_tx_queues; i++)
166 vmxnet3_tq_stop(&adapter->tx_queue[i], adapter);
167 }
d1a890fa
SB		 168 }
169}
170
d1a890fa
SB		 171static void
172vmxnet3_process_events(struct vmxnet3_adapter *adapter)
173{
09c5088e 174 int i;
e328d410 175 unsigned long flags;
115924b6 176 u32 events = le32_to_cpu(adapter->shared->ecr);
d1a890fa
SB		 177 if (!events)
178 return;
179
180 vmxnet3_ack_events(adapter, events);
181
182 /* Check if link state has changed */
183 if (events & VMXNET3_ECR_LINK)
4a1745fc 184 vmxnet3_check_link(adapter, true);
d1a890fa
SB		 185
186 /* Check if there is an error on xmit/recv queues */
187 if (events & (VMXNET3_ECR_TQERR | VMXNET3_ECR_RQERR)) {
e328d410 188 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa
SB		 189 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
190 VMXNET3_CMD_GET_QUEUE_STATUS);
e328d410 191 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
d1a890fa 192
09c5088e
SB		 193 for (i = 0; i < adapter->num_tx_queues; i++)
194 if (adapter->tqd_start[i].status.stopped)
195 dev_err(&adapter->netdev->dev,
196 "%s: tq[%d] error 0x%x\n",
197 adapter->netdev->name, i, le32_to_cpu(
198 adapter->tqd_start[i].status.error));
199 for (i = 0; i < adapter->num_rx_queues; i++)
200 if (adapter->rqd_start[i].status.stopped)
201 dev_err(&adapter->netdev->dev,
202 "%s: rq[%d] error 0x%x\n",
203 adapter->netdev->name, i,
204 adapter->rqd_start[i].status.error);
d1a890fa
SB		 205
206 schedule_work(&adapter->work);
207 }
208}
209
115924b6
SB		 210#ifdef __BIG_ENDIAN_BITFIELD
211/*
212 * The device expects the bitfields in shared structures to be written in
213 * little endian. When CPU is big endian, the following routines are used to
214 * correctly read and write into ABI.
215 * The general technique used here is : double word bitfields are defined in
216 * opposite order for big endian architecture. Then before reading them in
217 * driver the complete double word is translated using le32_to_cpu. Similarly
218 * After the driver writes into bitfields, cpu_to_le32 is used to translate the
219 * double words into required format.
220 * In order to avoid touching bits in shared structure more than once, temporary
221 * descriptors are used. These are passed as srcDesc to following functions.
222 */
223static void vmxnet3_RxDescToCPU(const struct Vmxnet3_RxDesc *srcDesc,
224 struct Vmxnet3_RxDesc *dstDesc)
225{
226 u32 *src = (u32 *)srcDesc + 2;
227 u32 *dst = (u32 *)dstDesc + 2;
228 dstDesc->addr = le64_to_cpu(srcDesc->addr);
229 *dst = le32_to_cpu(*src);
230 dstDesc->ext1 = le32_to_cpu(srcDesc->ext1);
231}
232
233static void vmxnet3_TxDescToLe(const struct Vmxnet3_TxDesc *srcDesc,
234 struct Vmxnet3_TxDesc *dstDesc)
235{
236 int i;
237 u32 *src = (u32 *)(srcDesc + 1);
238 u32 *dst = (u32 *)(dstDesc + 1);
239
240 /* Working backwards so that the gen bit is set at the end. */
241 for (i = 2; i > 0; i--) {
242 src--;
243 dst--;
244 *dst = cpu_to_le32(*src);
245 }
246}
247
248
249static void vmxnet3_RxCompToCPU(const struct Vmxnet3_RxCompDesc *srcDesc,
250 struct Vmxnet3_RxCompDesc *dstDesc)
251{
252 int i = 0;
253 u32 *src = (u32 *)srcDesc;
254 u32 *dst = (u32 *)dstDesc;
255 for (i = 0; i < sizeof(struct Vmxnet3_RxCompDesc) / sizeof(u32); i++) {
256 *dst = le32_to_cpu(*src);
257 src++;
258 dst++;
259 }
260}
261
262
263/* Used to read bitfield values from double words. */
264static u32 get_bitfield32(const __le32 *bitfield, u32 pos, u32 size)
265{
266 u32 temp = le32_to_cpu(*bitfield);
267 u32 mask = ((1 << size) - 1) << pos;
268 temp &= mask;
269 temp >>= pos;
270 return temp;
271}
272
273
274
275#endif /* __BIG_ENDIAN_BITFIELD */
276
277#ifdef __BIG_ENDIAN_BITFIELD
278
279# define VMXNET3_TXDESC_GET_GEN(txdesc) get_bitfield32(((const __le32 *) \
280 txdesc) + VMXNET3_TXD_GEN_DWORD_SHIFT, \
281 VMXNET3_TXD_GEN_SHIFT, VMXNET3_TXD_GEN_SIZE)
282# define VMXNET3_TXDESC_GET_EOP(txdesc) get_bitfield32(((const __le32 *) \
283 txdesc) + VMXNET3_TXD_EOP_DWORD_SHIFT, \
284 VMXNET3_TXD_EOP_SHIFT, VMXNET3_TXD_EOP_SIZE)
285# define VMXNET3_TCD_GET_GEN(tcd) get_bitfield32(((const __le32 *)tcd) + \
286 VMXNET3_TCD_GEN_DWORD_SHIFT, VMXNET3_TCD_GEN_SHIFT, \
287 VMXNET3_TCD_GEN_SIZE)
288# define VMXNET3_TCD_GET_TXIDX(tcd) get_bitfield32((const __le32 *)tcd, \
289 VMXNET3_TCD_TXIDX_SHIFT, VMXNET3_TCD_TXIDX_SIZE)
290# define vmxnet3_getRxComp(dstrcd, rcd, tmp) do { \
291 (dstrcd) = (tmp); \
292 vmxnet3_RxCompToCPU((rcd), (tmp)); \
293 } while (0)
294# define vmxnet3_getRxDesc(dstrxd, rxd, tmp) do { \
295 (dstrxd) = (tmp); \
296 vmxnet3_RxDescToCPU((rxd), (tmp)); \
297 } while (0)
298
299#else
300
301# define VMXNET3_TXDESC_GET_GEN(txdesc) ((txdesc)->gen)
302# define VMXNET3_TXDESC_GET_EOP(txdesc) ((txdesc)->eop)
303# define VMXNET3_TCD_GET_GEN(tcd) ((tcd)->gen)
304# define VMXNET3_TCD_GET_TXIDX(tcd) ((tcd)->txdIdx)
305# define vmxnet3_getRxComp(dstrcd, rcd, tmp) (dstrcd) = (rcd)
306# define vmxnet3_getRxDesc(dstrxd, rxd, tmp) (dstrxd) = (rxd)
307
308#endif /* __BIG_ENDIAN_BITFIELD */
309
d1a890fa
SB		 310
311static void
312vmxnet3_unmap_tx_buf(struct vmxnet3_tx_buf_info *tbi,
313 struct pci_dev *pdev)
314{
315 if (tbi->map_type == VMXNET3_MAP_SINGLE)
b0eb57cb 316 dma_unmap_single(&pdev->dev, tbi->dma_addr, tbi->len,
d1a890fa
SB		 317 PCI_DMA_TODEVICE);
318 else if (tbi->map_type == VMXNET3_MAP_PAGE)
b0eb57cb 319 dma_unmap_page(&pdev->dev, tbi->dma_addr, tbi->len,
d1a890fa
SB		 320 PCI_DMA_TODEVICE);
321 else
322 BUG_ON(tbi->map_type != VMXNET3_MAP_NONE);
323
324 tbi->map_type = VMXNET3_MAP_NONE; /* to help debugging */
325}
326
327
328static int
329vmxnet3_unmap_pkt(u32 eop_idx, struct vmxnet3_tx_queue *tq,
330 struct pci_dev *pdev, struct vmxnet3_adapter *adapter)
331{
332 struct sk_buff *skb;
333 int entries = 0;
334
335 /* no out of order completion */
336 BUG_ON(tq->buf_info[eop_idx].sop_idx != tq->tx_ring.next2comp);
115924b6 337 BUG_ON(VMXNET3_TXDESC_GET_EOP(&(tq->tx_ring.base[eop_idx].txd)) != 1);
d1a890fa
SB		 338
339 skb = tq->buf_info[eop_idx].skb;
340 BUG_ON(skb == NULL);
341 tq->buf_info[eop_idx].skb = NULL;
342
343 VMXNET3_INC_RING_IDX_ONLY(eop_idx, tq->tx_ring.size);
344
345 while (tq->tx_ring.next2comp != eop_idx) {
346 vmxnet3_unmap_tx_buf(tq->buf_info + tq->tx_ring.next2comp,
347 pdev);
348
349 /* update next2comp w/o tx_lock. Since we are marking more,
350 * instead of less, tx ring entries avail, the worst case is
351 * that the tx routine incorrectly re-queues a pkt due to
352 * insufficient tx ring entries.
353 */
354 vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring);
355 entries++;
356 }
357
358 dev_kfree_skb_any(skb);
359 return entries;
360}
361
362
363static int
364vmxnet3_tq_tx_complete(struct vmxnet3_tx_queue *tq,
365 struct vmxnet3_adapter *adapter)
366{
367 int completed = 0;
368 union Vmxnet3_GenericDesc *gdesc;
369
370 gdesc = tq->comp_ring.base + tq->comp_ring.next2proc;
115924b6
SB		 371 while (VMXNET3_TCD_GET_GEN(&gdesc->tcd) == tq->comp_ring.gen) {
372 completed += vmxnet3_unmap_pkt(VMXNET3_TCD_GET_TXIDX(
373 &gdesc->tcd), tq, adapter->pdev,
374 adapter);
d1a890fa
SB		 375
376 vmxnet3_comp_ring_adv_next2proc(&tq->comp_ring);
377 gdesc = tq->comp_ring.base + tq->comp_ring.next2proc;
378 }
379
380 if (completed) {
381 spin_lock(&tq->tx_lock);
382 if (unlikely(vmxnet3_tq_stopped(tq, adapter) &&
383 vmxnet3_cmd_ring_desc_avail(&tq->tx_ring) >
384 VMXNET3_WAKE_QUEUE_THRESHOLD(tq) &&
385 netif_carrier_ok(adapter->netdev))) {
386 vmxnet3_tq_wake(tq, adapter);
387 }
388 spin_unlock(&tq->tx_lock);
389 }
390 return completed;
391}
392
393
394static void
395vmxnet3_tq_cleanup(struct vmxnet3_tx_queue *tq,
396 struct vmxnet3_adapter *adapter)
397{
398 int i;
399
400 while (tq->tx_ring.next2comp != tq->tx_ring.next2fill) {
401 struct vmxnet3_tx_buf_info *tbi;
d1a890fa
SB		 402
403 tbi = tq->buf_info + tq->tx_ring.next2comp;
d1a890fa
SB		 404
405 vmxnet3_unmap_tx_buf(tbi, adapter->pdev);
406 if (tbi->skb) {
407 dev_kfree_skb_any(tbi->skb);
408 tbi->skb = NULL;
409 }
410 vmxnet3_cmd_ring_adv_next2comp(&tq->tx_ring);
411 }
412
413 /* sanity check, verify all buffers are indeed unmapped and freed */
414 for (i = 0; i < tq->tx_ring.size; i++) {
415 BUG_ON(tq->buf_info[i].skb != NULL ||
416 tq->buf_info[i].map_type != VMXNET3_MAP_NONE);
417 }
418
419 tq->tx_ring.gen = VMXNET3_INIT_GEN;
420 tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0;
421
422 tq->comp_ring.gen = VMXNET3_INIT_GEN;
423 tq->comp_ring.next2proc = 0;
424}
425
426
09c5088e 427static void
d1a890fa
SB		 428vmxnet3_tq_destroy(struct vmxnet3_tx_queue *tq,
429 struct vmxnet3_adapter *adapter)
430{
431 if (tq->tx_ring.base) {
b0eb57cb
AK		 432 dma_free_coherent(&adapter->pdev->dev, tq->tx_ring.size *
433 sizeof(struct Vmxnet3_TxDesc),
434 tq->tx_ring.base, tq->tx_ring.basePA);
d1a890fa
SB		 435 tq->tx_ring.base = NULL;
436 }
437 if (tq->data_ring.base) {
3c8b3efc
SK		 438 dma_free_coherent(&adapter->pdev->dev,
439 tq->data_ring.size * tq->txdata_desc_size,
b0eb57cb 440 tq->data_ring.base, tq->data_ring.basePA);
d1a890fa
SB		 441 tq->data_ring.base = NULL;
442 }
443 if (tq->comp_ring.base) {
b0eb57cb
AK		 444 dma_free_coherent(&adapter->pdev->dev, tq->comp_ring.size *
445 sizeof(struct Vmxnet3_TxCompDesc),
446 tq->comp_ring.base, tq->comp_ring.basePA);
d1a890fa
SB		 447 tq->comp_ring.base = NULL;
448 }
b0eb57cb
AK		 449 if (tq->buf_info) {
450 dma_free_coherent(&adapter->pdev->dev,
451 tq->tx_ring.size * sizeof(tq->buf_info[0]),
452 tq->buf_info, tq->buf_info_pa);
453 tq->buf_info = NULL;
454 }
d1a890fa
SB		 455}
456
457
09c5088e
SB		 458/* Destroy all tx queues */
459void
460vmxnet3_tq_destroy_all(struct vmxnet3_adapter *adapter)
461{
462 int i;
463
464 for (i = 0; i < adapter->num_tx_queues; i++)
465 vmxnet3_tq_destroy(&adapter->tx_queue[i], adapter);
466}
467
468
d1a890fa
SB		 469static void
470vmxnet3_tq_init(struct vmxnet3_tx_queue *tq,
471 struct vmxnet3_adapter *adapter)
472{
473 int i;
474
475 /* reset the tx ring contents to 0 and reset the tx ring states */
476 memset(tq->tx_ring.base, 0, tq->tx_ring.size *
477 sizeof(struct Vmxnet3_TxDesc));
478 tq->tx_ring.next2fill = tq->tx_ring.next2comp = 0;
479 tq->tx_ring.gen = VMXNET3_INIT_GEN;
480
3c8b3efc
SK		 481 memset(tq->data_ring.base, 0,
482 tq->data_ring.size * tq->txdata_desc_size);
d1a890fa
SB		 483
484 /* reset the tx comp ring contents to 0 and reset comp ring states */
485 memset(tq->comp_ring.base, 0, tq->comp_ring.size *
486 sizeof(struct Vmxnet3_TxCompDesc));
487 tq->comp_ring.next2proc = 0;
488 tq->comp_ring.gen = VMXNET3_INIT_GEN;
489
490 /* reset the bookkeeping data */
491 memset(tq->buf_info, 0, sizeof(tq->buf_info[0]) * tq->tx_ring.size);
492 for (i = 0; i < tq->tx_ring.size; i++)
493 tq->buf_info[i].map_type = VMXNET3_MAP_NONE;
494
495 /* stats are not reset */
496}
497
498
499static int
500vmxnet3_tq_create(struct vmxnet3_tx_queue *tq,
501 struct vmxnet3_adapter *adapter)
502{
b0eb57cb
AK		 503 size_t sz;
504
d1a890fa
SB		 505 BUG_ON(tq->tx_ring.base || tq->data_ring.base ||
506 tq->comp_ring.base || tq->buf_info);
507
b0eb57cb
AK		 508 tq->tx_ring.base = dma_alloc_coherent(&adapter->pdev->dev,
509 tq->tx_ring.size * sizeof(struct Vmxnet3_TxDesc),
510 &tq->tx_ring.basePA, GFP_KERNEL);
d1a890fa 511 if (!tq->tx_ring.base) {
204a6e65 512 netdev_err(adapter->netdev, "failed to allocate tx ring\n");
d1a890fa
SB		 513 goto err;
514 }
515
b0eb57cb 516 tq->data_ring.base = dma_alloc_coherent(&adapter->pdev->dev,
3c8b3efc 517 tq->data_ring.size * tq->txdata_desc_size,
b0eb57cb 518 &tq->data_ring.basePA, GFP_KERNEL);
d1a890fa 519 if (!tq->data_ring.base) {
3c8b3efc 520 netdev_err(adapter->netdev, "failed to allocate tx data ring\n");
d1a890fa
SB		 521 goto err;
522 }
523
b0eb57cb
AK		 524 tq->comp_ring.base = dma_alloc_coherent(&adapter->pdev->dev,
525 tq->comp_ring.size * sizeof(struct Vmxnet3_TxCompDesc),
526 &tq->comp_ring.basePA, GFP_KERNEL);
d1a890fa 527 if (!tq->comp_ring.base) {
204a6e65 528 netdev_err(adapter->netdev, "failed to allocate tx comp ring\n");
d1a890fa
SB		 529 goto err;
530 }
531
b0eb57cb
AK		 532 sz = tq->tx_ring.size * sizeof(tq->buf_info[0]);
533 tq->buf_info = dma_zalloc_coherent(&adapter->pdev->dev, sz,
534 &tq->buf_info_pa, GFP_KERNEL);
e404decb 535 if (!tq->buf_info)
d1a890fa 536 goto err;
d1a890fa
SB		 537
538 return 0;
539
540err:
541 vmxnet3_tq_destroy(tq, adapter);
542 return -ENOMEM;
543}
544
09c5088e
SB		 545static void
546vmxnet3_tq_cleanup_all(struct vmxnet3_adapter *adapter)
547{
548 int i;
549
550 for (i = 0; i < adapter->num_tx_queues; i++)
551 vmxnet3_tq_cleanup(&adapter->tx_queue[i], adapter);
552}
d1a890fa
SB		 553
554/*
555 * starting from ring->next2fill, allocate rx buffers for the given ring
556 * of the rx queue and update the rx desc. stop after @num_to_alloc buffers
557 * are allocated or allocation fails
558 */
559
560static int
561vmxnet3_rq_alloc_rx_buf(struct vmxnet3_rx_queue *rq, u32 ring_idx,
562 int num_to_alloc, struct vmxnet3_adapter *adapter)
563{
564 int num_allocated = 0;
565 struct vmxnet3_rx_buf_info *rbi_base = rq->buf_info[ring_idx];
566 struct vmxnet3_cmd_ring *ring = &rq->rx_ring[ring_idx];
567 u32 val;
568
5318d809 569 while (num_allocated <= num_to_alloc) {
d1a890fa
SB		 570 struct vmxnet3_rx_buf_info *rbi;
571 union Vmxnet3_GenericDesc *gd;
572
573 rbi = rbi_base + ring->next2fill;
574 gd = ring->base + ring->next2fill;
575
576 if (rbi->buf_type == VMXNET3_RX_BUF_SKB) {
577 if (rbi->skb == NULL) {
0d735f13
SH		 578 rbi->skb = __netdev_alloc_skb_ip_align(adapter->netdev,
579 rbi->len,
580 GFP_KERNEL);
d1a890fa
SB		 581 if (unlikely(rbi->skb == NULL)) {
582 rq->stats.rx_buf_alloc_failure++;
583 break;
584 }
d1a890fa 585
b0eb57cb
AK		 586 rbi->dma_addr = dma_map_single(
587 &adapter->pdev->dev,
d1a890fa
SB		 588 rbi->skb->data, rbi->len,
589 PCI_DMA_FROMDEVICE);
5738a09d
AK		 590 if (dma_mapping_error(&adapter->pdev->dev,
591 rbi->dma_addr)) {
592 dev_kfree_skb_any(rbi->skb);
593 rq->stats.rx_buf_alloc_failure++;
594 break;
595 }
d1a890fa
SB		 596 } else {
597 /* rx buffer skipped by the device */
598 }
599 val = VMXNET3_RXD_BTYPE_HEAD << VMXNET3_RXD_BTYPE_SHIFT;
600 } else {
601 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE ||
602 rbi->len != PAGE_SIZE);
603
604 if (rbi->page == NULL) {
605 rbi->page = alloc_page(GFP_ATOMIC);
606 if (unlikely(rbi->page == NULL)) {
607 rq->stats.rx_buf_alloc_failure++;
608 break;
609 }
b0eb57cb
AK		 610 rbi->dma_addr = dma_map_page(
611 &adapter->pdev->dev,
d1a890fa
SB		 612 rbi->page, 0, PAGE_SIZE,
613 PCI_DMA_FROMDEVICE);
5738a09d
AK		 614 if (dma_mapping_error(&adapter->pdev->dev,
615 rbi->dma_addr)) {
616 put_page(rbi->page);
617 rq->stats.rx_buf_alloc_failure++;
618 break;
619 }
d1a890fa
SB		 620 } else {
621 /* rx buffers skipped by the device */
622 }
623 val = VMXNET3_RXD_BTYPE_BODY << VMXNET3_RXD_BTYPE_SHIFT;
624 }
625
115924b6 626 gd->rxd.addr = cpu_to_le64(rbi->dma_addr);
5318d809 627 gd->dword[2] = cpu_to_le32((!ring->gen << VMXNET3_RXD_GEN_SHIFT)
115924b6 628 | val | rbi->len);
d1a890fa 629
5318d809
SB		 630 /* Fill the last buffer but dont mark it ready, or else the
631 * device will think that the queue is full */
632 if (num_allocated == num_to_alloc)
633 break;
634
635 gd->dword[2] |= cpu_to_le32(ring->gen << VMXNET3_RXD_GEN_SHIFT);
d1a890fa
SB		 636 num_allocated++;
637 vmxnet3_cmd_ring_adv_next2fill(ring);
638 }
d1a890fa 639
fdcd79b9 640 netdev_dbg(adapter->netdev,
69b9a712
SH		 641 "alloc_rx_buf: %d allocated, next2fill %u, next2comp %u\n",
642 num_allocated, ring->next2fill, ring->next2comp);
d1a890fa
SB		 643
644 /* so that the device can distinguish a full ring and an empty ring */
645 BUG_ON(num_allocated != 0 && ring->next2fill == ring->next2comp);
646
647 return num_allocated;
648}
649
650
651static void
652vmxnet3_append_frag(struct sk_buff *skb, struct Vmxnet3_RxCompDesc *rcd,
653 struct vmxnet3_rx_buf_info *rbi)
654{
655 struct skb_frag_struct *frag = skb_shinfo(skb)->frags +
656 skb_shinfo(skb)->nr_frags;
657
658 BUG_ON(skb_shinfo(skb)->nr_frags >= MAX_SKB_FRAGS);
659
0e0634d2 660 __skb_frag_set_page(frag, rbi->page);
d1a890fa 661 frag->page_offset = 0;
9e903e08
ED		 662 skb_frag_size_set(frag, rcd->len);
663 skb->data_len += rcd->len;
5e6c355c 664 skb->truesize += PAGE_SIZE;
d1a890fa
SB		 665 skb_shinfo(skb)->nr_frags++;
666}
667
668
5738a09d 669static int
d1a890fa
SB		 670vmxnet3_map_pkt(struct sk_buff *skb, struct vmxnet3_tx_ctx *ctx,
671 struct vmxnet3_tx_queue *tq, struct pci_dev *pdev,
672 struct vmxnet3_adapter *adapter)
673{
674 u32 dw2, len;
675 unsigned long buf_offset;
676 int i;
677 union Vmxnet3_GenericDesc *gdesc;
678 struct vmxnet3_tx_buf_info *tbi = NULL;
679
680 BUG_ON(ctx->copy_size > skb_headlen(skb));
681
682 /* use the previous gen bit for the SOP desc */
683 dw2 = (tq->tx_ring.gen ^ 0x1) << VMXNET3_TXD_GEN_SHIFT;
684
685 ctx->sop_txd = tq->tx_ring.base + tq->tx_ring.next2fill;
686 gdesc = ctx->sop_txd; /* both loops below can be skipped */
687
688 /* no need to map the buffer if headers are copied */
689 if (ctx->copy_size) {
115924b6 690 ctx->sop_txd->txd.addr = cpu_to_le64(tq->data_ring.basePA +
d1a890fa 691 tq->tx_ring.next2fill *
3c8b3efc 692 tq->txdata_desc_size);
115924b6 693 ctx->sop_txd->dword[2] = cpu_to_le32(dw2 | ctx->copy_size);
d1a890fa
SB		 694 ctx->sop_txd->dword[3] = 0;
695
696 tbi = tq->buf_info + tq->tx_ring.next2fill;
697 tbi->map_type = VMXNET3_MAP_NONE;
698
fdcd79b9 699 netdev_dbg(adapter->netdev,
f6965582 700 "txd[%u]: 0x%Lx 0x%x 0x%x\n",
115924b6
SB		 701 tq->tx_ring.next2fill,
702 le64_to_cpu(ctx->sop_txd->txd.addr),
d1a890fa
SB		 703 ctx->sop_txd->dword[2], ctx->sop_txd->dword[3]);
704 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
705
706 /* use the right gen for non-SOP desc */
707 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
708 }
709
710 /* linear part can use multiple tx desc if it's big */
711 len = skb_headlen(skb) - ctx->copy_size;
712 buf_offset = ctx->copy_size;
713 while (len) {
714 u32 buf_size;
715
1f4b1612
BD		 716 if (len < VMXNET3_MAX_TX_BUF_SIZE) {
717 buf_size = len;
718 dw2 |= len;
719 } else {
720 buf_size = VMXNET3_MAX_TX_BUF_SIZE;
721 /* spec says that for TxDesc.len, 0 == 2^14 */
722 }
d1a890fa
SB		 723
724 tbi = tq->buf_info + tq->tx_ring.next2fill;
725 tbi->map_type = VMXNET3_MAP_SINGLE;
b0eb57cb 726 tbi->dma_addr = dma_map_single(&adapter->pdev->dev,
d1a890fa
SB		 727 skb->data + buf_offset, buf_size,
728 PCI_DMA_TODEVICE);
5738a09d
AK		 729 if (dma_mapping_error(&adapter->pdev->dev, tbi->dma_addr))
730 return -EFAULT;
d1a890fa 731
1f4b1612 732 tbi->len = buf_size;
d1a890fa
SB		 733
734 gdesc = tq->tx_ring.base + tq->tx_ring.next2fill;
735 BUG_ON(gdesc->txd.gen == tq->tx_ring.gen);
736
115924b6 737 gdesc->txd.addr = cpu_to_le64(tbi->dma_addr);
1f4b1612 738 gdesc->dword[2] = cpu_to_le32(dw2);
d1a890fa
SB		 739 gdesc->dword[3] = 0;
740
fdcd79b9 741 netdev_dbg(adapter->netdev,
f6965582 742 "txd[%u]: 0x%Lx 0x%x 0x%x\n",
115924b6
SB		 743 tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr),
744 le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]);
d1a890fa
SB		 745 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
746 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
747
748 len -= buf_size;
749 buf_offset += buf_size;
750 }
751
752 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
9e903e08 753 const struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
a4d7e485 754 u32 buf_size;
d1a890fa 755
a4d7e485
ED		 756 buf_offset = 0;
757 len = skb_frag_size(frag);
758 while (len) {
759 tbi = tq->buf_info + tq->tx_ring.next2fill;
760 if (len < VMXNET3_MAX_TX_BUF_SIZE) {
761 buf_size = len;
762 dw2 |= len;
763 } else {
764 buf_size = VMXNET3_MAX_TX_BUF_SIZE;
765 /* spec says that for TxDesc.len, 0 == 2^14 */
766 }
767 tbi->map_type = VMXNET3_MAP_PAGE;
768 tbi->dma_addr = skb_frag_dma_map(&adapter->pdev->dev, frag,
769 buf_offset, buf_size,
770 DMA_TO_DEVICE);
5738a09d
AK		 771 if (dma_mapping_error(&adapter->pdev->dev, tbi->dma_addr))
772 return -EFAULT;
d1a890fa 773
a4d7e485 774 tbi->len = buf_size;
d1a890fa 775
a4d7e485
ED		 776 gdesc = tq->tx_ring.base + tq->tx_ring.next2fill;
777 BUG_ON(gdesc->txd.gen == tq->tx_ring.gen);
d1a890fa 778
a4d7e485
ED		 779 gdesc->txd.addr = cpu_to_le64(tbi->dma_addr);
780 gdesc->dword[2] = cpu_to_le32(dw2);
781 gdesc->dword[3] = 0;
d1a890fa 782
fdcd79b9 783 netdev_dbg(adapter->netdev,
8b429468 784 "txd[%u]: 0x%llx %u %u\n",
a4d7e485
ED		 785 tq->tx_ring.next2fill, le64_to_cpu(gdesc->txd.addr),
786 le32_to_cpu(gdesc->dword[2]), gdesc->dword[3]);
787 vmxnet3_cmd_ring_adv_next2fill(&tq->tx_ring);
788 dw2 = tq->tx_ring.gen << VMXNET3_TXD_GEN_SHIFT;
789
790 len -= buf_size;
791 buf_offset += buf_size;
792 }
d1a890fa
SB		 793 }
794
795 ctx->eop_txd = gdesc;
796
797 /* set the last buf_info for the pkt */
798 tbi->skb = skb;
799 tbi->sop_idx = ctx->sop_txd - tq->tx_ring.base;
5738a09d
AK		 800
801 return 0;
d1a890fa
SB		 802}
803
804
09c5088e
SB		 805/* Init all tx queues */
806static void
807vmxnet3_tq_init_all(struct vmxnet3_adapter *adapter)
808{
809 int i;
810
811 for (i = 0; i < adapter->num_tx_queues; i++)
812 vmxnet3_tq_init(&adapter->tx_queue[i], adapter);
813}
814
815
d1a890fa 816/*
cec05562 817 * parse relevant protocol headers:
d1a890fa
SB		 818 * For a tso pkt, relevant headers are L2/3/4 including options
819 * For a pkt requesting csum offloading, they are L2/3 and may include L4
820 * if it's a TCP/UDP pkt
821 *
822 * Returns:
823 * -1: error happens during parsing
824 * 0: protocol headers parsed, but too big to be copied
825 * 1: protocol headers parsed and copied
826 *
827 * Other effects:
828 * 1. related *ctx fields are updated.
829 * 2. ctx->copy_size is # of bytes copied
cec05562 830 * 3. the portion to be copied is guaranteed to be in the linear part
d1a890fa
SB		 831 *
832 */
833static int
cec05562
NH		 834vmxnet3_parse_hdr(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
835 struct vmxnet3_tx_ctx *ctx,
836 struct vmxnet3_adapter *adapter)
d1a890fa 837{
759c9359 838 u8 protocol = 0;
d1a890fa 839
0d0b1672 840 if (ctx->mss) { /* TSO */
d1a890fa 841 ctx->eth_ip_hdr_size = skb_transport_offset(skb);
8bca5d1e 842 ctx->l4_hdr_size = tcp_hdrlen(skb);
d1a890fa
SB		 843 ctx->copy_size = ctx->eth_ip_hdr_size + ctx->l4_hdr_size;
844 } else {
d1a890fa 845 if (skb->ip_summed == CHECKSUM_PARTIAL) {
0d0b1672 846 ctx->eth_ip_hdr_size = skb_checksum_start_offset(skb);
d1a890fa
SB		 847
848 if (ctx->ipv4) {
8bca5d1e
ED		 849 const struct iphdr *iph = ip_hdr(skb);
850
759c9359
SK		 851 protocol = iph->protocol;
852 } else if (ctx->ipv6) {
853 const struct ipv6hdr *ipv6h = ipv6_hdr(skb);
854
855 protocol = ipv6h->nexthdr;
856 }
857
858 switch (protocol) {
859 case IPPROTO_TCP:
860 ctx->l4_hdr_size = tcp_hdrlen(skb);
861 break;
862 case IPPROTO_UDP:
863 ctx->l4_hdr_size = sizeof(struct udphdr);
864 break;
865 default:
d1a890fa 866 ctx->l4_hdr_size = 0;
759c9359 867 break;
d1a890fa 868 }
759c9359 869
b203262d
NH		 870 ctx->copy_size = min(ctx->eth_ip_hdr_size +
871 ctx->l4_hdr_size, skb->len);
d1a890fa
SB		 872 } else {
873 ctx->eth_ip_hdr_size = 0;
874 ctx->l4_hdr_size = 0;
875 /* copy as much as allowed */
3c8b3efc
SK		 876 ctx->copy_size = min_t(unsigned int,
877 tq->txdata_desc_size,
878 skb_headlen(skb));
d1a890fa
SB		 879 }
880
c41fcce9
SB		 881 if (skb->len <= VMXNET3_HDR_COPY_SIZE)
882 ctx->copy_size = skb->len;
883
d1a890fa
SB		 884 /* make sure headers are accessible directly */
885 if (unlikely(!pskb_may_pull(skb, ctx->copy_size)))
886 goto err;
887 }
888
3c8b3efc 889 if (unlikely(ctx->copy_size > tq->txdata_desc_size)) {
d1a890fa
SB		 890 tq->stats.oversized_hdr++;
891 ctx->copy_size = 0;
892 return 0;
893 }
894
cec05562
NH		 895 return 1;
896err:
897 return -1;
898}
899
900/*
901 * copy relevant protocol headers to the transmit ring:
902 * For a tso pkt, relevant headers are L2/3/4 including options
903 * For a pkt requesting csum offloading, they are L2/3 and may include L4
904 * if it's a TCP/UDP pkt
905 *
906 *
907 * Note that this requires that vmxnet3_parse_hdr be called first to set the
908 * appropriate bits in ctx first
909 */
910static void
911vmxnet3_copy_hdr(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
912 struct vmxnet3_tx_ctx *ctx,
913 struct vmxnet3_adapter *adapter)
914{
915 struct Vmxnet3_TxDataDesc *tdd;
916
ff2e7d5d
SK		 917 tdd = (struct Vmxnet3_TxDataDesc *)((u8 *)tq->data_ring.base +
918 tq->tx_ring.next2fill *
919 tq->txdata_desc_size);
d1a890fa
SB		 920
921 memcpy(tdd->data, skb->data, ctx->copy_size);
fdcd79b9 922 netdev_dbg(adapter->netdev,
f6965582 923 "copy %u bytes to dataRing[%u]\n",
d1a890fa 924 ctx->copy_size, tq->tx_ring.next2fill);
d1a890fa
SB		 925}
926
927
928static void
929vmxnet3_prepare_tso(struct sk_buff *skb,
930 struct vmxnet3_tx_ctx *ctx)
931{
8bca5d1e
ED		 932 struct tcphdr *tcph = tcp_hdr(skb);
933
d1a890fa 934 if (ctx->ipv4) {
8bca5d1e
ED		 935 struct iphdr *iph = ip_hdr(skb);
936
d1a890fa
SB		 937 iph->check = 0;
938 tcph->check = ~csum_tcpudp_magic(iph->saddr, iph->daddr, 0,
939 IPPROTO_TCP, 0);
759c9359 940 } else if (ctx->ipv6) {
8bca5d1e
ED		 941 struct ipv6hdr *iph = ipv6_hdr(skb);
942
d1a890fa
SB		 943 tcph->check = ~csum_ipv6_magic(&iph->saddr, &iph->daddr, 0,
944 IPPROTO_TCP, 0);
945 }
946}
947
a4d7e485
ED		 948static int txd_estimate(const struct sk_buff *skb)
949{
950 int count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 1;
951 int i;
952
953 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
954 const struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
955
956 count += VMXNET3_TXD_NEEDED(skb_frag_size(frag));
957 }
958 return count;
959}
d1a890fa
SB		 960
961/*
962 * Transmits a pkt thru a given tq
963 * Returns:
964 * NETDEV_TX_OK: descriptors are setup successfully
25985edc 965 * NETDEV_TX_OK: error occurred, the pkt is dropped
d1a890fa
SB		 966 * NETDEV_TX_BUSY: tx ring is full, queue is stopped
967 *
968 * Side-effects:
969 * 1. tx ring may be changed
970 * 2. tq stats may be updated accordingly
971 * 3. shared->txNumDeferred may be updated
972 */
973
974static int
975vmxnet3_tq_xmit(struct sk_buff *skb, struct vmxnet3_tx_queue *tq,
976 struct vmxnet3_adapter *adapter, struct net_device *netdev)
977{
978 int ret;
979 u32 count;
980 unsigned long flags;
981 struct vmxnet3_tx_ctx ctx;
982 union Vmxnet3_GenericDesc *gdesc;
115924b6
SB		 983#ifdef __BIG_ENDIAN_BITFIELD
984 /* Use temporary descriptor to avoid touching bits multiple times */
985 union Vmxnet3_GenericDesc tempTxDesc;
986#endif
d1a890fa 987
a4d7e485 988 count = txd_estimate(skb);
d1a890fa 989
72e85c45 990 ctx.ipv4 = (vlan_get_protocol(skb) == cpu_to_be16(ETH_P_IP));
759c9359 991 ctx.ipv6 = (vlan_get_protocol(skb) == cpu_to_be16(ETH_P_IPV6));
d1a890fa
SB		 992
993 ctx.mss = skb_shinfo(skb)->gso_size;
994 if (ctx.mss) {
995 if (skb_header_cloned(skb)) {
996 if (unlikely(pskb_expand_head(skb, 0, 0,
997 GFP_ATOMIC) != 0)) {
998 tq->stats.drop_tso++;
999 goto drop_pkt;
1000 }
1001 tq->stats.copy_skb_header++;
1002 }
1003 vmxnet3_prepare_tso(skb, &ctx);
1004 } else {
1005 if (unlikely(count > VMXNET3_MAX_TXD_PER_PKT)) {
1006
1007 /* non-tso pkts must not use more than
1008 * VMXNET3_MAX_TXD_PER_PKT entries
1009 */
1010 if (skb_linearize(skb) != 0) {
1011 tq->stats.drop_too_many_frags++;
1012 goto drop_pkt;
1013 }
1014 tq->stats.linearized++;
1015
1016 /* recalculate the # of descriptors to use */
1017 count = VMXNET3_TXD_NEEDED(skb_headlen(skb)) + 1;
1018 }
1019 }
1020
cec05562 1021 ret = vmxnet3_parse_hdr(skb, tq, &ctx, adapter);
d1a890fa
SB		 1022 if (ret >= 0) {
1023 BUG_ON(ret <= 0 && ctx.copy_size != 0);
1024 /* hdrs parsed, check against other limits */
1025 if (ctx.mss) {
1026 if (unlikely(ctx.eth_ip_hdr_size + ctx.l4_hdr_size >
1027 VMXNET3_MAX_TX_BUF_SIZE)) {
efc21d95
AB		 1028 tq->stats.drop_oversized_hdr++;
1029 goto drop_pkt;
d1a890fa
SB		 1030 }
1031 } else {
1032 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1033 if (unlikely(ctx.eth_ip_hdr_size +
1034 skb->csum_offset >
1035 VMXNET3_MAX_CSUM_OFFSET)) {
efc21d95
AB		 1036 tq->stats.drop_oversized_hdr++;
1037 goto drop_pkt;
d1a890fa
SB		 1038 }
1039 }
1040 }
1041 } else {
1042 tq->stats.drop_hdr_inspect_err++;
cec05562 1043 goto drop_pkt;
d1a890fa
SB		 1044 }
1045
cec05562
NH		 1046 spin_lock_irqsave(&tq->tx_lock, flags);
1047
1048 if (count > vmxnet3_cmd_ring_desc_avail(&tq->tx_ring)) {
1049 tq->stats.tx_ring_full++;
1050 netdev_dbg(adapter->netdev,
1051 "tx queue stopped on %s, next2comp %u"
1052 " next2fill %u\n", adapter->netdev->name,
1053 tq->tx_ring.next2comp, tq->tx_ring.next2fill);
1054
1055 vmxnet3_tq_stop(tq, adapter);
1056 spin_unlock_irqrestore(&tq->tx_lock, flags);
1057 return NETDEV_TX_BUSY;
1058 }
1059
1060
1061 vmxnet3_copy_hdr(skb, tq, &ctx, adapter);
1062
d1a890fa 1063 /* fill tx descs related to addr & len */
5738a09d
AK		 1064 if (vmxnet3_map_pkt(skb, &ctx, tq, adapter->pdev, adapter))
1065 goto unlock_drop_pkt;
d1a890fa
SB		 1066
1067 /* setup the EOP desc */
115924b6 1068 ctx.eop_txd->dword[3] = cpu_to_le32(VMXNET3_TXD_CQ | VMXNET3_TXD_EOP);
d1a890fa
SB		 1069
1070 /* setup the SOP desc */
115924b6
SB		 1071#ifdef __BIG_ENDIAN_BITFIELD
1072 gdesc = &tempTxDesc;
1073 gdesc->dword[2] = ctx.sop_txd->dword[2];
1074 gdesc->dword[3] = ctx.sop_txd->dword[3];
1075#else
d1a890fa 1076 gdesc = ctx.sop_txd;
115924b6 1077#endif
d1a890fa
SB		 1078 if (ctx.mss) {
1079 gdesc->txd.hlen = ctx.eth_ip_hdr_size + ctx.l4_hdr_size;
1080 gdesc->txd.om = VMXNET3_OM_TSO;
1081 gdesc->txd.msscof = ctx.mss;
115924b6
SB		 1082 le32_add_cpu(&tq->shared->txNumDeferred, (skb->len -
1083 gdesc->txd.hlen + ctx.mss - 1) / ctx.mss);
d1a890fa
SB		 1084 } else {
1085 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1086 gdesc->txd.hlen = ctx.eth_ip_hdr_size;
1087 gdesc->txd.om = VMXNET3_OM_CSUM;
1088 gdesc->txd.msscof = ctx.eth_ip_hdr_size +
1089 skb->csum_offset;
1090 } else {
1091 gdesc->txd.om = 0;
1092 gdesc->txd.msscof = 0;
1093 }
115924b6 1094 le32_add_cpu(&tq->shared->txNumDeferred, 1);
d1a890fa
SB		 1095 }
1096
df8a39de 1097 if (skb_vlan_tag_present(skb)) {
d1a890fa 1098 gdesc->txd.ti = 1;
df8a39de 1099 gdesc->txd.tci = skb_vlan_tag_get(skb);
d1a890fa
SB		 1100 }
1101
115924b6
SB		 1102 /* finally flips the GEN bit of the SOP desc. */
1103 gdesc->dword[2] = cpu_to_le32(le32_to_cpu(gdesc->dword[2]) ^
1104 VMXNET3_TXD_GEN);
1105#ifdef __BIG_ENDIAN_BITFIELD
1106 /* Finished updating in bitfields of Tx Desc, so write them in original
1107 * place.
1108 */
1109 vmxnet3_TxDescToLe((struct Vmxnet3_TxDesc *)gdesc,
1110 (struct Vmxnet3_TxDesc *)ctx.sop_txd);
1111 gdesc = ctx.sop_txd;
1112#endif
fdcd79b9 1113 netdev_dbg(adapter->netdev,
f6965582 1114 "txd[%u]: SOP 0x%Lx 0x%x 0x%x\n",
c2fd03a0 1115 (u32)(ctx.sop_txd -
115924b6
SB		 1116 tq->tx_ring.base), le64_to_cpu(gdesc->txd.addr),
1117 le32_to_cpu(gdesc->dword[2]), le32_to_cpu(gdesc->dword[3]));
d1a890fa
SB		 1118
1119 spin_unlock_irqrestore(&tq->tx_lock, flags);
1120
115924b6
SB		 1121 if (le32_to_cpu(tq->shared->txNumDeferred) >=
1122 le32_to_cpu(tq->shared->txThreshold)) {
d1a890fa 1123 tq->shared->txNumDeferred = 0;
09c5088e
SB		 1124 VMXNET3_WRITE_BAR0_REG(adapter,
1125 VMXNET3_REG_TXPROD + tq->qid * 8,
d1a890fa
SB		 1126 tq->tx_ring.next2fill);
1127 }
d1a890fa
SB		 1128
1129 return NETDEV_TX_OK;
1130
f955e141
DC		 1131unlock_drop_pkt:
1132 spin_unlock_irqrestore(&tq->tx_lock, flags);
d1a890fa
SB		 1133drop_pkt:
1134 tq->stats.drop_total++;
b1b71817 1135 dev_kfree_skb_any(skb);
d1a890fa
SB		 1136 return NETDEV_TX_OK;
1137}
1138
1139
1140static netdev_tx_t
1141vmxnet3_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
1142{
1143 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
d1a890fa 1144
96800ee7 1145 BUG_ON(skb->queue_mapping > adapter->num_tx_queues);
1146 return vmxnet3_tq_xmit(skb,
1147 &adapter->tx_queue[skb->queue_mapping],
1148 adapter, netdev);
d1a890fa
SB		 1149}
1150
1151
1152static void
1153vmxnet3_rx_csum(struct vmxnet3_adapter *adapter,
1154 struct sk_buff *skb,
1155 union Vmxnet3_GenericDesc *gdesc)
1156{
a0d2730c 1157 if (!gdesc->rcd.cnc && adapter->netdev->features & NETIF_F_RXCSUM) {
f0d43780
SK		 1158 if (gdesc->rcd.v4 &&
1159 (le32_to_cpu(gdesc->dword[3]) &
1160 VMXNET3_RCD_CSUM_OK) == VMXNET3_RCD_CSUM_OK) {
1161 skb->ip_summed = CHECKSUM_UNNECESSARY;
1162 BUG_ON(!(gdesc->rcd.tcp || gdesc->rcd.udp));
1163 BUG_ON(gdesc->rcd.frg);
1164 } else if (gdesc->rcd.v6 && (le32_to_cpu(gdesc->dword[3]) &
1165 (1 << VMXNET3_RCD_TUC_SHIFT))) {
d1a890fa
SB		 1166 skb->ip_summed = CHECKSUM_UNNECESSARY;
1167 BUG_ON(!(gdesc->rcd.tcp || gdesc->rcd.udp));
d1a890fa
SB		 1168 BUG_ON(gdesc->rcd.frg);
1169 } else {
1170 if (gdesc->rcd.csum) {
1171 skb->csum = htons(gdesc->rcd.csum);
1172 skb->ip_summed = CHECKSUM_PARTIAL;
1173 } else {
bc8acf2c 1174 skb_checksum_none_assert(skb);
d1a890fa
SB		 1175 }
1176 }
1177 } else {
bc8acf2c 1178 skb_checksum_none_assert(skb);
d1a890fa
SB		 1179 }
1180}
1181
1182
1183static void
1184vmxnet3_rx_error(struct vmxnet3_rx_queue *rq, struct Vmxnet3_RxCompDesc *rcd,
1185 struct vmxnet3_rx_ctx *ctx, struct vmxnet3_adapter *adapter)
1186{
1187 rq->stats.drop_err++;
1188 if (!rcd->fcs)
1189 rq->stats.drop_fcs++;
1190
1191 rq->stats.drop_total++;
1192
1193 /*
1194 * We do not unmap and chain the rx buffer to the skb.
1195 * We basically pretend this buffer is not used and will be recycled
1196 * by vmxnet3_rq_alloc_rx_buf()
1197 */
1198
1199 /*
1200 * ctx->skb may be NULL if this is the first and the only one
1201 * desc for the pkt
1202 */
1203 if (ctx->skb)
1204 dev_kfree_skb_irq(ctx->skb);
1205
1206 ctx->skb = NULL;
1207}
1208
1209
45dac1d6
SB		 1210static u32
1211vmxnet3_get_hdr_len(struct vmxnet3_adapter *adapter, struct sk_buff *skb,
1212 union Vmxnet3_GenericDesc *gdesc)
1213{
1214 u32 hlen, maplen;
1215 union {
1216 void *ptr;
1217 struct ethhdr *eth;
1218 struct iphdr *ipv4;
1219 struct ipv6hdr *ipv6;
1220 struct tcphdr *tcp;
1221 } hdr;
1222 BUG_ON(gdesc->rcd.tcp == 0);
1223
1224 maplen = skb_headlen(skb);
1225 if (unlikely(sizeof(struct iphdr) + sizeof(struct tcphdr) > maplen))
1226 return 0;
1227
1228 hdr.eth = eth_hdr(skb);
1229 if (gdesc->rcd.v4) {
1230 BUG_ON(hdr.eth->h_proto != htons(ETH_P_IP));
1231 hdr.ptr += sizeof(struct ethhdr);
1232 BUG_ON(hdr.ipv4->protocol != IPPROTO_TCP);
1233 hlen = hdr.ipv4->ihl << 2;
1234 hdr.ptr += hdr.ipv4->ihl << 2;
1235 } else if (gdesc->rcd.v6) {
1236 BUG_ON(hdr.eth->h_proto != htons(ETH_P_IPV6));
1237 hdr.ptr += sizeof(struct ethhdr);
1238 /* Use an estimated value, since we also need to handle
1239 * TSO case.
1240 */
1241 if (hdr.ipv6->nexthdr != IPPROTO_TCP)
1242 return sizeof(struct ipv6hdr) + sizeof(struct tcphdr);
1243 hlen = sizeof(struct ipv6hdr);
1244 hdr.ptr += sizeof(struct ipv6hdr);
1245 } else {
1246 /* Non-IP pkt, dont estimate header length */
1247 return 0;
1248 }
1249
1250 if (hlen + sizeof(struct tcphdr) > maplen)
1251 return 0;
1252
1253 return (hlen + (hdr.tcp->doff << 2));
1254}
1255
d1a890fa
SB		 1256static int
1257vmxnet3_rq_rx_complete(struct vmxnet3_rx_queue *rq,
1258 struct vmxnet3_adapter *adapter, int quota)
1259{
215faf9c
JP		 1260 static const u32 rxprod_reg[2] = {
1261 VMXNET3_REG_RXPROD, VMXNET3_REG_RXPROD2
1262 };
0769636c 1263 u32 num_pkts = 0;
5318d809 1264 bool skip_page_frags = false;
d1a890fa
SB		 1265 struct Vmxnet3_RxCompDesc *rcd;
1266 struct vmxnet3_rx_ctx *ctx = &rq->rx_ctx;
45dac1d6 1267 u16 segCnt = 0, mss = 0;
115924b6
SB		 1268#ifdef __BIG_ENDIAN_BITFIELD
1269 struct Vmxnet3_RxDesc rxCmdDesc;
1270 struct Vmxnet3_RxCompDesc rxComp;
1271#endif
1272 vmxnet3_getRxComp(rcd, &rq->comp_ring.base[rq->comp_ring.next2proc].rcd,
1273 &rxComp);
d1a890fa
SB		 1274 while (rcd->gen == rq->comp_ring.gen) {
1275 struct vmxnet3_rx_buf_info *rbi;
5318d809
SB		 1276 struct sk_buff *skb, *new_skb = NULL;
1277 struct page *new_page = NULL;
5738a09d 1278 dma_addr_t new_dma_addr;
d1a890fa
SB		 1279 int num_to_alloc;
1280 struct Vmxnet3_RxDesc *rxd;
1281 u32 idx, ring_idx;
5318d809 1282 struct vmxnet3_cmd_ring *ring = NULL;
0769636c 1283 if (num_pkts >= quota) {
d1a890fa
SB		 1284 /* we may stop even before we see the EOP desc of
1285 * the current pkt
1286 */
1287 break;
1288 }
50a5ce3e
SK		 1289 BUG_ON(rcd->rqID != rq->qid && rcd->rqID != rq->qid2 &&
1290 rcd->rqID != rq->dataRingQid);
d1a890fa 1291 idx = rcd->rxdIdx;
50a5ce3e 1292 ring_idx = VMXNET3_GET_RING_IDX(adapter, rcd->rqID);
5318d809 1293 ring = rq->rx_ring + ring_idx;
115924b6
SB		 1294 vmxnet3_getRxDesc(rxd, &rq->rx_ring[ring_idx].base[idx].rxd,
1295 &rxCmdDesc);
d1a890fa
SB		 1296 rbi = rq->buf_info[ring_idx] + idx;
1297
115924b6
SB		 1298 BUG_ON(rxd->addr != rbi->dma_addr ||
1299 rxd->len != rbi->len);
d1a890fa
SB		 1300
1301 if (unlikely(rcd->eop && rcd->err)) {
1302 vmxnet3_rx_error(rq, rcd, ctx, adapter);
1303 goto rcd_done;
1304 }
1305
1306 if (rcd->sop) { /* first buf of the pkt */
50a5ce3e
SK		 1307 bool rxDataRingUsed;
1308 u16 len;
1309
d1a890fa 1310 BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_HEAD ||
50a5ce3e
SK		 1311 (rcd->rqID != rq->qid &&
1312 rcd->rqID != rq->dataRingQid));
d1a890fa
SB		 1313
1314 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_SKB);
1315 BUG_ON(ctx->skb != NULL || rbi->skb == NULL);
1316
1317 if (unlikely(rcd->len == 0)) {
1318 /* Pretend the rx buffer is skipped. */
1319 BUG_ON(!(rcd->sop && rcd->eop));
fdcd79b9 1320 netdev_dbg(adapter->netdev,
f6965582 1321 "rxRing[%u][%u] 0 length\n",
d1a890fa
SB		 1322 ring_idx, idx);
1323 goto rcd_done;
1324 }
1325
5318d809 1326 skip_page_frags = false;
d1a890fa 1327 ctx->skb = rbi->skb;
50a5ce3e
SK		 1328
1329 rxDataRingUsed =
1330 VMXNET3_RX_DATA_RING(adapter, rcd->rqID);
1331 len = rxDataRingUsed ? rcd->len : rbi->len;
0d735f13 1332 new_skb = netdev_alloc_skb_ip_align(adapter->netdev,
50a5ce3e 1333 len);
5318d809
SB		 1334 if (new_skb == NULL) {
1335 /* Skb allocation failed, do not handover this
1336 * skb to stack. Reuse it. Drop the existing pkt
1337 */
1338 rq->stats.rx_buf_alloc_failure++;
1339 ctx->skb = NULL;
1340 rq->stats.drop_total++;
1341 skip_page_frags = true;
1342 goto rcd_done;
1343 }
d1a890fa 1344
50a5ce3e
SK		 1345 if (rxDataRingUsed) {
1346 size_t sz;
1347
1348 BUG_ON(rcd->len > rq->data_ring.desc_size);
1349
1350 ctx->skb = new_skb;
1351 sz = rcd->rxdIdx * rq->data_ring.desc_size;
1352 memcpy(new_skb->data,
1353 &rq->data_ring.base[sz], rcd->len);
1354 } else {
1355 ctx->skb = rbi->skb;
1356
1357 new_dma_addr =
1358 dma_map_single(&adapter->pdev->dev,
1359 new_skb->data, rbi->len,
1360 PCI_DMA_FROMDEVICE);
1361 if (dma_mapping_error(&adapter->pdev->dev,
1362 new_dma_addr)) {
1363 dev_kfree_skb(new_skb);
1364 /* Skb allocation failed, do not
1365 * handover this skb to stack. Reuse
1366 * it. Drop the existing pkt.
1367 */
1368 rq->stats.rx_buf_alloc_failure++;
1369 ctx->skb = NULL;
1370 rq->stats.drop_total++;
1371 skip_page_frags = true;
1372 goto rcd_done;
1373 }
1374
1375 dma_unmap_single(&adapter->pdev->dev,
1376 rbi->dma_addr,
1377 rbi->len,
1378 PCI_DMA_FROMDEVICE);
1379
1380 /* Immediate refill */
1381 rbi->skb = new_skb;
1382 rbi->dma_addr = new_dma_addr;
1383 rxd->addr = cpu_to_le64(rbi->dma_addr);
1384 rxd->len = rbi->len;
1385 }
d1a890fa 1386
7db11f75
SH		 1387#ifdef VMXNET3_RSS
1388 if (rcd->rssType != VMXNET3_RCD_RSS_TYPE_NONE &&
1389 (adapter->netdev->features & NETIF_F_RXHASH))
2c15a154
MS		 1390 skb_set_hash(ctx->skb,
1391 le32_to_cpu(rcd->rssHash),
0b680703 1392 PKT_HASH_TYPE_L3);
7db11f75 1393#endif
d1a890fa 1394 skb_put(ctx->skb, rcd->len);
5318d809 1395
190af10f 1396 if (VMXNET3_VERSION_GE_2(adapter) &&
45dac1d6
SB		 1397 rcd->type == VMXNET3_CDTYPE_RXCOMP_LRO) {
1398 struct Vmxnet3_RxCompDescExt *rcdlro;
1399 rcdlro = (struct Vmxnet3_RxCompDescExt *)rcd;
1400
1401 segCnt = rcdlro->segCnt;
50219538 1402 WARN_ON_ONCE(segCnt == 0);
45dac1d6
SB		 1403 mss = rcdlro->mss;
1404 if (unlikely(segCnt <= 1))
1405 segCnt = 0;
1406 } else {
1407 segCnt = 0;
1408 }
d1a890fa 1409 } else {
5318d809
SB		 1410 BUG_ON(ctx->skb == NULL && !skip_page_frags);
1411
d1a890fa 1412 /* non SOP buffer must be type 1 in most cases */
5318d809
SB		 1413 BUG_ON(rbi->buf_type != VMXNET3_RX_BUF_PAGE);
1414 BUG_ON(rxd->btype != VMXNET3_RXD_BTYPE_BODY);
d1a890fa 1415
5318d809
SB		 1416 /* If an sop buffer was dropped, skip all
1417 * following non-sop fragments. They will be reused.
1418 */
1419 if (skip_page_frags)
1420 goto rcd_done;
d1a890fa 1421
c41fcce9
SB		 1422 if (rcd->len) {
1423 new_page = alloc_page(GFP_ATOMIC);
5318d809
SB		 1424 /* Replacement page frag could not be allocated.
1425 * Reuse this page. Drop the pkt and free the
1426 * skb which contained this page as a frag. Skip
1427 * processing all the following non-sop frags.
d1a890fa 1428 */
c41fcce9
SB		 1429 if (unlikely(!new_page)) {
1430 rq->stats.rx_buf_alloc_failure++;
1431 dev_kfree_skb(ctx->skb);
1432 ctx->skb = NULL;
1433 skip_page_frags = true;
1434 goto rcd_done;
1435 }
58caf637
SK		 1436 new_dma_addr = dma_map_page(&adapter->pdev->dev,
1437 new_page,
1438 0, PAGE_SIZE,
1439 PCI_DMA_FROMDEVICE);
5738a09d
AK		 1440 if (dma_mapping_error(&adapter->pdev->dev,
1441 new_dma_addr)) {
1442 put_page(new_page);
1443 rq->stats.rx_buf_alloc_failure++;
1444 dev_kfree_skb(ctx->skb);
1445 ctx->skb = NULL;
1446 skip_page_frags = true;
1447 goto rcd_done;
1448 }
5318d809 1449
b0eb57cb 1450 dma_unmap_page(&adapter->pdev->dev,
5318d809
SB		 1451 rbi->dma_addr, rbi->len,
1452 PCI_DMA_FROMDEVICE);
1453
1454 vmxnet3_append_frag(ctx->skb, rcd, rbi);
5318d809 1455
c41fcce9
SB		 1456 /* Immediate refill */
1457 rbi->page = new_page;
5738a09d 1458 rbi->dma_addr = new_dma_addr;
c41fcce9
SB		 1459 rxd->addr = cpu_to_le64(rbi->dma_addr);
1460 rxd->len = rbi->len;
1461 }
d1a890fa
SB		 1462 }
1463
5318d809 1464
d1a890fa
SB		 1465 skb = ctx->skb;
1466 if (rcd->eop) {
45dac1d6 1467 u32 mtu = adapter->netdev->mtu;
d1a890fa 1468 skb->len += skb->data_len;
d1a890fa
SB		 1469
1470 vmxnet3_rx_csum(adapter, skb,
1471 (union Vmxnet3_GenericDesc *)rcd);
1472 skb->protocol = eth_type_trans(skb, adapter->netdev);
45dac1d6
SB		 1473 if (!rcd->tcp || !adapter->lro)
1474 goto not_lro;
1475
1476 if (segCnt != 0 && mss != 0) {
1477 skb_shinfo(skb)->gso_type = rcd->v4 ?
1478 SKB_GSO_TCPV4 : SKB_GSO_TCPV6;
1479 skb_shinfo(skb)->gso_size = mss;
1480 skb_shinfo(skb)->gso_segs = segCnt;
1481 } else if (segCnt != 0 || skb->len > mtu) {
1482 u32 hlen;
1483
1484 hlen = vmxnet3_get_hdr_len(adapter, skb,
1485 (union Vmxnet3_GenericDesc *)rcd);
1486 if (hlen == 0)
1487 goto not_lro;
1488
1489 skb_shinfo(skb)->gso_type =
1490 rcd->v4 ? SKB_GSO_TCPV4 : SKB_GSO_TCPV6;
1491 if (segCnt != 0) {
1492 skb_shinfo(skb)->gso_segs = segCnt;
1493 skb_shinfo(skb)->gso_size =
1494 DIV_ROUND_UP(skb->len -
1495 hlen, segCnt);
1496 } else {
1497 skb_shinfo(skb)->gso_size = mtu - hlen;
1498 }
1499 }
1500not_lro:
72e85c45 1501 if (unlikely(rcd->ts))
86a9bad3 1502 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), rcd->tci);
72e85c45 1503
213ade8c
JG		 1504 if (adapter->netdev->features & NETIF_F_LRO)
1505 netif_receive_skb(skb);
1506 else
1507 napi_gro_receive(&rq->napi, skb);
d1a890fa 1508
d1a890fa 1509 ctx->skb = NULL;
0769636c 1510 num_pkts++;
d1a890fa
SB		 1511 }
1512
1513rcd_done:
5318d809
SB		 1514 /* device may have skipped some rx descs */
1515 ring->next2comp = idx;
1516 num_to_alloc = vmxnet3_cmd_ring_desc_avail(ring);
1517 ring = rq->rx_ring + ring_idx;
1518 while (num_to_alloc) {
1519 vmxnet3_getRxDesc(rxd, &ring->base[ring->next2fill].rxd,
1520 &rxCmdDesc);
1521 BUG_ON(!rxd->addr);
1522
1523 /* Recv desc is ready to be used by the device */
1524 rxd->gen = ring->gen;
1525 vmxnet3_cmd_ring_adv_next2fill(ring);
1526 num_to_alloc--;
1527 }
1528
1529 /* if needed, update the register */
1530 if (unlikely(rq->shared->updateRxProd)) {
1531 VMXNET3_WRITE_BAR0_REG(adapter,
96800ee7 1532 rxprod_reg[ring_idx] + rq->qid * 8,
1533 ring->next2fill);
d1a890fa
SB		 1534 }
1535
1536 vmxnet3_comp_ring_adv_next2proc(&rq->comp_ring);
115924b6 1537 vmxnet3_getRxComp(rcd,
96800ee7 1538 &rq->comp_ring.base[rq->comp_ring.next2proc].rcd, &rxComp);
d1a890fa
SB		 1539 }
1540
0769636c 1541 return num_pkts;
d1a890fa
SB		 1542}
1543
1544
1545static void
1546vmxnet3_rq_cleanup(struct vmxnet3_rx_queue *rq,
1547 struct vmxnet3_adapter *adapter)
1548{
1549 u32 i, ring_idx;
1550 struct Vmxnet3_RxDesc *rxd;
1551
1552 for (ring_idx = 0; ring_idx < 2; ring_idx++) {
1553 for (i = 0; i < rq->rx_ring[ring_idx].size; i++) {
115924b6
SB		 1554#ifdef __BIG_ENDIAN_BITFIELD
1555 struct Vmxnet3_RxDesc rxDesc;
1556#endif
1557 vmxnet3_getRxDesc(rxd,
1558 &rq->rx_ring[ring_idx].base[i].rxd, &rxDesc);
d1a890fa
SB		 1559
1560 if (rxd->btype == VMXNET3_RXD_BTYPE_HEAD &&
1561 rq->buf_info[ring_idx][i].skb) {
b0eb57cb 1562 dma_unmap_single(&adapter->pdev->dev, rxd->addr,
d1a890fa
SB		 1563 rxd->len, PCI_DMA_FROMDEVICE);
1564 dev_kfree_skb(rq->buf_info[ring_idx][i].skb);
1565 rq->buf_info[ring_idx][i].skb = NULL;
1566 } else if (rxd->btype == VMXNET3_RXD_BTYPE_BODY &&
1567 rq->buf_info[ring_idx][i].page) {
b0eb57cb 1568 dma_unmap_page(&adapter->pdev->dev, rxd->addr,
d1a890fa
SB		 1569 rxd->len, PCI_DMA_FROMDEVICE);
1570 put_page(rq->buf_info[ring_idx][i].page);
1571 rq->buf_info[ring_idx][i].page = NULL;
1572 }
1573 }
1574
1575 rq->rx_ring[ring_idx].gen = VMXNET3_INIT_GEN;
1576 rq->rx_ring[ring_idx].next2fill =
1577 rq->rx_ring[ring_idx].next2comp = 0;
d1a890fa
SB		 1578 }
1579
1580 rq->comp_ring.gen = VMXNET3_INIT_GEN;
1581 rq->comp_ring.next2proc = 0;
1582}
1583
1584
09c5088e
SB		 1585static void
1586vmxnet3_rq_cleanup_all(struct vmxnet3_adapter *adapter)
1587{
1588 int i;
1589
1590 for (i = 0; i < adapter->num_rx_queues; i++)
1591 vmxnet3_rq_cleanup(&adapter->rx_queue[i], adapter);
1592}
1593
1594
280b74f7 1595static void vmxnet3_rq_destroy(struct vmxnet3_rx_queue *rq,
1596 struct vmxnet3_adapter *adapter)
d1a890fa
SB		 1597{
1598 int i;
1599 int j;
1600
1601 /* all rx buffers must have already been freed */
1602 for (i = 0; i < 2; i++) {
1603 if (rq->buf_info[i]) {
1604 for (j = 0; j < rq->rx_ring[i].size; j++)
1605 BUG_ON(rq->buf_info[i][j].page != NULL);
1606 }
1607 }
1608
1609
d1a890fa
SB		 1610 for (i = 0; i < 2; i++) {
1611 if (rq->rx_ring[i].base) {
b0eb57cb
AK		 1612 dma_free_coherent(&adapter->pdev->dev,
1613 rq->rx_ring[i].size
1614 * sizeof(struct Vmxnet3_RxDesc),
1615 rq->rx_ring[i].base,
1616 rq->rx_ring[i].basePA);
d1a890fa
SB		 1617 rq->rx_ring[i].base = NULL;
1618 }
d1a890fa
SB		 1619 }
1620
50a5ce3e
SK		 1621 if (rq->data_ring.base) {
1622 dma_free_coherent(&adapter->pdev->dev,
1623 rq->rx_ring[0].size * rq->data_ring.desc_size,
1624 rq->data_ring.base, rq->data_ring.basePA);
1625 rq->data_ring.base = NULL;
1626 }
1627
d1a890fa 1628 if (rq->comp_ring.base) {
b0eb57cb
AK		 1629 dma_free_coherent(&adapter->pdev->dev, rq->comp_ring.size
1630 * sizeof(struct Vmxnet3_RxCompDesc),
1631 rq->comp_ring.base, rq->comp_ring.basePA);
d1a890fa
SB		 1632 rq->comp_ring.base = NULL;
1633 }
b0eb57cb
AK		 1634
1635 if (rq->buf_info[0]) {
1636 size_t sz = sizeof(struct vmxnet3_rx_buf_info) *
1637 (rq->rx_ring[0].size + rq->rx_ring[1].size);
1638 dma_free_coherent(&adapter->pdev->dev, sz, rq->buf_info[0],
1639 rq->buf_info_pa);
848b1598 1640 rq->buf_info[0] = rq->buf_info[1] = NULL;
b0eb57cb 1641 }
d1a890fa
SB		 1642}
1643
bb40aca7 1644static void
50a5ce3e
SK		 1645vmxnet3_rq_destroy_all_rxdataring(struct vmxnet3_adapter *adapter)
1646{
1647 int i;
1648
1649 for (i = 0; i < adapter->num_rx_queues; i++) {
1650 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
1651
1652 if (rq->data_ring.base) {
1653 dma_free_coherent(&adapter->pdev->dev,
1654 (rq->rx_ring[0].size *
1655 rq->data_ring.desc_size),
1656 rq->data_ring.base,
1657 rq->data_ring.basePA);
1658 rq->data_ring.base = NULL;
1659 rq->data_ring.desc_size = 0;
1660 }
1661 }
1662}
d1a890fa
SB		 1663
1664static int
1665vmxnet3_rq_init(struct vmxnet3_rx_queue *rq,
1666 struct vmxnet3_adapter *adapter)
1667{
1668 int i;
1669
1670 /* initialize buf_info */
1671 for (i = 0; i < rq->rx_ring[0].size; i++) {
1672
1673 /* 1st buf for a pkt is skbuff */
1674 if (i % adapter->rx_buf_per_pkt == 0) {
1675 rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_SKB;
1676 rq->buf_info[0][i].len = adapter->skb_buf_size;
1677 } else { /* subsequent bufs for a pkt is frag */
1678 rq->buf_info[0][i].buf_type = VMXNET3_RX_BUF_PAGE;
1679 rq->buf_info[0][i].len = PAGE_SIZE;
1680 }
1681 }
1682 for (i = 0; i < rq->rx_ring[1].size; i++) {
1683 rq->buf_info[1][i].buf_type = VMXNET3_RX_BUF_PAGE;
1684 rq->buf_info[1][i].len = PAGE_SIZE;
1685 }
1686
1687 /* reset internal state and allocate buffers for both rings */
1688 for (i = 0; i < 2; i++) {
1689 rq->rx_ring[i].next2fill = rq->rx_ring[i].next2comp = 0;
d1a890fa
SB		 1690
1691 memset(rq->rx_ring[i].base, 0, rq->rx_ring[i].size *
1692 sizeof(struct Vmxnet3_RxDesc));
1693 rq->rx_ring[i].gen = VMXNET3_INIT_GEN;
1694 }
1695 if (vmxnet3_rq_alloc_rx_buf(rq, 0, rq->rx_ring[0].size - 1,
1696 adapter) == 0) {
1697 /* at least has 1 rx buffer for the 1st ring */
1698 return -ENOMEM;
1699 }
1700 vmxnet3_rq_alloc_rx_buf(rq, 1, rq->rx_ring[1].size - 1, adapter);
1701
1702 /* reset the comp ring */
1703 rq->comp_ring.next2proc = 0;
1704 memset(rq->comp_ring.base, 0, rq->comp_ring.size *
1705 sizeof(struct Vmxnet3_RxCompDesc));
1706 rq->comp_ring.gen = VMXNET3_INIT_GEN;
1707
1708 /* reset rxctx */
1709 rq->rx_ctx.skb = NULL;
1710
1711 /* stats are not reset */
1712 return 0;
1713}
1714
1715
09c5088e
SB		 1716static int
1717vmxnet3_rq_init_all(struct vmxnet3_adapter *adapter)
1718{
1719 int i, err = 0;
1720
1721 for (i = 0; i < adapter->num_rx_queues; i++) {
1722 err = vmxnet3_rq_init(&adapter->rx_queue[i], adapter);
1723 if (unlikely(err)) {
1724 dev_err(&adapter->netdev->dev, "%s: failed to "
1725 "initialize rx queue%i\n",
1726 adapter->netdev->name, i);
1727 break;
1728 }
1729 }
1730 return err;
1731
1732}
1733
1734
d1a890fa
SB		 1735static int
1736vmxnet3_rq_create(struct vmxnet3_rx_queue *rq, struct vmxnet3_adapter *adapter)
1737{
1738 int i;
1739 size_t sz;
1740 struct vmxnet3_rx_buf_info *bi;
1741
1742 for (i = 0; i < 2; i++) {
1743
1744 sz = rq->rx_ring[i].size * sizeof(struct Vmxnet3_RxDesc);
b0eb57cb
AK		 1745 rq->rx_ring[i].base = dma_alloc_coherent(
1746 &adapter->pdev->dev, sz,
1747 &rq->rx_ring[i].basePA,
1748 GFP_KERNEL);
d1a890fa 1749 if (!rq->rx_ring[i].base) {
204a6e65
SH		 1750 netdev_err(adapter->netdev,
1751 "failed to allocate rx ring %d\n", i);
d1a890fa
SB		 1752 goto err;
1753 }
1754 }
1755
50a5ce3e
SK		 1756 if ((adapter->rxdataring_enabled) && (rq->data_ring.desc_size != 0)) {
1757 sz = rq->rx_ring[0].size * rq->data_ring.desc_size;
1758 rq->data_ring.base =
1759 dma_alloc_coherent(&adapter->pdev->dev, sz,
1760 &rq->data_ring.basePA,
1761 GFP_KERNEL);
1762 if (!rq->data_ring.base) {
1763 netdev_err(adapter->netdev,
1764 "rx data ring will be disabled\n");
1765 adapter->rxdataring_enabled = false;
1766 }
1767 } else {
1768 rq->data_ring.base = NULL;
1769 rq->data_ring.desc_size = 0;
1770 }
1771
d1a890fa 1772 sz = rq->comp_ring.size * sizeof(struct Vmxnet3_RxCompDesc);
b0eb57cb
AK		 1773 rq->comp_ring.base = dma_alloc_coherent(&adapter->pdev->dev, sz,
1774 &rq->comp_ring.basePA,
1775 GFP_KERNEL);
d1a890fa 1776 if (!rq->comp_ring.base) {
204a6e65 1777 netdev_err(adapter->netdev, "failed to allocate rx comp ring\n");
d1a890fa
SB		 1778 goto err;
1779 }
1780
1781 sz = sizeof(struct vmxnet3_rx_buf_info) * (rq->rx_ring[0].size +
1782 rq->rx_ring[1].size);
b0eb57cb
AK		 1783 bi = dma_zalloc_coherent(&adapter->pdev->dev, sz, &rq->buf_info_pa,
1784 GFP_KERNEL);
e404decb 1785 if (!bi)
d1a890fa 1786 goto err;
e404decb 1787
d1a890fa
SB		 1788 rq->buf_info[0] = bi;
1789 rq->buf_info[1] = bi + rq->rx_ring[0].size;
1790
1791 return 0;
1792
1793err:
1794 vmxnet3_rq_destroy(rq, adapter);
1795 return -ENOMEM;
1796}
1797
1798
09c5088e
SB		 1799static int
1800vmxnet3_rq_create_all(struct vmxnet3_adapter *adapter)
1801{
1802 int i, err = 0;
1803
50a5ce3e
SK		 1804 adapter->rxdataring_enabled = VMXNET3_VERSION_GE_3(adapter);
1805
09c5088e
SB		 1806 for (i = 0; i < adapter->num_rx_queues; i++) {
1807 err = vmxnet3_rq_create(&adapter->rx_queue[i], adapter);
1808 if (unlikely(err)) {
1809 dev_err(&adapter->netdev->dev,
1810 "%s: failed to create rx queue%i\n",
1811 adapter->netdev->name, i);
1812 goto err_out;
1813 }
1814 }
50a5ce3e
SK		 1815
1816 if (!adapter->rxdataring_enabled)
1817 vmxnet3_rq_destroy_all_rxdataring(adapter);
1818
09c5088e
SB		 1819 return err;
1820err_out:
1821 vmxnet3_rq_destroy_all(adapter);
1822 return err;
1823
1824}
1825
1826/* Multiple queue aware polling function for tx and rx */
1827
d1a890fa
SB		 1828static int
1829vmxnet3_do_poll(struct vmxnet3_adapter *adapter, int budget)
1830{
09c5088e 1831 int rcd_done = 0, i;
d1a890fa
SB		 1832 if (unlikely(adapter->shared->ecr))
1833 vmxnet3_process_events(adapter);
09c5088e
SB		 1834 for (i = 0; i < adapter->num_tx_queues; i++)
1835 vmxnet3_tq_tx_complete(&adapter->tx_queue[i], adapter);
d1a890fa 1836
09c5088e
SB		 1837 for (i = 0; i < adapter->num_rx_queues; i++)
1838 rcd_done += vmxnet3_rq_rx_complete(&adapter->rx_queue[i],
1839 adapter, budget);
1840 return rcd_done;
d1a890fa
SB		 1841}
1842
1843
1844static int
1845vmxnet3_poll(struct napi_struct *napi, int budget)
1846{
09c5088e
SB		 1847 struct vmxnet3_rx_queue *rx_queue = container_of(napi,
1848 struct vmxnet3_rx_queue, napi);
1849 int rxd_done;
1850
1851 rxd_done = vmxnet3_do_poll(rx_queue->adapter, budget);
1852
1853 if (rxd_done < budget) {
6ad20165 1854 napi_complete_done(napi, rxd_done);
09c5088e
SB		 1855 vmxnet3_enable_all_intrs(rx_queue->adapter);
1856 }
1857 return rxd_done;
1858}
1859
1860/*
1861 * NAPI polling function for MSI-X mode with multiple Rx queues
1862 * Returns the # of the NAPI credit consumed (# of rx descriptors processed)
1863 */
1864
1865static int
1866vmxnet3_poll_rx_only(struct napi_struct *napi, int budget)
1867{
1868 struct vmxnet3_rx_queue *rq = container_of(napi,
1869 struct vmxnet3_rx_queue, napi);
1870 struct vmxnet3_adapter *adapter = rq->adapter;
d1a890fa
SB		 1871 int rxd_done;
1872
09c5088e
SB		 1873 /* When sharing interrupt with corresponding tx queue, process
1874 * tx completions in that queue as well
1875 */
1876 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE) {
1877 struct vmxnet3_tx_queue *tq =
1878 &adapter->tx_queue[rq - adapter->rx_queue];
1879 vmxnet3_tq_tx_complete(tq, adapter);
1880 }
1881
1882 rxd_done = vmxnet3_rq_rx_complete(rq, adapter, budget);
d1a890fa
SB		 1883
1884 if (rxd_done < budget) {
6ad20165 1885 napi_complete_done(napi, rxd_done);
09c5088e 1886 vmxnet3_enable_intr(adapter, rq->comp_ring.intr_idx);
d1a890fa
SB		 1887 }
1888 return rxd_done;
1889}
1890
1891
09c5088e
SB		 1892#ifdef CONFIG_PCI_MSI
1893
1894/*
1895 * Handle completion interrupts on tx queues
1896 * Returns whether or not the intr is handled
1897 */
1898
1899static irqreturn_t
1900vmxnet3_msix_tx(int irq, void *data)
1901{
1902 struct vmxnet3_tx_queue *tq = data;
1903 struct vmxnet3_adapter *adapter = tq->adapter;
1904
1905 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
1906 vmxnet3_disable_intr(adapter, tq->comp_ring.intr_idx);
1907
1908 /* Handle the case where only one irq is allocate for all tx queues */
1909 if (adapter->share_intr == VMXNET3_INTR_TXSHARE) {
1910 int i;
1911 for (i = 0; i < adapter->num_tx_queues; i++) {
1912 struct vmxnet3_tx_queue *txq = &adapter->tx_queue[i];
1913 vmxnet3_tq_tx_complete(txq, adapter);
1914 }
1915 } else {
1916 vmxnet3_tq_tx_complete(tq, adapter);
1917 }
1918 vmxnet3_enable_intr(adapter, tq->comp_ring.intr_idx);
1919
1920 return IRQ_HANDLED;
1921}
1922
1923
1924/*
1925 * Handle completion interrupts on rx queues. Returns whether or not the
1926 * intr is handled
1927 */
1928
1929static irqreturn_t
1930vmxnet3_msix_rx(int irq, void *data)
1931{
1932 struct vmxnet3_rx_queue *rq = data;
1933 struct vmxnet3_adapter *adapter = rq->adapter;
1934
1935 /* disable intr if needed */
1936 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
1937 vmxnet3_disable_intr(adapter, rq->comp_ring.intr_idx);
1938 napi_schedule(&rq->napi);
1939
1940 return IRQ_HANDLED;
1941}
1942
1943/*
1944 *----------------------------------------------------------------------------
1945 *
1946 * vmxnet3_msix_event --
1947 *
1948 * vmxnet3 msix event intr handler
1949 *
1950 * Result:
1951 * whether or not the intr is handled
1952 *
1953 *----------------------------------------------------------------------------
1954 */
1955
1956static irqreturn_t
1957vmxnet3_msix_event(int irq, void *data)
1958{
1959 struct net_device *dev = data;
1960 struct vmxnet3_adapter *adapter = netdev_priv(dev);
1961
1962 /* disable intr if needed */
1963 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
1964 vmxnet3_disable_intr(adapter, adapter->intr.event_intr_idx);
1965
1966 if (adapter->shared->ecr)
1967 vmxnet3_process_events(adapter);
1968
1969 vmxnet3_enable_intr(adapter, adapter->intr.event_intr_idx);
1970
1971 return IRQ_HANDLED;
1972}
1973
1974#endif /* CONFIG_PCI_MSI */
1975
1976
d1a890fa
SB		 1977/* Interrupt handler for vmxnet3 */
1978static irqreturn_t
1979vmxnet3_intr(int irq, void *dev_id)
1980{
1981 struct net_device *dev = dev_id;
1982 struct vmxnet3_adapter *adapter = netdev_priv(dev);
1983
09c5088e 1984 if (adapter->intr.type == VMXNET3_IT_INTX) {
d1a890fa
SB		 1985 u32 icr = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_ICR);
1986 if (unlikely(icr == 0))
1987 /* not ours */
1988 return IRQ_NONE;
1989 }
1990
1991
1992 /* disable intr if needed */
1993 if (adapter->intr.mask_mode == VMXNET3_IMM_ACTIVE)
09c5088e 1994 vmxnet3_disable_all_intrs(adapter);
d1a890fa 1995
09c5088e 1996 napi_schedule(&adapter->rx_queue[0].napi);
d1a890fa
SB		 1997
1998 return IRQ_HANDLED;
1999}
2000
2001#ifdef CONFIG_NET_POLL_CONTROLLER
2002
d1a890fa
SB		 2003/* netpoll callback. */
2004static void
2005vmxnet3_netpoll(struct net_device *netdev)
2006{
2007 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
d1a890fa 2008
d25f06ea 2009 switch (adapter->intr.type) {
0a8d8c44
AB		 2010#ifdef CONFIG_PCI_MSI
2011 case VMXNET3_IT_MSIX: {
2012 int i;
d25f06ea
NH		 2013 for (i = 0; i < adapter->num_rx_queues; i++)
2014 vmxnet3_msix_rx(0, &adapter->rx_queue[i]);
2015 break;
0a8d8c44
AB		 2016 }
2017#endif
d25f06ea
NH		 2018 case VMXNET3_IT_MSI:
2019 default:
2020 vmxnet3_intr(0, adapter->netdev);
2021 break;
2022 }
d1a890fa 2023
d1a890fa 2024}
09c5088e 2025#endif /* CONFIG_NET_POLL_CONTROLLER */
d1a890fa
SB		 2026
2027static int
2028vmxnet3_request_irqs(struct vmxnet3_adapter *adapter)
2029{
09c5088e
SB		 2030 struct vmxnet3_intr *intr = &adapter->intr;
2031 int err = 0, i;
2032 int vector = 0;
d1a890fa 2033
8f7e524c 2034#ifdef CONFIG_PCI_MSI
d1a890fa 2035 if (adapter->intr.type == VMXNET3_IT_MSIX) {
09c5088e
SB		 2036 for (i = 0; i < adapter->num_tx_queues; i++) {
2037 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) {
2038 sprintf(adapter->tx_queue[i].name, "%s-tx-%d",
2039 adapter->netdev->name, vector);
2040 err = request_irq(
2041 intr->msix_entries[vector].vector,
2042 vmxnet3_msix_tx, 0,
2043 adapter->tx_queue[i].name,
2044 &adapter->tx_queue[i]);
2045 } else {
2046 sprintf(adapter->tx_queue[i].name, "%s-rxtx-%d",
2047 adapter->netdev->name, vector);
2048 }
2049 if (err) {
2050 dev_err(&adapter->netdev->dev,
2051 "Failed to request irq for MSIX, %s, "
2052 "error %d\n",
2053 adapter->tx_queue[i].name, err);
2054 return err;
2055 }
2056
2057 /* Handle the case where only 1 MSIx was allocated for
2058 * all tx queues */
2059 if (adapter->share_intr == VMXNET3_INTR_TXSHARE) {
2060 for (; i < adapter->num_tx_queues; i++)
2061 adapter->tx_queue[i].comp_ring.intr_idx
2062 = vector;
2063 vector++;
2064 break;
2065 } else {
2066 adapter->tx_queue[i].comp_ring.intr_idx
2067 = vector++;
2068 }
2069 }
2070 if (adapter->share_intr == VMXNET3_INTR_BUDDYSHARE)
2071 vector = 0;
2072
2073 for (i = 0; i < adapter->num_rx_queues; i++) {
2074 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE)
2075 sprintf(adapter->rx_queue[i].name, "%s-rx-%d",
2076 adapter->netdev->name, vector);
2077 else
2078 sprintf(adapter->rx_queue[i].name, "%s-rxtx-%d",
2079 adapter->netdev->name, vector);
2080 err = request_irq(intr->msix_entries[vector].vector,
2081 vmxnet3_msix_rx, 0,
2082 adapter->rx_queue[i].name,
2083 &(adapter->rx_queue[i]));
2084 if (err) {
204a6e65
SH		 2085 netdev_err(adapter->netdev,
2086 "Failed to request irq for MSIX, "
2087 "%s, error %d\n",
2088 adapter->rx_queue[i].name, err);
09c5088e
SB		 2089 return err;
2090 }
2091
2092 adapter->rx_queue[i].comp_ring.intr_idx = vector++;
2093 }
2094
2095 sprintf(intr->event_msi_vector_name, "%s-event-%d",
2096 adapter->netdev->name, vector);
2097 err = request_irq(intr->msix_entries[vector].vector,
2098 vmxnet3_msix_event, 0,
2099 intr->event_msi_vector_name, adapter->netdev);
2100 intr->event_intr_idx = vector;
2101
2102 } else if (intr->type == VMXNET3_IT_MSI) {
2103 adapter->num_rx_queues = 1;
d1a890fa
SB		 2104 err = request_irq(adapter->pdev->irq, vmxnet3_intr, 0,
2105 adapter->netdev->name, adapter->netdev);
09c5088e 2106 } else {
115924b6 2107#endif
09c5088e 2108 adapter->num_rx_queues = 1;
d1a890fa
SB		 2109 err = request_irq(adapter->pdev->irq, vmxnet3_intr,
2110 IRQF_SHARED, adapter->netdev->name,
2111 adapter->netdev);
09c5088e 2112#ifdef CONFIG_PCI_MSI
d1a890fa 2113 }
09c5088e
SB		 2114#endif
2115 intr->num_intrs = vector + 1;
2116 if (err) {
204a6e65
SH		 2117 netdev_err(adapter->netdev,
2118 "Failed to request irq (intr type:%d), error %d\n",
2119 intr->type, err);
09c5088e
SB		 2120 } else {
2121 /* Number of rx queues will not change after this */
2122 for (i = 0; i < adapter->num_rx_queues; i++) {
2123 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
2124 rq->qid = i;
2125 rq->qid2 = i + adapter->num_rx_queues;
50a5ce3e 2126 rq->dataRingQid = i + 2 * adapter->num_rx_queues;
09c5088e 2127 }
d1a890fa 2128
09c5088e
SB		 2129 /* init our intr settings */
2130 for (i = 0; i < intr->num_intrs; i++)
2131 intr->mod_levels[i] = UPT1_IML_ADAPTIVE;
2132 if (adapter->intr.type != VMXNET3_IT_MSIX) {
2133 adapter->intr.event_intr_idx = 0;
2134 for (i = 0; i < adapter->num_tx_queues; i++)
2135 adapter->tx_queue[i].comp_ring.intr_idx = 0;
2136 adapter->rx_queue[0].comp_ring.intr_idx = 0;
2137 }
d1a890fa 2138
204a6e65
SH		 2139 netdev_info(adapter->netdev,
2140 "intr type %u, mode %u, %u vectors allocated\n",
2141 intr->type, intr->mask_mode, intr->num_intrs);
d1a890fa
SB		 2142 }
2143
2144 return err;
2145}
2146
2147
2148static void
2149vmxnet3_free_irqs(struct vmxnet3_adapter *adapter)
2150{
09c5088e
SB		 2151 struct vmxnet3_intr *intr = &adapter->intr;
2152 BUG_ON(intr->type == VMXNET3_IT_AUTO || intr->num_intrs <= 0);
d1a890fa 2153
09c5088e 2154 switch (intr->type) {
8f7e524c 2155#ifdef CONFIG_PCI_MSI
d1a890fa
SB		 2156 case VMXNET3_IT_MSIX:
2157 {
09c5088e 2158 int i, vector = 0;
d1a890fa 2159
09c5088e
SB		 2160 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE) {
2161 for (i = 0; i < adapter->num_tx_queues; i++) {
2162 free_irq(intr->msix_entries[vector++].vector,
2163 &(adapter->tx_queue[i]));
2164 if (adapter->share_intr == VMXNET3_INTR_TXSHARE)
2165 break;
2166 }
2167 }
2168
2169 for (i = 0; i < adapter->num_rx_queues; i++) {
2170 free_irq(intr->msix_entries[vector++].vector,
2171 &(adapter->rx_queue[i]));
2172 }
2173
2174 free_irq(intr->msix_entries[vector].vector,
2175 adapter->netdev);
2176 BUG_ON(vector >= intr->num_intrs);
d1a890fa
SB		 2177 break;
2178 }
8f7e524c 2179#endif
d1a890fa
SB		 2180 case VMXNET3_IT_MSI:
2181 free_irq(adapter->pdev->irq, adapter->netdev);
2182 break;
2183 case VMXNET3_IT_INTX:
2184 free_irq(adapter->pdev->irq, adapter->netdev);
2185 break;
2186 default:
c068e777 2187 BUG();
d1a890fa
SB		 2188 }
2189}
2190
d1a890fa
SB		 2191
2192static void
2193vmxnet3_restore_vlan(struct vmxnet3_adapter *adapter)
2194{
72e85c45
JG		 2195 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
2196 u16 vid;
d1a890fa 2197
72e85c45
JG		 2198 /* allow untagged pkts */
2199 VMXNET3_SET_VFTABLE_ENTRY(vfTable, 0);
2200
2201 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
2202 VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid);
d1a890fa
SB		 2203}
2204
2205
8e586137 2206static int
80d5c368 2207vmxnet3_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, u16 vid)
d1a890fa
SB		 2208{
2209 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
d1a890fa 2210
f6957f88
JG		 2211 if (!(netdev->flags & IFF_PROMISC)) {
2212 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
2213 unsigned long flags;
2214
2215 VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid);
2216 spin_lock_irqsave(&adapter->cmd_lock, flags);
2217 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2218 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
2219 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2220 }
72e85c45
JG		 2221
2222 set_bit(vid, adapter->active_vlans);
8e586137
JP		 2223
2224 return 0;
d1a890fa
SB		 2225}
2226
2227
8e586137 2228static int
80d5c368 2229vmxnet3_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, u16 vid)
d1a890fa
SB		 2230{
2231 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
d1a890fa 2232
f6957f88
JG		 2233 if (!(netdev->flags & IFF_PROMISC)) {
2234 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
2235 unsigned long flags;
2236
2237 VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid);
2238 spin_lock_irqsave(&adapter->cmd_lock, flags);
2239 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2240 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
2241 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2242 }
72e85c45
JG		 2243
2244 clear_bit(vid, adapter->active_vlans);
8e586137
JP		 2245
2246 return 0;
d1a890fa
SB		 2247}
2248
2249
2250static u8 *
2251vmxnet3_copy_mc(struct net_device *netdev)
2252{
2253 u8 *buf = NULL;
4cd24eaf 2254 u32 sz = netdev_mc_count(netdev) * ETH_ALEN;
d1a890fa
SB		 2255
2256 /* struct Vmxnet3_RxFilterConf.mfTableLen is u16. */
2257 if (sz <= 0xffff) {
2258 /* We may be called with BH disabled */
2259 buf = kmalloc(sz, GFP_ATOMIC);
2260 if (buf) {
22bedad3 2261 struct netdev_hw_addr *ha;
567ec874 2262 int i = 0;
d1a890fa 2263
22bedad3
JP		 2264 netdev_for_each_mc_addr(ha, netdev)
2265 memcpy(buf + i++ * ETH_ALEN, ha->addr,
d1a890fa 2266 ETH_ALEN);
d1a890fa
SB		 2267 }
2268 }
2269 return buf;
2270}
2271
2272
2273static void
2274vmxnet3_set_mc(struct net_device *netdev)
2275{
2276 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
83d0feff 2277 unsigned long flags;
d1a890fa
SB		 2278 struct Vmxnet3_RxFilterConf *rxConf =
2279 &adapter->shared->devRead.rxFilterConf;
2280 u8 *new_table = NULL;
b0eb57cb 2281 dma_addr_t new_table_pa = 0;
fb5c6cfa 2282 bool new_table_pa_valid = false;
d1a890fa
SB		 2283 u32 new_mode = VMXNET3_RXM_UCAST;
2284
72e85c45
JG		 2285 if (netdev->flags & IFF_PROMISC) {
2286 u32 *vfTable = adapter->shared->devRead.rxFilterConf.vfTable;
2287 memset(vfTable, 0, VMXNET3_VFT_SIZE * sizeof(*vfTable));
2288
d1a890fa 2289 new_mode |= VMXNET3_RXM_PROMISC;
72e85c45
JG		 2290 } else {
2291 vmxnet3_restore_vlan(adapter);
2292 }
d1a890fa
SB		 2293
2294 if (netdev->flags & IFF_BROADCAST)
2295 new_mode |= VMXNET3_RXM_BCAST;
2296
2297 if (netdev->flags & IFF_ALLMULTI)
2298 new_mode |= VMXNET3_RXM_ALL_MULTI;
2299 else
4cd24eaf 2300 if (!netdev_mc_empty(netdev)) {
d1a890fa
SB		 2301 new_table = vmxnet3_copy_mc(netdev);
2302 if (new_table) {
d37d5ec8
SK		 2303 size_t sz = netdev_mc_count(netdev) * ETH_ALEN;
2304
2305 rxConf->mfTableLen = cpu_to_le16(sz);
b0eb57cb
AK		 2306 new_table_pa = dma_map_single(
2307 &adapter->pdev->dev,
2308 new_table,
d37d5ec8 2309 sz,
b0eb57cb 2310 PCI_DMA_TODEVICE);
fb5c6cfa
AK		 2311 if (!dma_mapping_error(&adapter->pdev->dev,
2312 new_table_pa)) {
2313 new_mode |= VMXNET3_RXM_MCAST;
2314 new_table_pa_valid = true;
2315 rxConf->mfTablePA = cpu_to_le64(
2316 new_table_pa);
2317 }
4ad9a64f 2318 }
fb5c6cfa 2319 if (!new_table_pa_valid) {
4ad9a64f
AK		 2320 netdev_info(netdev,
2321 "failed to copy mcast list, setting ALL_MULTI\n");
d1a890fa
SB		 2322 new_mode |= VMXNET3_RXM_ALL_MULTI;
2323 }
2324 }
2325
d1a890fa
SB		 2326 if (!(new_mode & VMXNET3_RXM_MCAST)) {
2327 rxConf->mfTableLen = 0;
2328 rxConf->mfTablePA = 0;
2329 }
2330
83d0feff 2331 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa 2332 if (new_mode != rxConf->rxMode) {
115924b6 2333 rxConf->rxMode = cpu_to_le32(new_mode);
d1a890fa
SB		 2334 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2335 VMXNET3_CMD_UPDATE_RX_MODE);
72e85c45
JG		 2336 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2337 VMXNET3_CMD_UPDATE_VLAN_FILTERS);
d1a890fa
SB		 2338 }
2339
2340 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2341 VMXNET3_CMD_UPDATE_MAC_FILTERS);
83d0feff 2342 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
d1a890fa 2343
fb5c6cfa 2344 if (new_table_pa_valid)
b0eb57cb
AK		 2345 dma_unmap_single(&adapter->pdev->dev, new_table_pa,
2346 rxConf->mfTableLen, PCI_DMA_TODEVICE);
4ad9a64f 2347 kfree(new_table);
d1a890fa
SB		 2348}
2349
09c5088e
SB		 2350void
2351vmxnet3_rq_destroy_all(struct vmxnet3_adapter *adapter)
2352{
2353 int i;
2354
2355 for (i = 0; i < adapter->num_rx_queues; i++)
2356 vmxnet3_rq_destroy(&adapter->rx_queue[i], adapter);
2357}
2358
d1a890fa
SB		 2359
2360/*
2361 * Set up driver_shared based on settings in adapter.
2362 */
2363
2364static void
2365vmxnet3_setup_driver_shared(struct vmxnet3_adapter *adapter)
2366{
2367 struct Vmxnet3_DriverShared *shared = adapter->shared;
2368 struct Vmxnet3_DSDevRead *devRead = &shared->devRead;
2369 struct Vmxnet3_TxQueueConf *tqc;
2370 struct Vmxnet3_RxQueueConf *rqc;
2371 int i;
2372
2373 memset(shared, 0, sizeof(*shared));
2374
2375 /* driver settings */
115924b6
SB		 2376 shared->magic = cpu_to_le32(VMXNET3_REV1_MAGIC);
2377 devRead->misc.driverInfo.version = cpu_to_le32(
2378 VMXNET3_DRIVER_VERSION_NUM);
d1a890fa
SB		 2379 devRead->misc.driverInfo.gos.gosBits = (sizeof(void *) == 4 ?
2380 VMXNET3_GOS_BITS_32 : VMXNET3_GOS_BITS_64);
2381 devRead->misc.driverInfo.gos.gosType = VMXNET3_GOS_TYPE_LINUX;
115924b6
SB		 2382 *((u32 *)&devRead->misc.driverInfo.gos) = cpu_to_le32(
2383 *((u32 *)&devRead->misc.driverInfo.gos));
2384 devRead->misc.driverInfo.vmxnet3RevSpt = cpu_to_le32(1);
2385 devRead->misc.driverInfo.uptVerSpt = cpu_to_le32(1);
d1a890fa 2386
b0eb57cb 2387 devRead->misc.ddPA = cpu_to_le64(adapter->adapter_pa);
115924b6 2388 devRead->misc.ddLen = cpu_to_le32(sizeof(struct vmxnet3_adapter));
d1a890fa
SB		 2389
2390 /* set up feature flags */
a0d2730c 2391 if (adapter->netdev->features & NETIF_F_RXCSUM)
3843e515 2392 devRead->misc.uptFeatures |= UPT1_F_RXCSUM;
d1a890fa 2393
a0d2730c 2394 if (adapter->netdev->features & NETIF_F_LRO) {
3843e515 2395 devRead->misc.uptFeatures |= UPT1_F_LRO;
115924b6 2396 devRead->misc.maxNumRxSG = cpu_to_le16(1 + MAX_SKB_FRAGS);
d1a890fa 2397 }
f646968f 2398 if (adapter->netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
3843e515 2399 devRead->misc.uptFeatures |= UPT1_F_RXVLAN;
d1a890fa 2400
115924b6
SB		 2401 devRead->misc.mtu = cpu_to_le32(adapter->netdev->mtu);
2402 devRead->misc.queueDescPA = cpu_to_le64(adapter->queue_desc_pa);
2403 devRead->misc.queueDescLen = cpu_to_le32(
09c5088e
SB		 2404 adapter->num_tx_queues * sizeof(struct Vmxnet3_TxQueueDesc) +
2405 adapter->num_rx_queues * sizeof(struct Vmxnet3_RxQueueDesc));
d1a890fa
SB		 2406
2407 /* tx queue settings */
09c5088e
SB		 2408 devRead->misc.numTxQueues = adapter->num_tx_queues;
2409 for (i = 0; i < adapter->num_tx_queues; i++) {
2410 struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i];
2411 BUG_ON(adapter->tx_queue[i].tx_ring.base == NULL);
2412 tqc = &adapter->tqd_start[i].conf;
2413 tqc->txRingBasePA = cpu_to_le64(tq->tx_ring.basePA);
2414 tqc->dataRingBasePA = cpu_to_le64(tq->data_ring.basePA);
2415 tqc->compRingBasePA = cpu_to_le64(tq->comp_ring.basePA);
b0eb57cb 2416 tqc->ddPA = cpu_to_le64(tq->buf_info_pa);
09c5088e
SB		 2417 tqc->txRingSize = cpu_to_le32(tq->tx_ring.size);
2418 tqc->dataRingSize = cpu_to_le32(tq->data_ring.size);
3c8b3efc 2419 tqc->txDataRingDescSize = cpu_to_le32(tq->txdata_desc_size);
09c5088e
SB		 2420 tqc->compRingSize = cpu_to_le32(tq->comp_ring.size);
2421 tqc->ddLen = cpu_to_le32(
2422 sizeof(struct vmxnet3_tx_buf_info) *
2423 tqc->txRingSize);
2424 tqc->intrIdx = tq->comp_ring.intr_idx;
2425 }
d1a890fa
SB		 2426
2427 /* rx queue settings */
09c5088e
SB		 2428 devRead->misc.numRxQueues = adapter->num_rx_queues;
2429 for (i = 0; i < adapter->num_rx_queues; i++) {
2430 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
2431 rqc = &adapter->rqd_start[i].conf;
2432 rqc->rxRingBasePA[0] = cpu_to_le64(rq->rx_ring[0].basePA);
2433 rqc->rxRingBasePA[1] = cpu_to_le64(rq->rx_ring[1].basePA);
2434 rqc->compRingBasePA = cpu_to_le64(rq->comp_ring.basePA);
b0eb57cb 2435 rqc->ddPA = cpu_to_le64(rq->buf_info_pa);
09c5088e
SB		 2436 rqc->rxRingSize[0] = cpu_to_le32(rq->rx_ring[0].size);
2437 rqc->rxRingSize[1] = cpu_to_le32(rq->rx_ring[1].size);
2438 rqc->compRingSize = cpu_to_le32(rq->comp_ring.size);
2439 rqc->ddLen = cpu_to_le32(
2440 sizeof(struct vmxnet3_rx_buf_info) *
2441 (rqc->rxRingSize[0] +
2442 rqc->rxRingSize[1]));
2443 rqc->intrIdx = rq->comp_ring.intr_idx;
50a5ce3e
SK		 2444 if (VMXNET3_VERSION_GE_3(adapter)) {
2445 rqc->rxDataRingBasePA =
2446 cpu_to_le64(rq->data_ring.basePA);
2447 rqc->rxDataRingDescSize =
2448 cpu_to_le16(rq->data_ring.desc_size);
2449 }
09c5088e
SB		 2450 }
2451
2452#ifdef VMXNET3_RSS
2453 memset(adapter->rss_conf, 0, sizeof(*adapter->rss_conf));
2454
2455 if (adapter->rss) {
2456 struct UPT1_RSSConf *rssConf = adapter->rss_conf;
66d35910 2457
09c5088e
SB		 2458 devRead->misc.uptFeatures |= UPT1_F_RSS;
2459 devRead->misc.numRxQueues = adapter->num_rx_queues;
2460 rssConf->hashType = UPT1_RSS_HASH_TYPE_TCP_IPV4 |
2461 UPT1_RSS_HASH_TYPE_IPV4 |
2462 UPT1_RSS_HASH_TYPE_TCP_IPV6 |
2463 UPT1_RSS_HASH_TYPE_IPV6;
2464 rssConf->hashFunc = UPT1_RSS_HASH_FUNC_TOEPLITZ;
2465 rssConf->hashKeySize = UPT1_RSS_MAX_KEY_SIZE;
2466 rssConf->indTableSize = VMXNET3_RSS_IND_TABLE_SIZE;
6bf79cdd 2467 netdev_rss_key_fill(rssConf->hashKey, sizeof(rssConf->hashKey));
66d35910 2468
09c5088e 2469 for (i = 0; i < rssConf->indTableSize; i++)
278bc429
BH		 2470 rssConf->indTable[i] = ethtool_rxfh_indir_default(
2471 i, adapter->num_rx_queues);
09c5088e
SB		 2472
2473 devRead->rssConfDesc.confVer = 1;
b0eb57cb
AK		 2474 devRead->rssConfDesc.confLen = cpu_to_le32(sizeof(*rssConf));
2475 devRead->rssConfDesc.confPA =
2476 cpu_to_le64(adapter->rss_conf_pa);
09c5088e
SB		 2477 }
2478
2479#endif /* VMXNET3_RSS */
d1a890fa
SB		 2480
2481 /* intr settings */
2482 devRead->intrConf.autoMask = adapter->intr.mask_mode ==
2483 VMXNET3_IMM_AUTO;
2484 devRead->intrConf.numIntrs = adapter->intr.num_intrs;
2485 for (i = 0; i < adapter->intr.num_intrs; i++)
2486 devRead->intrConf.modLevels[i] = adapter->intr.mod_levels[i];
2487
2488 devRead->intrConf.eventIntrIdx = adapter->intr.event_intr_idx;
6929fe8a 2489 devRead->intrConf.intrCtrl |= cpu_to_le32(VMXNET3_IC_DISABLE_ALL);
d1a890fa
SB		 2490
2491 /* rx filter settings */
2492 devRead->rxFilterConf.rxMode = 0;
2493 vmxnet3_restore_vlan(adapter);
f9f25026
SB		 2494 vmxnet3_write_mac_addr(adapter, adapter->netdev->dev_addr);
2495
d1a890fa
SB		 2496 /* the rest are already zeroed */
2497}
2498
4edef40e
SK		 2499static void
2500vmxnet3_init_coalesce(struct vmxnet3_adapter *adapter)
2501{
2502 struct Vmxnet3_DriverShared *shared = adapter->shared;
2503 union Vmxnet3_CmdInfo *cmdInfo = &shared->cu.cmdInfo;
2504 unsigned long flags;
2505
2506 if (!VMXNET3_VERSION_GE_3(adapter))
2507 return;
2508
2509 spin_lock_irqsave(&adapter->cmd_lock, flags);
2510 cmdInfo->varConf.confVer = 1;
2511 cmdInfo->varConf.confLen =
2512 cpu_to_le32(sizeof(*adapter->coal_conf));
2513 cmdInfo->varConf.confPA = cpu_to_le64(adapter->coal_conf_pa);
2514
2515 if (adapter->default_coal_mode) {
2516 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2517 VMXNET3_CMD_GET_COALESCE);
2518 } else {
2519 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2520 VMXNET3_CMD_SET_COALESCE);
2521 }
2522
2523 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2524}
d1a890fa
SB		 2525
2526int
2527vmxnet3_activate_dev(struct vmxnet3_adapter *adapter)
2528{
09c5088e 2529 int err, i;
d1a890fa 2530 u32 ret;
83d0feff 2531 unsigned long flags;
d1a890fa 2532
fdcd79b9 2533 netdev_dbg(adapter->netdev, "%s: skb_buf_size %d, rx_buf_per_pkt %d,"
09c5088e
SB		 2534 " ring sizes %u %u %u\n", adapter->netdev->name,
2535 adapter->skb_buf_size, adapter->rx_buf_per_pkt,
2536 adapter->tx_queue[0].tx_ring.size,
2537 adapter->rx_queue[0].rx_ring[0].size,
2538 adapter->rx_queue[0].rx_ring[1].size);
2539
2540 vmxnet3_tq_init_all(adapter);
2541 err = vmxnet3_rq_init_all(adapter);
d1a890fa 2542 if (err) {
204a6e65
SH		 2543 netdev_err(adapter->netdev,
2544 "Failed to init rx queue error %d\n", err);
d1a890fa
SB		 2545 goto rq_err;
2546 }
2547
2548 err = vmxnet3_request_irqs(adapter);
2549 if (err) {
204a6e65
SH		 2550 netdev_err(adapter->netdev,
2551 "Failed to setup irq for error %d\n", err);
d1a890fa
SB		 2552 goto irq_err;
2553 }
2554
2555 vmxnet3_setup_driver_shared(adapter);
2556
115924b6
SB		 2557 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, VMXNET3_GET_ADDR_LO(
2558 adapter->shared_pa));
2559 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, VMXNET3_GET_ADDR_HI(
2560 adapter->shared_pa));
83d0feff 2561 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa
SB		 2562 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2563 VMXNET3_CMD_ACTIVATE_DEV);
2564 ret = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
83d0feff 2565 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
d1a890fa
SB		 2566
2567 if (ret != 0) {
204a6e65
SH		 2568 netdev_err(adapter->netdev,
2569 "Failed to activate dev: error %u\n", ret);
d1a890fa
SB		 2570 err = -EINVAL;
2571 goto activate_err;
2572 }
09c5088e 2573
4edef40e
SK		 2574 vmxnet3_init_coalesce(adapter);
2575
09c5088e
SB		 2576 for (i = 0; i < adapter->num_rx_queues; i++) {
2577 VMXNET3_WRITE_BAR0_REG(adapter,
2578 VMXNET3_REG_RXPROD + i * VMXNET3_REG_ALIGN,
2579 adapter->rx_queue[i].rx_ring[0].next2fill);
2580 VMXNET3_WRITE_BAR0_REG(adapter, (VMXNET3_REG_RXPROD2 +
2581 (i * VMXNET3_REG_ALIGN)),
2582 adapter->rx_queue[i].rx_ring[1].next2fill);
2583 }
d1a890fa
SB		 2584
2585 /* Apply the rx filter settins last. */
2586 vmxnet3_set_mc(adapter->netdev);
2587
2588 /*
2589 * Check link state when first activating device. It will start the
2590 * tx queue if the link is up.
2591 */
4a1745fc 2592 vmxnet3_check_link(adapter, true);
09c5088e
SB		 2593 for (i = 0; i < adapter->num_rx_queues; i++)
2594 napi_enable(&adapter->rx_queue[i].napi);
d1a890fa
SB		 2595 vmxnet3_enable_all_intrs(adapter);
2596 clear_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state);
2597 return 0;
2598
2599activate_err:
2600 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAL, 0);
2601 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_DSAH, 0);
2602 vmxnet3_free_irqs(adapter);
2603irq_err:
2604rq_err:
2605 /* free up buffers we allocated */
09c5088e 2606 vmxnet3_rq_cleanup_all(adapter);
d1a890fa
SB		 2607 return err;
2608}
2609
2610
2611void
2612vmxnet3_reset_dev(struct vmxnet3_adapter *adapter)
2613{
83d0feff
SB		 2614 unsigned long flags;
2615 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa 2616 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD, VMXNET3_CMD_RESET_DEV);
83d0feff 2617 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
d1a890fa
SB		 2618}
2619
2620
2621int
2622vmxnet3_quiesce_dev(struct vmxnet3_adapter *adapter)
2623{
09c5088e 2624 int i;
83d0feff 2625 unsigned long flags;
d1a890fa
SB		 2626 if (test_and_set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state))
2627 return 0;
2628
2629
83d0feff 2630 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa
SB		 2631 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2632 VMXNET3_CMD_QUIESCE_DEV);
83d0feff 2633 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
d1a890fa
SB		 2634 vmxnet3_disable_all_intrs(adapter);
2635
09c5088e
SB		 2636 for (i = 0; i < adapter->num_rx_queues; i++)
2637 napi_disable(&adapter->rx_queue[i].napi);
d1a890fa
SB		 2638 netif_tx_disable(adapter->netdev);
2639 adapter->link_speed = 0;
2640 netif_carrier_off(adapter->netdev);
2641
09c5088e
SB		 2642 vmxnet3_tq_cleanup_all(adapter);
2643 vmxnet3_rq_cleanup_all(adapter);
d1a890fa
SB		 2644 vmxnet3_free_irqs(adapter);
2645 return 0;
2646}
2647
2648
2649static void
2650vmxnet3_write_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac)
2651{
2652 u32 tmp;
2653
2654 tmp = *(u32 *)mac;
2655 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACL, tmp);
2656
2657 tmp = (mac[5] << 8) | mac[4];
2658 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_MACH, tmp);
2659}
2660
2661
2662static int
2663vmxnet3_set_mac_addr(struct net_device *netdev, void *p)
2664{
2665 struct sockaddr *addr = p;
2666 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2667
2668 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
2669 vmxnet3_write_mac_addr(adapter, addr->sa_data);
2670
2671 return 0;
2672}
2673
2674
2675/* ==================== initialization and cleanup routines ============ */
2676
2677static int
2678vmxnet3_alloc_pci_resources(struct vmxnet3_adapter *adapter, bool *dma64)
2679{
2680 int err;
2681 unsigned long mmio_start, mmio_len;
2682 struct pci_dev *pdev = adapter->pdev;
2683
2684 err = pci_enable_device(pdev);
2685 if (err) {
204a6e65 2686 dev_err(&pdev->dev, "Failed to enable adapter: error %d\n", err);
d1a890fa
SB		 2687 return err;
2688 }
2689
2690 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) == 0) {
2691 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) {
204a6e65
SH		 2692 dev_err(&pdev->dev,
2693 "pci_set_consistent_dma_mask failed\n");
d1a890fa
SB		 2694 err = -EIO;
2695 goto err_set_mask;
2696 }
2697 *dma64 = true;
2698 } else {
2699 if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) {
204a6e65
SH		 2700 dev_err(&pdev->dev,
2701 "pci_set_dma_mask failed\n");
d1a890fa
SB		 2702 err = -EIO;
2703 goto err_set_mask;
2704 }
2705 *dma64 = false;
2706 }
2707
2708 err = pci_request_selected_regions(pdev, (1 << 2) - 1,
2709 vmxnet3_driver_name);
2710 if (err) {
204a6e65
SH		 2711 dev_err(&pdev->dev,
2712 "Failed to request region for adapter: error %d\n", err);
d1a890fa
SB		 2713 goto err_set_mask;
2714 }
2715
2716 pci_set_master(pdev);
2717
2718 mmio_start = pci_resource_start(pdev, 0);
2719 mmio_len = pci_resource_len(pdev, 0);
2720 adapter->hw_addr0 = ioremap(mmio_start, mmio_len);
2721 if (!adapter->hw_addr0) {
204a6e65 2722 dev_err(&pdev->dev, "Failed to map bar0\n");
d1a890fa
SB		 2723 err = -EIO;
2724 goto err_ioremap;
2725 }
2726
2727 mmio_start = pci_resource_start(pdev, 1);
2728 mmio_len = pci_resource_len(pdev, 1);
2729 adapter->hw_addr1 = ioremap(mmio_start, mmio_len);
2730 if (!adapter->hw_addr1) {
204a6e65 2731 dev_err(&pdev->dev, "Failed to map bar1\n");
d1a890fa
SB		 2732 err = -EIO;
2733 goto err_bar1;
2734 }
2735 return 0;
2736
2737err_bar1:
2738 iounmap(adapter->hw_addr0);
2739err_ioremap:
2740 pci_release_selected_regions(pdev, (1 << 2) - 1);
2741err_set_mask:
2742 pci_disable_device(pdev);
2743 return err;
2744}
2745
2746
2747static void
2748vmxnet3_free_pci_resources(struct vmxnet3_adapter *adapter)
2749{
2750 BUG_ON(!adapter->pdev);
2751
2752 iounmap(adapter->hw_addr0);
2753 iounmap(adapter->hw_addr1);
2754 pci_release_selected_regions(adapter->pdev, (1 << 2) - 1);
2755 pci_disable_device(adapter->pdev);
2756}
2757
2758
2759static void
2760vmxnet3_adjust_rx_ring_size(struct vmxnet3_adapter *adapter)
2761{
09c5088e 2762 size_t sz, i, ring0_size, ring1_size, comp_size;
d1a890fa
SB		 2763 if (adapter->netdev->mtu <= VMXNET3_MAX_SKB_BUF_SIZE -
2764 VMXNET3_MAX_ETH_HDR_SIZE) {
2765 adapter->skb_buf_size = adapter->netdev->mtu +
2766 VMXNET3_MAX_ETH_HDR_SIZE;
2767 if (adapter->skb_buf_size < VMXNET3_MIN_T0_BUF_SIZE)
2768 adapter->skb_buf_size = VMXNET3_MIN_T0_BUF_SIZE;
2769
2770 adapter->rx_buf_per_pkt = 1;
2771 } else {
2772 adapter->skb_buf_size = VMXNET3_MAX_SKB_BUF_SIZE;
2773 sz = adapter->netdev->mtu - VMXNET3_MAX_SKB_BUF_SIZE +
2774 VMXNET3_MAX_ETH_HDR_SIZE;
2775 adapter->rx_buf_per_pkt = 1 + (sz + PAGE_SIZE - 1) / PAGE_SIZE;
2776 }
2777
2778 /*
2779 * for simplicity, force the ring0 size to be a multiple of
2780 * rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN
2781 */
2782 sz = adapter->rx_buf_per_pkt * VMXNET3_RING_SIZE_ALIGN;
09c5088e
SB		 2783 ring0_size = adapter->rx_queue[0].rx_ring[0].size;
2784 ring0_size = (ring0_size + sz - 1) / sz * sz;
a53255d3 2785 ring0_size = min_t(u32, ring0_size, VMXNET3_RX_RING_MAX_SIZE /
09c5088e
SB		 2786 sz * sz);
2787 ring1_size = adapter->rx_queue[0].rx_ring[1].size;
53831aa1
SK		 2788 ring1_size = (ring1_size + sz - 1) / sz * sz;
2789 ring1_size = min_t(u32, ring1_size, VMXNET3_RX_RING2_MAX_SIZE /
2790 sz * sz);
09c5088e
SB		 2791 comp_size = ring0_size + ring1_size;
2792
2793 for (i = 0; i < adapter->num_rx_queues; i++) {
5e264e2b
CIK		 2794 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
2795
09c5088e
SB		 2796 rq->rx_ring[0].size = ring0_size;
2797 rq->rx_ring[1].size = ring1_size;
2798 rq->comp_ring.size = comp_size;
2799 }
d1a890fa
SB		 2800}
2801
2802
2803int
2804vmxnet3_create_queues(struct vmxnet3_adapter *adapter, u32 tx_ring_size,
3c8b3efc 2805 u32 rx_ring_size, u32 rx_ring2_size,
50a5ce3e 2806 u16 txdata_desc_size, u16 rxdata_desc_size)
d1a890fa 2807{
09c5088e
SB		 2808 int err = 0, i;
2809
2810 for (i = 0; i < adapter->num_tx_queues; i++) {
2811 struct vmxnet3_tx_queue *tq = &adapter->tx_queue[i];
2812 tq->tx_ring.size = tx_ring_size;
2813 tq->data_ring.size = tx_ring_size;
2814 tq->comp_ring.size = tx_ring_size;
3c8b3efc 2815 tq->txdata_desc_size = txdata_desc_size;
09c5088e
SB		 2816 tq->shared = &adapter->tqd_start[i].ctrl;
2817 tq->stopped = true;
2818 tq->adapter = adapter;
2819 tq->qid = i;
2820 err = vmxnet3_tq_create(tq, adapter);
2821 /*
2822 * Too late to change num_tx_queues. We cannot do away with
2823 * lesser number of queues than what we asked for
2824 */
2825 if (err)
2826 goto queue_err;
2827 }
d1a890fa 2828
09c5088e
SB		 2829 adapter->rx_queue[0].rx_ring[0].size = rx_ring_size;
2830 adapter->rx_queue[0].rx_ring[1].size = rx_ring2_size;
d1a890fa 2831 vmxnet3_adjust_rx_ring_size(adapter);
50a5ce3e
SK		 2832
2833 adapter->rxdataring_enabled = VMXNET3_VERSION_GE_3(adapter);
09c5088e
SB		 2834 for (i = 0; i < adapter->num_rx_queues; i++) {
2835 struct vmxnet3_rx_queue *rq = &adapter->rx_queue[i];
2836 /* qid and qid2 for rx queues will be assigned later when num
2837 * of rx queues is finalized after allocating intrs */
2838 rq->shared = &adapter->rqd_start[i].ctrl;
2839 rq->adapter = adapter;
50a5ce3e 2840 rq->data_ring.desc_size = rxdata_desc_size;
09c5088e
SB		 2841 err = vmxnet3_rq_create(rq, adapter);
2842 if (err) {
2843 if (i == 0) {
204a6e65
SH		 2844 netdev_err(adapter->netdev,
2845 "Could not allocate any rx queues. "
2846 "Aborting.\n");
09c5088e
SB		 2847 goto queue_err;
2848 } else {
204a6e65
SH		 2849 netdev_info(adapter->netdev,
2850 "Number of rx queues changed "
2851 "to : %d.\n", i);
09c5088e
SB		 2852 adapter->num_rx_queues = i;
2853 err = 0;
2854 break;
2855 }
2856 }
2857 }
50a5ce3e
SK		 2858
2859 if (!adapter->rxdataring_enabled)
2860 vmxnet3_rq_destroy_all_rxdataring(adapter);
2861
09c5088e
SB		 2862 return err;
2863queue_err:
2864 vmxnet3_tq_destroy_all(adapter);
d1a890fa
SB		 2865 return err;
2866}
2867
2868static int
2869vmxnet3_open(struct net_device *netdev)
2870{
2871 struct vmxnet3_adapter *adapter;
09c5088e 2872 int err, i;
d1a890fa
SB		 2873
2874 adapter = netdev_priv(netdev);
2875
09c5088e
SB		 2876 for (i = 0; i < adapter->num_tx_queues; i++)
2877 spin_lock_init(&adapter->tx_queue[i].tx_lock);
d1a890fa 2878
3c8b3efc
SK		 2879 if (VMXNET3_VERSION_GE_3(adapter)) {
2880 unsigned long flags;
2881 u16 txdata_desc_size;
2882
2883 spin_lock_irqsave(&adapter->cmd_lock, flags);
2884 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
2885 VMXNET3_CMD_GET_TXDATA_DESC_SIZE);
2886 txdata_desc_size = VMXNET3_READ_BAR1_REG(adapter,
2887 VMXNET3_REG_CMD);
2888 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
2889
2890 if ((txdata_desc_size < VMXNET3_TXDATA_DESC_MIN_SIZE) ||
2891 (txdata_desc_size > VMXNET3_TXDATA_DESC_MAX_SIZE) ||
2892 (txdata_desc_size & VMXNET3_TXDATA_DESC_SIZE_MASK)) {
2893 adapter->txdata_desc_size =
2894 sizeof(struct Vmxnet3_TxDataDesc);
2895 } else {
2896 adapter->txdata_desc_size = txdata_desc_size;
2897 }
2898 } else {
2899 adapter->txdata_desc_size = sizeof(struct Vmxnet3_TxDataDesc);
2900 }
2901
2902 err = vmxnet3_create_queues(adapter,
2903 adapter->tx_ring_size,
f00e2b0a 2904 adapter->rx_ring_size,
3c8b3efc 2905 adapter->rx_ring2_size,
50a5ce3e
SK		 2906 adapter->txdata_desc_size,
2907 adapter->rxdata_desc_size);
d1a890fa
SB		 2908 if (err)
2909 goto queue_err;
2910
2911 err = vmxnet3_activate_dev(adapter);
2912 if (err)
2913 goto activate_err;
2914
2915 return 0;
2916
2917activate_err:
09c5088e
SB		 2918 vmxnet3_rq_destroy_all(adapter);
2919 vmxnet3_tq_destroy_all(adapter);
d1a890fa
SB		 2920queue_err:
2921 return err;
2922}
2923
2924
2925static int
2926vmxnet3_close(struct net_device *netdev)
2927{
2928 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2929
2930 /*
2931 * Reset_work may be in the middle of resetting the device, wait for its
2932 * completion.
2933 */
2934 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
2935 msleep(1);
2936
2937 vmxnet3_quiesce_dev(adapter);
2938
09c5088e
SB		 2939 vmxnet3_rq_destroy_all(adapter);
2940 vmxnet3_tq_destroy_all(adapter);
d1a890fa
SB		 2941
2942 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
2943
2944
2945 return 0;
2946}
2947
2948
2949void
2950vmxnet3_force_close(struct vmxnet3_adapter *adapter)
2951{
09c5088e
SB		 2952 int i;
2953
d1a890fa
SB		 2954 /*
2955 * we must clear VMXNET3_STATE_BIT_RESETTING, otherwise
2956 * vmxnet3_close() will deadlock.
2957 */
2958 BUG_ON(test_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state));
2959
2960 /* we need to enable NAPI, otherwise dev_close will deadlock */
09c5088e
SB		 2961 for (i = 0; i < adapter->num_rx_queues; i++)
2962 napi_enable(&adapter->rx_queue[i].napi);
1c4d5f51
NH		 2963 /*
2964 * Need to clear the quiesce bit to ensure that vmxnet3_close
2965 * can quiesce the device properly
2966 */
2967 clear_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state);
d1a890fa
SB		 2968 dev_close(adapter->netdev);
2969}
2970
2971
2972static int
2973vmxnet3_change_mtu(struct net_device *netdev, int new_mtu)
2974{
2975 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
2976 int err = 0;
2977
d1a890fa
SB		 2978 netdev->mtu = new_mtu;
2979
2980 /*
2981 * Reset_work may be in the middle of resetting the device, wait for its
2982 * completion.
2983 */
2984 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
2985 msleep(1);
2986
2987 if (netif_running(netdev)) {
2988 vmxnet3_quiesce_dev(adapter);
2989 vmxnet3_reset_dev(adapter);
2990
2991 /* we need to re-create the rx queue based on the new mtu */
09c5088e 2992 vmxnet3_rq_destroy_all(adapter);
d1a890fa 2993 vmxnet3_adjust_rx_ring_size(adapter);
09c5088e 2994 err = vmxnet3_rq_create_all(adapter);
d1a890fa 2995 if (err) {
204a6e65
SH		 2996 netdev_err(netdev,
2997 "failed to re-create rx queues, "
2998 " error %d. Closing it.\n", err);
d1a890fa
SB		 2999 goto out;
3000 }
3001
3002 err = vmxnet3_activate_dev(adapter);
3003 if (err) {
204a6e65
SH		 3004 netdev_err(netdev,
3005 "failed to re-activate, error %d. "
3006 "Closing it\n", err);
d1a890fa
SB		 3007 goto out;
3008 }
3009 }
3010
3011out:
3012 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
3013 if (err)
3014 vmxnet3_force_close(adapter);
3015
3016 return err;
3017}
3018
3019
3020static void
3021vmxnet3_declare_features(struct vmxnet3_adapter *adapter, bool dma64)
3022{
3023 struct net_device *netdev = adapter->netdev;
3024
a0d2730c 3025 netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM |
f646968f
PM		 3026 NETIF_F_HW_CSUM | NETIF_F_HW_VLAN_CTAG_TX |
3027 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_TSO | NETIF_F_TSO6 |
72e85c45 3028 NETIF_F_LRO;
a0d2730c 3029 if (dma64)
ebbf9295 3030 netdev->hw_features |= NETIF_F_HIGHDMA;
72e85c45 3031 netdev->vlan_features = netdev->hw_features &
f646968f
PM		 3032 ~(NETIF_F_HW_VLAN_CTAG_TX |
3033 NETIF_F_HW_VLAN_CTAG_RX);
3034 netdev->features = netdev->hw_features | NETIF_F_HW_VLAN_CTAG_FILTER;
d1a890fa
SB		 3035}
3036
3037
3038static void
3039vmxnet3_read_mac_addr(struct vmxnet3_adapter *adapter, u8 *mac)
3040{
3041 u32 tmp;
3042
3043 tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACL);
3044 *(u32 *)mac = tmp;
3045
3046 tmp = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_MACH);
3047 mac[4] = tmp & 0xff;
3048 mac[5] = (tmp >> 8) & 0xff;
3049}
3050
09c5088e
SB		 3051#ifdef CONFIG_PCI_MSI
3052
3053/*
3054 * Enable MSIx vectors.
3055 * Returns :
25985edc 3056 * VMXNET3_LINUX_MIN_MSIX_VECT when only minimum number of vectors required
b60b869d
AG		 3057 * were enabled.
3058 * number of vectors which were enabled otherwise (this number is greater
09c5088e
SB		 3059 * than VMXNET3_LINUX_MIN_MSIX_VECT)
3060 */
3061
3062static int
b60b869d 3063vmxnet3_acquire_msix_vectors(struct vmxnet3_adapter *adapter, int nvec)
09c5088e 3064{
c0a1be38
AG		 3065 int ret = pci_enable_msix_range(adapter->pdev,
3066 adapter->intr.msix_entries, nvec, nvec);
09c5088e 3067
c0a1be38
AG		 3068 if (ret == -ENOSPC && nvec > VMXNET3_LINUX_MIN_MSIX_VECT) {
3069 dev_err(&adapter->netdev->dev,
3070 "Failed to enable %d MSI-X, trying %d\n",
3071 nvec, VMXNET3_LINUX_MIN_MSIX_VECT);
3072
3073 ret = pci_enable_msix_range(adapter->pdev,
3074 adapter->intr.msix_entries,
3075 VMXNET3_LINUX_MIN_MSIX_VECT,
3076 VMXNET3_LINUX_MIN_MSIX_VECT);
3077 }
3078
3079 if (ret < 0) {
3080 dev_err(&adapter->netdev->dev,
3081 "Failed to enable MSI-X, error: %d\n", ret);
3082 }
3083
3084 return ret;
09c5088e
SB		 3085}
3086
3087
3088#endif /* CONFIG_PCI_MSI */
d1a890fa
SB		 3089
3090static void
3091vmxnet3_alloc_intr_resources(struct vmxnet3_adapter *adapter)
3092{
3093 u32 cfg;
e328d410 3094 unsigned long flags;
d1a890fa
SB		 3095
3096 /* intr settings */
e328d410 3097 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa
SB		 3098 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3099 VMXNET3_CMD_GET_CONF_INTR);
3100 cfg = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_CMD);
e328d410 3101 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
d1a890fa
SB		 3102 adapter->intr.type = cfg & 0x3;
3103 adapter->intr.mask_mode = (cfg >> 2) & 0x3;
3104
3105 if (adapter->intr.type == VMXNET3_IT_AUTO) {
0bdc0d70
SB		 3106 adapter->intr.type = VMXNET3_IT_MSIX;
3107 }
d1a890fa 3108
8f7e524c 3109#ifdef CONFIG_PCI_MSI
0bdc0d70 3110 if (adapter->intr.type == VMXNET3_IT_MSIX) {
b60b869d
AG		 3111 int i, nvec;
3112
3113 nvec = adapter->share_intr == VMXNET3_INTR_TXSHARE ?
3114 1 : adapter->num_tx_queues;
3115 nvec += adapter->share_intr == VMXNET3_INTR_BUDDYSHARE ?
3116 0 : adapter->num_rx_queues;
3117 nvec += 1; /* for link event */
3118 nvec = nvec > VMXNET3_LINUX_MIN_MSIX_VECT ?
3119 nvec : VMXNET3_LINUX_MIN_MSIX_VECT;
3120
3121 for (i = 0; i < nvec; i++)
3122 adapter->intr.msix_entries[i].entry = i;
3123
3124 nvec = vmxnet3_acquire_msix_vectors(adapter, nvec);
3125 if (nvec < 0)
3126 goto msix_err;
3127
09c5088e
SB		 3128 /* If we cannot allocate one MSIx vector per queue
3129 * then limit the number of rx queues to 1
3130 */
b60b869d 3131 if (nvec == VMXNET3_LINUX_MIN_MSIX_VECT) {
09c5088e 3132 if (adapter->share_intr != VMXNET3_INTR_BUDDYSHARE
7e96fbf2 3133 || adapter->num_rx_queues != 1) {
09c5088e 3134 adapter->share_intr = VMXNET3_INTR_TXSHARE;
204a6e65
SH		 3135 netdev_err(adapter->netdev,
3136 "Number of rx queues : 1\n");
09c5088e 3137 adapter->num_rx_queues = 1;
09c5088e 3138 }
d1a890fa 3139 }
09c5088e 3140
b60b869d
AG		 3141 adapter->intr.num_intrs = nvec;
3142 return;
3143
3144msix_err:
09c5088e 3145 /* If we cannot allocate MSIx vectors use only one rx queue */
4bad25fa
SH		 3146 dev_info(&adapter->pdev->dev,
3147 "Failed to enable MSI-X, error %d. "
b60b869d 3148 "Limiting #rx queues to 1, try MSI.\n", nvec);
09c5088e 3149
0bdc0d70
SB		 3150 adapter->intr.type = VMXNET3_IT_MSI;
3151 }
d1a890fa 3152
0bdc0d70 3153 if (adapter->intr.type == VMXNET3_IT_MSI) {
b60b869d 3154 if (!pci_enable_msi(adapter->pdev)) {
09c5088e 3155 adapter->num_rx_queues = 1;
d1a890fa 3156 adapter->intr.num_intrs = 1;
d1a890fa
SB		 3157 return;
3158 }
3159 }
0bdc0d70 3160#endif /* CONFIG_PCI_MSI */
d1a890fa 3161
09c5088e 3162 adapter->num_rx_queues = 1;
204a6e65
SH		 3163 dev_info(&adapter->netdev->dev,
3164 "Using INTx interrupt, #Rx queues: 1.\n");
d1a890fa
SB		 3165 adapter->intr.type = VMXNET3_IT_INTX;
3166
3167 /* INT-X related setting */
3168 adapter->intr.num_intrs = 1;
3169}
3170
3171
3172static void
3173vmxnet3_free_intr_resources(struct vmxnet3_adapter *adapter)
3174{
3175 if (adapter->intr.type == VMXNET3_IT_MSIX)
3176 pci_disable_msix(adapter->pdev);
3177 else if (adapter->intr.type == VMXNET3_IT_MSI)
3178 pci_disable_msi(adapter->pdev);
3179 else
3180 BUG_ON(adapter->intr.type != VMXNET3_IT_INTX);
3181}
3182
3183
3184static void
3185vmxnet3_tx_timeout(struct net_device *netdev)
3186{
3187 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3188 adapter->tx_timeout_count++;
3189
204a6e65 3190 netdev_err(adapter->netdev, "tx hang\n");
d1a890fa
SB		 3191 schedule_work(&adapter->work);
3192}
3193
3194
3195static void
3196vmxnet3_reset_work(struct work_struct *data)
3197{
3198 struct vmxnet3_adapter *adapter;
3199
3200 adapter = container_of(data, struct vmxnet3_adapter, work);
3201
3202 /* if another thread is resetting the device, no need to proceed */
3203 if (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
3204 return;
3205
3206 /* if the device is closed, we must leave it alone */
d9a5f210 3207 rtnl_lock();
d1a890fa 3208 if (netif_running(adapter->netdev)) {
204a6e65 3209 netdev_notice(adapter->netdev, "resetting\n");
d1a890fa
SB		 3210 vmxnet3_quiesce_dev(adapter);
3211 vmxnet3_reset_dev(adapter);
3212 vmxnet3_activate_dev(adapter);
3213 } else {
204a6e65 3214 netdev_info(adapter->netdev, "already closed\n");
d1a890fa 3215 }
d9a5f210 3216 rtnl_unlock();
d1a890fa 3217
277964e1 3218 netif_wake_queue(adapter->netdev);
d1a890fa
SB		 3219 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
3220}
3221
3222
3a4751a3 3223static int
d1a890fa
SB		 3224vmxnet3_probe_device(struct pci_dev *pdev,
3225 const struct pci_device_id *id)
3226{
3227 static const struct net_device_ops vmxnet3_netdev_ops = {
3228 .ndo_open = vmxnet3_open,
3229 .ndo_stop = vmxnet3_close,
3230 .ndo_start_xmit = vmxnet3_xmit_frame,
3231 .ndo_set_mac_address = vmxnet3_set_mac_addr,
3232 .ndo_change_mtu = vmxnet3_change_mtu,
a0d2730c 3233 .ndo_set_features = vmxnet3_set_features,
95305f6c 3234 .ndo_get_stats64 = vmxnet3_get_stats64,
d1a890fa 3235 .ndo_tx_timeout = vmxnet3_tx_timeout,
afc4b13d 3236 .ndo_set_rx_mode = vmxnet3_set_mc,
d1a890fa
SB		 3237 .ndo_vlan_rx_add_vid = vmxnet3_vlan_rx_add_vid,
3238 .ndo_vlan_rx_kill_vid = vmxnet3_vlan_rx_kill_vid,
3239#ifdef CONFIG_NET_POLL_CONTROLLER
3240 .ndo_poll_controller = vmxnet3_netpoll,
3241#endif
3242 };
3243 int err;
3244 bool dma64 = false; /* stupid gcc */
3245 u32 ver;
3246 struct net_device *netdev;
3247 struct vmxnet3_adapter *adapter;
3248 u8 mac[ETH_ALEN];
09c5088e
SB		 3249 int size;
3250 int num_tx_queues;
3251 int num_rx_queues;
3252
e154b639
SB		 3253 if (!pci_msi_enabled())
3254 enable_mq = 0;
3255
09c5088e
SB		 3256#ifdef VMXNET3_RSS
3257 if (enable_mq)
3258 num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES,
3259 (int)num_online_cpus());
3260 else
3261#endif
3262 num_rx_queues = 1;
eebb02b1 3263 num_rx_queues = rounddown_pow_of_two(num_rx_queues);
09c5088e
SB		 3264
3265 if (enable_mq)
3266 num_tx_queues = min(VMXNET3_DEVICE_MAX_TX_QUEUES,
3267 (int)num_online_cpus());
3268 else
3269 num_tx_queues = 1;
3270
eebb02b1 3271 num_tx_queues = rounddown_pow_of_two(num_tx_queues);
09c5088e
SB		 3272 netdev = alloc_etherdev_mq(sizeof(struct vmxnet3_adapter),
3273 max(num_tx_queues, num_rx_queues));
204a6e65
SH		 3274 dev_info(&pdev->dev,
3275 "# of Tx queues : %d, # of Rx queues : %d\n",
3276 num_tx_queues, num_rx_queues);
d1a890fa 3277
41de8d4c 3278 if (!netdev)
d1a890fa 3279 return -ENOMEM;
d1a890fa
SB		 3280
3281 pci_set_drvdata(pdev, netdev);
3282 adapter = netdev_priv(netdev);
3283 adapter->netdev = netdev;
3284 adapter->pdev = pdev;
3285
f00e2b0a
NH		 3286 adapter->tx_ring_size = VMXNET3_DEF_TX_RING_SIZE;
3287 adapter->rx_ring_size = VMXNET3_DEF_RX_RING_SIZE;
53831aa1 3288 adapter->rx_ring2_size = VMXNET3_DEF_RX_RING2_SIZE;
f00e2b0a 3289
83d0feff 3290 spin_lock_init(&adapter->cmd_lock);
b0eb57cb
AK		 3291 adapter->adapter_pa = dma_map_single(&adapter->pdev->dev, adapter,
3292 sizeof(struct vmxnet3_adapter),
3293 PCI_DMA_TODEVICE);
5738a09d
AK		 3294 if (dma_mapping_error(&adapter->pdev->dev, adapter->adapter_pa)) {
3295 dev_err(&pdev->dev, "Failed to map dma\n");
3296 err = -EFAULT;
3297 goto err_dma_map;
3298 }
b0eb57cb
AK		 3299 adapter->shared = dma_alloc_coherent(
3300 &adapter->pdev->dev,
3301 sizeof(struct Vmxnet3_DriverShared),
3302 &adapter->shared_pa, GFP_KERNEL);
d1a890fa 3303 if (!adapter->shared) {
204a6e65 3304 dev_err(&pdev->dev, "Failed to allocate memory\n");
d1a890fa
SB		 3305 err = -ENOMEM;
3306 goto err_alloc_shared;
3307 }
3308
09c5088e
SB		 3309 adapter->num_rx_queues = num_rx_queues;
3310 adapter->num_tx_queues = num_tx_queues;
e4fabf2b 3311 adapter->rx_buf_per_pkt = 1;
09c5088e
SB		 3312
3313 size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues;
3314 size += sizeof(struct Vmxnet3_RxQueueDesc) * adapter->num_rx_queues;
b0eb57cb
AK		 3315 adapter->tqd_start = dma_alloc_coherent(&adapter->pdev->dev, size,
3316 &adapter->queue_desc_pa,
3317 GFP_KERNEL);
d1a890fa
SB		 3318
3319 if (!adapter->tqd_start) {
204a6e65 3320 dev_err(&pdev->dev, "Failed to allocate memory\n");
d1a890fa
SB		 3321 err = -ENOMEM;
3322 goto err_alloc_queue_desc;
3323 }
09c5088e 3324 adapter->rqd_start = (struct Vmxnet3_RxQueueDesc *)(adapter->tqd_start +
96800ee7 3325 adapter->num_tx_queues);
d1a890fa 3326
b0eb57cb
AK		 3327 adapter->pm_conf = dma_alloc_coherent(&adapter->pdev->dev,
3328 sizeof(struct Vmxnet3_PMConf),
3329 &adapter->pm_conf_pa,
3330 GFP_KERNEL);
d1a890fa 3331 if (adapter->pm_conf == NULL) {
d1a890fa
SB		 3332 err = -ENOMEM;
3333 goto err_alloc_pm;
3334 }
3335
09c5088e
SB		 3336#ifdef VMXNET3_RSS
3337
b0eb57cb
AK		 3338 adapter->rss_conf = dma_alloc_coherent(&adapter->pdev->dev,
3339 sizeof(struct UPT1_RSSConf),
3340 &adapter->rss_conf_pa,
3341 GFP_KERNEL);
09c5088e 3342 if (adapter->rss_conf == NULL) {
09c5088e
SB		 3343 err = -ENOMEM;
3344 goto err_alloc_rss;
3345 }
3346#endif /* VMXNET3_RSS */
3347
d1a890fa
SB		 3348 err = vmxnet3_alloc_pci_resources(adapter, &dma64);
3349 if (err < 0)
3350 goto err_alloc_pci;
3351
3352 ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_VRRS);
6af9d787
SK		 3353 if (ver & (1 << VMXNET3_REV_3)) {
3354 VMXNET3_WRITE_BAR1_REG(adapter,
3355 VMXNET3_REG_VRRS,
3356 1 << VMXNET3_REV_3);
3357 adapter->version = VMXNET3_REV_3 + 1;
3358 } else if (ver & (1 << VMXNET3_REV_2)) {
190af10f
SK		 3359 VMXNET3_WRITE_BAR1_REG(adapter,
3360 VMXNET3_REG_VRRS,
3361 1 << VMXNET3_REV_2);
3362 adapter->version = VMXNET3_REV_2 + 1;
3363 } else if (ver & (1 << VMXNET3_REV_1)) {
3364 VMXNET3_WRITE_BAR1_REG(adapter,
3365 VMXNET3_REG_VRRS,
3366 1 << VMXNET3_REV_1);
3367 adapter->version = VMXNET3_REV_1 + 1;
d1a890fa 3368 } else {
204a6e65
SH		 3369 dev_err(&pdev->dev,
3370 "Incompatible h/w version (0x%x) for adapter\n", ver);
d1a890fa
SB		 3371 err = -EBUSY;
3372 goto err_ver;
3373 }
45dac1d6 3374 dev_dbg(&pdev->dev, "Using device version %d\n", adapter->version);
d1a890fa
SB		 3375
3376 ver = VMXNET3_READ_BAR1_REG(adapter, VMXNET3_REG_UVRS);
3377 if (ver & 1) {
3378 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_UVRS, 1);
3379 } else {
204a6e65
SH		 3380 dev_err(&pdev->dev,
3381 "Incompatible upt version (0x%x) for adapter\n", ver);
d1a890fa
SB		 3382 err = -EBUSY;
3383 goto err_ver;
3384 }
3385
4edef40e
SK		 3386 if (VMXNET3_VERSION_GE_3(adapter)) {
3387 adapter->coal_conf =
3388 dma_alloc_coherent(&adapter->pdev->dev,
3389 sizeof(struct Vmxnet3_CoalesceScheme)
3390 ,
3391 &adapter->coal_conf_pa,
3392 GFP_KERNEL);
3393 if (!adapter->coal_conf) {
3394 err = -ENOMEM;
3395 goto err_ver;
3396 }
3397 memset(adapter->coal_conf, 0, sizeof(*adapter->coal_conf));
3398 adapter->coal_conf->coalMode = VMXNET3_COALESCE_DISABLED;
3399 adapter->default_coal_mode = true;
3400 }
3401
e101e7dd 3402 SET_NETDEV_DEV(netdev, &pdev->dev);
d1a890fa
SB		 3403 vmxnet3_declare_features(adapter, dma64);
3404
50a5ce3e
SK		 3405 adapter->rxdata_desc_size = VMXNET3_VERSION_GE_3(adapter) ?
3406 VMXNET3_DEF_RXDATA_DESC_SIZE : 0;
3407
4db37a78
SH		 3408 if (adapter->num_tx_queues == adapter->num_rx_queues)
3409 adapter->share_intr = VMXNET3_INTR_BUDDYSHARE;
3410 else
09c5088e
SB		 3411 adapter->share_intr = VMXNET3_INTR_DONTSHARE;
3412
d1a890fa
SB		 3413 vmxnet3_alloc_intr_resources(adapter);
3414
09c5088e
SB		 3415#ifdef VMXNET3_RSS
3416 if (adapter->num_rx_queues > 1 &&
3417 adapter->intr.type == VMXNET3_IT_MSIX) {
3418 adapter->rss = true;
7db11f75
SH		 3419 netdev->hw_features |= NETIF_F_RXHASH;
3420 netdev->features |= NETIF_F_RXHASH;
204a6e65 3421 dev_dbg(&pdev->dev, "RSS is enabled.\n");
09c5088e
SB		 3422 } else {
3423 adapter->rss = false;
3424 }
3425#endif
3426
d1a890fa
SB		 3427 vmxnet3_read_mac_addr(adapter, mac);
3428 memcpy(netdev->dev_addr, mac, netdev->addr_len);
3429
3430 netdev->netdev_ops = &vmxnet3_netdev_ops;
d1a890fa 3431 vmxnet3_set_ethtool_ops(netdev);
09c5088e 3432 netdev->watchdog_timeo = 5 * HZ;
d1a890fa 3433
d0c2c997
JW		 3434 /* MTU range: 60 - 9000 */
3435 netdev->min_mtu = VMXNET3_MIN_MTU;
3436 netdev->max_mtu = VMXNET3_MAX_MTU;
3437
d1a890fa 3438 INIT_WORK(&adapter->work, vmxnet3_reset_work);
e3bc4ffb 3439 set_bit(VMXNET3_STATE_BIT_QUIESCED, &adapter->state);
d1a890fa 3440
09c5088e
SB		 3441 if (adapter->intr.type == VMXNET3_IT_MSIX) {
3442 int i;
3443 for (i = 0; i < adapter->num_rx_queues; i++) {
3444 netif_napi_add(adapter->netdev,
3445 &adapter->rx_queue[i].napi,
3446 vmxnet3_poll_rx_only, 64);
3447 }
3448 } else {
3449 netif_napi_add(adapter->netdev, &adapter->rx_queue[0].napi,
3450 vmxnet3_poll, 64);
3451 }
3452
3453 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
3454 netif_set_real_num_rx_queues(adapter->netdev, adapter->num_rx_queues);
3455
6cdd20c3 3456 netif_carrier_off(netdev);
d1a890fa
SB		 3457 err = register_netdev(netdev);
3458
3459 if (err) {
204a6e65 3460 dev_err(&pdev->dev, "Failed to register adapter\n");
d1a890fa
SB		 3461 goto err_register;
3462 }
3463
4a1745fc 3464 vmxnet3_check_link(adapter, false);
d1a890fa
SB		 3465 return 0;
3466
3467err_register:
4edef40e
SK		 3468 if (VMXNET3_VERSION_GE_3(adapter)) {
3469 dma_free_coherent(&adapter->pdev->dev,
3470 sizeof(struct Vmxnet3_CoalesceScheme),
3471 adapter->coal_conf, adapter->coal_conf_pa);
3472 }
d1a890fa
SB		 3473 vmxnet3_free_intr_resources(adapter);
3474err_ver:
3475 vmxnet3_free_pci_resources(adapter);
3476err_alloc_pci:
09c5088e 3477#ifdef VMXNET3_RSS
b0eb57cb
AK		 3478 dma_free_coherent(&adapter->pdev->dev, sizeof(struct UPT1_RSSConf),
3479 adapter->rss_conf, adapter->rss_conf_pa);
09c5088e
SB		 3480err_alloc_rss:
3481#endif
b0eb57cb
AK		 3482 dma_free_coherent(&adapter->pdev->dev, sizeof(struct Vmxnet3_PMConf),
3483 adapter->pm_conf, adapter->pm_conf_pa);
d1a890fa 3484err_alloc_pm:
b0eb57cb
AK		 3485 dma_free_coherent(&adapter->pdev->dev, size, adapter->tqd_start,
3486 adapter->queue_desc_pa);
d1a890fa 3487err_alloc_queue_desc:
b0eb57cb
AK		 3488 dma_free_coherent(&adapter->pdev->dev,
3489 sizeof(struct Vmxnet3_DriverShared),
3490 adapter->shared, adapter->shared_pa);
d1a890fa 3491err_alloc_shared:
b0eb57cb
AK		 3492 dma_unmap_single(&adapter->pdev->dev, adapter->adapter_pa,
3493 sizeof(struct vmxnet3_adapter), PCI_DMA_TODEVICE);
5738a09d 3494err_dma_map:
d1a890fa
SB		 3495 free_netdev(netdev);
3496 return err;
3497}
3498
3499
3a4751a3 3500static void
d1a890fa
SB		 3501vmxnet3_remove_device(struct pci_dev *pdev)
3502{
3503 struct net_device *netdev = pci_get_drvdata(pdev);
3504 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
09c5088e
SB		 3505 int size = 0;
3506 int num_rx_queues;
3507
3508#ifdef VMXNET3_RSS
3509 if (enable_mq)
3510 num_rx_queues = min(VMXNET3_DEVICE_MAX_RX_QUEUES,
3511 (int)num_online_cpus());
3512 else
3513#endif
3514 num_rx_queues = 1;
eebb02b1 3515 num_rx_queues = rounddown_pow_of_two(num_rx_queues);
d1a890fa 3516
23f333a2 3517 cancel_work_sync(&adapter->work);
d1a890fa
SB		 3518
3519 unregister_netdev(netdev);
3520
3521 vmxnet3_free_intr_resources(adapter);
3522 vmxnet3_free_pci_resources(adapter);
4edef40e
SK		 3523 if (VMXNET3_VERSION_GE_3(adapter)) {
3524 dma_free_coherent(&adapter->pdev->dev,
3525 sizeof(struct Vmxnet3_CoalesceScheme),
3526 adapter->coal_conf, adapter->coal_conf_pa);
3527 }
09c5088e 3528#ifdef VMXNET3_RSS
b0eb57cb
AK		 3529 dma_free_coherent(&adapter->pdev->dev, sizeof(struct UPT1_RSSConf),
3530 adapter->rss_conf, adapter->rss_conf_pa);
09c5088e 3531#endif
b0eb57cb
AK		 3532 dma_free_coherent(&adapter->pdev->dev, sizeof(struct Vmxnet3_PMConf),
3533 adapter->pm_conf, adapter->pm_conf_pa);
09c5088e
SB		 3534
3535 size = sizeof(struct Vmxnet3_TxQueueDesc) * adapter->num_tx_queues;
3536 size += sizeof(struct Vmxnet3_RxQueueDesc) * num_rx_queues;
b0eb57cb
AK		 3537 dma_free_coherent(&adapter->pdev->dev, size, adapter->tqd_start,
3538 adapter->queue_desc_pa);
3539 dma_free_coherent(&adapter->pdev->dev,
3540 sizeof(struct Vmxnet3_DriverShared),
3541 adapter->shared, adapter->shared_pa);
3542 dma_unmap_single(&adapter->pdev->dev, adapter->adapter_pa,
3543 sizeof(struct vmxnet3_adapter), PCI_DMA_TODEVICE);
d1a890fa
SB		 3544 free_netdev(netdev);
3545}
3546
e9ba47bf
SB		 3547static void vmxnet3_shutdown_device(struct pci_dev *pdev)
3548{
3549 struct net_device *netdev = pci_get_drvdata(pdev);
3550 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3551 unsigned long flags;
3552
3553 /* Reset_work may be in the middle of resetting the device, wait for its
3554 * completion.
3555 */
3556 while (test_and_set_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state))
3557 msleep(1);
3558
3559 if (test_and_set_bit(VMXNET3_STATE_BIT_QUIESCED,
3560 &adapter->state)) {
3561 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
3562 return;
3563 }
3564 spin_lock_irqsave(&adapter->cmd_lock, flags);
3565 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3566 VMXNET3_CMD_QUIESCE_DEV);
3567 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
3568 vmxnet3_disable_all_intrs(adapter);
3569
3570 clear_bit(VMXNET3_STATE_BIT_RESETTING, &adapter->state);
3571}
3572
d1a890fa
SB		 3573
3574#ifdef CONFIG_PM
3575
3576static int
3577vmxnet3_suspend(struct device *device)
3578{
3579 struct pci_dev *pdev = to_pci_dev(device);
3580 struct net_device *netdev = pci_get_drvdata(pdev);
3581 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
3582 struct Vmxnet3_PMConf *pmConf;
3583 struct ethhdr *ehdr;
3584 struct arphdr *ahdr;
3585 u8 *arpreq;
3586 struct in_device *in_dev;
3587 struct in_ifaddr *ifa;
83d0feff 3588 unsigned long flags;
d1a890fa
SB		 3589 int i = 0;
3590
3591 if (!netif_running(netdev))
3592 return 0;
3593
51956cd6
SB		 3594 for (i = 0; i < adapter->num_rx_queues; i++)
3595 napi_disable(&adapter->rx_queue[i].napi);
3596
d1a890fa
SB		 3597 vmxnet3_disable_all_intrs(adapter);
3598 vmxnet3_free_irqs(adapter);
3599 vmxnet3_free_intr_resources(adapter);
3600
3601 netif_device_detach(netdev);
09c5088e 3602 netif_tx_stop_all_queues(netdev);
d1a890fa
SB		 3603
3604 /* Create wake-up filters. */
3605 pmConf = adapter->pm_conf;
3606 memset(pmConf, 0, sizeof(*pmConf));
3607
3608 if (adapter->wol & WAKE_UCAST) {
3609 pmConf->filters[i].patternSize = ETH_ALEN;
3610 pmConf->filters[i].maskSize = 1;
3611 memcpy(pmConf->filters[i].pattern, netdev->dev_addr, ETH_ALEN);
3612 pmConf->filters[i].mask[0] = 0x3F; /* LSB ETH_ALEN bits */
3613
3843e515 3614 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER;
d1a890fa
SB		 3615 i++;
3616 }
3617
3618 if (adapter->wol & WAKE_ARP) {
3619 in_dev = in_dev_get(netdev);
3620 if (!in_dev)
3621 goto skip_arp;
3622
3623 ifa = (struct in_ifaddr *)in_dev->ifa_list;
3624 if (!ifa)
3625 goto skip_arp;
3626
3627 pmConf->filters[i].patternSize = ETH_HLEN + /* Ethernet header*/
3628 sizeof(struct arphdr) + /* ARP header */
3629 2 * ETH_ALEN + /* 2 Ethernet addresses*/
3630 2 * sizeof(u32); /*2 IPv4 addresses */
3631 pmConf->filters[i].maskSize =
3632 (pmConf->filters[i].patternSize - 1) / 8 + 1;
3633
3634 /* ETH_P_ARP in Ethernet header. */
3635 ehdr = (struct ethhdr *)pmConf->filters[i].pattern;
3636 ehdr->h_proto = htons(ETH_P_ARP);
3637
3638 /* ARPOP_REQUEST in ARP header. */
3639 ahdr = (struct arphdr *)&pmConf->filters[i].pattern[ETH_HLEN];
3640 ahdr->ar_op = htons(ARPOP_REQUEST);
3641 arpreq = (u8 *)(ahdr + 1);
3642
3643 /* The Unicast IPv4 address in 'tip' field. */
3644 arpreq += 2 * ETH_ALEN + sizeof(u32);
3645 *(u32 *)arpreq = ifa->ifa_address;
3646
3647 /* The mask for the relevant bits. */
3648 pmConf->filters[i].mask[0] = 0x00;
3649 pmConf->filters[i].mask[1] = 0x30; /* ETH_P_ARP */
3650 pmConf->filters[i].mask[2] = 0x30; /* ARPOP_REQUEST */
3651 pmConf->filters[i].mask[3] = 0x00;
3652 pmConf->filters[i].mask[4] = 0xC0; /* IPv4 TIP */
3653 pmConf->filters[i].mask[5] = 0x03; /* IPv4 TIP */
3654 in_dev_put(in_dev);
3655
3843e515 3656 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_FILTER;
d1a890fa
SB		 3657 i++;
3658 }
3659
3660skip_arp:
3661 if (adapter->wol & WAKE_MAGIC)
3843e515 3662 pmConf->wakeUpEvents |= VMXNET3_PM_WAKEUP_MAGIC;
d1a890fa
SB		 3663
3664 pmConf->numFilters = i;
3665
115924b6
SB		 3666 adapter->shared->devRead.pmConfDesc.confVer = cpu_to_le32(1);
3667 adapter->shared->devRead.pmConfDesc.confLen = cpu_to_le32(sizeof(
3668 *pmConf));
b0eb57cb
AK		 3669 adapter->shared->devRead.pmConfDesc.confPA =
3670 cpu_to_le64(adapter->pm_conf_pa);
d1a890fa 3671
83d0feff 3672 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa
SB		 3673 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
3674 VMXNET3_CMD_UPDATE_PMCFG);
83d0feff 3675 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
d1a890fa
SB		 3676
3677 pci_save_state(pdev);
3678 pci_enable_wake(pdev, pci_choose_state(pdev, PMSG_SUSPEND),
3679 adapter->wol);
3680 pci_disable_device(pdev);
3681 pci_set_power_state(pdev, pci_choose_state(pdev, PMSG_SUSPEND));
3682
3683 return 0;
3684}
3685
3686
3687static int
3688vmxnet3_resume(struct device *device)
3689{
5ec82c1e 3690 int err;
83d0feff 3691 unsigned long flags;
d1a890fa
SB		 3692 struct pci_dev *pdev = to_pci_dev(device);
3693 struct net_device *netdev = pci_get_drvdata(pdev);
3694 struct vmxnet3_adapter *adapter = netdev_priv(netdev);
d1a890fa
SB		 3695
3696 if (!netif_running(netdev))
3697 return 0;
3698
d1a890fa
SB		 3699 pci_set_power_state(pdev, PCI_D0);
3700 pci_restore_state(pdev);
3701 err = pci_enable_device_mem(pdev);
3702 if (err != 0)
3703 return err;
3704
3705 pci_enable_wake(pdev, PCI_D0, 0);
3706
5ec82c1e
SK		 3707 vmxnet3_alloc_intr_resources(adapter);
3708
3709 /* During hibernate and suspend, device has to be reinitialized as the
3710 * device state need not be preserved.
3711 */
3712
3713 /* Need not check adapter state as other reset tasks cannot run during
3714 * device resume.
3715 */
83d0feff 3716 spin_lock_irqsave(&adapter->cmd_lock, flags);
d1a890fa 3717 VMXNET3_WRITE_BAR1_REG(adapter, VMXNET3_REG_CMD,
5ec82c1e 3718 VMXNET3_CMD_QUIESCE_DEV);
83d0feff 3719 spin_unlock_irqrestore(&adapter->cmd_lock, flags);
5ec82c1e
SK		 3720 vmxnet3_tq_cleanup_all(adapter);
3721 vmxnet3_rq_cleanup_all(adapter);
3722
3723 vmxnet3_reset_dev(adapter);
3724 err = vmxnet3_activate_dev(adapter);
3725 if (err != 0) {
3726 netdev_err(netdev,
3727 "failed to re-activate on resume, error: %d", err);
3728 vmxnet3_force_close(adapter);
3729 return err;
3730 }
3731 netif_device_attach(netdev);
d1a890fa
SB		 3732
3733 return 0;
3734}
3735
47145210 3736static const struct dev_pm_ops vmxnet3_pm_ops = {
d1a890fa
SB		 3737 .suspend = vmxnet3_suspend,
3738 .resume = vmxnet3_resume,
5ec82c1e
SK		 3739 .freeze = vmxnet3_suspend,
3740 .restore = vmxnet3_resume,
d1a890fa
SB		 3741};
3742#endif
3743
3744static struct pci_driver vmxnet3_driver = {
3745 .name = vmxnet3_driver_name,
3746 .id_table = vmxnet3_pciid_table,
3747 .probe = vmxnet3_probe_device,
3a4751a3 3748 .remove = vmxnet3_remove_device,
e9ba47bf 3749 .shutdown = vmxnet3_shutdown_device,
d1a890fa
SB		 3750#ifdef CONFIG_PM
3751 .driver.pm = &vmxnet3_pm_ops,
3752#endif
3753};
3754
3755
3756static int __init
3757vmxnet3_init_module(void)
3758{
204a6e65 3759 pr_info("%s - version %s\n", VMXNET3_DRIVER_DESC,
d1a890fa
SB		 3760 VMXNET3_DRIVER_VERSION_REPORT);
3761 return pci_register_driver(&vmxnet3_driver);
3762}
3763
3764module_init(vmxnet3_init_module);
3765
3766
3767static void
3768vmxnet3_exit_module(void)
3769{
3770 pci_unregister_driver(&vmxnet3_driver);
3771}
3772
3773module_exit(vmxnet3_exit_module);
3774
3775MODULE_AUTHOR("VMware, Inc.");
3776MODULE_DESCRIPTION(VMXNET3_DRIVER_DESC);
3777MODULE_LICENSE("GPL v2");
3778MODULE_VERSION(VMXNET3_DRIVER_VERSION_STRING);
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