]>
Commit | Line | Data |
---|---|---|
d1a890fa SB |
1 | /* |
2 | * Linux driver for VMware's vmxnet3 ethernet NIC. | |
3 | * | |
190af10f | 4 | * Copyright (C) 2008-2016, VMware, Inc. All Rights Reserved. |
d1a890fa SB |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License as published by the | |
8 | * Free Software Foundation; version 2 of the License and no later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but | |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
13 | * NON INFRINGEMENT. See the GNU General Public License for more | |
14 | * details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. | |
19 | * | |
20 | * The full GNU General Public License is included in this distribution in | |
21 | * the file called "COPYING". | |
22 | * | |
190af10f | 23 | * Maintained by: pv-drivers@vmware.com |
d1a890fa SB |
24 | * |
25 | */ | |
26 | ||
27 | #ifndef _VMXNET3_INT_H | |
28 | #define _VMXNET3_INT_H | |
29 | ||
72e85c45 | 30 | #include <linux/bitops.h> |
d1a890fa SB |
31 | #include <linux/ethtool.h> |
32 | #include <linux/delay.h> | |
33 | #include <linux/netdevice.h> | |
34 | #include <linux/pci.h> | |
d1a890fa | 35 | #include <linux/compiler.h> |
d1a890fa SB |
36 | #include <linux/slab.h> |
37 | #include <linux/spinlock.h> | |
38 | #include <linux/ioport.h> | |
39 | #include <linux/highmem.h> | |
d1a890fa SB |
40 | #include <linux/timer.h> |
41 | #include <linux/skbuff.h> | |
42 | #include <linux/interrupt.h> | |
43 | #include <linux/workqueue.h> | |
44 | #include <linux/uaccess.h> | |
45 | #include <asm/dma.h> | |
46 | #include <asm/page.h> | |
47 | ||
48 | #include <linux/tcp.h> | |
49 | #include <linux/udp.h> | |
50 | #include <linux/ip.h> | |
51 | #include <linux/ipv6.h> | |
52 | #include <linux/in.h> | |
53 | #include <linux/etherdevice.h> | |
54 | #include <asm/checksum.h> | |
55 | #include <linux/if_vlan.h> | |
56 | #include <linux/if_arp.h> | |
57 | #include <linux/inetdevice.h> | |
eebb02b1 | 58 | #include <linux/log2.h> |
d1a890fa SB |
59 | |
60 | #include "vmxnet3_defs.h" | |
61 | ||
62 | #ifdef DEBUG | |
63 | # define VMXNET3_DRIVER_VERSION_REPORT VMXNET3_DRIVER_VERSION_STRING"-NAPI(debug)" | |
64 | #else | |
65 | # define VMXNET3_DRIVER_VERSION_REPORT VMXNET3_DRIVER_VERSION_STRING"-NAPI" | |
66 | #endif | |
67 | ||
68 | ||
69 | /* | |
70 | * Version numbers | |
71 | */ | |
3dd7400b | 72 | #define VMXNET3_DRIVER_VERSION_STRING "1.4.17.0-k" |
d1a890fa | 73 | |
61aeecea | 74 | /* Each byte of this 32-bit integer encodes a version number in |
75 | * VMXNET3_DRIVER_VERSION_STRING. | |
76 | */ | |
3dd7400b | 77 | #define VMXNET3_DRIVER_VERSION_NUM 0x01041100 |
d1a890fa | 78 | |
09c5088e SB |
79 | #if defined(CONFIG_PCI_MSI) |
80 | /* RSS only makes sense if MSI-X is supported. */ | |
81 | #define VMXNET3_RSS | |
82 | #endif | |
d1a890fa | 83 | |
190af10f SK |
84 | #define VMXNET3_REV_3 2 /* Vmxnet3 Rev. 3 */ |
85 | #define VMXNET3_REV_2 1 /* Vmxnet3 Rev. 2 */ | |
86 | #define VMXNET3_REV_1 0 /* Vmxnet3 Rev. 1 */ | |
87 | ||
d1a890fa SB |
88 | /* |
89 | * Capabilities | |
90 | */ | |
91 | ||
92 | enum { | |
93 | VMNET_CAP_SG = 0x0001, /* Can do scatter-gather transmits. */ | |
94 | VMNET_CAP_IP4_CSUM = 0x0002, /* Can checksum only TCP/UDP over | |
95 | * IPv4 */ | |
96 | VMNET_CAP_HW_CSUM = 0x0004, /* Can checksum all packets. */ | |
97 | VMNET_CAP_HIGH_DMA = 0x0008, /* Can DMA to high memory. */ | |
98 | VMNET_CAP_TOE = 0x0010, /* Supports TCP/IP offload. */ | |
99 | VMNET_CAP_TSO = 0x0020, /* Supports TCP Segmentation | |
100 | * offload */ | |
101 | VMNET_CAP_SW_TSO = 0x0040, /* Supports SW TCP Segmentation */ | |
102 | VMNET_CAP_VMXNET_APROM = 0x0080, /* Vmxnet APROM support */ | |
103 | VMNET_CAP_HW_TX_VLAN = 0x0100, /* Can we do VLAN tagging in HW */ | |
104 | VMNET_CAP_HW_RX_VLAN = 0x0200, /* Can we do VLAN untagging in HW */ | |
105 | VMNET_CAP_SW_VLAN = 0x0400, /* VLAN tagging/untagging in SW */ | |
106 | VMNET_CAP_WAKE_PCKT_RCV = 0x0800, /* Can wake on network packet recv? */ | |
107 | VMNET_CAP_ENABLE_INT_INLINE = 0x1000, /* Enable Interrupt Inline */ | |
108 | VMNET_CAP_ENABLE_HEADER_COPY = 0x2000, /* copy header for vmkernel */ | |
109 | VMNET_CAP_TX_CHAIN = 0x4000, /* Guest can use multiple tx entries | |
110 | * for a pkt */ | |
111 | VMNET_CAP_RX_CHAIN = 0x8000, /* pkt can span multiple rx entries */ | |
112 | VMNET_CAP_LPD = 0x10000, /* large pkt delivery */ | |
113 | VMNET_CAP_BPF = 0x20000, /* BPF Support in VMXNET Virtual HW*/ | |
114 | VMNET_CAP_SG_SPAN_PAGES = 0x40000, /* Scatter-gather can span multiple*/ | |
115 | /* pages transmits */ | |
116 | VMNET_CAP_IP6_CSUM = 0x80000, /* Can do IPv6 csum offload. */ | |
117 | VMNET_CAP_TSO6 = 0x100000, /* TSO seg. offload for IPv6 pkts. */ | |
118 | VMNET_CAP_TSO256k = 0x200000, /* Can do TSO seg offload for */ | |
119 | /* pkts up to 256kB. */ | |
120 | VMNET_CAP_UPT = 0x400000 /* Support UPT */ | |
121 | }; | |
122 | ||
123 | /* | |
b1226c7d | 124 | * Maximum devices supported. |
d1a890fa | 125 | */ |
d1a890fa SB |
126 | #define MAX_ETHERNET_CARDS 10 |
127 | #define MAX_PCI_PASSTHRU_DEVICE 6 | |
128 | ||
129 | struct vmxnet3_cmd_ring { | |
130 | union Vmxnet3_GenericDesc *base; | |
131 | u32 size; | |
132 | u32 next2fill; | |
133 | u32 next2comp; | |
134 | u8 gen; | |
135 | dma_addr_t basePA; | |
136 | }; | |
137 | ||
138 | static inline void | |
139 | vmxnet3_cmd_ring_adv_next2fill(struct vmxnet3_cmd_ring *ring) | |
140 | { | |
141 | ring->next2fill++; | |
142 | if (unlikely(ring->next2fill == ring->size)) { | |
143 | ring->next2fill = 0; | |
144 | VMXNET3_FLIP_RING_GEN(ring->gen); | |
145 | } | |
146 | } | |
147 | ||
148 | static inline void | |
149 | vmxnet3_cmd_ring_adv_next2comp(struct vmxnet3_cmd_ring *ring) | |
150 | { | |
151 | VMXNET3_INC_RING_IDX_ONLY(ring->next2comp, ring->size); | |
152 | } | |
153 | ||
154 | static inline int | |
155 | vmxnet3_cmd_ring_desc_avail(struct vmxnet3_cmd_ring *ring) | |
156 | { | |
157 | return (ring->next2comp > ring->next2fill ? 0 : ring->size) + | |
158 | ring->next2comp - ring->next2fill - 1; | |
159 | } | |
160 | ||
161 | struct vmxnet3_comp_ring { | |
162 | union Vmxnet3_GenericDesc *base; | |
163 | u32 size; | |
164 | u32 next2proc; | |
165 | u8 gen; | |
166 | u8 intr_idx; | |
167 | dma_addr_t basePA; | |
168 | }; | |
169 | ||
170 | static inline void | |
171 | vmxnet3_comp_ring_adv_next2proc(struct vmxnet3_comp_ring *ring) | |
172 | { | |
173 | ring->next2proc++; | |
174 | if (unlikely(ring->next2proc == ring->size)) { | |
175 | ring->next2proc = 0; | |
176 | VMXNET3_FLIP_RING_GEN(ring->gen); | |
177 | } | |
178 | } | |
179 | ||
180 | struct vmxnet3_tx_data_ring { | |
181 | struct Vmxnet3_TxDataDesc *base; | |
182 | u32 size; | |
183 | dma_addr_t basePA; | |
184 | }; | |
185 | ||
186 | enum vmxnet3_buf_map_type { | |
187 | VMXNET3_MAP_INVALID = 0, | |
188 | VMXNET3_MAP_NONE, | |
189 | VMXNET3_MAP_SINGLE, | |
190 | VMXNET3_MAP_PAGE, | |
191 | }; | |
192 | ||
193 | struct vmxnet3_tx_buf_info { | |
194 | u32 map_type; | |
195 | u16 len; | |
196 | u16 sop_idx; | |
197 | dma_addr_t dma_addr; | |
198 | struct sk_buff *skb; | |
199 | }; | |
200 | ||
201 | struct vmxnet3_tq_driver_stats { | |
202 | u64 drop_total; /* # of pkts dropped by the driver, the | |
203 | * counters below track droppings due to | |
204 | * different reasons | |
205 | */ | |
206 | u64 drop_too_many_frags; | |
207 | u64 drop_oversized_hdr; | |
208 | u64 drop_hdr_inspect_err; | |
209 | u64 drop_tso; | |
210 | ||
211 | u64 tx_ring_full; | |
212 | u64 linearized; /* # of pkts linearized */ | |
213 | u64 copy_skb_header; /* # of times we have to copy skb header */ | |
214 | u64 oversized_hdr; | |
215 | }; | |
216 | ||
217 | struct vmxnet3_tx_ctx { | |
218 | bool ipv4; | |
759c9359 | 219 | bool ipv6; |
d1a890fa SB |
220 | u16 mss; |
221 | u32 eth_ip_hdr_size; /* only valid for pkts requesting tso or csum | |
222 | * offloading | |
223 | */ | |
224 | u32 l4_hdr_size; /* only valid if mss != 0 */ | |
225 | u32 copy_size; /* # of bytes copied into the data ring */ | |
226 | union Vmxnet3_GenericDesc *sop_txd; | |
227 | union Vmxnet3_GenericDesc *eop_txd; | |
228 | }; | |
229 | ||
230 | struct vmxnet3_tx_queue { | |
09c5088e SB |
231 | char name[IFNAMSIZ+8]; /* To identify interrupt */ |
232 | struct vmxnet3_adapter *adapter; | |
d1a890fa SB |
233 | spinlock_t tx_lock; |
234 | struct vmxnet3_cmd_ring tx_ring; | |
09c5088e | 235 | struct vmxnet3_tx_buf_info *buf_info; |
b0eb57cb | 236 | dma_addr_t buf_info_pa; |
d1a890fa SB |
237 | struct vmxnet3_tx_data_ring data_ring; |
238 | struct vmxnet3_comp_ring comp_ring; | |
09c5088e | 239 | struct Vmxnet3_TxQueueCtrl *shared; |
d1a890fa SB |
240 | struct vmxnet3_tq_driver_stats stats; |
241 | bool stopped; | |
242 | int num_stop; /* # of times the queue is | |
243 | * stopped */ | |
09c5088e | 244 | int qid; |
3c8b3efc | 245 | u16 txdata_desc_size; |
d1a890fa SB |
246 | } __attribute__((__aligned__(SMP_CACHE_BYTES))); |
247 | ||
248 | enum vmxnet3_rx_buf_type { | |
249 | VMXNET3_RX_BUF_NONE = 0, | |
250 | VMXNET3_RX_BUF_SKB = 1, | |
251 | VMXNET3_RX_BUF_PAGE = 2 | |
252 | }; | |
253 | ||
254 | struct vmxnet3_rx_buf_info { | |
255 | enum vmxnet3_rx_buf_type buf_type; | |
256 | u16 len; | |
257 | union { | |
258 | struct sk_buff *skb; | |
259 | struct page *page; | |
260 | }; | |
261 | dma_addr_t dma_addr; | |
262 | }; | |
263 | ||
264 | struct vmxnet3_rx_ctx { | |
265 | struct sk_buff *skb; | |
266 | u32 sop_idx; | |
267 | }; | |
268 | ||
269 | struct vmxnet3_rq_driver_stats { | |
270 | u64 drop_total; | |
271 | u64 drop_err; | |
272 | u64 drop_fcs; | |
273 | u64 rx_buf_alloc_failure; | |
274 | }; | |
275 | ||
50a5ce3e SK |
276 | struct vmxnet3_rx_data_ring { |
277 | Vmxnet3_RxDataDesc *base; | |
278 | dma_addr_t basePA; | |
279 | u16 desc_size; | |
280 | }; | |
281 | ||
d1a890fa | 282 | struct vmxnet3_rx_queue { |
09c5088e SB |
283 | char name[IFNAMSIZ + 8]; /* To identify interrupt */ |
284 | struct vmxnet3_adapter *adapter; | |
285 | struct napi_struct napi; | |
d1a890fa | 286 | struct vmxnet3_cmd_ring rx_ring[2]; |
50a5ce3e | 287 | struct vmxnet3_rx_data_ring data_ring; |
d1a890fa SB |
288 | struct vmxnet3_comp_ring comp_ring; |
289 | struct vmxnet3_rx_ctx rx_ctx; | |
290 | u32 qid; /* rqID in RCD for buffer from 1st ring */ | |
291 | u32 qid2; /* rqID in RCD for buffer from 2nd ring */ | |
50a5ce3e | 292 | u32 dataRingQid; /* rqID in RCD for buffer from data ring */ |
d1a890fa | 293 | struct vmxnet3_rx_buf_info *buf_info[2]; |
b0eb57cb | 294 | dma_addr_t buf_info_pa; |
d1a890fa SB |
295 | struct Vmxnet3_RxQueueCtrl *shared; |
296 | struct vmxnet3_rq_driver_stats stats; | |
297 | } __attribute__((__aligned__(SMP_CACHE_BYTES))); | |
298 | ||
09c5088e SB |
299 | #define VMXNET3_DEVICE_MAX_TX_QUEUES 8 |
300 | #define VMXNET3_DEVICE_MAX_RX_QUEUES 8 /* Keep this value as a power of 2 */ | |
301 | ||
302 | /* Should be less than UPT1_RSS_MAX_IND_TABLE_SIZE */ | |
303 | #define VMXNET3_RSS_IND_TABLE_SIZE (VMXNET3_DEVICE_MAX_RX_QUEUES * 4) | |
304 | ||
305 | #define VMXNET3_LINUX_MAX_MSIX_VECT (VMXNET3_DEVICE_MAX_TX_QUEUES + \ | |
306 | VMXNET3_DEVICE_MAX_RX_QUEUES + 1) | |
7e96fbf2 | 307 | #define VMXNET3_LINUX_MIN_MSIX_VECT 2 /* 1 for tx-rx pair and 1 for event */ |
09c5088e | 308 | |
d1a890fa SB |
309 | |
310 | struct vmxnet3_intr { | |
311 | enum vmxnet3_intr_mask_mode mask_mode; | |
312 | enum vmxnet3_intr_type type; /* MSI-X, MSI, or INTx? */ | |
313 | u8 num_intrs; /* # of intr vectors */ | |
314 | u8 event_intr_idx; /* idx of the intr vector for event */ | |
315 | u8 mod_levels[VMXNET3_LINUX_MAX_MSIX_VECT]; /* moderation level */ | |
c7673e4d | 316 | char event_msi_vector_name[IFNAMSIZ+17]; |
d1a890fa SB |
317 | #ifdef CONFIG_PCI_MSI |
318 | struct msix_entry msix_entries[VMXNET3_LINUX_MAX_MSIX_VECT]; | |
319 | #endif | |
320 | }; | |
321 | ||
09c5088e SB |
322 | /* Interrupt sharing schemes, share_intr */ |
323 | #define VMXNET3_INTR_BUDDYSHARE 0 /* Corresponding tx,rx queues share irq */ | |
324 | #define VMXNET3_INTR_TXSHARE 1 /* All tx queues share one irq */ | |
325 | #define VMXNET3_INTR_DONTSHARE 2 /* each queue has its own irq */ | |
326 | ||
327 | ||
d1a890fa SB |
328 | #define VMXNET3_STATE_BIT_RESETTING 0 |
329 | #define VMXNET3_STATE_BIT_QUIESCED 1 | |
330 | struct vmxnet3_adapter { | |
09c5088e SB |
331 | struct vmxnet3_tx_queue tx_queue[VMXNET3_DEVICE_MAX_TX_QUEUES]; |
332 | struct vmxnet3_rx_queue rx_queue[VMXNET3_DEVICE_MAX_RX_QUEUES]; | |
72e85c45 | 333 | unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; |
09c5088e | 334 | struct vmxnet3_intr intr; |
83d0feff | 335 | spinlock_t cmd_lock; |
09c5088e SB |
336 | struct Vmxnet3_DriverShared *shared; |
337 | struct Vmxnet3_PMConf *pm_conf; | |
338 | struct Vmxnet3_TxQueueDesc *tqd_start; /* all tx queue desc */ | |
339 | struct Vmxnet3_RxQueueDesc *rqd_start; /* all rx queue desc */ | |
340 | struct net_device *netdev; | |
09c5088e | 341 | struct pci_dev *pdev; |
d1a890fa | 342 | |
81e8e560 HH |
343 | u8 __iomem *hw_addr0; /* for BAR 0 */ |
344 | u8 __iomem *hw_addr1; /* for BAR 1 */ | |
45dac1d6 SB |
345 | u8 version; |
346 | ||
09c5088e SB |
347 | #ifdef VMXNET3_RSS |
348 | struct UPT1_RSSConf *rss_conf; | |
349 | bool rss; | |
350 | #endif | |
351 | u32 num_rx_queues; | |
352 | u32 num_tx_queues; | |
d1a890fa SB |
353 | |
354 | /* rx buffer related */ | |
355 | unsigned skb_buf_size; | |
356 | int rx_buf_per_pkt; /* only apply to the 1st ring */ | |
357 | dma_addr_t shared_pa; | |
358 | dma_addr_t queue_desc_pa; | |
4edef40e | 359 | dma_addr_t coal_conf_pa; |
d1a890fa SB |
360 | |
361 | /* Wake-on-LAN */ | |
362 | u32 wol; | |
363 | ||
364 | /* Link speed */ | |
365 | u32 link_speed; /* in mbps */ | |
366 | ||
367 | u64 tx_timeout_count; | |
f00e2b0a NH |
368 | |
369 | /* Ring sizes */ | |
370 | u32 tx_ring_size; | |
371 | u32 rx_ring_size; | |
53831aa1 | 372 | u32 rx_ring2_size; |
f00e2b0a | 373 | |
3c8b3efc SK |
374 | /* Size of buffer in the data ring */ |
375 | u16 txdata_desc_size; | |
50a5ce3e SK |
376 | u16 rxdata_desc_size; |
377 | ||
378 | bool rxdataring_enabled; | |
3c8b3efc | 379 | |
d1a890fa SB |
380 | struct work_struct work; |
381 | ||
382 | unsigned long state; /* VMXNET3_STATE_BIT_xxx */ | |
383 | ||
09c5088e | 384 | int share_intr; |
b0eb57cb | 385 | |
4edef40e SK |
386 | struct Vmxnet3_CoalesceScheme *coal_conf; |
387 | bool default_coal_mode; | |
388 | ||
b0eb57cb AK |
389 | dma_addr_t adapter_pa; |
390 | dma_addr_t pm_conf_pa; | |
391 | dma_addr_t rss_conf_pa; | |
d1a890fa SB |
392 | }; |
393 | ||
394 | #define VMXNET3_WRITE_BAR0_REG(adapter, reg, val) \ | |
b8744cab | 395 | writel((val), (adapter)->hw_addr0 + (reg)) |
d1a890fa | 396 | #define VMXNET3_READ_BAR0_REG(adapter, reg) \ |
b8744cab | 397 | readl((adapter)->hw_addr0 + (reg)) |
d1a890fa SB |
398 | |
399 | #define VMXNET3_WRITE_BAR1_REG(adapter, reg, val) \ | |
b8744cab | 400 | writel((val), (adapter)->hw_addr1 + (reg)) |
d1a890fa | 401 | #define VMXNET3_READ_BAR1_REG(adapter, reg) \ |
b8744cab | 402 | readl((adapter)->hw_addr1 + (reg)) |
d1a890fa SB |
403 | |
404 | #define VMXNET3_WAKE_QUEUE_THRESHOLD(tq) (5) | |
405 | #define VMXNET3_RX_ALLOC_THRESHOLD(rq, ring_idx, adapter) \ | |
406 | ((rq)->rx_ring[ring_idx].size >> 3) | |
407 | ||
408 | #define VMXNET3_GET_ADDR_LO(dma) ((u32)(dma)) | |
409 | #define VMXNET3_GET_ADDR_HI(dma) ((u32)(((u64)(dma)) >> 32)) | |
410 | ||
190af10f SK |
411 | #define VMXNET3_VERSION_GE_2(adapter) \ |
412 | (adapter->version >= VMXNET3_REV_2 + 1) | |
413 | #define VMXNET3_VERSION_GE_3(adapter) \ | |
414 | (adapter->version >= VMXNET3_REV_3 + 1) | |
415 | ||
d1a890fa SB |
416 | /* must be a multiple of VMXNET3_RING_SIZE_ALIGN */ |
417 | #define VMXNET3_DEF_TX_RING_SIZE 512 | |
7475908f SK |
418 | #define VMXNET3_DEF_RX_RING_SIZE 1024 |
419 | #define VMXNET3_DEF_RX_RING2_SIZE 256 | |
d1a890fa | 420 | |
50a5ce3e SK |
421 | #define VMXNET3_DEF_RXDATA_DESC_SIZE 128 |
422 | ||
d1a890fa SB |
423 | #define VMXNET3_MAX_ETH_HDR_SIZE 22 |
424 | #define VMXNET3_MAX_SKB_BUF_SIZE (3*1024) | |
425 | ||
50a5ce3e SK |
426 | #define VMXNET3_GET_RING_IDX(adapter, rqID) \ |
427 | ((rqID >= adapter->num_rx_queues && \ | |
428 | rqID < 2 * adapter->num_rx_queues) ? 1 : 0) \ | |
429 | ||
430 | #define VMXNET3_RX_DATA_RING(adapter, rqID) \ | |
431 | (rqID >= 2 * adapter->num_rx_queues && \ | |
432 | rqID < 3 * adapter->num_rx_queues) \ | |
433 | ||
4edef40e SK |
434 | #define VMXNET3_COAL_STATIC_DEFAULT_DEPTH 64 |
435 | ||
436 | #define VMXNET3_COAL_RBC_RATE(usecs) (1000000 / usecs) | |
437 | #define VMXNET3_COAL_RBC_USECS(rbc_rate) (1000000 / rbc_rate) | |
438 | ||
d1a890fa SB |
439 | int |
440 | vmxnet3_quiesce_dev(struct vmxnet3_adapter *adapter); | |
441 | ||
442 | int | |
443 | vmxnet3_activate_dev(struct vmxnet3_adapter *adapter); | |
444 | ||
445 | void | |
446 | vmxnet3_force_close(struct vmxnet3_adapter *adapter); | |
447 | ||
448 | void | |
449 | vmxnet3_reset_dev(struct vmxnet3_adapter *adapter); | |
450 | ||
451 | void | |
09c5088e | 452 | vmxnet3_tq_destroy_all(struct vmxnet3_adapter *adapter); |
d1a890fa SB |
453 | |
454 | void | |
09c5088e | 455 | vmxnet3_rq_destroy_all(struct vmxnet3_adapter *adapter); |
d1a890fa | 456 | |
3dd7400b RD |
457 | netdev_features_t |
458 | vmxnet3_fix_features(struct net_device *netdev, netdev_features_t features); | |
459 | ||
a0d2730c | 460 | int |
c8f44aff | 461 | vmxnet3_set_features(struct net_device *netdev, netdev_features_t features); |
a0d2730c | 462 | |
d1a890fa SB |
463 | int |
464 | vmxnet3_create_queues(struct vmxnet3_adapter *adapter, | |
3c8b3efc | 465 | u32 tx_ring_size, u32 rx_ring_size, u32 rx_ring2_size, |
50a5ce3e | 466 | u16 txdata_desc_size, u16 rxdata_desc_size); |
d1a890fa | 467 | |
d8dea1eb | 468 | void vmxnet3_set_ethtool_ops(struct net_device *netdev); |
95305f6c | 469 | |
bc1f4470 | 470 | void vmxnet3_get_stats64(struct net_device *dev, |
471 | struct rtnl_link_stats64 *stats); | |
d1a890fa SB |
472 | |
473 | extern char vmxnet3_driver_name[]; | |
474 | #endif |