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vxge: Fix a receive stall due to driver being out of synch with chip.
[mirror_ubuntu-bionic-kernel.git] / drivers / net / vxge / vxge-config.c
CommitLineData
40a3a915
RV		 1/******************************************************************************
2 * This software may be used and distributed according to the terms of
3 * the GNU General Public License (GPL), incorporated herein by reference.
4 * Drivers based on or derived from this code fall under the GPL and must
5 * retain the authorship, copyright and license notice. This file is not
6 * a complete program and may only be used when the entire operating
7 * system is licensed under the GPL.
8 * See the file COPYING in this distribution for more information.
9 *
10 * vxge-config.c: Driver for Neterion Inc's X3100 Series 10GbE PCIe I/O
11 * Virtualized Server Adapter.
12 * Copyright(c) 2002-2009 Neterion Inc.
13 ******************************************************************************/
14#include <linux/vmalloc.h>
15#include <linux/etherdevice.h>
16#include <linux/pci.h>
17#include <linux/pci_hotplug.h>
18
19#include "vxge-traffic.h"
20#include "vxge-config.h"
21
22/*
23 * __vxge_hw_channel_allocate - Allocate memory for channel
24 * This function allocates required memory for the channel and various arrays
25 * in the channel
26 */
27struct __vxge_hw_channel*
28__vxge_hw_channel_allocate(struct __vxge_hw_vpath_handle *vph,
29 enum __vxge_hw_channel_type type,
30 u32 length, u32 per_dtr_space, void *userdata)
31{
32 struct __vxge_hw_channel *channel;
33 struct __vxge_hw_device *hldev;
34 int size = 0;
35 u32 vp_id;
36
37 hldev = vph->vpath->hldev;
38 vp_id = vph->vpath->vp_id;
39
40 switch (type) {
41 case VXGE_HW_CHANNEL_TYPE_FIFO:
42 size = sizeof(struct __vxge_hw_fifo);
43 break;
44 case VXGE_HW_CHANNEL_TYPE_RING:
45 size = sizeof(struct __vxge_hw_ring);
46 break;
47 default:
48 break;
49 }
50
51 channel = kzalloc(size, GFP_KERNEL);
52 if (channel == NULL)
53 goto exit0;
54 INIT_LIST_HEAD(&channel->item);
55
56 channel->common_reg = hldev->common_reg;
57 channel->first_vp_id = hldev->first_vp_id;
58 channel->type = type;
59 channel->devh = hldev;
60 channel->vph = vph;
61 channel->userdata = userdata;
62 channel->per_dtr_space = per_dtr_space;
63 channel->length = length;
64 channel->vp_id = vp_id;
65
66 channel->work_arr = kzalloc(sizeof(void *)*length, GFP_KERNEL);
67 if (channel->work_arr == NULL)
68 goto exit1;
69
70 channel->free_arr = kzalloc(sizeof(void *)*length, GFP_KERNEL);
71 if (channel->free_arr == NULL)
72 goto exit1;
73 channel->free_ptr = length;
74
75 channel->reserve_arr = kzalloc(sizeof(void *)*length, GFP_KERNEL);
76 if (channel->reserve_arr == NULL)
77 goto exit1;
78 channel->reserve_ptr = length;
79 channel->reserve_top = 0;
80
81 channel->orig_arr = kzalloc(sizeof(void *)*length, GFP_KERNEL);
82 if (channel->orig_arr == NULL)
83 goto exit1;
84
85 return channel;
86exit1:
87 __vxge_hw_channel_free(channel);
88
89exit0:
90 return NULL;
91}
92
93/*
94 * __vxge_hw_channel_free - Free memory allocated for channel
95 * This function deallocates memory from the channel and various arrays
96 * in the channel
97 */
98void __vxge_hw_channel_free(struct __vxge_hw_channel *channel)
99{
100 kfree(channel->work_arr);
101 kfree(channel->free_arr);
102 kfree(channel->reserve_arr);
103 kfree(channel->orig_arr);
104 kfree(channel);
105}
106
107/*
108 * __vxge_hw_channel_initialize - Initialize a channel
109 * This function initializes a channel by properly setting the
110 * various references
111 */
112enum vxge_hw_status
113__vxge_hw_channel_initialize(struct __vxge_hw_channel *channel)
114{
115 u32 i;
116 struct __vxge_hw_virtualpath *vpath;
117
118 vpath = channel->vph->vpath;
119
120 if ((channel->reserve_arr != NULL) && (channel->orig_arr != NULL)) {
121 for (i = 0; i < channel->length; i++)
122 channel->orig_arr[i] = channel->reserve_arr[i];
123 }
124
125 switch (channel->type) {
126 case VXGE_HW_CHANNEL_TYPE_FIFO:
127 vpath->fifoh = (struct __vxge_hw_fifo *)channel;
128 channel->stats = &((struct __vxge_hw_fifo *)
129 channel)->stats->common_stats;
130 break;
131 case VXGE_HW_CHANNEL_TYPE_RING:
132 vpath->ringh = (struct __vxge_hw_ring *)channel;
133 channel->stats = &((struct __vxge_hw_ring *)
134 channel)->stats->common_stats;
135 break;
136 default:
137 break;
138 }
139
140 return VXGE_HW_OK;
141}
142
143/*
144 * __vxge_hw_channel_reset - Resets a channel
145 * This function resets a channel by properly setting the various references
146 */
147enum vxge_hw_status
148__vxge_hw_channel_reset(struct __vxge_hw_channel *channel)
149{
150 u32 i;
151
152 for (i = 0; i < channel->length; i++) {
153 if (channel->reserve_arr != NULL)
154 channel->reserve_arr[i] = channel->orig_arr[i];
155 if (channel->free_arr != NULL)
156 channel->free_arr[i] = NULL;
157 if (channel->work_arr != NULL)
158 channel->work_arr[i] = NULL;
159 }
160 channel->free_ptr = channel->length;
161 channel->reserve_ptr = channel->length;
162 channel->reserve_top = 0;
163 channel->post_index = 0;
164 channel->compl_index = 0;
165
166 return VXGE_HW_OK;
167}
168
169/*
170 * __vxge_hw_device_pci_e_init
171 * Initialize certain PCI/PCI-X configuration registers
172 * with recommended values. Save config space for future hw resets.
173 */
174void
175__vxge_hw_device_pci_e_init(struct __vxge_hw_device *hldev)
176{
177 u16 cmd = 0;
178
179 /* Set the PErr Repconse bit and SERR in PCI command register. */
180 pci_read_config_word(hldev->pdev, PCI_COMMAND, &cmd);
181 cmd |= 0x140;
182 pci_write_config_word(hldev->pdev, PCI_COMMAND, cmd);
183
184 pci_save_state(hldev->pdev);
185
186 return;
187}
188
189/*
190 * __vxge_hw_device_register_poll
191 * Will poll certain register for specified amount of time.
192 * Will poll until masked bit is not cleared.
193 */
194enum vxge_hw_status
195__vxge_hw_device_register_poll(void __iomem *reg, u64 mask, u32 max_millis)
196{
197 u64 val64;
198 u32 i = 0;
199 enum vxge_hw_status ret = VXGE_HW_FAIL;
200
201 udelay(10);
202
203 do {
204 val64 = readq(reg);
205 if (!(val64 & mask))
206 return VXGE_HW_OK;
207 udelay(100);
208 } while (++i <= 9);
209
210 i = 0;
211 do {
212 val64 = readq(reg);
213 if (!(val64 & mask))
214 return VXGE_HW_OK;
215 mdelay(1);
216 } while (++i <= max_millis);
217
218 return ret;
219}
220
221 /* __vxge_hw_device_vpath_reset_in_prog_check - Check if vpath reset
222 * in progress
223 * This routine checks the vpath reset in progress register is turned zero
224 */
225enum vxge_hw_status
226__vxge_hw_device_vpath_reset_in_prog_check(u64 __iomem *vpath_rst_in_prog)
227{
228 enum vxge_hw_status status;
229 status = __vxge_hw_device_register_poll(vpath_rst_in_prog,
230 VXGE_HW_VPATH_RST_IN_PROG_VPATH_RST_IN_PROG(0x1ffff),
231 VXGE_HW_DEF_DEVICE_POLL_MILLIS);
232 return status;
233}
234
235/*
236 * __vxge_hw_device_toc_get
237 * This routine sets the swapper and reads the toc pointer and returns the
238 * memory mapped address of the toc
239 */
240struct vxge_hw_toc_reg __iomem *
241__vxge_hw_device_toc_get(void __iomem *bar0)
242{
243 u64 val64;
244 struct vxge_hw_toc_reg __iomem *toc = NULL;
245 enum vxge_hw_status status;
246
247 struct vxge_hw_legacy_reg __iomem *legacy_reg =
248 (struct vxge_hw_legacy_reg __iomem *)bar0;
249
250 status = __vxge_hw_legacy_swapper_set(legacy_reg);
251 if (status != VXGE_HW_OK)
252 goto exit;
253
254 val64 = readq(&legacy_reg->toc_first_pointer);
255 toc = (struct vxge_hw_toc_reg __iomem *)(bar0+val64);
256exit:
257 return toc;
258}
259
260/*
261 * __vxge_hw_device_reg_addr_get
262 * This routine sets the swapper and reads the toc pointer and initializes the
263 * register location pointers in the device object. It waits until the ric is
264 * completed initializing registers.
265 */
266enum vxge_hw_status
267__vxge_hw_device_reg_addr_get(struct __vxge_hw_device *hldev)
268{
269 u64 val64;
270 u32 i;
271 enum vxge_hw_status status = VXGE_HW_OK;
272
273 hldev->legacy_reg = (struct vxge_hw_legacy_reg __iomem *)hldev->bar0;
274
275 hldev->toc_reg = __vxge_hw_device_toc_get(hldev->bar0);
276 if (hldev->toc_reg == NULL) {
277 status = VXGE_HW_FAIL;
278 goto exit;
279 }
280
281 val64 = readq(&hldev->toc_reg->toc_common_pointer);
282 hldev->common_reg =
283 (struct vxge_hw_common_reg __iomem *)(hldev->bar0 + val64);
284
285 val64 = readq(&hldev->toc_reg->toc_mrpcim_pointer);
286 hldev->mrpcim_reg =
287 (struct vxge_hw_mrpcim_reg __iomem *)(hldev->bar0 + val64);
288
289 for (i = 0; i < VXGE_HW_TITAN_SRPCIM_REG_SPACES; i++) {
290 val64 = readq(&hldev->toc_reg->toc_srpcim_pointer[i]);
291 hldev->srpcim_reg[i] =
292 (struct vxge_hw_srpcim_reg __iomem *)
293 (hldev->bar0 + val64);
294 }
295
296 for (i = 0; i < VXGE_HW_TITAN_VPMGMT_REG_SPACES; i++) {
297 val64 = readq(&hldev->toc_reg->toc_vpmgmt_pointer[i]);
298 hldev->vpmgmt_reg[i] =
299 (struct vxge_hw_vpmgmt_reg __iomem *)(hldev->bar0 + val64);
300 }
301
302 for (i = 0; i < VXGE_HW_TITAN_VPATH_REG_SPACES; i++) {
303 val64 = readq(&hldev->toc_reg->toc_vpath_pointer[i]);
304 hldev->vpath_reg[i] =
305 (struct vxge_hw_vpath_reg __iomem *)
306 (hldev->bar0 + val64);
307 }
308
309 val64 = readq(&hldev->toc_reg->toc_kdfc);
310
311 switch (VXGE_HW_TOC_GET_KDFC_INITIAL_BIR(val64)) {
312 case 0:
313 hldev->kdfc = (u8 __iomem *)(hldev->bar0 +
314 VXGE_HW_TOC_GET_KDFC_INITIAL_OFFSET(val64));
315 break;
40a3a915
RV		 316 default:
317 break;
318 }
319
320 status = __vxge_hw_device_vpath_reset_in_prog_check(
321 (u64 __iomem *)&hldev->common_reg->vpath_rst_in_prog);
322exit:
323 return status;
324}
325
326/*
327 * __vxge_hw_device_id_get
328 * This routine returns sets the device id and revision numbers into the device
329 * structure
330 */
331void __vxge_hw_device_id_get(struct __vxge_hw_device *hldev)
332{
333 u64 val64;
334
335 val64 = readq(&hldev->common_reg->titan_asic_id);
336 hldev->device_id =
337 (u16)VXGE_HW_TITAN_ASIC_ID_GET_INITIAL_DEVICE_ID(val64);
338
339 hldev->major_revision =
340 (u8)VXGE_HW_TITAN_ASIC_ID_GET_INITIAL_MAJOR_REVISION(val64);
341
342 hldev->minor_revision =
343 (u8)VXGE_HW_TITAN_ASIC_ID_GET_INITIAL_MINOR_REVISION(val64);
344
345 return;
346}
347
348/*
349 * __vxge_hw_device_access_rights_get: Get Access Rights of the driver
350 * This routine returns the Access Rights of the driver
351 */
352static u32
353__vxge_hw_device_access_rights_get(u32 host_type, u32 func_id)
354{
355 u32 access_rights = VXGE_HW_DEVICE_ACCESS_RIGHT_VPATH;
356
357 switch (host_type) {
358 case VXGE_HW_NO_MR_NO_SR_NORMAL_FUNCTION:
92cdd7c3
SH		 359 access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM |
360 VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM;
40a3a915
RV		 361 break;
362 case VXGE_HW_MR_NO_SR_VH0_BASE_FUNCTION:
363 access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM |
364 VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM;
365 break;
366 case VXGE_HW_NO_MR_SR_VH0_FUNCTION0:
367 access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM |
368 VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM;
369 break;
370 case VXGE_HW_NO_MR_SR_VH0_VIRTUAL_FUNCTION:
371 case VXGE_HW_SR_VH_VIRTUAL_FUNCTION:
372 case VXGE_HW_MR_SR_VH0_INVALID_CONFIG:
373 break;
374 case VXGE_HW_SR_VH_FUNCTION0:
375 case VXGE_HW_VH_NORMAL_FUNCTION:
376 access_rights |= VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM;
377 break;
378 }
379
380 return access_rights;
381}
92cdd7c3
SH		 382/*
383 * __vxge_hw_device_is_privilaged
384 * This routine checks if the device function is privilaged or not
385 */
386
387enum vxge_hw_status
388__vxge_hw_device_is_privilaged(u32 host_type, u32 func_id)
389{
390 if (__vxge_hw_device_access_rights_get(host_type,
391 func_id) &
392 VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)
393 return VXGE_HW_OK;
394 else
395 return VXGE_HW_ERR_PRIVILAGED_OPEARATION;
396}
397
40a3a915
RV		 398/*
399 * __vxge_hw_device_host_info_get
400 * This routine returns the host type assignments
401 */
402void __vxge_hw_device_host_info_get(struct __vxge_hw_device *hldev)
403{
404 u64 val64;
405 u32 i;
406
407 val64 = readq(&hldev->common_reg->host_type_assignments);
408
409 hldev->host_type =
410 (u32)VXGE_HW_HOST_TYPE_ASSIGNMENTS_GET_HOST_TYPE_ASSIGNMENTS(val64);
411
412 hldev->vpath_assignments = readq(&hldev->common_reg->vpath_assignments);
413
414 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
415
416 if (!(hldev->vpath_assignments & vxge_mBIT(i)))
417 continue;
418
419 hldev->func_id =
420 __vxge_hw_vpath_func_id_get(i, hldev->vpmgmt_reg[i]);
421
422 hldev->access_rights = __vxge_hw_device_access_rights_get(
423 hldev->host_type, hldev->func_id);
424
425 hldev->first_vp_id = i;
426 break;
427 }
428
429 return;
430}
431
432/*
433 * __vxge_hw_verify_pci_e_info - Validate the pci-e link parameters such as
434 * link width and signalling rate.
435 */
436static enum vxge_hw_status
437__vxge_hw_verify_pci_e_info(struct __vxge_hw_device *hldev)
438{
439 int exp_cap;
440 u16 lnk;
441
442 /* Get the negotiated link width and speed from PCI config space */
443 exp_cap = pci_find_capability(hldev->pdev, PCI_CAP_ID_EXP);
444 pci_read_config_word(hldev->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
445
446 if ((lnk & PCI_EXP_LNKSTA_CLS) != 1)
447 return VXGE_HW_ERR_INVALID_PCI_INFO;
448
449 switch ((lnk & PCI_EXP_LNKSTA_NLW) >> 4) {
450 case PCIE_LNK_WIDTH_RESRV:
451 case PCIE_LNK_X1:
452 case PCIE_LNK_X2:
453 case PCIE_LNK_X4:
454 case PCIE_LNK_X8:
455 break;
456 default:
457 return VXGE_HW_ERR_INVALID_PCI_INFO;
458 }
459
460 return VXGE_HW_OK;
461}
462
40a3a915
RV		 463/*
464 * __vxge_hw_device_initialize
465 * Initialize Titan-V hardware.
466 */
467enum vxge_hw_status __vxge_hw_device_initialize(struct __vxge_hw_device *hldev)
468{
469 enum vxge_hw_status status = VXGE_HW_OK;
470
92cdd7c3
SH		 471 if (VXGE_HW_OK == __vxge_hw_device_is_privilaged(hldev->host_type,
472 hldev->func_id)) {
5dbc9011
SS		 473 /* Validate the pci-e link width and speed */
474 status = __vxge_hw_verify_pci_e_info(hldev);
475 if (status != VXGE_HW_OK)
476 goto exit;
477 }
40a3a915 478
40a3a915
RV		 479exit:
480 return status;
481}
482
483/**
484 * vxge_hw_device_hw_info_get - Get the hw information
485 * Returns the vpath mask that has the bits set for each vpath allocated
486 * for the driver, FW version information and the first mac addresse for
487 * each vpath
488 */
489enum vxge_hw_status __devinit
490vxge_hw_device_hw_info_get(void __iomem *bar0,
491 struct vxge_hw_device_hw_info *hw_info)
492{
493 u32 i;
494 u64 val64;
495 struct vxge_hw_toc_reg __iomem *toc;
496 struct vxge_hw_mrpcim_reg __iomem *mrpcim_reg;
497 struct vxge_hw_common_reg __iomem *common_reg;
498 struct vxge_hw_vpath_reg __iomem *vpath_reg;
499 struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg;
500 enum vxge_hw_status status;
501
502 memset(hw_info, 0, sizeof(struct vxge_hw_device_hw_info));
503
504 toc = __vxge_hw_device_toc_get(bar0);
505 if (toc == NULL) {
506 status = VXGE_HW_ERR_CRITICAL;
507 goto exit;
508 }
509
510 val64 = readq(&toc->toc_common_pointer);
511 common_reg = (struct vxge_hw_common_reg __iomem *)(bar0 + val64);
512
513 status = __vxge_hw_device_vpath_reset_in_prog_check(
514 (u64 __iomem *)&common_reg->vpath_rst_in_prog);
515 if (status != VXGE_HW_OK)
516 goto exit;
517
518 hw_info->vpath_mask = readq(&common_reg->vpath_assignments);
519
520 val64 = readq(&common_reg->host_type_assignments);
521
522 hw_info->host_type =
523 (u32)VXGE_HW_HOST_TYPE_ASSIGNMENTS_GET_HOST_TYPE_ASSIGNMENTS(val64);
524
525 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
526
527 if (!((hw_info->vpath_mask) & vxge_mBIT(i)))
528 continue;
529
530 val64 = readq(&toc->toc_vpmgmt_pointer[i]);
531
532 vpmgmt_reg = (struct vxge_hw_vpmgmt_reg __iomem *)
533 (bar0 + val64);
534
535 hw_info->func_id = __vxge_hw_vpath_func_id_get(i, vpmgmt_reg);
536 if (__vxge_hw_device_access_rights_get(hw_info->host_type,
537 hw_info->func_id) &
538 VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM) {
539
540 val64 = readq(&toc->toc_mrpcim_pointer);
541
542 mrpcim_reg = (struct vxge_hw_mrpcim_reg __iomem *)
543 (bar0 + val64);
544
545 writeq(0, &mrpcim_reg->xgmac_gen_fw_memo_mask);
546 wmb();
547 }
548
549 val64 = readq(&toc->toc_vpath_pointer[i]);
550
551 vpath_reg = (struct vxge_hw_vpath_reg __iomem *)(bar0 + val64);
552
553 hw_info->function_mode =
554 __vxge_hw_vpath_pci_func_mode_get(i, vpath_reg);
555
556 status = __vxge_hw_vpath_fw_ver_get(i, vpath_reg, hw_info);
557 if (status != VXGE_HW_OK)
558 goto exit;
559
560 status = __vxge_hw_vpath_card_info_get(i, vpath_reg, hw_info);
561 if (status != VXGE_HW_OK)
562 goto exit;
563
564 break;
565 }
566
567 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
568
569 if (!((hw_info->vpath_mask) & vxge_mBIT(i)))
570 continue;
571
572 val64 = readq(&toc->toc_vpath_pointer[i]);
573 vpath_reg = (struct vxge_hw_vpath_reg __iomem *)(bar0 + val64);
574
575 status = __vxge_hw_vpath_addr_get(i, vpath_reg,
576 hw_info->mac_addrs[i],
577 hw_info->mac_addr_masks[i]);
578 if (status != VXGE_HW_OK)
579 goto exit;
580 }
581exit:
582 return status;
583}
584
585/*
586 * vxge_hw_device_initialize - Initialize Titan device.
587 * Initialize Titan device. Note that all the arguments of this public API
588 * are 'IN', including @hldev. Driver cooperates with
589 * OS to find new Titan device, locate its PCI and memory spaces.
590 *
591 * When done, the driver allocates sizeof(struct __vxge_hw_device) bytes for HW
592 * to enable the latter to perform Titan hardware initialization.
593 */
594enum vxge_hw_status __devinit
595vxge_hw_device_initialize(
596 struct __vxge_hw_device **devh,
597 struct vxge_hw_device_attr *attr,
598 struct vxge_hw_device_config *device_config)
599{
600 u32 i;
601 u32 nblocks = 0;
602 struct __vxge_hw_device *hldev = NULL;
603 enum vxge_hw_status status = VXGE_HW_OK;
604
605 status = __vxge_hw_device_config_check(device_config);
606 if (status != VXGE_HW_OK)
607 goto exit;
608
609 hldev = (struct __vxge_hw_device *)
610 vmalloc(sizeof(struct __vxge_hw_device));
611 if (hldev == NULL) {
612 status = VXGE_HW_ERR_OUT_OF_MEMORY;
613 goto exit;
614 }
615
616 memset(hldev, 0, sizeof(struct __vxge_hw_device));
617 hldev->magic = VXGE_HW_DEVICE_MAGIC;
618
619 vxge_hw_device_debug_set(hldev, VXGE_ERR, VXGE_COMPONENT_ALL);
620
621 /* apply config */
622 memcpy(&hldev->config, device_config,
623 sizeof(struct vxge_hw_device_config));
624
625 hldev->bar0 = attr->bar0;
40a3a915
RV		 626 hldev->pdev = attr->pdev;
627
628 hldev->uld_callbacks.link_up = attr->uld_callbacks.link_up;
629 hldev->uld_callbacks.link_down = attr->uld_callbacks.link_down;
630 hldev->uld_callbacks.crit_err = attr->uld_callbacks.crit_err;
631
632 __vxge_hw_device_pci_e_init(hldev);
633
634 status = __vxge_hw_device_reg_addr_get(hldev);
635 if (status != VXGE_HW_OK)
636 goto exit;
637 __vxge_hw_device_id_get(hldev);
638
639 __vxge_hw_device_host_info_get(hldev);
640
641 /* Incrementing for stats blocks */
642 nblocks++;
643
644 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
645
646 if (!(hldev->vpath_assignments & vxge_mBIT(i)))
647 continue;
648
649 if (device_config->vp_config[i].ring.enable ==
650 VXGE_HW_RING_ENABLE)
651 nblocks += device_config->vp_config[i].ring.ring_blocks;
652
653 if (device_config->vp_config[i].fifo.enable ==
654 VXGE_HW_FIFO_ENABLE)
655 nblocks += device_config->vp_config[i].fifo.fifo_blocks;
656 nblocks++;
657 }
658
659 if (__vxge_hw_blockpool_create(hldev,
660 &hldev->block_pool,
661 device_config->dma_blockpool_initial + nblocks,
662 device_config->dma_blockpool_max + nblocks) != VXGE_HW_OK) {
663
664 vxge_hw_device_terminate(hldev);
665 status = VXGE_HW_ERR_OUT_OF_MEMORY;
666 goto exit;
667 }
668
669 status = __vxge_hw_device_initialize(hldev);
670
671 if (status != VXGE_HW_OK) {
672 vxge_hw_device_terminate(hldev);
673 goto exit;
674 }
675
676 *devh = hldev;
677exit:
678 return status;
679}
680
681/*
682 * vxge_hw_device_terminate - Terminate Titan device.
683 * Terminate HW device.
684 */
685void
686vxge_hw_device_terminate(struct __vxge_hw_device *hldev)
687{
688 vxge_assert(hldev->magic == VXGE_HW_DEVICE_MAGIC);
689
690 hldev->magic = VXGE_HW_DEVICE_DEAD;
691 __vxge_hw_blockpool_destroy(&hldev->block_pool);
692 vfree(hldev);
693}
694
695/*
696 * vxge_hw_device_stats_get - Get the device hw statistics.
697 * Returns the vpath h/w stats for the device.
698 */
699enum vxge_hw_status
700vxge_hw_device_stats_get(struct __vxge_hw_device *hldev,
701 struct vxge_hw_device_stats_hw_info *hw_stats)
702{
703 u32 i;
704 enum vxge_hw_status status = VXGE_HW_OK;
705
706 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
707
708 if (!(hldev->vpaths_deployed & vxge_mBIT(i)) ||
709 (hldev->virtual_paths[i].vp_open ==
710 VXGE_HW_VP_NOT_OPEN))
711 continue;
712
713 memcpy(hldev->virtual_paths[i].hw_stats_sav,
714 hldev->virtual_paths[i].hw_stats,
715 sizeof(struct vxge_hw_vpath_stats_hw_info));
716
717 status = __vxge_hw_vpath_stats_get(
718 &hldev->virtual_paths[i],
719 hldev->virtual_paths[i].hw_stats);
720 }
721
722 memcpy(hw_stats, &hldev->stats.hw_dev_info_stats,
723 sizeof(struct vxge_hw_device_stats_hw_info));
724
725 return status;
726}
727
728/*
729 * vxge_hw_driver_stats_get - Get the device sw statistics.
730 * Returns the vpath s/w stats for the device.
731 */
732enum vxge_hw_status vxge_hw_driver_stats_get(
733 struct __vxge_hw_device *hldev,
734 struct vxge_hw_device_stats_sw_info *sw_stats)
735{
736 enum vxge_hw_status status = VXGE_HW_OK;
737
738 memcpy(sw_stats, &hldev->stats.sw_dev_info_stats,
739 sizeof(struct vxge_hw_device_stats_sw_info));
740
741 return status;
742}
743
744/*
745 * vxge_hw_mrpcim_stats_access - Access the statistics from the given location
746 * and offset and perform an operation
747 * Get the statistics from the given location and offset.
748 */
749enum vxge_hw_status
750vxge_hw_mrpcim_stats_access(struct __vxge_hw_device *hldev,
751 u32 operation, u32 location, u32 offset, u64 *stat)
752{
753 u64 val64;
754 enum vxge_hw_status status = VXGE_HW_OK;
755
92cdd7c3
SH		 756 status = __vxge_hw_device_is_privilaged(hldev->host_type,
757 hldev->func_id);
40a3a915
RV		 758 if (status != VXGE_HW_OK)
759 goto exit;
760
761 val64 = VXGE_HW_XMAC_STATS_SYS_CMD_OP(operation) |
762 VXGE_HW_XMAC_STATS_SYS_CMD_STROBE |
763 VXGE_HW_XMAC_STATS_SYS_CMD_LOC_SEL(location) |
764 VXGE_HW_XMAC_STATS_SYS_CMD_OFFSET_SEL(offset);
765
766 status = __vxge_hw_pio_mem_write64(val64,
767 &hldev->mrpcim_reg->xmac_stats_sys_cmd,
768 VXGE_HW_XMAC_STATS_SYS_CMD_STROBE,
769 hldev->config.device_poll_millis);
770
771 if ((status == VXGE_HW_OK) && (operation == VXGE_HW_STATS_OP_READ))
772 *stat = readq(&hldev->mrpcim_reg->xmac_stats_sys_data);
773 else
774 *stat = 0;
775exit:
776 return status;
777}
778
779/*
780 * vxge_hw_device_xmac_aggr_stats_get - Get the Statistics on aggregate port
781 * Get the Statistics on aggregate port
782 */
783enum vxge_hw_status
784vxge_hw_device_xmac_aggr_stats_get(struct __vxge_hw_device *hldev, u32 port,
785 struct vxge_hw_xmac_aggr_stats *aggr_stats)
786{
787 u64 *val64;
788 int i;
789 u32 offset = VXGE_HW_STATS_AGGRn_OFFSET;
790 enum vxge_hw_status status = VXGE_HW_OK;
791
792 val64 = (u64 *)aggr_stats;
793
92cdd7c3
SH		 794 status = __vxge_hw_device_is_privilaged(hldev->host_type,
795 hldev->func_id);
40a3a915
RV		 796 if (status != VXGE_HW_OK)
797 goto exit;
798
799 for (i = 0; i < sizeof(struct vxge_hw_xmac_aggr_stats) / 8; i++) {
800 status = vxge_hw_mrpcim_stats_access(hldev,
801 VXGE_HW_STATS_OP_READ,
802 VXGE_HW_STATS_LOC_AGGR,
803 ((offset + (104 * port)) >> 3), val64);
804 if (status != VXGE_HW_OK)
805 goto exit;
806
807 offset += 8;
808 val64++;
809 }
810exit:
811 return status;
812}
813
814/*
815 * vxge_hw_device_xmac_port_stats_get - Get the Statistics on a port
816 * Get the Statistics on port
817 */
818enum vxge_hw_status
819vxge_hw_device_xmac_port_stats_get(struct __vxge_hw_device *hldev, u32 port,
820 struct vxge_hw_xmac_port_stats *port_stats)
821{
822 u64 *val64;
823 enum vxge_hw_status status = VXGE_HW_OK;
824 int i;
825 u32 offset = 0x0;
826 val64 = (u64 *) port_stats;
827
92cdd7c3
SH		 828 status = __vxge_hw_device_is_privilaged(hldev->host_type,
829 hldev->func_id);
40a3a915
RV		 830 if (status != VXGE_HW_OK)
831 goto exit;
832
833 for (i = 0; i < sizeof(struct vxge_hw_xmac_port_stats) / 8; i++) {
834 status = vxge_hw_mrpcim_stats_access(hldev,
835 VXGE_HW_STATS_OP_READ,
836 VXGE_HW_STATS_LOC_AGGR,
837 ((offset + (608 * port)) >> 3), val64);
838 if (status != VXGE_HW_OK)
839 goto exit;
840
841 offset += 8;
842 val64++;
843 }
844
845exit:
846 return status;
847}
848
849/*
850 * vxge_hw_device_xmac_stats_get - Get the XMAC Statistics
851 * Get the XMAC Statistics
852 */
853enum vxge_hw_status
854vxge_hw_device_xmac_stats_get(struct __vxge_hw_device *hldev,
855 struct vxge_hw_xmac_stats *xmac_stats)
856{
857 enum vxge_hw_status status = VXGE_HW_OK;
858 u32 i;
859
860 status = vxge_hw_device_xmac_aggr_stats_get(hldev,
861 0, &xmac_stats->aggr_stats[0]);
862
863 if (status != VXGE_HW_OK)
864 goto exit;
865
866 status = vxge_hw_device_xmac_aggr_stats_get(hldev,
867 1, &xmac_stats->aggr_stats[1]);
868 if (status != VXGE_HW_OK)
869 goto exit;
870
871 for (i = 0; i <= VXGE_HW_MAC_MAX_MAC_PORT_ID; i++) {
872
873 status = vxge_hw_device_xmac_port_stats_get(hldev,
874 i, &xmac_stats->port_stats[i]);
875 if (status != VXGE_HW_OK)
876 goto exit;
877 }
878
879 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
880
881 if (!(hldev->vpaths_deployed & vxge_mBIT(i)))
882 continue;
883
884 status = __vxge_hw_vpath_xmac_tx_stats_get(
885 &hldev->virtual_paths[i],
886 &xmac_stats->vpath_tx_stats[i]);
887 if (status != VXGE_HW_OK)
888 goto exit;
889
890 status = __vxge_hw_vpath_xmac_rx_stats_get(
891 &hldev->virtual_paths[i],
892 &xmac_stats->vpath_rx_stats[i]);
893 if (status != VXGE_HW_OK)
894 goto exit;
895 }
896exit:
897 return status;
898}
899
900/*
901 * vxge_hw_device_debug_set - Set the debug module, level and timestamp
902 * This routine is used to dynamically change the debug output
903 */
904void vxge_hw_device_debug_set(struct __vxge_hw_device *hldev,
905 enum vxge_debug_level level, u32 mask)
906{
907 if (hldev == NULL)
908 return;
909
910#if defined(VXGE_DEBUG_TRACE_MASK) || \
911 defined(VXGE_DEBUG_ERR_MASK)
912 hldev->debug_module_mask = mask;
913 hldev->debug_level = level;
914#endif
915
916#if defined(VXGE_DEBUG_ERR_MASK)
917 hldev->level_err = level & VXGE_ERR;
918#endif
919
920#if defined(VXGE_DEBUG_TRACE_MASK)
921 hldev->level_trace = level & VXGE_TRACE;
922#endif
923}
924
925/*
926 * vxge_hw_device_error_level_get - Get the error level
927 * This routine returns the current error level set
928 */
929u32 vxge_hw_device_error_level_get(struct __vxge_hw_device *hldev)
930{
931#if defined(VXGE_DEBUG_ERR_MASK)
932 if (hldev == NULL)
933 return VXGE_ERR;
934 else
935 return hldev->level_err;
936#else
937 return 0;
938#endif
939}
940
941/*
942 * vxge_hw_device_trace_level_get - Get the trace level
943 * This routine returns the current trace level set
944 */
945u32 vxge_hw_device_trace_level_get(struct __vxge_hw_device *hldev)
946{
947#if defined(VXGE_DEBUG_TRACE_MASK)
948 if (hldev == NULL)
949 return VXGE_TRACE;
950 else
951 return hldev->level_trace;
952#else
953 return 0;
954#endif
955}
956/*
957 * vxge_hw_device_debug_mask_get - Get the debug mask
958 * This routine returns the current debug mask set
959 */
960u32 vxge_hw_device_debug_mask_get(struct __vxge_hw_device *hldev)
961{
962#if defined(VXGE_DEBUG_TRACE_MASK) || defined(VXGE_DEBUG_ERR_MASK)
963 if (hldev == NULL)
964 return 0;
965 return hldev->debug_module_mask;
966#else
967 return 0;
968#endif
969}
970
971/*
972 * vxge_hw_getpause_data -Pause frame frame generation and reception.
973 * Returns the Pause frame generation and reception capability of the NIC.
974 */
975enum vxge_hw_status vxge_hw_device_getpause_data(struct __vxge_hw_device *hldev,
976 u32 port, u32 *tx, u32 *rx)
977{
978 u64 val64;
979 enum vxge_hw_status status = VXGE_HW_OK;
980
981 if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) {
982 status = VXGE_HW_ERR_INVALID_DEVICE;
983 goto exit;
984 }
985
986 if (port > VXGE_HW_MAC_MAX_MAC_PORT_ID) {
987 status = VXGE_HW_ERR_INVALID_PORT;
988 goto exit;
989 }
990
991 if (!(hldev->access_rights & VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)) {
992 status = VXGE_HW_ERR_PRIVILAGED_OPEARATION;
993 goto exit;
994 }
995
996 val64 = readq(&hldev->mrpcim_reg->rxmac_pause_cfg_port[port]);
997 if (val64 & VXGE_HW_RXMAC_PAUSE_CFG_PORT_GEN_EN)
998 *tx = 1;
999 if (val64 & VXGE_HW_RXMAC_PAUSE_CFG_PORT_RCV_EN)
1000 *rx = 1;
1001exit:
1002 return status;
1003}
1004
1005/*
1006 * vxge_hw_device_setpause_data - set/reset pause frame generation.
1007 * It can be used to set or reset Pause frame generation or reception
1008 * support of the NIC.
1009 */
1010
1011enum vxge_hw_status vxge_hw_device_setpause_data(struct __vxge_hw_device *hldev,
1012 u32 port, u32 tx, u32 rx)
1013{
1014 u64 val64;
1015 enum vxge_hw_status status = VXGE_HW_OK;
1016
1017 if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) {
1018 status = VXGE_HW_ERR_INVALID_DEVICE;
1019 goto exit;
1020 }
1021
1022 if (port > VXGE_HW_MAC_MAX_MAC_PORT_ID) {
1023 status = VXGE_HW_ERR_INVALID_PORT;
1024 goto exit;
1025 }
1026
92cdd7c3
SH		 1027 status = __vxge_hw_device_is_privilaged(hldev->host_type,
1028 hldev->func_id);
40a3a915
RV		 1029 if (status != VXGE_HW_OK)
1030 goto exit;
1031
1032 val64 = readq(&hldev->mrpcim_reg->rxmac_pause_cfg_port[port]);
1033 if (tx)
1034 val64 |= VXGE_HW_RXMAC_PAUSE_CFG_PORT_GEN_EN;
1035 else
1036 val64 &= ~VXGE_HW_RXMAC_PAUSE_CFG_PORT_GEN_EN;
1037 if (rx)
1038 val64 |= VXGE_HW_RXMAC_PAUSE_CFG_PORT_RCV_EN;
1039 else
1040 val64 &= ~VXGE_HW_RXMAC_PAUSE_CFG_PORT_RCV_EN;
1041
1042 writeq(val64, &hldev->mrpcim_reg->rxmac_pause_cfg_port[port]);
1043exit:
1044 return status;
1045}
1046
1047u16 vxge_hw_device_link_width_get(struct __vxge_hw_device *hldev)
1048{
1049 int link_width, exp_cap;
1050 u16 lnk;
1051
1052 exp_cap = pci_find_capability(hldev->pdev, PCI_CAP_ID_EXP);
1053 pci_read_config_word(hldev->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
1054 link_width = (lnk & VXGE_HW_PCI_EXP_LNKCAP_LNK_WIDTH) >> 4;
1055 return link_width;
1056}
1057
1058/*
1059 * __vxge_hw_ring_block_memblock_idx - Return the memblock index
1060 * This function returns the index of memory block
1061 */
1062static inline u32
1063__vxge_hw_ring_block_memblock_idx(u8 *block)
1064{
1065 return (u32)*((u64 *)(block + VXGE_HW_RING_MEMBLOCK_IDX_OFFSET));
1066}
1067
1068/*
1069 * __vxge_hw_ring_block_memblock_idx_set - Sets the memblock index
1070 * This function sets index to a memory block
1071 */
1072static inline void
1073__vxge_hw_ring_block_memblock_idx_set(u8 *block, u32 memblock_idx)
1074{
1075 *((u64 *)(block + VXGE_HW_RING_MEMBLOCK_IDX_OFFSET)) = memblock_idx;
1076}
1077
1078/*
1079 * __vxge_hw_ring_block_next_pointer_set - Sets the next block pointer
1080 * in RxD block
1081 * Sets the next block pointer in RxD block
1082 */
1083static inline void
1084__vxge_hw_ring_block_next_pointer_set(u8 *block, dma_addr_t dma_next)
1085{
1086 *((u64 *)(block + VXGE_HW_RING_NEXT_BLOCK_POINTER_OFFSET)) = dma_next;
1087}
1088
1089/*
1090 * __vxge_hw_ring_first_block_address_get - Returns the dma address of the
1091 * first block
1092 * Returns the dma address of the first RxD block
1093 */
1094u64 __vxge_hw_ring_first_block_address_get(struct __vxge_hw_ring *ring)
1095{
1096 struct vxge_hw_mempool_dma *dma_object;
1097
1098 dma_object = ring->mempool->memblocks_dma_arr;
1099 vxge_assert(dma_object != NULL);
1100
1101 return dma_object->addr;
1102}
1103
1104/*
1105 * __vxge_hw_ring_item_dma_addr - Return the dma address of an item
1106 * This function returns the dma address of a given item
1107 */
1108static dma_addr_t __vxge_hw_ring_item_dma_addr(struct vxge_hw_mempool *mempoolh,
1109 void *item)
1110{
1111 u32 memblock_idx;
1112 void *memblock;
1113 struct vxge_hw_mempool_dma *memblock_dma_object;
1114 ptrdiff_t dma_item_offset;
1115
1116 /* get owner memblock index */
1117 memblock_idx = __vxge_hw_ring_block_memblock_idx(item);
1118
1119 /* get owner memblock by memblock index */
1120 memblock = mempoolh->memblocks_arr[memblock_idx];
1121
1122 /* get memblock DMA object by memblock index */
1123 memblock_dma_object = mempoolh->memblocks_dma_arr + memblock_idx;
1124
1125 /* calculate offset in the memblock of this item */
1126 dma_item_offset = (u8 *)item - (u8 *)memblock;
1127
1128 return memblock_dma_object->addr + dma_item_offset;
1129}
1130
1131/*
1132 * __vxge_hw_ring_rxdblock_link - Link the RxD blocks
1133 * This function returns the dma address of a given item
1134 */
1135static void __vxge_hw_ring_rxdblock_link(struct vxge_hw_mempool *mempoolh,
1136 struct __vxge_hw_ring *ring, u32 from,
1137 u32 to)
1138{
1139 u8 *to_item , *from_item;
1140 dma_addr_t to_dma;
1141
1142 /* get "from" RxD block */
1143 from_item = mempoolh->items_arr[from];
1144 vxge_assert(from_item);
1145
1146 /* get "to" RxD block */
1147 to_item = mempoolh->items_arr[to];
1148 vxge_assert(to_item);
1149
1150 /* return address of the beginning of previous RxD block */
1151 to_dma = __vxge_hw_ring_item_dma_addr(mempoolh, to_item);
1152
1153 /* set next pointer for this RxD block to point on
1154 * previous item's DMA start address */
1155 __vxge_hw_ring_block_next_pointer_set(from_item, to_dma);
1156}
1157
1158/*
1159 * __vxge_hw_ring_mempool_item_alloc - Allocate List blocks for RxD
1160 * block callback
1161 * This function is callback passed to __vxge_hw_mempool_create to create memory
1162 * pool for RxD block
1163 */
1164static void
1165__vxge_hw_ring_mempool_item_alloc(struct vxge_hw_mempool *mempoolh,
1166 u32 memblock_index,
1167 struct vxge_hw_mempool_dma *dma_object,
1168 u32 index, u32 is_last)
1169{
1170 u32 i;
1171 void *item = mempoolh->items_arr[index];
1172 struct __vxge_hw_ring *ring =
1173 (struct __vxge_hw_ring *)mempoolh->userdata;
1174
1175 /* format rxds array */
1176 for (i = 0; i < ring->rxds_per_block; i++) {
1177 void *rxdblock_priv;
1178 void *uld_priv;
1179 struct vxge_hw_ring_rxd_1 *rxdp;
1180
1181 u32 reserve_index = ring->channel.reserve_ptr -
1182 (index * ring->rxds_per_block + i + 1);
1183 u32 memblock_item_idx;
1184
1185 ring->channel.reserve_arr[reserve_index] = ((u8 *)item) +
1186 i * ring->rxd_size;
1187
1188 /* Note: memblock_item_idx is index of the item within
1189 * the memblock. For instance, in case of three RxD-blocks
1190 * per memblock this value can be 0, 1 or 2. */
1191 rxdblock_priv = __vxge_hw_mempool_item_priv(mempoolh,
1192 memblock_index, item,
1193 &memblock_item_idx);
1194
1195 rxdp = (struct vxge_hw_ring_rxd_1 *)
1196 ring->channel.reserve_arr[reserve_index];
1197
1198 uld_priv = ((u8 *)rxdblock_priv + ring->rxd_priv_size * i);
1199
1200 /* pre-format Host_Control */
1201 rxdp->host_control = (u64)(size_t)uld_priv;
1202 }
1203
1204 __vxge_hw_ring_block_memblock_idx_set(item, memblock_index);
1205
1206 if (is_last) {
1207 /* link last one with first one */
1208 __vxge_hw_ring_rxdblock_link(mempoolh, ring, index, 0);
1209 }
1210
1211 if (index > 0) {
1212 /* link this RxD block with previous one */
1213 __vxge_hw_ring_rxdblock_link(mempoolh, ring, index - 1, index);
1214 }
1215
1216 return;
1217}
1218
1219/*
1220 * __vxge_hw_ring_initial_replenish - Initial replenish of RxDs
1221 * This function replenishes the RxDs from reserve array to work array
1222 */
1223enum vxge_hw_status
1224vxge_hw_ring_replenish(struct __vxge_hw_ring *ring, u16 min_flag)
1225{
1226 void *rxd;
1227 int i = 0;
1228 struct __vxge_hw_channel *channel;
1229 enum vxge_hw_status status = VXGE_HW_OK;
1230
1231 channel = &ring->channel;
1232
1233 while (vxge_hw_channel_dtr_count(channel) > 0) {
1234
1235 status = vxge_hw_ring_rxd_reserve(ring, &rxd);
1236
1237 vxge_assert(status == VXGE_HW_OK);
1238
1239 if (ring->rxd_init) {
1240 status = ring->rxd_init(rxd, channel->userdata);
1241 if (status != VXGE_HW_OK) {
1242 vxge_hw_ring_rxd_free(ring, rxd);
1243 goto exit;
1244 }
1245 }
1246
1247 vxge_hw_ring_rxd_post(ring, rxd);
1248 if (min_flag) {
1249 i++;
1250 if (i == VXGE_HW_RING_MIN_BUFF_ALLOCATION)
1251 break;
1252 }
1253 }
1254 status = VXGE_HW_OK;
1255exit:
1256 return status;
1257}
1258
1259/*
1260 * __vxge_hw_ring_create - Create a Ring
1261 * This function creates Ring and initializes it.
1262 *
1263 */
1264enum vxge_hw_status
1265__vxge_hw_ring_create(struct __vxge_hw_vpath_handle *vp,
1266 struct vxge_hw_ring_attr *attr)
1267{
1268 enum vxge_hw_status status = VXGE_HW_OK;
1269 struct __vxge_hw_ring *ring;
1270 u32 ring_length;
1271 struct vxge_hw_ring_config *config;
1272 struct __vxge_hw_device *hldev;
1273 u32 vp_id;
1274 struct vxge_hw_mempool_cbs ring_mp_callback;
1275
1276 if ((vp == NULL) || (attr == NULL)) {
1277 status = VXGE_HW_FAIL;
1278 goto exit;
1279 }
1280
1281 hldev = vp->vpath->hldev;
1282 vp_id = vp->vpath->vp_id;
1283
1284 config = &hldev->config.vp_config[vp_id].ring;
1285
1286 ring_length = config->ring_blocks *
1287 vxge_hw_ring_rxds_per_block_get(config->buffer_mode);
1288
1289 ring = (struct __vxge_hw_ring *)__vxge_hw_channel_allocate(vp,
1290 VXGE_HW_CHANNEL_TYPE_RING,
1291 ring_length,
1292 attr->per_rxd_space,
1293 attr->userdata);
1294
1295 if (ring == NULL) {
1296 status = VXGE_HW_ERR_OUT_OF_MEMORY;
1297 goto exit;
1298 }
1299
1300 vp->vpath->ringh = ring;
1301 ring->vp_id = vp_id;
1302 ring->vp_reg = vp->vpath->vp_reg;
1303 ring->common_reg = hldev->common_reg;
1304 ring->stats = &vp->vpath->sw_stats->ring_stats;
1305 ring->config = config;
1306 ring->callback = attr->callback;
1307 ring->rxd_init = attr->rxd_init;
1308 ring->rxd_term = attr->rxd_term;
1309 ring->buffer_mode = config->buffer_mode;
1310 ring->rxds_limit = config->rxds_limit;
1311
1312 ring->rxd_size = vxge_hw_ring_rxd_size_get(config->buffer_mode);
1313 ring->rxd_priv_size =
1314 sizeof(struct __vxge_hw_ring_rxd_priv) + attr->per_rxd_space;
1315 ring->per_rxd_space = attr->per_rxd_space;
1316
1317 ring->rxd_priv_size =
1318 ((ring->rxd_priv_size + VXGE_CACHE_LINE_SIZE - 1) /
1319 VXGE_CACHE_LINE_SIZE) * VXGE_CACHE_LINE_SIZE;
1320
1321 /* how many RxDs can fit into one block. Depends on configured
1322 * buffer_mode. */
1323 ring->rxds_per_block =
1324 vxge_hw_ring_rxds_per_block_get(config->buffer_mode);
1325
1326 /* calculate actual RxD block private size */
1327 ring->rxdblock_priv_size = ring->rxd_priv_size * ring->rxds_per_block;
1328 ring_mp_callback.item_func_alloc = __vxge_hw_ring_mempool_item_alloc;
1329 ring->mempool = __vxge_hw_mempool_create(hldev,
1330 VXGE_HW_BLOCK_SIZE,
1331 VXGE_HW_BLOCK_SIZE,
1332 ring->rxdblock_priv_size,
1333 ring->config->ring_blocks,
1334 ring->config->ring_blocks,
1335 &ring_mp_callback,
1336 ring);
1337
1338 if (ring->mempool == NULL) {
1339 __vxge_hw_ring_delete(vp);
1340 return VXGE_HW_ERR_OUT_OF_MEMORY;
1341 }
1342
1343 status = __vxge_hw_channel_initialize(&ring->channel);
1344 if (status != VXGE_HW_OK) {
1345 __vxge_hw_ring_delete(vp);
1346 goto exit;
1347 }
1348
1349 /* Note:
1350 * Specifying rxd_init callback means two things:
1351 * 1) rxds need to be initialized by driver at channel-open time;
1352 * 2) rxds need to be posted at channel-open time
1353 * (that's what the initial_replenish() below does)
1354 * Currently we don't have a case when the 1) is done without the 2).
1355 */
1356 if (ring->rxd_init) {
1357 status = vxge_hw_ring_replenish(ring, 1);
1358 if (status != VXGE_HW_OK) {
1359 __vxge_hw_ring_delete(vp);
1360 goto exit;
1361 }
1362 }
1363
1364 /* initial replenish will increment the counter in its post() routine,
1365 * we have to reset it */
1366 ring->stats->common_stats.usage_cnt = 0;
1367exit:
1368 return status;
1369}
1370
1371/*
1372 * __vxge_hw_ring_abort - Returns the RxD
1373 * This function terminates the RxDs of ring
1374 */
1375enum vxge_hw_status __vxge_hw_ring_abort(struct __vxge_hw_ring *ring)
1376{
1377 void *rxdh;
1378 struct __vxge_hw_channel *channel;
1379
1380 channel = &ring->channel;
1381
1382 for (;;) {
1383 vxge_hw_channel_dtr_try_complete(channel, &rxdh);
1384
1385 if (rxdh == NULL)
1386 break;
1387
1388 vxge_hw_channel_dtr_complete(channel);
1389
1390 if (ring->rxd_term)
1391 ring->rxd_term(rxdh, VXGE_HW_RXD_STATE_POSTED,
1392 channel->userdata);
1393
1394 vxge_hw_channel_dtr_free(channel, rxdh);
1395 }
1396
1397 return VXGE_HW_OK;
1398}
1399
1400/*
1401 * __vxge_hw_ring_reset - Resets the ring
1402 * This function resets the ring during vpath reset operation
1403 */
1404enum vxge_hw_status __vxge_hw_ring_reset(struct __vxge_hw_ring *ring)
1405{
1406 enum vxge_hw_status status = VXGE_HW_OK;
1407 struct __vxge_hw_channel *channel;
1408
1409 channel = &ring->channel;
1410
1411 __vxge_hw_ring_abort(ring);
1412
1413 status = __vxge_hw_channel_reset(channel);
1414
1415 if (status != VXGE_HW_OK)
1416 goto exit;
1417
1418 if (ring->rxd_init) {
1419 status = vxge_hw_ring_replenish(ring, 1);
1420 if (status != VXGE_HW_OK)
1421 goto exit;
1422 }
1423exit:
1424 return status;
1425}
1426
1427/*
1428 * __vxge_hw_ring_delete - Removes the ring
1429 * This function freeup the memory pool and removes the ring
1430 */
1431enum vxge_hw_status __vxge_hw_ring_delete(struct __vxge_hw_vpath_handle *vp)
1432{
1433 struct __vxge_hw_ring *ring = vp->vpath->ringh;
1434
1435 __vxge_hw_ring_abort(ring);
1436
1437 if (ring->mempool)
1438 __vxge_hw_mempool_destroy(ring->mempool);
1439
1440 vp->vpath->ringh = NULL;
1441 __vxge_hw_channel_free(&ring->channel);
1442
1443 return VXGE_HW_OK;
1444}
1445
1446/*
1447 * __vxge_hw_mempool_grow
1448 * Will resize mempool up to %num_allocate value.
1449 */
1450enum vxge_hw_status
1451__vxge_hw_mempool_grow(struct vxge_hw_mempool *mempool, u32 num_allocate,
1452 u32 *num_allocated)
1453{
1454 u32 i, first_time = mempool->memblocks_allocated == 0 ? 1 : 0;
1455 u32 n_items = mempool->items_per_memblock;
1456 u32 start_block_idx = mempool->memblocks_allocated;
1457 u32 end_block_idx = mempool->memblocks_allocated + num_allocate;
1458 enum vxge_hw_status status = VXGE_HW_OK;
1459
1460 *num_allocated = 0;
1461
1462 if (end_block_idx > mempool->memblocks_max) {
1463 status = VXGE_HW_ERR_OUT_OF_MEMORY;
1464 goto exit;
1465 }
1466
1467 for (i = start_block_idx; i < end_block_idx; i++) {
1468 u32 j;
1469 u32 is_last = ((end_block_idx - 1) == i);
1470 struct vxge_hw_mempool_dma *dma_object =
1471 mempool->memblocks_dma_arr + i;
1472 void *the_memblock;
1473
1474 /* allocate memblock's private part. Each DMA memblock
1475 * has a space allocated for item's private usage upon
1476 * mempool's user request. Each time mempool grows, it will
1477 * allocate new memblock and its private part at once.
1478 * This helps to minimize memory usage a lot. */
1479 mempool->memblocks_priv_arr[i] =
1480 vmalloc(mempool->items_priv_size * n_items);
1481 if (mempool->memblocks_priv_arr[i] == NULL) {
1482 status = VXGE_HW_ERR_OUT_OF_MEMORY;
1483 goto exit;
1484 }
1485
1486 memset(mempool->memblocks_priv_arr[i], 0,
1487 mempool->items_priv_size * n_items);
1488
1489 /* allocate DMA-capable memblock */
1490 mempool->memblocks_arr[i] =
1491 __vxge_hw_blockpool_malloc(mempool->devh,
1492 mempool->memblock_size, dma_object);
1493 if (mempool->memblocks_arr[i] == NULL) {
1494 vfree(mempool->memblocks_priv_arr[i]);
1495 status = VXGE_HW_ERR_OUT_OF_MEMORY;
1496 goto exit;
1497 }
1498
1499 (*num_allocated)++;
1500 mempool->memblocks_allocated++;
1501
1502 memset(mempool->memblocks_arr[i], 0, mempool->memblock_size);
1503
1504 the_memblock = mempool->memblocks_arr[i];
1505
1506 /* fill the items hash array */
1507 for (j = 0; j < n_items; j++) {
1508 u32 index = i * n_items + j;
1509
1510 if (first_time && index >= mempool->items_initial)
1511 break;
1512
1513 mempool->items_arr[index] =
1514 ((char *)the_memblock + j*mempool->item_size);
1515
1516 /* let caller to do more job on each item */
1517 if (mempool->item_func_alloc != NULL)
1518 mempool->item_func_alloc(mempool, i,
1519 dma_object, index, is_last);
1520
1521 mempool->items_current = index + 1;
1522 }
1523
1524 if (first_time && mempool->items_current ==
1525 mempool->items_initial)
1526 break;
1527 }
1528exit:
1529 return status;
1530}
1531
1532/*
1533 * vxge_hw_mempool_create
1534 * This function will create memory pool object. Pool may grow but will
1535 * never shrink. Pool consists of number of dynamically allocated blocks
1536 * with size enough to hold %items_initial number of items. Memory is
1537 * DMA-able but client must map/unmap before interoperating with the device.
1538 */
1539struct vxge_hw_mempool*
1540__vxge_hw_mempool_create(
1541 struct __vxge_hw_device *devh,
1542 u32 memblock_size,
1543 u32 item_size,
1544 u32 items_priv_size,
1545 u32 items_initial,
1546 u32 items_max,
1547 struct vxge_hw_mempool_cbs *mp_callback,
1548 void *userdata)
1549{
1550 enum vxge_hw_status status = VXGE_HW_OK;
1551 u32 memblocks_to_allocate;
1552 struct vxge_hw_mempool *mempool = NULL;
1553 u32 allocated;
1554
1555 if (memblock_size < item_size) {
1556 status = VXGE_HW_FAIL;
1557 goto exit;
1558 }
1559
1560 mempool = (struct vxge_hw_mempool *)
1561 vmalloc(sizeof(struct vxge_hw_mempool));
1562 if (mempool == NULL) {
1563 status = VXGE_HW_ERR_OUT_OF_MEMORY;
1564 goto exit;
1565 }
1566 memset(mempool, 0, sizeof(struct vxge_hw_mempool));
1567
1568 mempool->devh = devh;
1569 mempool->memblock_size = memblock_size;
1570 mempool->items_max = items_max;
1571 mempool->items_initial = items_initial;
1572 mempool->item_size = item_size;
1573 mempool->items_priv_size = items_priv_size;
1574 mempool->item_func_alloc = mp_callback->item_func_alloc;
1575 mempool->userdata = userdata;
1576
1577 mempool->memblocks_allocated = 0;
1578
1579 mempool->items_per_memblock = memblock_size / item_size;
1580
1581 mempool->memblocks_max = (items_max + mempool->items_per_memblock - 1) /
1582 mempool->items_per_memblock;
1583
1584 /* allocate array of memblocks */
1585 mempool->memblocks_arr =
1586 (void **) vmalloc(sizeof(void *) * mempool->memblocks_max);
1587 if (mempool->memblocks_arr == NULL) {
1588 __vxge_hw_mempool_destroy(mempool);
1589 status = VXGE_HW_ERR_OUT_OF_MEMORY;
1590 mempool = NULL;
1591 goto exit;
1592 }
1593 memset(mempool->memblocks_arr, 0,
1594 sizeof(void *) * mempool->memblocks_max);
1595
1596 /* allocate array of private parts of items per memblocks */
1597 mempool->memblocks_priv_arr =
1598 (void **) vmalloc(sizeof(void *) * mempool->memblocks_max);
1599 if (mempool->memblocks_priv_arr == NULL) {
1600 __vxge_hw_mempool_destroy(mempool);
1601 status = VXGE_HW_ERR_OUT_OF_MEMORY;
1602 mempool = NULL;
1603 goto exit;
1604 }
1605 memset(mempool->memblocks_priv_arr, 0,
1606 sizeof(void *) * mempool->memblocks_max);
1607
1608 /* allocate array of memblocks DMA objects */
1609 mempool->memblocks_dma_arr = (struct vxge_hw_mempool_dma *)
1610 vmalloc(sizeof(struct vxge_hw_mempool_dma) *
1611 mempool->memblocks_max);
1612
1613 if (mempool->memblocks_dma_arr == NULL) {
1614 __vxge_hw_mempool_destroy(mempool);
1615 status = VXGE_HW_ERR_OUT_OF_MEMORY;
1616 mempool = NULL;
1617 goto exit;
1618 }
1619 memset(mempool->memblocks_dma_arr, 0,
1620 sizeof(struct vxge_hw_mempool_dma) *
1621 mempool->memblocks_max);
1622
1623 /* allocate hash array of items */
1624 mempool->items_arr =
1625 (void **) vmalloc(sizeof(void *) * mempool->items_max);
1626 if (mempool->items_arr == NULL) {
1627 __vxge_hw_mempool_destroy(mempool);
1628 status = VXGE_HW_ERR_OUT_OF_MEMORY;
1629 mempool = NULL;
1630 goto exit;
1631 }
1632 memset(mempool->items_arr, 0, sizeof(void *) * mempool->items_max);
1633
1634 /* calculate initial number of memblocks */
1635 memblocks_to_allocate = (mempool->items_initial +
1636 mempool->items_per_memblock - 1) /
1637 mempool->items_per_memblock;
1638
1639 /* pre-allocate the mempool */
1640 status = __vxge_hw_mempool_grow(mempool, memblocks_to_allocate,
1641 &allocated);
1642 if (status != VXGE_HW_OK) {
1643 __vxge_hw_mempool_destroy(mempool);
1644 status = VXGE_HW_ERR_OUT_OF_MEMORY;
1645 mempool = NULL;
1646 goto exit;
1647 }
1648
1649exit:
1650 return mempool;
1651}
1652
1653/*
1654 * vxge_hw_mempool_destroy
1655 */
1656void __vxge_hw_mempool_destroy(struct vxge_hw_mempool *mempool)
1657{
1658 u32 i, j;
1659 struct __vxge_hw_device *devh = mempool->devh;
1660
1661 for (i = 0; i < mempool->memblocks_allocated; i++) {
1662 struct vxge_hw_mempool_dma *dma_object;
1663
1664 vxge_assert(mempool->memblocks_arr[i]);
1665 vxge_assert(mempool->memblocks_dma_arr + i);
1666
1667 dma_object = mempool->memblocks_dma_arr + i;
1668
1669 for (j = 0; j < mempool->items_per_memblock; j++) {
1670 u32 index = i * mempool->items_per_memblock + j;
1671
1672 /* to skip last partially filled(if any) memblock */
1673 if (index >= mempool->items_current)
1674 break;
1675 }
1676
1677 vfree(mempool->memblocks_priv_arr[i]);
1678
1679 __vxge_hw_blockpool_free(devh, mempool->memblocks_arr[i],
1680 mempool->memblock_size, dma_object);
1681 }
1682
50d36a93 1683 vfree(mempool->items_arr);
40a3a915 1684
50d36a93 1685 vfree(mempool->memblocks_dma_arr);
40a3a915 1686
50d36a93 1687 vfree(mempool->memblocks_priv_arr);
40a3a915 1688
50d36a93 1689 vfree(mempool->memblocks_arr);
40a3a915
RV		 1690
1691 vfree(mempool);
1692}
1693
1694/*
1695 * __vxge_hw_device_fifo_config_check - Check fifo configuration.
1696 * Check the fifo configuration
1697 */
1698enum vxge_hw_status
1699__vxge_hw_device_fifo_config_check(struct vxge_hw_fifo_config *fifo_config)
1700{
1701 if ((fifo_config->fifo_blocks < VXGE_HW_MIN_FIFO_BLOCKS) ||
1702 (fifo_config->fifo_blocks > VXGE_HW_MAX_FIFO_BLOCKS))
1703 return VXGE_HW_BADCFG_FIFO_BLOCKS;
1704
1705 return VXGE_HW_OK;
1706}
1707
1708/*
1709 * __vxge_hw_device_vpath_config_check - Check vpath configuration.
1710 * Check the vpath configuration
1711 */
1712enum vxge_hw_status
1713__vxge_hw_device_vpath_config_check(struct vxge_hw_vp_config *vp_config)
1714{
1715 enum vxge_hw_status status;
1716
1717 if ((vp_config->min_bandwidth < VXGE_HW_VPATH_BANDWIDTH_MIN) ||
1718 (vp_config->min_bandwidth >
1719 VXGE_HW_VPATH_BANDWIDTH_MAX))
1720 return VXGE_HW_BADCFG_VPATH_MIN_BANDWIDTH;
1721
1722 status = __vxge_hw_device_fifo_config_check(&vp_config->fifo);
1723 if (status != VXGE_HW_OK)
1724 return status;
1725
1726 if ((vp_config->mtu != VXGE_HW_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU) &&
1727 ((vp_config->mtu < VXGE_HW_VPATH_MIN_INITIAL_MTU) ||
1728 (vp_config->mtu > VXGE_HW_VPATH_MAX_INITIAL_MTU)))
1729 return VXGE_HW_BADCFG_VPATH_MTU;
1730
1731 if ((vp_config->rpa_strip_vlan_tag !=
1732 VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT) &&
1733 (vp_config->rpa_strip_vlan_tag !=
1734 VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_ENABLE) &&
1735 (vp_config->rpa_strip_vlan_tag !=
1736 VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_DISABLE))
1737 return VXGE_HW_BADCFG_VPATH_RPA_STRIP_VLAN_TAG;
1738
1739 return VXGE_HW_OK;
1740}
1741
1742/*
1743 * __vxge_hw_device_config_check - Check device configuration.
1744 * Check the device configuration
1745 */
1746enum vxge_hw_status
1747__vxge_hw_device_config_check(struct vxge_hw_device_config *new_config)
1748{
1749 u32 i;
1750 enum vxge_hw_status status;
1751
1752 if ((new_config->intr_mode != VXGE_HW_INTR_MODE_IRQLINE) &&
1753 (new_config->intr_mode != VXGE_HW_INTR_MODE_MSIX) &&
1754 (new_config->intr_mode != VXGE_HW_INTR_MODE_MSIX_ONE_SHOT) &&
1755 (new_config->intr_mode != VXGE_HW_INTR_MODE_DEF))
1756 return VXGE_HW_BADCFG_INTR_MODE;
1757
1758 if ((new_config->rts_mac_en != VXGE_HW_RTS_MAC_DISABLE) &&
1759 (new_config->rts_mac_en != VXGE_HW_RTS_MAC_ENABLE))
1760 return VXGE_HW_BADCFG_RTS_MAC_EN;
1761
1762 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
1763 status = __vxge_hw_device_vpath_config_check(
1764 &new_config->vp_config[i]);
1765 if (status != VXGE_HW_OK)
1766 return status;
1767 }
1768
1769 return VXGE_HW_OK;
1770}
1771
1772/*
1773 * vxge_hw_device_config_default_get - Initialize device config with defaults.
1774 * Initialize Titan device config with default values.
1775 */
1776enum vxge_hw_status __devinit
1777vxge_hw_device_config_default_get(struct vxge_hw_device_config *device_config)
1778{
1779 u32 i;
1780
1781 device_config->dma_blockpool_initial =
1782 VXGE_HW_INITIAL_DMA_BLOCK_POOL_SIZE;
1783 device_config->dma_blockpool_max = VXGE_HW_MAX_DMA_BLOCK_POOL_SIZE;
1784 device_config->intr_mode = VXGE_HW_INTR_MODE_DEF;
1785 device_config->rth_en = VXGE_HW_RTH_DEFAULT;
1786 device_config->rth_it_type = VXGE_HW_RTH_IT_TYPE_DEFAULT;
1787 device_config->device_poll_millis = VXGE_HW_DEF_DEVICE_POLL_MILLIS;
1788 device_config->rts_mac_en = VXGE_HW_RTS_MAC_DEFAULT;
1789
1790 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
1791
1792 device_config->vp_config[i].vp_id = i;
1793
1794 device_config->vp_config[i].min_bandwidth =
1795 VXGE_HW_VPATH_BANDWIDTH_DEFAULT;
1796
1797 device_config->vp_config[i].ring.enable = VXGE_HW_RING_DEFAULT;
1798
1799 device_config->vp_config[i].ring.ring_blocks =
1800 VXGE_HW_DEF_RING_BLOCKS;
1801
1802 device_config->vp_config[i].ring.buffer_mode =
1803 VXGE_HW_RING_RXD_BUFFER_MODE_DEFAULT;
1804
1805 device_config->vp_config[i].ring.scatter_mode =
1806 VXGE_HW_RING_SCATTER_MODE_USE_FLASH_DEFAULT;
1807
1808 device_config->vp_config[i].ring.rxds_limit =
1809 VXGE_HW_DEF_RING_RXDS_LIMIT;
1810
1811 device_config->vp_config[i].fifo.enable = VXGE_HW_FIFO_ENABLE;
1812
1813 device_config->vp_config[i].fifo.fifo_blocks =
1814 VXGE_HW_MIN_FIFO_BLOCKS;
1815
1816 device_config->vp_config[i].fifo.max_frags =
1817 VXGE_HW_MAX_FIFO_FRAGS;
1818
1819 device_config->vp_config[i].fifo.memblock_size =
1820 VXGE_HW_DEF_FIFO_MEMBLOCK_SIZE;
1821
1822 device_config->vp_config[i].fifo.alignment_size =
1823 VXGE_HW_DEF_FIFO_ALIGNMENT_SIZE;
1824
1825 device_config->vp_config[i].fifo.intr =
1826 VXGE_HW_FIFO_QUEUE_INTR_DEFAULT;
1827
1828 device_config->vp_config[i].fifo.no_snoop_bits =
1829 VXGE_HW_FIFO_NO_SNOOP_DEFAULT;
1830 device_config->vp_config[i].tti.intr_enable =
1831 VXGE_HW_TIM_INTR_DEFAULT;
1832
1833 device_config->vp_config[i].tti.btimer_val =
1834 VXGE_HW_USE_FLASH_DEFAULT;
1835
1836 device_config->vp_config[i].tti.timer_ac_en =
1837 VXGE_HW_USE_FLASH_DEFAULT;
1838
1839 device_config->vp_config[i].tti.timer_ci_en =
1840 VXGE_HW_USE_FLASH_DEFAULT;
1841
1842 device_config->vp_config[i].tti.timer_ri_en =
1843 VXGE_HW_USE_FLASH_DEFAULT;
1844
1845 device_config->vp_config[i].tti.rtimer_val =
1846 VXGE_HW_USE_FLASH_DEFAULT;
1847
1848 device_config->vp_config[i].tti.util_sel =
1849 VXGE_HW_USE_FLASH_DEFAULT;
1850
1851 device_config->vp_config[i].tti.ltimer_val =
1852 VXGE_HW_USE_FLASH_DEFAULT;
1853
1854 device_config->vp_config[i].tti.urange_a =
1855 VXGE_HW_USE_FLASH_DEFAULT;
1856
1857 device_config->vp_config[i].tti.uec_a =
1858 VXGE_HW_USE_FLASH_DEFAULT;
1859
1860 device_config->vp_config[i].tti.urange_b =
1861 VXGE_HW_USE_FLASH_DEFAULT;
1862
1863 device_config->vp_config[i].tti.uec_b =
1864 VXGE_HW_USE_FLASH_DEFAULT;
1865
1866 device_config->vp_config[i].tti.urange_c =
1867 VXGE_HW_USE_FLASH_DEFAULT;
1868
1869 device_config->vp_config[i].tti.uec_c =
1870 VXGE_HW_USE_FLASH_DEFAULT;
1871
1872 device_config->vp_config[i].tti.uec_d =
1873 VXGE_HW_USE_FLASH_DEFAULT;
1874
1875 device_config->vp_config[i].rti.intr_enable =
1876 VXGE_HW_TIM_INTR_DEFAULT;
1877
1878 device_config->vp_config[i].rti.btimer_val =
1879 VXGE_HW_USE_FLASH_DEFAULT;
1880
1881 device_config->vp_config[i].rti.timer_ac_en =
1882 VXGE_HW_USE_FLASH_DEFAULT;
1883
1884 device_config->vp_config[i].rti.timer_ci_en =
1885 VXGE_HW_USE_FLASH_DEFAULT;
1886
1887 device_config->vp_config[i].rti.timer_ri_en =
1888 VXGE_HW_USE_FLASH_DEFAULT;
1889
1890 device_config->vp_config[i].rti.rtimer_val =
1891 VXGE_HW_USE_FLASH_DEFAULT;
1892
1893 device_config->vp_config[i].rti.util_sel =
1894 VXGE_HW_USE_FLASH_DEFAULT;
1895
1896 device_config->vp_config[i].rti.ltimer_val =
1897 VXGE_HW_USE_FLASH_DEFAULT;
1898
1899 device_config->vp_config[i].rti.urange_a =
1900 VXGE_HW_USE_FLASH_DEFAULT;
1901
1902 device_config->vp_config[i].rti.uec_a =
1903 VXGE_HW_USE_FLASH_DEFAULT;
1904
1905 device_config->vp_config[i].rti.urange_b =
1906 VXGE_HW_USE_FLASH_DEFAULT;
1907
1908 device_config->vp_config[i].rti.uec_b =
1909 VXGE_HW_USE_FLASH_DEFAULT;
1910
1911 device_config->vp_config[i].rti.urange_c =
1912 VXGE_HW_USE_FLASH_DEFAULT;
1913
1914 device_config->vp_config[i].rti.uec_c =
1915 VXGE_HW_USE_FLASH_DEFAULT;
1916
1917 device_config->vp_config[i].rti.uec_d =
1918 VXGE_HW_USE_FLASH_DEFAULT;
1919
1920 device_config->vp_config[i].mtu =
1921 VXGE_HW_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU;
1922
1923 device_config->vp_config[i].rpa_strip_vlan_tag =
1924 VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT;
1925 }
1926
1927 return VXGE_HW_OK;
1928}
1929
1930/*
1931 * _hw_legacy_swapper_set - Set the swapper bits for the legacy secion.
1932 * Set the swapper bits appropriately for the lagacy section.
1933 */
1934enum vxge_hw_status
1935__vxge_hw_legacy_swapper_set(struct vxge_hw_legacy_reg __iomem *legacy_reg)
1936{
1937 u64 val64;
1938 enum vxge_hw_status status = VXGE_HW_OK;
1939
1940 val64 = readq(&legacy_reg->toc_swapper_fb);
1941
1942 wmb();
1943
1944 switch (val64) {
1945
1946 case VXGE_HW_SWAPPER_INITIAL_VALUE:
1947 return status;
1948
1949 case VXGE_HW_SWAPPER_BYTE_SWAPPED_BIT_FLIPPED:
1950 writeq(VXGE_HW_SWAPPER_READ_BYTE_SWAP_ENABLE,
1951 &legacy_reg->pifm_rd_swap_en);
1952 writeq(VXGE_HW_SWAPPER_READ_BIT_FLAP_ENABLE,
1953 &legacy_reg->pifm_rd_flip_en);
1954 writeq(VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE,
1955 &legacy_reg->pifm_wr_swap_en);
1956 writeq(VXGE_HW_SWAPPER_WRITE_BIT_FLAP_ENABLE,
1957 &legacy_reg->pifm_wr_flip_en);
1958 break;
1959
1960 case VXGE_HW_SWAPPER_BYTE_SWAPPED:
1961 writeq(VXGE_HW_SWAPPER_READ_BYTE_SWAP_ENABLE,
1962 &legacy_reg->pifm_rd_swap_en);
1963 writeq(VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE,
1964 &legacy_reg->pifm_wr_swap_en);
1965 break;
1966
1967 case VXGE_HW_SWAPPER_BIT_FLIPPED:
1968 writeq(VXGE_HW_SWAPPER_READ_BIT_FLAP_ENABLE,
1969 &legacy_reg->pifm_rd_flip_en);
1970 writeq(VXGE_HW_SWAPPER_WRITE_BIT_FLAP_ENABLE,
1971 &legacy_reg->pifm_wr_flip_en);
1972 break;
1973 }
1974
1975 wmb();
1976
1977 val64 = readq(&legacy_reg->toc_swapper_fb);
1978
1979 if (val64 != VXGE_HW_SWAPPER_INITIAL_VALUE)
1980 status = VXGE_HW_ERR_SWAPPER_CTRL;
1981
1982 return status;
1983}
1984
1985/*
1986 * __vxge_hw_vpath_swapper_set - Set the swapper bits for the vpath.
1987 * Set the swapper bits appropriately for the vpath.
1988 */
1989enum vxge_hw_status
1990__vxge_hw_vpath_swapper_set(struct vxge_hw_vpath_reg __iomem *vpath_reg)
1991{
1992#ifndef __BIG_ENDIAN
1993 u64 val64;
1994
1995 val64 = readq(&vpath_reg->vpath_general_cfg1);
1996 wmb();
1997 val64 |= VXGE_HW_VPATH_GENERAL_CFG1_CTL_BYTE_SWAPEN;
1998 writeq(val64, &vpath_reg->vpath_general_cfg1);
1999 wmb();
2000#endif
2001 return VXGE_HW_OK;
2002}
2003
2004/*
2005 * __vxge_hw_kdfc_swapper_set - Set the swapper bits for the kdfc.
2006 * Set the swapper bits appropriately for the vpath.
2007 */
2008enum vxge_hw_status
2009__vxge_hw_kdfc_swapper_set(
2010 struct vxge_hw_legacy_reg __iomem *legacy_reg,
2011 struct vxge_hw_vpath_reg __iomem *vpath_reg)
2012{
2013 u64 val64;
2014
2015 val64 = readq(&legacy_reg->pifm_wr_swap_en);
2016
2017 if (val64 == VXGE_HW_SWAPPER_WRITE_BYTE_SWAP_ENABLE) {
2018 val64 = readq(&vpath_reg->kdfcctl_cfg0);
2019 wmb();
2020
2021 val64 |= VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO0 |
2022 VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO1 |
2023 VXGE_HW_KDFCCTL_CFG0_BYTE_SWAPEN_FIFO2;
2024
2025 writeq(val64, &vpath_reg->kdfcctl_cfg0);
2026 wmb();
2027 }
2028
2029 return VXGE_HW_OK;
2030}
2031
2032/*
2033 * vxge_hw_mgmt_device_config - Retrieve device configuration.
2034 * Get device configuration. Permits to retrieve at run-time configuration
2035 * values that were used to initialize and configure the device.
2036 */
2037enum vxge_hw_status
2038vxge_hw_mgmt_device_config(struct __vxge_hw_device *hldev,
2039 struct vxge_hw_device_config *dev_config, int size)
2040{
2041
2042 if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC))
2043 return VXGE_HW_ERR_INVALID_DEVICE;
2044
2045 if (size != sizeof(struct vxge_hw_device_config))
2046 return VXGE_HW_ERR_VERSION_CONFLICT;
2047
2048 memcpy(dev_config, &hldev->config,
2049 sizeof(struct vxge_hw_device_config));
2050
2051 return VXGE_HW_OK;
2052}
2053
2054/*
2055 * vxge_hw_mgmt_reg_read - Read Titan register.
2056 */
2057enum vxge_hw_status
2058vxge_hw_mgmt_reg_read(struct __vxge_hw_device *hldev,
2059 enum vxge_hw_mgmt_reg_type type,
2060 u32 index, u32 offset, u64 *value)
2061{
2062 enum vxge_hw_status status = VXGE_HW_OK;
2063
2064 if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) {
2065 status = VXGE_HW_ERR_INVALID_DEVICE;
2066 goto exit;
2067 }
2068
2069 switch (type) {
2070 case vxge_hw_mgmt_reg_type_legacy:
2071 if (offset > sizeof(struct vxge_hw_legacy_reg) - 8) {
2072 status = VXGE_HW_ERR_INVALID_OFFSET;
2073 break;
2074 }
2075 *value = readq((void __iomem *)hldev->legacy_reg + offset);
2076 break;
2077 case vxge_hw_mgmt_reg_type_toc:
2078 if (offset > sizeof(struct vxge_hw_toc_reg) - 8) {
2079 status = VXGE_HW_ERR_INVALID_OFFSET;
2080 break;
2081 }
2082 *value = readq((void __iomem *)hldev->toc_reg + offset);
2083 break;
2084 case vxge_hw_mgmt_reg_type_common:
2085 if (offset > sizeof(struct vxge_hw_common_reg) - 8) {
2086 status = VXGE_HW_ERR_INVALID_OFFSET;
2087 break;
2088 }
2089 *value = readq((void __iomem *)hldev->common_reg + offset);
2090 break;
2091 case vxge_hw_mgmt_reg_type_mrpcim:
2092 if (!(hldev->access_rights &
2093 VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)) {
2094 status = VXGE_HW_ERR_PRIVILAGED_OPEARATION;
2095 break;
2096 }
2097 if (offset > sizeof(struct vxge_hw_mrpcim_reg) - 8) {
2098 status = VXGE_HW_ERR_INVALID_OFFSET;
2099 break;
2100 }
2101 *value = readq((void __iomem *)hldev->mrpcim_reg + offset);
2102 break;
2103 case vxge_hw_mgmt_reg_type_srpcim:
2104 if (!(hldev->access_rights &
2105 VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM)) {
2106 status = VXGE_HW_ERR_PRIVILAGED_OPEARATION;
2107 break;
2108 }
2109 if (index > VXGE_HW_TITAN_SRPCIM_REG_SPACES - 1) {
2110 status = VXGE_HW_ERR_INVALID_INDEX;
2111 break;
2112 }
2113 if (offset > sizeof(struct vxge_hw_srpcim_reg) - 8) {
2114 status = VXGE_HW_ERR_INVALID_OFFSET;
2115 break;
2116 }
2117 *value = readq((void __iomem *)hldev->srpcim_reg[index] +
2118 offset);
2119 break;
2120 case vxge_hw_mgmt_reg_type_vpmgmt:
2121 if ((index > VXGE_HW_TITAN_VPMGMT_REG_SPACES - 1) ||
2122 (!(hldev->vpath_assignments & vxge_mBIT(index)))) {
2123 status = VXGE_HW_ERR_INVALID_INDEX;
2124 break;
2125 }
2126 if (offset > sizeof(struct vxge_hw_vpmgmt_reg) - 8) {
2127 status = VXGE_HW_ERR_INVALID_OFFSET;
2128 break;
2129 }
2130 *value = readq((void __iomem *)hldev->vpmgmt_reg[index] +
2131 offset);
2132 break;
2133 case vxge_hw_mgmt_reg_type_vpath:
2134 if ((index > VXGE_HW_TITAN_VPATH_REG_SPACES - 1) ||
2135 (!(hldev->vpath_assignments & vxge_mBIT(index)))) {
2136 status = VXGE_HW_ERR_INVALID_INDEX;
2137 break;
2138 }
2139 if (index > VXGE_HW_TITAN_VPATH_REG_SPACES - 1) {
2140 status = VXGE_HW_ERR_INVALID_INDEX;
2141 break;
2142 }
2143 if (offset > sizeof(struct vxge_hw_vpath_reg) - 8) {
2144 status = VXGE_HW_ERR_INVALID_OFFSET;
2145 break;
2146 }
2147 *value = readq((void __iomem *)hldev->vpath_reg[index] +
2148 offset);
2149 break;
2150 default:
2151 status = VXGE_HW_ERR_INVALID_TYPE;
2152 break;
2153 }
2154
2155exit:
2156 return status;
2157}
2158
fa41fd10
SH		 2159/*
2160 * vxge_hw_vpath_strip_fcs_check - Check for FCS strip.
2161 */
2162enum vxge_hw_status
2163vxge_hw_vpath_strip_fcs_check(struct __vxge_hw_device *hldev, u64 vpath_mask)
2164{
2165 struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg;
2166 enum vxge_hw_status status = VXGE_HW_OK;
2167 int i = 0, j = 0;
2168
2169 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
2170 if (!((vpath_mask) & vxge_mBIT(i)))
2171 continue;
2172 vpmgmt_reg = hldev->vpmgmt_reg[i];
2173 for (j = 0; j < VXGE_HW_MAC_MAX_MAC_PORT_ID; j++) {
2174 if (readq(&vpmgmt_reg->rxmac_cfg0_port_vpmgmt_clone[j])
2175 & VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_STRIP_FCS)
2176 return VXGE_HW_FAIL;
2177 }
2178 }
2179 return status;
2180}
40a3a915
RV		 2181/*
2182 * vxge_hw_mgmt_reg_Write - Write Titan register.
2183 */
2184enum vxge_hw_status
2185vxge_hw_mgmt_reg_write(struct __vxge_hw_device *hldev,
2186 enum vxge_hw_mgmt_reg_type type,
2187 u32 index, u32 offset, u64 value)
2188{
2189 enum vxge_hw_status status = VXGE_HW_OK;
2190
2191 if ((hldev == NULL) || (hldev->magic != VXGE_HW_DEVICE_MAGIC)) {
2192 status = VXGE_HW_ERR_INVALID_DEVICE;
2193 goto exit;
2194 }
2195
2196 switch (type) {
2197 case vxge_hw_mgmt_reg_type_legacy:
2198 if (offset > sizeof(struct vxge_hw_legacy_reg) - 8) {
2199 status = VXGE_HW_ERR_INVALID_OFFSET;
2200 break;
2201 }
2202 writeq(value, (void __iomem *)hldev->legacy_reg + offset);
2203 break;
2204 case vxge_hw_mgmt_reg_type_toc:
2205 if (offset > sizeof(struct vxge_hw_toc_reg) - 8) {
2206 status = VXGE_HW_ERR_INVALID_OFFSET;
2207 break;
2208 }
2209 writeq(value, (void __iomem *)hldev->toc_reg + offset);
2210 break;
2211 case vxge_hw_mgmt_reg_type_common:
2212 if (offset > sizeof(struct vxge_hw_common_reg) - 8) {
2213 status = VXGE_HW_ERR_INVALID_OFFSET;
2214 break;
2215 }
2216 writeq(value, (void __iomem *)hldev->common_reg + offset);
2217 break;
2218 case vxge_hw_mgmt_reg_type_mrpcim:
2219 if (!(hldev->access_rights &
2220 VXGE_HW_DEVICE_ACCESS_RIGHT_MRPCIM)) {
2221 status = VXGE_HW_ERR_PRIVILAGED_OPEARATION;
2222 break;
2223 }
2224 if (offset > sizeof(struct vxge_hw_mrpcim_reg) - 8) {
2225 status = VXGE_HW_ERR_INVALID_OFFSET;
2226 break;
2227 }
2228 writeq(value, (void __iomem *)hldev->mrpcim_reg + offset);
2229 break;
2230 case vxge_hw_mgmt_reg_type_srpcim:
2231 if (!(hldev->access_rights &
2232 VXGE_HW_DEVICE_ACCESS_RIGHT_SRPCIM)) {
2233 status = VXGE_HW_ERR_PRIVILAGED_OPEARATION;
2234 break;
2235 }
2236 if (index > VXGE_HW_TITAN_SRPCIM_REG_SPACES - 1) {
2237 status = VXGE_HW_ERR_INVALID_INDEX;
2238 break;
2239 }
2240 if (offset > sizeof(struct vxge_hw_srpcim_reg) - 8) {
2241 status = VXGE_HW_ERR_INVALID_OFFSET;
2242 break;
2243 }
2244 writeq(value, (void __iomem *)hldev->srpcim_reg[index] +
2245 offset);
2246
2247 break;
2248 case vxge_hw_mgmt_reg_type_vpmgmt:
2249 if ((index > VXGE_HW_TITAN_VPMGMT_REG_SPACES - 1) ||
2250 (!(hldev->vpath_assignments & vxge_mBIT(index)))) {
2251 status = VXGE_HW_ERR_INVALID_INDEX;
2252 break;
2253 }
2254 if (offset > sizeof(struct vxge_hw_vpmgmt_reg) - 8) {
2255 status = VXGE_HW_ERR_INVALID_OFFSET;
2256 break;
2257 }
2258 writeq(value, (void __iomem *)hldev->vpmgmt_reg[index] +
2259 offset);
2260 break;
2261 case vxge_hw_mgmt_reg_type_vpath:
2262 if ((index > VXGE_HW_TITAN_VPATH_REG_SPACES-1) ||
2263 (!(hldev->vpath_assignments & vxge_mBIT(index)))) {
2264 status = VXGE_HW_ERR_INVALID_INDEX;
2265 break;
2266 }
2267 if (offset > sizeof(struct vxge_hw_vpath_reg) - 8) {
2268 status = VXGE_HW_ERR_INVALID_OFFSET;
2269 break;
2270 }
2271 writeq(value, (void __iomem *)hldev->vpath_reg[index] +
2272 offset);
2273 break;
2274 default:
2275 status = VXGE_HW_ERR_INVALID_TYPE;
2276 break;
2277 }
2278exit:
2279 return status;
2280}
2281
2282/*
2283 * __vxge_hw_fifo_mempool_item_alloc - Allocate List blocks for TxD
2284 * list callback
2285 * This function is callback passed to __vxge_hw_mempool_create to create memory
2286 * pool for TxD list
2287 */
2288static void
2289__vxge_hw_fifo_mempool_item_alloc(
2290 struct vxge_hw_mempool *mempoolh,
2291 u32 memblock_index, struct vxge_hw_mempool_dma *dma_object,
2292 u32 index, u32 is_last)
2293{
2294 u32 memblock_item_idx;
2295 struct __vxge_hw_fifo_txdl_priv *txdl_priv;
2296 struct vxge_hw_fifo_txd *txdp =
2297 (struct vxge_hw_fifo_txd *)mempoolh->items_arr[index];
2298 struct __vxge_hw_fifo *fifo =
2299 (struct __vxge_hw_fifo *)mempoolh->userdata;
2300 void *memblock = mempoolh->memblocks_arr[memblock_index];
2301
2302 vxge_assert(txdp);
2303
2304 txdp->host_control = (u64) (size_t)
2305 __vxge_hw_mempool_item_priv(mempoolh, memblock_index, txdp,
2306 &memblock_item_idx);
2307
2308 txdl_priv = __vxge_hw_fifo_txdl_priv(fifo, txdp);
2309
2310 vxge_assert(txdl_priv);
2311
2312 fifo->channel.reserve_arr[fifo->channel.reserve_ptr - 1 - index] = txdp;
2313
2314 /* pre-format HW's TxDL's private */
2315 txdl_priv->dma_offset = (char *)txdp - (char *)memblock;
2316 txdl_priv->dma_addr = dma_object->addr + txdl_priv->dma_offset;
2317 txdl_priv->dma_handle = dma_object->handle;
2318 txdl_priv->memblock = memblock;
2319 txdl_priv->first_txdp = txdp;
2320 txdl_priv->next_txdl_priv = NULL;
2321 txdl_priv->alloc_frags = 0;
2322
2323 return;
2324}
2325
2326/*
2327 * __vxge_hw_fifo_create - Create a FIFO
2328 * This function creates FIFO and initializes it.
2329 */
2330enum vxge_hw_status
2331__vxge_hw_fifo_create(struct __vxge_hw_vpath_handle *vp,
2332 struct vxge_hw_fifo_attr *attr)
2333{
2334 enum vxge_hw_status status = VXGE_HW_OK;
2335 struct __vxge_hw_fifo *fifo;
2336 struct vxge_hw_fifo_config *config;
2337 u32 txdl_size, txdl_per_memblock;
2338 struct vxge_hw_mempool_cbs fifo_mp_callback;
2339 struct __vxge_hw_virtualpath *vpath;
2340
2341 if ((vp == NULL) || (attr == NULL)) {
2342 status = VXGE_HW_ERR_INVALID_HANDLE;
2343 goto exit;
2344 }
2345 vpath = vp->vpath;
2346 config = &vpath->hldev->config.vp_config[vpath->vp_id].fifo;
2347
2348 txdl_size = config->max_frags * sizeof(struct vxge_hw_fifo_txd);
2349
2350 txdl_per_memblock = config->memblock_size / txdl_size;
2351
2352 fifo = (struct __vxge_hw_fifo *)__vxge_hw_channel_allocate(vp,
2353 VXGE_HW_CHANNEL_TYPE_FIFO,
2354 config->fifo_blocks * txdl_per_memblock,
2355 attr->per_txdl_space, attr->userdata);
2356
2357 if (fifo == NULL) {
2358 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2359 goto exit;
2360 }
2361
2362 vpath->fifoh = fifo;
2363 fifo->nofl_db = vpath->nofl_db;
2364
2365 fifo->vp_id = vpath->vp_id;
2366 fifo->vp_reg = vpath->vp_reg;
2367 fifo->stats = &vpath->sw_stats->fifo_stats;
2368
2369 fifo->config = config;
2370
2371 /* apply "interrupts per txdl" attribute */
2372 fifo->interrupt_type = VXGE_HW_FIFO_TXD_INT_TYPE_UTILZ;
2373
2374 if (fifo->config->intr)
2375 fifo->interrupt_type = VXGE_HW_FIFO_TXD_INT_TYPE_PER_LIST;
2376
2377 fifo->no_snoop_bits = config->no_snoop_bits;
2378
2379 /*
2380 * FIFO memory management strategy:
2381 *
2382 * TxDL split into three independent parts:
2383 * - set of TxD's
2384 * - TxD HW private part
2385 * - driver private part
2386 *
2387 * Adaptative memory allocation used. i.e. Memory allocated on
2388 * demand with the size which will fit into one memory block.
2389 * One memory block may contain more than one TxDL.
2390 *
2391 * During "reserve" operations more memory can be allocated on demand
2392 * for example due to FIFO full condition.
2393 *
2394 * Pool of memory memblocks never shrinks except in __vxge_hw_fifo_close
2395 * routine which will essentially stop the channel and free resources.
2396 */
2397
2398 /* TxDL common private size == TxDL private + driver private */
2399 fifo->priv_size =
2400 sizeof(struct __vxge_hw_fifo_txdl_priv) + attr->per_txdl_space;
2401 fifo->priv_size = ((fifo->priv_size + VXGE_CACHE_LINE_SIZE - 1) /
2402 VXGE_CACHE_LINE_SIZE) * VXGE_CACHE_LINE_SIZE;
2403
2404 fifo->per_txdl_space = attr->per_txdl_space;
2405
2406 /* recompute txdl size to be cacheline aligned */
2407 fifo->txdl_size = txdl_size;
2408 fifo->txdl_per_memblock = txdl_per_memblock;
2409
2410 fifo->txdl_term = attr->txdl_term;
2411 fifo->callback = attr->callback;
2412
2413 if (fifo->txdl_per_memblock == 0) {
2414 __vxge_hw_fifo_delete(vp);
2415 status = VXGE_HW_ERR_INVALID_BLOCK_SIZE;
2416 goto exit;
2417 }
2418
2419 fifo_mp_callback.item_func_alloc = __vxge_hw_fifo_mempool_item_alloc;
2420
2421 fifo->mempool =
2422 __vxge_hw_mempool_create(vpath->hldev,
2423 fifo->config->memblock_size,
2424 fifo->txdl_size,
2425 fifo->priv_size,
2426 (fifo->config->fifo_blocks * fifo->txdl_per_memblock),
2427 (fifo->config->fifo_blocks * fifo->txdl_per_memblock),
2428 &fifo_mp_callback,
2429 fifo);
2430
2431 if (fifo->mempool == NULL) {
2432 __vxge_hw_fifo_delete(vp);
2433 status = VXGE_HW_ERR_OUT_OF_MEMORY;
2434 goto exit;
2435 }
2436
2437 status = __vxge_hw_channel_initialize(&fifo->channel);
2438 if (status != VXGE_HW_OK) {
2439 __vxge_hw_fifo_delete(vp);
2440 goto exit;
2441 }
2442
2443 vxge_assert(fifo->channel.reserve_ptr);
2444exit:
2445 return status;
2446}
2447
2448/*
2449 * __vxge_hw_fifo_abort - Returns the TxD
2450 * This function terminates the TxDs of fifo
2451 */
2452enum vxge_hw_status __vxge_hw_fifo_abort(struct __vxge_hw_fifo *fifo)
2453{
2454 void *txdlh;
2455
2456 for (;;) {
2457 vxge_hw_channel_dtr_try_complete(&fifo->channel, &txdlh);
2458
2459 if (txdlh == NULL)
2460 break;
2461
2462 vxge_hw_channel_dtr_complete(&fifo->channel);
2463
2464 if (fifo->txdl_term) {
2465 fifo->txdl_term(txdlh,
2466 VXGE_HW_TXDL_STATE_POSTED,
2467 fifo->channel.userdata);
2468 }
2469
2470 vxge_hw_channel_dtr_free(&fifo->channel, txdlh);
2471 }
2472
2473 return VXGE_HW_OK;
2474}
2475
2476/*
2477 * __vxge_hw_fifo_reset - Resets the fifo
2478 * This function resets the fifo during vpath reset operation
2479 */
2480enum vxge_hw_status __vxge_hw_fifo_reset(struct __vxge_hw_fifo *fifo)
2481{
2482 enum vxge_hw_status status = VXGE_HW_OK;
2483
2484 __vxge_hw_fifo_abort(fifo);
2485 status = __vxge_hw_channel_reset(&fifo->channel);
2486
2487 return status;
2488}
2489
2490/*
2491 * __vxge_hw_fifo_delete - Removes the FIFO
2492 * This function freeup the memory pool and removes the FIFO
2493 */
2494enum vxge_hw_status __vxge_hw_fifo_delete(struct __vxge_hw_vpath_handle *vp)
2495{
2496 struct __vxge_hw_fifo *fifo = vp->vpath->fifoh;
2497
2498 __vxge_hw_fifo_abort(fifo);
2499
2500 if (fifo->mempool)
2501 __vxge_hw_mempool_destroy(fifo->mempool);
2502
2503 vp->vpath->fifoh = NULL;
2504
2505 __vxge_hw_channel_free(&fifo->channel);
2506
2507 return VXGE_HW_OK;
2508}
2509
2510/*
2511 * __vxge_hw_vpath_pci_read - Read the content of given address
2512 * in pci config space.
2513 * Read from the vpath pci config space.
2514 */
2515enum vxge_hw_status
2516__vxge_hw_vpath_pci_read(struct __vxge_hw_virtualpath *vpath,
2517 u32 phy_func_0, u32 offset, u32 *val)
2518{
2519 u64 val64;
2520 enum vxge_hw_status status = VXGE_HW_OK;
2521 struct vxge_hw_vpath_reg __iomem *vp_reg = vpath->vp_reg;
2522
2523 val64 = VXGE_HW_PCI_CONFIG_ACCESS_CFG1_ADDRESS(offset);
2524
2525 if (phy_func_0)
2526 val64 |= VXGE_HW_PCI_CONFIG_ACCESS_CFG1_SEL_FUNC0;
2527
2528 writeq(val64, &vp_reg->pci_config_access_cfg1);
2529 wmb();
2530 writeq(VXGE_HW_PCI_CONFIG_ACCESS_CFG2_REQ,
2531 &vp_reg->pci_config_access_cfg2);
2532 wmb();
2533
2534 status = __vxge_hw_device_register_poll(
2535 &vp_reg->pci_config_access_cfg2,
2536 VXGE_HW_INTR_MASK_ALL, VXGE_HW_DEF_DEVICE_POLL_MILLIS);
2537
2538 if (status != VXGE_HW_OK)
2539 goto exit;
2540
2541 val64 = readq(&vp_reg->pci_config_access_status);
2542
2543 if (val64 & VXGE_HW_PCI_CONFIG_ACCESS_STATUS_ACCESS_ERR) {
2544 status = VXGE_HW_FAIL;
2545 *val = 0;
2546 } else
2547 *val = (u32)vxge_bVALn(val64, 32, 32);
2548exit:
2549 return status;
2550}
2551
2552/*
2553 * __vxge_hw_vpath_func_id_get - Get the function id of the vpath.
2554 * Returns the function number of the vpath.
2555 */
2556u32
2557__vxge_hw_vpath_func_id_get(u32 vp_id,
2558 struct vxge_hw_vpmgmt_reg __iomem *vpmgmt_reg)
2559{
2560 u64 val64;
2561
2562 val64 = readq(&vpmgmt_reg->vpath_to_func_map_cfg1);
2563
2564 return
2565 (u32)VXGE_HW_VPATH_TO_FUNC_MAP_CFG1_GET_VPATH_TO_FUNC_MAP_CFG1(val64);
2566}
2567
2568/*
2569 * __vxge_hw_read_rts_ds - Program RTS steering critieria
2570 */
2571static inline void
2572__vxge_hw_read_rts_ds(struct vxge_hw_vpath_reg __iomem *vpath_reg,
2573 u64 dta_struct_sel)
2574{
2575 writeq(0, &vpath_reg->rts_access_steer_ctrl);
2576 wmb();
2577 writeq(dta_struct_sel, &vpath_reg->rts_access_steer_data0);
2578 writeq(0, &vpath_reg->rts_access_steer_data1);
2579 wmb();
2580 return;
2581}
2582
2583
2584/*
2585 * __vxge_hw_vpath_card_info_get - Get the serial numbers,
2586 * part number and product description.
2587 */
2588enum vxge_hw_status
2589__vxge_hw_vpath_card_info_get(
2590 u32 vp_id,
2591 struct vxge_hw_vpath_reg __iomem *vpath_reg,
2592 struct vxge_hw_device_hw_info *hw_info)
2593{
2594 u32 i, j;
2595 u64 val64;
2596 u64 data1 = 0ULL;
2597 u64 data2 = 0ULL;
2598 enum vxge_hw_status status = VXGE_HW_OK;
2599 u8 *serial_number = hw_info->serial_number;
2600 u8 *part_number = hw_info->part_number;
2601 u8 *product_desc = hw_info->product_desc;
2602
2603 __vxge_hw_read_rts_ds(vpath_reg,
2604 VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_SERIAL_NUMBER);
2605
2606 val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(
2607 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY) |
2608 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(
2609 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO) |
2610 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE |
2611 VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(0);
2612
2613 status = __vxge_hw_pio_mem_write64(val64,
2614 &vpath_reg->rts_access_steer_ctrl,
2615 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE,
2616 VXGE_HW_DEF_DEVICE_POLL_MILLIS);
2617
2618 if (status != VXGE_HW_OK)
2619 return status;
2620
2621 val64 = readq(&vpath_reg->rts_access_steer_ctrl);
2622
2623 if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) {
2624 data1 = readq(&vpath_reg->rts_access_steer_data0);
2625 ((u64 *)serial_number)[0] = be64_to_cpu(data1);
2626
2627 data2 = readq(&vpath_reg->rts_access_steer_data1);
2628 ((u64 *)serial_number)[1] = be64_to_cpu(data2);
2629 status = VXGE_HW_OK;
2630 } else
2631 *serial_number = 0;
2632
2633 __vxge_hw_read_rts_ds(vpath_reg,
2634 VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PART_NUMBER);
2635
2636 val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(
2637 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY) |
2638 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(
2639 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO) |
2640 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE |
2641 VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(0);
2642
2643 status = __vxge_hw_pio_mem_write64(val64,
2644 &vpath_reg->rts_access_steer_ctrl,
2645 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE,
2646 VXGE_HW_DEF_DEVICE_POLL_MILLIS);
2647
2648 if (status != VXGE_HW_OK)
2649 return status;
2650
2651 val64 = readq(&vpath_reg->rts_access_steer_ctrl);
2652
2653 if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) {
2654
2655 data1 = readq(&vpath_reg->rts_access_steer_data0);
2656 ((u64 *)part_number)[0] = be64_to_cpu(data1);
2657
2658 data2 = readq(&vpath_reg->rts_access_steer_data1);
2659 ((u64 *)part_number)[1] = be64_to_cpu(data2);
2660
2661 status = VXGE_HW_OK;
2662
2663 } else
2664 *part_number = 0;
2665
2666 j = 0;
2667
2668 for (i = VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_0;
2669 i <= VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_DESC_3; i++) {
2670
2671 __vxge_hw_read_rts_ds(vpath_reg, i);
2672
2673 val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(
2674 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY) |
2675 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(
2676 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO) |
2677 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE |
2678 VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(0);
2679
2680 status = __vxge_hw_pio_mem_write64(val64,
2681 &vpath_reg->rts_access_steer_ctrl,
2682 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE,
2683 VXGE_HW_DEF_DEVICE_POLL_MILLIS);
2684
2685 if (status != VXGE_HW_OK)
2686 return status;
2687
2688 val64 = readq(&vpath_reg->rts_access_steer_ctrl);
2689
2690 if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) {
2691
2692 data1 = readq(&vpath_reg->rts_access_steer_data0);
2693 ((u64 *)product_desc)[j++] = be64_to_cpu(data1);
2694
2695 data2 = readq(&vpath_reg->rts_access_steer_data1);
2696 ((u64 *)product_desc)[j++] = be64_to_cpu(data2);
2697
2698 status = VXGE_HW_OK;
2699 } else
2700 *product_desc = 0;
2701 }
2702
2703 return status;
2704}
2705
2706/*
2707 * __vxge_hw_vpath_fw_ver_get - Get the fw version
2708 * Returns FW Version
2709 */
2710enum vxge_hw_status
2711__vxge_hw_vpath_fw_ver_get(
2712 u32 vp_id,
2713 struct vxge_hw_vpath_reg __iomem *vpath_reg,
2714 struct vxge_hw_device_hw_info *hw_info)
2715{
2716 u64 val64;
2717 u64 data1 = 0ULL;
2718 u64 data2 = 0ULL;
2719 struct vxge_hw_device_version *fw_version = &hw_info->fw_version;
2720 struct vxge_hw_device_date *fw_date = &hw_info->fw_date;
2721 struct vxge_hw_device_version *flash_version = &hw_info->flash_version;
2722 struct vxge_hw_device_date *flash_date = &hw_info->flash_date;
2723 enum vxge_hw_status status = VXGE_HW_OK;
2724
2725 val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(
2726 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY) |
2727 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(
2728 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO) |
2729 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE |
2730 VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(0);
2731
2732 status = __vxge_hw_pio_mem_write64(val64,
2733 &vpath_reg->rts_access_steer_ctrl,
2734 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE,
2735 VXGE_HW_DEF_DEVICE_POLL_MILLIS);
2736
2737 if (status != VXGE_HW_OK)
2738 goto exit;
2739
2740 val64 = readq(&vpath_reg->rts_access_steer_ctrl);
2741
2742 if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) {
2743
2744 data1 = readq(&vpath_reg->rts_access_steer_data0);
2745 data2 = readq(&vpath_reg->rts_access_steer_data1);
2746
2747 fw_date->day =
2748 (u32)VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_DAY(
2749 data1);
2750 fw_date->month =
2751 (u32)VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MONTH(
2752 data1);
2753 fw_date->year =
2754 (u32)VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_YEAR(
2755 data1);
2756
2757 snprintf(fw_date->date, VXGE_HW_FW_STRLEN, "%2.2d/%2.2d/%4.4d",
2758 fw_date->month, fw_date->day, fw_date->year);
2759
2760 fw_version->major =
2761 (u32)VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MAJOR(data1);
2762 fw_version->minor =
2763 (u32)VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MINOR(data1);
2764 fw_version->build =
2765 (u32)VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_BUILD(data1);
2766
2767 snprintf(fw_version->version, VXGE_HW_FW_STRLEN, "%d.%d.%d",
2768 fw_version->major, fw_version->minor, fw_version->build);
2769
2770 flash_date->day =
2771 (u32)VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_DAY(data2);
2772 flash_date->month =
2773 (u32)VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MONTH(data2);
2774 flash_date->year =
2775 (u32)VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_YEAR(data2);
2776
2777 snprintf(flash_date->date, VXGE_HW_FW_STRLEN,
2778 "%2.2d/%2.2d/%4.4d",
2779 flash_date->month, flash_date->day, flash_date->year);
2780
2781 flash_version->major =
2782 (u32)VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MAJOR(data2);
2783 flash_version->minor =
2784 (u32)VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_MINOR(data2);
2785 flash_version->build =
2786 (u32)VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_FLASH_VER_BUILD(data2);
2787
2788 snprintf(flash_version->version, VXGE_HW_FW_STRLEN, "%d.%d.%d",
2789 flash_version->major, flash_version->minor,
2790 flash_version->build);
2791
2792 status = VXGE_HW_OK;
2793
2794 } else
2795 status = VXGE_HW_FAIL;
2796exit:
2797 return status;
2798}
2799
2800/*
2801 * __vxge_hw_vpath_pci_func_mode_get - Get the pci mode
2802 * Returns pci function mode
2803 */
2804u64
2805__vxge_hw_vpath_pci_func_mode_get(
2806 u32 vp_id,
2807 struct vxge_hw_vpath_reg __iomem *vpath_reg)
2808{
2809 u64 val64;
2810 u64 data1 = 0ULL;
2811 enum vxge_hw_status status = VXGE_HW_OK;
2812
2813 __vxge_hw_read_rts_ds(vpath_reg,
2814 VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PCI_MODE);
2815
2816 val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(
2817 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_MEMO_ENTRY) |
2818 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(
2819 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO) |
2820 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE |
2821 VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(0);
2822
2823 status = __vxge_hw_pio_mem_write64(val64,
2824 &vpath_reg->rts_access_steer_ctrl,
2825 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE,
2826 VXGE_HW_DEF_DEVICE_POLL_MILLIS);
2827
2828 if (status != VXGE_HW_OK)
2829 goto exit;
2830
2831 val64 = readq(&vpath_reg->rts_access_steer_ctrl);
2832
2833 if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) {
2834 data1 = readq(&vpath_reg->rts_access_steer_data0);
2835 status = VXGE_HW_OK;
2836 } else {
2837 data1 = 0;
2838 status = VXGE_HW_FAIL;
2839 }
2840exit:
2841 return data1;
2842}
2843
2844/**
2845 * vxge_hw_device_flick_link_led - Flick (blink) link LED.
2846 * @hldev: HW device.
2847 * @on_off: TRUE if flickering to be on, FALSE to be off
2848 *
2849 * Flicker the link LED.
2850 */
2851enum vxge_hw_status
2852vxge_hw_device_flick_link_led(struct __vxge_hw_device *hldev,
2853 u64 on_off)
2854{
2855 u64 val64;
2856 enum vxge_hw_status status = VXGE_HW_OK;
2857 struct vxge_hw_vpath_reg __iomem *vp_reg;
2858
2859 if (hldev == NULL) {
2860 status = VXGE_HW_ERR_INVALID_DEVICE;
2861 goto exit;
2862 }
2863
2864 vp_reg = hldev->vpath_reg[hldev->first_vp_id];
2865
2866 writeq(0, &vp_reg->rts_access_steer_ctrl);
2867 wmb();
2868 writeq(on_off, &vp_reg->rts_access_steer_data0);
2869 writeq(0, &vp_reg->rts_access_steer_data1);
2870 wmb();
2871
2872 val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(
2873 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LED_CONTROL) |
2874 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(
2875 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_FW_MEMO) |
2876 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE |
2877 VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(0);
2878
2879 status = __vxge_hw_pio_mem_write64(val64,
2880 &vp_reg->rts_access_steer_ctrl,
2881 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE,
2882 VXGE_HW_DEF_DEVICE_POLL_MILLIS);
2883exit:
2884 return status;
2885}
2886
2887/*
2888 * __vxge_hw_vpath_rts_table_get - Get the entries from RTS access tables
2889 */
2890enum vxge_hw_status
2891__vxge_hw_vpath_rts_table_get(
2892 struct __vxge_hw_vpath_handle *vp,
2893 u32 action, u32 rts_table, u32 offset, u64 *data1, u64 *data2)
2894{
2895 u64 val64;
2896 struct __vxge_hw_virtualpath *vpath;
2897 struct vxge_hw_vpath_reg __iomem *vp_reg;
2898
2899 enum vxge_hw_status status = VXGE_HW_OK;
2900
2901 if (vp == NULL) {
2902 status = VXGE_HW_ERR_INVALID_HANDLE;
2903 goto exit;
2904 }
2905
2906 vpath = vp->vpath;
2907 vp_reg = vpath->vp_reg;
2908
2909 val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(action) |
2910 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(rts_table) |
2911 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE |
2912 VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(offset);
2913
2914 if ((rts_table ==
2915 VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT) ||
2916 (rts_table ==
2917 VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT) ||
2918 (rts_table ==
2919 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MASK) ||
2920 (rts_table ==
2921 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_KEY)) {
2922 val64 = val64 | VXGE_HW_RTS_ACCESS_STEER_CTRL_TABLE_SEL;
2923 }
2924
2925 status = __vxge_hw_pio_mem_write64(val64,
2926 &vp_reg->rts_access_steer_ctrl,
2927 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE,
2928 vpath->hldev->config.device_poll_millis);
2929
2930 if (status != VXGE_HW_OK)
2931 goto exit;
2932
2933 val64 = readq(&vp_reg->rts_access_steer_ctrl);
2934
2935 if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) {
2936
2937 *data1 = readq(&vp_reg->rts_access_steer_data0);
2938
2939 if ((rts_table ==
2940 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA) ||
2941 (rts_table ==
2942 VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT)) {
2943 *data2 = readq(&vp_reg->rts_access_steer_data1);
2944 }
2945 status = VXGE_HW_OK;
2946 } else
2947 status = VXGE_HW_FAIL;
2948exit:
2949 return status;
2950}
2951
2952/*
2953 * __vxge_hw_vpath_rts_table_set - Set the entries of RTS access tables
2954 */
2955enum vxge_hw_status
2956__vxge_hw_vpath_rts_table_set(
2957 struct __vxge_hw_vpath_handle *vp, u32 action, u32 rts_table,
2958 u32 offset, u64 data1, u64 data2)
2959{
2960 u64 val64;
2961 struct __vxge_hw_virtualpath *vpath;
2962 enum vxge_hw_status status = VXGE_HW_OK;
2963 struct vxge_hw_vpath_reg __iomem *vp_reg;
2964
2965 if (vp == NULL) {
2966 status = VXGE_HW_ERR_INVALID_HANDLE;
2967 goto exit;
2968 }
2969
2970 vpath = vp->vpath;
2971 vp_reg = vpath->vp_reg;
2972
2973 writeq(data1, &vp_reg->rts_access_steer_data0);
2974 wmb();
2975
2976 if ((rts_table == VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA) ||
2977 (rts_table ==
2978 VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT)) {
2979 writeq(data2, &vp_reg->rts_access_steer_data1);
2980 wmb();
2981 }
2982
2983 val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(action) |
2984 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(rts_table) |
2985 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE |
2986 VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(offset);
2987
2988 status = __vxge_hw_pio_mem_write64(val64,
2989 &vp_reg->rts_access_steer_ctrl,
2990 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE,
2991 vpath->hldev->config.device_poll_millis);
2992
2993 if (status != VXGE_HW_OK)
2994 goto exit;
2995
2996 val64 = readq(&vp_reg->rts_access_steer_ctrl);
2997
2998 if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS)
2999 status = VXGE_HW_OK;
3000 else
3001 status = VXGE_HW_FAIL;
3002exit:
3003 return status;
3004}
3005
3006/*
3007 * __vxge_hw_vpath_addr_get - Get the hw address entry for this vpath
3008 * from MAC address table.
3009 */
3010enum vxge_hw_status
3011__vxge_hw_vpath_addr_get(
3012 u32 vp_id, struct vxge_hw_vpath_reg __iomem *vpath_reg,
3013 u8 (macaddr)[ETH_ALEN], u8 (macaddr_mask)[ETH_ALEN])
3014{
3015 u32 i;
3016 u64 val64;
3017 u64 data1 = 0ULL;
3018 u64 data2 = 0ULL;
3019 enum vxge_hw_status status = VXGE_HW_OK;
3020
3021 val64 = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION(
3022 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_LIST_FIRST_ENTRY) |
3023 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(
3024 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_DA) |
3025 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE |
3026 VXGE_HW_RTS_ACCESS_STEER_CTRL_OFFSET(0);
3027
3028 status = __vxge_hw_pio_mem_write64(val64,
3029 &vpath_reg->rts_access_steer_ctrl,
3030 VXGE_HW_RTS_ACCESS_STEER_CTRL_STROBE,
3031 VXGE_HW_DEF_DEVICE_POLL_MILLIS);
3032
3033 if (status != VXGE_HW_OK)
3034 goto exit;
3035
3036 val64 = readq(&vpath_reg->rts_access_steer_ctrl);
3037
3038 if (val64 & VXGE_HW_RTS_ACCESS_STEER_CTRL_RMACJ_STATUS) {
3039
3040 data1 = readq(&vpath_reg->rts_access_steer_data0);
3041 data2 = readq(&vpath_reg->rts_access_steer_data1);
3042
3043 data1 = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(data1);
3044 data2 = VXGE_HW_RTS_ACCESS_STEER_DATA1_GET_DA_MAC_ADDR_MASK(
3045 data2);
3046
3047 for (i = ETH_ALEN; i > 0; i--) {
3048 macaddr[i-1] = (u8)(data1 & 0xFF);
3049 data1 >>= 8;
3050
3051 macaddr_mask[i-1] = (u8)(data2 & 0xFF);
3052 data2 >>= 8;
3053 }
3054 status = VXGE_HW_OK;
3055 } else
3056 status = VXGE_HW_FAIL;
3057exit:
3058 return status;
3059}
3060
3061/*
3062 * vxge_hw_vpath_rts_rth_set - Set/configure RTS hashing.
3063 */
3064enum vxge_hw_status vxge_hw_vpath_rts_rth_set(
3065 struct __vxge_hw_vpath_handle *vp,
3066 enum vxge_hw_rth_algoritms algorithm,
3067 struct vxge_hw_rth_hash_types *hash_type,
3068 u16 bucket_size)
3069{
3070 u64 data0, data1;
3071 enum vxge_hw_status status = VXGE_HW_OK;
3072
3073 if (vp == NULL) {
3074 status = VXGE_HW_ERR_INVALID_HANDLE;
3075 goto exit;
3076 }
3077
3078 status = __vxge_hw_vpath_rts_table_get(vp,
3079 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_READ_ENTRY,
3080 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG,
3081 0, &data0, &data1);
3082
3083 data0 &= ~(VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_BUCKET_SIZE(0xf) |
3084 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL(0x3));
3085
3086 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_EN |
3087 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_BUCKET_SIZE(bucket_size) |
3088 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ALG_SEL(algorithm);
3089
3090 if (hash_type->hash_type_tcpipv4_en)
3091 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV4_EN;
3092
3093 if (hash_type->hash_type_ipv4_en)
3094 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV4_EN;
3095
3096 if (hash_type->hash_type_tcpipv6_en)
3097 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV6_EN;
3098
3099 if (hash_type->hash_type_ipv6_en)
3100 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV6_EN;
3101
3102 if (hash_type->hash_type_tcpipv6ex_en)
3103 data0 |=
3104 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV6_EX_EN;
3105
3106 if (hash_type->hash_type_ipv6ex_en)
3107 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV6_EX_EN;
3108
3109 if (VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_ACTIVE_TABLE(data0))
3110 data0 &= ~VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ACTIVE_TABLE;
3111 else
3112 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ACTIVE_TABLE;
3113
3114 status = __vxge_hw_vpath_rts_table_set(vp,
3115 VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY,
3116 VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL_RTH_GEN_CFG,
3117 0, data0, 0);
3118exit:
3119 return status;
3120}
3121
3122static void
3123vxge_hw_rts_rth_data0_data1_get(u32 j, u64 *data0, u64 *data1,
3124 u16 flag, u8 *itable)
3125{
3126 switch (flag) {
3127 case 1:
3128 *data0 = VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_NUM(j)|
3129 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_ENTRY_EN |
3130 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_DATA(
3131 itable[j]);
3132 case 2:
3133 *data0 |=
3134 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_NUM(j)|
3135 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_ENTRY_EN |
3136 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM1_BUCKET_DATA(
3137 itable[j]);
3138 case 3:
3139 *data1 = VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_NUM(j)|
3140 VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_ENTRY_EN |
3141 VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM0_BUCKET_DATA(
3142 itable[j]);
3143 case 4:
3144 *data1 |=
3145 VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_NUM(j)|
3146 VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_ENTRY_EN |
3147 VXGE_HW_RTS_ACCESS_STEER_DATA1_RTH_ITEM1_BUCKET_DATA(
3148 itable[j]);
3149 default:
3150 return;
3151 }
3152}
3153/*
3154 * vxge_hw_vpath_rts_rth_itable_set - Set/configure indirection table (IT).
3155 */
3156enum vxge_hw_status vxge_hw_vpath_rts_rth_itable_set(
3157 struct __vxge_hw_vpath_handle **vpath_handles,
3158 u32 vpath_count,
3159 u8 *mtable,
3160 u8 *itable,
3161 u32 itable_size)
3162{
3163 u32 i, j, action, rts_table;
3164 u64 data0;
3165 u64 data1;
3166 u32 max_entries;
3167 enum vxge_hw_status status = VXGE_HW_OK;
3168 struct __vxge_hw_vpath_handle *vp = vpath_handles[0];
3169
3170 if (vp == NULL) {
3171 status = VXGE_HW_ERR_INVALID_HANDLE;
3172 goto exit;
3173 }
3174
3175 max_entries = (((u32)1) << itable_size);
3176
3177 if (vp->vpath->hldev->config.rth_it_type
3178 == VXGE_HW_RTH_IT_TYPE_SOLO_IT) {
3179 action = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY;
3180 rts_table =
3181 VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_SOLO_IT;
3182
3183 for (j = 0; j < max_entries; j++) {
3184
3185 data1 = 0;
3186
3187 data0 =
3188 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_BUCKET_DATA(
3189 itable[j]);
3190
3191 status = __vxge_hw_vpath_rts_table_set(vpath_handles[0],
3192 action, rts_table, j, data0, data1);
3193
3194 if (status != VXGE_HW_OK)
3195 goto exit;
3196 }
3197
3198 for (j = 0; j < max_entries; j++) {
3199
3200 data1 = 0;
3201
3202 data0 =
3203 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_ENTRY_EN |
3204 VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_SOLO_IT_BUCKET_DATA(
3205 itable[j]);
3206
3207 status = __vxge_hw_vpath_rts_table_set(
3208 vpath_handles[mtable[itable[j]]], action,
3209 rts_table, j, data0, data1);
3210
3211 if (status != VXGE_HW_OK)
3212 goto exit;
3213 }
3214 } else {
3215 action = VXGE_HW_RTS_ACCESS_STEER_CTRL_ACTION_WRITE_ENTRY;
3216 rts_table =
3217 VXGE_HW_RTS_ACS_STEER_CTRL_DATA_STRUCT_SEL_RTH_MULTI_IT;
3218 for (i = 0; i < vpath_count; i++) {
3219
3220 for (j = 0; j < max_entries;) {
3221
3222 data0 = 0;
3223 data1 = 0;
3224
3225 while (j < max_entries) {
3226 if (mtable[itable[j]] != i) {
3227 j++;
3228 continue;
3229 }
3230 vxge_hw_rts_rth_data0_data1_get(j,
3231 &data0, &data1, 1, itable);
3232 j++;
3233 break;
3234 }
3235
3236 while (j < max_entries) {
3237 if (mtable[itable[j]] != i) {
3238 j++;
3239 continue;
3240 }
3241 vxge_hw_rts_rth_data0_data1_get(j,
3242 &data0, &data1, 2, itable);
3243 j++;
3244 break;
3245 }
3246
3247 while (j < max_entries) {
3248 if (mtable[itable[j]] != i) {
3249 j++;
3250 continue;
3251 }
3252 vxge_hw_rts_rth_data0_data1_get(j,
3253 &data0, &data1, 3, itable);
3254 j++;
3255 break;
3256 }
3257
3258 while (j < max_entries) {
3259 if (mtable[itable[j]] != i) {
3260 j++;
3261 continue;
3262 }
3263 vxge_hw_rts_rth_data0_data1_get(j,
3264 &data0, &data1, 4, itable);
3265 j++;
3266 break;
3267 }
3268
3269 if (data0 != 0) {
3270 status = __vxge_hw_vpath_rts_table_set(
3271 vpath_handles[i],
3272 action, rts_table,
3273 0, data0, data1);
3274
3275 if (status != VXGE_HW_OK)
3276 goto exit;
3277 }
3278 }
3279 }
3280 }
3281exit:
3282 return status;
3283}
3284
3285/**
3286 * vxge_hw_vpath_check_leak - Check for memory leak
3287 * @ringh: Handle to the ring object used for receive
3288 *
3289 * If PRC_RXD_DOORBELL_VPn.NEW_QW_CNT is larger or equal to
3290 * PRC_CFG6_VPn.RXD_SPAT then a leak has occurred.
3291 * Returns: VXGE_HW_FAIL, if leak has occurred.
3292 *
3293 */
3294enum vxge_hw_status
3295vxge_hw_vpath_check_leak(struct __vxge_hw_ring *ring)
3296{
3297 enum vxge_hw_status status = VXGE_HW_OK;
3298 u64 rxd_new_count, rxd_spat;
3299
3300 if (ring == NULL)
3301 return status;
3302
3303 rxd_new_count = readl(&ring->vp_reg->prc_rxd_doorbell);
3304 rxd_spat = readq(&ring->vp_reg->prc_cfg6);
3305 rxd_spat = VXGE_HW_PRC_CFG6_RXD_SPAT(rxd_spat);
3306
3307 if (rxd_new_count >= rxd_spat)
3308 status = VXGE_HW_FAIL;
3309
3310 return status;
3311}
3312
3313/*
3314 * __vxge_hw_vpath_mgmt_read
3315 * This routine reads the vpath_mgmt registers
3316 */
3317static enum vxge_hw_status
3318__vxge_hw_vpath_mgmt_read(
3319 struct __vxge_hw_device *hldev,
3320 struct __vxge_hw_virtualpath *vpath)
3321{
3322 u32 i, mtu = 0, max_pyld = 0;
3323 u64 val64;
3324 enum vxge_hw_status status = VXGE_HW_OK;
3325
3326 for (i = 0; i < VXGE_HW_MAC_MAX_MAC_PORT_ID; i++) {
3327
3328 val64 = readq(&vpath->vpmgmt_reg->
3329 rxmac_cfg0_port_vpmgmt_clone[i]);
3330 max_pyld =
3331 (u32)
3332 VXGE_HW_RXMAC_CFG0_PORT_VPMGMT_CLONE_GET_MAX_PYLD_LEN
3333 (val64);
3334 if (mtu < max_pyld)
3335 mtu = max_pyld;
3336 }
3337
3338 vpath->max_mtu = mtu + VXGE_HW_MAC_HEADER_MAX_SIZE;
3339
3340 val64 = readq(&vpath->vpmgmt_reg->xmac_vsport_choices_vp);
3341
3342 for (i = 0; i < VXGE_HW_MAX_VIRTUAL_PATHS; i++) {
3343 if (val64 & vxge_mBIT(i))
3344 vpath->vsport_number = i;
3345 }
3346
3347 val64 = readq(&vpath->vpmgmt_reg->xgmac_gen_status_vpmgmt_clone);
3348
3349 if (val64 & VXGE_HW_XGMAC_GEN_STATUS_VPMGMT_CLONE_XMACJ_NTWK_OK)
3350 VXGE_HW_DEVICE_LINK_STATE_SET(vpath->hldev, VXGE_HW_LINK_UP);
3351 else
3352 VXGE_HW_DEVICE_LINK_STATE_SET(vpath->hldev, VXGE_HW_LINK_DOWN);
3353
3354 return status;
3355}
3356
3357/*
3358 * __vxge_hw_vpath_reset_check - Check if resetting the vpath completed
3359 * This routine checks the vpath_rst_in_prog register to see if
3360 * adapter completed the reset process for the vpath
3361 */
3362enum vxge_hw_status
3363__vxge_hw_vpath_reset_check(struct __vxge_hw_virtualpath *vpath)
3364{
3365 enum vxge_hw_status status;
3366
3367 status = __vxge_hw_device_register_poll(
3368 &vpath->hldev->common_reg->vpath_rst_in_prog,
3369 VXGE_HW_VPATH_RST_IN_PROG_VPATH_RST_IN_PROG(
3370 1 << (16 - vpath->vp_id)),
3371 vpath->hldev->config.device_poll_millis);
3372
3373 return status;
3374}
3375
3376/*
3377 * __vxge_hw_vpath_reset
3378 * This routine resets the vpath on the device
3379 */
3380enum vxge_hw_status
3381__vxge_hw_vpath_reset(struct __vxge_hw_device *hldev, u32 vp_id)
3382{
3383 u64 val64;
3384 enum vxge_hw_status status = VXGE_HW_OK;
3385
3386 val64 = VXGE_HW_CMN_RSTHDLR_CFG0_SW_RESET_VPATH(1 << (16 - vp_id));
3387
3388 __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32),
3389 &hldev->common_reg->cmn_rsthdlr_cfg0);
3390
3391 return status;
3392}
3393
3394/*
3395 * __vxge_hw_vpath_sw_reset
3396 * This routine resets the vpath structures
3397 */
3398enum vxge_hw_status
3399__vxge_hw_vpath_sw_reset(struct __vxge_hw_device *hldev, u32 vp_id)
3400{
3401 enum vxge_hw_status status = VXGE_HW_OK;
3402 struct __vxge_hw_virtualpath *vpath;
3403
3404 vpath = (struct __vxge_hw_virtualpath *)&hldev->virtual_paths[vp_id];
3405
3406 if (vpath->ringh) {
3407 status = __vxge_hw_ring_reset(vpath->ringh);
3408 if (status != VXGE_HW_OK)
3409 goto exit;
3410 }
3411
3412 if (vpath->fifoh)
3413 status = __vxge_hw_fifo_reset(vpath->fifoh);
3414exit:
3415 return status;
3416}
3417
3418/*
3419 * __vxge_hw_vpath_prc_configure
3420 * This routine configures the prc registers of virtual path using the config
3421 * passed
3422 */
3423void
3424__vxge_hw_vpath_prc_configure(struct __vxge_hw_device *hldev, u32 vp_id)
3425{
3426 u64 val64;
3427 struct __vxge_hw_virtualpath *vpath;
3428 struct vxge_hw_vp_config *vp_config;
3429 struct vxge_hw_vpath_reg __iomem *vp_reg;
3430
3431 vpath = &hldev->virtual_paths[vp_id];
3432 vp_reg = vpath->vp_reg;
3433 vp_config = vpath->vp_config;
3434
3435 if (vp_config->ring.enable == VXGE_HW_RING_DISABLE)
3436 return;
3437
3438 val64 = readq(&vp_reg->prc_cfg1);
3439 val64 |= VXGE_HW_PRC_CFG1_RTI_TINT_DISABLE;
3440 writeq(val64, &vp_reg->prc_cfg1);
3441
3442 val64 = readq(&vpath->vp_reg->prc_cfg6);
3443 val64 |= VXGE_HW_PRC_CFG6_DOORBELL_MODE_EN;
3444 writeq(val64, &vpath->vp_reg->prc_cfg6);
3445
3446 val64 = readq(&vp_reg->prc_cfg7);
3447
3448 if (vpath->vp_config->ring.scatter_mode !=
3449 VXGE_HW_RING_SCATTER_MODE_USE_FLASH_DEFAULT) {
3450
3451 val64 &= ~VXGE_HW_PRC_CFG7_SCATTER_MODE(0x3);
3452
3453 switch (vpath->vp_config->ring.scatter_mode) {
3454 case VXGE_HW_RING_SCATTER_MODE_A:
3455 val64 |= VXGE_HW_PRC_CFG7_SCATTER_MODE(
3456 VXGE_HW_PRC_CFG7_SCATTER_MODE_A);
3457 break;
3458 case VXGE_HW_RING_SCATTER_MODE_B:
3459 val64 |= VXGE_HW_PRC_CFG7_SCATTER_MODE(
3460 VXGE_HW_PRC_CFG7_SCATTER_MODE_B);
3461 break;
3462 case VXGE_HW_RING_SCATTER_MODE_C:
3463 val64 |= VXGE_HW_PRC_CFG7_SCATTER_MODE(
3464 VXGE_HW_PRC_CFG7_SCATTER_MODE_C);
3465 break;
3466 }
3467 }
3468
3469 writeq(val64, &vp_reg->prc_cfg7);
3470
3471 writeq(VXGE_HW_PRC_CFG5_RXD0_ADD(
3472 __vxge_hw_ring_first_block_address_get(
3473 vpath->ringh) >> 3), &vp_reg->prc_cfg5);
3474
3475 val64 = readq(&vp_reg->prc_cfg4);
3476 val64 |= VXGE_HW_PRC_CFG4_IN_SVC;
3477 val64 &= ~VXGE_HW_PRC_CFG4_RING_MODE(0x3);
3478
3479 val64 |= VXGE_HW_PRC_CFG4_RING_MODE(
3480 VXGE_HW_PRC_CFG4_RING_MODE_ONE_BUFFER);
3481
3482 if (hldev->config.rth_en == VXGE_HW_RTH_DISABLE)
3483 val64 |= VXGE_HW_PRC_CFG4_RTH_DISABLE;
3484 else
3485 val64 &= ~VXGE_HW_PRC_CFG4_RTH_DISABLE;
3486
3487 writeq(val64, &vp_reg->prc_cfg4);
3488 return;
3489}
3490
3491/*
3492 * __vxge_hw_vpath_kdfc_configure
3493 * This routine configures the kdfc registers of virtual path using the
3494 * config passed
3495 */
3496enum vxge_hw_status
3497__vxge_hw_vpath_kdfc_configure(struct __vxge_hw_device *hldev, u32 vp_id)
3498{
3499 u64 val64;
3500 u64 vpath_stride;
3501 enum vxge_hw_status status = VXGE_HW_OK;
3502 struct __vxge_hw_virtualpath *vpath;
3503 struct vxge_hw_vpath_reg __iomem *vp_reg;
3504
3505 vpath = &hldev->virtual_paths[vp_id];
3506 vp_reg = vpath->vp_reg;
3507 status = __vxge_hw_kdfc_swapper_set(hldev->legacy_reg, vp_reg);
3508
3509 if (status != VXGE_HW_OK)
3510 goto exit;
3511
3512 val64 = readq(&vp_reg->kdfc_drbl_triplet_total);
3513
3514 vpath->max_kdfc_db =
3515 (u32)VXGE_HW_KDFC_DRBL_TRIPLET_TOTAL_GET_KDFC_MAX_SIZE(
3516 val64+1)/2;
3517
3518 if (vpath->vp_config->fifo.enable == VXGE_HW_FIFO_ENABLE) {
3519
3520 vpath->max_nofl_db = vpath->max_kdfc_db;
3521
3522 if (vpath->max_nofl_db <
3523 ((vpath->vp_config->fifo.memblock_size /
3524 (vpath->vp_config->fifo.max_frags *
3525 sizeof(struct vxge_hw_fifo_txd))) *
3526 vpath->vp_config->fifo.fifo_blocks)) {
3527
3528 return VXGE_HW_BADCFG_FIFO_BLOCKS;
3529 }
3530 val64 = VXGE_HW_KDFC_FIFO_TRPL_PARTITION_LENGTH_0(
3531 (vpath->max_nofl_db*2)-1);
3532 }
3533
3534 writeq(val64, &vp_reg->kdfc_fifo_trpl_partition);
3535
3536 writeq(VXGE_HW_KDFC_FIFO_TRPL_CTRL_TRIPLET_ENABLE,
3537 &vp_reg->kdfc_fifo_trpl_ctrl);
3538
3539 val64 = readq(&vp_reg->kdfc_trpl_fifo_0_ctrl);
3540
3541 val64 &= ~(VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE(0x3) |
3542 VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SELECT(0xFF));
3543
3544 val64 |= VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE(
3545 VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MODE_NON_OFFLOAD_ONLY) |
3546#ifndef __BIG_ENDIAN
3547 VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SWAP_EN |
3548#endif
3549 VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SELECT(0);
3550
3551 writeq(val64, &vp_reg->kdfc_trpl_fifo_0_ctrl);
3552 writeq((u64)0, &vp_reg->kdfc_trpl_fifo_0_wb_address);
3553 wmb();
3554 vpath_stride = readq(&hldev->toc_reg->toc_kdfc_vpath_stride);
3555
3556 vpath->nofl_db =
3557 (struct __vxge_hw_non_offload_db_wrapper __iomem *)
3558 (hldev->kdfc + (vp_id *
3559 VXGE_HW_TOC_KDFC_VPATH_STRIDE_GET_TOC_KDFC_VPATH_STRIDE(
3560 vpath_stride)));
3561exit:
3562 return status;
3563}
3564
3565/*
3566 * __vxge_hw_vpath_mac_configure
3567 * This routine configures the mac of virtual path using the config passed
3568 */
3569enum vxge_hw_status
3570__vxge_hw_vpath_mac_configure(struct __vxge_hw_device *hldev, u32 vp_id)
3571{
3572 u64 val64;
3573 enum vxge_hw_status status = VXGE_HW_OK;
3574 struct __vxge_hw_virtualpath *vpath;
3575 struct vxge_hw_vp_config *vp_config;
3576 struct vxge_hw_vpath_reg __iomem *vp_reg;
3577
3578 vpath = &hldev->virtual_paths[vp_id];
3579 vp_reg = vpath->vp_reg;
3580 vp_config = vpath->vp_config;
3581
3582 writeq(VXGE_HW_XMAC_VSPORT_CHOICE_VSPORT_NUMBER(
3583 vpath->vsport_number), &vp_reg->xmac_vsport_choice);
3584
3585 if (vp_config->ring.enable == VXGE_HW_RING_ENABLE) {
3586
3587 val64 = readq(&vp_reg->xmac_rpa_vcfg);
3588
3589 if (vp_config->rpa_strip_vlan_tag !=
3590 VXGE_HW_VPATH_RPA_STRIP_VLAN_TAG_USE_FLASH_DEFAULT) {
3591 if (vp_config->rpa_strip_vlan_tag)
3592 val64 |= VXGE_HW_XMAC_RPA_VCFG_STRIP_VLAN_TAG;
3593 else
3594 val64 &= ~VXGE_HW_XMAC_RPA_VCFG_STRIP_VLAN_TAG;
3595 }
3596
3597 writeq(val64, &vp_reg->xmac_rpa_vcfg);
3598 val64 = readq(&vp_reg->rxmac_vcfg0);
3599
3600 if (vp_config->mtu !=
3601 VXGE_HW_VPATH_USE_FLASH_DEFAULT_INITIAL_MTU) {
3602 val64 &= ~VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(0x3fff);
3603 if ((vp_config->mtu +
3604 VXGE_HW_MAC_HEADER_MAX_SIZE) < vpath->max_mtu)
3605 val64 |= VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(
3606 vp_config->mtu +
3607 VXGE_HW_MAC_HEADER_MAX_SIZE);
3608 else
3609 val64 |= VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(
3610 vpath->max_mtu);
3611 }
3612
3613 writeq(val64, &vp_reg->rxmac_vcfg0);
3614
3615 val64 = readq(&vp_reg->rxmac_vcfg1);
3616
3617 val64 &= ~(VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_BD_MODE(0x3) |
3618 VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_EN_MODE);
3619
3620 if (hldev->config.rth_it_type ==
3621 VXGE_HW_RTH_IT_TYPE_MULTI_IT) {
3622 val64 |= VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_BD_MODE(
3623 0x2) |
3624 VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_EN_MODE;
3625 }
3626
3627 writeq(val64, &vp_reg->rxmac_vcfg1);
3628 }
3629 return status;
3630}
3631
3632/*
3633 * __vxge_hw_vpath_tim_configure
3634 * This routine configures the tim registers of virtual path using the config
3635 * passed
3636 */
3637enum vxge_hw_status
3638__vxge_hw_vpath_tim_configure(struct __vxge_hw_device *hldev, u32 vp_id)
3639{
3640 u64 val64;
3641 enum vxge_hw_status status = VXGE_HW_OK;
3642 struct __vxge_hw_virtualpath *vpath;
3643 struct vxge_hw_vpath_reg __iomem *vp_reg;
3644 struct vxge_hw_vp_config *config;
3645
3646 vpath = &hldev->virtual_paths[vp_id];
3647 vp_reg = vpath->vp_reg;
3648 config = vpath->vp_config;
3649
3650 writeq((u64)0, &vp_reg->tim_dest_addr);
3651 writeq((u64)0, &vp_reg->tim_vpath_map);
3652 writeq((u64)0, &vp_reg->tim_bitmap);
3653 writeq((u64)0, &vp_reg->tim_remap);
3654
3655 if (config->ring.enable == VXGE_HW_RING_ENABLE)
3656 writeq(VXGE_HW_TIM_RING_ASSN_INT_NUM(
3657 (vp_id * VXGE_HW_MAX_INTR_PER_VP) +
3658 VXGE_HW_VPATH_INTR_RX), &vp_reg->tim_ring_assn);
3659
3660 val64 = readq(&vp_reg->tim_pci_cfg);
3661 val64 |= VXGE_HW_TIM_PCI_CFG_ADD_PAD;
3662 writeq(val64, &vp_reg->tim_pci_cfg);
3663
3664 if (config->fifo.enable == VXGE_HW_FIFO_ENABLE) {
3665
3666 val64 = readq(&vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
3667
3668 if (config->tti.btimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
3669 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(
3670 0x3ffffff);
3671 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(
3672 config->tti.btimer_val);
3673 }
3674
3675 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BITMP_EN;
3676
3677 if (config->tti.timer_ac_en != VXGE_HW_USE_FLASH_DEFAULT) {
3678 if (config->tti.timer_ac_en)
3679 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC;
3680 else
3681 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC;
3682 }
3683
3684 if (config->tti.timer_ci_en != VXGE_HW_USE_FLASH_DEFAULT) {
3685 if (config->tti.timer_ci_en)
3686 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
3687 else
3688 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
3689 }
3690
3691 if (config->tti.urange_a != VXGE_HW_USE_FLASH_DEFAULT) {
3692 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(0x3f);
3693 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(
3694 config->tti.urange_a);
3695 }
3696
3697 if (config->tti.urange_b != VXGE_HW_USE_FLASH_DEFAULT) {
3698 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(0x3f);
3699 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(
3700 config->tti.urange_b);
3701 }
3702
3703 if (config->tti.urange_c != VXGE_HW_USE_FLASH_DEFAULT) {
3704 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(0x3f);
3705 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(
3706 config->tti.urange_c);
3707 }
3708
3709 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
3710 val64 = readq(&vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_TX]);
3711
3712 if (config->tti.uec_a != VXGE_HW_USE_FLASH_DEFAULT) {
3713 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(0xffff);
3714 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(
3715 config->tti.uec_a);
3716 }
3717
3718 if (config->tti.uec_b != VXGE_HW_USE_FLASH_DEFAULT) {
3719 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(0xffff);
3720 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(
3721 config->tti.uec_b);
3722 }
3723
3724 if (config->tti.uec_c != VXGE_HW_USE_FLASH_DEFAULT) {
3725 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(0xffff);
3726 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(
3727 config->tti.uec_c);
3728 }
3729
3730 if (config->tti.uec_d != VXGE_HW_USE_FLASH_DEFAULT) {
3731 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(0xffff);
3732 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(
3733 config->tti.uec_d);
3734 }
3735
3736 writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_TX]);
3737 val64 = readq(&vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_TX]);
3738
3739 if (config->tti.timer_ri_en != VXGE_HW_USE_FLASH_DEFAULT) {
3740 if (config->tti.timer_ri_en)
3741 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI;
3742 else
3743 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI;
3744 }
3745
3746 if (config->tti.rtimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
3747 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(
3748 0x3ffffff);
3749 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(
3750 config->tti.rtimer_val);
3751 }
3752
3753 if (config->tti.util_sel != VXGE_HW_USE_FLASH_DEFAULT) {
3754 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(0x3f);
3755 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(
3756 config->tti.util_sel);
3757 }
3758
3759 if (config->tti.ltimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
3760 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL(
3761 0x3ffffff);
3762 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL(
3763 config->tti.ltimer_val);
3764 }
3765
3766 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_TX]);
3767 }
3768
3769 if (config->ring.enable == VXGE_HW_RING_ENABLE) {
3770
3771 val64 = readq(&vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_RX]);
3772
3773 if (config->rti.btimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
3774 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(
3775 0x3ffffff);
3776 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_BTIMER_VAL(
3777 config->rti.btimer_val);
3778 }
3779
3780 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_BITMP_EN;
3781
3782 if (config->rti.timer_ac_en != VXGE_HW_USE_FLASH_DEFAULT) {
3783 if (config->rti.timer_ac_en)
3784 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC;
3785 else
3786 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_TIMER_AC;
3787 }
3788
3789 if (config->rti.timer_ci_en != VXGE_HW_USE_FLASH_DEFAULT) {
3790 if (config->rti.timer_ci_en)
3791 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
3792 else
3793 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
3794 }
3795
3796 if (config->rti.urange_a != VXGE_HW_USE_FLASH_DEFAULT) {
3797 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(0x3f);
3798 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_A(
3799 config->rti.urange_a);
3800 }
3801
3802 if (config->rti.urange_b != VXGE_HW_USE_FLASH_DEFAULT) {
3803 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(0x3f);
3804 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_B(
3805 config->rti.urange_b);
3806 }
3807
3808 if (config->rti.urange_c != VXGE_HW_USE_FLASH_DEFAULT) {
3809 val64 &= ~VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(0x3f);
3810 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_URNG_C(
3811 config->rti.urange_c);
3812 }
3813
3814 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_RX]);
3815 val64 = readq(&vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_RX]);
3816
3817 if (config->rti.uec_a != VXGE_HW_USE_FLASH_DEFAULT) {
3818 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(0xffff);
3819 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_A(
3820 config->rti.uec_a);
3821 }
3822
3823 if (config->rti.uec_b != VXGE_HW_USE_FLASH_DEFAULT) {
3824 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(0xffff);
3825 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(
3826 config->rti.uec_b);
3827 }
3828
3829 if (config->rti.uec_c != VXGE_HW_USE_FLASH_DEFAULT) {
3830 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(0xffff);
3831 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_C(
3832 config->rti.uec_c);
3833 }
3834
3835 if (config->rti.uec_d != VXGE_HW_USE_FLASH_DEFAULT) {
3836 val64 &= ~VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(0xffff);
3837 val64 |= VXGE_HW_TIM_CFG2_INT_NUM_UEC_D(
3838 config->rti.uec_d);
3839 }
3840
3841 writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_RX]);
3842 val64 = readq(&vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_RX]);
3843
3844 if (config->rti.timer_ri_en != VXGE_HW_USE_FLASH_DEFAULT) {
3845 if (config->rti.timer_ri_en)
3846 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI;
3847 else
3848 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_TIMER_RI;
3849 }
3850
3851 if (config->rti.rtimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
3852 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(
3853 0x3ffffff);
3854 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(
3855 config->rti.rtimer_val);
3856 }
3857
3858 if (config->rti.util_sel != VXGE_HW_USE_FLASH_DEFAULT) {
3859 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(0x3f);
3860 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_UTIL_SEL(
3861 config->rti.util_sel);
3862 }
3863
3864 if (config->rti.ltimer_val != VXGE_HW_USE_FLASH_DEFAULT) {
3865 val64 &= ~VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL(
3866 0x3ffffff);
3867 val64 |= VXGE_HW_TIM_CFG3_INT_NUM_LTIMER_VAL(
3868 config->rti.ltimer_val);
3869 }
3870
3871 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_RX]);
3872 }
3873
3874 val64 = 0;
3875 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_EINTA]);
3876 writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_EINTA]);
3877 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_EINTA]);
3878 writeq(val64, &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_BMAP]);
3879 writeq(val64, &vp_reg->tim_cfg2_int_num[VXGE_HW_VPATH_INTR_BMAP]);
3880 writeq(val64, &vp_reg->tim_cfg3_int_num[VXGE_HW_VPATH_INTR_BMAP]);
3881
3882 return status;
3883}
3884
eb5f10c2
SH		 3885void
3886vxge_hw_vpath_tti_ci_set(struct __vxge_hw_device *hldev, u32 vp_id)
3887{
3888 struct __vxge_hw_virtualpath *vpath;
3889 struct vxge_hw_vpath_reg __iomem *vp_reg;
3890 struct vxge_hw_vp_config *config;
3891 u64 val64;
3892
3893 vpath = &hldev->virtual_paths[vp_id];
3894 vp_reg = vpath->vp_reg;
3895 config = vpath->vp_config;
3896
3897 if (config->fifo.enable == VXGE_HW_FIFO_ENABLE) {
3898 val64 = readq(&vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
3899
3900 if (config->tti.timer_ci_en != VXGE_HW_TIM_TIMER_CI_ENABLE) {
3901 config->tti.timer_ci_en = VXGE_HW_TIM_TIMER_CI_ENABLE;
3902 val64 |= VXGE_HW_TIM_CFG1_INT_NUM_TIMER_CI;
3903 writeq(val64,
3904 &vp_reg->tim_cfg1_int_num[VXGE_HW_VPATH_INTR_TX]);
3905 }
3906 }
3907 return;
3908}
40a3a915
RV		 3909/*
3910 * __vxge_hw_vpath_initialize
3911 * This routine is the final phase of init which initializes the
3912 * registers of the vpath using the configuration passed.
3913 */
3914enum vxge_hw_status
3915__vxge_hw_vpath_initialize(struct __vxge_hw_device *hldev, u32 vp_id)
3916{
3917 u64 val64;
3918 u32 val32;
3919 enum vxge_hw_status status = VXGE_HW_OK;
3920 struct __vxge_hw_virtualpath *vpath;
3921 struct vxge_hw_vpath_reg __iomem *vp_reg;
3922
3923 vpath = &hldev->virtual_paths[vp_id];
3924
3925 if (!(hldev->vpath_assignments & vxge_mBIT(vp_id))) {
3926 status = VXGE_HW_ERR_VPATH_NOT_AVAILABLE;
3927 goto exit;
3928 }
3929 vp_reg = vpath->vp_reg;
3930
3931 status = __vxge_hw_vpath_swapper_set(vpath->vp_reg);
3932
3933 if (status != VXGE_HW_OK)
3934 goto exit;
3935
3936 status = __vxge_hw_vpath_mac_configure(hldev, vp_id);
3937
3938 if (status != VXGE_HW_OK)
3939 goto exit;
3940
3941 status = __vxge_hw_vpath_kdfc_configure(hldev, vp_id);
3942
3943 if (status != VXGE_HW_OK)
3944 goto exit;
3945
3946 status = __vxge_hw_vpath_tim_configure(hldev, vp_id);
3947
3948 if (status != VXGE_HW_OK)
3949 goto exit;
3950
40a3a915
RV		 3951 val64 = readq(&vp_reg->rtdma_rd_optimization_ctrl);
3952
3953 /* Get MRRS value from device control */
3954 status = __vxge_hw_vpath_pci_read(vpath, 1, 0x78, &val32);
3955
3956 if (status == VXGE_HW_OK) {
3957 val32 = (val32 & VXGE_HW_PCI_EXP_DEVCTL_READRQ) >> 12;
3958 val64 &=
3959 ~(VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_FILL_THRESH(7));
3960 val64 |=
3961 VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_FILL_THRESH(val32);
3962
3963 val64 |= VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_WAIT_FOR_SPACE;
3964 }
3965
3966 val64 &= ~(VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY(7));
3967 val64 |=
3968 VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY(
3969 VXGE_HW_MAX_PAYLOAD_SIZE_512);
3970
3971 val64 |= VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_FB_ADDR_BDRY_EN;
3972 writeq(val64, &vp_reg->rtdma_rd_optimization_ctrl);
3973
3974exit:
3975 return status;
3976}
3977
3978/*
3979 * __vxge_hw_vp_initialize - Initialize Virtual Path structure
3980 * This routine is the initial phase of init which resets the vpath and
3981 * initializes the software support structures.
3982 */
3983enum vxge_hw_status
3984__vxge_hw_vp_initialize(struct __vxge_hw_device *hldev, u32 vp_id,
3985 struct vxge_hw_vp_config *config)
3986{
3987 struct __vxge_hw_virtualpath *vpath;
3988 enum vxge_hw_status status = VXGE_HW_OK;
3989
3990 if (!(hldev->vpath_assignments & vxge_mBIT(vp_id))) {
3991 status = VXGE_HW_ERR_VPATH_NOT_AVAILABLE;
3992 goto exit;
3993 }
3994
3995 vpath = &hldev->virtual_paths[vp_id];
3996
3997 vpath->vp_id = vp_id;
3998 vpath->vp_open = VXGE_HW_VP_OPEN;
3999 vpath->hldev = hldev;
4000 vpath->vp_config = config;
4001 vpath->vp_reg = hldev->vpath_reg[vp_id];
4002 vpath->vpmgmt_reg = hldev->vpmgmt_reg[vp_id];
4003
4004 __vxge_hw_vpath_reset(hldev, vp_id);
4005
4006 status = __vxge_hw_vpath_reset_check(vpath);
4007
4008 if (status != VXGE_HW_OK) {
4009 memset(vpath, 0, sizeof(struct __vxge_hw_virtualpath));
4010 goto exit;
4011 }
4012
4013 status = __vxge_hw_vpath_mgmt_read(hldev, vpath);
4014
4015 if (status != VXGE_HW_OK) {
4016 memset(vpath, 0, sizeof(struct __vxge_hw_virtualpath));
4017 goto exit;
4018 }
4019
4020 INIT_LIST_HEAD(&vpath->vpath_handles);
4021
4022 vpath->sw_stats = &hldev->stats.sw_dev_info_stats.vpath_info[vp_id];
4023
4024 VXGE_HW_DEVICE_TIM_INT_MASK_SET(hldev->tim_int_mask0,
4025 hldev->tim_int_mask1, vp_id);
4026
4027 status = __vxge_hw_vpath_initialize(hldev, vp_id);
4028
4029 if (status != VXGE_HW_OK)
4030 __vxge_hw_vp_terminate(hldev, vp_id);
4031exit:
4032 return status;
4033}
4034
4035/*
4036 * __vxge_hw_vp_terminate - Terminate Virtual Path structure
4037 * This routine closes all channels it opened and freeup memory
4038 */
4039void
4040__vxge_hw_vp_terminate(struct __vxge_hw_device *hldev, u32 vp_id)
4041{
4042 struct __vxge_hw_virtualpath *vpath;
4043
4044 vpath = &hldev->virtual_paths[vp_id];
4045
4046 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN)
4047 goto exit;
4048
4049 VXGE_HW_DEVICE_TIM_INT_MASK_RESET(vpath->hldev->tim_int_mask0,
4050 vpath->hldev->tim_int_mask1, vpath->vp_id);
4051 hldev->stats.hw_dev_info_stats.vpath_info[vpath->vp_id] = NULL;
4052
4053 memset(vpath, 0, sizeof(struct __vxge_hw_virtualpath));
4054exit:
4055 return;
4056}
4057
4058/*
4059 * vxge_hw_vpath_mtu_set - Set MTU.
4060 * Set new MTU value. Example, to use jumbo frames:
4061 * vxge_hw_vpath_mtu_set(my_device, 9600);
4062 */
4063enum vxge_hw_status
4064vxge_hw_vpath_mtu_set(struct __vxge_hw_vpath_handle *vp, u32 new_mtu)
4065{
4066 u64 val64;
4067 enum vxge_hw_status status = VXGE_HW_OK;
4068 struct __vxge_hw_virtualpath *vpath;
4069
4070 if (vp == NULL) {
4071 status = VXGE_HW_ERR_INVALID_HANDLE;
4072 goto exit;
4073 }
4074 vpath = vp->vpath;
4075
4076 new_mtu += VXGE_HW_MAC_HEADER_MAX_SIZE;
4077
4078 if ((new_mtu < VXGE_HW_MIN_MTU) || (new_mtu > vpath->max_mtu))
4079 status = VXGE_HW_ERR_INVALID_MTU_SIZE;
4080
4081 val64 = readq(&vpath->vp_reg->rxmac_vcfg0);
4082
4083 val64 &= ~VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(0x3fff);
4084 val64 |= VXGE_HW_RXMAC_VCFG0_RTS_MAX_FRM_LEN(new_mtu);
4085
4086 writeq(val64, &vpath->vp_reg->rxmac_vcfg0);
4087
4088 vpath->vp_config->mtu = new_mtu - VXGE_HW_MAC_HEADER_MAX_SIZE;
4089
4090exit:
4091 return status;
4092}
4093
4094/*
4095 * vxge_hw_vpath_open - Open a virtual path on a given adapter
4096 * This function is used to open access to virtual path of an
4097 * adapter for offload, GRO operations. This function returns
4098 * synchronously.
4099 */
4100enum vxge_hw_status
4101vxge_hw_vpath_open(struct __vxge_hw_device *hldev,
4102 struct vxge_hw_vpath_attr *attr,
4103 struct __vxge_hw_vpath_handle **vpath_handle)
4104{
4105 struct __vxge_hw_virtualpath *vpath;
4106 struct __vxge_hw_vpath_handle *vp;
4107 enum vxge_hw_status status;
4108
4109 vpath = &hldev->virtual_paths[attr->vp_id];
4110
4111 if (vpath->vp_open == VXGE_HW_VP_OPEN) {
4112 status = VXGE_HW_ERR_INVALID_STATE;
4113 goto vpath_open_exit1;
4114 }
4115
4116 status = __vxge_hw_vp_initialize(hldev, attr->vp_id,
4117 &hldev->config.vp_config[attr->vp_id]);
4118
4119 if (status != VXGE_HW_OK)
4120 goto vpath_open_exit1;
4121
4122 vp = (struct __vxge_hw_vpath_handle *)
4123 vmalloc(sizeof(struct __vxge_hw_vpath_handle));
4124 if (vp == NULL) {
4125 status = VXGE_HW_ERR_OUT_OF_MEMORY;
4126 goto vpath_open_exit2;
4127 }
4128
4129 memset(vp, 0, sizeof(struct __vxge_hw_vpath_handle));
4130
4131 vp->vpath = vpath;
4132
4133 if (vpath->vp_config->fifo.enable == VXGE_HW_FIFO_ENABLE) {
4134 status = __vxge_hw_fifo_create(vp, &attr->fifo_attr);
4135 if (status != VXGE_HW_OK)
4136 goto vpath_open_exit6;
4137 }
4138
4139 if (vpath->vp_config->ring.enable == VXGE_HW_RING_ENABLE) {
4140 status = __vxge_hw_ring_create(vp, &attr->ring_attr);
4141 if (status != VXGE_HW_OK)
4142 goto vpath_open_exit7;
4143
4144 __vxge_hw_vpath_prc_configure(hldev, attr->vp_id);
4145 }
4146
4147 vpath->fifoh->tx_intr_num =
4148 (attr->vp_id * VXGE_HW_MAX_INTR_PER_VP) +
4149 VXGE_HW_VPATH_INTR_TX;
4150
4151 vpath->stats_block = __vxge_hw_blockpool_block_allocate(hldev,
4152 VXGE_HW_BLOCK_SIZE);
4153
4154 if (vpath->stats_block == NULL) {
4155 status = VXGE_HW_ERR_OUT_OF_MEMORY;
4156 goto vpath_open_exit8;
4157 }
4158
4159 vpath->hw_stats = (struct vxge_hw_vpath_stats_hw_info *)vpath->
4160 stats_block->memblock;
4161 memset(vpath->hw_stats, 0,
4162 sizeof(struct vxge_hw_vpath_stats_hw_info));
4163
4164 hldev->stats.hw_dev_info_stats.vpath_info[attr->vp_id] =
4165 vpath->hw_stats;
4166
4167 vpath->hw_stats_sav =
4168 &hldev->stats.hw_dev_info_stats.vpath_info_sav[attr->vp_id];
4169 memset(vpath->hw_stats_sav, 0,
4170 sizeof(struct vxge_hw_vpath_stats_hw_info));
4171
4172 writeq(vpath->stats_block->dma_addr, &vpath->vp_reg->stats_cfg);
4173
4174 status = vxge_hw_vpath_stats_enable(vp);
4175 if (status != VXGE_HW_OK)
4176 goto vpath_open_exit8;
4177
4178 list_add(&vp->item, &vpath->vpath_handles);
4179
4180 hldev->vpaths_deployed |= vxge_mBIT(vpath->vp_id);
4181
4182 *vpath_handle = vp;
4183
4184 attr->fifo_attr.userdata = vpath->fifoh;
4185 attr->ring_attr.userdata = vpath->ringh;
4186
4187 return VXGE_HW_OK;
4188
4189vpath_open_exit8:
4190 if (vpath->ringh != NULL)
4191 __vxge_hw_ring_delete(vp);
4192vpath_open_exit7:
4193 if (vpath->fifoh != NULL)
4194 __vxge_hw_fifo_delete(vp);
4195vpath_open_exit6:
4196 vfree(vp);
4197vpath_open_exit2:
4198 __vxge_hw_vp_terminate(hldev, attr->vp_id);
4199vpath_open_exit1:
4200
4201 return status;
4202}
4203
4204/**
4205 * vxge_hw_vpath_rx_doorbell_post - Close the handle got from previous vpath
4206 * (vpath) open
4207 * @vp: Handle got from previous vpath open
4208 *
4209 * This function is used to close access to virtual path opened
4210 * earlier.
4211 */
4212void
4213vxge_hw_vpath_rx_doorbell_init(struct __vxge_hw_vpath_handle *vp)
4214{
4215 struct __vxge_hw_virtualpath *vpath = NULL;
4216 u64 new_count, val64, val164;
4217 struct __vxge_hw_ring *ring;
4218
4219 vpath = vp->vpath;
4220 ring = vpath->ringh;
4221
4222 new_count = readq(&vpath->vp_reg->rxdmem_size);
4223 new_count &= 0x1fff;
4224 val164 = (VXGE_HW_RXDMEM_SIZE_PRC_RXDMEM_SIZE(new_count));
4225
4226 writeq(VXGE_HW_PRC_RXD_DOORBELL_NEW_QW_CNT(val164),
4227 &vpath->vp_reg->prc_rxd_doorbell);
4228 readl(&vpath->vp_reg->prc_rxd_doorbell);
4229
4230 val164 /= 2;
4231 val64 = readq(&vpath->vp_reg->prc_cfg6);
4232 val64 = VXGE_HW_PRC_CFG6_RXD_SPAT(val64);
4233 val64 &= 0x1ff;
4234
4235 /*
4236 * Each RxD is of 4 qwords
4237 */
4238 new_count -= (val64 + 1);
4239 val64 = min(val164, new_count) / 4;
4240
4241 ring->rxds_limit = min(ring->rxds_limit, val64);
4242 if (ring->rxds_limit < 4)
4243 ring->rxds_limit = 4;
4244}
4245
4246/*
4247 * vxge_hw_vpath_close - Close the handle got from previous vpath (vpath) open
4248 * This function is used to close access to virtual path opened
4249 * earlier.
4250 */
4251enum vxge_hw_status vxge_hw_vpath_close(struct __vxge_hw_vpath_handle *vp)
4252{
4253 struct __vxge_hw_virtualpath *vpath = NULL;
4254 struct __vxge_hw_device *devh = NULL;
4255 u32 vp_id = vp->vpath->vp_id;
4256 u32 is_empty = TRUE;
4257 enum vxge_hw_status status = VXGE_HW_OK;
4258
4259 vpath = vp->vpath;
4260 devh = vpath->hldev;
4261
4262 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
4263 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
4264 goto vpath_close_exit;
4265 }
4266
4267 list_del(&vp->item);
4268
4269 if (!list_empty(&vpath->vpath_handles)) {
4270 list_add(&vp->item, &vpath->vpath_handles);
4271 is_empty = FALSE;
4272 }
4273
4274 if (!is_empty) {
4275 status = VXGE_HW_FAIL;
4276 goto vpath_close_exit;
4277 }
4278
4279 devh->vpaths_deployed &= ~vxge_mBIT(vp_id);
4280
4281 if (vpath->ringh != NULL)
4282 __vxge_hw_ring_delete(vp);
4283
4284 if (vpath->fifoh != NULL)
4285 __vxge_hw_fifo_delete(vp);
4286
4287 if (vpath->stats_block != NULL)
4288 __vxge_hw_blockpool_block_free(devh, vpath->stats_block);
4289
4290 vfree(vp);
4291
4292 __vxge_hw_vp_terminate(devh, vp_id);
4293
4294 vpath->vp_open = VXGE_HW_VP_NOT_OPEN;
4295
4296vpath_close_exit:
4297 return status;
4298}
4299
4300/*
4301 * vxge_hw_vpath_reset - Resets vpath
4302 * This function is used to request a reset of vpath
4303 */
4304enum vxge_hw_status vxge_hw_vpath_reset(struct __vxge_hw_vpath_handle *vp)
4305{
4306 enum vxge_hw_status status;
4307 u32 vp_id;
4308 struct __vxge_hw_virtualpath *vpath = vp->vpath;
4309
4310 vp_id = vpath->vp_id;
4311
4312 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
4313 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
4314 goto exit;
4315 }
4316
4317 status = __vxge_hw_vpath_reset(vpath->hldev, vp_id);
4318 if (status == VXGE_HW_OK)
4319 vpath->sw_stats->soft_reset_cnt++;
4320exit:
4321 return status;
4322}
4323
4324/*
4325 * vxge_hw_vpath_recover_from_reset - Poll for reset complete and re-initialize.
4326 * This function poll's for the vpath reset completion and re initializes
4327 * the vpath.
4328 */
4329enum vxge_hw_status
4330vxge_hw_vpath_recover_from_reset(struct __vxge_hw_vpath_handle *vp)
4331{
4332 struct __vxge_hw_virtualpath *vpath = NULL;
4333 enum vxge_hw_status status;
4334 struct __vxge_hw_device *hldev;
4335 u32 vp_id;
4336
4337 vp_id = vp->vpath->vp_id;
4338 vpath = vp->vpath;
4339 hldev = vpath->hldev;
4340
4341 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
4342 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
4343 goto exit;
4344 }
4345
4346 status = __vxge_hw_vpath_reset_check(vpath);
4347 if (status != VXGE_HW_OK)
4348 goto exit;
4349
4350 status = __vxge_hw_vpath_sw_reset(hldev, vp_id);
4351 if (status != VXGE_HW_OK)
4352 goto exit;
4353
4354 status = __vxge_hw_vpath_initialize(hldev, vp_id);
4355 if (status != VXGE_HW_OK)
4356 goto exit;
4357
4358 if (vpath->ringh != NULL)
4359 __vxge_hw_vpath_prc_configure(hldev, vp_id);
4360
4361 memset(vpath->hw_stats, 0,
4362 sizeof(struct vxge_hw_vpath_stats_hw_info));
4363
4364 memset(vpath->hw_stats_sav, 0,
4365 sizeof(struct vxge_hw_vpath_stats_hw_info));
4366
4367 writeq(vpath->stats_block->dma_addr,
4368 &vpath->vp_reg->stats_cfg);
4369
4370 status = vxge_hw_vpath_stats_enable(vp);
4371
4372exit:
4373 return status;
4374}
4375
4376/*
4377 * vxge_hw_vpath_enable - Enable vpath.
4378 * This routine clears the vpath reset thereby enabling a vpath
4379 * to start forwarding frames and generating interrupts.
4380 */
4381void
4382vxge_hw_vpath_enable(struct __vxge_hw_vpath_handle *vp)
4383{
4384 struct __vxge_hw_device *hldev;
4385 u64 val64;
4386
4387 hldev = vp->vpath->hldev;
4388
4389 val64 = VXGE_HW_CMN_RSTHDLR_CFG1_CLR_VPATH_RESET(
4390 1 << (16 - vp->vpath->vp_id));
4391
4392 __vxge_hw_pio_mem_write32_upper((u32)vxge_bVALn(val64, 0, 32),
4393 &hldev->common_reg->cmn_rsthdlr_cfg1);
4394}
4395
4396/*
4397 * vxge_hw_vpath_stats_enable - Enable vpath h/wstatistics.
4398 * Enable the DMA vpath statistics. The function is to be called to re-enable
4399 * the adapter to update stats into the host memory
4400 */
4401enum vxge_hw_status
4402vxge_hw_vpath_stats_enable(struct __vxge_hw_vpath_handle *vp)
4403{
4404 enum vxge_hw_status status = VXGE_HW_OK;
4405 struct __vxge_hw_virtualpath *vpath;
4406
4407 vpath = vp->vpath;
4408
4409 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
4410 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
4411 goto exit;
4412 }
4413
4414 memcpy(vpath->hw_stats_sav, vpath->hw_stats,
4415 sizeof(struct vxge_hw_vpath_stats_hw_info));
4416
4417 status = __vxge_hw_vpath_stats_get(vpath, vpath->hw_stats);
4418exit:
4419 return status;
4420}
4421
4422/*
4423 * __vxge_hw_vpath_stats_access - Get the statistics from the given location
4424 * and offset and perform an operation
4425 */
4426enum vxge_hw_status
4427__vxge_hw_vpath_stats_access(struct __vxge_hw_virtualpath *vpath,
4428 u32 operation, u32 offset, u64 *stat)
4429{
4430 u64 val64;
4431 enum vxge_hw_status status = VXGE_HW_OK;
4432 struct vxge_hw_vpath_reg __iomem *vp_reg;
4433
4434 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
4435 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
4436 goto vpath_stats_access_exit;
4437 }
4438
4439 vp_reg = vpath->vp_reg;
4440
4441 val64 = VXGE_HW_XMAC_STATS_ACCESS_CMD_OP(operation) |
4442 VXGE_HW_XMAC_STATS_ACCESS_CMD_STROBE |
4443 VXGE_HW_XMAC_STATS_ACCESS_CMD_OFFSET_SEL(offset);
4444
4445 status = __vxge_hw_pio_mem_write64(val64,
4446 &vp_reg->xmac_stats_access_cmd,
4447 VXGE_HW_XMAC_STATS_ACCESS_CMD_STROBE,
4448 vpath->hldev->config.device_poll_millis);
4449
4450 if ((status == VXGE_HW_OK) && (operation == VXGE_HW_STATS_OP_READ))
4451 *stat = readq(&vp_reg->xmac_stats_access_data);
4452 else
4453 *stat = 0;
4454
4455vpath_stats_access_exit:
4456 return status;
4457}
4458
4459/*
4460 * __vxge_hw_vpath_xmac_tx_stats_get - Get the TX Statistics of a vpath
4461 */
4462enum vxge_hw_status
4463__vxge_hw_vpath_xmac_tx_stats_get(
4464 struct __vxge_hw_virtualpath *vpath,
4465 struct vxge_hw_xmac_vpath_tx_stats *vpath_tx_stats)
4466{
4467 u64 *val64;
4468 int i;
4469 u32 offset = VXGE_HW_STATS_VPATH_TX_OFFSET;
4470 enum vxge_hw_status status = VXGE_HW_OK;
4471
4472 val64 = (u64 *) vpath_tx_stats;
4473
4474 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
4475 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
4476 goto exit;
4477 }
4478
4479 for (i = 0; i < sizeof(struct vxge_hw_xmac_vpath_tx_stats) / 8; i++) {
4480 status = __vxge_hw_vpath_stats_access(vpath,
4481 VXGE_HW_STATS_OP_READ,
4482 offset, val64);
4483 if (status != VXGE_HW_OK)
4484 goto exit;
4485 offset++;
4486 val64++;
4487 }
4488exit:
4489 return status;
4490}
4491
4492/*
4493 * __vxge_hw_vpath_xmac_rx_stats_get - Get the RX Statistics of a vpath
4494 */
4495enum vxge_hw_status
4496__vxge_hw_vpath_xmac_rx_stats_get(struct __vxge_hw_virtualpath *vpath,
4497 struct vxge_hw_xmac_vpath_rx_stats *vpath_rx_stats)
4498{
4499 u64 *val64;
4500 enum vxge_hw_status status = VXGE_HW_OK;
4501 int i;
4502 u32 offset = VXGE_HW_STATS_VPATH_RX_OFFSET;
4503 val64 = (u64 *) vpath_rx_stats;
4504
4505 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
4506 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
4507 goto exit;
4508 }
4509 for (i = 0; i < sizeof(struct vxge_hw_xmac_vpath_rx_stats) / 8; i++) {
4510 status = __vxge_hw_vpath_stats_access(vpath,
4511 VXGE_HW_STATS_OP_READ,
4512 offset >> 3, val64);
4513 if (status != VXGE_HW_OK)
4514 goto exit;
4515
4516 offset += 8;
4517 val64++;
4518 }
4519exit:
4520 return status;
4521}
4522
4523/*
4524 * __vxge_hw_vpath_stats_get - Get the vpath hw statistics.
4525 */
4526enum vxge_hw_status __vxge_hw_vpath_stats_get(
4527 struct __vxge_hw_virtualpath *vpath,
4528 struct vxge_hw_vpath_stats_hw_info *hw_stats)
4529{
4530 u64 val64;
4531 enum vxge_hw_status status = VXGE_HW_OK;
4532 struct vxge_hw_vpath_reg __iomem *vp_reg;
4533
4534 if (vpath->vp_open == VXGE_HW_VP_NOT_OPEN) {
4535 status = VXGE_HW_ERR_VPATH_NOT_OPEN;
4536 goto exit;
4537 }
4538 vp_reg = vpath->vp_reg;
4539
4540 val64 = readq(&vp_reg->vpath_debug_stats0);
4541 hw_stats->ini_num_mwr_sent =
4542 (u32)VXGE_HW_VPATH_DEBUG_STATS0_GET_INI_NUM_MWR_SENT(val64);
4543
4544 val64 = readq(&vp_reg->vpath_debug_stats1);
4545 hw_stats->ini_num_mrd_sent =
4546 (u32)VXGE_HW_VPATH_DEBUG_STATS1_GET_INI_NUM_MRD_SENT(val64);
4547
4548 val64 = readq(&vp_reg->vpath_debug_stats2);
4549 hw_stats->ini_num_cpl_rcvd =
4550 (u32)VXGE_HW_VPATH_DEBUG_STATS2_GET_INI_NUM_CPL_RCVD(val64);
4551
4552 val64 = readq(&vp_reg->vpath_debug_stats3);
4553 hw_stats->ini_num_mwr_byte_sent =
4554 VXGE_HW_VPATH_DEBUG_STATS3_GET_INI_NUM_MWR_BYTE_SENT(val64);
4555
4556 val64 = readq(&vp_reg->vpath_debug_stats4);
4557 hw_stats->ini_num_cpl_byte_rcvd =
4558 VXGE_HW_VPATH_DEBUG_STATS4_GET_INI_NUM_CPL_BYTE_RCVD(val64);
4559
4560 val64 = readq(&vp_reg->vpath_debug_stats5);
4561 hw_stats->wrcrdtarb_xoff =
4562 (u32)VXGE_HW_VPATH_DEBUG_STATS5_GET_WRCRDTARB_XOFF(val64);
4563
4564 val64 = readq(&vp_reg->vpath_debug_stats6);
4565 hw_stats->rdcrdtarb_xoff =
4566 (u32)VXGE_HW_VPATH_DEBUG_STATS6_GET_RDCRDTARB_XOFF(val64);
4567
4568 val64 = readq(&vp_reg->vpath_genstats_count01);
4569 hw_stats->vpath_genstats_count0 =
4570 (u32)VXGE_HW_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT0(
4571 val64);
4572
4573 val64 = readq(&vp_reg->vpath_genstats_count01);
4574 hw_stats->vpath_genstats_count1 =
4575 (u32)VXGE_HW_VPATH_GENSTATS_COUNT01_GET_PPIF_VPATH_GENSTATS_COUNT1(
4576 val64);
4577
4578 val64 = readq(&vp_reg->vpath_genstats_count23);
4579 hw_stats->vpath_genstats_count2 =
4580 (u32)VXGE_HW_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT2(
4581 val64);
4582
4583 val64 = readq(&vp_reg->vpath_genstats_count01);
4584 hw_stats->vpath_genstats_count3 =
4585 (u32)VXGE_HW_VPATH_GENSTATS_COUNT23_GET_PPIF_VPATH_GENSTATS_COUNT3(
4586 val64);
4587
4588 val64 = readq(&vp_reg->vpath_genstats_count4);
4589 hw_stats->vpath_genstats_count4 =
4590 (u32)VXGE_HW_VPATH_GENSTATS_COUNT4_GET_PPIF_VPATH_GENSTATS_COUNT4(
4591 val64);
4592
4593 val64 = readq(&vp_reg->vpath_genstats_count5);
4594 hw_stats->vpath_genstats_count5 =
4595 (u32)VXGE_HW_VPATH_GENSTATS_COUNT5_GET_PPIF_VPATH_GENSTATS_COUNT5(
4596 val64);
4597
4598 status = __vxge_hw_vpath_xmac_tx_stats_get(vpath, &hw_stats->tx_stats);
4599 if (status != VXGE_HW_OK)
4600 goto exit;
4601
4602 status = __vxge_hw_vpath_xmac_rx_stats_get(vpath, &hw_stats->rx_stats);
4603 if (status != VXGE_HW_OK)
4604 goto exit;
4605
4606 VXGE_HW_VPATH_STATS_PIO_READ(
4607 VXGE_HW_STATS_VPATH_PROG_EVENT_VNUM0_OFFSET);
4608
4609 hw_stats->prog_event_vnum0 =
4610 (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM0(val64);
4611
4612 hw_stats->prog_event_vnum1 =
4613 (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM1(val64);
4614
4615 VXGE_HW_VPATH_STATS_PIO_READ(
4616 VXGE_HW_STATS_VPATH_PROG_EVENT_VNUM2_OFFSET);
4617
4618 hw_stats->prog_event_vnum2 =
4619 (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM2(val64);
4620
4621 hw_stats->prog_event_vnum3 =
4622 (u32)VXGE_HW_STATS_GET_VPATH_PROG_EVENT_VNUM3(val64);
4623
4624 val64 = readq(&vp_reg->rx_multi_cast_stats);
4625 hw_stats->rx_multi_cast_frame_discard =
4626 (u16)VXGE_HW_RX_MULTI_CAST_STATS_GET_FRAME_DISCARD(val64);
4627
4628 val64 = readq(&vp_reg->rx_frm_transferred);
4629 hw_stats->rx_frm_transferred =
4630 (u32)VXGE_HW_RX_FRM_TRANSFERRED_GET_RX_FRM_TRANSFERRED(val64);
4631
4632 val64 = readq(&vp_reg->rxd_returned);
4633 hw_stats->rxd_returned =
4634 (u16)VXGE_HW_RXD_RETURNED_GET_RXD_RETURNED(val64);
4635
4636 val64 = readq(&vp_reg->dbg_stats_rx_mpa);
4637 hw_stats->rx_mpa_len_fail_frms =
4638 (u16)VXGE_HW_DBG_STATS_GET_RX_MPA_LEN_FAIL_FRMS(val64);
4639 hw_stats->rx_mpa_mrk_fail_frms =
4640 (u16)VXGE_HW_DBG_STATS_GET_RX_MPA_MRK_FAIL_FRMS(val64);
4641 hw_stats->rx_mpa_crc_fail_frms =
4642 (u16)VXGE_HW_DBG_STATS_GET_RX_MPA_CRC_FAIL_FRMS(val64);
4643
4644 val64 = readq(&vp_reg->dbg_stats_rx_fau);
4645 hw_stats->rx_permitted_frms =
4646 (u16)VXGE_HW_DBG_STATS_GET_RX_FAU_RX_PERMITTED_FRMS(val64);
4647 hw_stats->rx_vp_reset_discarded_frms =
4648 (u16)VXGE_HW_DBG_STATS_GET_RX_FAU_RX_VP_RESET_DISCARDED_FRMS(val64);
4649 hw_stats->rx_wol_frms =
4650 (u16)VXGE_HW_DBG_STATS_GET_RX_FAU_RX_WOL_FRMS(val64);
4651
4652 val64 = readq(&vp_reg->tx_vp_reset_discarded_frms);
4653 hw_stats->tx_vp_reset_discarded_frms =
4654 (u16)VXGE_HW_TX_VP_RESET_DISCARDED_FRMS_GET_TX_VP_RESET_DISCARDED_FRMS(
4655 val64);
4656exit:
4657 return status;
4658}
4659
4660/*
4661 * __vxge_hw_blockpool_create - Create block pool
4662 */
4663
4664enum vxge_hw_status
4665__vxge_hw_blockpool_create(struct __vxge_hw_device *hldev,
4666 struct __vxge_hw_blockpool *blockpool,
4667 u32 pool_size,
4668 u32 pool_max)
4669{
4670 u32 i;
4671 struct __vxge_hw_blockpool_entry *entry = NULL;
4672 void *memblock;
4673 dma_addr_t dma_addr;
4674 struct pci_dev *dma_handle;
4675 struct pci_dev *acc_handle;
4676 enum vxge_hw_status status = VXGE_HW_OK;
4677
4678 if (blockpool == NULL) {
4679 status = VXGE_HW_FAIL;
4680 goto blockpool_create_exit;
4681 }
4682
4683 blockpool->hldev = hldev;
4684 blockpool->block_size = VXGE_HW_BLOCK_SIZE;
4685 blockpool->pool_size = 0;
4686 blockpool->pool_max = pool_max;
4687 blockpool->req_out = 0;
4688
4689 INIT_LIST_HEAD(&blockpool->free_block_list);
4690 INIT_LIST_HEAD(&blockpool->free_entry_list);
4691
4692 for (i = 0; i < pool_size + pool_max; i++) {
4693 entry = kzalloc(sizeof(struct __vxge_hw_blockpool_entry),
4694 GFP_KERNEL);
4695 if (entry == NULL) {
4696 __vxge_hw_blockpool_destroy(blockpool);
4697 status = VXGE_HW_ERR_OUT_OF_MEMORY;
4698 goto blockpool_create_exit;
4699 }
4700 list_add(&entry->item, &blockpool->free_entry_list);
4701 }
4702
4703 for (i = 0; i < pool_size; i++) {
4704
4705 memblock = vxge_os_dma_malloc(
4706 hldev->pdev,
4707 VXGE_HW_BLOCK_SIZE,
4708 &dma_handle,
4709 &acc_handle);
4710
4711 if (memblock == NULL) {
4712 __vxge_hw_blockpool_destroy(blockpool);
4713 status = VXGE_HW_ERR_OUT_OF_MEMORY;
4714 goto blockpool_create_exit;
4715 }
4716
4717 dma_addr = pci_map_single(hldev->pdev, memblock,
4718 VXGE_HW_BLOCK_SIZE, PCI_DMA_BIDIRECTIONAL);
4719
4720 if (unlikely(pci_dma_mapping_error(hldev->pdev,
4721 dma_addr))) {
4722
4723 vxge_os_dma_free(hldev->pdev, memblock, &acc_handle);
4724 __vxge_hw_blockpool_destroy(blockpool);
4725 status = VXGE_HW_ERR_OUT_OF_MEMORY;
4726 goto blockpool_create_exit;
4727 }
4728
4729 if (!list_empty(&blockpool->free_entry_list))
4730 entry = (struct __vxge_hw_blockpool_entry *)
4731 list_first_entry(&blockpool->free_entry_list,
4732 struct __vxge_hw_blockpool_entry,
4733 item);
4734
4735 if (entry == NULL)
4736 entry =
4737 kzalloc(sizeof(struct __vxge_hw_blockpool_entry),
4738 GFP_KERNEL);
4739 if (entry != NULL) {
4740 list_del(&entry->item);
4741 entry->length = VXGE_HW_BLOCK_SIZE;
4742 entry->memblock = memblock;
4743 entry->dma_addr = dma_addr;
4744 entry->acc_handle = acc_handle;
4745 entry->dma_handle = dma_handle;
4746 list_add(&entry->item,
4747 &blockpool->free_block_list);
4748 blockpool->pool_size++;
4749 } else {
4750 __vxge_hw_blockpool_destroy(blockpool);
4751 status = VXGE_HW_ERR_OUT_OF_MEMORY;
4752 goto blockpool_create_exit;
4753 }
4754 }
4755
4756blockpool_create_exit:
4757 return status;
4758}
4759
4760/*
4761 * __vxge_hw_blockpool_destroy - Deallocates the block pool
4762 */
4763
4764void __vxge_hw_blockpool_destroy(struct __vxge_hw_blockpool *blockpool)
4765{
4766
4767 struct __vxge_hw_device *hldev;
4768 struct list_head *p, *n;
4769 u16 ret;
4770
4771 if (blockpool == NULL) {
4772 ret = 1;
4773 goto exit;
4774 }
4775
4776 hldev = blockpool->hldev;
4777
4778 list_for_each_safe(p, n, &blockpool->free_block_list) {
4779
4780 pci_unmap_single(hldev->pdev,
4781 ((struct __vxge_hw_blockpool_entry *)p)->dma_addr,
4782 ((struct __vxge_hw_blockpool_entry *)p)->length,
4783 PCI_DMA_BIDIRECTIONAL);
4784
4785 vxge_os_dma_free(hldev->pdev,
4786 ((struct __vxge_hw_blockpool_entry *)p)->memblock,
4787 &((struct __vxge_hw_blockpool_entry *) p)->acc_handle);
4788
4789 list_del(
4790 &((struct __vxge_hw_blockpool_entry *)p)->item);
4791 kfree(p);
4792 blockpool->pool_size--;
4793 }
4794
4795 list_for_each_safe(p, n, &blockpool->free_entry_list) {
4796 list_del(
4797 &((struct __vxge_hw_blockpool_entry *)p)->item);
4798 kfree((void *)p);
4799 }
4800 ret = 0;
4801exit:
4802 return;
4803}
4804
4805/*
4806 * __vxge_hw_blockpool_blocks_add - Request additional blocks
4807 */
4808static
4809void __vxge_hw_blockpool_blocks_add(struct __vxge_hw_blockpool *blockpool)
4810{
4811 u32 nreq = 0, i;
4812
4813 if ((blockpool->pool_size + blockpool->req_out) <
4814 VXGE_HW_MIN_DMA_BLOCK_POOL_SIZE) {
4815 nreq = VXGE_HW_INCR_DMA_BLOCK_POOL_SIZE;
4816 blockpool->req_out += nreq;
4817 }
4818
4819 for (i = 0; i < nreq; i++)
4820 vxge_os_dma_malloc_async(
4821 ((struct __vxge_hw_device *)blockpool->hldev)->pdev,
4822 blockpool->hldev, VXGE_HW_BLOCK_SIZE);
4823}
4824
4825/*
4826 * __vxge_hw_blockpool_blocks_remove - Free additional blocks
4827 */
4828static
4829void __vxge_hw_blockpool_blocks_remove(struct __vxge_hw_blockpool *blockpool)
4830{
4831 struct list_head *p, *n;
4832
4833 list_for_each_safe(p, n, &blockpool->free_block_list) {
4834
4835 if (blockpool->pool_size < blockpool->pool_max)
4836 break;
4837
4838 pci_unmap_single(
4839 ((struct __vxge_hw_device *)blockpool->hldev)->pdev,
4840 ((struct __vxge_hw_blockpool_entry *)p)->dma_addr,
4841 ((struct __vxge_hw_blockpool_entry *)p)->length,
4842 PCI_DMA_BIDIRECTIONAL);
4843
4844 vxge_os_dma_free(
4845 ((struct __vxge_hw_device *)blockpool->hldev)->pdev,
4846 ((struct __vxge_hw_blockpool_entry *)p)->memblock,
4847 &((struct __vxge_hw_blockpool_entry *)p)->acc_handle);
4848
4849 list_del(&((struct __vxge_hw_blockpool_entry *)p)->item);
4850
4851 list_add(p, &blockpool->free_entry_list);
4852
4853 blockpool->pool_size--;
4854
4855 }
4856}
4857
4858/*
4859 * vxge_hw_blockpool_block_add - callback for vxge_os_dma_malloc_async
4860 * Adds a block to block pool
4861 */
4862void vxge_hw_blockpool_block_add(
4863 struct __vxge_hw_device *devh,
4864 void *block_addr,
4865 u32 length,
4866 struct pci_dev *dma_h,
4867 struct pci_dev *acc_handle)
4868{
4869 struct __vxge_hw_blockpool *blockpool;
4870 struct __vxge_hw_blockpool_entry *entry = NULL;
4871 dma_addr_t dma_addr;
4872 enum vxge_hw_status status = VXGE_HW_OK;
4873 u32 req_out;
4874
4875 blockpool = &devh->block_pool;
4876
4877 if (block_addr == NULL) {
4878 blockpool->req_out--;
4879 status = VXGE_HW_FAIL;
4880 goto exit;
4881 }
4882
4883 dma_addr = pci_map_single(devh->pdev, block_addr, length,
4884 PCI_DMA_BIDIRECTIONAL);
4885
4886 if (unlikely(pci_dma_mapping_error(devh->pdev, dma_addr))) {
4887
4888 vxge_os_dma_free(devh->pdev, block_addr, &acc_handle);
4889 blockpool->req_out--;
4890 status = VXGE_HW_FAIL;
4891 goto exit;
4892 }
4893
4894
4895 if (!list_empty(&blockpool->free_entry_list))
4896 entry = (struct __vxge_hw_blockpool_entry *)
4897 list_first_entry(&blockpool->free_entry_list,
4898 struct __vxge_hw_blockpool_entry,
4899 item);
4900
4901 if (entry == NULL)
4902 entry = (struct __vxge_hw_blockpool_entry *)
4903 vmalloc(sizeof(struct __vxge_hw_blockpool_entry));
4904 else
4905 list_del(&entry->item);
4906
4907 if (entry != NULL) {
4908 entry->length = length;
4909 entry->memblock = block_addr;
4910 entry->dma_addr = dma_addr;
4911 entry->acc_handle = acc_handle;
4912 entry->dma_handle = dma_h;
4913 list_add(&entry->item, &blockpool->free_block_list);
4914 blockpool->pool_size++;
4915 status = VXGE_HW_OK;
4916 } else
4917 status = VXGE_HW_ERR_OUT_OF_MEMORY;
4918
4919 blockpool->req_out--;
4920
4921 req_out = blockpool->req_out;
4922exit:
4923 return;
4924}
4925
4926/*
4927 * __vxge_hw_blockpool_malloc - Allocate a memory block from pool
4928 * Allocates a block of memory of given size, either from block pool
4929 * or by calling vxge_os_dma_malloc()
4930 */
4931void *
4932__vxge_hw_blockpool_malloc(struct __vxge_hw_device *devh, u32 size,
4933 struct vxge_hw_mempool_dma *dma_object)
4934{
4935 struct __vxge_hw_blockpool_entry *entry = NULL;
4936 struct __vxge_hw_blockpool *blockpool;
4937 void *memblock = NULL;
4938 enum vxge_hw_status status = VXGE_HW_OK;
4939
4940 blockpool = &devh->block_pool;
4941
4942 if (size != blockpool->block_size) {
4943
4944 memblock = vxge_os_dma_malloc(devh->pdev, size,
4945 &dma_object->handle,
4946 &dma_object->acc_handle);
4947
4948 if (memblock == NULL) {
4949 status = VXGE_HW_ERR_OUT_OF_MEMORY;
4950 goto exit;
4951 }
4952
4953 dma_object->addr = pci_map_single(devh->pdev, memblock, size,
4954 PCI_DMA_BIDIRECTIONAL);
4955
4956 if (unlikely(pci_dma_mapping_error(devh->pdev,
4957 dma_object->addr))) {
4958 vxge_os_dma_free(devh->pdev, memblock,
4959 &dma_object->acc_handle);
4960 status = VXGE_HW_ERR_OUT_OF_MEMORY;
4961 goto exit;
4962 }
4963
4964 } else {
4965
4966 if (!list_empty(&blockpool->free_block_list))
4967 entry = (struct __vxge_hw_blockpool_entry *)
4968 list_first_entry(&blockpool->free_block_list,
4969 struct __vxge_hw_blockpool_entry,
4970 item);
4971
4972 if (entry != NULL) {
4973 list_del(&entry->item);
4974 dma_object->addr = entry->dma_addr;
4975 dma_object->handle = entry->dma_handle;
4976 dma_object->acc_handle = entry->acc_handle;
4977 memblock = entry->memblock;
4978
4979 list_add(&entry->item,
4980 &blockpool->free_entry_list);
4981 blockpool->pool_size--;
4982 }
4983
4984 if (memblock != NULL)
4985 __vxge_hw_blockpool_blocks_add(blockpool);
4986 }
4987exit:
4988 return memblock;
4989}
4990
4991/*
4992 * __vxge_hw_blockpool_free - Frees the memory allcoated with
4993 __vxge_hw_blockpool_malloc
4994 */
4995void
4996__vxge_hw_blockpool_free(struct __vxge_hw_device *devh,
4997 void *memblock, u32 size,
4998 struct vxge_hw_mempool_dma *dma_object)
4999{
5000 struct __vxge_hw_blockpool_entry *entry = NULL;
5001 struct __vxge_hw_blockpool *blockpool;
5002 enum vxge_hw_status status = VXGE_HW_OK;
5003
5004 blockpool = &devh->block_pool;
5005
5006 if (size != blockpool->block_size) {
5007 pci_unmap_single(devh->pdev, dma_object->addr, size,
5008 PCI_DMA_BIDIRECTIONAL);
5009 vxge_os_dma_free(devh->pdev, memblock, &dma_object->acc_handle);
5010 } else {
5011
5012 if (!list_empty(&blockpool->free_entry_list))
5013 entry = (struct __vxge_hw_blockpool_entry *)
5014 list_first_entry(&blockpool->free_entry_list,
5015 struct __vxge_hw_blockpool_entry,
5016 item);
5017
5018 if (entry == NULL)
5019 entry = (struct __vxge_hw_blockpool_entry *)
5020 vmalloc(sizeof(
5021 struct __vxge_hw_blockpool_entry));
5022 else
5023 list_del(&entry->item);
5024
5025 if (entry != NULL) {
5026 entry->length = size;
5027 entry->memblock = memblock;
5028 entry->dma_addr = dma_object->addr;
5029 entry->acc_handle = dma_object->acc_handle;
5030 entry->dma_handle = dma_object->handle;
5031 list_add(&entry->item,
5032 &blockpool->free_block_list);
5033 blockpool->pool_size++;
5034 status = VXGE_HW_OK;
5035 } else
5036 status = VXGE_HW_ERR_OUT_OF_MEMORY;
5037
5038 if (status == VXGE_HW_OK)
5039 __vxge_hw_blockpool_blocks_remove(blockpool);
5040 }
5041
5042 return;
5043}
5044
5045/*
5046 * __vxge_hw_blockpool_block_allocate - Allocates a block from block pool
5047 * This function allocates a block from block pool or from the system
5048 */
5049struct __vxge_hw_blockpool_entry *
5050__vxge_hw_blockpool_block_allocate(struct __vxge_hw_device *devh, u32 size)
5051{
5052 struct __vxge_hw_blockpool_entry *entry = NULL;
5053 struct __vxge_hw_blockpool *blockpool;
5054
5055 blockpool = &devh->block_pool;
5056
5057 if (size == blockpool->block_size) {
5058
5059 if (!list_empty(&blockpool->free_block_list))
5060 entry = (struct __vxge_hw_blockpool_entry *)
5061 list_first_entry(&blockpool->free_block_list,
5062 struct __vxge_hw_blockpool_entry,
5063 item);
5064
5065 if (entry != NULL) {
5066 list_del(&entry->item);
5067 blockpool->pool_size--;
5068 }
5069 }
5070
5071 if (entry != NULL)
5072 __vxge_hw_blockpool_blocks_add(blockpool);
5073
5074 return entry;
5075}
5076
5077/*
5078 * __vxge_hw_blockpool_block_free - Frees a block from block pool
5079 * @devh: Hal device
5080 * @entry: Entry of block to be freed
5081 *
5082 * This function frees a block from block pool
5083 */
5084void
5085__vxge_hw_blockpool_block_free(struct __vxge_hw_device *devh,
5086 struct __vxge_hw_blockpool_entry *entry)
5087{
5088 struct __vxge_hw_blockpool *blockpool;
5089
5090 blockpool = &devh->block_pool;
5091
5092 if (entry->length == blockpool->block_size) {
5093 list_add(&entry->item, &blockpool->free_block_list);
5094 blockpool->pool_size++;
5095 }
5096
5097 __vxge_hw_blockpool_blocks_remove(blockpool);
5098
5099 return;
5100}
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