[mirror_ubuntu-bionic-kernel.git] / drivers / net / wan / c101.c

/*
 * Moxa C101 synchronous serial card driver for Linux
 *
 * Copyright (C) 2000-2003 Krzysztof Halasa <khc@pm.waw.pl>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of version 2 of the GNU General Public License
 * as published by the Free Software Foundation.
 *
 * For information see <http://www.kernel.org/pub/linux/utils/net/hdlc/>
 *
 * Sources of information:
 *    Hitachi HD64570 SCA User's Manual
 *    Moxa C101 User's Manual
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/types.h>
#include <linux/string.h>
#include <linux/errno.h>
#include <linux/init.h>
#include <linux/moduleparam.h>
#include <linux/netdevice.h>
#include <linux/hdlc.h>
#include <linux/delay.h>
#include <asm/io.h>

#include "hd64570.h"


static const char* version = "Moxa C101 driver version: 1.15";
static const char* devname = "C101";

#undef DEBUG_PKT
#define DEBUG_RINGS

#define C101_PAGE 0x1D00
#define C101_DTR 0x1E00
#define C101_SCA 0x1F00
#define C101_WINDOW_SIZE 0x2000
#define C101_MAPPED_RAM_SIZE 0x4000

#define RAM_SIZE (256 * 1024)
#define TX_RING_BUFFERS 10
#define RX_RING_BUFFERS ((RAM_SIZE - C101_WINDOW_SIZE) /		\
			 (sizeof(pkt_desc) + HDLC_MAX_MRU) - TX_RING_BUFFERS)

#define CLOCK_BASE 9830400	/* 9.8304 MHz */
#define PAGE0_ALWAYS_MAPPED

static char *hw;		/* pointer to hw=xxx command line string */


typedef struct card_s {
	struct net_device *dev;
	spinlock_t lock;	/* TX lock */
	u8 __iomem *win0base;	/* ISA window base address */
	u32 phy_winbase;	/* ISA physical base address */
	sync_serial_settings settings;
	int rxpart;		/* partial frame received, next frame invalid*/
	unsigned short encoding;
	unsigned short parity;
	u16 rx_ring_buffers;	/* number of buffers in a ring */
	u16 tx_ring_buffers;
	u16 buff_offset;	/* offset of first buffer of first channel */
	u16 rxin;		/* rx ring buffer 'in' pointer */
	u16 txin;		/* tx ring buffer 'in' and 'last' pointers */
	u16 txlast;
	u8 rxs, txs, tmc;	/* SCA registers */
	u8 irq;			/* IRQ (3-15) */
	u8 page;

	struct card_s *next_card;
}card_t;

typedef card_t port_t;

static card_t *first_card;
static card_t **new_card = &first_card;


#define sca_in(reg, card)	   readb((card)->win0base + C101_SCA + (reg))
#define sca_out(value, reg, card)  writeb(value, (card)->win0base + C101_SCA + (reg))
#define sca_inw(reg, card)	   readw((card)->win0base + C101_SCA + (reg))

/* EDA address register must be set in EDAL, EDAH order - 8 bit ISA bus */
#define sca_outw(value, reg, card) do { \
	writeb(value & 0xFF, (card)->win0base + C101_SCA + (reg)); \
	writeb((value >> 8 ) & 0xFF, (card)->win0base + C101_SCA + (reg+1));\
} while(0)

#define port_to_card(port)	   (port)
#define log_node(port)		   (0)
#define phy_node(port)		   (0)
#define winsize(card)		   (C101_WINDOW_SIZE)
#define win0base(card)		   ((card)->win0base)
#define winbase(card)      	   ((card)->win0base + 0x2000)
#define get_port(card, port)	   (card)
static void sca_msci_intr(port_t *port);


static inline u8 sca_get_page(card_t *card)
{
	return card->page;
}

static inline void openwin(card_t *card, u8 page)
{
	card->page = page;
	writeb(page, card->win0base + C101_PAGE);
}


#include "hd6457x.c"


static inline void set_carrier(port_t *port)
{
	if (!(sca_in(MSCI1_OFFSET + ST3, port) & ST3_DCD))
		netif_carrier_on(port_to_dev(port));
	else
		netif_carrier_off(port_to_dev(port));
}


static void sca_msci_intr(port_t *port)
{
	u8 stat = sca_in(MSCI0_OFFSET + ST1, port); /* read MSCI ST1 status */

	/* Reset MSCI TX underrun and CDCD (ignored) status bit */
	sca_out(stat & (ST1_UDRN | ST1_CDCD), MSCI0_OFFSET + ST1, port);

	if (stat & ST1_UDRN) {
		/* TX Underrun error detected */
		port_to_dev(port)->stats.tx_errors++;
		port_to_dev(port)->stats.tx_fifo_errors++;
	}

	stat = sca_in(MSCI1_OFFSET + ST1, port); /* read MSCI1 ST1 status */
	/* Reset MSCI CDCD status bit - uses ch#2 DCD input */
	sca_out(stat & ST1_CDCD, MSCI1_OFFSET + ST1, port);

	if (stat & ST1_CDCD)
		set_carrier(port);
}


static void c101_set_iface(port_t *port)
{
	u8 rxs = port->rxs & CLK_BRG_MASK;
	u8 txs = port->txs & CLK_BRG_MASK;

	switch(port->settings.clock_type) {
	case CLOCK_INT:
		rxs |= CLK_BRG_RX; /* TX clock */
		txs |= CLK_RXCLK_TX; /* BRG output */
		break;

	case CLOCK_TXINT:
		rxs |= CLK_LINE_RX; /* RXC input */
		txs |= CLK_BRG_TX; /* BRG output */
		break;

	case CLOCK_TXFROMRX:
		rxs |= CLK_LINE_RX; /* RXC input */
		txs |= CLK_RXCLK_TX; /* RX clock */
		break;

	default:	/* EXTernal clock */
		rxs |= CLK_LINE_RX; /* RXC input */
		txs |= CLK_LINE_TX; /* TXC input */
	}

	port->rxs = rxs;
	port->txs = txs;
	sca_out(rxs, MSCI1_OFFSET + RXS, port);
	sca_out(txs, MSCI1_OFFSET + TXS, port);
	sca_set_port(port);
}


static int c101_open(struct net_device *dev)
{
	port_t *port = dev_to_port(dev);
	int result;

	result = hdlc_open(dev);
	if (result)
		return result;

	writeb(1, port->win0base + C101_DTR);
	sca_out(0, MSCI1_OFFSET + CTL, port); /* RTS uses ch#2 output */
	sca_open(dev);
	/* DCD is connected to port 2 !@#$%^& - disable MSCI0 CDCD interrupt */
	sca_out(IE1_UDRN, MSCI0_OFFSET + IE1, port);
	sca_out(IE0_TXINT, MSCI0_OFFSET + IE0, port);

	set_carrier(port);

	/* enable MSCI1 CDCD interrupt */
	sca_out(IE1_CDCD, MSCI1_OFFSET + IE1, port);
	sca_out(IE0_RXINTA, MSCI1_OFFSET + IE0, port);
	sca_out(0x48, IER0, port); /* TXINT #0 and RXINT #1 */
	c101_set_iface(port);
	return 0;
}


static int c101_close(struct net_device *dev)
{
	port_t *port = dev_to_port(dev);

	sca_close(dev);
	writeb(0, port->win0base + C101_DTR);
	sca_out(CTL_NORTS, MSCI1_OFFSET + CTL, port);
	hdlc_close(dev);
	return 0;
}


static int c101_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
{
	const size_t size = sizeof(sync_serial_settings);
	sync_serial_settings new_line;
	sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
	port_t *port = dev_to_port(dev);

#ifdef DEBUG_RINGS
	if (cmd == SIOCDEVPRIVATE) {
		sca_dump_rings(dev);
		printk(KERN_DEBUG "MSCI1: ST: %02x %02x %02x %02x\n",
		       sca_in(MSCI1_OFFSET + ST0, port),
		       sca_in(MSCI1_OFFSET + ST1, port),
		       sca_in(MSCI1_OFFSET + ST2, port),
		       sca_in(MSCI1_OFFSET + ST3, port));
		return 0;
	}
#endif
	if (cmd != SIOCWANDEV)
		return hdlc_ioctl(dev, ifr, cmd);

	switch(ifr->ifr_settings.type) {
	case IF_GET_IFACE:
		ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
		if (ifr->ifr_settings.size < size) {
			ifr->ifr_settings.size = size; /* data size wanted */
			return -ENOBUFS;
		}
		if (copy_to_user(line, &port->settings, size))
			return -EFAULT;
		return 0;

	case IF_IFACE_SYNC_SERIAL:
		if(!capable(CAP_NET_ADMIN))
			return -EPERM;

		if (copy_from_user(&new_line, line, size))
			return -EFAULT;

		if (new_line.clock_type != CLOCK_EXT &&
		    new_line.clock_type != CLOCK_TXFROMRX &&
		    new_line.clock_type != CLOCK_INT &&
		    new_line.clock_type != CLOCK_TXINT)
		return -EINVAL;	/* No such clock setting */

		if (new_line.loopback != 0 && new_line.loopback != 1)
			return -EINVAL;

		memcpy(&port->settings, &new_line, size); /* Update settings */
		c101_set_iface(port);
		return 0;

	default:
		return hdlc_ioctl(dev, ifr, cmd);
	}
}


static void c101_destroy_card(card_t *card)
{
	readb(card->win0base + C101_PAGE); /* Resets SCA? */

	if (card->irq)
		free_irq(card->irq, card);

	if (card->win0base) {
		iounmap(card->win0base);
		release_mem_region(card->phy_winbase, C101_MAPPED_RAM_SIZE);
	}

	free_netdev(card->dev);

	kfree(card);
}


static int __init c101_run(unsigned long irq, unsigned long winbase)
{
	struct net_device *dev;
	hdlc_device *hdlc;
	card_t *card;
	int result;

	if (irq<3 || irq>15 || irq == 6) /* FIXME */ {
		printk(KERN_ERR "c101: invalid IRQ value\n");
		return -ENODEV;
	}

	if (winbase < 0xC0000 || winbase > 0xDFFFF || (winbase & 0x3FFF) !=0) {
		printk(KERN_ERR "c101: invalid RAM value\n");
		return -ENODEV;
	}

	card = kzalloc(sizeof(card_t), GFP_KERNEL);
	if (card == NULL) {
		printk(KERN_ERR "c101: unable to allocate memory\n");
		return -ENOBUFS;
	}

	card->dev = alloc_hdlcdev(card);
	if (!card->dev) {
		printk(KERN_ERR "c101: unable to allocate memory\n");
		kfree(card);
		return -ENOBUFS;
	}

	if (request_irq(irq, sca_intr, 0, devname, card)) {
		printk(KERN_ERR "c101: could not allocate IRQ\n");
		c101_destroy_card(card);
		return -EBUSY;
	}
	card->irq = irq;

	if (!request_mem_region(winbase, C101_MAPPED_RAM_SIZE, devname)) {
		printk(KERN_ERR "c101: could not request RAM window\n");
		c101_destroy_card(card);
		return -EBUSY;
	}
	card->phy_winbase = winbase;
	card->win0base = ioremap(winbase, C101_MAPPED_RAM_SIZE);
	if (!card->win0base) {
		printk(KERN_ERR "c101: could not map I/O address\n");
		c101_destroy_card(card);
		return -EFAULT;
	}

	card->tx_ring_buffers = TX_RING_BUFFERS;
	card->rx_ring_buffers = RX_RING_BUFFERS;
	card->buff_offset = C101_WINDOW_SIZE; /* Bytes 1D00-1FFF reserved */

	readb(card->win0base + C101_PAGE); /* Resets SCA? */
	udelay(100);
	writeb(0, card->win0base + C101_PAGE);
	writeb(0, card->win0base + C101_DTR); /* Power-up for RAM? */

	sca_init(card, 0);

	dev = port_to_dev(card);
	hdlc = dev_to_hdlc(dev);

	spin_lock_init(&card->lock);
	dev->irq = irq;
	dev->mem_start = winbase;
	dev->mem_end = winbase + C101_MAPPED_RAM_SIZE - 1;
	dev->tx_queue_len = 50;
	dev->do_ioctl = c101_ioctl;
	dev->open = c101_open;
	dev->stop = c101_close;
	hdlc->attach = sca_attach;
	hdlc->xmit = sca_xmit;
	card->settings.clock_type = CLOCK_EXT;

	result = register_hdlc_device(dev);
	if (result) {
		printk(KERN_WARNING "c101: unable to register hdlc device\n");
		c101_destroy_card(card);
		return result;
	}

	sca_init_sync_port(card); /* Set up C101 memory */
	set_carrier(card);

	printk(KERN_INFO "%s: Moxa C101 on IRQ%u,"
	       " using %u TX + %u RX packets rings\n",
	       dev->name, card->irq,
	       card->tx_ring_buffers, card->rx_ring_buffers);

	*new_card = card;
	new_card = &card->next_card;
	return 0;
}


static int __init c101_init(void)
{
	if (hw == NULL) {
#ifdef MODULE
		printk(KERN_INFO "c101: no card initialized\n");
#endif
		return -EINVAL;	/* no parameters specified, abort */
	}

	printk(KERN_INFO "%s\n", version);

	do {
		unsigned long irq, ram;

		irq = simple_strtoul(hw, &hw, 0);

		if (*hw++ != ',')
			break;
		ram = simple_strtoul(hw, &hw, 0);

		if (*hw == ':' || *hw == '\x0')
			c101_run(irq, ram);

		if (*hw == '\x0')
			return first_card ? 0 : -EINVAL;
	}while(*hw++ == ':');

	printk(KERN_ERR "c101: invalid hardware parameters\n");
	return first_card ? 0 : -EINVAL;
}


static void __exit c101_cleanup(void)
{
	card_t *card = first_card;

	while (card) {
		card_t *ptr = card;
		card = card->next_card;
		unregister_hdlc_device(port_to_dev(ptr));
		c101_destroy_card(ptr);
	}
}


module_init(c101_init);
module_exit(c101_cleanup);

MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>");
MODULE_DESCRIPTION("Moxa C101 serial port driver");
MODULE_LICENSE("GPL v2");
module_param(hw, charp, 0444);
MODULE_PARM_DESC(hw, "irq,ram:irq,...");
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Moxa C101 synchronous serial card driver for Linux
	3	*
	4	* Copyright (C) 2000-2003 Krzysztof Halasa <khc@pm.waw.pl>
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of version 2 of the GNU General Public License
	8	* as published by the Free Software Foundation.
	9	*
467c432a	10	* For information see <http://www.kernel.org/pub/linux/utils/net/hdlc/>
1da177e4 LT	11	*
	12	* Sources of information:
	13	* Hitachi HD64570 SCA User's Manual
	14	* Moxa C101 User's Manual
	15	*/
	16
	17	#include <linux/module.h>
	18	#include <linux/kernel.h>
	19	#include <linux/slab.h>
	20	#include <linux/types.h>
	21	#include <linux/string.h>
	22	#include <linux/errno.h>
	23	#include <linux/init.h>
	24	#include <linux/moduleparam.h>
	25	#include <linux/netdevice.h>
	26	#include <linux/hdlc.h>
	27	#include <linux/delay.h>
	28	#include <asm/io.h>
	29
	30	#include "hd64570.h"
	31
	32
	33	static const char* version = "Moxa C101 driver version: 1.15";
	34	static const char* devname = "C101";
	35
	36	#undef DEBUG_PKT
	37	#define DEBUG_RINGS
	38
	39	#define C101_PAGE 0x1D00
	40	#define C101_DTR 0x1E00
	41	#define C101_SCA 0x1F00
	42	#define C101_WINDOW_SIZE 0x2000
	43	#define C101_MAPPED_RAM_SIZE 0x4000
	44
	45	#define RAM_SIZE (256 * 1024)
	46	#define TX_RING_BUFFERS 10
	47	#define RX_RING_BUFFERS ((RAM_SIZE - C101_WINDOW_SIZE) / \
	48	(sizeof(pkt_desc) + HDLC_MAX_MRU) - TX_RING_BUFFERS)
	49
	50	#define CLOCK_BASE 9830400 /* 9.8304 MHz */
	51	#define PAGE0_ALWAYS_MAPPED
	52
	53	static char hw; / pointer to hw=xxx command line string */
	54
	55
	56	typedef struct card_s {
	57	struct net_device *dev;
	58	spinlock_t lock; /* TX lock */
	59	u8 __iomem win0base; / ISA window base address */
	60	u32 phy_winbase; /* ISA physical base address */
	61	sync_serial_settings settings;
	62	int rxpart; /* partial frame received, next frame invalid*/
	63	unsigned short encoding;
	64	unsigned short parity;
	65	u16 rx_ring_buffers; /* number of buffers in a ring */
	66	u16 tx_ring_buffers;
	67	u16 buff_offset; /* offset of first buffer of first channel */
	68	u16 rxin; /* rx ring buffer 'in' pointer */
	69	u16 txin; /* tx ring buffer 'in' and 'last' pointers */
	70	u16 txlast;
	71	u8 rxs, txs, tmc; /* SCA registers */
	72	u8 irq; /* IRQ (3-15) */
	73	u8 page;
	74
75	struct card_s *next_card;
76	}card_t;
77
78	typedef card_t port_t;
79
80	static card_t *first_card;
81	static card_t **new_card = &first_card;
82
83
84	#define sca_in(reg, card) readb((card)->win0base + C101_SCA + (reg))
85	#define sca_out(value, reg, card) writeb(value, (card)->win0base + C101_SCA + (reg))
86	#define sca_inw(reg, card) readw((card)->win0base + C101_SCA + (reg))
87
88	/* EDA address register must be set in EDAL, EDAH order - 8 bit ISA bus */
89	#define sca_outw(value, reg, card) do { \
90	writeb(value & 0xFF, (card)->win0base + C101_SCA + (reg)); \
91	writeb((value >> 8 ) & 0xFF, (card)->win0base + C101_SCA + (reg+1));\
92	} while(0)
93
94	#define port_to_card(port) (port)
95	#define log_node(port) (0)
96	#define phy_node(port) (0)
97	#define winsize(card) (C101_WINDOW_SIZE)
98	#define win0base(card) ((card)->win0base)
99	#define winbase(card) ((card)->win0base + 0x2000)
100	#define get_port(card, port) (card)
101	static void sca_msci_intr(port_t *port);
102
103
104	static inline u8 sca_get_page(card_t *card)
105	{
106	return card->page;
107	}
108
109	static inline void openwin(card_t *card, u8 page)
110	{
111	card->page = page;
112	writeb(page, card->win0base + C101_PAGE);
113	}
114
115
116	#include "hd6457x.c"
117
118
c2ce9204 KH	119	static inline void set_carrier(port_t *port)
c2ce9204 KH	120	{
a76b044a	121	if (!(sca_in(MSCI1_OFFSET + ST3, port) & ST3_DCD))
c2ce9204 KH	122	netif_carrier_on(port_to_dev(port));
	123	else
	124	netif_carrier_off(port_to_dev(port));
	125	}
	126
	127
1da177e4 LT	128	static void sca_msci_intr(port_t *port)
1da177e4 LT	129	{
a76b044a	130	u8 stat = sca_in(MSCI0_OFFSET + ST1, port); /* read MSCI ST1 status */
1da177e4	131
a76b044a KH	132	/* Reset MSCI TX underrun and CDCD (ignored) status bit */
a76b044a KH	133	sca_out(stat & (ST1_UDRN \| ST1_CDCD), MSCI0_OFFSET + ST1, port);
1da177e4 LT	134
1da177e4 LT	135	if (stat & ST1_UDRN) {
198191c4 KH	136	/* TX Underrun error detected */
	137	port_to_dev(port)->stats.tx_errors++;
	138	port_to_dev(port)->stats.tx_fifo_errors++;
1da177e4 LT	139	}
1da177e4 LT	140
a76b044a	141	stat = sca_in(MSCI1_OFFSET + ST1, port); /* read MSCI1 ST1 status */
1da177e4	142	/* Reset MSCI CDCD status bit - uses ch#2 DCD input */
c2ce9204	143	sca_out(stat & ST1_CDCD, MSCI1_OFFSET + ST1, port);
1da177e4 LT	144
1da177e4 LT	145	if (stat & ST1_CDCD)
c2ce9204	146	set_carrier(port);
1da177e4 LT	147	}
	148
	149
	150	static void c101_set_iface(port_t *port)
	151	{
	152	u8 rxs = port->rxs & CLK_BRG_MASK;
	153	u8 txs = port->txs & CLK_BRG_MASK;
	154
	155	switch(port->settings.clock_type) {
	156	case CLOCK_INT:
	157	rxs \|= CLK_BRG_RX; /* TX clock */
	158	txs \|= CLK_RXCLK_TX; /* BRG output */
	159	break;
	160
	161	case CLOCK_TXINT:
	162	rxs \|= CLK_LINE_RX; /* RXC input */
	163	txs \|= CLK_BRG_TX; /* BRG output */
	164	break;
	165
	166	case CLOCK_TXFROMRX:
	167	rxs \|= CLK_LINE_RX; /* RXC input */
	168	txs \|= CLK_RXCLK_TX; /* RX clock */
	169	break;
	170
	171	default: /* EXTernal clock */
	172	rxs \|= CLK_LINE_RX; /* RXC input */
	173	txs \|= CLK_LINE_TX; /* TXC input */
	174	}
	175
	176	port->rxs = rxs;
	177	port->txs = txs;
	178	sca_out(rxs, MSCI1_OFFSET + RXS, port);
	179	sca_out(txs, MSCI1_OFFSET + TXS, port);
	180	sca_set_port(port);
	181	}
	182
	183
	184	static int c101_open(struct net_device *dev)
	185	{
	186	port_t *port = dev_to_port(dev);
	187	int result;
	188
	189	result = hdlc_open(dev);
	190	if (result)
	191	return result;
	192
	193	writeb(1, port->win0base + C101_DTR);
	194	sca_out(0, MSCI1_OFFSET + CTL, port); /* RTS uses ch#2 output */
	195	sca_open(dev);
	196	/* DCD is connected to port 2 !@#$%^& - disable MSCI0 CDCD interrupt */
	197	sca_out(IE1_UDRN, MSCI0_OFFSET + IE1, port);
	198	sca_out(IE0_TXINT, MSCI0_OFFSET + IE0, port);
	199
c2ce9204	200	set_carrier(port);
1da177e4 LT	201
	202	/* enable MSCI1 CDCD interrupt */
	203	sca_out(IE1_CDCD, MSCI1_OFFSET + IE1, port);
	204	sca_out(IE0_RXINTA, MSCI1_OFFSET + IE0, port);
	205	sca_out(0x48, IER0, port); /* TXINT #0 and RXINT #1 */
	206	c101_set_iface(port);
	207	return 0;
	208	}
	209
	210
	211	static int c101_close(struct net_device *dev)
	212	{
	213	port_t *port = dev_to_port(dev);
	214
	215	sca_close(dev);
	216	writeb(0, port->win0base + C101_DTR);
	217	sca_out(CTL_NORTS, MSCI1_OFFSET + CTL, port);
	218	hdlc_close(dev);
	219	return 0;
	220	}
	221
	222
	223	static int c101_ioctl(struct net_device dev, struct ifreq ifr, int cmd)
	224	{
	225	const size_t size = sizeof(sync_serial_settings);
	226	sync_serial_settings new_line;
	227	sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
	228	port_t *port = dev_to_port(dev);
	229
	230	#ifdef DEBUG_RINGS
	231	if (cmd == SIOCDEVPRIVATE) {
	232	sca_dump_rings(dev);
	233	printk(KERN_DEBUG "MSCI1: ST: %02x %02x %02x %02x\n",
	234	sca_in(MSCI1_OFFSET + ST0, port),
	235	sca_in(MSCI1_OFFSET + ST1, port),
	236	sca_in(MSCI1_OFFSET + ST2, port),
	237	sca_in(MSCI1_OFFSET + ST3, port));
	238	return 0;
	239	}
	240	#endif
	241	if (cmd != SIOCWANDEV)
	242	return hdlc_ioctl(dev, ifr, cmd);
	243
	244	switch(ifr->ifr_settings.type) {
	245	case IF_GET_IFACE:
	246	ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
	247	if (ifr->ifr_settings.size < size) {
	248	ifr->ifr_settings.size = size; /* data size wanted */
	249	return -ENOBUFS;
	250	}
	251	if (copy_to_user(line, &port->settings, size))
	252	return -EFAULT;
	253	return 0;
	254
	255	case IF_IFACE_SYNC_SERIAL:
	256	if(!capable(CAP_NET_ADMIN))
	257	return -EPERM;
	258
	259	if (copy_from_user(&new_line, line, size))
	260	return -EFAULT;
	261
	262	if (new_line.clock_type != CLOCK_EXT &&
	263	new_line.clock_type != CLOCK_TXFROMRX &&
	264	new_line.clock_type != CLOCK_INT &&
265	new_line.clock_type != CLOCK_TXINT)
266	return -EINVAL; /* No such clock setting */
267
268	if (new_line.loopback != 0 && new_line.loopback != 1)
269	return -EINVAL;
270
271	memcpy(&port->settings, &new_line, size); /* Update settings */
272	c101_set_iface(port);
273	return 0;
274
275	default:
276	return hdlc_ioctl(dev, ifr, cmd);
277	}
278	}
279
280
281
282	static void c101_destroy_card(card_t *card)
283	{
284	readb(card->win0base + C101_PAGE); /* Resets SCA? */
285
286	if (card->irq)
287	free_irq(card->irq, card);
288
289	if (card->win0base) {
290	iounmap(card->win0base);
291	release_mem_region(card->phy_winbase, C101_MAPPED_RAM_SIZE);
292	}
293
294	free_netdev(card->dev);
295
296	kfree(card);
297	}
298
299
300
301	static int __init c101_run(unsigned long irq, unsigned long winbase)
302	{
303	struct net_device *dev;
304	hdlc_device *hdlc;
305	card_t *card;
306	int result;
307
308	if (irq<3 \|\| irq>15 \|\| irq == 6) /* FIXME */ {
309	printk(KERN_ERR "c101: invalid IRQ value\n");
310	return -ENODEV;
311	}
312
313	if (winbase < 0xC0000 \|\| winbase > 0xDFFFF \|\| (winbase & 0x3FFF) !=0) {
314	printk(KERN_ERR "c101: invalid RAM value\n");
315	return -ENODEV;
316	}
317
dd00cc48	318	card = kzalloc(sizeof(card_t), GFP_KERNEL);
1da177e4 LT	319	if (card == NULL) {
	320	printk(KERN_ERR "c101: unable to allocate memory\n");
	321	return -ENOBUFS;
	322	}
1da177e4 LT	323
	324	card->dev = alloc_hdlcdev(card);
	325	if (!card->dev) {
	326	printk(KERN_ERR "c101: unable to allocate memory\n");
	327	kfree(card);
	328	return -ENOBUFS;
	329	}
	330
	331	if (request_irq(irq, sca_intr, 0, devname, card)) {
	332	printk(KERN_ERR "c101: could not allocate IRQ\n");
	333	c101_destroy_card(card);
4446065a	334	return -EBUSY;
1da177e4 LT	335	}
	336	card->irq = irq;
	337
	338	if (!request_mem_region(winbase, C101_MAPPED_RAM_SIZE, devname)) {
	339	printk(KERN_ERR "c101: could not request RAM window\n");
	340	c101_destroy_card(card);
4446065a	341	return -EBUSY;
1da177e4 LT	342	}
	343	card->phy_winbase = winbase;
	344	card->win0base = ioremap(winbase, C101_MAPPED_RAM_SIZE);
	345	if (!card->win0base) {
	346	printk(KERN_ERR "c101: could not map I/O address\n");
	347	c101_destroy_card(card);
4446065a	348	return -EFAULT;
1da177e4 LT	349	}
	350
	351	card->tx_ring_buffers = TX_RING_BUFFERS;
	352	card->rx_ring_buffers = RX_RING_BUFFERS;
	353	card->buff_offset = C101_WINDOW_SIZE; /* Bytes 1D00-1FFF reserved */
	354
	355	readb(card->win0base + C101_PAGE); /* Resets SCA? */
	356	udelay(100);
	357	writeb(0, card->win0base + C101_PAGE);
	358	writeb(0, card->win0base + C101_DTR); /* Power-up for RAM? */
	359
	360	sca_init(card, 0);
	361
	362	dev = port_to_dev(card);
	363	hdlc = dev_to_hdlc(dev);
	364
	365	spin_lock_init(&card->lock);
1da177e4 LT	366	dev->irq = irq;
	367	dev->mem_start = winbase;
	368	dev->mem_end = winbase + C101_MAPPED_RAM_SIZE - 1;
	369	dev->tx_queue_len = 50;
	370	dev->do_ioctl = c101_ioctl;
	371	dev->open = c101_open;
	372	dev->stop = c101_close;
	373	hdlc->attach = sca_attach;
	374	hdlc->xmit = sca_xmit;
	375	card->settings.clock_type = CLOCK_EXT;
	376
	377	result = register_hdlc_device(dev);
	378	if (result) {
	379	printk(KERN_WARNING "c101: unable to register hdlc device\n");
	380	c101_destroy_card(card);
	381	return result;
	382	}
	383
	384	sca_init_sync_port(card); /* Set up C101 memory */
c2ce9204	385	set_carrier(card);
1da177e4 LT	386
	387	printk(KERN_INFO "%s: Moxa C101 on IRQ%u,"
	388	" using %u TX + %u RX packets rings\n",
	389	dev->name, card->irq,
	390	card->tx_ring_buffers, card->rx_ring_buffers);
	391
	392	*new_card = card;
	393	new_card = &card->next_card;
	394	return 0;
	395	}
	396
	397
	398
	399	static int __init c101_init(void)
	400	{
	401	if (hw == NULL) {
	402	#ifdef MODULE
	403	printk(KERN_INFO "c101: no card initialized\n");
	404	#endif
d753d824	405	return -EINVAL; /* no parameters specified, abort */
1da177e4 LT	406	}
	407
	408	printk(KERN_INFO "%s\n", version);
	409
	410	do {
	411	unsigned long irq, ram;
	412
	413	irq = simple_strtoul(hw, &hw, 0);
	414
	415	if (*hw++ != ',')
	416	break;
	417	ram = simple_strtoul(hw, &hw, 0);
	418
	419	if (hw == ':' \|\| hw == '\x0')
	420	c101_run(irq, ram);
	421
	422	if (*hw == '\x0')
d753d824	423	return first_card ? 0 : -EINVAL;
1da177e4 LT	424	}while(*hw++ == ':');
	425
	426	printk(KERN_ERR "c101: invalid hardware parameters\n");
d753d824	427	return first_card ? 0 : -EINVAL;
1da177e4 LT	428	}
	429
	430
	431	static void __exit c101_cleanup(void)
	432	{
	433	card_t *card = first_card;
	434
	435	while (card) {
	436	card_t *ptr = card;
	437	card = card->next_card;
	438	unregister_hdlc_device(port_to_dev(ptr));
	439	c101_destroy_card(ptr);
	440	}
	441	}
	442
	443
	444	module_init(c101_init);
	445	module_exit(c101_cleanup);
	446
	447	MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>");
	448	MODULE_DESCRIPTION("Moxa C101 serial port driver");
	449	MODULE_LICENSE("GPL v2");
41b1d174 KH	450	module_param(hw, charp, 0444);
41b1d174 KH	451	MODULE_PARM_DESC(hw, "irq,ram:irq,...");