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1da177e4 LT |
1 | /* |
2 | * drivers/net/wan/dscc4/dscc4.c: a DSCC4 HDLC driver for Linux | |
3 | * | |
4 | * This software may be used and distributed according to the terms of the | |
5 | * GNU General Public License. | |
6 | * | |
7 | * The author may be reached as romieu@cogenit.fr. | |
8 | * Specific bug reports/asian food will be welcome. | |
9 | * | |
10 | * Special thanks to the nice people at CS-Telecom for the hardware and the | |
11 | * access to the test/measure tools. | |
12 | * | |
13 | * | |
14 | * Theory of Operation | |
15 | * | |
16 | * I. Board Compatibility | |
17 | * | |
18 | * This device driver is designed for the Siemens PEB20534 4 ports serial | |
19 | * controller as found on Etinc PCISYNC cards. The documentation for the | |
20 | * chipset is available at http://www.infineon.com: | |
21 | * - Data Sheet "DSCC4, DMA Supported Serial Communication Controller with | |
22 | * 4 Channels, PEB 20534 Version 2.1, PEF 20534 Version 2.1"; | |
23 | * - Application Hint "Management of DSCC4 on-chip FIFO resources". | |
24 | * - Errata sheet DS5 (courtesy of Michael Skerritt). | |
25 | * Jens David has built an adapter based on the same chipset. Take a look | |
26 | * at http://www.afthd.tu-darmstadt.de/~dg1kjd/pciscc4 for a specific | |
27 | * driver. | |
28 | * Sample code (2 revisions) is available at Infineon. | |
29 | * | |
30 | * II. Board-specific settings | |
31 | * | |
32 | * Pcisync can transmit some clock signal to the outside world on the | |
33 | * *first two* ports provided you put a quartz and a line driver on it and | |
34 | * remove the jumpers. The operation is described on Etinc web site. If you | |
35 | * go DCE on these ports, don't forget to use an adequate cable. | |
36 | * | |
37 | * Sharing of the PCI interrupt line for this board is possible. | |
38 | * | |
39 | * III. Driver operation | |
40 | * | |
41 | * The rx/tx operations are based on a linked list of descriptors. The driver | |
42 | * doesn't use HOLD mode any more. HOLD mode is definitely buggy and the more | |
43 | * I tried to fix it, the more it started to look like (convoluted) software | |
44 | * mutation of LxDA method. Errata sheet DS5 suggests to use LxDA: consider | |
45 | * this a rfc2119 MUST. | |
46 | * | |
47 | * Tx direction | |
48 | * When the tx ring is full, the xmit routine issues a call to netdev_stop. | |
49 | * The device is supposed to be enabled again during an ALLS irq (we could | |
50 | * use HI but as it's easy to lose events, it's fscked). | |
51 | * | |
52 | * Rx direction | |
53 | * The received frames aren't supposed to span over multiple receiving areas. | |
54 | * I may implement it some day but it isn't the highest ranked item. | |
55 | * | |
56 | * IV. Notes | |
57 | * The current error (XDU, RFO) recovery code is untested. | |
58 | * So far, RDO takes his RX channel down and the right sequence to enable it | |
59 | * again is still a mistery. If RDO happens, plan a reboot. More details | |
60 | * in the code (NB: as this happens, TX still works). | |
61 | * Don't mess the cables during operation, especially on DTE ports. I don't | |
62 | * suggest it for DCE either but at least one can get some messages instead | |
63 | * of a complete instant freeze. | |
64 | * Tests are done on Rev. 20 of the silicium. The RDO handling changes with | |
65 | * the documentation/chipset releases. | |
66 | * | |
67 | * TODO: | |
68 | * - test X25. | |
69 | * - use polling at high irq/s, | |
70 | * - performance analysis, | |
71 | * - endianness. | |
72 | * | |
73 | * 2001/12/10 Daniela Squassoni <daniela@cyclades.com> | |
74 | * - Contribution to support the new generic HDLC layer. | |
75 | * | |
76 | * 2002/01 Ueimor | |
77 | * - old style interface removal | |
78 | * - dscc4_release_ring fix (related to DMA mapping) | |
79 | * - hard_start_xmit fix (hint: TxSizeMax) | |
80 | * - misc crapectomy. | |
81 | */ | |
82 | ||
83 | #include <linux/module.h> | |
84 | #include <linux/types.h> | |
85 | #include <linux/errno.h> | |
86 | #include <linux/list.h> | |
87 | #include <linux/ioport.h> | |
88 | #include <linux/pci.h> | |
89 | #include <linux/kernel.h> | |
90 | #include <linux/mm.h> | |
91 | ||
92 | #include <asm/system.h> | |
93 | #include <asm/cache.h> | |
94 | #include <asm/byteorder.h> | |
95 | #include <asm/uaccess.h> | |
96 | #include <asm/io.h> | |
97 | #include <asm/irq.h> | |
98 | ||
99 | #include <linux/init.h> | |
100 | #include <linux/string.h> | |
101 | ||
102 | #include <linux/if_arp.h> | |
103 | #include <linux/netdevice.h> | |
104 | #include <linux/skbuff.h> | |
105 | #include <linux/delay.h> | |
106 | #include <net/syncppp.h> | |
107 | #include <linux/hdlc.h> | |
108 | ||
109 | /* Version */ | |
110 | static const char version[] = "$Id: dscc4.c,v 1.173 2003/09/20 23:55:34 romieu Exp $ for Linux\n"; | |
111 | static int debug; | |
112 | static int quartz; | |
113 | ||
114 | #ifdef CONFIG_DSCC4_PCI_RST | |
115 | static DECLARE_MUTEX(dscc4_sem); | |
116 | static u32 dscc4_pci_config_store[16]; | |
117 | #endif | |
118 | ||
119 | #define DRV_NAME "dscc4" | |
120 | ||
121 | #undef DSCC4_POLLING | |
122 | ||
123 | /* Module parameters */ | |
124 | ||
125 | MODULE_AUTHOR("Maintainer: Francois Romieu <romieu@cogenit.fr>"); | |
126 | MODULE_DESCRIPTION("Siemens PEB20534 PCI Controler"); | |
127 | MODULE_LICENSE("GPL"); | |
128 | module_param(debug, int, 0); | |
129 | MODULE_PARM_DESC(debug,"Enable/disable extra messages"); | |
130 | module_param(quartz, int, 0); | |
131 | MODULE_PARM_DESC(quartz,"If present, on-board quartz frequency (Hz)"); | |
132 | ||
133 | /* Structures */ | |
134 | ||
135 | struct thingie { | |
136 | int define; | |
137 | u32 bits; | |
138 | }; | |
139 | ||
140 | struct TxFD { | |
141 | u32 state; | |
142 | u32 next; | |
143 | u32 data; | |
144 | u32 complete; | |
145 | u32 jiffies; /* Allows sizeof(TxFD) == sizeof(RxFD) + extra hack */ | |
146 | }; | |
147 | ||
148 | struct RxFD { | |
149 | u32 state1; | |
150 | u32 next; | |
151 | u32 data; | |
152 | u32 state2; | |
153 | u32 end; | |
154 | }; | |
155 | ||
156 | #define DUMMY_SKB_SIZE 64 | |
157 | #define TX_LOW 8 | |
158 | #define TX_RING_SIZE 32 | |
159 | #define RX_RING_SIZE 32 | |
160 | #define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct TxFD) | |
161 | #define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct RxFD) | |
162 | #define IRQ_RING_SIZE 64 /* Keep it a multiple of 32 */ | |
163 | #define TX_TIMEOUT (HZ/10) | |
164 | #define DSCC4_HZ_MAX 33000000 | |
165 | #define BRR_DIVIDER_MAX 64*0x00004000 /* Cf errata DS5 p.10 */ | |
166 | #define dev_per_card 4 | |
167 | #define SCC_REGISTERS_MAX 23 /* Cf errata DS5 p.4 */ | |
168 | ||
169 | #define SOURCE_ID(flags) (((flags) >> 28) & 0x03) | |
170 | #define TO_SIZE(state) (((state) >> 16) & 0x1fff) | |
171 | ||
172 | /* | |
173 | * Given the operating range of Linux HDLC, the 2 defines below could be | |
174 | * made simpler. However they are a fine reminder for the limitations of | |
175 | * the driver: it's better to stay < TxSizeMax and < RxSizeMax. | |
176 | */ | |
177 | #define TO_STATE_TX(len) cpu_to_le32(((len) & TxSizeMax) << 16) | |
178 | #define TO_STATE_RX(len) cpu_to_le32((RX_MAX(len) % RxSizeMax) << 16) | |
179 | #define RX_MAX(len) ((((len) >> 5) + 1) << 5) /* Cf RLCR */ | |
180 | #define SCC_REG_START(dpriv) (SCC_START+(dpriv->dev_id)*SCC_OFFSET) | |
181 | ||
182 | struct dscc4_pci_priv { | |
183 | u32 *iqcfg; | |
184 | int cfg_cur; | |
185 | spinlock_t lock; | |
186 | struct pci_dev *pdev; | |
187 | ||
188 | struct dscc4_dev_priv *root; | |
189 | dma_addr_t iqcfg_dma; | |
190 | u32 xtal_hz; | |
191 | }; | |
192 | ||
193 | struct dscc4_dev_priv { | |
194 | struct sk_buff *rx_skbuff[RX_RING_SIZE]; | |
195 | struct sk_buff *tx_skbuff[TX_RING_SIZE]; | |
196 | ||
197 | struct RxFD *rx_fd; | |
198 | struct TxFD *tx_fd; | |
199 | u32 *iqrx; | |
200 | u32 *iqtx; | |
201 | ||
202 | /* FIXME: check all the volatile are required */ | |
203 | volatile u32 tx_current; | |
204 | u32 rx_current; | |
205 | u32 iqtx_current; | |
206 | u32 iqrx_current; | |
207 | ||
208 | volatile u32 tx_dirty; | |
209 | volatile u32 ltda; | |
210 | u32 rx_dirty; | |
211 | u32 lrda; | |
212 | ||
213 | dma_addr_t tx_fd_dma; | |
214 | dma_addr_t rx_fd_dma; | |
215 | dma_addr_t iqtx_dma; | |
216 | dma_addr_t iqrx_dma; | |
217 | ||
218 | u32 scc_regs[SCC_REGISTERS_MAX]; /* Cf errata DS5 p.4 */ | |
219 | ||
220 | struct timer_list timer; | |
221 | ||
222 | struct dscc4_pci_priv *pci_priv; | |
223 | spinlock_t lock; | |
224 | ||
225 | int dev_id; | |
226 | volatile u32 flags; | |
227 | u32 timer_help; | |
228 | ||
229 | unsigned short encoding; | |
230 | unsigned short parity; | |
231 | struct net_device *dev; | |
232 | sync_serial_settings settings; | |
233 | void __iomem *base_addr; | |
234 | u32 __pad __attribute__ ((aligned (4))); | |
235 | }; | |
236 | ||
237 | /* GLOBAL registers definitions */ | |
238 | #define GCMDR 0x00 | |
239 | #define GSTAR 0x04 | |
240 | #define GMODE 0x08 | |
241 | #define IQLENR0 0x0C | |
242 | #define IQLENR1 0x10 | |
243 | #define IQRX0 0x14 | |
244 | #define IQTX0 0x24 | |
245 | #define IQCFG 0x3c | |
246 | #define FIFOCR1 0x44 | |
247 | #define FIFOCR2 0x48 | |
248 | #define FIFOCR3 0x4c | |
249 | #define FIFOCR4 0x34 | |
250 | #define CH0CFG 0x50 | |
251 | #define CH0BRDA 0x54 | |
252 | #define CH0BTDA 0x58 | |
253 | #define CH0FRDA 0x98 | |
254 | #define CH0FTDA 0xb0 | |
255 | #define CH0LRDA 0xc8 | |
256 | #define CH0LTDA 0xe0 | |
257 | ||
258 | /* SCC registers definitions */ | |
259 | #define SCC_START 0x0100 | |
260 | #define SCC_OFFSET 0x80 | |
261 | #define CMDR 0x00 | |
262 | #define STAR 0x04 | |
263 | #define CCR0 0x08 | |
264 | #define CCR1 0x0c | |
265 | #define CCR2 0x10 | |
266 | #define BRR 0x2C | |
267 | #define RLCR 0x40 | |
268 | #define IMR 0x54 | |
269 | #define ISR 0x58 | |
270 | ||
271 | #define GPDIR 0x0400 | |
272 | #define GPDATA 0x0404 | |
273 | #define GPIM 0x0408 | |
274 | ||
275 | /* Bit masks */ | |
276 | #define EncodingMask 0x00700000 | |
277 | #define CrcMask 0x00000003 | |
278 | ||
279 | #define IntRxScc0 0x10000000 | |
280 | #define IntTxScc0 0x01000000 | |
281 | ||
282 | #define TxPollCmd 0x00000400 | |
283 | #define RxActivate 0x08000000 | |
284 | #define MTFi 0x04000000 | |
285 | #define Rdr 0x00400000 | |
286 | #define Rdt 0x00200000 | |
287 | #define Idr 0x00100000 | |
288 | #define Idt 0x00080000 | |
289 | #define TxSccRes 0x01000000 | |
290 | #define RxSccRes 0x00010000 | |
291 | #define TxSizeMax 0x1fff /* Datasheet DS1 - 11.1.1.1 */ | |
292 | #define RxSizeMax 0x1ffc /* Datasheet DS1 - 11.1.2.1 */ | |
293 | ||
294 | #define Ccr0ClockMask 0x0000003f | |
295 | #define Ccr1LoopMask 0x00000200 | |
296 | #define IsrMask 0x000fffff | |
297 | #define BrrExpMask 0x00000f00 | |
298 | #define BrrMultMask 0x0000003f | |
299 | #define EncodingMask 0x00700000 | |
300 | #define Hold 0x40000000 | |
301 | #define SccBusy 0x10000000 | |
302 | #define PowerUp 0x80000000 | |
303 | #define Vis 0x00001000 | |
304 | #define FrameOk (FrameVfr | FrameCrc) | |
305 | #define FrameVfr 0x80 | |
306 | #define FrameRdo 0x40 | |
307 | #define FrameCrc 0x20 | |
308 | #define FrameRab 0x10 | |
309 | #define FrameAborted 0x00000200 | |
310 | #define FrameEnd 0x80000000 | |
311 | #define DataComplete 0x40000000 | |
312 | #define LengthCheck 0x00008000 | |
313 | #define SccEvt 0x02000000 | |
314 | #define NoAck 0x00000200 | |
315 | #define Action 0x00000001 | |
316 | #define HiDesc 0x20000000 | |
317 | ||
318 | /* SCC events */ | |
319 | #define RxEvt 0xf0000000 | |
320 | #define TxEvt 0x0f000000 | |
321 | #define Alls 0x00040000 | |
322 | #define Xdu 0x00010000 | |
323 | #define Cts 0x00004000 | |
324 | #define Xmr 0x00002000 | |
325 | #define Xpr 0x00001000 | |
326 | #define Rdo 0x00000080 | |
327 | #define Rfs 0x00000040 | |
328 | #define Cd 0x00000004 | |
329 | #define Rfo 0x00000002 | |
330 | #define Flex 0x00000001 | |
331 | ||
332 | /* DMA core events */ | |
333 | #define Cfg 0x00200000 | |
334 | #define Hi 0x00040000 | |
335 | #define Fi 0x00020000 | |
336 | #define Err 0x00010000 | |
337 | #define Arf 0x00000002 | |
338 | #define ArAck 0x00000001 | |
339 | ||
340 | /* State flags */ | |
341 | #define Ready 0x00000000 | |
342 | #define NeedIDR 0x00000001 | |
343 | #define NeedIDT 0x00000002 | |
344 | #define RdoSet 0x00000004 | |
345 | #define FakeReset 0x00000008 | |
346 | ||
347 | /* Don't mask RDO. Ever. */ | |
348 | #ifdef DSCC4_POLLING | |
349 | #define EventsMask 0xfffeef7f | |
350 | #else | |
351 | #define EventsMask 0xfffa8f7a | |
352 | #endif | |
353 | ||
354 | /* Functions prototypes */ | |
355 | static void dscc4_rx_irq(struct dscc4_pci_priv *, struct dscc4_dev_priv *); | |
356 | static void dscc4_tx_irq(struct dscc4_pci_priv *, struct dscc4_dev_priv *); | |
357 | static int dscc4_found1(struct pci_dev *, void __iomem *ioaddr); | |
358 | static int dscc4_init_one(struct pci_dev *, const struct pci_device_id *ent); | |
359 | static int dscc4_open(struct net_device *); | |
360 | static int dscc4_start_xmit(struct sk_buff *, struct net_device *); | |
361 | static int dscc4_close(struct net_device *); | |
362 | static int dscc4_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); | |
363 | static int dscc4_init_ring(struct net_device *); | |
364 | static void dscc4_release_ring(struct dscc4_dev_priv *); | |
365 | static void dscc4_timer(unsigned long); | |
366 | static void dscc4_tx_timeout(struct net_device *); | |
367 | static irqreturn_t dscc4_irq(int irq, void *dev_id, struct pt_regs *ptregs); | |
368 | static int dscc4_hdlc_attach(struct net_device *, unsigned short, unsigned short); | |
369 | static int dscc4_set_iface(struct dscc4_dev_priv *, struct net_device *); | |
370 | #ifdef DSCC4_POLLING | |
371 | static int dscc4_tx_poll(struct dscc4_dev_priv *, struct net_device *); | |
372 | #endif | |
373 | ||
374 | static inline struct dscc4_dev_priv *dscc4_priv(struct net_device *dev) | |
375 | { | |
376 | return dev_to_hdlc(dev)->priv; | |
377 | } | |
378 | ||
379 | static inline struct net_device *dscc4_to_dev(struct dscc4_dev_priv *p) | |
380 | { | |
381 | return p->dev; | |
382 | } | |
383 | ||
384 | static void scc_patchl(u32 mask, u32 value, struct dscc4_dev_priv *dpriv, | |
385 | struct net_device *dev, int offset) | |
386 | { | |
387 | u32 state; | |
388 | ||
389 | /* Cf scc_writel for concern regarding thread-safety */ | |
390 | state = dpriv->scc_regs[offset >> 2]; | |
391 | state &= ~mask; | |
392 | state |= value; | |
393 | dpriv->scc_regs[offset >> 2] = state; | |
394 | writel(state, dpriv->base_addr + SCC_REG_START(dpriv) + offset); | |
395 | } | |
396 | ||
397 | static void scc_writel(u32 bits, struct dscc4_dev_priv *dpriv, | |
398 | struct net_device *dev, int offset) | |
399 | { | |
400 | /* | |
401 | * Thread-UNsafe. | |
402 | * As of 2002/02/16, there are no thread racing for access. | |
403 | */ | |
404 | dpriv->scc_regs[offset >> 2] = bits; | |
405 | writel(bits, dpriv->base_addr + SCC_REG_START(dpriv) + offset); | |
406 | } | |
407 | ||
408 | static inline u32 scc_readl(struct dscc4_dev_priv *dpriv, int offset) | |
409 | { | |
410 | return dpriv->scc_regs[offset >> 2]; | |
411 | } | |
412 | ||
413 | static u32 scc_readl_star(struct dscc4_dev_priv *dpriv, struct net_device *dev) | |
414 | { | |
415 | /* Cf errata DS5 p.4 */ | |
416 | readl(dpriv->base_addr + SCC_REG_START(dpriv) + STAR); | |
417 | return readl(dpriv->base_addr + SCC_REG_START(dpriv) + STAR); | |
418 | } | |
419 | ||
420 | static inline void dscc4_do_tx(struct dscc4_dev_priv *dpriv, | |
421 | struct net_device *dev) | |
422 | { | |
423 | dpriv->ltda = dpriv->tx_fd_dma + | |
424 | ((dpriv->tx_current-1)%TX_RING_SIZE)*sizeof(struct TxFD); | |
425 | writel(dpriv->ltda, dpriv->base_addr + CH0LTDA + dpriv->dev_id*4); | |
426 | /* Flush posted writes *NOW* */ | |
427 | readl(dpriv->base_addr + CH0LTDA + dpriv->dev_id*4); | |
428 | } | |
429 | ||
430 | static inline void dscc4_rx_update(struct dscc4_dev_priv *dpriv, | |
431 | struct net_device *dev) | |
432 | { | |
433 | dpriv->lrda = dpriv->rx_fd_dma + | |
434 | ((dpriv->rx_dirty - 1)%RX_RING_SIZE)*sizeof(struct RxFD); | |
435 | writel(dpriv->lrda, dpriv->base_addr + CH0LRDA + dpriv->dev_id*4); | |
436 | } | |
437 | ||
438 | static inline unsigned int dscc4_tx_done(struct dscc4_dev_priv *dpriv) | |
439 | { | |
440 | return dpriv->tx_current == dpriv->tx_dirty; | |
441 | } | |
442 | ||
443 | static inline unsigned int dscc4_tx_quiescent(struct dscc4_dev_priv *dpriv, | |
444 | struct net_device *dev) | |
445 | { | |
446 | return readl(dpriv->base_addr + CH0FTDA + dpriv->dev_id*4) == dpriv->ltda; | |
447 | } | |
448 | ||
449 | int state_check(u32 state, struct dscc4_dev_priv *dpriv, struct net_device *dev, | |
450 | const char *msg) | |
451 | { | |
452 | int ret = 0; | |
453 | ||
454 | if (debug > 1) { | |
455 | if (SOURCE_ID(state) != dpriv->dev_id) { | |
456 | printk(KERN_DEBUG "%s (%s): Source Id=%d, state=%08x\n", | |
457 | dev->name, msg, SOURCE_ID(state), state ); | |
458 | ret = -1; | |
459 | } | |
460 | if (state & 0x0df80c00) { | |
461 | printk(KERN_DEBUG "%s (%s): state=%08x (UFO alert)\n", | |
462 | dev->name, msg, state); | |
463 | ret = -1; | |
464 | } | |
465 | } | |
466 | return ret; | |
467 | } | |
468 | ||
469 | void dscc4_tx_print(struct net_device *dev, struct dscc4_dev_priv *dpriv, | |
470 | char *msg) | |
471 | { | |
472 | printk(KERN_DEBUG "%s: tx_current=%02d tx_dirty=%02d (%s)\n", | |
473 | dev->name, dpriv->tx_current, dpriv->tx_dirty, msg); | |
474 | } | |
475 | ||
476 | static void dscc4_release_ring(struct dscc4_dev_priv *dpriv) | |
477 | { | |
478 | struct pci_dev *pdev = dpriv->pci_priv->pdev; | |
479 | struct TxFD *tx_fd = dpriv->tx_fd; | |
480 | struct RxFD *rx_fd = dpriv->rx_fd; | |
481 | struct sk_buff **skbuff; | |
482 | int i; | |
483 | ||
484 | pci_free_consistent(pdev, TX_TOTAL_SIZE, tx_fd, dpriv->tx_fd_dma); | |
485 | pci_free_consistent(pdev, RX_TOTAL_SIZE, rx_fd, dpriv->rx_fd_dma); | |
486 | ||
487 | skbuff = dpriv->tx_skbuff; | |
488 | for (i = 0; i < TX_RING_SIZE; i++) { | |
489 | if (*skbuff) { | |
490 | pci_unmap_single(pdev, tx_fd->data, (*skbuff)->len, | |
491 | PCI_DMA_TODEVICE); | |
492 | dev_kfree_skb(*skbuff); | |
493 | } | |
494 | skbuff++; | |
495 | tx_fd++; | |
496 | } | |
497 | ||
498 | skbuff = dpriv->rx_skbuff; | |
499 | for (i = 0; i < RX_RING_SIZE; i++) { | |
500 | if (*skbuff) { | |
501 | pci_unmap_single(pdev, rx_fd->data, | |
502 | RX_MAX(HDLC_MAX_MRU), PCI_DMA_FROMDEVICE); | |
503 | dev_kfree_skb(*skbuff); | |
504 | } | |
505 | skbuff++; | |
506 | rx_fd++; | |
507 | } | |
508 | } | |
509 | ||
510 | inline int try_get_rx_skb(struct dscc4_dev_priv *dpriv, struct net_device *dev) | |
511 | { | |
512 | unsigned int dirty = dpriv->rx_dirty%RX_RING_SIZE; | |
513 | struct RxFD *rx_fd = dpriv->rx_fd + dirty; | |
514 | const int len = RX_MAX(HDLC_MAX_MRU); | |
515 | struct sk_buff *skb; | |
516 | int ret = 0; | |
517 | ||
518 | skb = dev_alloc_skb(len); | |
519 | dpriv->rx_skbuff[dirty] = skb; | |
520 | if (skb) { | |
521 | skb->protocol = hdlc_type_trans(skb, dev); | |
522 | rx_fd->data = pci_map_single(dpriv->pci_priv->pdev, skb->data, | |
523 | len, PCI_DMA_FROMDEVICE); | |
524 | } else { | |
525 | rx_fd->data = (u32) NULL; | |
526 | ret = -1; | |
527 | } | |
528 | return ret; | |
529 | } | |
530 | ||
531 | /* | |
532 | * IRQ/thread/whatever safe | |
533 | */ | |
534 | static int dscc4_wait_ack_cec(struct dscc4_dev_priv *dpriv, | |
535 | struct net_device *dev, char *msg) | |
536 | { | |
537 | s8 i = 0; | |
538 | ||
539 | do { | |
540 | if (!(scc_readl_star(dpriv, dev) & SccBusy)) { | |
541 | printk(KERN_DEBUG "%s: %s ack (%d try)\n", dev->name, | |
542 | msg, i); | |
543 | goto done; | |
544 | } | |
3173c890 | 545 | schedule_timeout_uninterruptible(10); |
1da177e4 LT |
546 | rmb(); |
547 | } while (++i > 0); | |
548 | printk(KERN_ERR "%s: %s timeout\n", dev->name, msg); | |
549 | done: | |
550 | return (i >= 0) ? i : -EAGAIN; | |
551 | } | |
552 | ||
553 | static int dscc4_do_action(struct net_device *dev, char *msg) | |
554 | { | |
555 | void __iomem *ioaddr = dscc4_priv(dev)->base_addr; | |
556 | s16 i = 0; | |
557 | ||
558 | writel(Action, ioaddr + GCMDR); | |
559 | ioaddr += GSTAR; | |
560 | do { | |
561 | u32 state = readl(ioaddr); | |
562 | ||
563 | if (state & ArAck) { | |
564 | printk(KERN_DEBUG "%s: %s ack\n", dev->name, msg); | |
565 | writel(ArAck, ioaddr); | |
566 | goto done; | |
567 | } else if (state & Arf) { | |
568 | printk(KERN_ERR "%s: %s failed\n", dev->name, msg); | |
569 | writel(Arf, ioaddr); | |
570 | i = -1; | |
571 | goto done; | |
572 | } | |
573 | rmb(); | |
574 | } while (++i > 0); | |
575 | printk(KERN_ERR "%s: %s timeout\n", dev->name, msg); | |
576 | done: | |
577 | return i; | |
578 | } | |
579 | ||
580 | static inline int dscc4_xpr_ack(struct dscc4_dev_priv *dpriv) | |
581 | { | |
582 | int cur = dpriv->iqtx_current%IRQ_RING_SIZE; | |
583 | s8 i = 0; | |
584 | ||
585 | do { | |
586 | if (!(dpriv->flags & (NeedIDR | NeedIDT)) || | |
587 | (dpriv->iqtx[cur] & Xpr)) | |
588 | break; | |
589 | smp_rmb(); | |
3173c890 | 590 | schedule_timeout_uninterruptible(10); |
1da177e4 LT |
591 | } while (++i > 0); |
592 | ||
593 | return (i >= 0 ) ? i : -EAGAIN; | |
594 | } | |
595 | ||
596 | #if 0 /* dscc4_{rx/tx}_reset are both unreliable - more tweak needed */ | |
597 | static void dscc4_rx_reset(struct dscc4_dev_priv *dpriv, struct net_device *dev) | |
598 | { | |
599 | unsigned long flags; | |
600 | ||
601 | spin_lock_irqsave(&dpriv->pci_priv->lock, flags); | |
602 | /* Cf errata DS5 p.6 */ | |
603 | writel(0x00000000, dpriv->base_addr + CH0LRDA + dpriv->dev_id*4); | |
604 | scc_patchl(PowerUp, 0, dpriv, dev, CCR0); | |
605 | readl(dpriv->base_addr + CH0LRDA + dpriv->dev_id*4); | |
606 | writel(MTFi|Rdr, dpriv->base_addr + dpriv->dev_id*0x0c + CH0CFG); | |
607 | writel(Action, dpriv->base_addr + GCMDR); | |
608 | spin_unlock_irqrestore(&dpriv->pci_priv->lock, flags); | |
609 | } | |
610 | ||
611 | #endif | |
612 | ||
613 | #if 0 | |
614 | static void dscc4_tx_reset(struct dscc4_dev_priv *dpriv, struct net_device *dev) | |
615 | { | |
616 | u16 i = 0; | |
617 | ||
618 | /* Cf errata DS5 p.7 */ | |
619 | scc_patchl(PowerUp, 0, dpriv, dev, CCR0); | |
620 | scc_writel(0x00050000, dpriv, dev, CCR2); | |
621 | /* | |
622 | * Must be longer than the time required to fill the fifo. | |
623 | */ | |
624 | while (!dscc4_tx_quiescent(dpriv, dev) && ++i) { | |
625 | udelay(1); | |
626 | wmb(); | |
627 | } | |
628 | ||
629 | writel(MTFi|Rdt, dpriv->base_addr + dpriv->dev_id*0x0c + CH0CFG); | |
630 | if (dscc4_do_action(dev, "Rdt") < 0) | |
631 | printk(KERN_ERR "%s: Tx reset failed\n", dev->name); | |
632 | } | |
633 | #endif | |
634 | ||
635 | /* TODO: (ab)use this function to refill a completely depleted RX ring. */ | |
636 | static inline void dscc4_rx_skb(struct dscc4_dev_priv *dpriv, | |
637 | struct net_device *dev) | |
638 | { | |
639 | struct RxFD *rx_fd = dpriv->rx_fd + dpriv->rx_current%RX_RING_SIZE; | |
640 | struct net_device_stats *stats = hdlc_stats(dev); | |
641 | struct pci_dev *pdev = dpriv->pci_priv->pdev; | |
642 | struct sk_buff *skb; | |
643 | int pkt_len; | |
644 | ||
645 | skb = dpriv->rx_skbuff[dpriv->rx_current++%RX_RING_SIZE]; | |
646 | if (!skb) { | |
647 | printk(KERN_DEBUG "%s: skb=0 (%s)\n", dev->name, __FUNCTION__); | |
648 | goto refill; | |
649 | } | |
650 | pkt_len = TO_SIZE(rx_fd->state2); | |
651 | pci_unmap_single(pdev, rx_fd->data, RX_MAX(HDLC_MAX_MRU), PCI_DMA_FROMDEVICE); | |
652 | if ((skb->data[--pkt_len] & FrameOk) == FrameOk) { | |
653 | stats->rx_packets++; | |
654 | stats->rx_bytes += pkt_len; | |
655 | skb_put(skb, pkt_len); | |
656 | if (netif_running(dev)) | |
657 | skb->protocol = hdlc_type_trans(skb, dev); | |
658 | skb->dev->last_rx = jiffies; | |
659 | netif_rx(skb); | |
660 | } else { | |
661 | if (skb->data[pkt_len] & FrameRdo) | |
662 | stats->rx_fifo_errors++; | |
663 | else if (!(skb->data[pkt_len] | ~FrameCrc)) | |
664 | stats->rx_crc_errors++; | |
665 | else if (!(skb->data[pkt_len] | ~(FrameVfr | FrameRab))) | |
666 | stats->rx_length_errors++; | |
667 | else | |
668 | stats->rx_errors++; | |
669 | dev_kfree_skb_irq(skb); | |
670 | } | |
671 | refill: | |
672 | while ((dpriv->rx_dirty - dpriv->rx_current) % RX_RING_SIZE) { | |
673 | if (try_get_rx_skb(dpriv, dev) < 0) | |
674 | break; | |
675 | dpriv->rx_dirty++; | |
676 | } | |
677 | dscc4_rx_update(dpriv, dev); | |
678 | rx_fd->state2 = 0x00000000; | |
679 | rx_fd->end = 0xbabeface; | |
680 | } | |
681 | ||
682 | static void dscc4_free1(struct pci_dev *pdev) | |
683 | { | |
684 | struct dscc4_pci_priv *ppriv; | |
685 | struct dscc4_dev_priv *root; | |
686 | int i; | |
687 | ||
688 | ppriv = pci_get_drvdata(pdev); | |
689 | root = ppriv->root; | |
690 | ||
691 | for (i = 0; i < dev_per_card; i++) | |
692 | unregister_hdlc_device(dscc4_to_dev(root + i)); | |
693 | ||
694 | pci_set_drvdata(pdev, NULL); | |
695 | ||
696 | for (i = 0; i < dev_per_card; i++) | |
697 | free_netdev(root[i].dev); | |
698 | kfree(root); | |
699 | kfree(ppriv); | |
700 | } | |
701 | ||
702 | static int __devinit dscc4_init_one(struct pci_dev *pdev, | |
703 | const struct pci_device_id *ent) | |
704 | { | |
705 | struct dscc4_pci_priv *priv; | |
706 | struct dscc4_dev_priv *dpriv; | |
707 | void __iomem *ioaddr; | |
708 | int i, rc; | |
709 | ||
710 | printk(KERN_DEBUG "%s", version); | |
711 | ||
712 | rc = pci_enable_device(pdev); | |
713 | if (rc < 0) | |
714 | goto out; | |
715 | ||
716 | rc = pci_request_region(pdev, 0, "registers"); | |
717 | if (rc < 0) { | |
718 | printk(KERN_ERR "%s: can't reserve MMIO region (regs)\n", | |
719 | DRV_NAME); | |
720 | goto err_disable_0; | |
721 | } | |
722 | rc = pci_request_region(pdev, 1, "LBI interface"); | |
723 | if (rc < 0) { | |
724 | printk(KERN_ERR "%s: can't reserve MMIO region (lbi)\n", | |
725 | DRV_NAME); | |
726 | goto err_free_mmio_region_1; | |
727 | } | |
728 | ||
729 | ioaddr = ioremap(pci_resource_start(pdev, 0), | |
730 | pci_resource_len(pdev, 0)); | |
731 | if (!ioaddr) { | |
732 | printk(KERN_ERR "%s: cannot remap MMIO region %lx @ %lx\n", | |
733 | DRV_NAME, pci_resource_len(pdev, 0), | |
734 | pci_resource_start(pdev, 0)); | |
735 | rc = -EIO; | |
736 | goto err_free_mmio_regions_2; | |
737 | } | |
738 | printk(KERN_DEBUG "Siemens DSCC4, MMIO at %#lx (regs), %#lx (lbi), IRQ %d\n", | |
739 | pci_resource_start(pdev, 0), | |
740 | pci_resource_start(pdev, 1), pdev->irq); | |
741 | ||
742 | /* Cf errata DS5 p.2 */ | |
743 | pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xf8); | |
744 | pci_set_master(pdev); | |
745 | ||
746 | rc = dscc4_found1(pdev, ioaddr); | |
747 | if (rc < 0) | |
748 | goto err_iounmap_3; | |
749 | ||
750 | priv = pci_get_drvdata(pdev); | |
751 | ||
752 | rc = request_irq(pdev->irq, dscc4_irq, SA_SHIRQ, DRV_NAME, priv->root); | |
753 | if (rc < 0) { | |
754 | printk(KERN_WARNING "%s: IRQ %d busy\n", DRV_NAME, pdev->irq); | |
755 | goto err_release_4; | |
756 | } | |
757 | ||
758 | /* power up/little endian/dma core controlled via lrda/ltda */ | |
759 | writel(0x00000001, ioaddr + GMODE); | |
760 | /* Shared interrupt queue */ | |
761 | { | |
762 | u32 bits; | |
763 | ||
764 | bits = (IRQ_RING_SIZE >> 5) - 1; | |
765 | bits |= bits << 4; | |
766 | bits |= bits << 8; | |
767 | bits |= bits << 16; | |
768 | writel(bits, ioaddr + IQLENR0); | |
769 | } | |
770 | /* Global interrupt queue */ | |
771 | writel((u32)(((IRQ_RING_SIZE >> 5) - 1) << 20), ioaddr + IQLENR1); | |
772 | priv->iqcfg = (u32 *) pci_alloc_consistent(pdev, | |
773 | IRQ_RING_SIZE*sizeof(u32), &priv->iqcfg_dma); | |
774 | if (!priv->iqcfg) | |
775 | goto err_free_irq_5; | |
776 | writel(priv->iqcfg_dma, ioaddr + IQCFG); | |
777 | ||
778 | rc = -ENOMEM; | |
779 | ||
780 | /* | |
781 | * SCC 0-3 private rx/tx irq structures | |
782 | * IQRX/TXi needs to be set soon. Learned it the hard way... | |
783 | */ | |
784 | for (i = 0; i < dev_per_card; i++) { | |
785 | dpriv = priv->root + i; | |
786 | dpriv->iqtx = (u32 *) pci_alloc_consistent(pdev, | |
787 | IRQ_RING_SIZE*sizeof(u32), &dpriv->iqtx_dma); | |
788 | if (!dpriv->iqtx) | |
789 | goto err_free_iqtx_6; | |
790 | writel(dpriv->iqtx_dma, ioaddr + IQTX0 + i*4); | |
791 | } | |
792 | for (i = 0; i < dev_per_card; i++) { | |
793 | dpriv = priv->root + i; | |
794 | dpriv->iqrx = (u32 *) pci_alloc_consistent(pdev, | |
795 | IRQ_RING_SIZE*sizeof(u32), &dpriv->iqrx_dma); | |
796 | if (!dpriv->iqrx) | |
797 | goto err_free_iqrx_7; | |
798 | writel(dpriv->iqrx_dma, ioaddr + IQRX0 + i*4); | |
799 | } | |
800 | ||
801 | /* Cf application hint. Beware of hard-lock condition on threshold. */ | |
802 | writel(0x42104000, ioaddr + FIFOCR1); | |
803 | //writel(0x9ce69800, ioaddr + FIFOCR2); | |
804 | writel(0xdef6d800, ioaddr + FIFOCR2); | |
805 | //writel(0x11111111, ioaddr + FIFOCR4); | |
806 | writel(0x18181818, ioaddr + FIFOCR4); | |
807 | // FIXME: should depend on the chipset revision | |
808 | writel(0x0000000e, ioaddr + FIFOCR3); | |
809 | ||
810 | writel(0xff200001, ioaddr + GCMDR); | |
811 | ||
812 | rc = 0; | |
813 | out: | |
814 | return rc; | |
815 | ||
816 | err_free_iqrx_7: | |
817 | while (--i >= 0) { | |
818 | dpriv = priv->root + i; | |
819 | pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32), | |
820 | dpriv->iqrx, dpriv->iqrx_dma); | |
821 | } | |
822 | i = dev_per_card; | |
823 | err_free_iqtx_6: | |
824 | while (--i >= 0) { | |
825 | dpriv = priv->root + i; | |
826 | pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32), | |
827 | dpriv->iqtx, dpriv->iqtx_dma); | |
828 | } | |
829 | pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32), priv->iqcfg, | |
830 | priv->iqcfg_dma); | |
831 | err_free_irq_5: | |
832 | free_irq(pdev->irq, priv->root); | |
833 | err_release_4: | |
834 | dscc4_free1(pdev); | |
835 | err_iounmap_3: | |
836 | iounmap (ioaddr); | |
837 | err_free_mmio_regions_2: | |
838 | pci_release_region(pdev, 1); | |
839 | err_free_mmio_region_1: | |
840 | pci_release_region(pdev, 0); | |
841 | err_disable_0: | |
842 | pci_disable_device(pdev); | |
843 | goto out; | |
844 | }; | |
845 | ||
846 | /* | |
847 | * Let's hope the default values are decent enough to protect my | |
848 | * feet from the user's gun - Ueimor | |
849 | */ | |
850 | static void dscc4_init_registers(struct dscc4_dev_priv *dpriv, | |
851 | struct net_device *dev) | |
852 | { | |
853 | /* No interrupts, SCC core disabled. Let's relax */ | |
854 | scc_writel(0x00000000, dpriv, dev, CCR0); | |
855 | ||
856 | scc_writel(LengthCheck | (HDLC_MAX_MRU >> 5), dpriv, dev, RLCR); | |
857 | ||
858 | /* | |
859 | * No address recognition/crc-CCITT/cts enabled | |
860 | * Shared flags transmission disabled - cf errata DS5 p.11 | |
861 | * Carrier detect disabled - cf errata p.14 | |
862 | * FIXME: carrier detection/polarity may be handled more gracefully. | |
863 | */ | |
864 | scc_writel(0x02408000, dpriv, dev, CCR1); | |
865 | ||
866 | /* crc not forwarded - Cf errata DS5 p.11 */ | |
867 | scc_writel(0x00050008 & ~RxActivate, dpriv, dev, CCR2); | |
868 | // crc forwarded | |
869 | //scc_writel(0x00250008 & ~RxActivate, dpriv, dev, CCR2); | |
870 | } | |
871 | ||
872 | static inline int dscc4_set_quartz(struct dscc4_dev_priv *dpriv, int hz) | |
873 | { | |
874 | int ret = 0; | |
875 | ||
876 | if ((hz < 0) || (hz > DSCC4_HZ_MAX)) | |
877 | ret = -EOPNOTSUPP; | |
878 | else | |
879 | dpriv->pci_priv->xtal_hz = hz; | |
880 | ||
881 | return ret; | |
882 | } | |
883 | ||
884 | static int dscc4_found1(struct pci_dev *pdev, void __iomem *ioaddr) | |
885 | { | |
886 | struct dscc4_pci_priv *ppriv; | |
887 | struct dscc4_dev_priv *root; | |
888 | int i, ret = -ENOMEM; | |
889 | ||
890 | root = kmalloc(dev_per_card*sizeof(*root), GFP_KERNEL); | |
891 | if (!root) { | |
892 | printk(KERN_ERR "%s: can't allocate data\n", DRV_NAME); | |
893 | goto err_out; | |
894 | } | |
895 | memset(root, 0, dev_per_card*sizeof(*root)); | |
896 | ||
897 | for (i = 0; i < dev_per_card; i++) { | |
898 | root[i].dev = alloc_hdlcdev(root + i); | |
899 | if (!root[i].dev) | |
900 | goto err_free_dev; | |
901 | } | |
902 | ||
903 | ppriv = kmalloc(sizeof(*ppriv), GFP_KERNEL); | |
904 | if (!ppriv) { | |
905 | printk(KERN_ERR "%s: can't allocate private data\n", DRV_NAME); | |
906 | goto err_free_dev; | |
907 | } | |
908 | memset(ppriv, 0, sizeof(struct dscc4_pci_priv)); | |
909 | ||
910 | ppriv->root = root; | |
911 | spin_lock_init(&ppriv->lock); | |
912 | ||
913 | for (i = 0; i < dev_per_card; i++) { | |
914 | struct dscc4_dev_priv *dpriv = root + i; | |
915 | struct net_device *d = dscc4_to_dev(dpriv); | |
916 | hdlc_device *hdlc = dev_to_hdlc(d); | |
917 | ||
918 | d->base_addr = (unsigned long)ioaddr; | |
919 | d->init = NULL; | |
920 | d->irq = pdev->irq; | |
921 | d->open = dscc4_open; | |
922 | d->stop = dscc4_close; | |
923 | d->set_multicast_list = NULL; | |
924 | d->do_ioctl = dscc4_ioctl; | |
925 | d->tx_timeout = dscc4_tx_timeout; | |
926 | d->watchdog_timeo = TX_TIMEOUT; | |
927 | SET_MODULE_OWNER(d); | |
928 | SET_NETDEV_DEV(d, &pdev->dev); | |
929 | ||
930 | dpriv->dev_id = i; | |
931 | dpriv->pci_priv = ppriv; | |
932 | dpriv->base_addr = ioaddr; | |
933 | spin_lock_init(&dpriv->lock); | |
934 | ||
935 | hdlc->xmit = dscc4_start_xmit; | |
936 | hdlc->attach = dscc4_hdlc_attach; | |
937 | ||
938 | dscc4_init_registers(dpriv, d); | |
939 | dpriv->parity = PARITY_CRC16_PR0_CCITT; | |
940 | dpriv->encoding = ENCODING_NRZ; | |
941 | ||
942 | ret = dscc4_init_ring(d); | |
943 | if (ret < 0) | |
944 | goto err_unregister; | |
945 | ||
946 | ret = register_hdlc_device(d); | |
947 | if (ret < 0) { | |
948 | printk(KERN_ERR "%s: unable to register\n", DRV_NAME); | |
949 | dscc4_release_ring(dpriv); | |
950 | goto err_unregister; | |
951 | } | |
952 | } | |
953 | ||
954 | ret = dscc4_set_quartz(root, quartz); | |
955 | if (ret < 0) | |
956 | goto err_unregister; | |
957 | ||
958 | pci_set_drvdata(pdev, ppriv); | |
959 | return ret; | |
960 | ||
961 | err_unregister: | |
962 | while (i-- > 0) { | |
963 | dscc4_release_ring(root + i); | |
964 | unregister_hdlc_device(dscc4_to_dev(root + i)); | |
965 | } | |
966 | kfree(ppriv); | |
967 | i = dev_per_card; | |
968 | err_free_dev: | |
969 | while (i-- > 0) | |
970 | free_netdev(root[i].dev); | |
971 | kfree(root); | |
972 | err_out: | |
973 | return ret; | |
974 | }; | |
975 | ||
976 | /* FIXME: get rid of the unneeded code */ | |
977 | static void dscc4_timer(unsigned long data) | |
978 | { | |
979 | struct net_device *dev = (struct net_device *)data; | |
980 | struct dscc4_dev_priv *dpriv = dscc4_priv(dev); | |
981 | // struct dscc4_pci_priv *ppriv; | |
982 | ||
983 | goto done; | |
984 | done: | |
985 | dpriv->timer.expires = jiffies + TX_TIMEOUT; | |
986 | add_timer(&dpriv->timer); | |
987 | } | |
988 | ||
989 | static void dscc4_tx_timeout(struct net_device *dev) | |
990 | { | |
991 | /* FIXME: something is missing there */ | |
992 | } | |
993 | ||
994 | static int dscc4_loopback_check(struct dscc4_dev_priv *dpriv) | |
995 | { | |
996 | sync_serial_settings *settings = &dpriv->settings; | |
997 | ||
998 | if (settings->loopback && (settings->clock_type != CLOCK_INT)) { | |
999 | struct net_device *dev = dscc4_to_dev(dpriv); | |
1000 | ||
1001 | printk(KERN_INFO "%s: loopback requires clock\n", dev->name); | |
1002 | return -1; | |
1003 | } | |
1004 | return 0; | |
1005 | } | |
1006 | ||
1007 | #ifdef CONFIG_DSCC4_PCI_RST | |
1008 | /* | |
1009 | * Some DSCC4-based cards wires the GPIO port and the PCI #RST pin together | |
1010 | * so as to provide a safe way to reset the asic while not the whole machine | |
1011 | * rebooting. | |
1012 | * | |
1013 | * This code doesn't need to be efficient. Keep It Simple | |
1014 | */ | |
1015 | static void dscc4_pci_reset(struct pci_dev *pdev, void __iomem *ioaddr) | |
1016 | { | |
1017 | int i; | |
1018 | ||
1019 | down(&dscc4_sem); | |
1020 | for (i = 0; i < 16; i++) | |
1021 | pci_read_config_dword(pdev, i << 2, dscc4_pci_config_store + i); | |
1022 | ||
1023 | /* Maximal LBI clock divider (who cares ?) and whole GPIO range. */ | |
1024 | writel(0x001c0000, ioaddr + GMODE); | |
1025 | /* Configure GPIO port as output */ | |
1026 | writel(0x0000ffff, ioaddr + GPDIR); | |
1027 | /* Disable interruption */ | |
1028 | writel(0x0000ffff, ioaddr + GPIM); | |
1029 | ||
1030 | writel(0x0000ffff, ioaddr + GPDATA); | |
1031 | writel(0x00000000, ioaddr + GPDATA); | |
1032 | ||
1033 | /* Flush posted writes */ | |
1034 | readl(ioaddr + GSTAR); | |
1035 | ||
3173c890 | 1036 | schedule_timeout_uninterruptible(10); |
1da177e4 LT |
1037 | |
1038 | for (i = 0; i < 16; i++) | |
1039 | pci_write_config_dword(pdev, i << 2, dscc4_pci_config_store[i]); | |
1040 | up(&dscc4_sem); | |
1041 | } | |
1042 | #else | |
1043 | #define dscc4_pci_reset(pdev,ioaddr) do {} while (0) | |
1044 | #endif /* CONFIG_DSCC4_PCI_RST */ | |
1045 | ||
1046 | static int dscc4_open(struct net_device *dev) | |
1047 | { | |
1048 | struct dscc4_dev_priv *dpriv = dscc4_priv(dev); | |
1049 | struct dscc4_pci_priv *ppriv; | |
1050 | int ret = -EAGAIN; | |
1051 | ||
1052 | if ((dscc4_loopback_check(dpriv) < 0) || !dev->hard_start_xmit) | |
1053 | goto err; | |
1054 | ||
1055 | if ((ret = hdlc_open(dev))) | |
1056 | goto err; | |
1057 | ||
1058 | ppriv = dpriv->pci_priv; | |
1059 | ||
1060 | /* | |
1061 | * Due to various bugs, there is no way to reliably reset a | |
1062 | * specific port (manufacturer's dependant special PCI #RST wiring | |
1063 | * apart: it affects all ports). Thus the device goes in the best | |
1064 | * silent mode possible at dscc4_close() time and simply claims to | |
1065 | * be up if it's opened again. It still isn't possible to change | |
1066 | * the HDLC configuration without rebooting but at least the ports | |
1067 | * can be up/down ifconfig'ed without killing the host. | |
1068 | */ | |
1069 | if (dpriv->flags & FakeReset) { | |
1070 | dpriv->flags &= ~FakeReset; | |
1071 | scc_patchl(0, PowerUp, dpriv, dev, CCR0); | |
1072 | scc_patchl(0, 0x00050000, dpriv, dev, CCR2); | |
1073 | scc_writel(EventsMask, dpriv, dev, IMR); | |
1074 | printk(KERN_INFO "%s: up again.\n", dev->name); | |
1075 | goto done; | |
1076 | } | |
1077 | ||
1078 | /* IDT+IDR during XPR */ | |
1079 | dpriv->flags = NeedIDR | NeedIDT; | |
1080 | ||
1081 | scc_patchl(0, PowerUp | Vis, dpriv, dev, CCR0); | |
1082 | ||
1083 | /* | |
1084 | * The following is a bit paranoid... | |
1085 | * | |
1086 | * NB: the datasheet "...CEC will stay active if the SCC is in | |
1087 | * power-down mode or..." and CCR2.RAC = 1 are two different | |
1088 | * situations. | |
1089 | */ | |
1090 | if (scc_readl_star(dpriv, dev) & SccBusy) { | |
1091 | printk(KERN_ERR "%s busy. Try later\n", dev->name); | |
1092 | ret = -EAGAIN; | |
1093 | goto err_out; | |
1094 | } else | |
1095 | printk(KERN_INFO "%s: available. Good\n", dev->name); | |
1096 | ||
1097 | scc_writel(EventsMask, dpriv, dev, IMR); | |
1098 | ||
1099 | /* Posted write is flushed in the wait_ack loop */ | |
1100 | scc_writel(TxSccRes | RxSccRes, dpriv, dev, CMDR); | |
1101 | ||
1102 | if ((ret = dscc4_wait_ack_cec(dpriv, dev, "Cec")) < 0) | |
1103 | goto err_disable_scc_events; | |
1104 | ||
1105 | /* | |
1106 | * I would expect XPR near CE completion (before ? after ?). | |
1107 | * At worst, this code won't see a late XPR and people | |
1108 | * will have to re-issue an ifconfig (this is harmless). | |
1109 | * WARNING, a really missing XPR usually means a hardware | |
1110 | * reset is needed. Suggestions anyone ? | |
1111 | */ | |
1112 | if ((ret = dscc4_xpr_ack(dpriv)) < 0) { | |
1113 | printk(KERN_ERR "%s: %s timeout\n", DRV_NAME, "XPR"); | |
1114 | goto err_disable_scc_events; | |
1115 | } | |
1116 | ||
1117 | if (debug > 2) | |
1118 | dscc4_tx_print(dev, dpriv, "Open"); | |
1119 | ||
1120 | done: | |
1121 | netif_start_queue(dev); | |
1122 | ||
1123 | init_timer(&dpriv->timer); | |
1124 | dpriv->timer.expires = jiffies + 10*HZ; | |
1125 | dpriv->timer.data = (unsigned long)dev; | |
1126 | dpriv->timer.function = &dscc4_timer; | |
1127 | add_timer(&dpriv->timer); | |
1128 | netif_carrier_on(dev); | |
1129 | ||
1130 | return 0; | |
1131 | ||
1132 | err_disable_scc_events: | |
1133 | scc_writel(0xffffffff, dpriv, dev, IMR); | |
1134 | scc_patchl(PowerUp | Vis, 0, dpriv, dev, CCR0); | |
1135 | err_out: | |
1136 | hdlc_close(dev); | |
1137 | err: | |
1138 | return ret; | |
1139 | } | |
1140 | ||
1141 | #ifdef DSCC4_POLLING | |
1142 | static int dscc4_tx_poll(struct dscc4_dev_priv *dpriv, struct net_device *dev) | |
1143 | { | |
1144 | /* FIXME: it's gonna be easy (TM), for sure */ | |
1145 | } | |
1146 | #endif /* DSCC4_POLLING */ | |
1147 | ||
1148 | static int dscc4_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
1149 | { | |
1150 | struct dscc4_dev_priv *dpriv = dscc4_priv(dev); | |
1151 | struct dscc4_pci_priv *ppriv = dpriv->pci_priv; | |
1152 | struct TxFD *tx_fd; | |
1153 | int next; | |
1154 | ||
1155 | next = dpriv->tx_current%TX_RING_SIZE; | |
1156 | dpriv->tx_skbuff[next] = skb; | |
1157 | tx_fd = dpriv->tx_fd + next; | |
1158 | tx_fd->state = FrameEnd | TO_STATE_TX(skb->len); | |
1159 | tx_fd->data = pci_map_single(ppriv->pdev, skb->data, skb->len, | |
1160 | PCI_DMA_TODEVICE); | |
1161 | tx_fd->complete = 0x00000000; | |
1162 | tx_fd->jiffies = jiffies; | |
1163 | mb(); | |
1164 | ||
1165 | #ifdef DSCC4_POLLING | |
1166 | spin_lock(&dpriv->lock); | |
1167 | while (dscc4_tx_poll(dpriv, dev)); | |
1168 | spin_unlock(&dpriv->lock); | |
1169 | #endif | |
1170 | ||
1171 | dev->trans_start = jiffies; | |
1172 | ||
1173 | if (debug > 2) | |
1174 | dscc4_tx_print(dev, dpriv, "Xmit"); | |
1175 | /* To be cleaned(unsigned int)/optimized. Later, ok ? */ | |
1176 | if (!((++dpriv->tx_current - dpriv->tx_dirty)%TX_RING_SIZE)) | |
1177 | netif_stop_queue(dev); | |
1178 | ||
1179 | if (dscc4_tx_quiescent(dpriv, dev)) | |
1180 | dscc4_do_tx(dpriv, dev); | |
1181 | ||
1182 | return 0; | |
1183 | } | |
1184 | ||
1185 | static int dscc4_close(struct net_device *dev) | |
1186 | { | |
1187 | struct dscc4_dev_priv *dpriv = dscc4_priv(dev); | |
1188 | ||
1189 | del_timer_sync(&dpriv->timer); | |
1190 | netif_stop_queue(dev); | |
1191 | ||
1192 | scc_patchl(PowerUp | Vis, 0, dpriv, dev, CCR0); | |
1193 | scc_patchl(0x00050000, 0, dpriv, dev, CCR2); | |
1194 | scc_writel(0xffffffff, dpriv, dev, IMR); | |
1195 | ||
1196 | dpriv->flags |= FakeReset; | |
1197 | ||
1198 | hdlc_close(dev); | |
1199 | ||
1200 | return 0; | |
1201 | } | |
1202 | ||
1203 | static inline int dscc4_check_clock_ability(int port) | |
1204 | { | |
1205 | int ret = 0; | |
1206 | ||
1207 | #ifdef CONFIG_DSCC4_PCISYNC | |
1208 | if (port >= 2) | |
1209 | ret = -1; | |
1210 | #endif | |
1211 | return ret; | |
1212 | } | |
1213 | ||
1214 | /* | |
1215 | * DS1 p.137: "There are a total of 13 different clocking modes..." | |
1216 | * ^^ | |
1217 | * Design choices: | |
1218 | * - by default, assume a clock is provided on pin RxClk/TxClk (clock mode 0a). | |
1219 | * Clock mode 3b _should_ work but the testing seems to make this point | |
1220 | * dubious (DIY testing requires setting CCR0 at 0x00000033). | |
1221 | * This is supposed to provide least surprise "DTE like" behavior. | |
1222 | * - if line rate is specified, clocks are assumed to be locally generated. | |
1223 | * A quartz must be available (on pin XTAL1). Modes 6b/7b are used. Choosing | |
1224 | * between these it automagically done according on the required frequency | |
1225 | * scaling. Of course some rounding may take place. | |
1226 | * - no high speed mode (40Mb/s). May be trivial to do but I don't have an | |
1227 | * appropriate external clocking device for testing. | |
1228 | * - no time-slot/clock mode 5: shameless lazyness. | |
1229 | * | |
1230 | * The clock signals wiring can be (is ?) manufacturer dependant. Good luck. | |
1231 | * | |
1232 | * BIG FAT WARNING: if the device isn't provided enough clocking signal, it | |
1233 | * won't pass the init sequence. For example, straight back-to-back DTE without | |
1234 | * external clock will fail when dscc4_open() (<- 'ifconfig hdlcx xxx') is | |
1235 | * called. | |
1236 | * | |
1237 | * Typos lurk in datasheet (missing divier in clock mode 7a figure 51 p.153 | |
1238 | * DS0 for example) | |
1239 | * | |
1240 | * Clock mode related bits of CCR0: | |
1241 | * +------------ TOE: output TxClk (0b/2b/3a/3b/6b/7a/7b only) | |
1242 | * | +---------- SSEL: sub-mode select 0 -> a, 1 -> b | |
1243 | * | | +-------- High Speed: say 0 | |
1244 | * | | | +-+-+-- Clock Mode: 0..7 | |
1245 | * | | | | | | | |
1246 | * -+-+-+-+-+-+-+-+ | |
1247 | * x|x|5|4|3|2|1|0| lower bits | |
1248 | * | |
1249 | * Division factor of BRR: k = (N+1)x2^M (total divider = 16xk in mode 6b) | |
1250 | * +-+-+-+------------------ M (0..15) | |
1251 | * | | | | +-+-+-+-+-+-- N (0..63) | |
1252 | * 0 0 0 0 | | | | 0 0 | | | | | | | |
1253 | * ...-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ | |
1254 | * f|e|d|c|b|a|9|8|7|6|5|4|3|2|1|0| lower bits | |
1255 | * | |
1256 | */ | |
1257 | static int dscc4_set_clock(struct net_device *dev, u32 *bps, u32 *state) | |
1258 | { | |
1259 | struct dscc4_dev_priv *dpriv = dscc4_priv(dev); | |
1260 | int ret = -1; | |
1261 | u32 brr; | |
1262 | ||
1263 | *state &= ~Ccr0ClockMask; | |
1264 | if (*bps) { /* Clock generated - required for DCE */ | |
1265 | u32 n = 0, m = 0, divider; | |
1266 | int xtal; | |
1267 | ||
1268 | xtal = dpriv->pci_priv->xtal_hz; | |
1269 | if (!xtal) | |
1270 | goto done; | |
1271 | if (dscc4_check_clock_ability(dpriv->dev_id) < 0) | |
1272 | goto done; | |
1273 | divider = xtal / *bps; | |
1274 | if (divider > BRR_DIVIDER_MAX) { | |
1275 | divider >>= 4; | |
1276 | *state |= 0x00000036; /* Clock mode 6b (BRG/16) */ | |
1277 | } else | |
1278 | *state |= 0x00000037; /* Clock mode 7b (BRG) */ | |
1279 | if (divider >> 22) { | |
1280 | n = 63; | |
1281 | m = 15; | |
1282 | } else if (divider) { | |
1283 | /* Extraction of the 6 highest weighted bits */ | |
1284 | m = 0; | |
1285 | while (0xffffffc0 & divider) { | |
1286 | m++; | |
1287 | divider >>= 1; | |
1288 | } | |
1289 | n = divider; | |
1290 | } | |
1291 | brr = (m << 8) | n; | |
1292 | divider = n << m; | |
1293 | if (!(*state & 0x00000001)) /* ?b mode mask => clock mode 6b */ | |
1294 | divider <<= 4; | |
1295 | *bps = xtal / divider; | |
1296 | } else { | |
1297 | /* | |
1298 | * External clock - DTE | |
1299 | * "state" already reflects Clock mode 0a (CCR0 = 0xzzzzzz00). | |
1300 | * Nothing more to be done | |
1301 | */ | |
1302 | brr = 0; | |
1303 | } | |
1304 | scc_writel(brr, dpriv, dev, BRR); | |
1305 | ret = 0; | |
1306 | done: | |
1307 | return ret; | |
1308 | } | |
1309 | ||
1310 | static int dscc4_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
1311 | { | |
1312 | sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync; | |
1313 | struct dscc4_dev_priv *dpriv = dscc4_priv(dev); | |
1314 | const size_t size = sizeof(dpriv->settings); | |
1315 | int ret = 0; | |
1316 | ||
1317 | if (dev->flags & IFF_UP) | |
1318 | return -EBUSY; | |
1319 | ||
1320 | if (cmd != SIOCWANDEV) | |
1321 | return -EOPNOTSUPP; | |
1322 | ||
1323 | switch(ifr->ifr_settings.type) { | |
1324 | case IF_GET_IFACE: | |
1325 | ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL; | |
1326 | if (ifr->ifr_settings.size < size) { | |
1327 | ifr->ifr_settings.size = size; /* data size wanted */ | |
1328 | return -ENOBUFS; | |
1329 | } | |
1330 | if (copy_to_user(line, &dpriv->settings, size)) | |
1331 | return -EFAULT; | |
1332 | break; | |
1333 | ||
1334 | case IF_IFACE_SYNC_SERIAL: | |
1335 | if (!capable(CAP_NET_ADMIN)) | |
1336 | return -EPERM; | |
1337 | ||
1338 | if (dpriv->flags & FakeReset) { | |
1339 | printk(KERN_INFO "%s: please reset the device" | |
1340 | " before this command\n", dev->name); | |
1341 | return -EPERM; | |
1342 | } | |
1343 | if (copy_from_user(&dpriv->settings, line, size)) | |
1344 | return -EFAULT; | |
1345 | ret = dscc4_set_iface(dpriv, dev); | |
1346 | break; | |
1347 | ||
1348 | default: | |
1349 | ret = hdlc_ioctl(dev, ifr, cmd); | |
1350 | break; | |
1351 | } | |
1352 | ||
1353 | return ret; | |
1354 | } | |
1355 | ||
1356 | static int dscc4_match(struct thingie *p, int value) | |
1357 | { | |
1358 | int i; | |
1359 | ||
1360 | for (i = 0; p[i].define != -1; i++) { | |
1361 | if (value == p[i].define) | |
1362 | break; | |
1363 | } | |
1364 | if (p[i].define == -1) | |
1365 | return -1; | |
1366 | else | |
1367 | return i; | |
1368 | } | |
1369 | ||
1370 | static int dscc4_clock_setting(struct dscc4_dev_priv *dpriv, | |
1371 | struct net_device *dev) | |
1372 | { | |
1373 | sync_serial_settings *settings = &dpriv->settings; | |
1374 | int ret = -EOPNOTSUPP; | |
1375 | u32 bps, state; | |
1376 | ||
1377 | bps = settings->clock_rate; | |
1378 | state = scc_readl(dpriv, CCR0); | |
1379 | if (dscc4_set_clock(dev, &bps, &state) < 0) | |
1380 | goto done; | |
1381 | if (bps) { /* DCE */ | |
1382 | printk(KERN_DEBUG "%s: generated RxClk (DCE)\n", dev->name); | |
1383 | if (settings->clock_rate != bps) { | |
1384 | printk(KERN_DEBUG "%s: clock adjusted (%08d -> %08d)\n", | |
1385 | dev->name, settings->clock_rate, bps); | |
1386 | settings->clock_rate = bps; | |
1387 | } | |
1388 | } else { /* DTE */ | |
1389 | state |= PowerUp | Vis; | |
1390 | printk(KERN_DEBUG "%s: external RxClk (DTE)\n", dev->name); | |
1391 | } | |
1392 | scc_writel(state, dpriv, dev, CCR0); | |
1393 | ret = 0; | |
1394 | done: | |
1395 | return ret; | |
1396 | } | |
1397 | ||
1398 | static int dscc4_encoding_setting(struct dscc4_dev_priv *dpriv, | |
1399 | struct net_device *dev) | |
1400 | { | |
1401 | struct thingie encoding[] = { | |
1402 | { ENCODING_NRZ, 0x00000000 }, | |
1403 | { ENCODING_NRZI, 0x00200000 }, | |
1404 | { ENCODING_FM_MARK, 0x00400000 }, | |
1405 | { ENCODING_FM_SPACE, 0x00500000 }, | |
1406 | { ENCODING_MANCHESTER, 0x00600000 }, | |
1407 | { -1, 0} | |
1408 | }; | |
1409 | int i, ret = 0; | |
1410 | ||
1411 | i = dscc4_match(encoding, dpriv->encoding); | |
1412 | if (i >= 0) | |
1413 | scc_patchl(EncodingMask, encoding[i].bits, dpriv, dev, CCR0); | |
1414 | else | |
1415 | ret = -EOPNOTSUPP; | |
1416 | return ret; | |
1417 | } | |
1418 | ||
1419 | static int dscc4_loopback_setting(struct dscc4_dev_priv *dpriv, | |
1420 | struct net_device *dev) | |
1421 | { | |
1422 | sync_serial_settings *settings = &dpriv->settings; | |
1423 | u32 state; | |
1424 | ||
1425 | state = scc_readl(dpriv, CCR1); | |
1426 | if (settings->loopback) { | |
1427 | printk(KERN_DEBUG "%s: loopback\n", dev->name); | |
1428 | state |= 0x00000100; | |
1429 | } else { | |
1430 | printk(KERN_DEBUG "%s: normal\n", dev->name); | |
1431 | state &= ~0x00000100; | |
1432 | } | |
1433 | scc_writel(state, dpriv, dev, CCR1); | |
1434 | return 0; | |
1435 | } | |
1436 | ||
1437 | static int dscc4_crc_setting(struct dscc4_dev_priv *dpriv, | |
1438 | struct net_device *dev) | |
1439 | { | |
1440 | struct thingie crc[] = { | |
1441 | { PARITY_CRC16_PR0_CCITT, 0x00000010 }, | |
1442 | { PARITY_CRC16_PR1_CCITT, 0x00000000 }, | |
1443 | { PARITY_CRC32_PR0_CCITT, 0x00000011 }, | |
1444 | { PARITY_CRC32_PR1_CCITT, 0x00000001 } | |
1445 | }; | |
1446 | int i, ret = 0; | |
1447 | ||
1448 | i = dscc4_match(crc, dpriv->parity); | |
1449 | if (i >= 0) | |
1450 | scc_patchl(CrcMask, crc[i].bits, dpriv, dev, CCR1); | |
1451 | else | |
1452 | ret = -EOPNOTSUPP; | |
1453 | return ret; | |
1454 | } | |
1455 | ||
1456 | static int dscc4_set_iface(struct dscc4_dev_priv *dpriv, struct net_device *dev) | |
1457 | { | |
1458 | struct { | |
1459 | int (*action)(struct dscc4_dev_priv *, struct net_device *); | |
1460 | } *p, do_setting[] = { | |
1461 | { dscc4_encoding_setting }, | |
1462 | { dscc4_clock_setting }, | |
1463 | { dscc4_loopback_setting }, | |
1464 | { dscc4_crc_setting }, | |
1465 | { NULL } | |
1466 | }; | |
1467 | int ret = 0; | |
1468 | ||
1469 | for (p = do_setting; p->action; p++) { | |
1470 | if ((ret = p->action(dpriv, dev)) < 0) | |
1471 | break; | |
1472 | } | |
1473 | return ret; | |
1474 | } | |
1475 | ||
1476 | static irqreturn_t dscc4_irq(int irq, void *token, struct pt_regs *ptregs) | |
1477 | { | |
1478 | struct dscc4_dev_priv *root = token; | |
1479 | struct dscc4_pci_priv *priv; | |
1480 | struct net_device *dev; | |
1481 | void __iomem *ioaddr; | |
1482 | u32 state; | |
1483 | unsigned long flags; | |
1484 | int i, handled = 1; | |
1485 | ||
1486 | priv = root->pci_priv; | |
1487 | dev = dscc4_to_dev(root); | |
1488 | ||
1489 | spin_lock_irqsave(&priv->lock, flags); | |
1490 | ||
1491 | ioaddr = root->base_addr; | |
1492 | ||
1493 | state = readl(ioaddr + GSTAR); | |
1494 | if (!state) { | |
1495 | handled = 0; | |
1496 | goto out; | |
1497 | } | |
1498 | if (debug > 3) | |
1499 | printk(KERN_DEBUG "%s: GSTAR = 0x%08x\n", DRV_NAME, state); | |
1500 | writel(state, ioaddr + GSTAR); | |
1501 | ||
1502 | if (state & Arf) { | |
1503 | printk(KERN_ERR "%s: failure (Arf). Harass the maintener\n", | |
1504 | dev->name); | |
1505 | goto out; | |
1506 | } | |
1507 | state &= ~ArAck; | |
1508 | if (state & Cfg) { | |
1509 | if (debug > 0) | |
1510 | printk(KERN_DEBUG "%s: CfgIV\n", DRV_NAME); | |
1511 | if (priv->iqcfg[priv->cfg_cur++%IRQ_RING_SIZE] & Arf) | |
1512 | printk(KERN_ERR "%s: %s failed\n", dev->name, "CFG"); | |
1513 | if (!(state &= ~Cfg)) | |
1514 | goto out; | |
1515 | } | |
1516 | if (state & RxEvt) { | |
1517 | i = dev_per_card - 1; | |
1518 | do { | |
1519 | dscc4_rx_irq(priv, root + i); | |
1520 | } while (--i >= 0); | |
1521 | state &= ~RxEvt; | |
1522 | } | |
1523 | if (state & TxEvt) { | |
1524 | i = dev_per_card - 1; | |
1525 | do { | |
1526 | dscc4_tx_irq(priv, root + i); | |
1527 | } while (--i >= 0); | |
1528 | state &= ~TxEvt; | |
1529 | } | |
1530 | out: | |
1531 | spin_unlock_irqrestore(&priv->lock, flags); | |
1532 | return IRQ_RETVAL(handled); | |
1533 | } | |
1534 | ||
1535 | static void dscc4_tx_irq(struct dscc4_pci_priv *ppriv, | |
1536 | struct dscc4_dev_priv *dpriv) | |
1537 | { | |
1538 | struct net_device *dev = dscc4_to_dev(dpriv); | |
1539 | u32 state; | |
1540 | int cur, loop = 0; | |
1541 | ||
1542 | try: | |
1543 | cur = dpriv->iqtx_current%IRQ_RING_SIZE; | |
1544 | state = dpriv->iqtx[cur]; | |
1545 | if (!state) { | |
1546 | if (debug > 4) | |
1547 | printk(KERN_DEBUG "%s: Tx ISR = 0x%08x\n", dev->name, | |
1548 | state); | |
1549 | if ((debug > 1) && (loop > 1)) | |
1550 | printk(KERN_DEBUG "%s: Tx irq loop=%d\n", dev->name, loop); | |
1551 | if (loop && netif_queue_stopped(dev)) | |
1552 | if ((dpriv->tx_current - dpriv->tx_dirty)%TX_RING_SIZE) | |
1553 | netif_wake_queue(dev); | |
1554 | ||
1555 | if (netif_running(dev) && dscc4_tx_quiescent(dpriv, dev) && | |
1556 | !dscc4_tx_done(dpriv)) | |
1557 | dscc4_do_tx(dpriv, dev); | |
1558 | return; | |
1559 | } | |
1560 | loop++; | |
1561 | dpriv->iqtx[cur] = 0; | |
1562 | dpriv->iqtx_current++; | |
1563 | ||
1564 | if (state_check(state, dpriv, dev, "Tx") < 0) | |
1565 | return; | |
1566 | ||
1567 | if (state & SccEvt) { | |
1568 | if (state & Alls) { | |
1569 | struct net_device_stats *stats = hdlc_stats(dev); | |
1570 | struct sk_buff *skb; | |
1571 | struct TxFD *tx_fd; | |
1572 | ||
1573 | if (debug > 2) | |
1574 | dscc4_tx_print(dev, dpriv, "Alls"); | |
1575 | /* | |
1576 | * DataComplete can't be trusted for Tx completion. | |
1577 | * Cf errata DS5 p.8 | |
1578 | */ | |
1579 | cur = dpriv->tx_dirty%TX_RING_SIZE; | |
1580 | tx_fd = dpriv->tx_fd + cur; | |
1581 | skb = dpriv->tx_skbuff[cur]; | |
1582 | if (skb) { | |
1583 | pci_unmap_single(ppriv->pdev, tx_fd->data, | |
1584 | skb->len, PCI_DMA_TODEVICE); | |
1585 | if (tx_fd->state & FrameEnd) { | |
1586 | stats->tx_packets++; | |
1587 | stats->tx_bytes += skb->len; | |
1588 | } | |
1589 | dev_kfree_skb_irq(skb); | |
1590 | dpriv->tx_skbuff[cur] = NULL; | |
1591 | ++dpriv->tx_dirty; | |
1592 | } else { | |
1593 | if (debug > 1) | |
1594 | printk(KERN_ERR "%s Tx: NULL skb %d\n", | |
1595 | dev->name, cur); | |
1596 | } | |
1597 | /* | |
1598 | * If the driver ends sending crap on the wire, it | |
1599 | * will be way easier to diagnose than the (not so) | |
1600 | * random freeze induced by null sized tx frames. | |
1601 | */ | |
1602 | tx_fd->data = tx_fd->next; | |
1603 | tx_fd->state = FrameEnd | TO_STATE_TX(2*DUMMY_SKB_SIZE); | |
1604 | tx_fd->complete = 0x00000000; | |
1605 | tx_fd->jiffies = 0; | |
1606 | ||
1607 | if (!(state &= ~Alls)) | |
1608 | goto try; | |
1609 | } | |
1610 | /* | |
1611 | * Transmit Data Underrun | |
1612 | */ | |
1613 | if (state & Xdu) { | |
1614 | printk(KERN_ERR "%s: XDU. Ask maintainer\n", DRV_NAME); | |
1615 | dpriv->flags = NeedIDT; | |
1616 | /* Tx reset */ | |
1617 | writel(MTFi | Rdt, | |
1618 | dpriv->base_addr + 0x0c*dpriv->dev_id + CH0CFG); | |
1619 | writel(Action, dpriv->base_addr + GCMDR); | |
1620 | return; | |
1621 | } | |
1622 | if (state & Cts) { | |
1623 | printk(KERN_INFO "%s: CTS transition\n", dev->name); | |
1624 | if (!(state &= ~Cts)) /* DEBUG */ | |
1625 | goto try; | |
1626 | } | |
1627 | if (state & Xmr) { | |
1628 | /* Frame needs to be sent again - FIXME */ | |
1629 | printk(KERN_ERR "%s: Xmr. Ask maintainer\n", DRV_NAME); | |
1630 | if (!(state &= ~Xmr)) /* DEBUG */ | |
1631 | goto try; | |
1632 | } | |
1633 | if (state & Xpr) { | |
1634 | void __iomem *scc_addr; | |
1635 | unsigned long ring; | |
1636 | int i; | |
1637 | ||
1638 | /* | |
1639 | * - the busy condition happens (sometimes); | |
1640 | * - it doesn't seem to make the handler unreliable. | |
1641 | */ | |
1642 | for (i = 1; i; i <<= 1) { | |
1643 | if (!(scc_readl_star(dpriv, dev) & SccBusy)) | |
1644 | break; | |
1645 | } | |
1646 | if (!i) | |
1647 | printk(KERN_INFO "%s busy in irq\n", dev->name); | |
1648 | ||
1649 | scc_addr = dpriv->base_addr + 0x0c*dpriv->dev_id; | |
1650 | /* Keep this order: IDT before IDR */ | |
1651 | if (dpriv->flags & NeedIDT) { | |
1652 | if (debug > 2) | |
1653 | dscc4_tx_print(dev, dpriv, "Xpr"); | |
1654 | ring = dpriv->tx_fd_dma + | |
1655 | (dpriv->tx_dirty%TX_RING_SIZE)* | |
1656 | sizeof(struct TxFD); | |
1657 | writel(ring, scc_addr + CH0BTDA); | |
1658 | dscc4_do_tx(dpriv, dev); | |
1659 | writel(MTFi | Idt, scc_addr + CH0CFG); | |
1660 | if (dscc4_do_action(dev, "IDT") < 0) | |
1661 | goto err_xpr; | |
1662 | dpriv->flags &= ~NeedIDT; | |
1663 | } | |
1664 | if (dpriv->flags & NeedIDR) { | |
1665 | ring = dpriv->rx_fd_dma + | |
1666 | (dpriv->rx_current%RX_RING_SIZE)* | |
1667 | sizeof(struct RxFD); | |
1668 | writel(ring, scc_addr + CH0BRDA); | |
1669 | dscc4_rx_update(dpriv, dev); | |
1670 | writel(MTFi | Idr, scc_addr + CH0CFG); | |
1671 | if (dscc4_do_action(dev, "IDR") < 0) | |
1672 | goto err_xpr; | |
1673 | dpriv->flags &= ~NeedIDR; | |
1674 | smp_wmb(); | |
1675 | /* Activate receiver and misc */ | |
1676 | scc_writel(0x08050008, dpriv, dev, CCR2); | |
1677 | } | |
1678 | err_xpr: | |
1679 | if (!(state &= ~Xpr)) | |
1680 | goto try; | |
1681 | } | |
1682 | if (state & Cd) { | |
1683 | if (debug > 0) | |
1684 | printk(KERN_INFO "%s: CD transition\n", dev->name); | |
1685 | if (!(state &= ~Cd)) /* DEBUG */ | |
1686 | goto try; | |
1687 | } | |
1688 | } else { /* ! SccEvt */ | |
1689 | if (state & Hi) { | |
1690 | #ifdef DSCC4_POLLING | |
1691 | while (!dscc4_tx_poll(dpriv, dev)); | |
1692 | #endif | |
1693 | printk(KERN_INFO "%s: Tx Hi\n", dev->name); | |
1694 | state &= ~Hi; | |
1695 | } | |
1696 | if (state & Err) { | |
1697 | printk(KERN_INFO "%s: Tx ERR\n", dev->name); | |
1698 | hdlc_stats(dev)->tx_errors++; | |
1699 | state &= ~Err; | |
1700 | } | |
1701 | } | |
1702 | goto try; | |
1703 | } | |
1704 | ||
1705 | static void dscc4_rx_irq(struct dscc4_pci_priv *priv, | |
1706 | struct dscc4_dev_priv *dpriv) | |
1707 | { | |
1708 | struct net_device *dev = dscc4_to_dev(dpriv); | |
1709 | u32 state; | |
1710 | int cur; | |
1711 | ||
1712 | try: | |
1713 | cur = dpriv->iqrx_current%IRQ_RING_SIZE; | |
1714 | state = dpriv->iqrx[cur]; | |
1715 | if (!state) | |
1716 | return; | |
1717 | dpriv->iqrx[cur] = 0; | |
1718 | dpriv->iqrx_current++; | |
1719 | ||
1720 | if (state_check(state, dpriv, dev, "Rx") < 0) | |
1721 | return; | |
1722 | ||
1723 | if (!(state & SccEvt)){ | |
1724 | struct RxFD *rx_fd; | |
1725 | ||
1726 | if (debug > 4) | |
1727 | printk(KERN_DEBUG "%s: Rx ISR = 0x%08x\n", dev->name, | |
1728 | state); | |
1729 | state &= 0x00ffffff; | |
1730 | if (state & Err) { /* Hold or reset */ | |
1731 | printk(KERN_DEBUG "%s: Rx ERR\n", dev->name); | |
1732 | cur = dpriv->rx_current%RX_RING_SIZE; | |
1733 | rx_fd = dpriv->rx_fd + cur; | |
1734 | /* | |
1735 | * Presume we're not facing a DMAC receiver reset. | |
1736 | * As We use the rx size-filtering feature of the | |
1737 | * DSCC4, the beginning of a new frame is waiting in | |
1738 | * the rx fifo. I bet a Receive Data Overflow will | |
1739 | * happen most of time but let's try and avoid it. | |
1740 | * Btw (as for RDO) if one experiences ERR whereas | |
1741 | * the system looks rather idle, there may be a | |
1742 | * problem with latency. In this case, increasing | |
1743 | * RX_RING_SIZE may help. | |
1744 | */ | |
1745 | //while (dpriv->rx_needs_refill) { | |
1746 | while (!(rx_fd->state1 & Hold)) { | |
1747 | rx_fd++; | |
1748 | cur++; | |
1749 | if (!(cur = cur%RX_RING_SIZE)) | |
1750 | rx_fd = dpriv->rx_fd; | |
1751 | } | |
1752 | //dpriv->rx_needs_refill--; | |
1753 | try_get_rx_skb(dpriv, dev); | |
1754 | if (!rx_fd->data) | |
1755 | goto try; | |
1756 | rx_fd->state1 &= ~Hold; | |
1757 | rx_fd->state2 = 0x00000000; | |
1758 | rx_fd->end = 0xbabeface; | |
1759 | //} | |
1760 | goto try; | |
1761 | } | |
1762 | if (state & Fi) { | |
1763 | dscc4_rx_skb(dpriv, dev); | |
1764 | goto try; | |
1765 | } | |
1766 | if (state & Hi ) { /* HI bit */ | |
1767 | printk(KERN_INFO "%s: Rx Hi\n", dev->name); | |
1768 | state &= ~Hi; | |
1769 | goto try; | |
1770 | } | |
1771 | } else { /* SccEvt */ | |
1772 | if (debug > 1) { | |
1773 | //FIXME: verifier la presence de tous les evenements | |
1774 | static struct { | |
1775 | u32 mask; | |
1776 | const char *irq_name; | |
1777 | } evts[] = { | |
1778 | { 0x00008000, "TIN"}, | |
1779 | { 0x00000020, "RSC"}, | |
1780 | { 0x00000010, "PCE"}, | |
1781 | { 0x00000008, "PLLA"}, | |
1782 | { 0, NULL} | |
1783 | }, *evt; | |
1784 | ||
1785 | for (evt = evts; evt->irq_name; evt++) { | |
1786 | if (state & evt->mask) { | |
1787 | printk(KERN_DEBUG "%s: %s\n", | |
1788 | dev->name, evt->irq_name); | |
1789 | if (!(state &= ~evt->mask)) | |
1790 | goto try; | |
1791 | } | |
1792 | } | |
1793 | } else { | |
1794 | if (!(state &= ~0x0000c03c)) | |
1795 | goto try; | |
1796 | } | |
1797 | if (state & Cts) { | |
1798 | printk(KERN_INFO "%s: CTS transition\n", dev->name); | |
1799 | if (!(state &= ~Cts)) /* DEBUG */ | |
1800 | goto try; | |
1801 | } | |
1802 | /* | |
1803 | * Receive Data Overflow (FIXME: fscked) | |
1804 | */ | |
1805 | if (state & Rdo) { | |
1806 | struct RxFD *rx_fd; | |
1807 | void __iomem *scc_addr; | |
1808 | int cur; | |
1809 | ||
1810 | //if (debug) | |
1811 | // dscc4_rx_dump(dpriv); | |
1812 | scc_addr = dpriv->base_addr + 0x0c*dpriv->dev_id; | |
1813 | ||
1814 | scc_patchl(RxActivate, 0, dpriv, dev, CCR2); | |
1815 | /* | |
1816 | * This has no effect. Why ? | |
1817 | * ORed with TxSccRes, one sees the CFG ack (for | |
1818 | * the TX part only). | |
1819 | */ | |
1820 | scc_writel(RxSccRes, dpriv, dev, CMDR); | |
1821 | dpriv->flags |= RdoSet; | |
1822 | ||
1823 | /* | |
1824 | * Let's try and save something in the received data. | |
1825 | * rx_current must be incremented at least once to | |
1826 | * avoid HOLD in the BRDA-to-be-pointed desc. | |
1827 | */ | |
1828 | do { | |
1829 | cur = dpriv->rx_current++%RX_RING_SIZE; | |
1830 | rx_fd = dpriv->rx_fd + cur; | |
1831 | if (!(rx_fd->state2 & DataComplete)) | |
1832 | break; | |
1833 | if (rx_fd->state2 & FrameAborted) { | |
1834 | hdlc_stats(dev)->rx_over_errors++; | |
1835 | rx_fd->state1 |= Hold; | |
1836 | rx_fd->state2 = 0x00000000; | |
1837 | rx_fd->end = 0xbabeface; | |
1838 | } else | |
1839 | dscc4_rx_skb(dpriv, dev); | |
1840 | } while (1); | |
1841 | ||
1842 | if (debug > 0) { | |
1843 | if (dpriv->flags & RdoSet) | |
1844 | printk(KERN_DEBUG | |
1845 | "%s: no RDO in Rx data\n", DRV_NAME); | |
1846 | } | |
1847 | #ifdef DSCC4_RDO_EXPERIMENTAL_RECOVERY | |
1848 | /* | |
1849 | * FIXME: must the reset be this violent ? | |
1850 | */ | |
1851 | #warning "FIXME: CH0BRDA" | |
1852 | writel(dpriv->rx_fd_dma + | |
1853 | (dpriv->rx_current%RX_RING_SIZE)* | |
1854 | sizeof(struct RxFD), scc_addr + CH0BRDA); | |
1855 | writel(MTFi|Rdr|Idr, scc_addr + CH0CFG); | |
1856 | if (dscc4_do_action(dev, "RDR") < 0) { | |
1857 | printk(KERN_ERR "%s: RDO recovery failed(%s)\n", | |
1858 | dev->name, "RDR"); | |
1859 | goto rdo_end; | |
1860 | } | |
1861 | writel(MTFi|Idr, scc_addr + CH0CFG); | |
1862 | if (dscc4_do_action(dev, "IDR") < 0) { | |
1863 | printk(KERN_ERR "%s: RDO recovery failed(%s)\n", | |
1864 | dev->name, "IDR"); | |
1865 | goto rdo_end; | |
1866 | } | |
1867 | rdo_end: | |
1868 | #endif | |
1869 | scc_patchl(0, RxActivate, dpriv, dev, CCR2); | |
1870 | goto try; | |
1871 | } | |
1872 | if (state & Cd) { | |
1873 | printk(KERN_INFO "%s: CD transition\n", dev->name); | |
1874 | if (!(state &= ~Cd)) /* DEBUG */ | |
1875 | goto try; | |
1876 | } | |
1877 | if (state & Flex) { | |
1878 | printk(KERN_DEBUG "%s: Flex. Ttttt...\n", DRV_NAME); | |
1879 | if (!(state &= ~Flex)) | |
1880 | goto try; | |
1881 | } | |
1882 | } | |
1883 | } | |
1884 | ||
1885 | /* | |
1886 | * I had expected the following to work for the first descriptor | |
1887 | * (tx_fd->state = 0xc0000000) | |
1888 | * - Hold=1 (don't try and branch to the next descripto); | |
1889 | * - No=0 (I want an empty data section, i.e. size=0); | |
1890 | * - Fe=1 (required by No=0 or we got an Err irq and must reset). | |
1891 | * It failed and locked solid. Thus the introduction of a dummy skb. | |
1892 | * Problem is acknowledged in errata sheet DS5. Joy :o/ | |
1893 | */ | |
1894 | struct sk_buff *dscc4_init_dummy_skb(struct dscc4_dev_priv *dpriv) | |
1895 | { | |
1896 | struct sk_buff *skb; | |
1897 | ||
1898 | skb = dev_alloc_skb(DUMMY_SKB_SIZE); | |
1899 | if (skb) { | |
1900 | int last = dpriv->tx_dirty%TX_RING_SIZE; | |
1901 | struct TxFD *tx_fd = dpriv->tx_fd + last; | |
1902 | ||
1903 | skb->len = DUMMY_SKB_SIZE; | |
1904 | memcpy(skb->data, version, strlen(version)%DUMMY_SKB_SIZE); | |
1905 | tx_fd->state = FrameEnd | TO_STATE_TX(DUMMY_SKB_SIZE); | |
1906 | tx_fd->data = pci_map_single(dpriv->pci_priv->pdev, skb->data, | |
1907 | DUMMY_SKB_SIZE, PCI_DMA_TODEVICE); | |
1908 | dpriv->tx_skbuff[last] = skb; | |
1909 | } | |
1910 | return skb; | |
1911 | } | |
1912 | ||
1913 | static int dscc4_init_ring(struct net_device *dev) | |
1914 | { | |
1915 | struct dscc4_dev_priv *dpriv = dscc4_priv(dev); | |
1916 | struct pci_dev *pdev = dpriv->pci_priv->pdev; | |
1917 | struct TxFD *tx_fd; | |
1918 | struct RxFD *rx_fd; | |
1919 | void *ring; | |
1920 | int i; | |
1921 | ||
1922 | ring = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &dpriv->rx_fd_dma); | |
1923 | if (!ring) | |
1924 | goto err_out; | |
1925 | dpriv->rx_fd = rx_fd = (struct RxFD *) ring; | |
1926 | ||
1927 | ring = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &dpriv->tx_fd_dma); | |
1928 | if (!ring) | |
1929 | goto err_free_dma_rx; | |
1930 | dpriv->tx_fd = tx_fd = (struct TxFD *) ring; | |
1931 | ||
1932 | memset(dpriv->tx_skbuff, 0, sizeof(struct sk_buff *)*TX_RING_SIZE); | |
1933 | dpriv->tx_dirty = 0xffffffff; | |
1934 | i = dpriv->tx_current = 0; | |
1935 | do { | |
1936 | tx_fd->state = FrameEnd | TO_STATE_TX(2*DUMMY_SKB_SIZE); | |
1937 | tx_fd->complete = 0x00000000; | |
1938 | /* FIXME: NULL should be ok - to be tried */ | |
1939 | tx_fd->data = dpriv->tx_fd_dma; | |
1940 | (tx_fd++)->next = (u32)(dpriv->tx_fd_dma + | |
1941 | (++i%TX_RING_SIZE)*sizeof(*tx_fd)); | |
1942 | } while (i < TX_RING_SIZE); | |
1943 | ||
1944 | if (dscc4_init_dummy_skb(dpriv) < 0) | |
1945 | goto err_free_dma_tx; | |
1946 | ||
1947 | memset(dpriv->rx_skbuff, 0, sizeof(struct sk_buff *)*RX_RING_SIZE); | |
1948 | i = dpriv->rx_dirty = dpriv->rx_current = 0; | |
1949 | do { | |
1950 | /* size set by the host. Multiple of 4 bytes please */ | |
1951 | rx_fd->state1 = HiDesc; | |
1952 | rx_fd->state2 = 0x00000000; | |
1953 | rx_fd->end = 0xbabeface; | |
1954 | rx_fd->state1 |= TO_STATE_RX(HDLC_MAX_MRU); | |
1955 | // FIXME: return value verifiee mais traitement suspect | |
1956 | if (try_get_rx_skb(dpriv, dev) >= 0) | |
1957 | dpriv->rx_dirty++; | |
1958 | (rx_fd++)->next = (u32)(dpriv->rx_fd_dma + | |
1959 | (++i%RX_RING_SIZE)*sizeof(*rx_fd)); | |
1960 | } while (i < RX_RING_SIZE); | |
1961 | ||
1962 | return 0; | |
1963 | ||
1964 | err_free_dma_tx: | |
1965 | pci_free_consistent(pdev, TX_TOTAL_SIZE, ring, dpriv->tx_fd_dma); | |
1966 | err_free_dma_rx: | |
1967 | pci_free_consistent(pdev, RX_TOTAL_SIZE, rx_fd, dpriv->rx_fd_dma); | |
1968 | err_out: | |
1969 | return -ENOMEM; | |
1970 | } | |
1971 | ||
1972 | static void __devexit dscc4_remove_one(struct pci_dev *pdev) | |
1973 | { | |
1974 | struct dscc4_pci_priv *ppriv; | |
1975 | struct dscc4_dev_priv *root; | |
1976 | void __iomem *ioaddr; | |
1977 | int i; | |
1978 | ||
1979 | ppriv = pci_get_drvdata(pdev); | |
1980 | root = ppriv->root; | |
1981 | ||
1982 | ioaddr = root->base_addr; | |
1983 | ||
1984 | dscc4_pci_reset(pdev, ioaddr); | |
1985 | ||
1986 | free_irq(pdev->irq, root); | |
1987 | pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32), ppriv->iqcfg, | |
1988 | ppriv->iqcfg_dma); | |
1989 | for (i = 0; i < dev_per_card; i++) { | |
1990 | struct dscc4_dev_priv *dpriv = root + i; | |
1991 | ||
1992 | dscc4_release_ring(dpriv); | |
1993 | pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32), | |
1994 | dpriv->iqrx, dpriv->iqrx_dma); | |
1995 | pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32), | |
1996 | dpriv->iqtx, dpriv->iqtx_dma); | |
1997 | } | |
1998 | ||
1999 | dscc4_free1(pdev); | |
2000 | ||
2001 | iounmap(ioaddr); | |
2002 | ||
2003 | pci_release_region(pdev, 1); | |
2004 | pci_release_region(pdev, 0); | |
2005 | ||
2006 | pci_disable_device(pdev); | |
2007 | } | |
2008 | ||
2009 | static int dscc4_hdlc_attach(struct net_device *dev, unsigned short encoding, | |
2010 | unsigned short parity) | |
2011 | { | |
2012 | struct dscc4_dev_priv *dpriv = dscc4_priv(dev); | |
2013 | ||
2014 | if (encoding != ENCODING_NRZ && | |
2015 | encoding != ENCODING_NRZI && | |
2016 | encoding != ENCODING_FM_MARK && | |
2017 | encoding != ENCODING_FM_SPACE && | |
2018 | encoding != ENCODING_MANCHESTER) | |
2019 | return -EINVAL; | |
2020 | ||
2021 | if (parity != PARITY_NONE && | |
2022 | parity != PARITY_CRC16_PR0_CCITT && | |
2023 | parity != PARITY_CRC16_PR1_CCITT && | |
2024 | parity != PARITY_CRC32_PR0_CCITT && | |
2025 | parity != PARITY_CRC32_PR1_CCITT) | |
2026 | return -EINVAL; | |
2027 | ||
2028 | dpriv->encoding = encoding; | |
2029 | dpriv->parity = parity; | |
2030 | return 0; | |
2031 | } | |
2032 | ||
2033 | #ifndef MODULE | |
2034 | static int __init dscc4_setup(char *str) | |
2035 | { | |
2036 | int *args[] = { &debug, &quartz, NULL }, **p = args; | |
2037 | ||
2038 | while (*p && (get_option(&str, *p) == 2)) | |
2039 | p++; | |
2040 | return 1; | |
2041 | } | |
2042 | ||
2043 | __setup("dscc4.setup=", dscc4_setup); | |
2044 | #endif | |
2045 | ||
2046 | static struct pci_device_id dscc4_pci_tbl[] = { | |
2047 | { PCI_VENDOR_ID_SIEMENS, PCI_DEVICE_ID_SIEMENS_DSCC4, | |
2048 | PCI_ANY_ID, PCI_ANY_ID, }, | |
2049 | { 0,} | |
2050 | }; | |
2051 | MODULE_DEVICE_TABLE(pci, dscc4_pci_tbl); | |
2052 | ||
2053 | static struct pci_driver dscc4_driver = { | |
2054 | .name = DRV_NAME, | |
2055 | .id_table = dscc4_pci_tbl, | |
2056 | .probe = dscc4_init_one, | |
2057 | .remove = __devexit_p(dscc4_remove_one), | |
2058 | }; | |
2059 | ||
2060 | static int __init dscc4_init_module(void) | |
2061 | { | |
2062 | return pci_module_init(&dscc4_driver); | |
2063 | } | |
2064 | ||
2065 | static void __exit dscc4_cleanup_module(void) | |
2066 | { | |
2067 | pci_unregister_driver(&dscc4_driver); | |
2068 | } | |
2069 | ||
2070 | module_init(dscc4_init_module); | |
2071 | module_exit(dscc4_cleanup_module); |