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WAN: Convert generic HDLC drivers to netdev_ops.
[mirror_ubuntu-artful-kernel.git] / drivers / net / wan / dscc4.c
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1da177e4
LT		 1/*
2 * drivers/net/wan/dscc4/dscc4.c: a DSCC4 HDLC driver for Linux
3 *
4 * This software may be used and distributed according to the terms of the
5 * GNU General Public License.
6 *
7 * The author may be reached as romieu@cogenit.fr.
8 * Specific bug reports/asian food will be welcome.
9 *
10 * Special thanks to the nice people at CS-Telecom for the hardware and the
11 * access to the test/measure tools.
12 *
13 *
14 * Theory of Operation
15 *
16 * I. Board Compatibility
17 *
18 * This device driver is designed for the Siemens PEB20534 4 ports serial
19 * controller as found on Etinc PCISYNC cards. The documentation for the
20 * chipset is available at http://www.infineon.com:
21 * - Data Sheet "DSCC4, DMA Supported Serial Communication Controller with
22 * 4 Channels, PEB 20534 Version 2.1, PEF 20534 Version 2.1";
23 * - Application Hint "Management of DSCC4 on-chip FIFO resources".
24 * - Errata sheet DS5 (courtesy of Michael Skerritt).
25 * Jens David has built an adapter based on the same chipset. Take a look
26 * at http://www.afthd.tu-darmstadt.de/~dg1kjd/pciscc4 for a specific
27 * driver.
28 * Sample code (2 revisions) is available at Infineon.
29 *
30 * II. Board-specific settings
31 *
32 * Pcisync can transmit some clock signal to the outside world on the
33 * *first two* ports provided you put a quartz and a line driver on it and
34 * remove the jumpers. The operation is described on Etinc web site. If you
35 * go DCE on these ports, don't forget to use an adequate cable.
36 *
37 * Sharing of the PCI interrupt line for this board is possible.
38 *
39 * III. Driver operation
40 *
41 * The rx/tx operations are based on a linked list of descriptors. The driver
42 * doesn't use HOLD mode any more. HOLD mode is definitely buggy and the more
43 * I tried to fix it, the more it started to look like (convoluted) software
44 * mutation of LxDA method. Errata sheet DS5 suggests to use LxDA: consider
45 * this a rfc2119 MUST.
46 *
47 * Tx direction
48 * When the tx ring is full, the xmit routine issues a call to netdev_stop.
49 * The device is supposed to be enabled again during an ALLS irq (we could
50 * use HI but as it's easy to lose events, it's fscked).
51 *
52 * Rx direction
53 * The received frames aren't supposed to span over multiple receiving areas.
54 * I may implement it some day but it isn't the highest ranked item.
55 *
56 * IV. Notes
57 * The current error (XDU, RFO) recovery code is untested.
58 * So far, RDO takes his RX channel down and the right sequence to enable it
59 * again is still a mistery. If RDO happens, plan a reboot. More details
60 * in the code (NB: as this happens, TX still works).
61 * Don't mess the cables during operation, especially on DTE ports. I don't
62 * suggest it for DCE either but at least one can get some messages instead
63 * of a complete instant freeze.
64 * Tests are done on Rev. 20 of the silicium. The RDO handling changes with
65 * the documentation/chipset releases.
66 *
67 * TODO:
68 * - test X25.
69 * - use polling at high irq/s,
70 * - performance analysis,
71 * - endianness.
72 *
73 * 2001/12/10 Daniela Squassoni <daniela@cyclades.com>
74 * - Contribution to support the new generic HDLC layer.
75 *
76 * 2002/01 Ueimor
77 * - old style interface removal
78 * - dscc4_release_ring fix (related to DMA mapping)
79 * - hard_start_xmit fix (hint: TxSizeMax)
80 * - misc crapectomy.
81 */
82
83#include <linux/module.h>
84#include <linux/types.h>
85#include <linux/errno.h>
86#include <linux/list.h>
87#include <linux/ioport.h>
88#include <linux/pci.h>
89#include <linux/kernel.h>
90#include <linux/mm.h>
91
92#include <asm/system.h>
93#include <asm/cache.h>
94#include <asm/byteorder.h>
95#include <asm/uaccess.h>
96#include <asm/io.h>
97#include <asm/irq.h>
98
99#include <linux/init.h>
100#include <linux/string.h>
101
102#include <linux/if_arp.h>
103#include <linux/netdevice.h>
104#include <linux/skbuff.h>
105#include <linux/delay.h>
1da177e4 106#include <linux/hdlc.h>
14cc3e2b 107#include <linux/mutex.h>
1da177e4
LT		 108
109/* Version */
110static const char version[] = "$Id: dscc4.c,v 1.173 2003/09/20 23:55:34 romieu Exp $ for Linux\n";
111static int debug;
112static int quartz;
113
114#ifdef CONFIG_DSCC4_PCI_RST
14cc3e2b 115static DEFINE_MUTEX(dscc4_mutex);
1da177e4
LT		 116static u32 dscc4_pci_config_store[16];
117#endif
118
119#define DRV_NAME "dscc4"
120
121#undef DSCC4_POLLING
122
123/* Module parameters */
124
125MODULE_AUTHOR("Maintainer: Francois Romieu <romieu@cogenit.fr>");
126MODULE_DESCRIPTION("Siemens PEB20534 PCI Controler");
127MODULE_LICENSE("GPL");
128module_param(debug, int, 0);
129MODULE_PARM_DESC(debug,"Enable/disable extra messages");
130module_param(quartz, int, 0);
131MODULE_PARM_DESC(quartz,"If present, on-board quartz frequency (Hz)");
132
133/* Structures */
134
135struct thingie {
136 int define;
137 u32 bits;
138};
139
140struct TxFD {
409cd63e
AV		 141 __le32 state;
142 __le32 next;
143 __le32 data;
144 __le32 complete;
1da177e4 145 u32 jiffies; /* Allows sizeof(TxFD) == sizeof(RxFD) + extra hack */
409cd63e
AV		 146 /* FWIW, datasheet calls that "dummy" and says that card
147 * never looks at it; neither does the driver */
1da177e4
LT		 148};
149
150struct RxFD {
409cd63e
AV		 151 __le32 state1;
152 __le32 next;
153 __le32 data;
154 __le32 state2;
155 __le32 end;
1da177e4
LT		 156};
157
158#define DUMMY_SKB_SIZE 64
159#define TX_LOW 8
160#define TX_RING_SIZE 32
161#define RX_RING_SIZE 32
162#define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct TxFD)
163#define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct RxFD)
164#define IRQ_RING_SIZE 64 /* Keep it a multiple of 32 */
165#define TX_TIMEOUT (HZ/10)
166#define DSCC4_HZ_MAX 33000000
167#define BRR_DIVIDER_MAX 64*0x00004000 /* Cf errata DS5 p.10 */
168#define dev_per_card 4
169#define SCC_REGISTERS_MAX 23 /* Cf errata DS5 p.4 */
170
171#define SOURCE_ID(flags) (((flags) >> 28) & 0x03)
172#define TO_SIZE(state) (((state) >> 16) & 0x1fff)
173
174/*
175 * Given the operating range of Linux HDLC, the 2 defines below could be
176 * made simpler. However they are a fine reminder for the limitations of
177 * the driver: it's better to stay < TxSizeMax and < RxSizeMax.
178 */
179#define TO_STATE_TX(len) cpu_to_le32(((len) & TxSizeMax) << 16)
180#define TO_STATE_RX(len) cpu_to_le32((RX_MAX(len) % RxSizeMax) << 16)
181#define RX_MAX(len) ((((len) >> 5) + 1) << 5) /* Cf RLCR */
182#define SCC_REG_START(dpriv) (SCC_START+(dpriv->dev_id)*SCC_OFFSET)
183
184struct dscc4_pci_priv {
409cd63e 185 __le32 *iqcfg;
1da177e4
LT		 186 int cfg_cur;
187 spinlock_t lock;
188 struct pci_dev *pdev;
189
190 struct dscc4_dev_priv *root;
191 dma_addr_t iqcfg_dma;
192 u32 xtal_hz;
193};
194
195struct dscc4_dev_priv {
196 struct sk_buff *rx_skbuff[RX_RING_SIZE];
197 struct sk_buff *tx_skbuff[TX_RING_SIZE];
198
199 struct RxFD *rx_fd;
200 struct TxFD *tx_fd;
409cd63e
AV		 201 __le32 *iqrx;
202 __le32 *iqtx;
1da177e4
LT		 203
204 /* FIXME: check all the volatile are required */
205 volatile u32 tx_current;
206 u32 rx_current;
207 u32 iqtx_current;
208 u32 iqrx_current;
209
210 volatile u32 tx_dirty;
211 volatile u32 ltda;
212 u32 rx_dirty;
213 u32 lrda;
214
215 dma_addr_t tx_fd_dma;
216 dma_addr_t rx_fd_dma;
217 dma_addr_t iqtx_dma;
218 dma_addr_t iqrx_dma;
219
220 u32 scc_regs[SCC_REGISTERS_MAX]; /* Cf errata DS5 p.4 */
221
222 struct timer_list timer;
223
224 struct dscc4_pci_priv *pci_priv;
225 spinlock_t lock;
226
227 int dev_id;
228 volatile u32 flags;
229 u32 timer_help;
230
231 unsigned short encoding;
232 unsigned short parity;
233 struct net_device *dev;
234 sync_serial_settings settings;
235 void __iomem *base_addr;
236 u32 __pad __attribute__ ((aligned (4)));
237};
238
239/* GLOBAL registers definitions */
240#define GCMDR 0x00
241#define GSTAR 0x04
242#define GMODE 0x08
243#define IQLENR0 0x0C
244#define IQLENR1 0x10
245#define IQRX0 0x14
246#define IQTX0 0x24
247#define IQCFG 0x3c
248#define FIFOCR1 0x44
249#define FIFOCR2 0x48
250#define FIFOCR3 0x4c
251#define FIFOCR4 0x34
252#define CH0CFG 0x50
253#define CH0BRDA 0x54
254#define CH0BTDA 0x58
255#define CH0FRDA 0x98
256#define CH0FTDA 0xb0
257#define CH0LRDA 0xc8
258#define CH0LTDA 0xe0
259
260/* SCC registers definitions */
261#define SCC_START 0x0100
262#define SCC_OFFSET 0x80
263#define CMDR 0x00
264#define STAR 0x04
265#define CCR0 0x08
266#define CCR1 0x0c
267#define CCR2 0x10
268#define BRR 0x2C
269#define RLCR 0x40
270#define IMR 0x54
271#define ISR 0x58
272
273#define GPDIR 0x0400
274#define GPDATA 0x0404
275#define GPIM 0x0408
276
277/* Bit masks */
278#define EncodingMask 0x00700000
279#define CrcMask 0x00000003
280
281#define IntRxScc0 0x10000000
282#define IntTxScc0 0x01000000
283
284#define TxPollCmd 0x00000400
285#define RxActivate 0x08000000
286#define MTFi 0x04000000
287#define Rdr 0x00400000
288#define Rdt 0x00200000
289#define Idr 0x00100000
290#define Idt 0x00080000
291#define TxSccRes 0x01000000
292#define RxSccRes 0x00010000
293#define TxSizeMax 0x1fff /* Datasheet DS1 - 11.1.1.1 */
294#define RxSizeMax 0x1ffc /* Datasheet DS1 - 11.1.2.1 */
295
296#define Ccr0ClockMask 0x0000003f
297#define Ccr1LoopMask 0x00000200
298#define IsrMask 0x000fffff
299#define BrrExpMask 0x00000f00
300#define BrrMultMask 0x0000003f
301#define EncodingMask 0x00700000
409cd63e 302#define Hold cpu_to_le32(0x40000000)
1da177e4
LT		 303#define SccBusy 0x10000000
304#define PowerUp 0x80000000
305#define Vis 0x00001000
306#define FrameOk (FrameVfr | FrameCrc)
307#define FrameVfr 0x80
308#define FrameRdo 0x40
309#define FrameCrc 0x20
310#define FrameRab 0x10
409cd63e
AV		 311#define FrameAborted cpu_to_le32(0x00000200)
312#define FrameEnd cpu_to_le32(0x80000000)
313#define DataComplete cpu_to_le32(0x40000000)
1da177e4
LT		 314#define LengthCheck 0x00008000
315#define SccEvt 0x02000000
316#define NoAck 0x00000200
317#define Action 0x00000001
409cd63e 318#define HiDesc cpu_to_le32(0x20000000)
1da177e4
LT		 319
320/* SCC events */
321#define RxEvt 0xf0000000
322#define TxEvt 0x0f000000
323#define Alls 0x00040000
324#define Xdu 0x00010000
325#define Cts 0x00004000
326#define Xmr 0x00002000
327#define Xpr 0x00001000
328#define Rdo 0x00000080
329#define Rfs 0x00000040
330#define Cd 0x00000004
331#define Rfo 0x00000002
332#define Flex 0x00000001
333
334/* DMA core events */
335#define Cfg 0x00200000
336#define Hi 0x00040000
337#define Fi 0x00020000
338#define Err 0x00010000
339#define Arf 0x00000002
340#define ArAck 0x00000001
341
342/* State flags */
343#define Ready 0x00000000
344#define NeedIDR 0x00000001
345#define NeedIDT 0x00000002
346#define RdoSet 0x00000004
347#define FakeReset 0x00000008
348
349/* Don't mask RDO. Ever. */
350#ifdef DSCC4_POLLING
351#define EventsMask 0xfffeef7f
352#else
353#define EventsMask 0xfffa8f7a
354#endif
355
356/* Functions prototypes */
357static void dscc4_rx_irq(struct dscc4_pci_priv *, struct dscc4_dev_priv *);
358static void dscc4_tx_irq(struct dscc4_pci_priv *, struct dscc4_dev_priv *);
359static int dscc4_found1(struct pci_dev *, void __iomem *ioaddr);
360static int dscc4_init_one(struct pci_dev *, const struct pci_device_id *ent);
361static int dscc4_open(struct net_device *);
362static int dscc4_start_xmit(struct sk_buff *, struct net_device *);
363static int dscc4_close(struct net_device *);
364static int dscc4_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
365static int dscc4_init_ring(struct net_device *);
366static void dscc4_release_ring(struct dscc4_dev_priv *);
367static void dscc4_timer(unsigned long);
368static void dscc4_tx_timeout(struct net_device *);
7d12e780 369static irqreturn_t dscc4_irq(int irq, void *dev_id);
1da177e4
LT		 370static int dscc4_hdlc_attach(struct net_device *, unsigned short, unsigned short);
371static int dscc4_set_iface(struct dscc4_dev_priv *, struct net_device *);
372#ifdef DSCC4_POLLING
373static int dscc4_tx_poll(struct dscc4_dev_priv *, struct net_device *);
374#endif
375
376static inline struct dscc4_dev_priv *dscc4_priv(struct net_device *dev)
377{
378 return dev_to_hdlc(dev)->priv;
379}
380
381static inline struct net_device *dscc4_to_dev(struct dscc4_dev_priv *p)
382{
383 return p->dev;
384}
385
386static void scc_patchl(u32 mask, u32 value, struct dscc4_dev_priv *dpriv,
387 struct net_device *dev, int offset)
388{
389 u32 state;
390
391 /* Cf scc_writel for concern regarding thread-safety */
392 state = dpriv->scc_regs[offset >> 2];
393 state &= ~mask;
394 state |= value;
395 dpriv->scc_regs[offset >> 2] = state;
396 writel(state, dpriv->base_addr + SCC_REG_START(dpriv) + offset);
397}
398
399static void scc_writel(u32 bits, struct dscc4_dev_priv *dpriv,
400 struct net_device *dev, int offset)
401{
402 /*
403 * Thread-UNsafe.
404 * As of 2002/02/16, there are no thread racing for access.
405 */
406 dpriv->scc_regs[offset >> 2] = bits;
407 writel(bits, dpriv->base_addr + SCC_REG_START(dpriv) + offset);
408}
409
410static inline u32 scc_readl(struct dscc4_dev_priv *dpriv, int offset)
411{
412 return dpriv->scc_regs[offset >> 2];
413}
414
415static u32 scc_readl_star(struct dscc4_dev_priv *dpriv, struct net_device *dev)
416{
417 /* Cf errata DS5 p.4 */
418 readl(dpriv->base_addr + SCC_REG_START(dpriv) + STAR);
419 return readl(dpriv->base_addr + SCC_REG_START(dpriv) + STAR);
420}
421
422static inline void dscc4_do_tx(struct dscc4_dev_priv *dpriv,
423 struct net_device *dev)
424{
425 dpriv->ltda = dpriv->tx_fd_dma +
426 ((dpriv->tx_current-1)%TX_RING_SIZE)*sizeof(struct TxFD);
427 writel(dpriv->ltda, dpriv->base_addr + CH0LTDA + dpriv->dev_id*4);
428 /* Flush posted writes *NOW* */
429 readl(dpriv->base_addr + CH0LTDA + dpriv->dev_id*4);
430}
431
432static inline void dscc4_rx_update(struct dscc4_dev_priv *dpriv,
433 struct net_device *dev)
434{
435 dpriv->lrda = dpriv->rx_fd_dma +
436 ((dpriv->rx_dirty - 1)%RX_RING_SIZE)*sizeof(struct RxFD);
437 writel(dpriv->lrda, dpriv->base_addr + CH0LRDA + dpriv->dev_id*4);
438}
439
440static inline unsigned int dscc4_tx_done(struct dscc4_dev_priv *dpriv)
441{
442 return dpriv->tx_current == dpriv->tx_dirty;
443}
444
445static inline unsigned int dscc4_tx_quiescent(struct dscc4_dev_priv *dpriv,
446 struct net_device *dev)
447{
448 return readl(dpriv->base_addr + CH0FTDA + dpriv->dev_id*4) == dpriv->ltda;
449}
450
7665a089
AB		 451static int state_check(u32 state, struct dscc4_dev_priv *dpriv,
452 struct net_device *dev, const char *msg)
1da177e4
LT		 453{
454 int ret = 0;
455
456 if (debug > 1) {
457 if (SOURCE_ID(state) != dpriv->dev_id) {
458 printk(KERN_DEBUG "%s (%s): Source Id=%d, state=%08x\n",
459 dev->name, msg, SOURCE_ID(state), state );
460 ret = -1;
461 }
462 if (state & 0x0df80c00) {
463 printk(KERN_DEBUG "%s (%s): state=%08x (UFO alert)\n",
464 dev->name, msg, state);
465 ret = -1;
466 }
467 }
468 return ret;
469}
470
7665a089
AB		 471static void dscc4_tx_print(struct net_device *dev,
472 struct dscc4_dev_priv *dpriv,
473 char *msg)
1da177e4
LT		 474{
475 printk(KERN_DEBUG "%s: tx_current=%02d tx_dirty=%02d (%s)\n",
476 dev->name, dpriv->tx_current, dpriv->tx_dirty, msg);
477}
478
479static void dscc4_release_ring(struct dscc4_dev_priv *dpriv)
480{
481 struct pci_dev *pdev = dpriv->pci_priv->pdev;
482 struct TxFD *tx_fd = dpriv->tx_fd;
483 struct RxFD *rx_fd = dpriv->rx_fd;
484 struct sk_buff **skbuff;
485 int i;
486
487 pci_free_consistent(pdev, TX_TOTAL_SIZE, tx_fd, dpriv->tx_fd_dma);
488 pci_free_consistent(pdev, RX_TOTAL_SIZE, rx_fd, dpriv->rx_fd_dma);
489
490 skbuff = dpriv->tx_skbuff;
491 for (i = 0; i < TX_RING_SIZE; i++) {
492 if (*skbuff) {
409cd63e
AV		 493 pci_unmap_single(pdev, le32_to_cpu(tx_fd->data),
494 (*skbuff)->len, PCI_DMA_TODEVICE);
1da177e4
LT		 495 dev_kfree_skb(*skbuff);
496 }
497 skbuff++;
498 tx_fd++;
499 }
500
501 skbuff = dpriv->rx_skbuff;
502 for (i = 0; i < RX_RING_SIZE; i++) {
503 if (*skbuff) {
409cd63e 504 pci_unmap_single(pdev, le32_to_cpu(rx_fd->data),
1da177e4
LT		 505 RX_MAX(HDLC_MAX_MRU), PCI_DMA_FROMDEVICE);
506 dev_kfree_skb(*skbuff);
507 }
508 skbuff++;
509 rx_fd++;
510 }
511}
512
7665a089
AB		 513static inline int try_get_rx_skb(struct dscc4_dev_priv *dpriv,
514 struct net_device *dev)
1da177e4
LT		 515{
516 unsigned int dirty = dpriv->rx_dirty%RX_RING_SIZE;
517 struct RxFD *rx_fd = dpriv->rx_fd + dirty;
518 const int len = RX_MAX(HDLC_MAX_MRU);
519 struct sk_buff *skb;
520 int ret = 0;
521
522 skb = dev_alloc_skb(len);
523 dpriv->rx_skbuff[dirty] = skb;
524 if (skb) {
525 skb->protocol = hdlc_type_trans(skb, dev);
409cd63e
AV		 526 rx_fd->data = cpu_to_le32(pci_map_single(dpriv->pci_priv->pdev,
527 skb->data, len, PCI_DMA_FROMDEVICE));
1da177e4 528 } else {
409cd63e 529 rx_fd->data = 0;
1da177e4
LT		 530 ret = -1;
531 }
532 return ret;
533}
534
535/*
536 * IRQ/thread/whatever safe
537 */
538static int dscc4_wait_ack_cec(struct dscc4_dev_priv *dpriv,
539 struct net_device *dev, char *msg)
540{
541 s8 i = 0;
542
543 do {
544 if (!(scc_readl_star(dpriv, dev) & SccBusy)) {
545 printk(KERN_DEBUG "%s: %s ack (%d try)\n", dev->name,
546 msg, i);
547 goto done;
548 }
3173c890 549 schedule_timeout_uninterruptible(10);
1da177e4
LT		 550 rmb();
551 } while (++i > 0);
552 printk(KERN_ERR "%s: %s timeout\n", dev->name, msg);
553done:
554 return (i >= 0) ? i : -EAGAIN;
555}
556
557static int dscc4_do_action(struct net_device *dev, char *msg)
558{
559 void __iomem *ioaddr = dscc4_priv(dev)->base_addr;
560 s16 i = 0;
561
562 writel(Action, ioaddr + GCMDR);
563 ioaddr += GSTAR;
564 do {
565 u32 state = readl(ioaddr);
566
567 if (state & ArAck) {
568 printk(KERN_DEBUG "%s: %s ack\n", dev->name, msg);
569 writel(ArAck, ioaddr);
570 goto done;
571 } else if (state & Arf) {
572 printk(KERN_ERR "%s: %s failed\n", dev->name, msg);
573 writel(Arf, ioaddr);
574 i = -1;
575 goto done;
576 }
577 rmb();
578 } while (++i > 0);
579 printk(KERN_ERR "%s: %s timeout\n", dev->name, msg);
580done:
581 return i;
582}
583
584static inline int dscc4_xpr_ack(struct dscc4_dev_priv *dpriv)
585{
586 int cur = dpriv->iqtx_current%IRQ_RING_SIZE;
587 s8 i = 0;
588
589 do {
590 if (!(dpriv->flags & (NeedIDR | NeedIDT)) ||
409cd63e 591 (dpriv->iqtx[cur] & cpu_to_le32(Xpr)))
1da177e4
LT		 592 break;
593 smp_rmb();
3173c890 594 schedule_timeout_uninterruptible(10);
1da177e4
LT		 595 } while (++i > 0);
596
597 return (i >= 0 ) ? i : -EAGAIN;
598}
599
600#if 0 /* dscc4_{rx/tx}_reset are both unreliable - more tweak needed */
601static void dscc4_rx_reset(struct dscc4_dev_priv *dpriv, struct net_device *dev)
602{
603 unsigned long flags;
604
605 spin_lock_irqsave(&dpriv->pci_priv->lock, flags);
606 /* Cf errata DS5 p.6 */
607 writel(0x00000000, dpriv->base_addr + CH0LRDA + dpriv->dev_id*4);
608 scc_patchl(PowerUp, 0, dpriv, dev, CCR0);
609 readl(dpriv->base_addr + CH0LRDA + dpriv->dev_id*4);
610 writel(MTFi|Rdr, dpriv->base_addr + dpriv->dev_id*0x0c + CH0CFG);
611 writel(Action, dpriv->base_addr + GCMDR);
612 spin_unlock_irqrestore(&dpriv->pci_priv->lock, flags);
613}
614
615#endif
616
617#if 0
618static void dscc4_tx_reset(struct dscc4_dev_priv *dpriv, struct net_device *dev)
619{
620 u16 i = 0;
621
622 /* Cf errata DS5 p.7 */
623 scc_patchl(PowerUp, 0, dpriv, dev, CCR0);
624 scc_writel(0x00050000, dpriv, dev, CCR2);
625 /*
626 * Must be longer than the time required to fill the fifo.
627 */
628 while (!dscc4_tx_quiescent(dpriv, dev) && ++i) {
629 udelay(1);
630 wmb();
631 }
632
633 writel(MTFi|Rdt, dpriv->base_addr + dpriv->dev_id*0x0c + CH0CFG);
634 if (dscc4_do_action(dev, "Rdt") < 0)
635 printk(KERN_ERR "%s: Tx reset failed\n", dev->name);
636}
637#endif
638
639/* TODO: (ab)use this function to refill a completely depleted RX ring. */
640static inline void dscc4_rx_skb(struct dscc4_dev_priv *dpriv,
641 struct net_device *dev)
642{
643 struct RxFD *rx_fd = dpriv->rx_fd + dpriv->rx_current%RX_RING_SIZE;
1da177e4
LT		 644 struct pci_dev *pdev = dpriv->pci_priv->pdev;
645 struct sk_buff *skb;
646 int pkt_len;
647
648 skb = dpriv->rx_skbuff[dpriv->rx_current++%RX_RING_SIZE];
649 if (!skb) {
b39d66a8 650 printk(KERN_DEBUG "%s: skb=0 (%s)\n", dev->name, __func__);
1da177e4
LT		 651 goto refill;
652 }
409cd63e
AV		 653 pkt_len = TO_SIZE(le32_to_cpu(rx_fd->state2));
654 pci_unmap_single(pdev, le32_to_cpu(rx_fd->data),
655 RX_MAX(HDLC_MAX_MRU), PCI_DMA_FROMDEVICE);
1da177e4 656 if ((skb->data[--pkt_len] & FrameOk) == FrameOk) {
198191c4
KH		 657 dev->stats.rx_packets++;
658 dev->stats.rx_bytes += pkt_len;
1da177e4
LT		 659 skb_put(skb, pkt_len);
660 if (netif_running(dev))
661 skb->protocol = hdlc_type_trans(skb, dev);
1da177e4
LT		 662 netif_rx(skb);
663 } else {
664 if (skb->data[pkt_len] & FrameRdo)
198191c4 665 dev->stats.rx_fifo_errors++;
1da177e4 666 else if (!(skb->data[pkt_len] | ~FrameCrc))
198191c4 667 dev->stats.rx_crc_errors++;
1da177e4 668 else if (!(skb->data[pkt_len] | ~(FrameVfr | FrameRab)))
198191c4 669 dev->stats.rx_length_errors++;
1da177e4 670 else
198191c4 671 dev->stats.rx_errors++;
1da177e4
LT		 672 dev_kfree_skb_irq(skb);
673 }
674refill:
675 while ((dpriv->rx_dirty - dpriv->rx_current) % RX_RING_SIZE) {
676 if (try_get_rx_skb(dpriv, dev) < 0)
677 break;
678 dpriv->rx_dirty++;
679 }
680 dscc4_rx_update(dpriv, dev);
681 rx_fd->state2 = 0x00000000;
409cd63e 682 rx_fd->end = cpu_to_le32(0xbabeface);
1da177e4
LT		 683}
684
685static void dscc4_free1(struct pci_dev *pdev)
686{
687 struct dscc4_pci_priv *ppriv;
688 struct dscc4_dev_priv *root;
689 int i;
690
691 ppriv = pci_get_drvdata(pdev);
692 root = ppriv->root;
693
694 for (i = 0; i < dev_per_card; i++)
695 unregister_hdlc_device(dscc4_to_dev(root + i));
696
697 pci_set_drvdata(pdev, NULL);
698
699 for (i = 0; i < dev_per_card; i++)
700 free_netdev(root[i].dev);
701 kfree(root);
702 kfree(ppriv);
703}
704
705static int __devinit dscc4_init_one(struct pci_dev *pdev,
706 const struct pci_device_id *ent)
707{
708 struct dscc4_pci_priv *priv;
709 struct dscc4_dev_priv *dpriv;
710 void __iomem *ioaddr;
711 int i, rc;
712
713 printk(KERN_DEBUG "%s", version);
714
715 rc = pci_enable_device(pdev);
716 if (rc < 0)
717 goto out;
718
719 rc = pci_request_region(pdev, 0, "registers");
720 if (rc < 0) {
721 printk(KERN_ERR "%s: can't reserve MMIO region (regs)\n",
722 DRV_NAME);
723 goto err_disable_0;
724 }
725 rc = pci_request_region(pdev, 1, "LBI interface");
726 if (rc < 0) {
727 printk(KERN_ERR "%s: can't reserve MMIO region (lbi)\n",
728 DRV_NAME);
729 goto err_free_mmio_region_1;
730 }
731
275f165f 732 ioaddr = pci_ioremap_bar(pdev, 0);
1da177e4 733 if (!ioaddr) {
7c7459d1
GKH		 734 printk(KERN_ERR "%s: cannot remap MMIO region %llx @ %llx\n",
735 DRV_NAME, (unsigned long long)pci_resource_len(pdev, 0),
736 (unsigned long long)pci_resource_start(pdev, 0));
1da177e4
LT		 737 rc = -EIO;
738 goto err_free_mmio_regions_2;
739 }
7c7459d1
GKH		 740 printk(KERN_DEBUG "Siemens DSCC4, MMIO at %#llx (regs), %#llx (lbi), IRQ %d\n",
741 (unsigned long long)pci_resource_start(pdev, 0),
742 (unsigned long long)pci_resource_start(pdev, 1), pdev->irq);
1da177e4
LT		 743
744 /* Cf errata DS5 p.2 */
745 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xf8);
746 pci_set_master(pdev);
747
748 rc = dscc4_found1(pdev, ioaddr);
749 if (rc < 0)
750 goto err_iounmap_3;
751
752 priv = pci_get_drvdata(pdev);
753
1fb9df5d 754 rc = request_irq(pdev->irq, dscc4_irq, IRQF_SHARED, DRV_NAME, priv->root);
1da177e4
LT		 755 if (rc < 0) {
756 printk(KERN_WARNING "%s: IRQ %d busy\n", DRV_NAME, pdev->irq);
757 goto err_release_4;
758 }
759
760 /* power up/little endian/dma core controlled via lrda/ltda */
761 writel(0x00000001, ioaddr + GMODE);
762 /* Shared interrupt queue */
763 {
764 u32 bits;
765
766 bits = (IRQ_RING_SIZE >> 5) - 1;
767 bits |= bits << 4;
768 bits |= bits << 8;
769 bits |= bits << 16;
770 writel(bits, ioaddr + IQLENR0);
771 }
772 /* Global interrupt queue */
773 writel((u32)(((IRQ_RING_SIZE >> 5) - 1) << 20), ioaddr + IQLENR1);
409cd63e
AV		 774 priv->iqcfg = (__le32 *) pci_alloc_consistent(pdev,
775 IRQ_RING_SIZE*sizeof(__le32), &priv->iqcfg_dma);
1da177e4
LT		 776 if (!priv->iqcfg)
777 goto err_free_irq_5;
778 writel(priv->iqcfg_dma, ioaddr + IQCFG);
779
780 rc = -ENOMEM;
781
782 /*
783 * SCC 0-3 private rx/tx irq structures
784 * IQRX/TXi needs to be set soon. Learned it the hard way...
785 */
786 for (i = 0; i < dev_per_card; i++) {
787 dpriv = priv->root + i;
409cd63e 788 dpriv->iqtx = (__le32 *) pci_alloc_consistent(pdev,
1da177e4
LT		 789 IRQ_RING_SIZE*sizeof(u32), &dpriv->iqtx_dma);
790 if (!dpriv->iqtx)
791 goto err_free_iqtx_6;
792 writel(dpriv->iqtx_dma, ioaddr + IQTX0 + i*4);
793 }
794 for (i = 0; i < dev_per_card; i++) {
795 dpriv = priv->root + i;
409cd63e 796 dpriv->iqrx = (__le32 *) pci_alloc_consistent(pdev,
1da177e4
LT		 797 IRQ_RING_SIZE*sizeof(u32), &dpriv->iqrx_dma);
798 if (!dpriv->iqrx)
799 goto err_free_iqrx_7;
800 writel(dpriv->iqrx_dma, ioaddr + IQRX0 + i*4);
801 }
802
803 /* Cf application hint. Beware of hard-lock condition on threshold. */
804 writel(0x42104000, ioaddr + FIFOCR1);
805 //writel(0x9ce69800, ioaddr + FIFOCR2);
806 writel(0xdef6d800, ioaddr + FIFOCR2);
807 //writel(0x11111111, ioaddr + FIFOCR4);
808 writel(0x18181818, ioaddr + FIFOCR4);
809 // FIXME: should depend on the chipset revision
810 writel(0x0000000e, ioaddr + FIFOCR3);
811
812 writel(0xff200001, ioaddr + GCMDR);
813
814 rc = 0;
815out:
816 return rc;
817
818err_free_iqrx_7:
819 while (--i >= 0) {
820 dpriv = priv->root + i;
821 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
822 dpriv->iqrx, dpriv->iqrx_dma);
823 }
824 i = dev_per_card;
825err_free_iqtx_6:
826 while (--i >= 0) {
827 dpriv = priv->root + i;
828 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
829 dpriv->iqtx, dpriv->iqtx_dma);
830 }
831 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32), priv->iqcfg,
832 priv->iqcfg_dma);
833err_free_irq_5:
834 free_irq(pdev->irq, priv->root);
835err_release_4:
836 dscc4_free1(pdev);
837err_iounmap_3:
838 iounmap (ioaddr);
839err_free_mmio_regions_2:
840 pci_release_region(pdev, 1);
841err_free_mmio_region_1:
842 pci_release_region(pdev, 0);
843err_disable_0:
844 pci_disable_device(pdev);
845 goto out;
846};
847
848/*
849 * Let's hope the default values are decent enough to protect my
850 * feet from the user's gun - Ueimor
851 */
852static void dscc4_init_registers(struct dscc4_dev_priv *dpriv,
853 struct net_device *dev)
854{
855 /* No interrupts, SCC core disabled. Let's relax */
856 scc_writel(0x00000000, dpriv, dev, CCR0);
857
858 scc_writel(LengthCheck | (HDLC_MAX_MRU >> 5), dpriv, dev, RLCR);
859
860 /*
861 * No address recognition/crc-CCITT/cts enabled
862 * Shared flags transmission disabled - cf errata DS5 p.11
863 * Carrier detect disabled - cf errata p.14
864 * FIXME: carrier detection/polarity may be handled more gracefully.
865 */
866 scc_writel(0x02408000, dpriv, dev, CCR1);
867
868 /* crc not forwarded - Cf errata DS5 p.11 */
869 scc_writel(0x00050008 & ~RxActivate, dpriv, dev, CCR2);
870 // crc forwarded
871 //scc_writel(0x00250008 & ~RxActivate, dpriv, dev, CCR2);
872}
873
874static inline int dscc4_set_quartz(struct dscc4_dev_priv *dpriv, int hz)
875{
876 int ret = 0;
877
878 if ((hz < 0) || (hz > DSCC4_HZ_MAX))
879 ret = -EOPNOTSUPP;
880 else
881 dpriv->pci_priv->xtal_hz = hz;
882
883 return ret;
884}
885
991990a1
KH		 886static const struct net_device_ops dscc4_ops = {
887 .ndo_open = dscc4_open,
888 .ndo_stop = dscc4_close,
889 .ndo_change_mtu = hdlc_change_mtu,
890 .ndo_start_xmit = hdlc_start_xmit,
891 .ndo_do_ioctl = dscc4_ioctl,
892 .ndo_tx_timeout = dscc4_tx_timeout,
893};
894
1da177e4
LT		 895static int dscc4_found1(struct pci_dev *pdev, void __iomem *ioaddr)
896{
897 struct dscc4_pci_priv *ppriv;
898 struct dscc4_dev_priv *root;
899 int i, ret = -ENOMEM;
900
dd00cc48 901 root = kcalloc(dev_per_card, sizeof(*root), GFP_KERNEL);
1da177e4
LT		 902 if (!root) {
903 printk(KERN_ERR "%s: can't allocate data\n", DRV_NAME);
904 goto err_out;
905 }
1da177e4
LT		 906
907 for (i = 0; i < dev_per_card; i++) {
908 root[i].dev = alloc_hdlcdev(root + i);
909 if (!root[i].dev)
910 goto err_free_dev;
911 }
912
dd00cc48 913 ppriv = kzalloc(sizeof(*ppriv), GFP_KERNEL);
1da177e4
LT		 914 if (!ppriv) {
915 printk(KERN_ERR "%s: can't allocate private data\n", DRV_NAME);
916 goto err_free_dev;
917 }
1da177e4
LT		 918
919 ppriv->root = root;
920 spin_lock_init(&ppriv->lock);
921
922 for (i = 0; i < dev_per_card; i++) {
923 struct dscc4_dev_priv *dpriv = root + i;
924 struct net_device *d = dscc4_to_dev(dpriv);
925 hdlc_device *hdlc = dev_to_hdlc(d);
926
927 d->base_addr = (unsigned long)ioaddr;
1da177e4 928 d->irq = pdev->irq;
991990a1 929 d->netdev_ops = &dscc4_ops;
1da177e4 930 d->watchdog_timeo = TX_TIMEOUT;
1da177e4
LT		 931 SET_NETDEV_DEV(d, &pdev->dev);
932
933 dpriv->dev_id = i;
934 dpriv->pci_priv = ppriv;
935 dpriv->base_addr = ioaddr;
936 spin_lock_init(&dpriv->lock);
937
938 hdlc->xmit = dscc4_start_xmit;
939 hdlc->attach = dscc4_hdlc_attach;
940
941 dscc4_init_registers(dpriv, d);
942 dpriv->parity = PARITY_CRC16_PR0_CCITT;
943 dpriv->encoding = ENCODING_NRZ;
944
945 ret = dscc4_init_ring(d);
946 if (ret < 0)
947 goto err_unregister;
948
949 ret = register_hdlc_device(d);
950 if (ret < 0) {
951 printk(KERN_ERR "%s: unable to register\n", DRV_NAME);
952 dscc4_release_ring(dpriv);
953 goto err_unregister;
954 }
955 }
956
957 ret = dscc4_set_quartz(root, quartz);
958 if (ret < 0)
959 goto err_unregister;
960
961 pci_set_drvdata(pdev, ppriv);
962 return ret;
963
964err_unregister:
965 while (i-- > 0) {
966 dscc4_release_ring(root + i);
967 unregister_hdlc_device(dscc4_to_dev(root + i));
968 }
969 kfree(ppriv);
970 i = dev_per_card;
971err_free_dev:
972 while (i-- > 0)
973 free_netdev(root[i].dev);
974 kfree(root);
975err_out:
976 return ret;
977};
978
979/* FIXME: get rid of the unneeded code */
980static void dscc4_timer(unsigned long data)
981{
982 struct net_device *dev = (struct net_device *)data;
983 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
984// struct dscc4_pci_priv *ppriv;
985
986 goto done;
987done:
988 dpriv->timer.expires = jiffies + TX_TIMEOUT;
989 add_timer(&dpriv->timer);
990}
991
992static void dscc4_tx_timeout(struct net_device *dev)
993{
994 /* FIXME: something is missing there */
995}
996
997static int dscc4_loopback_check(struct dscc4_dev_priv *dpriv)
998{
999 sync_serial_settings *settings = &dpriv->settings;
1000
1001 if (settings->loopback && (settings->clock_type != CLOCK_INT)) {
1002 struct net_device *dev = dscc4_to_dev(dpriv);
1003
1004 printk(KERN_INFO "%s: loopback requires clock\n", dev->name);
1005 return -1;
1006 }
1007 return 0;
1008}
1009
1010#ifdef CONFIG_DSCC4_PCI_RST
1011/*
1012 * Some DSCC4-based cards wires the GPIO port and the PCI #RST pin together
1013 * so as to provide a safe way to reset the asic while not the whole machine
1014 * rebooting.
1015 *
1016 * This code doesn't need to be efficient. Keep It Simple
1017 */
1018static void dscc4_pci_reset(struct pci_dev *pdev, void __iomem *ioaddr)
1019{
1020 int i;
1021
14cc3e2b 1022 mutex_lock(&dscc4_mutex);
1da177e4
LT		 1023 for (i = 0; i < 16; i++)
1024 pci_read_config_dword(pdev, i << 2, dscc4_pci_config_store + i);
1025
1026 /* Maximal LBI clock divider (who cares ?) and whole GPIO range. */
1027 writel(0x001c0000, ioaddr + GMODE);
1028 /* Configure GPIO port as output */
1029 writel(0x0000ffff, ioaddr + GPDIR);
1030 /* Disable interruption */
1031 writel(0x0000ffff, ioaddr + GPIM);
1032
1033 writel(0x0000ffff, ioaddr + GPDATA);
1034 writel(0x00000000, ioaddr + GPDATA);
1035
1036 /* Flush posted writes */
1037 readl(ioaddr + GSTAR);
1038
3173c890 1039 schedule_timeout_uninterruptible(10);
1da177e4
LT		 1040
1041 for (i = 0; i < 16; i++)
1042 pci_write_config_dword(pdev, i << 2, dscc4_pci_config_store[i]);
14cc3e2b 1043 mutex_unlock(&dscc4_mutex);
1da177e4
LT		 1044}
1045#else
1046#define dscc4_pci_reset(pdev,ioaddr) do {} while (0)
1047#endif /* CONFIG_DSCC4_PCI_RST */
1048
1049static int dscc4_open(struct net_device *dev)
1050{
1051 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1052 struct dscc4_pci_priv *ppriv;
1053 int ret = -EAGAIN;
1054
991990a1 1055 if ((dscc4_loopback_check(dpriv) < 0))
1da177e4
LT		 1056 goto err;
1057
1058 if ((ret = hdlc_open(dev)))
1059 goto err;
1060
1061 ppriv = dpriv->pci_priv;
1062
1063 /*
1064 * Due to various bugs, there is no way to reliably reset a
1065 * specific port (manufacturer's dependant special PCI #RST wiring
1066 * apart: it affects all ports). Thus the device goes in the best
1067 * silent mode possible at dscc4_close() time and simply claims to
1068 * be up if it's opened again. It still isn't possible to change
1069 * the HDLC configuration without rebooting but at least the ports
1070 * can be up/down ifconfig'ed without killing the host.
1071 */
1072 if (dpriv->flags & FakeReset) {
1073 dpriv->flags &= ~FakeReset;
1074 scc_patchl(0, PowerUp, dpriv, dev, CCR0);
1075 scc_patchl(0, 0x00050000, dpriv, dev, CCR2);
1076 scc_writel(EventsMask, dpriv, dev, IMR);
1077 printk(KERN_INFO "%s: up again.\n", dev->name);
1078 goto done;
1079 }
1080
1081 /* IDT+IDR during XPR */
1082 dpriv->flags = NeedIDR | NeedIDT;
1083
1084 scc_patchl(0, PowerUp | Vis, dpriv, dev, CCR0);
1085
1086 /*
1087 * The following is a bit paranoid...
1088 *
1089 * NB: the datasheet "...CEC will stay active if the SCC is in
1090 * power-down mode or..." and CCR2.RAC = 1 are two different
1091 * situations.
1092 */
1093 if (scc_readl_star(dpriv, dev) & SccBusy) {
1094 printk(KERN_ERR "%s busy. Try later\n", dev->name);
1095 ret = -EAGAIN;
1096 goto err_out;
1097 } else
1098 printk(KERN_INFO "%s: available. Good\n", dev->name);
1099
1100 scc_writel(EventsMask, dpriv, dev, IMR);
1101
1102 /* Posted write is flushed in the wait_ack loop */
1103 scc_writel(TxSccRes | RxSccRes, dpriv, dev, CMDR);
1104
1105 if ((ret = dscc4_wait_ack_cec(dpriv, dev, "Cec")) < 0)
1106 goto err_disable_scc_events;
1107
1108 /*
1109 * I would expect XPR near CE completion (before ? after ?).
1110 * At worst, this code won't see a late XPR and people
1111 * will have to re-issue an ifconfig (this is harmless).
1112 * WARNING, a really missing XPR usually means a hardware
1113 * reset is needed. Suggestions anyone ?
1114 */
1115 if ((ret = dscc4_xpr_ack(dpriv)) < 0) {
1116 printk(KERN_ERR "%s: %s timeout\n", DRV_NAME, "XPR");
1117 goto err_disable_scc_events;
1118 }
1119
1120 if (debug > 2)
1121 dscc4_tx_print(dev, dpriv, "Open");
1122
1123done:
1124 netif_start_queue(dev);
1125
1126 init_timer(&dpriv->timer);
1127 dpriv->timer.expires = jiffies + 10*HZ;
1128 dpriv->timer.data = (unsigned long)dev;
1129 dpriv->timer.function = &dscc4_timer;
1130 add_timer(&dpriv->timer);
1131 netif_carrier_on(dev);
1132
1133 return 0;
1134
1135err_disable_scc_events:
1136 scc_writel(0xffffffff, dpriv, dev, IMR);
1137 scc_patchl(PowerUp | Vis, 0, dpriv, dev, CCR0);
1138err_out:
1139 hdlc_close(dev);
1140err:
1141 return ret;
1142}
1143
1144#ifdef DSCC4_POLLING
1145static int dscc4_tx_poll(struct dscc4_dev_priv *dpriv, struct net_device *dev)
1146{
1147 /* FIXME: it's gonna be easy (TM), for sure */
1148}
1149#endif /* DSCC4_POLLING */
1150
1151static int dscc4_start_xmit(struct sk_buff *skb, struct net_device *dev)
1152{
1153 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1154 struct dscc4_pci_priv *ppriv = dpriv->pci_priv;
1155 struct TxFD *tx_fd;
1156 int next;
1157
1158 next = dpriv->tx_current%TX_RING_SIZE;
1159 dpriv->tx_skbuff[next] = skb;
1160 tx_fd = dpriv->tx_fd + next;
1161 tx_fd->state = FrameEnd | TO_STATE_TX(skb->len);
409cd63e
AV		 1162 tx_fd->data = cpu_to_le32(pci_map_single(ppriv->pdev, skb->data, skb->len,
1163 PCI_DMA_TODEVICE));
1da177e4
LT		 1164 tx_fd->complete = 0x00000000;
1165 tx_fd->jiffies = jiffies;
1166 mb();
1167
1168#ifdef DSCC4_POLLING
1169 spin_lock(&dpriv->lock);
1170 while (dscc4_tx_poll(dpriv, dev));
1171 spin_unlock(&dpriv->lock);
1172#endif
1173
1174 dev->trans_start = jiffies;
1175
1176 if (debug > 2)
1177 dscc4_tx_print(dev, dpriv, "Xmit");
1178 /* To be cleaned(unsigned int)/optimized. Later, ok ? */
1179 if (!((++dpriv->tx_current - dpriv->tx_dirty)%TX_RING_SIZE))
1180 netif_stop_queue(dev);
1181
1182 if (dscc4_tx_quiescent(dpriv, dev))
1183 dscc4_do_tx(dpriv, dev);
1184
1185 return 0;
1186}
1187
1188static int dscc4_close(struct net_device *dev)
1189{
1190 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1191
1192 del_timer_sync(&dpriv->timer);
1193 netif_stop_queue(dev);
1194
1195 scc_patchl(PowerUp | Vis, 0, dpriv, dev, CCR0);
1196 scc_patchl(0x00050000, 0, dpriv, dev, CCR2);
1197 scc_writel(0xffffffff, dpriv, dev, IMR);
1198
1199 dpriv->flags |= FakeReset;
1200
1201 hdlc_close(dev);
1202
1203 return 0;
1204}
1205
1206static inline int dscc4_check_clock_ability(int port)
1207{
1208 int ret = 0;
1209
1210#ifdef CONFIG_DSCC4_PCISYNC
1211 if (port >= 2)
1212 ret = -1;
1213#endif
1214 return ret;
1215}
1216
1217/*
1218 * DS1 p.137: "There are a total of 13 different clocking modes..."
1219 * ^^
1220 * Design choices:
1221 * - by default, assume a clock is provided on pin RxClk/TxClk (clock mode 0a).
1222 * Clock mode 3b _should_ work but the testing seems to make this point
1223 * dubious (DIY testing requires setting CCR0 at 0x00000033).
1224 * This is supposed to provide least surprise "DTE like" behavior.
1225 * - if line rate is specified, clocks are assumed to be locally generated.
1226 * A quartz must be available (on pin XTAL1). Modes 6b/7b are used. Choosing
1227 * between these it automagically done according on the required frequency
1228 * scaling. Of course some rounding may take place.
1229 * - no high speed mode (40Mb/s). May be trivial to do but I don't have an
1230 * appropriate external clocking device for testing.
1231 * - no time-slot/clock mode 5: shameless lazyness.
1232 *
1233 * The clock signals wiring can be (is ?) manufacturer dependant. Good luck.
1234 *
1235 * BIG FAT WARNING: if the device isn't provided enough clocking signal, it
1236 * won't pass the init sequence. For example, straight back-to-back DTE without
1237 * external clock will fail when dscc4_open() (<- 'ifconfig hdlcx xxx') is
1238 * called.
1239 *
1240 * Typos lurk in datasheet (missing divier in clock mode 7a figure 51 p.153
1241 * DS0 for example)
1242 *
1243 * Clock mode related bits of CCR0:
1244 * +------------ TOE: output TxClk (0b/2b/3a/3b/6b/7a/7b only)
1245 * | +---------- SSEL: sub-mode select 0 -> a, 1 -> b
1246 * | | +-------- High Speed: say 0
1247 * | | | +-+-+-- Clock Mode: 0..7
1248 * | | | | | |
1249 * -+-+-+-+-+-+-+-+
1250 * x|x|5|4|3|2|1|0| lower bits
1251 *
1252 * Division factor of BRR: k = (N+1)x2^M (total divider = 16xk in mode 6b)
1253 * +-+-+-+------------------ M (0..15)
1254 * | | | | +-+-+-+-+-+-- N (0..63)
1255 * 0 0 0 0 | | | | 0 0 | | | | | |
1256 * ...-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
1257 * f|e|d|c|b|a|9|8|7|6|5|4|3|2|1|0| lower bits
1258 *
1259 */
1260static int dscc4_set_clock(struct net_device *dev, u32 *bps, u32 *state)
1261{
1262 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1263 int ret = -1;
1264 u32 brr;
1265
1266 *state &= ~Ccr0ClockMask;
1267 if (*bps) { /* Clock generated - required for DCE */
1268 u32 n = 0, m = 0, divider;
1269 int xtal;
1270
1271 xtal = dpriv->pci_priv->xtal_hz;
1272 if (!xtal)
1273 goto done;
1274 if (dscc4_check_clock_ability(dpriv->dev_id) < 0)
1275 goto done;
1276 divider = xtal / *bps;
1277 if (divider > BRR_DIVIDER_MAX) {
1278 divider >>= 4;
1279 *state |= 0x00000036; /* Clock mode 6b (BRG/16) */
1280 } else
1281 *state |= 0x00000037; /* Clock mode 7b (BRG) */
1282 if (divider >> 22) {
1283 n = 63;
1284 m = 15;
1285 } else if (divider) {
1286 /* Extraction of the 6 highest weighted bits */
1287 m = 0;
1288 while (0xffffffc0 & divider) {
1289 m++;
1290 divider >>= 1;
1291 }
1292 n = divider;
1293 }
1294 brr = (m << 8) | n;
1295 divider = n << m;
1296 if (!(*state & 0x00000001)) /* ?b mode mask => clock mode 6b */
1297 divider <<= 4;
1298 *bps = xtal / divider;
1299 } else {
1300 /*
1301 * External clock - DTE
1302 * "state" already reflects Clock mode 0a (CCR0 = 0xzzzzzz00).
1303 * Nothing more to be done
1304 */
1305 brr = 0;
1306 }
1307 scc_writel(brr, dpriv, dev, BRR);
1308 ret = 0;
1309done:
1310 return ret;
1311}
1312
1313static int dscc4_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1314{
1315 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1316 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1317 const size_t size = sizeof(dpriv->settings);
1318 int ret = 0;
1319
1320 if (dev->flags & IFF_UP)
1321 return -EBUSY;
1322
1323 if (cmd != SIOCWANDEV)
1324 return -EOPNOTSUPP;
1325
1326 switch(ifr->ifr_settings.type) {
1327 case IF_GET_IFACE:
1328 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1329 if (ifr->ifr_settings.size < size) {
1330 ifr->ifr_settings.size = size; /* data size wanted */
1331 return -ENOBUFS;
1332 }
1333 if (copy_to_user(line, &dpriv->settings, size))
1334 return -EFAULT;
1335 break;
1336
1337 case IF_IFACE_SYNC_SERIAL:
1338 if (!capable(CAP_NET_ADMIN))
1339 return -EPERM;
1340
1341 if (dpriv->flags & FakeReset) {
1342 printk(KERN_INFO "%s: please reset the device"
1343 " before this command\n", dev->name);
1344 return -EPERM;
1345 }
1346 if (copy_from_user(&dpriv->settings, line, size))
1347 return -EFAULT;
1348 ret = dscc4_set_iface(dpriv, dev);
1349 break;
1350
1351 default:
1352 ret = hdlc_ioctl(dev, ifr, cmd);
1353 break;
1354 }
1355
1356 return ret;
1357}
1358
1359static int dscc4_match(struct thingie *p, int value)
1360{
1361 int i;
1362
1363 for (i = 0; p[i].define != -1; i++) {
1364 if (value == p[i].define)
1365 break;
1366 }
1367 if (p[i].define == -1)
1368 return -1;
1369 else
1370 return i;
1371}
1372
1373static int dscc4_clock_setting(struct dscc4_dev_priv *dpriv,
1374 struct net_device *dev)
1375{
1376 sync_serial_settings *settings = &dpriv->settings;
1377 int ret = -EOPNOTSUPP;
1378 u32 bps, state;
1379
1380 bps = settings->clock_rate;
1381 state = scc_readl(dpriv, CCR0);
1382 if (dscc4_set_clock(dev, &bps, &state) < 0)
1383 goto done;
1384 if (bps) { /* DCE */
1385 printk(KERN_DEBUG "%s: generated RxClk (DCE)\n", dev->name);
1386 if (settings->clock_rate != bps) {
1387 printk(KERN_DEBUG "%s: clock adjusted (%08d -> %08d)\n",
1388 dev->name, settings->clock_rate, bps);
1389 settings->clock_rate = bps;
1390 }
1391 } else { /* DTE */
1392 state |= PowerUp | Vis;
1393 printk(KERN_DEBUG "%s: external RxClk (DTE)\n", dev->name);
1394 }
1395 scc_writel(state, dpriv, dev, CCR0);
1396 ret = 0;
1397done:
1398 return ret;
1399}
1400
1401static int dscc4_encoding_setting(struct dscc4_dev_priv *dpriv,
1402 struct net_device *dev)
1403{
1404 struct thingie encoding[] = {
1405 { ENCODING_NRZ, 0x00000000 },
1406 { ENCODING_NRZI, 0x00200000 },
1407 { ENCODING_FM_MARK, 0x00400000 },
1408 { ENCODING_FM_SPACE, 0x00500000 },
1409 { ENCODING_MANCHESTER, 0x00600000 },
1410 { -1, 0}
1411 };
1412 int i, ret = 0;
1413
1414 i = dscc4_match(encoding, dpriv->encoding);
1415 if (i >= 0)
1416 scc_patchl(EncodingMask, encoding[i].bits, dpriv, dev, CCR0);
1417 else
1418 ret = -EOPNOTSUPP;
1419 return ret;
1420}
1421
1422static int dscc4_loopback_setting(struct dscc4_dev_priv *dpriv,
1423 struct net_device *dev)
1424{
1425 sync_serial_settings *settings = &dpriv->settings;
1426 u32 state;
1427
1428 state = scc_readl(dpriv, CCR1);
1429 if (settings->loopback) {
1430 printk(KERN_DEBUG "%s: loopback\n", dev->name);
1431 state |= 0x00000100;
1432 } else {
1433 printk(KERN_DEBUG "%s: normal\n", dev->name);
1434 state &= ~0x00000100;
1435 }
1436 scc_writel(state, dpriv, dev, CCR1);
1437 return 0;
1438}
1439
1440static int dscc4_crc_setting(struct dscc4_dev_priv *dpriv,
1441 struct net_device *dev)
1442{
1443 struct thingie crc[] = {
1444 { PARITY_CRC16_PR0_CCITT, 0x00000010 },
1445 { PARITY_CRC16_PR1_CCITT, 0x00000000 },
1446 { PARITY_CRC32_PR0_CCITT, 0x00000011 },
1447 { PARITY_CRC32_PR1_CCITT, 0x00000001 }
1448 };
1449 int i, ret = 0;
1450
1451 i = dscc4_match(crc, dpriv->parity);
1452 if (i >= 0)
1453 scc_patchl(CrcMask, crc[i].bits, dpriv, dev, CCR1);
1454 else
1455 ret = -EOPNOTSUPP;
1456 return ret;
1457}
1458
1459static int dscc4_set_iface(struct dscc4_dev_priv *dpriv, struct net_device *dev)
1460{
1461 struct {
1462 int (*action)(struct dscc4_dev_priv *, struct net_device *);
1463 } *p, do_setting[] = {
1464 { dscc4_encoding_setting },
1465 { dscc4_clock_setting },
1466 { dscc4_loopback_setting },
1467 { dscc4_crc_setting },
1468 { NULL }
1469 };
1470 int ret = 0;
1471
1472 for (p = do_setting; p->action; p++) {
1473 if ((ret = p->action(dpriv, dev)) < 0)
1474 break;
1475 }
1476 return ret;
1477}
1478
7d12e780 1479static irqreturn_t dscc4_irq(int irq, void *token)
1da177e4
LT		 1480{
1481 struct dscc4_dev_priv *root = token;
1482 struct dscc4_pci_priv *priv;
1483 struct net_device *dev;
1484 void __iomem *ioaddr;
1485 u32 state;
1486 unsigned long flags;
1487 int i, handled = 1;
1488
1489 priv = root->pci_priv;
1490 dev = dscc4_to_dev(root);
1491
1492 spin_lock_irqsave(&priv->lock, flags);
1493
1494 ioaddr = root->base_addr;
1495
1496 state = readl(ioaddr + GSTAR);
1497 if (!state) {
1498 handled = 0;
1499 goto out;
1500 }
1501 if (debug > 3)
1502 printk(KERN_DEBUG "%s: GSTAR = 0x%08x\n", DRV_NAME, state);
1503 writel(state, ioaddr + GSTAR);
1504
1505 if (state & Arf) {
1506 printk(KERN_ERR "%s: failure (Arf). Harass the maintener\n",
1507 dev->name);
1508 goto out;
1509 }
1510 state &= ~ArAck;
1511 if (state & Cfg) {
1512 if (debug > 0)
1513 printk(KERN_DEBUG "%s: CfgIV\n", DRV_NAME);
409cd63e 1514 if (priv->iqcfg[priv->cfg_cur++%IRQ_RING_SIZE] & cpu_to_le32(Arf))
1da177e4
LT		 1515 printk(KERN_ERR "%s: %s failed\n", dev->name, "CFG");
1516 if (!(state &= ~Cfg))
1517 goto out;
1518 }
1519 if (state & RxEvt) {
1520 i = dev_per_card - 1;
1521 do {
1522 dscc4_rx_irq(priv, root + i);
1523 } while (--i >= 0);
1524 state &= ~RxEvt;
1525 }
1526 if (state & TxEvt) {
1527 i = dev_per_card - 1;
1528 do {
1529 dscc4_tx_irq(priv, root + i);
1530 } while (--i >= 0);
1531 state &= ~TxEvt;
1532 }
1533out:
1534 spin_unlock_irqrestore(&priv->lock, flags);
1535 return IRQ_RETVAL(handled);
1536}
1537
1538static void dscc4_tx_irq(struct dscc4_pci_priv *ppriv,
1539 struct dscc4_dev_priv *dpriv)
1540{
1541 struct net_device *dev = dscc4_to_dev(dpriv);
1542 u32 state;
1543 int cur, loop = 0;
1544
1545try:
1546 cur = dpriv->iqtx_current%IRQ_RING_SIZE;
409cd63e 1547 state = le32_to_cpu(dpriv->iqtx[cur]);
1da177e4
LT		 1548 if (!state) {
1549 if (debug > 4)
1550 printk(KERN_DEBUG "%s: Tx ISR = 0x%08x\n", dev->name,
1551 state);
1552 if ((debug > 1) && (loop > 1))
1553 printk(KERN_DEBUG "%s: Tx irq loop=%d\n", dev->name, loop);
1554 if (loop && netif_queue_stopped(dev))
1555 if ((dpriv->tx_current - dpriv->tx_dirty)%TX_RING_SIZE)
1556 netif_wake_queue(dev);
1557
1558 if (netif_running(dev) && dscc4_tx_quiescent(dpriv, dev) &&
1559 !dscc4_tx_done(dpriv))
1560 dscc4_do_tx(dpriv, dev);
1561 return;
1562 }
1563 loop++;
1564 dpriv->iqtx[cur] = 0;
1565 dpriv->iqtx_current++;
1566
1567 if (state_check(state, dpriv, dev, "Tx") < 0)
1568 return;
1569
1570 if (state & SccEvt) {
1571 if (state & Alls) {
1da177e4
LT		 1572 struct sk_buff *skb;
1573 struct TxFD *tx_fd;
1574
1575 if (debug > 2)
1576 dscc4_tx_print(dev, dpriv, "Alls");
1577 /*
1578 * DataComplete can't be trusted for Tx completion.
1579 * Cf errata DS5 p.8
1580 */
1581 cur = dpriv->tx_dirty%TX_RING_SIZE;
1582 tx_fd = dpriv->tx_fd + cur;
1583 skb = dpriv->tx_skbuff[cur];
1584 if (skb) {
409cd63e 1585 pci_unmap_single(ppriv->pdev, le32_to_cpu(tx_fd->data),
1da177e4
LT		 1586 skb->len, PCI_DMA_TODEVICE);
1587 if (tx_fd->state & FrameEnd) {
198191c4
KH		 1588 dev->stats.tx_packets++;
1589 dev->stats.tx_bytes += skb->len;
1da177e4
LT		 1590 }
1591 dev_kfree_skb_irq(skb);
1592 dpriv->tx_skbuff[cur] = NULL;
1593 ++dpriv->tx_dirty;
1594 } else {
1595 if (debug > 1)
1596 printk(KERN_ERR "%s Tx: NULL skb %d\n",
1597 dev->name, cur);
1598 }
1599 /*
1600 * If the driver ends sending crap on the wire, it
1601 * will be way easier to diagnose than the (not so)
1602 * random freeze induced by null sized tx frames.
1603 */
1604 tx_fd->data = tx_fd->next;
1605 tx_fd->state = FrameEnd | TO_STATE_TX(2*DUMMY_SKB_SIZE);
1606 tx_fd->complete = 0x00000000;
1607 tx_fd->jiffies = 0;
1608
1609 if (!(state &= ~Alls))
1610 goto try;
1611 }
1612 /*
1613 * Transmit Data Underrun
1614 */
1615 if (state & Xdu) {
1616 printk(KERN_ERR "%s: XDU. Ask maintainer\n", DRV_NAME);
1617 dpriv->flags = NeedIDT;
1618 /* Tx reset */
1619 writel(MTFi | Rdt,
1620 dpriv->base_addr + 0x0c*dpriv->dev_id + CH0CFG);
1621 writel(Action, dpriv->base_addr + GCMDR);
1622 return;
1623 }
1624 if (state & Cts) {
1625 printk(KERN_INFO "%s: CTS transition\n", dev->name);
1626 if (!(state &= ~Cts)) /* DEBUG */
1627 goto try;
1628 }
1629 if (state & Xmr) {
1630 /* Frame needs to be sent again - FIXME */
1631 printk(KERN_ERR "%s: Xmr. Ask maintainer\n", DRV_NAME);
1632 if (!(state &= ~Xmr)) /* DEBUG */
1633 goto try;
1634 }
1635 if (state & Xpr) {
1636 void __iomem *scc_addr;
1637 unsigned long ring;
1638 int i;
1639
1640 /*
1641 * - the busy condition happens (sometimes);
1642 * - it doesn't seem to make the handler unreliable.
1643 */
1644 for (i = 1; i; i <<= 1) {
1645 if (!(scc_readl_star(dpriv, dev) & SccBusy))
1646 break;
1647 }
1648 if (!i)
1649 printk(KERN_INFO "%s busy in irq\n", dev->name);
1650
1651 scc_addr = dpriv->base_addr + 0x0c*dpriv->dev_id;
1652 /* Keep this order: IDT before IDR */
1653 if (dpriv->flags & NeedIDT) {
1654 if (debug > 2)
1655 dscc4_tx_print(dev, dpriv, "Xpr");
1656 ring = dpriv->tx_fd_dma +
1657 (dpriv->tx_dirty%TX_RING_SIZE)*
1658 sizeof(struct TxFD);
1659 writel(ring, scc_addr + CH0BTDA);
1660 dscc4_do_tx(dpriv, dev);
1661 writel(MTFi | Idt, scc_addr + CH0CFG);
1662 if (dscc4_do_action(dev, "IDT") < 0)
1663 goto err_xpr;
1664 dpriv->flags &= ~NeedIDT;
1665 }
1666 if (dpriv->flags & NeedIDR) {
1667 ring = dpriv->rx_fd_dma +
1668 (dpriv->rx_current%RX_RING_SIZE)*
1669 sizeof(struct RxFD);
1670 writel(ring, scc_addr + CH0BRDA);
1671 dscc4_rx_update(dpriv, dev);
1672 writel(MTFi | Idr, scc_addr + CH0CFG);
1673 if (dscc4_do_action(dev, "IDR") < 0)
1674 goto err_xpr;
1675 dpriv->flags &= ~NeedIDR;
1676 smp_wmb();
1677 /* Activate receiver and misc */
1678 scc_writel(0x08050008, dpriv, dev, CCR2);
1679 }
1680 err_xpr:
1681 if (!(state &= ~Xpr))
1682 goto try;
1683 }
1684 if (state & Cd) {
1685 if (debug > 0)
1686 printk(KERN_INFO "%s: CD transition\n", dev->name);
1687 if (!(state &= ~Cd)) /* DEBUG */
1688 goto try;
1689 }
1690 } else { /* ! SccEvt */
1691 if (state & Hi) {
1692#ifdef DSCC4_POLLING
1693 while (!dscc4_tx_poll(dpriv, dev));
1694#endif
1695 printk(KERN_INFO "%s: Tx Hi\n", dev->name);
1696 state &= ~Hi;
1697 }
1698 if (state & Err) {
1699 printk(KERN_INFO "%s: Tx ERR\n", dev->name);
198191c4 1700 dev->stats.tx_errors++;
1da177e4
LT		 1701 state &= ~Err;
1702 }
1703 }
1704 goto try;
1705}
1706
1707static void dscc4_rx_irq(struct dscc4_pci_priv *priv,
1708 struct dscc4_dev_priv *dpriv)
1709{
1710 struct net_device *dev = dscc4_to_dev(dpriv);
1711 u32 state;
1712 int cur;
1713
1714try:
1715 cur = dpriv->iqrx_current%IRQ_RING_SIZE;
409cd63e 1716 state = le32_to_cpu(dpriv->iqrx[cur]);
1da177e4
LT		 1717 if (!state)
1718 return;
1719 dpriv->iqrx[cur] = 0;
1720 dpriv->iqrx_current++;
1721
1722 if (state_check(state, dpriv, dev, "Rx") < 0)
1723 return;
1724
1725 if (!(state & SccEvt)){
1726 struct RxFD *rx_fd;
1727
1728 if (debug > 4)
1729 printk(KERN_DEBUG "%s: Rx ISR = 0x%08x\n", dev->name,
1730 state);
1731 state &= 0x00ffffff;
1732 if (state & Err) { /* Hold or reset */
1733 printk(KERN_DEBUG "%s: Rx ERR\n", dev->name);
1734 cur = dpriv->rx_current%RX_RING_SIZE;
1735 rx_fd = dpriv->rx_fd + cur;
1736 /*
1737 * Presume we're not facing a DMAC receiver reset.
1738 * As We use the rx size-filtering feature of the
1739 * DSCC4, the beginning of a new frame is waiting in
1740 * the rx fifo. I bet a Receive Data Overflow will
1741 * happen most of time but let's try and avoid it.
1742 * Btw (as for RDO) if one experiences ERR whereas
1743 * the system looks rather idle, there may be a
1744 * problem with latency. In this case, increasing
1745 * RX_RING_SIZE may help.
1746 */
1747 //while (dpriv->rx_needs_refill) {
1748 while (!(rx_fd->state1 & Hold)) {
1749 rx_fd++;
1750 cur++;
1751 if (!(cur = cur%RX_RING_SIZE))
1752 rx_fd = dpriv->rx_fd;
1753 }
1754 //dpriv->rx_needs_refill--;
1755 try_get_rx_skb(dpriv, dev);
1756 if (!rx_fd->data)
1757 goto try;
1758 rx_fd->state1 &= ~Hold;
1759 rx_fd->state2 = 0x00000000;
409cd63e 1760 rx_fd->end = cpu_to_le32(0xbabeface);
1da177e4
LT		 1761 //}
1762 goto try;
1763 }
1764 if (state & Fi) {
1765 dscc4_rx_skb(dpriv, dev);
1766 goto try;
1767 }
1768 if (state & Hi ) { /* HI bit */
1769 printk(KERN_INFO "%s: Rx Hi\n", dev->name);
1770 state &= ~Hi;
1771 goto try;
1772 }
1773 } else { /* SccEvt */
1774 if (debug > 1) {
1775 //FIXME: verifier la presence de tous les evenements
1776 static struct {
1777 u32 mask;
1778 const char *irq_name;
1779 } evts[] = {
1780 { 0x00008000, "TIN"},
1781 { 0x00000020, "RSC"},
1782 { 0x00000010, "PCE"},
1783 { 0x00000008, "PLLA"},
1784 { 0, NULL}
1785 }, *evt;
1786
1787 for (evt = evts; evt->irq_name; evt++) {
1788 if (state & evt->mask) {
1789 printk(KERN_DEBUG "%s: %s\n",
1790 dev->name, evt->irq_name);
1791 if (!(state &= ~evt->mask))
1792 goto try;
1793 }
1794 }
1795 } else {
1796 if (!(state &= ~0x0000c03c))
1797 goto try;
1798 }
1799 if (state & Cts) {
1800 printk(KERN_INFO "%s: CTS transition\n", dev->name);
1801 if (!(state &= ~Cts)) /* DEBUG */
1802 goto try;
1803 }
1804 /*
1805 * Receive Data Overflow (FIXME: fscked)
1806 */
1807 if (state & Rdo) {
1808 struct RxFD *rx_fd;
1809 void __iomem *scc_addr;
1810 int cur;
1811
1812 //if (debug)
1813 // dscc4_rx_dump(dpriv);
1814 scc_addr = dpriv->base_addr + 0x0c*dpriv->dev_id;
1815
1816 scc_patchl(RxActivate, 0, dpriv, dev, CCR2);
1817 /*
1818 * This has no effect. Why ?
1819 * ORed with TxSccRes, one sees the CFG ack (for
1820 * the TX part only).
1821 */
1822 scc_writel(RxSccRes, dpriv, dev, CMDR);
1823 dpriv->flags |= RdoSet;
1824
1825 /*
1826 * Let's try and save something in the received data.
1827 * rx_current must be incremented at least once to
1828 * avoid HOLD in the BRDA-to-be-pointed desc.
1829 */
1830 do {
1831 cur = dpriv->rx_current++%RX_RING_SIZE;
1832 rx_fd = dpriv->rx_fd + cur;
1833 if (!(rx_fd->state2 & DataComplete))
1834 break;
1835 if (rx_fd->state2 & FrameAborted) {
198191c4 1836 dev->stats.rx_over_errors++;
1da177e4
LT		 1837 rx_fd->state1 |= Hold;
1838 rx_fd->state2 = 0x00000000;
409cd63e 1839 rx_fd->end = cpu_to_le32(0xbabeface);
1da177e4
LT		 1840 } else
1841 dscc4_rx_skb(dpriv, dev);
1842 } while (1);
1843
1844 if (debug > 0) {
1845 if (dpriv->flags & RdoSet)
1846 printk(KERN_DEBUG
1847 "%s: no RDO in Rx data\n", DRV_NAME);
1848 }
1849#ifdef DSCC4_RDO_EXPERIMENTAL_RECOVERY
1850 /*
1851 * FIXME: must the reset be this violent ?
1852 */
1853#warning "FIXME: CH0BRDA"
1854 writel(dpriv->rx_fd_dma +
1855 (dpriv->rx_current%RX_RING_SIZE)*
1856 sizeof(struct RxFD), scc_addr + CH0BRDA);
1857 writel(MTFi|Rdr|Idr, scc_addr + CH0CFG);
1858 if (dscc4_do_action(dev, "RDR") < 0) {
1859 printk(KERN_ERR "%s: RDO recovery failed(%s)\n",
1860 dev->name, "RDR");
1861 goto rdo_end;
1862 }
1863 writel(MTFi|Idr, scc_addr + CH0CFG);
1864 if (dscc4_do_action(dev, "IDR") < 0) {
1865 printk(KERN_ERR "%s: RDO recovery failed(%s)\n",
1866 dev->name, "IDR");
1867 goto rdo_end;
1868 }
1869 rdo_end:
1870#endif
1871 scc_patchl(0, RxActivate, dpriv, dev, CCR2);
1872 goto try;
1873 }
1874 if (state & Cd) {
1875 printk(KERN_INFO "%s: CD transition\n", dev->name);
1876 if (!(state &= ~Cd)) /* DEBUG */
1877 goto try;
1878 }
1879 if (state & Flex) {
1880 printk(KERN_DEBUG "%s: Flex. Ttttt...\n", DRV_NAME);
1881 if (!(state &= ~Flex))
1882 goto try;
1883 }
1884 }
1885}
1886
1887/*
1888 * I had expected the following to work for the first descriptor
1889 * (tx_fd->state = 0xc0000000)
1890 * - Hold=1 (don't try and branch to the next descripto);
1891 * - No=0 (I want an empty data section, i.e. size=0);
1892 * - Fe=1 (required by No=0 or we got an Err irq and must reset).
1893 * It failed and locked solid. Thus the introduction of a dummy skb.
1894 * Problem is acknowledged in errata sheet DS5. Joy :o/
1895 */
7665a089 1896static struct sk_buff *dscc4_init_dummy_skb(struct dscc4_dev_priv *dpriv)
1da177e4
LT		 1897{
1898 struct sk_buff *skb;
1899
1900 skb = dev_alloc_skb(DUMMY_SKB_SIZE);
1901 if (skb) {
1902 int last = dpriv->tx_dirty%TX_RING_SIZE;
1903 struct TxFD *tx_fd = dpriv->tx_fd + last;
1904
1905 skb->len = DUMMY_SKB_SIZE;
27d7ff46
ACM		 1906 skb_copy_to_linear_data(skb, version,
1907 strlen(version) % DUMMY_SKB_SIZE);
1da177e4 1908 tx_fd->state = FrameEnd | TO_STATE_TX(DUMMY_SKB_SIZE);
409cd63e
AV		 1909 tx_fd->data = cpu_to_le32(pci_map_single(dpriv->pci_priv->pdev,
1910 skb->data, DUMMY_SKB_SIZE,
1911 PCI_DMA_TODEVICE));
1da177e4
LT		 1912 dpriv->tx_skbuff[last] = skb;
1913 }
1914 return skb;
1915}
1916
1917static int dscc4_init_ring(struct net_device *dev)
1918{
1919 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
1920 struct pci_dev *pdev = dpriv->pci_priv->pdev;
1921 struct TxFD *tx_fd;
1922 struct RxFD *rx_fd;
1923 void *ring;
1924 int i;
1925
1926 ring = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &dpriv->rx_fd_dma);
1927 if (!ring)
1928 goto err_out;
1929 dpriv->rx_fd = rx_fd = (struct RxFD *) ring;
1930
1931 ring = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &dpriv->tx_fd_dma);
1932 if (!ring)
1933 goto err_free_dma_rx;
1934 dpriv->tx_fd = tx_fd = (struct TxFD *) ring;
1935
1936 memset(dpriv->tx_skbuff, 0, sizeof(struct sk_buff *)*TX_RING_SIZE);
1937 dpriv->tx_dirty = 0xffffffff;
1938 i = dpriv->tx_current = 0;
1939 do {
1940 tx_fd->state = FrameEnd | TO_STATE_TX(2*DUMMY_SKB_SIZE);
1941 tx_fd->complete = 0x00000000;
1942 /* FIXME: NULL should be ok - to be tried */
409cd63e
AV		 1943 tx_fd->data = cpu_to_le32(dpriv->tx_fd_dma);
1944 (tx_fd++)->next = cpu_to_le32(dpriv->tx_fd_dma +
1da177e4
LT		 1945 (++i%TX_RING_SIZE)*sizeof(*tx_fd));
1946 } while (i < TX_RING_SIZE);
1947
3e710bfa 1948 if (!dscc4_init_dummy_skb(dpriv))
1da177e4
LT		 1949 goto err_free_dma_tx;
1950
1951 memset(dpriv->rx_skbuff, 0, sizeof(struct sk_buff *)*RX_RING_SIZE);
1952 i = dpriv->rx_dirty = dpriv->rx_current = 0;
1953 do {
1954 /* size set by the host. Multiple of 4 bytes please */
1955 rx_fd->state1 = HiDesc;
1956 rx_fd->state2 = 0x00000000;
409cd63e 1957 rx_fd->end = cpu_to_le32(0xbabeface);
1da177e4
LT		 1958 rx_fd->state1 |= TO_STATE_RX(HDLC_MAX_MRU);
1959 // FIXME: return value verifiee mais traitement suspect
1960 if (try_get_rx_skb(dpriv, dev) >= 0)
1961 dpriv->rx_dirty++;
409cd63e 1962 (rx_fd++)->next = cpu_to_le32(dpriv->rx_fd_dma +
1da177e4
LT		 1963 (++i%RX_RING_SIZE)*sizeof(*rx_fd));
1964 } while (i < RX_RING_SIZE);
1965
1966 return 0;
1967
1968err_free_dma_tx:
1969 pci_free_consistent(pdev, TX_TOTAL_SIZE, ring, dpriv->tx_fd_dma);
1970err_free_dma_rx:
1971 pci_free_consistent(pdev, RX_TOTAL_SIZE, rx_fd, dpriv->rx_fd_dma);
1972err_out:
1973 return -ENOMEM;
1974}
1975
1976static void __devexit dscc4_remove_one(struct pci_dev *pdev)
1977{
1978 struct dscc4_pci_priv *ppriv;
1979 struct dscc4_dev_priv *root;
1980 void __iomem *ioaddr;
1981 int i;
1982
1983 ppriv = pci_get_drvdata(pdev);
1984 root = ppriv->root;
1985
1986 ioaddr = root->base_addr;
1987
1988 dscc4_pci_reset(pdev, ioaddr);
1989
1990 free_irq(pdev->irq, root);
1991 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32), ppriv->iqcfg,
1992 ppriv->iqcfg_dma);
1993 for (i = 0; i < dev_per_card; i++) {
1994 struct dscc4_dev_priv *dpriv = root + i;
1995
1996 dscc4_release_ring(dpriv);
1997 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
1998 dpriv->iqrx, dpriv->iqrx_dma);
1999 pci_free_consistent(pdev, IRQ_RING_SIZE*sizeof(u32),
2000 dpriv->iqtx, dpriv->iqtx_dma);
2001 }
2002
2003 dscc4_free1(pdev);
2004
2005 iounmap(ioaddr);
2006
2007 pci_release_region(pdev, 1);
2008 pci_release_region(pdev, 0);
2009
2010 pci_disable_device(pdev);
2011}
2012
2013static int dscc4_hdlc_attach(struct net_device *dev, unsigned short encoding,
2014 unsigned short parity)
2015{
2016 struct dscc4_dev_priv *dpriv = dscc4_priv(dev);
2017
2018 if (encoding != ENCODING_NRZ &&
2019 encoding != ENCODING_NRZI &&
2020 encoding != ENCODING_FM_MARK &&
2021 encoding != ENCODING_FM_SPACE &&
2022 encoding != ENCODING_MANCHESTER)
2023 return -EINVAL;
2024
2025 if (parity != PARITY_NONE &&
2026 parity != PARITY_CRC16_PR0_CCITT &&
2027 parity != PARITY_CRC16_PR1_CCITT &&
2028 parity != PARITY_CRC32_PR0_CCITT &&
2029 parity != PARITY_CRC32_PR1_CCITT)
2030 return -EINVAL;
2031
2032 dpriv->encoding = encoding;
2033 dpriv->parity = parity;
2034 return 0;
2035}
2036
2037#ifndef MODULE
2038static int __init dscc4_setup(char *str)
2039{
2040 int *args[] = { &debug, &quartz, NULL }, **p = args;
2041
2042 while (*p && (get_option(&str, *p) == 2))
2043 p++;
2044 return 1;
2045}
2046
2047__setup("dscc4.setup=", dscc4_setup);
2048#endif
2049
2050static struct pci_device_id dscc4_pci_tbl[] = {
2051 { PCI_VENDOR_ID_SIEMENS, PCI_DEVICE_ID_SIEMENS_DSCC4,
2052 PCI_ANY_ID, PCI_ANY_ID, },
2053 { 0,}
2054};
2055MODULE_DEVICE_TABLE(pci, dscc4_pci_tbl);
2056
2057static struct pci_driver dscc4_driver = {
2058 .name = DRV_NAME,
2059 .id_table = dscc4_pci_tbl,
2060 .probe = dscc4_init_one,
2061 .remove = __devexit_p(dscc4_remove_one),
2062};
2063
2064static int __init dscc4_init_module(void)
2065{
29917620 2066 return pci_register_driver(&dscc4_driver);
1da177e4
LT		 2067}
2068
2069static void __exit dscc4_cleanup_module(void)
2070{
2071 pci_unregister_driver(&dscc4_driver);
2072}
2073
2074module_init(dscc4_init_module);
2075module_exit(dscc4_cleanup_module);
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