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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
14b9764c | 2 | /* FarSync WAN driver for Linux (2.6.x kernel version) |
1da177e4 LT |
3 | * |
4 | * Actually sync driver for X.21, V.35 and V.24 on FarSync T-series cards | |
5 | * | |
6 | * Copyright (C) 2001-2004 FarSite Communications Ltd. | |
7 | * www.farsite.co.uk | |
8 | * | |
1da177e4 LT |
9 | * Author: R.J.Dunlop <bob.dunlop@farsite.co.uk> |
10 | * Maintainer: Kevin Curtis <kevin.curtis@farsite.co.uk> | |
11 | */ | |
12 | ||
3f326d40 JP |
13 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
14 | ||
1da177e4 LT |
15 | #include <linux/module.h> |
16 | #include <linux/kernel.h> | |
17 | #include <linux/version.h> | |
18 | #include <linux/pci.h> | |
d43c36dc | 19 | #include <linux/sched.h> |
5a0e3ad6 | 20 | #include <linux/slab.h> |
1da177e4 LT |
21 | #include <linux/ioport.h> |
22 | #include <linux/init.h> | |
a6b7a407 | 23 | #include <linux/interrupt.h> |
8db4ec66 | 24 | #include <linux/delay.h> |
1da177e4 LT |
25 | #include <linux/if.h> |
26 | #include <linux/hdlc.h> | |
27 | #include <asm/io.h> | |
7c0f6ba6 | 28 | #include <linux/uaccess.h> |
1da177e4 LT |
29 | |
30 | #include "farsync.h" | |
31 | ||
14b9764c | 32 | /* Module info |
1da177e4 LT |
33 | */ |
34 | MODULE_AUTHOR("R.J.Dunlop <bob.dunlop@farsite.co.uk>"); | |
35 | MODULE_DESCRIPTION("FarSync T-Series WAN driver. FarSite Communications Ltd."); | |
36 | MODULE_LICENSE("GPL"); | |
37 | ||
38 | /* Driver configuration and global parameters | |
39 | * ========================================== | |
40 | */ | |
41 | ||
42 | /* Number of ports (per card) and cards supported | |
43 | */ | |
44 | #define FST_MAX_PORTS 4 | |
45 | #define FST_MAX_CARDS 32 | |
46 | ||
47 | /* Default parameters for the link | |
48 | */ | |
49 | #define FST_TX_QUEUE_LEN 100 /* At 8Mbps a longer queue length is | |
14b9764c PL |
50 | * useful |
51 | */ | |
1da177e4 LT |
52 | #define FST_TXQ_DEPTH 16 /* This one is for the buffering |
53 | * of frames on the way down to the card | |
54 | * so that we can keep the card busy | |
55 | * and maximise throughput | |
56 | */ | |
57 | #define FST_HIGH_WATER_MARK 12 /* Point at which we flow control | |
14b9764c PL |
58 | * network layer |
59 | */ | |
1da177e4 | 60 | #define FST_LOW_WATER_MARK 8 /* Point at which we remove flow |
14b9764c PL |
61 | * control from network layer |
62 | */ | |
1da177e4 LT |
63 | #define FST_MAX_MTU 8000 /* Huge but possible */ |
64 | #define FST_DEF_MTU 1500 /* Common sane value */ | |
65 | ||
37947a9b | 66 | #define FST_TX_TIMEOUT (2 * HZ) |
1da177e4 LT |
67 | |
68 | #ifdef ARPHRD_RAWHDLC | |
69 | #define ARPHRD_MYTYPE ARPHRD_RAWHDLC /* Raw frames */ | |
70 | #else | |
71 | #define ARPHRD_MYTYPE ARPHRD_HDLC /* Cisco-HDLC (keepalives etc) */ | |
72 | #endif | |
73 | ||
14b9764c | 74 | /* Modules parameters and associated variables |
1da177e4 | 75 | */ |
7665a089 AB |
76 | static int fst_txq_low = FST_LOW_WATER_MARK; |
77 | static int fst_txq_high = FST_HIGH_WATER_MARK; | |
78 | static int fst_max_reads = 7; | |
8ccac4a5 | 79 | static int fst_excluded_cards; |
7665a089 | 80 | static int fst_excluded_list[FST_MAX_CARDS]; |
1da177e4 LT |
81 | |
82 | module_param(fst_txq_low, int, 0); | |
83 | module_param(fst_txq_high, int, 0); | |
84 | module_param(fst_max_reads, int, 0); | |
85 | module_param(fst_excluded_cards, int, 0); | |
86 | module_param_array(fst_excluded_list, int, NULL, 0); | |
87 | ||
88 | /* Card shared memory layout | |
89 | * ========================= | |
90 | */ | |
91 | #pragma pack(1) | |
92 | ||
93 | /* This information is derived in part from the FarSite FarSync Smc.h | |
94 | * file. Unfortunately various name clashes and the non-portability of the | |
95 | * bit field declarations in that file have meant that I have chosen to | |
96 | * recreate the information here. | |
97 | * | |
98 | * The SMC (Shared Memory Configuration) has a version number that is | |
99 | * incremented every time there is a significant change. This number can | |
100 | * be used to check that we have not got out of step with the firmware | |
101 | * contained in the .CDE files. | |
102 | */ | |
103 | #define SMC_VERSION 24 | |
104 | ||
105 | #define FST_MEMSIZE 0x100000 /* Size of card memory (1Mb) */ | |
106 | ||
107 | #define SMC_BASE 0x00002000L /* Base offset of the shared memory window main | |
14b9764c PL |
108 | * configuration structure |
109 | */ | |
1da177e4 | 110 | #define BFM_BASE 0x00010000L /* Base offset of the shared memory window DMA |
14b9764c PL |
111 | * buffers |
112 | */ | |
1da177e4 LT |
113 | |
114 | #define LEN_TX_BUFFER 8192 /* Size of packet buffers */ | |
115 | #define LEN_RX_BUFFER 8192 | |
116 | ||
117 | #define LEN_SMALL_TX_BUFFER 256 /* Size of obsolete buffs used for DOS diags */ | |
118 | #define LEN_SMALL_RX_BUFFER 256 | |
119 | ||
120 | #define NUM_TX_BUFFER 2 /* Must be power of 2. Fixed by firmware */ | |
121 | #define NUM_RX_BUFFER 8 | |
122 | ||
123 | /* Interrupt retry time in milliseconds */ | |
124 | #define INT_RETRY_TIME 2 | |
125 | ||
126 | /* The Am186CH/CC processors support a SmartDMA mode using circular pools | |
127 | * of buffer descriptors. The structure is almost identical to that used | |
128 | * in the LANCE Ethernet controllers. Details available as PDF from the | |
bfe4c403 | 129 | * AMD web site: https://www.amd.com/products/epd/processors/\ |
1da177e4 LT |
130 | * 2.16bitcont/3.am186cxfa/a21914/21914.pdf |
131 | */ | |
132 | struct txdesc { /* Transmit descriptor */ | |
133 | volatile u16 ladr; /* Low order address of packet. This is a | |
134 | * linear address in the Am186 memory space | |
135 | */ | |
136 | volatile u8 hadr; /* High order address. Low 4 bits only, high 4 | |
137 | * bits must be zero | |
138 | */ | |
139 | volatile u8 bits; /* Status and config */ | |
140 | volatile u16 bcnt; /* 2s complement of packet size in low 15 bits. | |
141 | * Transmit terminal count interrupt enable in | |
142 | * top bit. | |
143 | */ | |
144 | u16 unused; /* Not used in Tx */ | |
145 | }; | |
146 | ||
147 | struct rxdesc { /* Receive descriptor */ | |
148 | volatile u16 ladr; /* Low order address of packet */ | |
149 | volatile u8 hadr; /* High order address */ | |
150 | volatile u8 bits; /* Status and config */ | |
151 | volatile u16 bcnt; /* 2s complement of buffer size in low 15 bits. | |
152 | * Receive terminal count interrupt enable in | |
153 | * top bit. | |
154 | */ | |
155 | volatile u16 mcnt; /* Message byte count (15 bits) */ | |
156 | }; | |
157 | ||
158 | /* Convert a length into the 15 bit 2's complement */ | |
159 | /* #define cnv_bcnt(len) (( ~(len) + 1 ) & 0x7FFF ) */ | |
160 | /* Since we need to set the high bit to enable the completion interrupt this | |
161 | * can be made a lot simpler | |
162 | */ | |
163 | #define cnv_bcnt(len) (-(len)) | |
164 | ||
165 | /* Status and config bits for the above */ | |
166 | #define DMA_OWN 0x80 /* SmartDMA owns the descriptor */ | |
167 | #define TX_STP 0x02 /* Tx: start of packet */ | |
168 | #define TX_ENP 0x01 /* Tx: end of packet */ | |
169 | #define RX_ERR 0x40 /* Rx: error (OR of next 4 bits) */ | |
170 | #define RX_FRAM 0x20 /* Rx: framing error */ | |
171 | #define RX_OFLO 0x10 /* Rx: overflow error */ | |
172 | #define RX_CRC 0x08 /* Rx: CRC error */ | |
173 | #define RX_HBUF 0x04 /* Rx: buffer error */ | |
174 | #define RX_STP 0x02 /* Rx: start of packet */ | |
175 | #define RX_ENP 0x01 /* Rx: end of packet */ | |
176 | ||
177 | /* Interrupts from the card are caused by various events which are presented | |
178 | * in a circular buffer as several events may be processed on one physical int | |
179 | */ | |
180 | #define MAX_CIRBUFF 32 | |
181 | ||
182 | struct cirbuff { | |
183 | u8 rdindex; /* read, then increment and wrap */ | |
184 | u8 wrindex; /* write, then increment and wrap */ | |
185 | u8 evntbuff[MAX_CIRBUFF]; | |
186 | }; | |
187 | ||
188 | /* Interrupt event codes. | |
189 | * Where appropriate the two low order bits indicate the port number | |
190 | */ | |
191 | #define CTLA_CHG 0x18 /* Control signal changed */ | |
192 | #define CTLB_CHG 0x19 | |
193 | #define CTLC_CHG 0x1A | |
194 | #define CTLD_CHG 0x1B | |
195 | ||
196 | #define INIT_CPLT 0x20 /* Initialisation complete */ | |
197 | #define INIT_FAIL 0x21 /* Initialisation failed */ | |
198 | ||
199 | #define ABTA_SENT 0x24 /* Abort sent */ | |
200 | #define ABTB_SENT 0x25 | |
201 | #define ABTC_SENT 0x26 | |
202 | #define ABTD_SENT 0x27 | |
203 | ||
204 | #define TXA_UNDF 0x28 /* Transmission underflow */ | |
205 | #define TXB_UNDF 0x29 | |
206 | #define TXC_UNDF 0x2A | |
207 | #define TXD_UNDF 0x2B | |
208 | ||
209 | #define F56_INT 0x2C | |
210 | #define M32_INT 0x2D | |
211 | ||
212 | #define TE1_ALMA 0x30 | |
213 | ||
214 | /* Port physical configuration. See farsync.h for field values */ | |
215 | struct port_cfg { | |
216 | u16 lineInterface; /* Physical interface type */ | |
217 | u8 x25op; /* Unused at present */ | |
218 | u8 internalClock; /* 1 => internal clock, 0 => external */ | |
219 | u8 transparentMode; /* 1 => on, 0 => off */ | |
220 | u8 invertClock; /* 0 => normal, 1 => inverted */ | |
221 | u8 padBytes[6]; /* Padding */ | |
222 | u32 lineSpeed; /* Speed in bps */ | |
223 | }; | |
224 | ||
225 | /* TE1 port physical configuration */ | |
226 | struct su_config { | |
227 | u32 dataRate; | |
228 | u8 clocking; | |
229 | u8 framing; | |
230 | u8 structure; | |
231 | u8 interface; | |
232 | u8 coding; | |
233 | u8 lineBuildOut; | |
234 | u8 equalizer; | |
235 | u8 transparentMode; | |
236 | u8 loopMode; | |
237 | u8 range; | |
238 | u8 txBufferMode; | |
239 | u8 rxBufferMode; | |
240 | u8 startingSlot; | |
241 | u8 losThreshold; | |
242 | u8 enableIdleCode; | |
243 | u8 idleCode; | |
244 | u8 spare[44]; | |
245 | }; | |
246 | ||
247 | /* TE1 Status */ | |
248 | struct su_status { | |
249 | u32 receiveBufferDelay; | |
250 | u32 framingErrorCount; | |
251 | u32 codeViolationCount; | |
252 | u32 crcErrorCount; | |
253 | u32 lineAttenuation; | |
254 | u8 portStarted; | |
255 | u8 lossOfSignal; | |
256 | u8 receiveRemoteAlarm; | |
257 | u8 alarmIndicationSignal; | |
258 | u8 spare[40]; | |
259 | }; | |
260 | ||
261 | /* Finally sling all the above together into the shared memory structure. | |
262 | * Sorry it's a hodge podge of arrays, structures and unused bits, it's been | |
263 | * evolving under NT for some time so I guess we're stuck with it. | |
264 | * The structure starts at offset SMC_BASE. | |
265 | * See farsync.h for some field values. | |
266 | */ | |
267 | struct fst_shared { | |
268 | /* DMA descriptor rings */ | |
269 | struct rxdesc rxDescrRing[FST_MAX_PORTS][NUM_RX_BUFFER]; | |
270 | struct txdesc txDescrRing[FST_MAX_PORTS][NUM_TX_BUFFER]; | |
271 | ||
272 | /* Obsolete small buffers */ | |
273 | u8 smallRxBuffer[FST_MAX_PORTS][NUM_RX_BUFFER][LEN_SMALL_RX_BUFFER]; | |
274 | u8 smallTxBuffer[FST_MAX_PORTS][NUM_TX_BUFFER][LEN_SMALL_TX_BUFFER]; | |
275 | ||
276 | u8 taskStatus; /* 0x00 => initialising, 0x01 => running, | |
277 | * 0xFF => halted | |
278 | */ | |
279 | ||
280 | u8 interruptHandshake; /* Set to 0x01 by adapter to signal interrupt, | |
281 | * set to 0xEE by host to acknowledge interrupt | |
282 | */ | |
283 | ||
284 | u16 smcVersion; /* Must match SMC_VERSION */ | |
285 | ||
286 | u32 smcFirmwareVersion; /* 0xIIVVRRBB where II = product ID, VV = major | |
287 | * version, RR = revision and BB = build | |
288 | */ | |
289 | ||
290 | u16 txa_done; /* Obsolete completion flags */ | |
291 | u16 rxa_done; | |
292 | u16 txb_done; | |
293 | u16 rxb_done; | |
294 | u16 txc_done; | |
295 | u16 rxc_done; | |
296 | u16 txd_done; | |
297 | u16 rxd_done; | |
298 | ||
299 | u16 mailbox[4]; /* Diagnostics mailbox. Not used */ | |
300 | ||
301 | struct cirbuff interruptEvent; /* interrupt causes */ | |
302 | ||
303 | u32 v24IpSts[FST_MAX_PORTS]; /* V.24 control input status */ | |
304 | u32 v24OpSts[FST_MAX_PORTS]; /* V.24 control output status */ | |
305 | ||
306 | struct port_cfg portConfig[FST_MAX_PORTS]; | |
307 | ||
308 | u16 clockStatus[FST_MAX_PORTS]; /* lsb: 0=> present, 1=> absent */ | |
309 | ||
310 | u16 cableStatus; /* lsb: 0=> present, 1=> absent */ | |
311 | ||
312 | u16 txDescrIndex[FST_MAX_PORTS]; /* transmit descriptor ring index */ | |
313 | u16 rxDescrIndex[FST_MAX_PORTS]; /* receive descriptor ring index */ | |
314 | ||
315 | u16 portMailbox[FST_MAX_PORTS][2]; /* command, modifier */ | |
316 | u16 cardMailbox[4]; /* Not used */ | |
317 | ||
318 | /* Number of times the card thinks the host has | |
319 | * missed an interrupt by not acknowledging | |
320 | * within 2mS (I guess NT has problems) | |
321 | */ | |
322 | u32 interruptRetryCount; | |
323 | ||
324 | /* Driver private data used as an ID. We'll not | |
325 | * use this as I'd rather keep such things | |
326 | * in main memory rather than on the PCI bus | |
327 | */ | |
328 | u32 portHandle[FST_MAX_PORTS]; | |
329 | ||
330 | /* Count of Tx underflows for stats */ | |
331 | u32 transmitBufferUnderflow[FST_MAX_PORTS]; | |
332 | ||
333 | /* Debounced V.24 control input status */ | |
334 | u32 v24DebouncedSts[FST_MAX_PORTS]; | |
335 | ||
336 | /* Adapter debounce timers. Don't touch */ | |
337 | u32 ctsTimer[FST_MAX_PORTS]; | |
338 | u32 ctsTimerRun[FST_MAX_PORTS]; | |
339 | u32 dcdTimer[FST_MAX_PORTS]; | |
340 | u32 dcdTimerRun[FST_MAX_PORTS]; | |
341 | ||
342 | u32 numberOfPorts; /* Number of ports detected at startup */ | |
343 | ||
344 | u16 _reserved[64]; | |
345 | ||
346 | u16 cardMode; /* Bit-mask to enable features: | |
347 | * Bit 0: 1 enables LED identify mode | |
348 | */ | |
349 | ||
350 | u16 portScheduleOffset; | |
351 | ||
352 | struct su_config suConfig; /* TE1 Bits */ | |
353 | struct su_status suStatus; | |
354 | ||
355 | u32 endOfSmcSignature; /* endOfSmcSignature MUST be the last member of | |
356 | * the structure and marks the end of shared | |
357 | * memory. Adapter code initializes it as | |
358 | * END_SIG. | |
359 | */ | |
360 | }; | |
361 | ||
362 | /* endOfSmcSignature value */ | |
363 | #define END_SIG 0x12345678 | |
364 | ||
365 | /* Mailbox values. (portMailbox) */ | |
366 | #define NOP 0 /* No operation */ | |
367 | #define ACK 1 /* Positive acknowledgement to PC driver */ | |
368 | #define NAK 2 /* Negative acknowledgement to PC driver */ | |
369 | #define STARTPORT 3 /* Start an HDLC port */ | |
370 | #define STOPPORT 4 /* Stop an HDLC port */ | |
371 | #define ABORTTX 5 /* Abort the transmitter for a port */ | |
372 | #define SETV24O 6 /* Set V24 outputs */ | |
373 | ||
374 | /* PLX Chip Register Offsets */ | |
375 | #define CNTRL_9052 0x50 /* Control Register */ | |
376 | #define CNTRL_9054 0x6c /* Control Register */ | |
377 | ||
378 | #define INTCSR_9052 0x4c /* Interrupt control/status register */ | |
379 | #define INTCSR_9054 0x68 /* Interrupt control/status register */ | |
380 | ||
381 | /* 9054 DMA Registers */ | |
14b9764c | 382 | /* Note that we will be using DMA Channel 0 for copying rx data |
1da177e4 LT |
383 | * and Channel 1 for copying tx data |
384 | */ | |
385 | #define DMAMODE0 0x80 | |
386 | #define DMAPADR0 0x84 | |
387 | #define DMALADR0 0x88 | |
388 | #define DMASIZ0 0x8c | |
389 | #define DMADPR0 0x90 | |
390 | #define DMAMODE1 0x94 | |
391 | #define DMAPADR1 0x98 | |
392 | #define DMALADR1 0x9c | |
393 | #define DMASIZ1 0xa0 | |
394 | #define DMADPR1 0xa4 | |
395 | #define DMACSR0 0xa8 | |
396 | #define DMACSR1 0xa9 | |
397 | #define DMAARB 0xac | |
398 | #define DMATHR 0xb0 | |
399 | #define DMADAC0 0xb4 | |
400 | #define DMADAC1 0xb8 | |
401 | #define DMAMARBR 0xac | |
402 | ||
403 | #define FST_MIN_DMA_LEN 64 | |
404 | #define FST_RX_DMA_INT 0x01 | |
405 | #define FST_TX_DMA_INT 0x02 | |
406 | #define FST_CARD_INT 0x04 | |
407 | ||
408 | /* Larger buffers are positioned in memory at offset BFM_BASE */ | |
409 | struct buf_window { | |
410 | u8 txBuffer[FST_MAX_PORTS][NUM_TX_BUFFER][LEN_TX_BUFFER]; | |
411 | u8 rxBuffer[FST_MAX_PORTS][NUM_RX_BUFFER][LEN_RX_BUFFER]; | |
412 | }; | |
413 | ||
414 | /* Calculate offset of a buffer object within the shared memory window */ | |
415 | #define BUF_OFFSET(X) (BFM_BASE + offsetof(struct buf_window, X)) | |
416 | ||
417 | #pragma pack() | |
418 | ||
419 | /* Device driver private information | |
420 | * ================================= | |
421 | */ | |
422 | /* Per port (line or channel) information | |
423 | */ | |
424 | struct fst_port_info { | |
3a950181 | 425 | struct net_device *dev; /* Device struct - must be first */ |
1da177e4 LT |
426 | struct fst_card_info *card; /* Card we're associated with */ |
427 | int index; /* Port index on the card */ | |
428 | int hwif; /* Line hardware (lineInterface copy) */ | |
429 | int run; /* Port is running */ | |
430 | int mode; /* Normal or FarSync raw */ | |
431 | int rxpos; /* Next Rx buffer to use */ | |
432 | int txpos; /* Next Tx buffer to use */ | |
433 | int txipos; /* Next Tx buffer to check for free */ | |
434 | int start; /* Indication of start/stop to network */ | |
14b9764c | 435 | /* A sixteen entry transmit queue |
1da177e4 LT |
436 | */ |
437 | int txqs; /* index to get next buffer to tx */ | |
438 | int txqe; /* index to queue next packet */ | |
439 | struct sk_buff *txq[FST_TXQ_DEPTH]; /* The queue */ | |
440 | int rxqdepth; | |
441 | }; | |
442 | ||
443 | /* Per card information | |
444 | */ | |
445 | struct fst_card_info { | |
446 | char __iomem *mem; /* Card memory mapped to kernel space */ | |
447 | char __iomem *ctlmem; /* Control memory for PCI cards */ | |
448 | unsigned int phys_mem; /* Physical memory window address */ | |
449 | unsigned int phys_ctlmem; /* Physical control memory address */ | |
450 | unsigned int irq; /* Interrupt request line number */ | |
451 | unsigned int nports; /* Number of serial ports */ | |
452 | unsigned int type; /* Type index of card */ | |
453 | unsigned int state; /* State of card */ | |
454 | spinlock_t card_lock; /* Lock for SMP access */ | |
455 | unsigned short pci_conf; /* PCI card config in I/O space */ | |
456 | /* Per port info */ | |
457 | struct fst_port_info ports[FST_MAX_PORTS]; | |
458 | struct pci_dev *device; /* Information about the pci device */ | |
459 | int card_no; /* Inst of the card on the system */ | |
460 | int family; /* TxP or TxU */ | |
461 | int dmarx_in_progress; | |
462 | int dmatx_in_progress; | |
463 | unsigned long int_count; | |
464 | unsigned long int_time_ave; | |
465 | void *rx_dma_handle_host; | |
466 | dma_addr_t rx_dma_handle_card; | |
467 | void *tx_dma_handle_host; | |
468 | dma_addr_t tx_dma_handle_card; | |
469 | struct sk_buff *dma_skb_rx; | |
470 | struct fst_port_info *dma_port_rx; | |
471 | struct fst_port_info *dma_port_tx; | |
472 | int dma_len_rx; | |
473 | int dma_len_tx; | |
474 | int dma_txpos; | |
475 | int dma_rxpos; | |
476 | }; | |
477 | ||
478 | /* Convert an HDLC device pointer into a port info pointer and similar */ | |
479 | #define dev_to_port(D) (dev_to_hdlc(D)->priv) | |
480 | #define port_to_dev(P) ((P)->dev) | |
481 | ||
14b9764c | 482 | /* Shared memory window access macros |
1da177e4 LT |
483 | * |
484 | * We have a nice memory based structure above, which could be directly | |
485 | * mapped on i386 but might not work on other architectures unless we use | |
486 | * the readb,w,l and writeb,w,l macros. Unfortunately these macros take | |
487 | * physical offsets so we have to convert. The only saving grace is that | |
488 | * this should all collapse back to a simple indirection eventually. | |
489 | */ | |
490 | #define WIN_OFFSET(X) ((long)&(((struct fst_shared *)SMC_BASE)->X)) | |
491 | ||
7619ab16 PL |
492 | #define FST_RDB(C, E) (readb((C)->mem + WIN_OFFSET(E))) |
493 | #define FST_RDW(C, E) (readw((C)->mem + WIN_OFFSET(E))) | |
494 | #define FST_RDL(C, E) (readl((C)->mem + WIN_OFFSET(E))) | |
1da177e4 | 495 | |
7619ab16 PL |
496 | #define FST_WRB(C, E, B) (writeb((B), (C)->mem + WIN_OFFSET(E))) |
497 | #define FST_WRW(C, E, W) (writew((W), (C)->mem + WIN_OFFSET(E))) | |
498 | #define FST_WRL(C, E, L) (writel((L), (C)->mem + WIN_OFFSET(E))) | |
1da177e4 | 499 | |
14b9764c | 500 | /* Debug support |
1da177e4 LT |
501 | */ |
502 | #if FST_DEBUG | |
503 | ||
504 | static int fst_debug_mask = { FST_DEBUG }; | |
505 | ||
506 | /* Most common debug activity is to print something if the corresponding bit | |
507 | * is set in the debug mask. Note: this uses a non-ANSI extension in GCC to | |
508 | * support variable numbers of macro parameters. The inverted if prevents us | |
509 | * eating someone else's else clause. | |
510 | */ | |
3f326d40 JP |
511 | #define dbg(F, fmt, args...) \ |
512 | do { \ | |
513 | if (fst_debug_mask & (F)) \ | |
514 | printk(KERN_DEBUG pr_fmt(fmt), ##args); \ | |
515 | } while (0) | |
1da177e4 | 516 | #else |
3f326d40 JP |
517 | #define dbg(F, fmt, args...) \ |
518 | do { \ | |
519 | if (0) \ | |
520 | printk(KERN_DEBUG pr_fmt(fmt), ##args); \ | |
521 | } while (0) | |
1da177e4 LT |
522 | #endif |
523 | ||
14b9764c | 524 | /* PCI ID lookup table |
1da177e4 | 525 | */ |
9baa3c34 | 526 | static const struct pci_device_id fst_pci_dev_id[] = { |
d70711da | 527 | {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T2P, PCI_ANY_ID, |
1da177e4 LT |
528 | PCI_ANY_ID, 0, 0, FST_TYPE_T2P}, |
529 | ||
d70711da | 530 | {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T4P, PCI_ANY_ID, |
1da177e4 LT |
531 | PCI_ANY_ID, 0, 0, FST_TYPE_T4P}, |
532 | ||
d70711da | 533 | {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T1U, PCI_ANY_ID, |
1da177e4 LT |
534 | PCI_ANY_ID, 0, 0, FST_TYPE_T1U}, |
535 | ||
d70711da | 536 | {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T2U, PCI_ANY_ID, |
1da177e4 LT |
537 | PCI_ANY_ID, 0, 0, FST_TYPE_T2U}, |
538 | ||
d70711da | 539 | {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_T4U, PCI_ANY_ID, |
1da177e4 LT |
540 | PCI_ANY_ID, 0, 0, FST_TYPE_T4U}, |
541 | ||
d70711da | 542 | {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_TE1, PCI_ANY_ID, |
1da177e4 LT |
543 | PCI_ANY_ID, 0, 0, FST_TYPE_TE1}, |
544 | ||
d70711da | 545 | {PCI_VENDOR_ID_FARSITE, PCI_DEVICE_ID_FARSITE_TE1C, PCI_ANY_ID, |
1da177e4 LT |
546 | PCI_ANY_ID, 0, 0, FST_TYPE_TE1}, |
547 | {0,} /* End */ | |
548 | }; | |
549 | ||
550 | MODULE_DEVICE_TABLE(pci, fst_pci_dev_id); | |
551 | ||
14b9764c | 552 | /* Device Driver Work Queues |
1da177e4 | 553 | * |
d70711da PL |
554 | * So that we don't spend too much time processing events in the |
555 | * Interrupt Service routine, we will declare a work queue per Card | |
1da177e4 LT |
556 | * and make the ISR schedule a task in the queue for later execution. |
557 | * In the 2.4 Kernel we used to use the immediate queue for BH's | |
d70711da | 558 | * Now that they are gone, tasklets seem to be much better than work |
1da177e4 LT |
559 | * queues. |
560 | */ | |
561 | ||
562 | static void do_bottom_half_tx(struct fst_card_info *card); | |
563 | static void do_bottom_half_rx(struct fst_card_info *card); | |
8cc8993c ERB |
564 | static void fst_process_tx_work_q(struct tasklet_struct *unused); |
565 | static void fst_process_int_work_q(struct tasklet_struct *unused); | |
1da177e4 | 566 | |
8cc8993c ERB |
567 | static DECLARE_TASKLET(fst_tx_task, fst_process_tx_work_q); |
568 | static DECLARE_TASKLET(fst_int_task, fst_process_int_work_q); | |
1da177e4 | 569 | |
7665a089 | 570 | static struct fst_card_info *fst_card_array[FST_MAX_CARDS]; |
a1281601 | 571 | static DEFINE_SPINLOCK(fst_work_q_lock); |
7665a089 AB |
572 | static u64 fst_work_txq; |
573 | static u64 fst_work_intq; | |
1da177e4 LT |
574 | |
575 | static void | |
8ea4bfb3 | 576 | fst_q_work_item(u64 *queue, int card_index) |
1da177e4 LT |
577 | { |
578 | unsigned long flags; | |
579 | u64 mask; | |
580 | ||
14b9764c | 581 | /* Grab the queue exclusively |
1da177e4 LT |
582 | */ |
583 | spin_lock_irqsave(&fst_work_q_lock, flags); | |
584 | ||
14b9764c | 585 | /* Making an entry in the queue is simply a matter of setting |
1da177e4 LT |
586 | * a bit for the card indicating that there is work to do in the |
587 | * bottom half for the card. Note the limitation of 64 cards. | |
588 | * That ought to be enough | |
589 | */ | |
50fb47ae | 590 | mask = (u64)1 << card_index; |
1da177e4 LT |
591 | *queue |= mask; |
592 | spin_unlock_irqrestore(&fst_work_q_lock, flags); | |
593 | } | |
594 | ||
595 | static void | |
8cc8993c | 596 | fst_process_tx_work_q(struct tasklet_struct *unused) |
1da177e4 LT |
597 | { |
598 | unsigned long flags; | |
599 | u64 work_txq; | |
600 | int i; | |
601 | ||
14b9764c | 602 | /* Grab the queue exclusively |
1da177e4 LT |
603 | */ |
604 | dbg(DBG_TX, "fst_process_tx_work_q\n"); | |
605 | spin_lock_irqsave(&fst_work_q_lock, flags); | |
606 | work_txq = fst_work_txq; | |
607 | fst_work_txq = 0; | |
608 | spin_unlock_irqrestore(&fst_work_q_lock, flags); | |
609 | ||
14b9764c | 610 | /* Call the bottom half for each card with work waiting |
1da177e4 LT |
611 | */ |
612 | for (i = 0; i < FST_MAX_CARDS; i++) { | |
613 | if (work_txq & 0x01) { | |
f23a3da7 | 614 | if (fst_card_array[i]) { |
1da177e4 LT |
615 | dbg(DBG_TX, "Calling tx bh for card %d\n", i); |
616 | do_bottom_half_tx(fst_card_array[i]); | |
617 | } | |
618 | } | |
619 | work_txq = work_txq >> 1; | |
620 | } | |
621 | } | |
622 | ||
623 | static void | |
8cc8993c | 624 | fst_process_int_work_q(struct tasklet_struct *unused) |
1da177e4 LT |
625 | { |
626 | unsigned long flags; | |
627 | u64 work_intq; | |
628 | int i; | |
629 | ||
14b9764c | 630 | /* Grab the queue exclusively |
1da177e4 LT |
631 | */ |
632 | dbg(DBG_INTR, "fst_process_int_work_q\n"); | |
633 | spin_lock_irqsave(&fst_work_q_lock, flags); | |
634 | work_intq = fst_work_intq; | |
635 | fst_work_intq = 0; | |
636 | spin_unlock_irqrestore(&fst_work_q_lock, flags); | |
637 | ||
14b9764c | 638 | /* Call the bottom half for each card with work waiting |
1da177e4 LT |
639 | */ |
640 | for (i = 0; i < FST_MAX_CARDS; i++) { | |
641 | if (work_intq & 0x01) { | |
f23a3da7 | 642 | if (fst_card_array[i]) { |
1da177e4 LT |
643 | dbg(DBG_INTR, |
644 | "Calling rx & tx bh for card %d\n", i); | |
645 | do_bottom_half_rx(fst_card_array[i]); | |
646 | do_bottom_half_tx(fst_card_array[i]); | |
647 | } | |
648 | } | |
649 | work_intq = work_intq >> 1; | |
650 | } | |
651 | } | |
652 | ||
653 | /* Card control functions | |
654 | * ====================== | |
655 | */ | |
656 | /* Place the processor in reset state | |
657 | * | |
658 | * Used to be a simple write to card control space but a glitch in the latest | |
659 | * AMD Am186CH processor means that we now have to do it by asserting and de- | |
660 | * asserting the PLX chip PCI Adapter Software Reset. Bit 30 in CNTRL register | |
661 | * at offset 9052_CNTRL. Note the updates for the TXU. | |
662 | */ | |
663 | static inline void | |
664 | fst_cpureset(struct fst_card_info *card) | |
665 | { | |
666 | unsigned char interrupt_line_register; | |
1da177e4 LT |
667 | unsigned int regval; |
668 | ||
669 | if (card->family == FST_FAMILY_TXU) { | |
670 | if (pci_read_config_byte | |
671 | (card->device, PCI_INTERRUPT_LINE, &interrupt_line_register)) { | |
672 | dbg(DBG_ASS, | |
673 | "Error in reading interrupt line register\n"); | |
674 | } | |
14b9764c | 675 | /* Assert PLX software reset and Am186 hardware reset |
1da177e4 LT |
676 | * and then deassert the PLX software reset but 186 still in reset |
677 | */ | |
678 | outw(0x440f, card->pci_conf + CNTRL_9054 + 2); | |
679 | outw(0x040f, card->pci_conf + CNTRL_9054 + 2); | |
14b9764c | 680 | /* We are delaying here to allow the 9054 to reset itself |
1da177e4 | 681 | */ |
8db4ec66 | 682 | usleep_range(10, 20); |
1da177e4 | 683 | outw(0x240f, card->pci_conf + CNTRL_9054 + 2); |
14b9764c | 684 | /* We are delaying here to allow the 9054 to reload its eeprom |
1da177e4 | 685 | */ |
8db4ec66 | 686 | usleep_range(10, 20); |
1da177e4 LT |
687 | outw(0x040f, card->pci_conf + CNTRL_9054 + 2); |
688 | ||
689 | if (pci_write_config_byte | |
690 | (card->device, PCI_INTERRUPT_LINE, interrupt_line_register)) { | |
691 | dbg(DBG_ASS, | |
692 | "Error in writing interrupt line register\n"); | |
693 | } | |
694 | ||
695 | } else { | |
696 | regval = inl(card->pci_conf + CNTRL_9052); | |
697 | ||
698 | outl(regval | 0x40000000, card->pci_conf + CNTRL_9052); | |
699 | outl(regval & ~0x40000000, card->pci_conf + CNTRL_9052); | |
700 | } | |
701 | } | |
702 | ||
703 | /* Release the processor from reset | |
704 | */ | |
705 | static inline void | |
706 | fst_cpurelease(struct fst_card_info *card) | |
707 | { | |
708 | if (card->family == FST_FAMILY_TXU) { | |
14b9764c | 709 | /* Force posted writes to complete |
1da177e4 | 710 | */ |
b64b5aee | 711 | (void)readb(card->mem); |
1da177e4 | 712 | |
14b9764c | 713 | /* Release LRESET DO = 1 |
1da177e4 LT |
714 | * Then release Local Hold, DO = 1 |
715 | */ | |
716 | outw(0x040e, card->pci_conf + CNTRL_9054 + 2); | |
717 | outw(0x040f, card->pci_conf + CNTRL_9054 + 2); | |
718 | } else { | |
b64b5aee | 719 | (void)readb(card->ctlmem); |
1da177e4 LT |
720 | } |
721 | } | |
722 | ||
723 | /* Clear the cards interrupt flag | |
724 | */ | |
725 | static inline void | |
726 | fst_clear_intr(struct fst_card_info *card) | |
727 | { | |
728 | if (card->family == FST_FAMILY_TXU) { | |
b64b5aee | 729 | (void)readb(card->ctlmem); |
1da177e4 LT |
730 | } else { |
731 | /* Poke the appropriate PLX chip register (same as enabling interrupts) | |
732 | */ | |
733 | outw(0x0543, card->pci_conf + INTCSR_9052); | |
734 | } | |
735 | } | |
736 | ||
737 | /* Enable card interrupts | |
738 | */ | |
739 | static inline void | |
740 | fst_enable_intr(struct fst_card_info *card) | |
741 | { | |
fa8d10b5 | 742 | if (card->family == FST_FAMILY_TXU) |
1da177e4 | 743 | outl(0x0f0c0900, card->pci_conf + INTCSR_9054); |
fa8d10b5 | 744 | else |
1da177e4 | 745 | outw(0x0543, card->pci_conf + INTCSR_9052); |
1da177e4 LT |
746 | } |
747 | ||
748 | /* Disable card interrupts | |
749 | */ | |
750 | static inline void | |
751 | fst_disable_intr(struct fst_card_info *card) | |
752 | { | |
fa8d10b5 | 753 | if (card->family == FST_FAMILY_TXU) |
1da177e4 | 754 | outl(0x00000000, card->pci_conf + INTCSR_9054); |
fa8d10b5 | 755 | else |
1da177e4 | 756 | outw(0x0000, card->pci_conf + INTCSR_9052); |
1da177e4 LT |
757 | } |
758 | ||
759 | /* Process the result of trying to pass a received frame up the stack | |
760 | */ | |
761 | static void | |
762 | fst_process_rx_status(int rx_status, char *name) | |
763 | { | |
764 | switch (rx_status) { | |
765 | case NET_RX_SUCCESS: | |
766 | { | |
14b9764c | 767 | /* Nothing to do here |
1da177e4 LT |
768 | */ |
769 | break; | |
770 | } | |
1da177e4 LT |
771 | case NET_RX_DROP: |
772 | { | |
773 | dbg(DBG_ASS, "%s: Received packet dropped\n", name); | |
774 | break; | |
775 | } | |
776 | } | |
777 | } | |
778 | ||
779 | /* Initilaise DMA for PLX 9054 | |
780 | */ | |
781 | static inline void | |
782 | fst_init_dma(struct fst_card_info *card) | |
783 | { | |
14b9764c | 784 | /* This is only required for the PLX 9054 |
1da177e4 LT |
785 | */ |
786 | if (card->family == FST_FAMILY_TXU) { | |
3a950181 | 787 | pci_set_master(card->device); |
1da177e4 LT |
788 | outl(0x00020441, card->pci_conf + DMAMODE0); |
789 | outl(0x00020441, card->pci_conf + DMAMODE1); | |
790 | outl(0x0, card->pci_conf + DMATHR); | |
791 | } | |
792 | } | |
793 | ||
794 | /* Tx dma complete interrupt | |
795 | */ | |
796 | static void | |
797 | fst_tx_dma_complete(struct fst_card_info *card, struct fst_port_info *port, | |
798 | int len, int txpos) | |
799 | { | |
800 | struct net_device *dev = port_to_dev(port); | |
1da177e4 | 801 | |
14b9764c | 802 | /* Everything is now set, just tell the card to go |
1da177e4 LT |
803 | */ |
804 | dbg(DBG_TX, "fst_tx_dma_complete\n"); | |
805 | FST_WRB(card, txDescrRing[port->index][txpos].bits, | |
806 | DMA_OWN | TX_STP | TX_ENP); | |
198191c4 KH |
807 | dev->stats.tx_packets++; |
808 | dev->stats.tx_bytes += len; | |
860e9538 | 809 | netif_trans_update(dev); |
1da177e4 LT |
810 | } |
811 | ||
14b9764c | 812 | /* Mark it for our own raw sockets interface |
1da177e4 | 813 | */ |
ab611487 | 814 | static __be16 farsync_type_trans(struct sk_buff *skb, struct net_device *dev) |
1da177e4 LT |
815 | { |
816 | skb->dev = dev; | |
459a98ed | 817 | skb_reset_mac_header(skb); |
1da177e4 LT |
818 | skb->pkt_type = PACKET_HOST; |
819 | return htons(ETH_P_CUST); | |
820 | } | |
821 | ||
822 | /* Rx dma complete interrupt | |
823 | */ | |
824 | static void | |
825 | fst_rx_dma_complete(struct fst_card_info *card, struct fst_port_info *port, | |
826 | int len, struct sk_buff *skb, int rxp) | |
827 | { | |
828 | struct net_device *dev = port_to_dev(port); | |
1da177e4 LT |
829 | int pi; |
830 | int rx_status; | |
831 | ||
832 | dbg(DBG_TX, "fst_rx_dma_complete\n"); | |
833 | pi = port->index; | |
59ae1d12 | 834 | skb_put_data(skb, card->rx_dma_handle_host, len); |
1da177e4 LT |
835 | |
836 | /* Reset buffer descriptor */ | |
837 | FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN); | |
838 | ||
839 | /* Update stats */ | |
198191c4 KH |
840 | dev->stats.rx_packets++; |
841 | dev->stats.rx_bytes += len; | |
1da177e4 LT |
842 | |
843 | /* Push upstream */ | |
844 | dbg(DBG_RX, "Pushing the frame up the stack\n"); | |
845 | if (port->mode == FST_RAW) | |
846 | skb->protocol = farsync_type_trans(skb, dev); | |
847 | else | |
848 | skb->protocol = hdlc_type_trans(skb, dev); | |
849 | rx_status = netif_rx(skb); | |
850 | fst_process_rx_status(rx_status, port_to_dev(port)->name); | |
851 | if (rx_status == NET_RX_DROP) | |
198191c4 | 852 | dev->stats.rx_dropped++; |
1da177e4 LT |
853 | } |
854 | ||
14b9764c | 855 | /* Receive a frame through the DMA |
1da177e4 LT |
856 | */ |
857 | static inline void | |
581d9baa | 858 | fst_rx_dma(struct fst_card_info *card, dma_addr_t dma, u32 mem, int len) |
1da177e4 | 859 | { |
14b9764c | 860 | /* This routine will setup the DMA and start it |
1da177e4 LT |
861 | */ |
862 | ||
581d9baa | 863 | dbg(DBG_RX, "In fst_rx_dma %x %x %d\n", (u32)dma, mem, len); |
fa8d10b5 | 864 | if (card->dmarx_in_progress) |
1da177e4 | 865 | dbg(DBG_ASS, "In fst_rx_dma while dma in progress\n"); |
1da177e4 | 866 | |
581d9baa | 867 | outl(dma, card->pci_conf + DMAPADR0); /* Copy to here */ |
5d337d6f | 868 | outl(mem, card->pci_conf + DMALADR0); /* from here */ |
1da177e4 LT |
869 | outl(len, card->pci_conf + DMASIZ0); /* for this length */ |
870 | outl(0x00000000c, card->pci_conf + DMADPR0); /* In this direction */ | |
871 | ||
14b9764c | 872 | /* We use the dmarx_in_progress flag to flag the channel as busy |
1da177e4 LT |
873 | */ |
874 | card->dmarx_in_progress = 1; | |
875 | outb(0x03, card->pci_conf + DMACSR0); /* Start the transfer */ | |
876 | } | |
877 | ||
14b9764c | 878 | /* Send a frame through the DMA |
1da177e4 LT |
879 | */ |
880 | static inline void | |
581d9baa | 881 | fst_tx_dma(struct fst_card_info *card, dma_addr_t dma, u32 mem, int len) |
1da177e4 | 882 | { |
14b9764c | 883 | /* This routine will setup the DMA and start it. |
1da177e4 LT |
884 | */ |
885 | ||
581d9baa | 886 | dbg(DBG_TX, "In fst_tx_dma %x %x %d\n", (u32)dma, mem, len); |
fa8d10b5 | 887 | if (card->dmatx_in_progress) |
1da177e4 | 888 | dbg(DBG_ASS, "In fst_tx_dma while dma in progress\n"); |
1da177e4 | 889 | |
581d9baa BH |
890 | outl(dma, card->pci_conf + DMAPADR1); /* Copy from here */ |
891 | outl(mem, card->pci_conf + DMALADR1); /* to here */ | |
1da177e4 LT |
892 | outl(len, card->pci_conf + DMASIZ1); /* for this length */ |
893 | outl(0x000000004, card->pci_conf + DMADPR1); /* In this direction */ | |
894 | ||
14b9764c | 895 | /* We use the dmatx_in_progress to flag the channel as busy |
1da177e4 LT |
896 | */ |
897 | card->dmatx_in_progress = 1; | |
898 | outb(0x03, card->pci_conf + DMACSR1); /* Start the transfer */ | |
899 | } | |
900 | ||
901 | /* Issue a Mailbox command for a port. | |
902 | * Note we issue them on a fire and forget basis, not expecting to see an | |
903 | * error and not waiting for completion. | |
904 | */ | |
905 | static void | |
906 | fst_issue_cmd(struct fst_port_info *port, unsigned short cmd) | |
907 | { | |
908 | struct fst_card_info *card; | |
909 | unsigned short mbval; | |
910 | unsigned long flags; | |
911 | int safety; | |
912 | ||
913 | card = port->card; | |
914 | spin_lock_irqsave(&card->card_lock, flags); | |
915 | mbval = FST_RDW(card, portMailbox[port->index][0]); | |
916 | ||
917 | safety = 0; | |
918 | /* Wait for any previous command to complete */ | |
919 | while (mbval > NAK) { | |
920 | spin_unlock_irqrestore(&card->card_lock, flags); | |
3173c890 | 921 | schedule_timeout_uninterruptible(1); |
1da177e4 LT |
922 | spin_lock_irqsave(&card->card_lock, flags); |
923 | ||
924 | if (++safety > 2000) { | |
3f326d40 | 925 | pr_err("Mailbox safety timeout\n"); |
1da177e4 LT |
926 | break; |
927 | } | |
928 | ||
929 | mbval = FST_RDW(card, portMailbox[port->index][0]); | |
930 | } | |
fa8d10b5 | 931 | if (safety > 0) |
1da177e4 | 932 | dbg(DBG_CMD, "Mailbox clear after %d jiffies\n", safety); |
fa8d10b5 PL |
933 | |
934 | if (mbval == NAK) | |
1da177e4 | 935 | dbg(DBG_CMD, "issue_cmd: previous command was NAK'd\n"); |
1da177e4 LT |
936 | |
937 | FST_WRW(card, portMailbox[port->index][0], cmd); | |
938 | ||
939 | if (cmd == ABORTTX || cmd == STARTPORT) { | |
940 | port->txpos = 0; | |
941 | port->txipos = 0; | |
942 | port->start = 0; | |
943 | } | |
944 | ||
945 | spin_unlock_irqrestore(&card->card_lock, flags); | |
946 | } | |
947 | ||
948 | /* Port output signals control | |
949 | */ | |
950 | static inline void | |
951 | fst_op_raise(struct fst_port_info *port, unsigned int outputs) | |
952 | { | |
953 | outputs |= FST_RDL(port->card, v24OpSts[port->index]); | |
954 | FST_WRL(port->card, v24OpSts[port->index], outputs); | |
955 | ||
956 | if (port->run) | |
957 | fst_issue_cmd(port, SETV24O); | |
958 | } | |
959 | ||
960 | static inline void | |
961 | fst_op_lower(struct fst_port_info *port, unsigned int outputs) | |
962 | { | |
963 | outputs = ~outputs & FST_RDL(port->card, v24OpSts[port->index]); | |
964 | FST_WRL(port->card, v24OpSts[port->index], outputs); | |
965 | ||
966 | if (port->run) | |
967 | fst_issue_cmd(port, SETV24O); | |
968 | } | |
969 | ||
14b9764c | 970 | /* Setup port Rx buffers |
1da177e4 LT |
971 | */ |
972 | static void | |
973 | fst_rx_config(struct fst_port_info *port) | |
974 | { | |
975 | int i; | |
976 | int pi; | |
977 | unsigned int offset; | |
978 | unsigned long flags; | |
979 | struct fst_card_info *card; | |
980 | ||
981 | pi = port->index; | |
982 | card = port->card; | |
983 | spin_lock_irqsave(&card->card_lock, flags); | |
984 | for (i = 0; i < NUM_RX_BUFFER; i++) { | |
985 | offset = BUF_OFFSET(rxBuffer[pi][i][0]); | |
986 | ||
b64b5aee PL |
987 | FST_WRW(card, rxDescrRing[pi][i].ladr, (u16)offset); |
988 | FST_WRB(card, rxDescrRing[pi][i].hadr, (u8)(offset >> 16)); | |
1da177e4 LT |
989 | FST_WRW(card, rxDescrRing[pi][i].bcnt, cnv_bcnt(LEN_RX_BUFFER)); |
990 | FST_WRW(card, rxDescrRing[pi][i].mcnt, LEN_RX_BUFFER); | |
991 | FST_WRB(card, rxDescrRing[pi][i].bits, DMA_OWN); | |
992 | } | |
993 | port->rxpos = 0; | |
994 | spin_unlock_irqrestore(&card->card_lock, flags); | |
995 | } | |
996 | ||
14b9764c | 997 | /* Setup port Tx buffers |
1da177e4 LT |
998 | */ |
999 | static void | |
1000 | fst_tx_config(struct fst_port_info *port) | |
1001 | { | |
1002 | int i; | |
1003 | int pi; | |
1004 | unsigned int offset; | |
1005 | unsigned long flags; | |
1006 | struct fst_card_info *card; | |
1007 | ||
1008 | pi = port->index; | |
1009 | card = port->card; | |
1010 | spin_lock_irqsave(&card->card_lock, flags); | |
1011 | for (i = 0; i < NUM_TX_BUFFER; i++) { | |
1012 | offset = BUF_OFFSET(txBuffer[pi][i][0]); | |
1013 | ||
b64b5aee PL |
1014 | FST_WRW(card, txDescrRing[pi][i].ladr, (u16)offset); |
1015 | FST_WRB(card, txDescrRing[pi][i].hadr, (u8)(offset >> 16)); | |
1da177e4 LT |
1016 | FST_WRW(card, txDescrRing[pi][i].bcnt, 0); |
1017 | FST_WRB(card, txDescrRing[pi][i].bits, 0); | |
1018 | } | |
1019 | port->txpos = 0; | |
1020 | port->txipos = 0; | |
1021 | port->start = 0; | |
1022 | spin_unlock_irqrestore(&card->card_lock, flags); | |
1023 | } | |
1024 | ||
1025 | /* TE1 Alarm change interrupt event | |
1026 | */ | |
1027 | static void | |
1028 | fst_intr_te1_alarm(struct fst_card_info *card, struct fst_port_info *port) | |
1029 | { | |
1030 | u8 los; | |
1031 | u8 rra; | |
1032 | u8 ais; | |
1033 | ||
1034 | los = FST_RDB(card, suStatus.lossOfSignal); | |
1035 | rra = FST_RDB(card, suStatus.receiveRemoteAlarm); | |
1036 | ais = FST_RDB(card, suStatus.alarmIndicationSignal); | |
1037 | ||
1038 | if (los) { | |
14b9764c | 1039 | /* Lost the link |
1da177e4 LT |
1040 | */ |
1041 | if (netif_carrier_ok(port_to_dev(port))) { | |
1042 | dbg(DBG_INTR, "Net carrier off\n"); | |
1043 | netif_carrier_off(port_to_dev(port)); | |
1044 | } | |
1045 | } else { | |
14b9764c | 1046 | /* Link available |
1da177e4 LT |
1047 | */ |
1048 | if (!netif_carrier_ok(port_to_dev(port))) { | |
1049 | dbg(DBG_INTR, "Net carrier on\n"); | |
1050 | netif_carrier_on(port_to_dev(port)); | |
1051 | } | |
1052 | } | |
1053 | ||
1054 | if (los) | |
1055 | dbg(DBG_INTR, "Assert LOS Alarm\n"); | |
1056 | else | |
1057 | dbg(DBG_INTR, "De-assert LOS Alarm\n"); | |
1058 | if (rra) | |
1059 | dbg(DBG_INTR, "Assert RRA Alarm\n"); | |
1060 | else | |
1061 | dbg(DBG_INTR, "De-assert RRA Alarm\n"); | |
1062 | ||
1063 | if (ais) | |
1064 | dbg(DBG_INTR, "Assert AIS Alarm\n"); | |
1065 | else | |
1066 | dbg(DBG_INTR, "De-assert AIS Alarm\n"); | |
1067 | } | |
1068 | ||
1069 | /* Control signal change interrupt event | |
1070 | */ | |
1071 | static void | |
1072 | fst_intr_ctlchg(struct fst_card_info *card, struct fst_port_info *port) | |
1073 | { | |
1074 | int signals; | |
1075 | ||
1076 | signals = FST_RDL(card, v24DebouncedSts[port->index]); | |
1077 | ||
ae1be3fa | 1078 | if (signals & ((port->hwif == X21 || port->hwif == X21D) |
1da177e4 LT |
1079 | ? IPSTS_INDICATE : IPSTS_DCD)) { |
1080 | if (!netif_carrier_ok(port_to_dev(port))) { | |
1081 | dbg(DBG_INTR, "DCD active\n"); | |
1082 | netif_carrier_on(port_to_dev(port)); | |
1083 | } | |
1084 | } else { | |
1085 | if (netif_carrier_ok(port_to_dev(port))) { | |
1086 | dbg(DBG_INTR, "DCD lost\n"); | |
1087 | netif_carrier_off(port_to_dev(port)); | |
1088 | } | |
1089 | } | |
1090 | } | |
1091 | ||
1092 | /* Log Rx Errors | |
1093 | */ | |
1094 | static void | |
1095 | fst_log_rx_error(struct fst_card_info *card, struct fst_port_info *port, | |
1096 | unsigned char dmabits, int rxp, unsigned short len) | |
1097 | { | |
1098 | struct net_device *dev = port_to_dev(port); | |
1da177e4 | 1099 | |
14b9764c | 1100 | /* Increment the appropriate error counter |
1da177e4 | 1101 | */ |
198191c4 | 1102 | dev->stats.rx_errors++; |
1da177e4 | 1103 | if (dmabits & RX_OFLO) { |
198191c4 | 1104 | dev->stats.rx_fifo_errors++; |
1da177e4 LT |
1105 | dbg(DBG_ASS, "Rx fifo error on card %d port %d buffer %d\n", |
1106 | card->card_no, port->index, rxp); | |
1107 | } | |
1108 | if (dmabits & RX_CRC) { | |
198191c4 | 1109 | dev->stats.rx_crc_errors++; |
1da177e4 LT |
1110 | dbg(DBG_ASS, "Rx crc error on card %d port %d\n", |
1111 | card->card_no, port->index); | |
1112 | } | |
1113 | if (dmabits & RX_FRAM) { | |
198191c4 | 1114 | dev->stats.rx_frame_errors++; |
1da177e4 LT |
1115 | dbg(DBG_ASS, "Rx frame error on card %d port %d\n", |
1116 | card->card_no, port->index); | |
1117 | } | |
1118 | if (dmabits == (RX_STP | RX_ENP)) { | |
198191c4 | 1119 | dev->stats.rx_length_errors++; |
1da177e4 LT |
1120 | dbg(DBG_ASS, "Rx length error (%d) on card %d port %d\n", |
1121 | len, card->card_no, port->index); | |
1122 | } | |
1123 | } | |
1124 | ||
1125 | /* Rx Error Recovery | |
1126 | */ | |
1127 | static void | |
1128 | fst_recover_rx_error(struct fst_card_info *card, struct fst_port_info *port, | |
1129 | unsigned char dmabits, int rxp, unsigned short len) | |
1130 | { | |
1131 | int i; | |
1132 | int pi; | |
1133 | ||
1134 | pi = port->index; | |
14b9764c | 1135 | /* Discard buffer descriptors until we see the start of the |
1da177e4 | 1136 | * next frame. Note that for long frames this could be in |
d70711da | 1137 | * a subsequent interrupt. |
1da177e4 LT |
1138 | */ |
1139 | i = 0; | |
1140 | while ((dmabits & (DMA_OWN | RX_STP)) == 0) { | |
1141 | FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN); | |
37947a9b | 1142 | rxp = (rxp + 1) % NUM_RX_BUFFER; |
1da177e4 LT |
1143 | if (++i > NUM_RX_BUFFER) { |
1144 | dbg(DBG_ASS, "intr_rx: Discarding more bufs" | |
1145 | " than we have\n"); | |
1146 | break; | |
1147 | } | |
1148 | dmabits = FST_RDB(card, rxDescrRing[pi][rxp].bits); | |
1149 | dbg(DBG_ASS, "DMA Bits of next buffer was %x\n", dmabits); | |
1150 | } | |
1151 | dbg(DBG_ASS, "There were %d subsequent buffers in error\n", i); | |
1152 | ||
1153 | /* Discard the terminal buffer */ | |
1154 | if (!(dmabits & DMA_OWN)) { | |
1155 | FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN); | |
37947a9b | 1156 | rxp = (rxp + 1) % NUM_RX_BUFFER; |
1da177e4 LT |
1157 | } |
1158 | port->rxpos = rxp; | |
1da177e4 LT |
1159 | } |
1160 | ||
1161 | /* Rx complete interrupt | |
1162 | */ | |
1163 | static void | |
1164 | fst_intr_rx(struct fst_card_info *card, struct fst_port_info *port) | |
1165 | { | |
1166 | unsigned char dmabits; | |
1167 | int pi; | |
1168 | int rxp; | |
1169 | int rx_status; | |
1170 | unsigned short len; | |
1171 | struct sk_buff *skb; | |
1172 | struct net_device *dev = port_to_dev(port); | |
1da177e4 LT |
1173 | |
1174 | /* Check we have a buffer to process */ | |
1175 | pi = port->index; | |
1176 | rxp = port->rxpos; | |
1177 | dmabits = FST_RDB(card, rxDescrRing[pi][rxp].bits); | |
1178 | if (dmabits & DMA_OWN) { | |
1179 | dbg(DBG_RX | DBG_INTR, "intr_rx: No buffer port %d pos %d\n", | |
1180 | pi, rxp); | |
1181 | return; | |
1182 | } | |
fa8d10b5 | 1183 | if (card->dmarx_in_progress) |
1da177e4 | 1184 | return; |
1da177e4 LT |
1185 | |
1186 | /* Get buffer length */ | |
1187 | len = FST_RDW(card, rxDescrRing[pi][rxp].mcnt); | |
1188 | /* Discard the CRC */ | |
1189 | len -= 2; | |
1190 | if (len == 0) { | |
14b9764c | 1191 | /* This seems to happen on the TE1 interface sometimes |
1da177e4 LT |
1192 | * so throw the frame away and log the event. |
1193 | */ | |
3f326d40 JP |
1194 | pr_err("Frame received with 0 length. Card %d Port %d\n", |
1195 | card->card_no, port->index); | |
1da177e4 LT |
1196 | /* Return descriptor to card */ |
1197 | FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN); | |
1198 | ||
37947a9b | 1199 | rxp = (rxp + 1) % NUM_RX_BUFFER; |
1da177e4 LT |
1200 | port->rxpos = rxp; |
1201 | return; | |
1202 | } | |
1203 | ||
1204 | /* Check buffer length and for other errors. We insist on one packet | |
1205 | * in one buffer. This simplifies things greatly and since we've | |
1206 | * allocated 8K it shouldn't be a real world limitation | |
1207 | */ | |
1208 | dbg(DBG_RX, "intr_rx: %d,%d: flags %x len %d\n", pi, rxp, dmabits, len); | |
1209 | if (dmabits != (RX_STP | RX_ENP) || len > LEN_RX_BUFFER - 2) { | |
1210 | fst_log_rx_error(card, port, dmabits, rxp, len); | |
1211 | fst_recover_rx_error(card, port, dmabits, rxp, len); | |
1212 | return; | |
1213 | } | |
1214 | ||
1215 | /* Allocate SKB */ | |
40996bcf PL |
1216 | skb = dev_alloc_skb(len); |
1217 | if (!skb) { | |
1da177e4 LT |
1218 | dbg(DBG_RX, "intr_rx: can't allocate buffer\n"); |
1219 | ||
198191c4 | 1220 | dev->stats.rx_dropped++; |
1da177e4 LT |
1221 | |
1222 | /* Return descriptor to card */ | |
1223 | FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN); | |
1224 | ||
37947a9b | 1225 | rxp = (rxp + 1) % NUM_RX_BUFFER; |
1da177e4 LT |
1226 | port->rxpos = rxp; |
1227 | return; | |
1228 | } | |
1229 | ||
14b9764c | 1230 | /* We know the length we need to receive, len. |
1da177e4 LT |
1231 | * It's not worth using the DMA for reads of less than |
1232 | * FST_MIN_DMA_LEN | |
1233 | */ | |
1234 | ||
ae1be3fa | 1235 | if (len < FST_MIN_DMA_LEN || card->family == FST_FAMILY_TXP) { |
1da177e4 LT |
1236 | memcpy_fromio(skb_put(skb, len), |
1237 | card->mem + BUF_OFFSET(rxBuffer[pi][rxp][0]), | |
1238 | len); | |
1239 | ||
1240 | /* Reset buffer descriptor */ | |
1241 | FST_WRB(card, rxDescrRing[pi][rxp].bits, DMA_OWN); | |
1242 | ||
1243 | /* Update stats */ | |
198191c4 KH |
1244 | dev->stats.rx_packets++; |
1245 | dev->stats.rx_bytes += len; | |
1da177e4 LT |
1246 | |
1247 | /* Push upstream */ | |
1248 | dbg(DBG_RX, "Pushing frame up the stack\n"); | |
1249 | if (port->mode == FST_RAW) | |
1250 | skb->protocol = farsync_type_trans(skb, dev); | |
1251 | else | |
1252 | skb->protocol = hdlc_type_trans(skb, dev); | |
1253 | rx_status = netif_rx(skb); | |
1254 | fst_process_rx_status(rx_status, port_to_dev(port)->name); | |
198191c4 KH |
1255 | if (rx_status == NET_RX_DROP) |
1256 | dev->stats.rx_dropped++; | |
1da177e4 LT |
1257 | } else { |
1258 | card->dma_skb_rx = skb; | |
1259 | card->dma_port_rx = port; | |
1260 | card->dma_len_rx = len; | |
1261 | card->dma_rxpos = rxp; | |
5d337d6f DM |
1262 | fst_rx_dma(card, card->rx_dma_handle_card, |
1263 | BUF_OFFSET(rxBuffer[pi][rxp][0]), len); | |
1da177e4 LT |
1264 | } |
1265 | if (rxp != port->rxpos) { | |
1266 | dbg(DBG_ASS, "About to increment rxpos by more than 1\n"); | |
1267 | dbg(DBG_ASS, "rxp = %d rxpos = %d\n", rxp, port->rxpos); | |
1268 | } | |
37947a9b | 1269 | rxp = (rxp + 1) % NUM_RX_BUFFER; |
1da177e4 LT |
1270 | port->rxpos = rxp; |
1271 | } | |
1272 | ||
14b9764c | 1273 | /* The bottom half to the ISR |
1da177e4 LT |
1274 | * |
1275 | */ | |
1276 | ||
1277 | static void | |
1278 | do_bottom_half_tx(struct fst_card_info *card) | |
1279 | { | |
1280 | struct fst_port_info *port; | |
1281 | int pi; | |
1282 | int txq_length; | |
1283 | struct sk_buff *skb; | |
1284 | unsigned long flags; | |
1285 | struct net_device *dev; | |
1da177e4 | 1286 | |
14b9764c | 1287 | /* Find a free buffer for the transmit |
1da177e4 LT |
1288 | * Step through each port on this card |
1289 | */ | |
1290 | ||
1291 | dbg(DBG_TX, "do_bottom_half_tx\n"); | |
1292 | for (pi = 0, port = card->ports; pi < card->nports; pi++, port++) { | |
1293 | if (!port->run) | |
1294 | continue; | |
1295 | ||
198191c4 KH |
1296 | dev = port_to_dev(port); |
1297 | while (!(FST_RDB(card, txDescrRing[pi][port->txpos].bits) & | |
8e95a202 JP |
1298 | DMA_OWN) && |
1299 | !(card->dmatx_in_progress)) { | |
14b9764c | 1300 | /* There doesn't seem to be a txdone event per-se |
1da177e4 LT |
1301 | * We seem to have to deduce it, by checking the DMA_OWN |
1302 | * bit on the next buffer we think we can use | |
1303 | */ | |
1304 | spin_lock_irqsave(&card->card_lock, flags); | |
40996bcf PL |
1305 | txq_length = port->txqe - port->txqs; |
1306 | if (txq_length < 0) { | |
14b9764c | 1307 | /* This is the case where one has wrapped and the |
1da177e4 LT |
1308 | * maths gives us a negative number |
1309 | */ | |
1310 | txq_length = txq_length + FST_TXQ_DEPTH; | |
1311 | } | |
1312 | spin_unlock_irqrestore(&card->card_lock, flags); | |
1313 | if (txq_length > 0) { | |
14b9764c | 1314 | /* There is something to send |
1da177e4 LT |
1315 | */ |
1316 | spin_lock_irqsave(&card->card_lock, flags); | |
1317 | skb = port->txq[port->txqs]; | |
1318 | port->txqs++; | |
fa8d10b5 | 1319 | if (port->txqs == FST_TXQ_DEPTH) |
1da177e4 | 1320 | port->txqs = 0; |
fa8d10b5 | 1321 | |
1da177e4 | 1322 | spin_unlock_irqrestore(&card->card_lock, flags); |
14b9764c | 1323 | /* copy the data and set the required indicators on the |
1da177e4 LT |
1324 | * card. |
1325 | */ | |
1326 | FST_WRW(card, txDescrRing[pi][port->txpos].bcnt, | |
1327 | cnv_bcnt(skb->len)); | |
ae1be3fa PL |
1328 | if (skb->len < FST_MIN_DMA_LEN || |
1329 | card->family == FST_FAMILY_TXP) { | |
1da177e4 LT |
1330 | /* Enqueue the packet with normal io */ |
1331 | memcpy_toio(card->mem + | |
1332 | BUF_OFFSET(txBuffer[pi] | |
1333 | [port-> | |
1334 | txpos][0]), | |
1335 | skb->data, skb->len); | |
1336 | FST_WRB(card, | |
1337 | txDescrRing[pi][port->txpos]. | |
1338 | bits, | |
1339 | DMA_OWN | TX_STP | TX_ENP); | |
198191c4 KH |
1340 | dev->stats.tx_packets++; |
1341 | dev->stats.tx_bytes += skb->len; | |
860e9538 | 1342 | netif_trans_update(dev); |
1da177e4 LT |
1343 | } else { |
1344 | /* Or do it through dma */ | |
1345 | memcpy(card->tx_dma_handle_host, | |
1346 | skb->data, skb->len); | |
1347 | card->dma_port_tx = port; | |
1348 | card->dma_len_tx = skb->len; | |
1349 | card->dma_txpos = port->txpos; | |
1350 | fst_tx_dma(card, | |
581d9baa | 1351 | card->tx_dma_handle_card, |
1da177e4 LT |
1352 | BUF_OFFSET(txBuffer[pi] |
1353 | [port->txpos][0]), | |
1354 | skb->len); | |
1355 | } | |
1356 | if (++port->txpos >= NUM_TX_BUFFER) | |
1357 | port->txpos = 0; | |
14b9764c | 1358 | /* If we have flow control on, can we now release it? |
1da177e4 LT |
1359 | */ |
1360 | if (port->start) { | |
1361 | if (txq_length < fst_txq_low) { | |
1362 | netif_wake_queue(port_to_dev | |
1363 | (port)); | |
1364 | port->start = 0; | |
1365 | } | |
1366 | } | |
1367 | dev_kfree_skb(skb); | |
1368 | } else { | |
14b9764c | 1369 | /* Nothing to send so break out of the while loop |
1da177e4 LT |
1370 | */ |
1371 | break; | |
1372 | } | |
1373 | } | |
1374 | } | |
1375 | } | |
1376 | ||
1377 | static void | |
1378 | do_bottom_half_rx(struct fst_card_info *card) | |
1379 | { | |
1380 | struct fst_port_info *port; | |
1381 | int pi; | |
1382 | int rx_count = 0; | |
1383 | ||
1384 | /* Check for rx completions on all ports on this card */ | |
1385 | dbg(DBG_RX, "do_bottom_half_rx\n"); | |
1386 | for (pi = 0, port = card->ports; pi < card->nports; pi++, port++) { | |
1387 | if (!port->run) | |
1388 | continue; | |
1389 | ||
1390 | while (!(FST_RDB(card, rxDescrRing[pi][port->rxpos].bits) | |
1391 | & DMA_OWN) && !(card->dmarx_in_progress)) { | |
1392 | if (rx_count > fst_max_reads) { | |
14b9764c | 1393 | /* Don't spend forever in receive processing |
1da177e4 LT |
1394 | * Schedule another event |
1395 | */ | |
1396 | fst_q_work_item(&fst_work_intq, card->card_no); | |
1397 | tasklet_schedule(&fst_int_task); | |
1398 | break; /* Leave the loop */ | |
1399 | } | |
1400 | fst_intr_rx(card, port); | |
1401 | rx_count++; | |
1402 | } | |
1403 | } | |
1404 | } | |
1405 | ||
14b9764c | 1406 | /* The interrupt service routine |
1da177e4 LT |
1407 | * Dev_id is our fst_card_info pointer |
1408 | */ | |
7665a089 | 1409 | static irqreturn_t |
28fc1f5a | 1410 | fst_intr(int dummy, void *dev_id) |
1da177e4 | 1411 | { |
28fc1f5a | 1412 | struct fst_card_info *card = dev_id; |
1da177e4 LT |
1413 | struct fst_port_info *port; |
1414 | int rdidx; /* Event buffer indices */ | |
1415 | int wridx; | |
1416 | int event; /* Actual event for processing */ | |
1417 | unsigned int dma_intcsr = 0; | |
1418 | unsigned int do_card_interrupt; | |
1419 | unsigned int int_retry_count; | |
1420 | ||
14b9764c | 1421 | /* Check to see if the interrupt was for this card |
1da177e4 LT |
1422 | * return if not |
1423 | * Note that the call to clear the interrupt is important | |
1424 | */ | |
28fc1f5a | 1425 | dbg(DBG_INTR, "intr: %d %p\n", card->irq, card); |
1da177e4 | 1426 | if (card->state != FST_RUNNING) { |
3f326d40 JP |
1427 | pr_err("Interrupt received for card %d in a non running state (%d)\n", |
1428 | card->card_no, card->state); | |
1da177e4 | 1429 | |
14b9764c | 1430 | /* It is possible to really be running, i.e. we have re-loaded |
1da177e4 | 1431 | * a running card |
d70711da | 1432 | * Clear and reprime the interrupt source |
1da177e4 LT |
1433 | */ |
1434 | fst_clear_intr(card); | |
1435 | return IRQ_HANDLED; | |
1436 | } | |
1437 | ||
1438 | /* Clear and reprime the interrupt source */ | |
1439 | fst_clear_intr(card); | |
1440 | ||
14b9764c | 1441 | /* Is the interrupt for this card (handshake == 1) |
1da177e4 LT |
1442 | */ |
1443 | do_card_interrupt = 0; | |
1444 | if (FST_RDB(card, interruptHandshake) == 1) { | |
1445 | do_card_interrupt += FST_CARD_INT; | |
1446 | /* Set the software acknowledge */ | |
1447 | FST_WRB(card, interruptHandshake, 0xEE); | |
1448 | } | |
1449 | if (card->family == FST_FAMILY_TXU) { | |
14b9764c | 1450 | /* Is it a DMA Interrupt |
1da177e4 LT |
1451 | */ |
1452 | dma_intcsr = inl(card->pci_conf + INTCSR_9054); | |
1453 | if (dma_intcsr & 0x00200000) { | |
14b9764c | 1454 | /* DMA Channel 0 (Rx transfer complete) |
1da177e4 LT |
1455 | */ |
1456 | dbg(DBG_RX, "DMA Rx xfer complete\n"); | |
1457 | outb(0x8, card->pci_conf + DMACSR0); | |
1458 | fst_rx_dma_complete(card, card->dma_port_rx, | |
1459 | card->dma_len_rx, card->dma_skb_rx, | |
1460 | card->dma_rxpos); | |
1461 | card->dmarx_in_progress = 0; | |
1462 | do_card_interrupt += FST_RX_DMA_INT; | |
1463 | } | |
1464 | if (dma_intcsr & 0x00400000) { | |
14b9764c | 1465 | /* DMA Channel 1 (Tx transfer complete) |
1da177e4 LT |
1466 | */ |
1467 | dbg(DBG_TX, "DMA Tx xfer complete\n"); | |
1468 | outb(0x8, card->pci_conf + DMACSR1); | |
1469 | fst_tx_dma_complete(card, card->dma_port_tx, | |
1470 | card->dma_len_tx, card->dma_txpos); | |
1471 | card->dmatx_in_progress = 0; | |
1472 | do_card_interrupt += FST_TX_DMA_INT; | |
1473 | } | |
1474 | } | |
1475 | ||
14b9764c | 1476 | /* Have we been missing Interrupts |
1da177e4 LT |
1477 | */ |
1478 | int_retry_count = FST_RDL(card, interruptRetryCount); | |
1479 | if (int_retry_count) { | |
1480 | dbg(DBG_ASS, "Card %d int_retry_count is %d\n", | |
1481 | card->card_no, int_retry_count); | |
1482 | FST_WRL(card, interruptRetryCount, 0); | |
1483 | } | |
1484 | ||
fa8d10b5 | 1485 | if (!do_card_interrupt) |
1da177e4 | 1486 | return IRQ_HANDLED; |
1da177e4 LT |
1487 | |
1488 | /* Scehdule the bottom half of the ISR */ | |
1489 | fst_q_work_item(&fst_work_intq, card->card_no); | |
1490 | tasklet_schedule(&fst_int_task); | |
1491 | ||
1492 | /* Drain the event queue */ | |
1493 | rdidx = FST_RDB(card, interruptEvent.rdindex) & 0x1f; | |
1494 | wridx = FST_RDB(card, interruptEvent.wrindex) & 0x1f; | |
1495 | while (rdidx != wridx) { | |
1496 | event = FST_RDB(card, interruptEvent.evntbuff[rdidx]); | |
1497 | port = &card->ports[event & 0x03]; | |
1498 | ||
1499 | dbg(DBG_INTR, "Processing Interrupt event: %x\n", event); | |
1500 | ||
1501 | switch (event) { | |
1502 | case TE1_ALMA: | |
1503 | dbg(DBG_INTR, "TE1 Alarm intr\n"); | |
1504 | if (port->run) | |
1505 | fst_intr_te1_alarm(card, port); | |
1506 | break; | |
1507 | ||
1508 | case CTLA_CHG: | |
1509 | case CTLB_CHG: | |
1510 | case CTLC_CHG: | |
1511 | case CTLD_CHG: | |
1512 | if (port->run) | |
1513 | fst_intr_ctlchg(card, port); | |
1514 | break; | |
1515 | ||
1516 | case ABTA_SENT: | |
1517 | case ABTB_SENT: | |
1518 | case ABTC_SENT: | |
1519 | case ABTD_SENT: | |
1520 | dbg(DBG_TX, "Abort complete port %d\n", port->index); | |
1521 | break; | |
1522 | ||
1523 | case TXA_UNDF: | |
1524 | case TXB_UNDF: | |
1525 | case TXC_UNDF: | |
1526 | case TXD_UNDF: | |
1527 | /* Difficult to see how we'd get this given that we | |
1528 | * always load up the entire packet for DMA. | |
1529 | */ | |
1530 | dbg(DBG_TX, "Tx underflow port %d\n", port->index); | |
198191c4 KH |
1531 | port_to_dev(port)->stats.tx_errors++; |
1532 | port_to_dev(port)->stats.tx_fifo_errors++; | |
1da177e4 LT |
1533 | dbg(DBG_ASS, "Tx underflow on card %d port %d\n", |
1534 | card->card_no, port->index); | |
1535 | break; | |
1536 | ||
1537 | case INIT_CPLT: | |
1538 | dbg(DBG_INIT, "Card init OK intr\n"); | |
1539 | break; | |
1540 | ||
1541 | case INIT_FAIL: | |
1542 | dbg(DBG_INIT, "Card init FAILED intr\n"); | |
1543 | card->state = FST_IFAILED; | |
1544 | break; | |
1545 | ||
1546 | default: | |
3f326d40 | 1547 | pr_err("intr: unknown card event %d. ignored\n", event); |
1da177e4 LT |
1548 | break; |
1549 | } | |
1550 | ||
1551 | /* Bump and wrap the index */ | |
1552 | if (++rdidx >= MAX_CIRBUFF) | |
1553 | rdidx = 0; | |
1554 | } | |
1555 | FST_WRB(card, interruptEvent.rdindex, rdidx); | |
3a950181 | 1556 | return IRQ_HANDLED; |
1da177e4 LT |
1557 | } |
1558 | ||
1559 | /* Check that the shared memory configuration is one that we can handle | |
1560 | * and that some basic parameters are correct | |
1561 | */ | |
1562 | static void | |
1563 | check_started_ok(struct fst_card_info *card) | |
1564 | { | |
1565 | int i; | |
1566 | ||
1567 | /* Check structure version and end marker */ | |
1568 | if (FST_RDW(card, smcVersion) != SMC_VERSION) { | |
3f326d40 JP |
1569 | pr_err("Bad shared memory version %d expected %d\n", |
1570 | FST_RDW(card, smcVersion), SMC_VERSION); | |
1da177e4 LT |
1571 | card->state = FST_BADVERSION; |
1572 | return; | |
1573 | } | |
1574 | if (FST_RDL(card, endOfSmcSignature) != END_SIG) { | |
3f326d40 | 1575 | pr_err("Missing shared memory signature\n"); |
1da177e4 LT |
1576 | card->state = FST_BADVERSION; |
1577 | return; | |
1578 | } | |
1579 | /* Firmware status flag, 0x00 = initialising, 0x01 = OK, 0xFF = fail */ | |
40996bcf PL |
1580 | i = FST_RDB(card, taskStatus); |
1581 | if (i == 0x01) { | |
1da177e4 LT |
1582 | card->state = FST_RUNNING; |
1583 | } else if (i == 0xFF) { | |
3f326d40 | 1584 | pr_err("Firmware initialisation failed. Card halted\n"); |
1da177e4 LT |
1585 | card->state = FST_HALTED; |
1586 | return; | |
1587 | } else if (i != 0x00) { | |
3f326d40 | 1588 | pr_err("Unknown firmware status 0x%x\n", i); |
1da177e4 LT |
1589 | card->state = FST_HALTED; |
1590 | return; | |
1591 | } | |
1592 | ||
1593 | /* Finally check the number of ports reported by firmware against the | |
1594 | * number we assumed at card detection. Should never happen with | |
1595 | * existing firmware etc so we just report it for the moment. | |
1596 | */ | |
1597 | if (FST_RDL(card, numberOfPorts) != card->nports) { | |
e8c122f4 JP |
1598 | pr_warn("Port count mismatch on card %d. Firmware thinks %d we say %d\n", |
1599 | card->card_no, | |
1600 | FST_RDL(card, numberOfPorts), card->nports); | |
1da177e4 LT |
1601 | } |
1602 | } | |
1603 | ||
1604 | static int | |
1605 | set_conf_from_info(struct fst_card_info *card, struct fst_port_info *port, | |
1606 | struct fstioc_info *info) | |
1607 | { | |
1608 | int err; | |
1609 | unsigned char my_framing; | |
1610 | ||
d70711da PL |
1611 | /* Set things according to the user set valid flags |
1612 | * Several of the old options have been invalidated/replaced by the | |
1da177e4 LT |
1613 | * generic hdlc package. |
1614 | */ | |
1615 | err = 0; | |
1616 | if (info->valid & FSTVAL_PROTO) { | |
1617 | if (info->proto == FST_RAW) | |
1618 | port->mode = FST_RAW; | |
1619 | else | |
1620 | port->mode = FST_GEN_HDLC; | |
1621 | } | |
1622 | ||
1623 | if (info->valid & FSTVAL_CABLE) | |
1624 | err = -EINVAL; | |
1625 | ||
1626 | if (info->valid & FSTVAL_SPEED) | |
1627 | err = -EINVAL; | |
1628 | ||
1629 | if (info->valid & FSTVAL_PHASE) | |
1630 | FST_WRB(card, portConfig[port->index].invertClock, | |
1631 | info->invertClock); | |
1632 | if (info->valid & FSTVAL_MODE) | |
1633 | FST_WRW(card, cardMode, info->cardMode); | |
1634 | if (info->valid & FSTVAL_TE1) { | |
1635 | FST_WRL(card, suConfig.dataRate, info->lineSpeed); | |
1636 | FST_WRB(card, suConfig.clocking, info->clockSource); | |
1637 | my_framing = FRAMING_E1; | |
1638 | if (info->framing == E1) | |
1639 | my_framing = FRAMING_E1; | |
1640 | if (info->framing == T1) | |
1641 | my_framing = FRAMING_T1; | |
1642 | if (info->framing == J1) | |
1643 | my_framing = FRAMING_J1; | |
1644 | FST_WRB(card, suConfig.framing, my_framing); | |
1645 | FST_WRB(card, suConfig.structure, info->structure); | |
1646 | FST_WRB(card, suConfig.interface, info->interface); | |
1647 | FST_WRB(card, suConfig.coding, info->coding); | |
1648 | FST_WRB(card, suConfig.lineBuildOut, info->lineBuildOut); | |
1649 | FST_WRB(card, suConfig.equalizer, info->equalizer); | |
1650 | FST_WRB(card, suConfig.transparentMode, info->transparentMode); | |
1651 | FST_WRB(card, suConfig.loopMode, info->loopMode); | |
1652 | FST_WRB(card, suConfig.range, info->range); | |
1653 | FST_WRB(card, suConfig.txBufferMode, info->txBufferMode); | |
1654 | FST_WRB(card, suConfig.rxBufferMode, info->rxBufferMode); | |
1655 | FST_WRB(card, suConfig.startingSlot, info->startingSlot); | |
1656 | FST_WRB(card, suConfig.losThreshold, info->losThreshold); | |
1657 | if (info->idleCode) | |
1658 | FST_WRB(card, suConfig.enableIdleCode, 1); | |
1659 | else | |
1660 | FST_WRB(card, suConfig.enableIdleCode, 0); | |
1661 | FST_WRB(card, suConfig.idleCode, info->idleCode); | |
1662 | #if FST_DEBUG | |
1663 | if (info->valid & FSTVAL_TE1) { | |
1664 | printk("Setting TE1 data\n"); | |
1665 | printk("Line Speed = %d\n", info->lineSpeed); | |
1666 | printk("Start slot = %d\n", info->startingSlot); | |
1667 | printk("Clock source = %d\n", info->clockSource); | |
1668 | printk("Framing = %d\n", my_framing); | |
1669 | printk("Structure = %d\n", info->structure); | |
1670 | printk("interface = %d\n", info->interface); | |
1671 | printk("Coding = %d\n", info->coding); | |
1672 | printk("Line build out = %d\n", info->lineBuildOut); | |
1673 | printk("Equaliser = %d\n", info->equalizer); | |
1674 | printk("Transparent mode = %d\n", | |
1675 | info->transparentMode); | |
1676 | printk("Loop mode = %d\n", info->loopMode); | |
1677 | printk("Range = %d\n", info->range); | |
1678 | printk("Tx Buffer mode = %d\n", info->txBufferMode); | |
1679 | printk("Rx Buffer mode = %d\n", info->rxBufferMode); | |
1680 | printk("LOS Threshold = %d\n", info->losThreshold); | |
1681 | printk("Idle Code = %d\n", info->idleCode); | |
1682 | } | |
1683 | #endif | |
1684 | } | |
1685 | #if FST_DEBUG | |
fa8d10b5 | 1686 | if (info->valid & FSTVAL_DEBUG) |
1da177e4 | 1687 | fst_debug_mask = info->debug; |
1da177e4 LT |
1688 | #endif |
1689 | ||
1690 | return err; | |
1691 | } | |
1692 | ||
1693 | static void | |
1694 | gather_conf_info(struct fst_card_info *card, struct fst_port_info *port, | |
1695 | struct fstioc_info *info) | |
1696 | { | |
1697 | int i; | |
1698 | ||
b64b5aee | 1699 | memset(info, 0, sizeof(struct fstioc_info)); |
1da177e4 LT |
1700 | |
1701 | i = port->index; | |
1702 | info->kernelVersion = LINUX_VERSION_CODE; | |
1703 | info->nports = card->nports; | |
1704 | info->type = card->type; | |
1705 | info->state = card->state; | |
1706 | info->proto = FST_GEN_HDLC; | |
1707 | info->index = i; | |
1708 | #if FST_DEBUG | |
1709 | info->debug = fst_debug_mask; | |
1710 | #endif | |
1711 | ||
1712 | /* Only mark information as valid if card is running. | |
1713 | * Copy the data anyway in case it is useful for diagnostics | |
1714 | */ | |
1715 | info->valid = ((card->state == FST_RUNNING) ? FSTVAL_ALL : FSTVAL_CARD) | |
1716 | #if FST_DEBUG | |
1717 | | FSTVAL_DEBUG | |
1718 | #endif | |
1719 | ; | |
1720 | ||
1721 | info->lineInterface = FST_RDW(card, portConfig[i].lineInterface); | |
1722 | info->internalClock = FST_RDB(card, portConfig[i].internalClock); | |
1723 | info->lineSpeed = FST_RDL(card, portConfig[i].lineSpeed); | |
1724 | info->invertClock = FST_RDB(card, portConfig[i].invertClock); | |
1725 | info->v24IpSts = FST_RDL(card, v24IpSts[i]); | |
1726 | info->v24OpSts = FST_RDL(card, v24OpSts[i]); | |
1727 | info->clockStatus = FST_RDW(card, clockStatus[i]); | |
1728 | info->cableStatus = FST_RDW(card, cableStatus); | |
1729 | info->cardMode = FST_RDW(card, cardMode); | |
1730 | info->smcFirmwareVersion = FST_RDL(card, smcFirmwareVersion); | |
1731 | ||
14b9764c | 1732 | /* The T2U can report cable presence for both A or B |
d70711da | 1733 | * in bits 0 and 1 of cableStatus. See which port we are and |
1da177e4 LT |
1734 | * do the mapping. |
1735 | */ | |
1736 | if (card->family == FST_FAMILY_TXU) { | |
1737 | if (port->index == 0) { | |
14b9764c | 1738 | /* Port A |
1da177e4 LT |
1739 | */ |
1740 | info->cableStatus = info->cableStatus & 1; | |
1741 | } else { | |
14b9764c | 1742 | /* Port B |
1da177e4 LT |
1743 | */ |
1744 | info->cableStatus = info->cableStatus >> 1; | |
1745 | info->cableStatus = info->cableStatus & 1; | |
1746 | } | |
1747 | } | |
14b9764c | 1748 | /* Some additional bits if we are TE1 |
1da177e4 LT |
1749 | */ |
1750 | if (card->type == FST_TYPE_TE1) { | |
1751 | info->lineSpeed = FST_RDL(card, suConfig.dataRate); | |
1752 | info->clockSource = FST_RDB(card, suConfig.clocking); | |
1753 | info->framing = FST_RDB(card, suConfig.framing); | |
1754 | info->structure = FST_RDB(card, suConfig.structure); | |
1755 | info->interface = FST_RDB(card, suConfig.interface); | |
1756 | info->coding = FST_RDB(card, suConfig.coding); | |
1757 | info->lineBuildOut = FST_RDB(card, suConfig.lineBuildOut); | |
1758 | info->equalizer = FST_RDB(card, suConfig.equalizer); | |
1759 | info->loopMode = FST_RDB(card, suConfig.loopMode); | |
1760 | info->range = FST_RDB(card, suConfig.range); | |
1761 | info->txBufferMode = FST_RDB(card, suConfig.txBufferMode); | |
1762 | info->rxBufferMode = FST_RDB(card, suConfig.rxBufferMode); | |
1763 | info->startingSlot = FST_RDB(card, suConfig.startingSlot); | |
1764 | info->losThreshold = FST_RDB(card, suConfig.losThreshold); | |
1765 | if (FST_RDB(card, suConfig.enableIdleCode)) | |
1766 | info->idleCode = FST_RDB(card, suConfig.idleCode); | |
1767 | else | |
1768 | info->idleCode = 0; | |
1769 | info->receiveBufferDelay = | |
1770 | FST_RDL(card, suStatus.receiveBufferDelay); | |
1771 | info->framingErrorCount = | |
1772 | FST_RDL(card, suStatus.framingErrorCount); | |
1773 | info->codeViolationCount = | |
1774 | FST_RDL(card, suStatus.codeViolationCount); | |
1775 | info->crcErrorCount = FST_RDL(card, suStatus.crcErrorCount); | |
1776 | info->lineAttenuation = FST_RDL(card, suStatus.lineAttenuation); | |
1777 | info->lossOfSignal = FST_RDB(card, suStatus.lossOfSignal); | |
1778 | info->receiveRemoteAlarm = | |
1779 | FST_RDB(card, suStatus.receiveRemoteAlarm); | |
1780 | info->alarmIndicationSignal = | |
1781 | FST_RDB(card, suStatus.alarmIndicationSignal); | |
1782 | } | |
1783 | } | |
1784 | ||
1785 | static int | |
1786 | fst_set_iface(struct fst_card_info *card, struct fst_port_info *port, | |
1787 | struct ifreq *ifr) | |
1788 | { | |
1789 | sync_serial_settings sync; | |
1790 | int i; | |
1791 | ||
fa8d10b5 | 1792 | if (ifr->ifr_settings.size != sizeof(sync)) |
1da177e4 | 1793 | return -ENOMEM; |
1da177e4 LT |
1794 | |
1795 | if (copy_from_user | |
fa8d10b5 | 1796 | (&sync, ifr->ifr_settings.ifs_ifsu.sync, sizeof(sync))) |
1da177e4 | 1797 | return -EFAULT; |
1da177e4 LT |
1798 | |
1799 | if (sync.loopback) | |
1800 | return -EINVAL; | |
1801 | ||
1802 | i = port->index; | |
1803 | ||
1804 | switch (ifr->ifr_settings.type) { | |
1805 | case IF_IFACE_V35: | |
1806 | FST_WRW(card, portConfig[i].lineInterface, V35); | |
1807 | port->hwif = V35; | |
1808 | break; | |
1809 | ||
1810 | case IF_IFACE_V24: | |
1811 | FST_WRW(card, portConfig[i].lineInterface, V24); | |
1812 | port->hwif = V24; | |
1813 | break; | |
1814 | ||
1815 | case IF_IFACE_X21: | |
1816 | FST_WRW(card, portConfig[i].lineInterface, X21); | |
1817 | port->hwif = X21; | |
1818 | break; | |
1819 | ||
1820 | case IF_IFACE_X21D: | |
1821 | FST_WRW(card, portConfig[i].lineInterface, X21D); | |
1822 | port->hwif = X21D; | |
1823 | break; | |
1824 | ||
1825 | case IF_IFACE_T1: | |
1826 | FST_WRW(card, portConfig[i].lineInterface, T1); | |
1827 | port->hwif = T1; | |
1828 | break; | |
1829 | ||
1830 | case IF_IFACE_E1: | |
1831 | FST_WRW(card, portConfig[i].lineInterface, E1); | |
1832 | port->hwif = E1; | |
1833 | break; | |
1834 | ||
1835 | case IF_IFACE_SYNC_SERIAL: | |
1836 | break; | |
1837 | ||
1838 | default: | |
1839 | return -EINVAL; | |
1840 | } | |
1841 | ||
1842 | switch (sync.clock_type) { | |
1843 | case CLOCK_EXT: | |
1844 | FST_WRB(card, portConfig[i].internalClock, EXTCLK); | |
1845 | break; | |
1846 | ||
1847 | case CLOCK_INT: | |
1848 | FST_WRB(card, portConfig[i].internalClock, INTCLK); | |
1849 | break; | |
1850 | ||
1851 | default: | |
1852 | return -EINVAL; | |
1853 | } | |
1854 | FST_WRL(card, portConfig[i].lineSpeed, sync.clock_rate); | |
1855 | return 0; | |
1856 | } | |
1857 | ||
1858 | static int | |
1859 | fst_get_iface(struct fst_card_info *card, struct fst_port_info *port, | |
1860 | struct ifreq *ifr) | |
1861 | { | |
1862 | sync_serial_settings sync; | |
1863 | int i; | |
1864 | ||
1865 | /* First check what line type is set, we'll default to reporting X.21 | |
1866 | * if nothing is set as IF_IFACE_SYNC_SERIAL implies it can't be | |
1867 | * changed | |
1868 | */ | |
1869 | switch (port->hwif) { | |
1870 | case E1: | |
1871 | ifr->ifr_settings.type = IF_IFACE_E1; | |
1872 | break; | |
1873 | case T1: | |
1874 | ifr->ifr_settings.type = IF_IFACE_T1; | |
1875 | break; | |
1876 | case V35: | |
1877 | ifr->ifr_settings.type = IF_IFACE_V35; | |
1878 | break; | |
1879 | case V24: | |
1880 | ifr->ifr_settings.type = IF_IFACE_V24; | |
1881 | break; | |
1882 | case X21D: | |
1883 | ifr->ifr_settings.type = IF_IFACE_X21D; | |
1884 | break; | |
1885 | case X21: | |
1886 | default: | |
1887 | ifr->ifr_settings.type = IF_IFACE_X21; | |
1888 | break; | |
1889 | } | |
fa8d10b5 | 1890 | if (ifr->ifr_settings.size == 0) |
1da177e4 | 1891 | return 0; /* only type requested */ |
fa8d10b5 PL |
1892 | |
1893 | if (ifr->ifr_settings.size < sizeof(sync)) | |
1da177e4 | 1894 | return -ENOMEM; |
1da177e4 LT |
1895 | |
1896 | i = port->index; | |
96b34040 | 1897 | memset(&sync, 0, sizeof(sync)); |
1da177e4 LT |
1898 | sync.clock_rate = FST_RDL(card, portConfig[i].lineSpeed); |
1899 | /* Lucky card and linux use same encoding here */ | |
1900 | sync.clock_type = FST_RDB(card, portConfig[i].internalClock) == | |
1901 | INTCLK ? CLOCK_INT : CLOCK_EXT; | |
1902 | sync.loopback = 0; | |
1903 | ||
fa8d10b5 | 1904 | if (copy_to_user(ifr->ifr_settings.ifs_ifsu.sync, &sync, sizeof(sync))) |
1da177e4 | 1905 | return -EFAULT; |
1da177e4 | 1906 | |
b64b5aee | 1907 | ifr->ifr_settings.size = sizeof(sync); |
1da177e4 LT |
1908 | return 0; |
1909 | } | |
1910 | ||
1911 | static int | |
73d74f61 | 1912 | fst_siocdevprivate(struct net_device *dev, struct ifreq *ifr, void __user *data, int cmd) |
1da177e4 LT |
1913 | { |
1914 | struct fst_card_info *card; | |
1915 | struct fst_port_info *port; | |
1916 | struct fstioc_write wrthdr; | |
1917 | struct fstioc_info info; | |
1918 | unsigned long flags; | |
5ffa6d7f | 1919 | void *buf; |
1da177e4 | 1920 | |
73d74f61 | 1921 | dbg(DBG_IOCTL, "ioctl: %x, %p\n", cmd, data); |
1da177e4 LT |
1922 | |
1923 | port = dev_to_port(dev); | |
1924 | card = port->card; | |
1925 | ||
1926 | if (!capable(CAP_NET_ADMIN)) | |
1927 | return -EPERM; | |
1928 | ||
1929 | switch (cmd) { | |
1930 | case FSTCPURESET: | |
1931 | fst_cpureset(card); | |
1932 | card->state = FST_RESET; | |
1933 | return 0; | |
1934 | ||
1935 | case FSTCPURELEASE: | |
1936 | fst_cpurelease(card); | |
1937 | card->state = FST_STARTING; | |
1938 | return 0; | |
1939 | ||
1940 | case FSTWRITE: /* Code write (download) */ | |
1941 | ||
1942 | /* First copy in the header with the length and offset of data | |
1943 | * to write | |
1944 | */ | |
73d74f61 | 1945 | if (!data) |
1da177e4 | 1946 | return -EINVAL; |
fa8d10b5 | 1947 | |
73d74f61 | 1948 | if (copy_from_user(&wrthdr, data, sizeof(struct fstioc_write))) |
1da177e4 | 1949 | return -EFAULT; |
1da177e4 LT |
1950 | |
1951 | /* Sanity check the parameters. We don't support partial writes | |
1952 | * when going over the top | |
1953 | */ | |
8e95a202 | 1954 | if (wrthdr.size > FST_MEMSIZE || wrthdr.offset > FST_MEMSIZE || |
fa8d10b5 | 1955 | wrthdr.size + wrthdr.offset > FST_MEMSIZE) |
1da177e4 | 1956 | return -ENXIO; |
1da177e4 | 1957 | |
5ffa6d7f AV |
1958 | /* Now copy the data to the card. */ |
1959 | ||
73d74f61 | 1960 | buf = memdup_user(data + sizeof(struct fstioc_write), |
7d889504 JL |
1961 | wrthdr.size); |
1962 | if (IS_ERR(buf)) | |
1963 | return PTR_ERR(buf); | |
1da177e4 | 1964 | |
5ffa6d7f AV |
1965 | memcpy_toio(card->mem + wrthdr.offset, buf, wrthdr.size); |
1966 | kfree(buf); | |
1967 | ||
1da177e4 LT |
1968 | /* Writes to the memory of a card in the reset state constitute |
1969 | * a download | |
1970 | */ | |
fa8d10b5 | 1971 | if (card->state == FST_RESET) |
1da177e4 | 1972 | card->state = FST_DOWNLOAD; |
fa8d10b5 | 1973 | |
1da177e4 LT |
1974 | return 0; |
1975 | ||
1976 | case FSTGETCONF: | |
1977 | ||
1978 | /* If card has just been started check the shared memory config | |
1979 | * version and marker | |
1980 | */ | |
1981 | if (card->state == FST_STARTING) { | |
1982 | check_started_ok(card); | |
1983 | ||
1984 | /* If everything checked out enable card interrupts */ | |
1985 | if (card->state == FST_RUNNING) { | |
1986 | spin_lock_irqsave(&card->card_lock, flags); | |
1987 | fst_enable_intr(card); | |
1988 | FST_WRB(card, interruptHandshake, 0xEE); | |
1989 | spin_unlock_irqrestore(&card->card_lock, flags); | |
1990 | } | |
1991 | } | |
1992 | ||
73d74f61 | 1993 | if (!data) |
1da177e4 | 1994 | return -EINVAL; |
1da177e4 LT |
1995 | |
1996 | gather_conf_info(card, port, &info); | |
1997 | ||
73d74f61 | 1998 | if (copy_to_user(data, &info, sizeof(info))) |
1da177e4 | 1999 | return -EFAULT; |
fa8d10b5 | 2000 | |
1da177e4 LT |
2001 | return 0; |
2002 | ||
2003 | case FSTSETCONF: | |
14b9764c | 2004 | /* Most of the settings have been moved to the generic ioctls |
1da177e4 LT |
2005 | * this just covers debug and board ident now |
2006 | */ | |
2007 | ||
2008 | if (card->state != FST_RUNNING) { | |
3f326d40 JP |
2009 | pr_err("Attempt to configure card %d in non-running state (%d)\n", |
2010 | card->card_no, card->state); | |
1da177e4 LT |
2011 | return -EIO; |
2012 | } | |
73d74f61 | 2013 | if (copy_from_user(&info, data, sizeof(info))) |
1da177e4 | 2014 | return -EFAULT; |
1da177e4 LT |
2015 | |
2016 | return set_conf_from_info(card, port, &info); | |
73d74f61 AB |
2017 | default: |
2018 | return -EINVAL; | |
2019 | } | |
2020 | } | |
1da177e4 | 2021 | |
73d74f61 AB |
2022 | static int |
2023 | fst_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
2024 | { | |
2025 | struct fst_card_info *card; | |
2026 | struct fst_port_info *port; | |
2027 | ||
2028 | dbg(DBG_IOCTL, "ioctl: %x, %x\n", cmd, ifr->ifr_settings.type); | |
2029 | ||
2030 | port = dev_to_port(dev); | |
2031 | card = port->card; | |
2032 | ||
2033 | if (!capable(CAP_NET_ADMIN)) | |
2034 | return -EPERM; | |
2035 | ||
2036 | switch (cmd) { | |
1da177e4 LT |
2037 | case SIOCWANDEV: |
2038 | switch (ifr->ifr_settings.type) { | |
2039 | case IF_GET_IFACE: | |
2040 | return fst_get_iface(card, port, ifr); | |
2041 | ||
2042 | case IF_IFACE_SYNC_SERIAL: | |
2043 | case IF_IFACE_V35: | |
2044 | case IF_IFACE_V24: | |
2045 | case IF_IFACE_X21: | |
2046 | case IF_IFACE_X21D: | |
2047 | case IF_IFACE_T1: | |
2048 | case IF_IFACE_E1: | |
2049 | return fst_set_iface(card, port, ifr); | |
2050 | ||
2051 | case IF_PROTO_RAW: | |
2052 | port->mode = FST_RAW; | |
2053 | return 0; | |
2054 | ||
2055 | case IF_GET_PROTO: | |
2056 | if (port->mode == FST_RAW) { | |
2057 | ifr->ifr_settings.type = IF_PROTO_RAW; | |
2058 | return 0; | |
2059 | } | |
2060 | return hdlc_ioctl(dev, ifr, cmd); | |
2061 | ||
2062 | default: | |
2063 | port->mode = FST_GEN_HDLC; | |
2064 | dbg(DBG_IOCTL, "Passing this type to hdlc %x\n", | |
2065 | ifr->ifr_settings.type); | |
2066 | return hdlc_ioctl(dev, ifr, cmd); | |
2067 | } | |
2068 | ||
2069 | default: | |
2070 | /* Not one of ours. Pass through to HDLC package */ | |
2071 | return hdlc_ioctl(dev, ifr, cmd); | |
2072 | } | |
2073 | } | |
2074 | ||
2075 | static void | |
2076 | fst_openport(struct fst_port_info *port) | |
2077 | { | |
2078 | int signals; | |
1da177e4 LT |
2079 | |
2080 | /* Only init things if card is actually running. This allows open to | |
2081 | * succeed for downloads etc. | |
2082 | */ | |
2083 | if (port->card->state == FST_RUNNING) { | |
2084 | if (port->run) { | |
2085 | dbg(DBG_OPEN, "open: found port already running\n"); | |
2086 | ||
2087 | fst_issue_cmd(port, STOPPORT); | |
2088 | port->run = 0; | |
2089 | } | |
2090 | ||
2091 | fst_rx_config(port); | |
2092 | fst_tx_config(port); | |
2093 | fst_op_raise(port, OPSTS_RTS | OPSTS_DTR); | |
2094 | ||
2095 | fst_issue_cmd(port, STARTPORT); | |
2096 | port->run = 1; | |
2097 | ||
2098 | signals = FST_RDL(port->card, v24DebouncedSts[port->index]); | |
ae1be3fa | 2099 | if (signals & ((port->hwif == X21 || port->hwif == X21D) |
1da177e4 LT |
2100 | ? IPSTS_INDICATE : IPSTS_DCD)) |
2101 | netif_carrier_on(port_to_dev(port)); | |
2102 | else | |
2103 | netif_carrier_off(port_to_dev(port)); | |
2104 | ||
1da177e4 LT |
2105 | port->txqe = 0; |
2106 | port->txqs = 0; | |
2107 | } | |
1da177e4 LT |
2108 | } |
2109 | ||
2110 | static void | |
2111 | fst_closeport(struct fst_port_info *port) | |
2112 | { | |
2113 | if (port->card->state == FST_RUNNING) { | |
2114 | if (port->run) { | |
2115 | port->run = 0; | |
2116 | fst_op_lower(port, OPSTS_RTS | OPSTS_DTR); | |
2117 | ||
2118 | fst_issue_cmd(port, STOPPORT); | |
2119 | } else { | |
2120 | dbg(DBG_OPEN, "close: port not running\n"); | |
2121 | } | |
2122 | } | |
2123 | } | |
2124 | ||
2125 | static int | |
2126 | fst_open(struct net_device *dev) | |
2127 | { | |
2128 | int err; | |
2129 | struct fst_port_info *port; | |
2130 | ||
2131 | port = dev_to_port(dev); | |
2132 | if (!try_module_get(THIS_MODULE)) | |
3a950181 | 2133 | return -EBUSY; |
1da177e4 LT |
2134 | |
2135 | if (port->mode != FST_RAW) { | |
2136 | err = hdlc_open(dev); | |
d0fd64c1 PS |
2137 | if (err) { |
2138 | module_put(THIS_MODULE); | |
1da177e4 | 2139 | return err; |
d0fd64c1 | 2140 | } |
1da177e4 LT |
2141 | } |
2142 | ||
2143 | fst_openport(port); | |
2144 | netif_wake_queue(dev); | |
2145 | return 0; | |
2146 | } | |
2147 | ||
2148 | static int | |
2149 | fst_close(struct net_device *dev) | |
2150 | { | |
2151 | struct fst_port_info *port; | |
2152 | struct fst_card_info *card; | |
2153 | unsigned char tx_dma_done; | |
2154 | unsigned char rx_dma_done; | |
2155 | ||
2156 | port = dev_to_port(dev); | |
2157 | card = port->card; | |
2158 | ||
2159 | tx_dma_done = inb(card->pci_conf + DMACSR1); | |
2160 | rx_dma_done = inb(card->pci_conf + DMACSR0); | |
2161 | dbg(DBG_OPEN, | |
2162 | "Port Close: tx_dma_in_progress = %d (%x) rx_dma_in_progress = %d (%x)\n", | |
2163 | card->dmatx_in_progress, tx_dma_done, card->dmarx_in_progress, | |
2164 | rx_dma_done); | |
2165 | ||
2166 | netif_stop_queue(dev); | |
2167 | fst_closeport(dev_to_port(dev)); | |
fa8d10b5 | 2168 | if (port->mode != FST_RAW) |
1da177e4 | 2169 | hdlc_close(dev); |
fa8d10b5 | 2170 | |
1da177e4 LT |
2171 | module_put(THIS_MODULE); |
2172 | return 0; | |
2173 | } | |
2174 | ||
2175 | static int | |
2176 | fst_attach(struct net_device *dev, unsigned short encoding, unsigned short parity) | |
2177 | { | |
14b9764c | 2178 | /* Setting currently fixed in FarSync card so we check and forget |
1da177e4 LT |
2179 | */ |
2180 | if (encoding != ENCODING_NRZ || parity != PARITY_CRC16_PR1_CCITT) | |
2181 | return -EINVAL; | |
2182 | return 0; | |
2183 | } | |
2184 | ||
2185 | static void | |
0290bd29 | 2186 | fst_tx_timeout(struct net_device *dev, unsigned int txqueue) |
1da177e4 LT |
2187 | { |
2188 | struct fst_port_info *port; | |
2189 | struct fst_card_info *card; | |
1da177e4 LT |
2190 | |
2191 | port = dev_to_port(dev); | |
2192 | card = port->card; | |
198191c4 KH |
2193 | dev->stats.tx_errors++; |
2194 | dev->stats.tx_aborted_errors++; | |
1da177e4 LT |
2195 | dbg(DBG_ASS, "Tx timeout card %d port %d\n", |
2196 | card->card_no, port->index); | |
2197 | fst_issue_cmd(port, ABORTTX); | |
2198 | ||
860e9538 | 2199 | netif_trans_update(dev); |
1da177e4 LT |
2200 | netif_wake_queue(dev); |
2201 | port->start = 0; | |
2202 | } | |
2203 | ||
d71a6749 | 2204 | static netdev_tx_t |
1da177e4 LT |
2205 | fst_start_xmit(struct sk_buff *skb, struct net_device *dev) |
2206 | { | |
2207 | struct fst_card_info *card; | |
2208 | struct fst_port_info *port; | |
1da177e4 LT |
2209 | unsigned long flags; |
2210 | int txq_length; | |
2211 | ||
2212 | port = dev_to_port(dev); | |
2213 | card = port->card; | |
2214 | dbg(DBG_TX, "fst_start_xmit: length = %d\n", skb->len); | |
2215 | ||
2216 | /* Drop packet with error if we don't have carrier */ | |
2217 | if (!netif_carrier_ok(dev)) { | |
2218 | dev_kfree_skb(skb); | |
198191c4 KH |
2219 | dev->stats.tx_errors++; |
2220 | dev->stats.tx_carrier_errors++; | |
1da177e4 LT |
2221 | dbg(DBG_ASS, |
2222 | "Tried to transmit but no carrier on card %d port %d\n", | |
2223 | card->card_no, port->index); | |
ec634fe3 | 2224 | return NETDEV_TX_OK; |
1da177e4 LT |
2225 | } |
2226 | ||
2227 | /* Drop it if it's too big! MTU failure ? */ | |
2228 | if (skb->len > LEN_TX_BUFFER) { | |
2229 | dbg(DBG_ASS, "Packet too large %d vs %d\n", skb->len, | |
2230 | LEN_TX_BUFFER); | |
2231 | dev_kfree_skb(skb); | |
198191c4 | 2232 | dev->stats.tx_errors++; |
ec634fe3 | 2233 | return NETDEV_TX_OK; |
1da177e4 LT |
2234 | } |
2235 | ||
14b9764c | 2236 | /* We are always going to queue the packet |
1da177e4 LT |
2237 | * so that the bottom half is the only place we tx from |
2238 | * Check there is room in the port txq | |
2239 | */ | |
2240 | spin_lock_irqsave(&card->card_lock, flags); | |
40996bcf PL |
2241 | txq_length = port->txqe - port->txqs; |
2242 | if (txq_length < 0) { | |
14b9764c | 2243 | /* This is the case where the next free has wrapped but the |
1da177e4 LT |
2244 | * last used hasn't |
2245 | */ | |
2246 | txq_length = txq_length + FST_TXQ_DEPTH; | |
2247 | } | |
2248 | spin_unlock_irqrestore(&card->card_lock, flags); | |
2249 | if (txq_length > fst_txq_high) { | |
14b9764c | 2250 | /* We have got enough buffers in the pipeline. Ask the network |
1da177e4 LT |
2251 | * layer to stop sending frames down |
2252 | */ | |
2253 | netif_stop_queue(dev); | |
2254 | port->start = 1; /* I'm using this to signal stop sent up */ | |
2255 | } | |
2256 | ||
2257 | if (txq_length == FST_TXQ_DEPTH - 1) { | |
14b9764c | 2258 | /* This shouldn't have happened but such is life |
1da177e4 LT |
2259 | */ |
2260 | dev_kfree_skb(skb); | |
198191c4 | 2261 | dev->stats.tx_errors++; |
1da177e4 LT |
2262 | dbg(DBG_ASS, "Tx queue overflow card %d port %d\n", |
2263 | card->card_no, port->index); | |
ec634fe3 | 2264 | return NETDEV_TX_OK; |
1da177e4 LT |
2265 | } |
2266 | ||
14b9764c | 2267 | /* queue the buffer |
1da177e4 LT |
2268 | */ |
2269 | spin_lock_irqsave(&card->card_lock, flags); | |
2270 | port->txq[port->txqe] = skb; | |
2271 | port->txqe++; | |
2272 | if (port->txqe == FST_TXQ_DEPTH) | |
2273 | port->txqe = 0; | |
2274 | spin_unlock_irqrestore(&card->card_lock, flags); | |
2275 | ||
2276 | /* Scehdule the bottom half which now does transmit processing */ | |
2277 | fst_q_work_item(&fst_work_txq, card->card_no); | |
2278 | tasklet_schedule(&fst_tx_task); | |
2279 | ||
ec634fe3 | 2280 | return NETDEV_TX_OK; |
1da177e4 LT |
2281 | } |
2282 | ||
14b9764c | 2283 | /* Card setup having checked hardware resources. |
1da177e4 LT |
2284 | * Should be pretty bizarre if we get an error here (kernel memory |
2285 | * exhaustion is one possibility). If we do see a problem we report it | |
2286 | * via a printk and leave the corresponding interface and all that follow | |
2287 | * disabled. | |
2288 | */ | |
5a37931f | 2289 | static char *type_strings[] = { |
1da177e4 LT |
2290 | "no hardware", /* Should never be seen */ |
2291 | "FarSync T2P", | |
2292 | "FarSync T4P", | |
2293 | "FarSync T1U", | |
2294 | "FarSync T2U", | |
2295 | "FarSync T4U", | |
2296 | "FarSync TE1" | |
2297 | }; | |
2298 | ||
19eeb2f9 | 2299 | static int |
1da177e4 LT |
2300 | fst_init_card(struct fst_card_info *card) |
2301 | { | |
2302 | int i; | |
2303 | int err; | |
2304 | ||
2305 | /* We're working on a number of ports based on the card ID. If the | |
2306 | * firmware detects something different later (should never happen) | |
2307 | * we'll have to revise it in some way then. | |
2308 | */ | |
2309 | for (i = 0; i < card->nports; i++) { | |
19eeb2f9 AK |
2310 | err = register_hdlc_device(card->ports[i].dev); |
2311 | if (err < 0) { | |
3f326d40 | 2312 | pr_err("Cannot register HDLC device for port %d (errno %d)\n", |
d2a1054b | 2313 | i, -err); |
19eeb2f9 AK |
2314 | while (i--) |
2315 | unregister_hdlc_device(card->ports[i].dev); | |
2316 | return err; | |
2317 | } | |
1da177e4 LT |
2318 | } |
2319 | ||
3f326d40 JP |
2320 | pr_info("%s-%s: %s IRQ%d, %d ports\n", |
2321 | port_to_dev(&card->ports[0])->name, | |
2322 | port_to_dev(&card->ports[card->nports - 1])->name, | |
2323 | type_strings[card->type], card->irq, card->nports); | |
19eeb2f9 | 2324 | return 0; |
1da177e4 LT |
2325 | } |
2326 | ||
991990a1 KH |
2327 | static const struct net_device_ops fst_ops = { |
2328 | .ndo_open = fst_open, | |
2329 | .ndo_stop = fst_close, | |
991990a1 | 2330 | .ndo_start_xmit = hdlc_start_xmit, |
73d74f61 AB |
2331 | .ndo_do_ioctl = fst_ioctl, |
2332 | .ndo_siocdevprivate = fst_siocdevprivate, | |
991990a1 KH |
2333 | .ndo_tx_timeout = fst_tx_timeout, |
2334 | }; | |
2335 | ||
14b9764c | 2336 | /* Initialise card when detected. |
1da177e4 LT |
2337 | * Returns 0 to indicate success, or errno otherwise. |
2338 | */ | |
5a37931f | 2339 | static int |
1da177e4 LT |
2340 | fst_add_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
2341 | { | |
8ccac4a5 | 2342 | static int no_of_cards_added; |
1da177e4 LT |
2343 | struct fst_card_info *card; |
2344 | int err = 0; | |
2345 | int i; | |
2346 | ||
3f326d40 JP |
2347 | printk_once(KERN_INFO |
2348 | pr_fmt("FarSync WAN driver " FST_USER_VERSION | |
2349 | " (c) 2001-2004 FarSite Communications Ltd.\n")); | |
2350 | #if FST_DEBUG | |
2351 | dbg(DBG_ASS, "The value of debug mask is %x\n", fst_debug_mask); | |
2352 | #endif | |
14b9764c | 2353 | /* We are going to be clever and allow certain cards not to be |
1da177e4 LT |
2354 | * configured. An exclude list can be provided in /etc/modules.conf |
2355 | */ | |
2356 | if (fst_excluded_cards != 0) { | |
14b9764c | 2357 | /* There are cards to exclude |
1da177e4 LT |
2358 | * |
2359 | */ | |
2360 | for (i = 0; i < fst_excluded_cards; i++) { | |
ae1be3fa | 2361 | if (pdev->devfn >> 3 == fst_excluded_list[i]) { |
3f326d40 JP |
2362 | pr_info("FarSync PCI device %d not assigned\n", |
2363 | (pdev->devfn) >> 3); | |
1da177e4 LT |
2364 | return -EBUSY; |
2365 | } | |
2366 | } | |
2367 | } | |
2368 | ||
2369 | /* Allocate driver private data */ | |
1d5d1fdc | 2370 | card = kzalloc(sizeof(struct fst_card_info), GFP_KERNEL); |
fa8d10b5 | 2371 | if (!card) |
1da177e4 | 2372 | return -ENOMEM; |
1da177e4 LT |
2373 | |
2374 | /* Try to enable the device */ | |
40996bcf PL |
2375 | err = pci_enable_device(pdev); |
2376 | if (err) { | |
3f326d40 | 2377 | pr_err("Failed to enable card. Err %d\n", -err); |
19eeb2f9 | 2378 | goto enable_fail; |
1da177e4 LT |
2379 | } |
2380 | ||
40996bcf PL |
2381 | err = pci_request_regions(pdev, "FarSync"); |
2382 | if (err) { | |
3f326d40 | 2383 | pr_err("Failed to allocate regions. Err %d\n", -err); |
19eeb2f9 | 2384 | goto regions_fail; |
1da177e4 LT |
2385 | } |
2386 | ||
2387 | /* Get virtual addresses of memory regions */ | |
2388 | card->pci_conf = pci_resource_start(pdev, 1); | |
2389 | card->phys_mem = pci_resource_start(pdev, 2); | |
2390 | card->phys_ctlmem = pci_resource_start(pdev, 3); | |
40996bcf PL |
2391 | card->mem = ioremap(card->phys_mem, FST_MEMSIZE); |
2392 | if (!card->mem) { | |
3f326d40 | 2393 | pr_err("Physical memory remap failed\n"); |
19eeb2f9 AK |
2394 | err = -ENODEV; |
2395 | goto ioremap_physmem_fail; | |
1da177e4 | 2396 | } |
40996bcf PL |
2397 | card->ctlmem = ioremap(card->phys_ctlmem, 0x10); |
2398 | if (!card->ctlmem) { | |
3f326d40 | 2399 | pr_err("Control memory remap failed\n"); |
19eeb2f9 AK |
2400 | err = -ENODEV; |
2401 | goto ioremap_ctlmem_fail; | |
1da177e4 LT |
2402 | } |
2403 | dbg(DBG_PCI, "kernel mem %p, ctlmem %p\n", card->mem, card->ctlmem); | |
2404 | ||
2405 | /* Register the interrupt handler */ | |
1fb9df5d | 2406 | if (request_irq(pdev->irq, fst_intr, IRQF_SHARED, FST_DEV_NAME, card)) { |
3f326d40 | 2407 | pr_err("Unable to register interrupt %d\n", card->irq); |
19eeb2f9 AK |
2408 | err = -ENODEV; |
2409 | goto irq_fail; | |
1da177e4 LT |
2410 | } |
2411 | ||
2412 | /* Record info we need */ | |
2413 | card->irq = pdev->irq; | |
2414 | card->type = ent->driver_data; | |
2415 | card->family = ((ent->driver_data == FST_TYPE_T2P) || | |
2416 | (ent->driver_data == FST_TYPE_T4P)) | |
2417 | ? FST_FAMILY_TXP : FST_FAMILY_TXU; | |
ae1be3fa PL |
2418 | if (ent->driver_data == FST_TYPE_T1U || |
2419 | ent->driver_data == FST_TYPE_TE1) | |
1da177e4 LT |
2420 | card->nports = 1; |
2421 | else | |
2422 | card->nports = ((ent->driver_data == FST_TYPE_T2P) || | |
2423 | (ent->driver_data == FST_TYPE_T2U)) ? 2 : 4; | |
2424 | ||
2425 | card->state = FST_UNINIT; | |
3a950181 | 2426 | spin_lock_init(&card->card_lock); |
1da177e4 | 2427 | |
3a950181 | 2428 | for (i = 0; i < card->nports; i++) { |
1da177e4 LT |
2429 | struct net_device *dev = alloc_hdlcdev(&card->ports[i]); |
2430 | hdlc_device *hdlc; | |
50d4c363 | 2431 | |
1da177e4 LT |
2432 | if (!dev) { |
2433 | while (i--) | |
2434 | free_netdev(card->ports[i].dev); | |
3f326d40 | 2435 | pr_err("FarSync: out of memory\n"); |
19eeb2f9 AK |
2436 | err = -ENOMEM; |
2437 | goto hdlcdev_fail; | |
1da177e4 LT |
2438 | } |
2439 | card->ports[i].dev = dev; | |
3a950181 PL |
2440 | card->ports[i].card = card; |
2441 | card->ports[i].index = i; | |
2442 | card->ports[i].run = 0; | |
1da177e4 LT |
2443 | |
2444 | hdlc = dev_to_hdlc(dev); | |
2445 | ||
3a950181 | 2446 | /* Fill in the net device info */ |
1da177e4 LT |
2447 | /* Since this is a PCI setup this is purely |
2448 | * informational. Give them the buffer addresses | |
2449 | * and basic card I/O. | |
2450 | */ | |
3a950181 PL |
2451 | dev->mem_start = card->phys_mem |
2452 | + BUF_OFFSET(txBuffer[i][0][0]); | |
2453 | dev->mem_end = card->phys_mem | |
2454 | + BUF_OFFSET(txBuffer[i][NUM_TX_BUFFER - 1][LEN_RX_BUFFER - 1]); | |
2455 | dev->base_addr = card->pci_conf; | |
2456 | dev->irq = card->irq; | |
1da177e4 | 2457 | |
991990a1 KH |
2458 | dev->netdev_ops = &fst_ops; |
2459 | dev->tx_queue_len = FST_TX_QUEUE_LEN; | |
2460 | dev->watchdog_timeo = FST_TX_TIMEOUT; | |
3a950181 PL |
2461 | hdlc->attach = fst_attach; |
2462 | hdlc->xmit = fst_start_xmit; | |
1da177e4 LT |
2463 | } |
2464 | ||
2465 | card->device = pdev; | |
2466 | ||
2467 | dbg(DBG_PCI, "type %d nports %d irq %d\n", card->type, | |
2468 | card->nports, card->irq); | |
2469 | dbg(DBG_PCI, "conf %04x mem %08x ctlmem %08x\n", | |
2470 | card->pci_conf, card->phys_mem, card->phys_ctlmem); | |
2471 | ||
2472 | /* Reset the card's processor */ | |
2473 | fst_cpureset(card); | |
2474 | card->state = FST_RESET; | |
2475 | ||
2476 | /* Initialise DMA (if required) */ | |
2477 | fst_init_dma(card); | |
2478 | ||
2479 | /* Record driver data for later use */ | |
2480 | pci_set_drvdata(pdev, card); | |
2481 | ||
2482 | /* Remainder of card setup */ | |
19eeb2f9 AK |
2483 | if (no_of_cards_added >= FST_MAX_CARDS) { |
2484 | pr_err("FarSync: too many cards\n"); | |
2485 | err = -ENOMEM; | |
2486 | goto card_array_fail; | |
2487 | } | |
1da177e4 LT |
2488 | fst_card_array[no_of_cards_added] = card; |
2489 | card->card_no = no_of_cards_added++; /* Record instance and bump it */ | |
19eeb2f9 AK |
2490 | err = fst_init_card(card); |
2491 | if (err) | |
2492 | goto init_card_fail; | |
1da177e4 | 2493 | if (card->family == FST_FAMILY_TXU) { |
14b9764c | 2494 | /* Allocate a dma buffer for transmit and receives |
1da177e4 LT |
2495 | */ |
2496 | card->rx_dma_handle_host = | |
4c900a6b CJ |
2497 | dma_alloc_coherent(&card->device->dev, FST_MAX_MTU, |
2498 | &card->rx_dma_handle_card, GFP_KERNEL); | |
fa8d10b5 | 2499 | if (!card->rx_dma_handle_host) { |
3f326d40 | 2500 | pr_err("Could not allocate rx dma buffer\n"); |
19eeb2f9 AK |
2501 | err = -ENOMEM; |
2502 | goto rx_dma_fail; | |
1da177e4 LT |
2503 | } |
2504 | card->tx_dma_handle_host = | |
4c900a6b CJ |
2505 | dma_alloc_coherent(&card->device->dev, FST_MAX_MTU, |
2506 | &card->tx_dma_handle_card, GFP_KERNEL); | |
fa8d10b5 | 2507 | if (!card->tx_dma_handle_host) { |
3f326d40 | 2508 | pr_err("Could not allocate tx dma buffer\n"); |
19eeb2f9 AK |
2509 | err = -ENOMEM; |
2510 | goto tx_dma_fail; | |
1da177e4 LT |
2511 | } |
2512 | } | |
2513 | return 0; /* Success */ | |
19eeb2f9 AK |
2514 | |
2515 | tx_dma_fail: | |
4c900a6b CJ |
2516 | dma_free_coherent(&card->device->dev, FST_MAX_MTU, |
2517 | card->rx_dma_handle_host, card->rx_dma_handle_card); | |
19eeb2f9 AK |
2518 | rx_dma_fail: |
2519 | fst_disable_intr(card); | |
2520 | for (i = 0 ; i < card->nports ; i++) | |
2521 | unregister_hdlc_device(card->ports[i].dev); | |
2522 | init_card_fail: | |
2523 | fst_card_array[card->card_no] = NULL; | |
2524 | card_array_fail: | |
2525 | for (i = 0 ; i < card->nports ; i++) | |
2526 | free_netdev(card->ports[i].dev); | |
2527 | hdlcdev_fail: | |
2528 | free_irq(card->irq, card); | |
2529 | irq_fail: | |
2530 | iounmap(card->ctlmem); | |
2531 | ioremap_ctlmem_fail: | |
2532 | iounmap(card->mem); | |
2533 | ioremap_physmem_fail: | |
2534 | pci_release_regions(pdev); | |
2535 | regions_fail: | |
2536 | pci_disable_device(pdev); | |
2537 | enable_fail: | |
2538 | kfree(card); | |
2539 | return err; | |
1da177e4 LT |
2540 | } |
2541 | ||
14b9764c | 2542 | /* Cleanup and close down a card |
1da177e4 | 2543 | */ |
5a37931f | 2544 | static void |
1da177e4 LT |
2545 | fst_remove_one(struct pci_dev *pdev) |
2546 | { | |
2547 | struct fst_card_info *card; | |
2548 | int i; | |
2549 | ||
2550 | card = pci_get_drvdata(pdev); | |
2551 | ||
2552 | for (i = 0; i < card->nports; i++) { | |
2553 | struct net_device *dev = port_to_dev(&card->ports[i]); | |
50d4c363 | 2554 | |
1da177e4 LT |
2555 | unregister_hdlc_device(dev); |
2556 | } | |
2557 | ||
2558 | fst_disable_intr(card); | |
2559 | free_irq(card->irq, card); | |
2560 | ||
2561 | iounmap(card->ctlmem); | |
2562 | iounmap(card->mem); | |
2563 | pci_release_regions(pdev); | |
2564 | if (card->family == FST_FAMILY_TXU) { | |
14b9764c | 2565 | /* Free dma buffers |
1da177e4 | 2566 | */ |
4c900a6b CJ |
2567 | dma_free_coherent(&card->device->dev, FST_MAX_MTU, |
2568 | card->rx_dma_handle_host, | |
2569 | card->rx_dma_handle_card); | |
2570 | dma_free_coherent(&card->device->dev, FST_MAX_MTU, | |
2571 | card->tx_dma_handle_host, | |
2572 | card->tx_dma_handle_card); | |
1da177e4 LT |
2573 | } |
2574 | fst_card_array[card->card_no] = NULL; | |
2575 | } | |
2576 | ||
2577 | static struct pci_driver fst_driver = { | |
f21bbd63 VG |
2578 | .name = FST_NAME, |
2579 | .id_table = fst_pci_dev_id, | |
2580 | .probe = fst_add_one, | |
2581 | .remove = fst_remove_one, | |
1da177e4 LT |
2582 | }; |
2583 | ||
2584 | static int __init | |
2585 | fst_init(void) | |
2586 | { | |
2587 | int i; | |
2588 | ||
2589 | for (i = 0; i < FST_MAX_CARDS; i++) | |
2590 | fst_card_array[i] = NULL; | |
29917620 | 2591 | return pci_register_driver(&fst_driver); |
1da177e4 LT |
2592 | } |
2593 | ||
2594 | static void __exit | |
2595 | fst_cleanup_module(void) | |
2596 | { | |
3f326d40 | 2597 | pr_info("FarSync WAN driver unloading\n"); |
1da177e4 LT |
2598 | pci_unregister_driver(&fst_driver); |
2599 | } | |
2600 | ||
2601 | module_init(fst_init); | |
2602 | module_exit(fst_cleanup_module); |