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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
c19b6d24 ZQ |
2 | /* Freescale QUICC Engine HDLC Device Driver |
3 | * | |
4 | * Copyright 2016 Freescale Semiconductor Inc. | |
c19b6d24 ZQ |
5 | */ |
6 | ||
7 | #include <linux/delay.h> | |
8 | #include <linux/dma-mapping.h> | |
9 | #include <linux/hdlc.h> | |
10 | #include <linux/init.h> | |
11 | #include <linux/interrupt.h> | |
12 | #include <linux/io.h> | |
13 | #include <linux/irq.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <linux/module.h> | |
16 | #include <linux/netdevice.h> | |
17 | #include <linux/of_address.h> | |
18 | #include <linux/of_irq.h> | |
19 | #include <linux/of_platform.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/sched.h> | |
22 | #include <linux/skbuff.h> | |
23 | #include <linux/slab.h> | |
24 | #include <linux/spinlock.h> | |
25 | #include <linux/stddef.h> | |
26 | #include <soc/fsl/qe/qe_tdm.h> | |
27 | #include <uapi/linux/if_arp.h> | |
28 | ||
29 | #include "fsl_ucc_hdlc.h" | |
30 | ||
31 | #define DRV_DESC "Freescale QE UCC HDLC Driver" | |
32 | #define DRV_NAME "ucc_hdlc" | |
33 | ||
34 | #define TDM_PPPOHT_SLIC_MAXIN | |
ba59d570 | 35 | #define RX_BD_ERRORS (R_CD_S | R_OV_S | R_CR_S | R_AB_S | R_NO_S | R_LG_S) |
c19b6d24 ZQ |
36 | |
37 | static struct ucc_tdm_info utdm_primary_info = { | |
38 | .uf_info = { | |
39 | .tsa = 0, | |
40 | .cdp = 0, | |
41 | .cds = 1, | |
42 | .ctsp = 1, | |
43 | .ctss = 1, | |
44 | .revd = 0, | |
45 | .urfs = 256, | |
46 | .utfs = 256, | |
47 | .urfet = 128, | |
48 | .urfset = 192, | |
49 | .utfet = 128, | |
50 | .utftt = 0x40, | |
51 | .ufpt = 256, | |
52 | .mode = UCC_FAST_PROTOCOL_MODE_HDLC, | |
53 | .ttx_trx = UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL, | |
54 | .tenc = UCC_FAST_TX_ENCODING_NRZ, | |
55 | .renc = UCC_FAST_RX_ENCODING_NRZ, | |
56 | .tcrc = UCC_FAST_16_BIT_CRC, | |
57 | .synl = UCC_FAST_SYNC_LEN_NOT_USED, | |
58 | }, | |
59 | ||
60 | .si_info = { | |
61 | #ifdef TDM_PPPOHT_SLIC_MAXIN | |
62 | .simr_rfsd = 1, | |
63 | .simr_tfsd = 2, | |
64 | #else | |
65 | .simr_rfsd = 0, | |
66 | .simr_tfsd = 0, | |
67 | #endif | |
68 | .simr_crt = 0, | |
69 | .simr_sl = 0, | |
70 | .simr_ce = 1, | |
71 | .simr_fe = 1, | |
72 | .simr_gm = 0, | |
73 | }, | |
74 | }; | |
75 | ||
879b2462 | 76 | static struct ucc_tdm_info utdm_info[UCC_MAX_NUM]; |
c19b6d24 ZQ |
77 | |
78 | static int uhdlc_init(struct ucc_hdlc_private *priv) | |
79 | { | |
80 | struct ucc_tdm_info *ut_info; | |
81 | struct ucc_fast_info *uf_info; | |
82 | u32 cecr_subblock; | |
83 | u16 bd_status; | |
84 | int ret, i; | |
85 | void *bd_buffer; | |
86 | dma_addr_t bd_dma_addr; | |
87 | u32 riptr; | |
88 | u32 tiptr; | |
89 | u32 gumr; | |
90 | ||
91 | ut_info = priv->ut_info; | |
92 | uf_info = &ut_info->uf_info; | |
93 | ||
94 | if (priv->tsa) { | |
95 | uf_info->tsa = 1; | |
96 | uf_info->ctsp = 1; | |
040b7c94 DG |
97 | uf_info->cds = 1; |
98 | uf_info->ctss = 1; | |
99 | } else { | |
100 | uf_info->cds = 0; | |
101 | uf_info->ctsp = 0; | |
102 | uf_info->ctss = 0; | |
c19b6d24 | 103 | } |
067bb938 HB |
104 | |
105 | /* This sets HPM register in CMXUCR register which configures a | |
106 | * open drain connected HDLC bus | |
107 | */ | |
108 | if (priv->hdlc_bus) | |
109 | uf_info->brkpt_support = 1; | |
110 | ||
c19b6d24 ZQ |
111 | uf_info->uccm_mask = ((UCC_HDLC_UCCE_RXB | UCC_HDLC_UCCE_RXF | |
112 | UCC_HDLC_UCCE_TXB) << 16); | |
113 | ||
114 | ret = ucc_fast_init(uf_info, &priv->uccf); | |
115 | if (ret) { | |
116 | dev_err(priv->dev, "Failed to init uccf."); | |
117 | return ret; | |
118 | } | |
119 | ||
120 | priv->uf_regs = priv->uccf->uf_regs; | |
121 | ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX); | |
122 | ||
123 | /* Loopback mode */ | |
124 | if (priv->loopback) { | |
125 | dev_info(priv->dev, "Loopback Mode\n"); | |
54e9e087 HB |
126 | /* use the same clock when work in loopback */ |
127 | qe_setbrg(ut_info->uf_info.rx_clock, 20000000, 1); | |
128 | ||
c19b6d24 ZQ |
129 | gumr = ioread32be(&priv->uf_regs->gumr); |
130 | gumr |= (UCC_FAST_GUMR_LOOPBACK | UCC_FAST_GUMR_CDS | | |
131 | UCC_FAST_GUMR_TCI); | |
132 | gumr &= ~(UCC_FAST_GUMR_CTSP | UCC_FAST_GUMR_RSYN); | |
133 | iowrite32be(gumr, &priv->uf_regs->gumr); | |
134 | } | |
135 | ||
136 | /* Initialize SI */ | |
137 | if (priv->tsa) | |
138 | ucc_tdm_init(priv->utdm, priv->ut_info); | |
139 | ||
140 | /* Write to QE CECR, UCCx channel to Stop Transmission */ | |
141 | cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num); | |
142 | ret = qe_issue_cmd(QE_STOP_TX, cecr_subblock, | |
143 | QE_CR_PROTOCOL_UNSPECIFIED, 0); | |
144 | ||
145 | /* Set UPSMR normal mode (need fixed)*/ | |
146 | iowrite32be(0, &priv->uf_regs->upsmr); | |
147 | ||
067bb938 HB |
148 | /* hdlc_bus mode */ |
149 | if (priv->hdlc_bus) { | |
150 | u32 upsmr; | |
151 | ||
152 | dev_info(priv->dev, "HDLC bus Mode\n"); | |
153 | upsmr = ioread32be(&priv->uf_regs->upsmr); | |
154 | ||
155 | /* bus mode and retransmit enable, with collision window | |
156 | * set to 8 bytes | |
157 | */ | |
158 | upsmr |= UCC_HDLC_UPSMR_RTE | UCC_HDLC_UPSMR_BUS | | |
159 | UCC_HDLC_UPSMR_CW8; | |
160 | iowrite32be(upsmr, &priv->uf_regs->upsmr); | |
161 | ||
162 | /* explicitly disable CDS & CTSP */ | |
163 | gumr = ioread32be(&priv->uf_regs->gumr); | |
164 | gumr &= ~(UCC_FAST_GUMR_CDS | UCC_FAST_GUMR_CTSP); | |
165 | /* set automatic sync to explicitly ignore CD signal */ | |
166 | gumr |= UCC_FAST_GUMR_SYNL_AUTO; | |
167 | iowrite32be(gumr, &priv->uf_regs->gumr); | |
168 | } | |
169 | ||
c19b6d24 ZQ |
170 | priv->rx_ring_size = RX_BD_RING_LEN; |
171 | priv->tx_ring_size = TX_BD_RING_LEN; | |
172 | /* Alloc Rx BD */ | |
173 | priv->rx_bd_base = dma_alloc_coherent(priv->dev, | |
5b8aad93 | 174 | RX_BD_RING_LEN * sizeof(struct qe_bd), |
c19b6d24 ZQ |
175 | &priv->dma_rx_bd, GFP_KERNEL); |
176 | ||
177 | if (!priv->rx_bd_base) { | |
178 | dev_err(priv->dev, "Cannot allocate MURAM memory for RxBDs\n"); | |
179 | ret = -ENOMEM; | |
1efb597d | 180 | goto free_uccf; |
c19b6d24 ZQ |
181 | } |
182 | ||
183 | /* Alloc Tx BD */ | |
184 | priv->tx_bd_base = dma_alloc_coherent(priv->dev, | |
5b8aad93 | 185 | TX_BD_RING_LEN * sizeof(struct qe_bd), |
c19b6d24 ZQ |
186 | &priv->dma_tx_bd, GFP_KERNEL); |
187 | ||
188 | if (!priv->tx_bd_base) { | |
189 | dev_err(priv->dev, "Cannot allocate MURAM memory for TxBDs\n"); | |
190 | ret = -ENOMEM; | |
1efb597d | 191 | goto free_rx_bd; |
c19b6d24 ZQ |
192 | } |
193 | ||
194 | /* Alloc parameter ram for ucc hdlc */ | |
85deed56 | 195 | priv->ucc_pram_offset = qe_muram_alloc(sizeof(struct ucc_hdlc_param), |
c19b6d24 ZQ |
196 | ALIGNMENT_OF_UCC_HDLC_PRAM); |
197 | ||
fd800f64 | 198 | if (IS_ERR_VALUE(priv->ucc_pram_offset)) { |
24a24d07 | 199 | dev_err(priv->dev, "Can not allocate MURAM for hdlc parameter.\n"); |
c19b6d24 | 200 | ret = -ENOMEM; |
1efb597d | 201 | goto free_tx_bd; |
c19b6d24 ZQ |
202 | } |
203 | ||
6396bb22 KC |
204 | priv->rx_skbuff = kcalloc(priv->rx_ring_size, |
205 | sizeof(*priv->rx_skbuff), | |
c19b6d24 | 206 | GFP_KERNEL); |
695ed402 JJB |
207 | if (!priv->rx_skbuff) { |
208 | ret = -ENOMEM; | |
1efb597d | 209 | goto free_ucc_pram; |
695ed402 | 210 | } |
c19b6d24 | 211 | |
6396bb22 KC |
212 | priv->tx_skbuff = kcalloc(priv->tx_ring_size, |
213 | sizeof(*priv->tx_skbuff), | |
c19b6d24 | 214 | GFP_KERNEL); |
695ed402 JJB |
215 | if (!priv->tx_skbuff) { |
216 | ret = -ENOMEM; | |
1efb597d | 217 | goto free_rx_skbuff; |
695ed402 | 218 | } |
c19b6d24 ZQ |
219 | |
220 | priv->skb_curtx = 0; | |
221 | priv->skb_dirtytx = 0; | |
222 | priv->curtx_bd = priv->tx_bd_base; | |
223 | priv->dirty_tx = priv->tx_bd_base; | |
224 | priv->currx_bd = priv->rx_bd_base; | |
225 | priv->currx_bdnum = 0; | |
226 | ||
227 | /* init parameter base */ | |
228 | cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num); | |
229 | ret = qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, cecr_subblock, | |
230 | QE_CR_PROTOCOL_UNSPECIFIED, priv->ucc_pram_offset); | |
231 | ||
232 | priv->ucc_pram = (struct ucc_hdlc_param __iomem *) | |
233 | qe_muram_addr(priv->ucc_pram_offset); | |
234 | ||
235 | /* Zero out parameter ram */ | |
236 | memset_io(priv->ucc_pram, 0, sizeof(struct ucc_hdlc_param)); | |
237 | ||
238 | /* Alloc riptr, tiptr */ | |
239 | riptr = qe_muram_alloc(32, 32); | |
fd800f64 | 240 | if (IS_ERR_VALUE(riptr)) { |
c19b6d24 ZQ |
241 | dev_err(priv->dev, "Cannot allocate MURAM mem for Receive internal temp data pointer\n"); |
242 | ret = -ENOMEM; | |
1efb597d | 243 | goto free_tx_skbuff; |
c19b6d24 ZQ |
244 | } |
245 | ||
246 | tiptr = qe_muram_alloc(32, 32); | |
fd800f64 | 247 | if (IS_ERR_VALUE(tiptr)) { |
c19b6d24 ZQ |
248 | dev_err(priv->dev, "Cannot allocate MURAM mem for Transmit internal temp data pointer\n"); |
249 | ret = -ENOMEM; | |
1efb597d | 250 | goto free_riptr; |
c19b6d24 | 251 | } |
dc91735b RV |
252 | if (riptr != (u16)riptr || tiptr != (u16)tiptr) { |
253 | dev_err(priv->dev, "MURAM allocation out of addressable range\n"); | |
254 | ret = -ENOMEM; | |
255 | goto free_tiptr; | |
256 | } | |
c19b6d24 ZQ |
257 | |
258 | /* Set RIPTR, TIPTR */ | |
259 | iowrite16be(riptr, &priv->ucc_pram->riptr); | |
260 | iowrite16be(tiptr, &priv->ucc_pram->tiptr); | |
261 | ||
262 | /* Set MRBLR */ | |
263 | iowrite16be(MAX_RX_BUF_LENGTH, &priv->ucc_pram->mrblr); | |
264 | ||
265 | /* Set RBASE, TBASE */ | |
266 | iowrite32be(priv->dma_rx_bd, &priv->ucc_pram->rbase); | |
267 | iowrite32be(priv->dma_tx_bd, &priv->ucc_pram->tbase); | |
268 | ||
269 | /* Set RSTATE, TSTATE */ | |
270 | iowrite32be(BMR_GBL | BMR_BIG_ENDIAN, &priv->ucc_pram->rstate); | |
271 | iowrite32be(BMR_GBL | BMR_BIG_ENDIAN, &priv->ucc_pram->tstate); | |
272 | ||
273 | /* Set C_MASK, C_PRES for 16bit CRC */ | |
274 | iowrite32be(CRC_16BIT_MASK, &priv->ucc_pram->c_mask); | |
275 | iowrite32be(CRC_16BIT_PRES, &priv->ucc_pram->c_pres); | |
276 | ||
277 | iowrite16be(MAX_FRAME_LENGTH, &priv->ucc_pram->mflr); | |
278 | iowrite16be(DEFAULT_RFTHR, &priv->ucc_pram->rfthr); | |
279 | iowrite16be(DEFAULT_RFTHR, &priv->ucc_pram->rfcnt); | |
045f77ba | 280 | iowrite16be(priv->hmask, &priv->ucc_pram->hmask); |
c19b6d24 ZQ |
281 | iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr1); |
282 | iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr2); | |
283 | iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr3); | |
284 | iowrite16be(DEFAULT_HDLC_ADDR, &priv->ucc_pram->haddr4); | |
285 | ||
286 | /* Get BD buffer */ | |
750afb08 LC |
287 | bd_buffer = dma_alloc_coherent(priv->dev, |
288 | (RX_BD_RING_LEN + TX_BD_RING_LEN) * MAX_RX_BUF_LENGTH, | |
289 | &bd_dma_addr, GFP_KERNEL); | |
c19b6d24 ZQ |
290 | |
291 | if (!bd_buffer) { | |
292 | dev_err(priv->dev, "Could not allocate buffer descriptors\n"); | |
293 | ret = -ENOMEM; | |
1efb597d | 294 | goto free_tiptr; |
c19b6d24 ZQ |
295 | } |
296 | ||
c19b6d24 ZQ |
297 | priv->rx_buffer = bd_buffer; |
298 | priv->tx_buffer = bd_buffer + RX_BD_RING_LEN * MAX_RX_BUF_LENGTH; | |
299 | ||
300 | priv->dma_rx_addr = bd_dma_addr; | |
301 | priv->dma_tx_addr = bd_dma_addr + RX_BD_RING_LEN * MAX_RX_BUF_LENGTH; | |
302 | ||
303 | for (i = 0; i < RX_BD_RING_LEN; i++) { | |
304 | if (i < (RX_BD_RING_LEN - 1)) | |
305 | bd_status = R_E_S | R_I_S; | |
306 | else | |
307 | bd_status = R_E_S | R_I_S | R_W_S; | |
308 | ||
309 | iowrite16be(bd_status, &priv->rx_bd_base[i].status); | |
310 | iowrite32be(priv->dma_rx_addr + i * MAX_RX_BUF_LENGTH, | |
311 | &priv->rx_bd_base[i].buf); | |
312 | } | |
313 | ||
314 | for (i = 0; i < TX_BD_RING_LEN; i++) { | |
315 | if (i < (TX_BD_RING_LEN - 1)) | |
316 | bd_status = T_I_S | T_TC_S; | |
317 | else | |
318 | bd_status = T_I_S | T_TC_S | T_W_S; | |
319 | ||
320 | iowrite16be(bd_status, &priv->tx_bd_base[i].status); | |
321 | iowrite32be(priv->dma_tx_addr + i * MAX_RX_BUF_LENGTH, | |
322 | &priv->tx_bd_base[i].buf); | |
323 | } | |
324 | ||
325 | return 0; | |
326 | ||
1efb597d | 327 | free_tiptr: |
c19b6d24 | 328 | qe_muram_free(tiptr); |
1efb597d | 329 | free_riptr: |
c19b6d24 | 330 | qe_muram_free(riptr); |
1efb597d | 331 | free_tx_skbuff: |
c19b6d24 | 332 | kfree(priv->tx_skbuff); |
1efb597d | 333 | free_rx_skbuff: |
c19b6d24 | 334 | kfree(priv->rx_skbuff); |
1efb597d | 335 | free_ucc_pram: |
c19b6d24 | 336 | qe_muram_free(priv->ucc_pram_offset); |
1efb597d | 337 | free_tx_bd: |
c19b6d24 | 338 | dma_free_coherent(priv->dev, |
5b8aad93 | 339 | TX_BD_RING_LEN * sizeof(struct qe_bd), |
c19b6d24 | 340 | priv->tx_bd_base, priv->dma_tx_bd); |
1efb597d | 341 | free_rx_bd: |
c19b6d24 | 342 | dma_free_coherent(priv->dev, |
5b8aad93 | 343 | RX_BD_RING_LEN * sizeof(struct qe_bd), |
c19b6d24 | 344 | priv->rx_bd_base, priv->dma_rx_bd); |
1efb597d | 345 | free_uccf: |
c19b6d24 ZQ |
346 | ucc_fast_free(priv->uccf); |
347 | ||
348 | return ret; | |
349 | } | |
350 | ||
351 | static netdev_tx_t ucc_hdlc_tx(struct sk_buff *skb, struct net_device *dev) | |
352 | { | |
353 | hdlc_device *hdlc = dev_to_hdlc(dev); | |
354 | struct ucc_hdlc_private *priv = (struct ucc_hdlc_private *)hdlc->priv; | |
355 | struct qe_bd __iomem *bd; | |
356 | u16 bd_status; | |
357 | unsigned long flags; | |
c19b6d24 ZQ |
358 | u16 *proto_head; |
359 | ||
360 | switch (dev->type) { | |
361 | case ARPHRD_RAWHDLC: | |
362 | if (skb_headroom(skb) < HDLC_HEAD_LEN) { | |
363 | dev->stats.tx_dropped++; | |
364 | dev_kfree_skb(skb); | |
365 | netdev_err(dev, "No enough space for hdlc head\n"); | |
366 | return -ENOMEM; | |
367 | } | |
368 | ||
369 | skb_push(skb, HDLC_HEAD_LEN); | |
370 | ||
371 | proto_head = (u16 *)skb->data; | |
372 | *proto_head = htons(DEFAULT_HDLC_HEAD); | |
373 | ||
374 | dev->stats.tx_bytes += skb->len; | |
375 | break; | |
376 | ||
377 | case ARPHRD_PPP: | |
378 | proto_head = (u16 *)skb->data; | |
379 | if (*proto_head != htons(DEFAULT_PPP_HEAD)) { | |
380 | dev->stats.tx_dropped++; | |
381 | dev_kfree_skb(skb); | |
382 | netdev_err(dev, "Wrong ppp header\n"); | |
383 | return -ENOMEM; | |
384 | } | |
385 | ||
386 | dev->stats.tx_bytes += skb->len; | |
387 | break; | |
388 | ||
8978ca7c DG |
389 | case ARPHRD_ETHER: |
390 | dev->stats.tx_bytes += skb->len; | |
391 | break; | |
392 | ||
c19b6d24 ZQ |
393 | default: |
394 | dev->stats.tx_dropped++; | |
395 | dev_kfree_skb(skb); | |
396 | return -ENOMEM; | |
397 | } | |
2e7ad56a | 398 | netdev_sent_queue(dev, skb->len); |
c19b6d24 ZQ |
399 | spin_lock_irqsave(&priv->lock, flags); |
400 | ||
401 | /* Start from the next BD that should be filled */ | |
402 | bd = priv->curtx_bd; | |
403 | bd_status = ioread16be(&bd->status); | |
404 | /* Save the skb pointer so we can free it later */ | |
405 | priv->tx_skbuff[priv->skb_curtx] = skb; | |
406 | ||
407 | /* Update the current skb pointer (wrapping if this was the last) */ | |
408 | priv->skb_curtx = | |
409 | (priv->skb_curtx + 1) & TX_RING_MOD_MASK(TX_BD_RING_LEN); | |
410 | ||
411 | /* copy skb data to tx buffer for sdma processing */ | |
412 | memcpy(priv->tx_buffer + (be32_to_cpu(bd->buf) - priv->dma_tx_addr), | |
413 | skb->data, skb->len); | |
414 | ||
415 | /* set bd status and length */ | |
416 | bd_status = (bd_status & T_W_S) | T_R_S | T_I_S | T_L_S | T_TC_S; | |
417 | ||
c19b6d24 | 418 | iowrite16be(skb->len, &bd->length); |
02bb56dd | 419 | iowrite16be(bd_status, &bd->status); |
c19b6d24 ZQ |
420 | |
421 | /* Move to next BD in the ring */ | |
422 | if (!(bd_status & T_W_S)) | |
423 | bd += 1; | |
424 | else | |
425 | bd = priv->tx_bd_base; | |
426 | ||
427 | if (bd == priv->dirty_tx) { | |
428 | if (!netif_queue_stopped(dev)) | |
429 | netif_stop_queue(dev); | |
430 | } | |
431 | ||
432 | priv->curtx_bd = bd; | |
433 | ||
434 | spin_unlock_irqrestore(&priv->lock, flags); | |
435 | ||
436 | return NETDEV_TX_OK; | |
437 | } | |
438 | ||
ba59d570 MT |
439 | static int hdlc_tx_restart(struct ucc_hdlc_private *priv) |
440 | { | |
441 | u32 cecr_subblock; | |
442 | ||
443 | cecr_subblock = | |
444 | ucc_fast_get_qe_cr_subblock(priv->ut_info->uf_info.ucc_num); | |
445 | ||
446 | qe_issue_cmd(QE_RESTART_TX, cecr_subblock, | |
447 | QE_CR_PROTOCOL_UNSPECIFIED, 0); | |
448 | return 0; | |
449 | } | |
450 | ||
c19b6d24 ZQ |
451 | static int hdlc_tx_done(struct ucc_hdlc_private *priv) |
452 | { | |
453 | /* Start from the next BD that should be filled */ | |
454 | struct net_device *dev = priv->ndev; | |
2e7ad56a MT |
455 | unsigned int bytes_sent = 0; |
456 | int howmany = 0; | |
c19b6d24 ZQ |
457 | struct qe_bd *bd; /* BD pointer */ |
458 | u16 bd_status; | |
ba59d570 | 459 | int tx_restart = 0; |
c19b6d24 ZQ |
460 | |
461 | bd = priv->dirty_tx; | |
462 | bd_status = ioread16be(&bd->status); | |
463 | ||
464 | /* Normal processing. */ | |
465 | while ((bd_status & T_R_S) == 0) { | |
466 | struct sk_buff *skb; | |
467 | ||
ba59d570 MT |
468 | if (bd_status & T_UN_S) { /* Underrun */ |
469 | dev->stats.tx_fifo_errors++; | |
470 | tx_restart = 1; | |
471 | } | |
472 | if (bd_status & T_CT_S) { /* Carrier lost */ | |
473 | dev->stats.tx_carrier_errors++; | |
474 | tx_restart = 1; | |
475 | } | |
476 | ||
c19b6d24 ZQ |
477 | /* BD contains already transmitted buffer. */ |
478 | /* Handle the transmitted buffer and release */ | |
479 | /* the BD to be used with the current frame */ | |
480 | ||
481 | skb = priv->tx_skbuff[priv->skb_dirtytx]; | |
482 | if (!skb) | |
483 | break; | |
2e7ad56a MT |
484 | howmany++; |
485 | bytes_sent += skb->len; | |
c19b6d24 ZQ |
486 | dev->stats.tx_packets++; |
487 | memset(priv->tx_buffer + | |
488 | (be32_to_cpu(bd->buf) - priv->dma_tx_addr), | |
489 | 0, skb->len); | |
7c3850ad | 490 | dev_consume_skb_irq(skb); |
c19b6d24 ZQ |
491 | |
492 | priv->tx_skbuff[priv->skb_dirtytx] = NULL; | |
493 | priv->skb_dirtytx = | |
494 | (priv->skb_dirtytx + | |
495 | 1) & TX_RING_MOD_MASK(TX_BD_RING_LEN); | |
496 | ||
497 | /* We freed a buffer, so now we can restart transmission */ | |
498 | if (netif_queue_stopped(dev)) | |
499 | netif_wake_queue(dev); | |
500 | ||
501 | /* Advance the confirmation BD pointer */ | |
502 | if (!(bd_status & T_W_S)) | |
503 | bd += 1; | |
504 | else | |
505 | bd = priv->tx_bd_base; | |
506 | bd_status = ioread16be(&bd->status); | |
507 | } | |
508 | priv->dirty_tx = bd; | |
509 | ||
ba59d570 MT |
510 | if (tx_restart) |
511 | hdlc_tx_restart(priv); | |
512 | ||
2e7ad56a | 513 | netdev_completed_queue(dev, howmany, bytes_sent); |
c19b6d24 ZQ |
514 | return 0; |
515 | } | |
516 | ||
517 | static int hdlc_rx_done(struct ucc_hdlc_private *priv, int rx_work_limit) | |
518 | { | |
519 | struct net_device *dev = priv->ndev; | |
66bb144b | 520 | struct sk_buff *skb = NULL; |
c19b6d24 ZQ |
521 | hdlc_device *hdlc = dev_to_hdlc(dev); |
522 | struct qe_bd *bd; | |
02bb56dd | 523 | u16 bd_status; |
c19b6d24 ZQ |
524 | u16 length, howmany = 0; |
525 | u8 *bdbuffer; | |
c19b6d24 ZQ |
526 | |
527 | bd = priv->currx_bd; | |
528 | bd_status = ioread16be(&bd->status); | |
529 | ||
530 | /* while there are received buffers and BD is full (~R_E) */ | |
531 | while (!((bd_status & (R_E_S)) || (--rx_work_limit < 0))) { | |
ba59d570 MT |
532 | if (bd_status & (RX_BD_ERRORS)) { |
533 | dev->stats.rx_errors++; | |
534 | ||
535 | if (bd_status & R_CD_S) | |
536 | dev->stats.collisions++; | |
537 | if (bd_status & R_OV_S) | |
538 | dev->stats.rx_fifo_errors++; | |
539 | if (bd_status & R_CR_S) | |
540 | dev->stats.rx_crc_errors++; | |
541 | if (bd_status & R_AB_S) | |
542 | dev->stats.rx_over_errors++; | |
543 | if (bd_status & R_NO_S) | |
544 | dev->stats.rx_frame_errors++; | |
545 | if (bd_status & R_LG_S) | |
546 | dev->stats.rx_length_errors++; | |
547 | ||
c19b6d24 ZQ |
548 | goto recycle; |
549 | } | |
550 | bdbuffer = priv->rx_buffer + | |
551 | (priv->currx_bdnum * MAX_RX_BUF_LENGTH); | |
552 | length = ioread16be(&bd->length); | |
553 | ||
c19b6d24 ZQ |
554 | switch (dev->type) { |
555 | case ARPHRD_RAWHDLC: | |
556 | bdbuffer += HDLC_HEAD_LEN; | |
557 | length -= (HDLC_HEAD_LEN + HDLC_CRC_SIZE); | |
558 | ||
559 | skb = dev_alloc_skb(length); | |
560 | if (!skb) { | |
561 | dev->stats.rx_dropped++; | |
562 | return -ENOMEM; | |
563 | } | |
564 | ||
565 | skb_put(skb, length); | |
566 | skb->len = length; | |
567 | skb->dev = dev; | |
568 | memcpy(skb->data, bdbuffer, length); | |
569 | break; | |
570 | ||
571 | case ARPHRD_PPP: | |
8978ca7c | 572 | case ARPHRD_ETHER: |
c19b6d24 ZQ |
573 | length -= HDLC_CRC_SIZE; |
574 | ||
575 | skb = dev_alloc_skb(length); | |
576 | if (!skb) { | |
577 | dev->stats.rx_dropped++; | |
578 | return -ENOMEM; | |
579 | } | |
580 | ||
581 | skb_put(skb, length); | |
582 | skb->len = length; | |
583 | skb->dev = dev; | |
584 | memcpy(skb->data, bdbuffer, length); | |
585 | break; | |
586 | } | |
587 | ||
588 | dev->stats.rx_packets++; | |
589 | dev->stats.rx_bytes += skb->len; | |
590 | howmany++; | |
591 | if (hdlc->proto) | |
592 | skb->protocol = hdlc_type_trans(skb, dev); | |
c19b6d24 ZQ |
593 | netif_receive_skb(skb); |
594 | ||
595 | recycle: | |
ba59d570 | 596 | iowrite16be((bd_status & R_W_S) | R_E_S | R_I_S, &bd->status); |
c19b6d24 ZQ |
597 | |
598 | /* update to point at the next bd */ | |
599 | if (bd_status & R_W_S) { | |
600 | priv->currx_bdnum = 0; | |
601 | bd = priv->rx_bd_base; | |
602 | } else { | |
603 | if (priv->currx_bdnum < (RX_BD_RING_LEN - 1)) | |
604 | priv->currx_bdnum += 1; | |
605 | else | |
606 | priv->currx_bdnum = RX_BD_RING_LEN - 1; | |
607 | ||
608 | bd += 1; | |
609 | } | |
610 | ||
611 | bd_status = ioread16be(&bd->status); | |
612 | } | |
613 | ||
614 | priv->currx_bd = bd; | |
615 | return howmany; | |
616 | } | |
617 | ||
618 | static int ucc_hdlc_poll(struct napi_struct *napi, int budget) | |
619 | { | |
620 | struct ucc_hdlc_private *priv = container_of(napi, | |
621 | struct ucc_hdlc_private, | |
622 | napi); | |
623 | int howmany; | |
624 | ||
625 | /* Tx event processing */ | |
626 | spin_lock(&priv->lock); | |
10515db5 | 627 | hdlc_tx_done(priv); |
c19b6d24 ZQ |
628 | spin_unlock(&priv->lock); |
629 | ||
630 | howmany = 0; | |
631 | howmany += hdlc_rx_done(priv, budget - howmany); | |
632 | ||
633 | if (howmany < budget) { | |
6ad20165 | 634 | napi_complete_done(napi, howmany); |
c19b6d24 ZQ |
635 | qe_setbits32(priv->uccf->p_uccm, |
636 | (UCCE_HDLC_RX_EVENTS | UCCE_HDLC_TX_EVENTS) << 16); | |
637 | } | |
638 | ||
639 | return howmany; | |
640 | } | |
641 | ||
642 | static irqreturn_t ucc_hdlc_irq_handler(int irq, void *dev_id) | |
643 | { | |
644 | struct ucc_hdlc_private *priv = (struct ucc_hdlc_private *)dev_id; | |
645 | struct net_device *dev = priv->ndev; | |
646 | struct ucc_fast_private *uccf; | |
647 | struct ucc_tdm_info *ut_info; | |
648 | u32 ucce; | |
649 | u32 uccm; | |
650 | ||
651 | ut_info = priv->ut_info; | |
652 | uccf = priv->uccf; | |
653 | ||
654 | ucce = ioread32be(uccf->p_ucce); | |
655 | uccm = ioread32be(uccf->p_uccm); | |
656 | ucce &= uccm; | |
657 | iowrite32be(ucce, uccf->p_ucce); | |
c19b6d24 ZQ |
658 | if (!ucce) |
659 | return IRQ_NONE; | |
660 | ||
661 | if ((ucce >> 16) & (UCCE_HDLC_RX_EVENTS | UCCE_HDLC_TX_EVENTS)) { | |
662 | if (napi_schedule_prep(&priv->napi)) { | |
663 | uccm &= ~((UCCE_HDLC_RX_EVENTS | UCCE_HDLC_TX_EVENTS) | |
664 | << 16); | |
665 | iowrite32be(uccm, uccf->p_uccm); | |
666 | __napi_schedule(&priv->napi); | |
667 | } | |
668 | } | |
669 | ||
670 | /* Errors and other events */ | |
671 | if (ucce >> 16 & UCC_HDLC_UCCE_BSY) | |
ba59d570 | 672 | dev->stats.rx_missed_errors++; |
c19b6d24 ZQ |
673 | if (ucce >> 16 & UCC_HDLC_UCCE_TXE) |
674 | dev->stats.tx_errors++; | |
675 | ||
676 | return IRQ_HANDLED; | |
677 | } | |
678 | ||
679 | static int uhdlc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
680 | { | |
681 | const size_t size = sizeof(te1_settings); | |
682 | te1_settings line; | |
683 | struct ucc_hdlc_private *priv = netdev_priv(dev); | |
684 | ||
685 | if (cmd != SIOCWANDEV) | |
686 | return hdlc_ioctl(dev, ifr, cmd); | |
687 | ||
688 | switch (ifr->ifr_settings.type) { | |
689 | case IF_GET_IFACE: | |
690 | ifr->ifr_settings.type = IF_IFACE_E1; | |
691 | if (ifr->ifr_settings.size < size) { | |
692 | ifr->ifr_settings.size = size; /* data size wanted */ | |
693 | return -ENOBUFS; | |
694 | } | |
2f43b9be | 695 | memset(&line, 0, sizeof(line)); |
c19b6d24 | 696 | line.clock_type = priv->clocking; |
c19b6d24 ZQ |
697 | |
698 | if (copy_to_user(ifr->ifr_settings.ifs_ifsu.sync, &line, size)) | |
699 | return -EFAULT; | |
700 | return 0; | |
701 | ||
702 | default: | |
703 | return hdlc_ioctl(dev, ifr, cmd); | |
704 | } | |
705 | } | |
706 | ||
707 | static int uhdlc_open(struct net_device *dev) | |
708 | { | |
709 | u32 cecr_subblock; | |
710 | hdlc_device *hdlc = dev_to_hdlc(dev); | |
711 | struct ucc_hdlc_private *priv = hdlc->priv; | |
712 | struct ucc_tdm *utdm = priv->utdm; | |
713 | ||
714 | if (priv->hdlc_busy != 1) { | |
715 | if (request_irq(priv->ut_info->uf_info.irq, | |
716 | ucc_hdlc_irq_handler, 0, "hdlc", priv)) | |
717 | return -ENODEV; | |
718 | ||
719 | cecr_subblock = ucc_fast_get_qe_cr_subblock( | |
720 | priv->ut_info->uf_info.ucc_num); | |
721 | ||
722 | qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock, | |
723 | QE_CR_PROTOCOL_UNSPECIFIED, 0); | |
724 | ||
725 | ucc_fast_enable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX); | |
726 | ||
727 | /* Enable the TDM port */ | |
728 | if (priv->tsa) | |
729 | utdm->si_regs->siglmr1_h |= (0x1 << utdm->tdm_port); | |
730 | ||
731 | priv->hdlc_busy = 1; | |
732 | netif_device_attach(priv->ndev); | |
733 | napi_enable(&priv->napi); | |
2e7ad56a | 734 | netdev_reset_queue(dev); |
c19b6d24 ZQ |
735 | netif_start_queue(dev); |
736 | hdlc_open(dev); | |
737 | } | |
738 | ||
739 | return 0; | |
740 | } | |
741 | ||
742 | static void uhdlc_memclean(struct ucc_hdlc_private *priv) | |
743 | { | |
744 | qe_muram_free(priv->ucc_pram->riptr); | |
745 | qe_muram_free(priv->ucc_pram->tiptr); | |
746 | ||
747 | if (priv->rx_bd_base) { | |
748 | dma_free_coherent(priv->dev, | |
5b8aad93 | 749 | RX_BD_RING_LEN * sizeof(struct qe_bd), |
c19b6d24 ZQ |
750 | priv->rx_bd_base, priv->dma_rx_bd); |
751 | ||
752 | priv->rx_bd_base = NULL; | |
753 | priv->dma_rx_bd = 0; | |
754 | } | |
755 | ||
756 | if (priv->tx_bd_base) { | |
757 | dma_free_coherent(priv->dev, | |
5b8aad93 | 758 | TX_BD_RING_LEN * sizeof(struct qe_bd), |
c19b6d24 ZQ |
759 | priv->tx_bd_base, priv->dma_tx_bd); |
760 | ||
761 | priv->tx_bd_base = NULL; | |
762 | priv->dma_tx_bd = 0; | |
763 | } | |
764 | ||
765 | if (priv->ucc_pram) { | |
766 | qe_muram_free(priv->ucc_pram_offset); | |
767 | priv->ucc_pram = NULL; | |
768 | priv->ucc_pram_offset = 0; | |
769 | } | |
770 | ||
771 | kfree(priv->rx_skbuff); | |
772 | priv->rx_skbuff = NULL; | |
773 | ||
774 | kfree(priv->tx_skbuff); | |
775 | priv->tx_skbuff = NULL; | |
776 | ||
777 | if (priv->uf_regs) { | |
778 | iounmap(priv->uf_regs); | |
779 | priv->uf_regs = NULL; | |
780 | } | |
781 | ||
782 | if (priv->uccf) { | |
783 | ucc_fast_free(priv->uccf); | |
784 | priv->uccf = NULL; | |
785 | } | |
786 | ||
787 | if (priv->rx_buffer) { | |
788 | dma_free_coherent(priv->dev, | |
789 | RX_BD_RING_LEN * MAX_RX_BUF_LENGTH, | |
790 | priv->rx_buffer, priv->dma_rx_addr); | |
791 | priv->rx_buffer = NULL; | |
792 | priv->dma_rx_addr = 0; | |
793 | } | |
794 | ||
795 | if (priv->tx_buffer) { | |
796 | dma_free_coherent(priv->dev, | |
797 | TX_BD_RING_LEN * MAX_RX_BUF_LENGTH, | |
798 | priv->tx_buffer, priv->dma_tx_addr); | |
799 | priv->tx_buffer = NULL; | |
800 | priv->dma_tx_addr = 0; | |
801 | } | |
802 | } | |
803 | ||
804 | static int uhdlc_close(struct net_device *dev) | |
805 | { | |
806 | struct ucc_hdlc_private *priv = dev_to_hdlc(dev)->priv; | |
807 | struct ucc_tdm *utdm = priv->utdm; | |
808 | u32 cecr_subblock; | |
809 | ||
810 | napi_disable(&priv->napi); | |
811 | cecr_subblock = ucc_fast_get_qe_cr_subblock( | |
812 | priv->ut_info->uf_info.ucc_num); | |
813 | ||
814 | qe_issue_cmd(QE_GRACEFUL_STOP_TX, cecr_subblock, | |
815 | (u8)QE_CR_PROTOCOL_UNSPECIFIED, 0); | |
816 | qe_issue_cmd(QE_CLOSE_RX_BD, cecr_subblock, | |
817 | (u8)QE_CR_PROTOCOL_UNSPECIFIED, 0); | |
818 | ||
819 | if (priv->tsa) | |
820 | utdm->si_regs->siglmr1_h &= ~(0x1 << utdm->tdm_port); | |
821 | ||
822 | ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX); | |
823 | ||
824 | free_irq(priv->ut_info->uf_info.irq, priv); | |
825 | netif_stop_queue(dev); | |
2e7ad56a | 826 | netdev_reset_queue(dev); |
c19b6d24 ZQ |
827 | priv->hdlc_busy = 0; |
828 | ||
829 | return 0; | |
830 | } | |
831 | ||
832 | static int ucc_hdlc_attach(struct net_device *dev, unsigned short encoding, | |
833 | unsigned short parity) | |
834 | { | |
835 | struct ucc_hdlc_private *priv = dev_to_hdlc(dev)->priv; | |
836 | ||
837 | if (encoding != ENCODING_NRZ && | |
838 | encoding != ENCODING_NRZI) | |
839 | return -EINVAL; | |
840 | ||
841 | if (parity != PARITY_NONE && | |
842 | parity != PARITY_CRC32_PR1_CCITT && | |
43a78e0e | 843 | parity != PARITY_CRC16_PR0_CCITT && |
c19b6d24 ZQ |
844 | parity != PARITY_CRC16_PR1_CCITT) |
845 | return -EINVAL; | |
846 | ||
847 | priv->encoding = encoding; | |
848 | priv->parity = parity; | |
849 | ||
850 | return 0; | |
851 | } | |
852 | ||
853 | #ifdef CONFIG_PM | |
854 | static void store_clk_config(struct ucc_hdlc_private *priv) | |
855 | { | |
856 | struct qe_mux *qe_mux_reg = &qe_immr->qmx; | |
857 | ||
858 | /* store si clk */ | |
859 | priv->cmxsi1cr_h = ioread32be(&qe_mux_reg->cmxsi1cr_h); | |
860 | priv->cmxsi1cr_l = ioread32be(&qe_mux_reg->cmxsi1cr_l); | |
861 | ||
862 | /* store si sync */ | |
863 | priv->cmxsi1syr = ioread32be(&qe_mux_reg->cmxsi1syr); | |
864 | ||
865 | /* store ucc clk */ | |
866 | memcpy_fromio(priv->cmxucr, qe_mux_reg->cmxucr, 4 * sizeof(u32)); | |
867 | } | |
868 | ||
869 | static void resume_clk_config(struct ucc_hdlc_private *priv) | |
870 | { | |
871 | struct qe_mux *qe_mux_reg = &qe_immr->qmx; | |
872 | ||
873 | memcpy_toio(qe_mux_reg->cmxucr, priv->cmxucr, 4 * sizeof(u32)); | |
874 | ||
875 | iowrite32be(priv->cmxsi1cr_h, &qe_mux_reg->cmxsi1cr_h); | |
876 | iowrite32be(priv->cmxsi1cr_l, &qe_mux_reg->cmxsi1cr_l); | |
877 | ||
878 | iowrite32be(priv->cmxsi1syr, &qe_mux_reg->cmxsi1syr); | |
879 | } | |
880 | ||
881 | static int uhdlc_suspend(struct device *dev) | |
882 | { | |
883 | struct ucc_hdlc_private *priv = dev_get_drvdata(dev); | |
884 | struct ucc_tdm_info *ut_info; | |
885 | struct ucc_fast __iomem *uf_regs; | |
886 | ||
887 | if (!priv) | |
888 | return -EINVAL; | |
889 | ||
890 | if (!netif_running(priv->ndev)) | |
891 | return 0; | |
892 | ||
893 | netif_device_detach(priv->ndev); | |
894 | napi_disable(&priv->napi); | |
895 | ||
896 | ut_info = priv->ut_info; | |
897 | uf_regs = priv->uf_regs; | |
898 | ||
899 | /* backup gumr guemr*/ | |
900 | priv->gumr = ioread32be(&uf_regs->gumr); | |
901 | priv->guemr = ioread8(&uf_regs->guemr); | |
902 | ||
903 | priv->ucc_pram_bak = kmalloc(sizeof(*priv->ucc_pram_bak), | |
904 | GFP_KERNEL); | |
905 | if (!priv->ucc_pram_bak) | |
906 | return -ENOMEM; | |
907 | ||
908 | /* backup HDLC parameter */ | |
909 | memcpy_fromio(priv->ucc_pram_bak, priv->ucc_pram, | |
910 | sizeof(struct ucc_hdlc_param)); | |
911 | ||
912 | /* store the clk configuration */ | |
913 | store_clk_config(priv); | |
914 | ||
915 | /* save power */ | |
916 | ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX); | |
917 | ||
c19b6d24 ZQ |
918 | return 0; |
919 | } | |
920 | ||
921 | static int uhdlc_resume(struct device *dev) | |
922 | { | |
923 | struct ucc_hdlc_private *priv = dev_get_drvdata(dev); | |
8c57a3a7 | 924 | struct ucc_tdm *utdm; |
c19b6d24 ZQ |
925 | struct ucc_tdm_info *ut_info; |
926 | struct ucc_fast __iomem *uf_regs; | |
927 | struct ucc_fast_private *uccf; | |
928 | struct ucc_fast_info *uf_info; | |
929 | int ret, i; | |
930 | u32 cecr_subblock; | |
931 | u16 bd_status; | |
932 | ||
933 | if (!priv) | |
934 | return -EINVAL; | |
935 | ||
936 | if (!netif_running(priv->ndev)) | |
937 | return 0; | |
938 | ||
8c57a3a7 | 939 | utdm = priv->utdm; |
c19b6d24 ZQ |
940 | ut_info = priv->ut_info; |
941 | uf_info = &ut_info->uf_info; | |
942 | uf_regs = priv->uf_regs; | |
943 | uccf = priv->uccf; | |
944 | ||
945 | /* restore gumr guemr */ | |
946 | iowrite8(priv->guemr, &uf_regs->guemr); | |
947 | iowrite32be(priv->gumr, &uf_regs->gumr); | |
948 | ||
949 | /* Set Virtual Fifo registers */ | |
950 | iowrite16be(uf_info->urfs, &uf_regs->urfs); | |
951 | iowrite16be(uf_info->urfet, &uf_regs->urfet); | |
952 | iowrite16be(uf_info->urfset, &uf_regs->urfset); | |
953 | iowrite16be(uf_info->utfs, &uf_regs->utfs); | |
954 | iowrite16be(uf_info->utfet, &uf_regs->utfet); | |
955 | iowrite16be(uf_info->utftt, &uf_regs->utftt); | |
956 | /* utfb, urfb are offsets from MURAM base */ | |
957 | iowrite32be(uccf->ucc_fast_tx_virtual_fifo_base_offset, &uf_regs->utfb); | |
958 | iowrite32be(uccf->ucc_fast_rx_virtual_fifo_base_offset, &uf_regs->urfb); | |
959 | ||
960 | /* Rx Tx and sync clock routing */ | |
961 | resume_clk_config(priv); | |
962 | ||
963 | iowrite32be(uf_info->uccm_mask, &uf_regs->uccm); | |
964 | iowrite32be(0xffffffff, &uf_regs->ucce); | |
965 | ||
966 | ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX); | |
967 | ||
968 | /* rebuild SIRAM */ | |
969 | if (priv->tsa) | |
970 | ucc_tdm_init(priv->utdm, priv->ut_info); | |
971 | ||
972 | /* Write to QE CECR, UCCx channel to Stop Transmission */ | |
973 | cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num); | |
974 | ret = qe_issue_cmd(QE_STOP_TX, cecr_subblock, | |
975 | (u8)QE_CR_PROTOCOL_UNSPECIFIED, 0); | |
976 | ||
977 | /* Set UPSMR normal mode */ | |
978 | iowrite32be(0, &uf_regs->upsmr); | |
979 | ||
980 | /* init parameter base */ | |
981 | cecr_subblock = ucc_fast_get_qe_cr_subblock(uf_info->ucc_num); | |
982 | ret = qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, cecr_subblock, | |
983 | QE_CR_PROTOCOL_UNSPECIFIED, priv->ucc_pram_offset); | |
984 | ||
985 | priv->ucc_pram = (struct ucc_hdlc_param __iomem *) | |
986 | qe_muram_addr(priv->ucc_pram_offset); | |
987 | ||
988 | /* restore ucc parameter */ | |
989 | memcpy_toio(priv->ucc_pram, priv->ucc_pram_bak, | |
990 | sizeof(struct ucc_hdlc_param)); | |
991 | kfree(priv->ucc_pram_bak); | |
992 | ||
993 | /* rebuild BD entry */ | |
994 | for (i = 0; i < RX_BD_RING_LEN; i++) { | |
995 | if (i < (RX_BD_RING_LEN - 1)) | |
996 | bd_status = R_E_S | R_I_S; | |
997 | else | |
998 | bd_status = R_E_S | R_I_S | R_W_S; | |
999 | ||
1000 | iowrite16be(bd_status, &priv->rx_bd_base[i].status); | |
1001 | iowrite32be(priv->dma_rx_addr + i * MAX_RX_BUF_LENGTH, | |
1002 | &priv->rx_bd_base[i].buf); | |
1003 | } | |
1004 | ||
1005 | for (i = 0; i < TX_BD_RING_LEN; i++) { | |
1006 | if (i < (TX_BD_RING_LEN - 1)) | |
1007 | bd_status = T_I_S | T_TC_S; | |
1008 | else | |
1009 | bd_status = T_I_S | T_TC_S | T_W_S; | |
1010 | ||
1011 | iowrite16be(bd_status, &priv->tx_bd_base[i].status); | |
1012 | iowrite32be(priv->dma_tx_addr + i * MAX_RX_BUF_LENGTH, | |
1013 | &priv->tx_bd_base[i].buf); | |
1014 | } | |
1015 | ||
1016 | /* if hdlc is busy enable TX and RX */ | |
1017 | if (priv->hdlc_busy == 1) { | |
1018 | cecr_subblock = ucc_fast_get_qe_cr_subblock( | |
1019 | priv->ut_info->uf_info.ucc_num); | |
1020 | ||
1021 | qe_issue_cmd(QE_INIT_TX_RX, cecr_subblock, | |
1022 | (u8)QE_CR_PROTOCOL_UNSPECIFIED, 0); | |
1023 | ||
1024 | ucc_fast_enable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX); | |
1025 | ||
1026 | /* Enable the TDM port */ | |
1027 | if (priv->tsa) | |
1028 | utdm->si_regs->siglmr1_h |= (0x1 << utdm->tdm_port); | |
1029 | } | |
1030 | ||
1031 | napi_enable(&priv->napi); | |
1032 | netif_device_attach(priv->ndev); | |
1033 | ||
1034 | return 0; | |
1035 | } | |
1036 | ||
1037 | static const struct dev_pm_ops uhdlc_pm_ops = { | |
1038 | .suspend = uhdlc_suspend, | |
1039 | .resume = uhdlc_resume, | |
1040 | .freeze = uhdlc_suspend, | |
1041 | .thaw = uhdlc_resume, | |
1042 | }; | |
1043 | ||
1044 | #define HDLC_PM_OPS (&uhdlc_pm_ops) | |
1045 | ||
1046 | #else | |
1047 | ||
1048 | #define HDLC_PM_OPS NULL | |
1049 | ||
1050 | #endif | |
ccb7bc0e DG |
1051 | static void uhdlc_tx_timeout(struct net_device *ndev) |
1052 | { | |
1053 | netdev_err(ndev, "%s\n", __func__); | |
1054 | } | |
1055 | ||
c19b6d24 ZQ |
1056 | static const struct net_device_ops uhdlc_ops = { |
1057 | .ndo_open = uhdlc_open, | |
1058 | .ndo_stop = uhdlc_close, | |
c19b6d24 ZQ |
1059 | .ndo_start_xmit = hdlc_start_xmit, |
1060 | .ndo_do_ioctl = uhdlc_ioctl, | |
ccb7bc0e | 1061 | .ndo_tx_timeout = uhdlc_tx_timeout, |
c19b6d24 ZQ |
1062 | }; |
1063 | ||
8d68100a WY |
1064 | static int hdlc_map_iomem(char *name, int init_flag, void __iomem **ptr) |
1065 | { | |
1066 | struct device_node *np; | |
1067 | struct platform_device *pdev; | |
1068 | struct resource *res; | |
1069 | static int siram_init_flag; | |
1070 | int ret = 0; | |
1071 | ||
1072 | np = of_find_compatible_node(NULL, NULL, name); | |
1073 | if (!np) | |
1074 | return -EINVAL; | |
1075 | ||
1076 | pdev = of_find_device_by_node(np); | |
1077 | if (!pdev) { | |
1078 | pr_err("%pOFn: failed to lookup pdev\n", np); | |
1079 | of_node_put(np); | |
1080 | return -EINVAL; | |
1081 | } | |
1082 | ||
1083 | of_node_put(np); | |
1084 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1085 | if (!res) { | |
1086 | ret = -EINVAL; | |
1087 | goto error_put_device; | |
1088 | } | |
1089 | *ptr = ioremap(res->start, resource_size(res)); | |
1090 | if (!*ptr) { | |
1091 | ret = -ENOMEM; | |
1092 | goto error_put_device; | |
1093 | } | |
1094 | ||
1095 | /* We've remapped the addresses, and we don't need the device any | |
1096 | * more, so we should release it. | |
1097 | */ | |
1098 | put_device(&pdev->dev); | |
1099 | ||
1100 | if (init_flag && siram_init_flag == 0) { | |
1101 | memset_io(*ptr, 0, resource_size(res)); | |
1102 | siram_init_flag = 1; | |
1103 | } | |
1104 | return 0; | |
1105 | ||
1106 | error_put_device: | |
1107 | put_device(&pdev->dev); | |
1108 | ||
1109 | return ret; | |
1110 | } | |
1111 | ||
c19b6d24 ZQ |
1112 | static int ucc_hdlc_probe(struct platform_device *pdev) |
1113 | { | |
1114 | struct device_node *np = pdev->dev.of_node; | |
1115 | struct ucc_hdlc_private *uhdlc_priv = NULL; | |
1116 | struct ucc_tdm_info *ut_info; | |
66bb144b | 1117 | struct ucc_tdm *utdm = NULL; |
c19b6d24 ZQ |
1118 | struct resource res; |
1119 | struct net_device *dev; | |
1120 | hdlc_device *hdlc; | |
1121 | int ucc_num; | |
1122 | const char *sprop; | |
1123 | int ret; | |
1124 | u32 val; | |
1125 | ||
1126 | ret = of_property_read_u32_index(np, "cell-index", 0, &val); | |
1127 | if (ret) { | |
1128 | dev_err(&pdev->dev, "Invalid ucc property\n"); | |
1129 | return -ENODEV; | |
1130 | } | |
1131 | ||
1132 | ucc_num = val - 1; | |
d8d74777 | 1133 | if (ucc_num > (UCC_MAX_NUM - 1) || ucc_num < 0) { |
c19b6d24 ZQ |
1134 | dev_err(&pdev->dev, ": Invalid UCC num\n"); |
1135 | return -EINVAL; | |
1136 | } | |
1137 | ||
1138 | memcpy(&utdm_info[ucc_num], &utdm_primary_info, | |
1139 | sizeof(utdm_primary_info)); | |
1140 | ||
1141 | ut_info = &utdm_info[ucc_num]; | |
1142 | ut_info->uf_info.ucc_num = ucc_num; | |
1143 | ||
1144 | sprop = of_get_property(np, "rx-clock-name", NULL); | |
1145 | if (sprop) { | |
1146 | ut_info->uf_info.rx_clock = qe_clock_source(sprop); | |
1147 | if ((ut_info->uf_info.rx_clock < QE_CLK_NONE) || | |
1148 | (ut_info->uf_info.rx_clock > QE_CLK24)) { | |
1149 | dev_err(&pdev->dev, "Invalid rx-clock-name property\n"); | |
1150 | return -EINVAL; | |
1151 | } | |
1152 | } else { | |
1153 | dev_err(&pdev->dev, "Invalid rx-clock-name property\n"); | |
1154 | return -EINVAL; | |
1155 | } | |
1156 | ||
1157 | sprop = of_get_property(np, "tx-clock-name", NULL); | |
1158 | if (sprop) { | |
1159 | ut_info->uf_info.tx_clock = qe_clock_source(sprop); | |
1160 | if ((ut_info->uf_info.tx_clock < QE_CLK_NONE) || | |
1161 | (ut_info->uf_info.tx_clock > QE_CLK24)) { | |
1162 | dev_err(&pdev->dev, "Invalid tx-clock-name property\n"); | |
1163 | return -EINVAL; | |
1164 | } | |
1165 | } else { | |
1166 | dev_err(&pdev->dev, "Invalid tx-clock-name property\n"); | |
1167 | return -EINVAL; | |
1168 | } | |
1169 | ||
c19b6d24 ZQ |
1170 | ret = of_address_to_resource(np, 0, &res); |
1171 | if (ret) | |
1172 | return -EINVAL; | |
1173 | ||
1174 | ut_info->uf_info.regs = res.start; | |
1175 | ut_info->uf_info.irq = irq_of_parse_and_map(np, 0); | |
1176 | ||
1177 | uhdlc_priv = kzalloc(sizeof(*uhdlc_priv), GFP_KERNEL); | |
1178 | if (!uhdlc_priv) { | |
1efb597d | 1179 | return -ENOMEM; |
c19b6d24 ZQ |
1180 | } |
1181 | ||
1182 | dev_set_drvdata(&pdev->dev, uhdlc_priv); | |
1183 | uhdlc_priv->dev = &pdev->dev; | |
1184 | uhdlc_priv->ut_info = ut_info; | |
1185 | ||
1186 | if (of_get_property(np, "fsl,tdm-interface", NULL)) | |
1187 | uhdlc_priv->tsa = 1; | |
1188 | ||
1189 | if (of_get_property(np, "fsl,ucc-internal-loopback", NULL)) | |
1190 | uhdlc_priv->loopback = 1; | |
1191 | ||
067bb938 HB |
1192 | if (of_get_property(np, "fsl,hdlc-bus", NULL)) |
1193 | uhdlc_priv->hdlc_bus = 1; | |
1194 | ||
c19b6d24 ZQ |
1195 | if (uhdlc_priv->tsa == 1) { |
1196 | utdm = kzalloc(sizeof(*utdm), GFP_KERNEL); | |
1197 | if (!utdm) { | |
1198 | ret = -ENOMEM; | |
1199 | dev_err(&pdev->dev, "No mem to alloc ucc tdm data\n"); | |
1efb597d | 1200 | goto free_uhdlc_priv; |
c19b6d24 ZQ |
1201 | } |
1202 | uhdlc_priv->utdm = utdm; | |
1203 | ret = ucc_of_parse_tdm(np, utdm, ut_info); | |
1204 | if (ret) | |
1efb597d | 1205 | goto free_utdm; |
8d68100a WY |
1206 | |
1207 | ret = hdlc_map_iomem("fsl,t1040-qe-si", 0, | |
1208 | (void __iomem **)&utdm->si_regs); | |
1209 | if (ret) | |
1210 | goto free_utdm; | |
1211 | ret = hdlc_map_iomem("fsl,t1040-qe-siram", 1, | |
1212 | (void __iomem **)&utdm->siram); | |
1213 | if (ret) | |
1214 | goto unmap_si_regs; | |
c19b6d24 ZQ |
1215 | } |
1216 | ||
045f77ba DG |
1217 | if (of_property_read_u16(np, "fsl,hmask", &uhdlc_priv->hmask)) |
1218 | uhdlc_priv->hmask = DEFAULT_ADDR_MASK; | |
1219 | ||
c19b6d24 ZQ |
1220 | ret = uhdlc_init(uhdlc_priv); |
1221 | if (ret) { | |
1222 | dev_err(&pdev->dev, "Failed to init uhdlc\n"); | |
8d68100a | 1223 | goto undo_uhdlc_init; |
c19b6d24 ZQ |
1224 | } |
1225 | ||
1226 | dev = alloc_hdlcdev(uhdlc_priv); | |
1227 | if (!dev) { | |
1228 | ret = -ENOMEM; | |
1229 | pr_err("ucc_hdlc: unable to allocate memory\n"); | |
1efb597d | 1230 | goto undo_uhdlc_init; |
c19b6d24 ZQ |
1231 | } |
1232 | ||
1233 | uhdlc_priv->ndev = dev; | |
1234 | hdlc = dev_to_hdlc(dev); | |
1235 | dev->tx_queue_len = 16; | |
1236 | dev->netdev_ops = &uhdlc_ops; | |
ccb7bc0e | 1237 | dev->watchdog_timeo = 2 * HZ; |
c19b6d24 ZQ |
1238 | hdlc->attach = ucc_hdlc_attach; |
1239 | hdlc->xmit = ucc_hdlc_tx; | |
1240 | netif_napi_add(dev, &uhdlc_priv->napi, ucc_hdlc_poll, 32); | |
1241 | if (register_hdlc_device(dev)) { | |
1242 | ret = -ENOBUFS; | |
1243 | pr_err("ucc_hdlc: unable to register hdlc device\n"); | |
1efb597d | 1244 | goto free_dev; |
c19b6d24 ZQ |
1245 | } |
1246 | ||
1247 | return 0; | |
1248 | ||
1efb597d ZQ |
1249 | free_dev: |
1250 | free_netdev(dev); | |
1251 | undo_uhdlc_init: | |
8d68100a WY |
1252 | iounmap(utdm->siram); |
1253 | unmap_si_regs: | |
1254 | iounmap(utdm->si_regs); | |
1efb597d | 1255 | free_utdm: |
c19b6d24 ZQ |
1256 | if (uhdlc_priv->tsa) |
1257 | kfree(utdm); | |
1efb597d | 1258 | free_uhdlc_priv: |
c19b6d24 | 1259 | kfree(uhdlc_priv); |
c19b6d24 ZQ |
1260 | return ret; |
1261 | } | |
1262 | ||
1263 | static int ucc_hdlc_remove(struct platform_device *pdev) | |
1264 | { | |
1265 | struct ucc_hdlc_private *priv = dev_get_drvdata(&pdev->dev); | |
1266 | ||
1267 | uhdlc_memclean(priv); | |
1268 | ||
1269 | if (priv->utdm->si_regs) { | |
1270 | iounmap(priv->utdm->si_regs); | |
1271 | priv->utdm->si_regs = NULL; | |
1272 | } | |
1273 | ||
1274 | if (priv->utdm->siram) { | |
1275 | iounmap(priv->utdm->siram); | |
1276 | priv->utdm->siram = NULL; | |
1277 | } | |
1278 | kfree(priv); | |
1279 | ||
1280 | dev_info(&pdev->dev, "UCC based hdlc module removed\n"); | |
1281 | ||
1282 | return 0; | |
1283 | } | |
1284 | ||
1285 | static const struct of_device_id fsl_ucc_hdlc_of_match[] = { | |
1286 | { | |
1287 | .compatible = "fsl,ucc-hdlc", | |
1288 | }, | |
1289 | {}, | |
1290 | }; | |
1291 | ||
1292 | MODULE_DEVICE_TABLE(of, fsl_ucc_hdlc_of_match); | |
1293 | ||
1294 | static struct platform_driver ucc_hdlc_driver = { | |
1295 | .probe = ucc_hdlc_probe, | |
1296 | .remove = ucc_hdlc_remove, | |
1297 | .driver = { | |
c19b6d24 ZQ |
1298 | .name = DRV_NAME, |
1299 | .pm = HDLC_PM_OPS, | |
1300 | .of_match_table = fsl_ucc_hdlc_of_match, | |
1301 | }, | |
1302 | }; | |
1303 | ||
459421cc | 1304 | module_platform_driver(ucc_hdlc_driver); |
74179d44 | 1305 | MODULE_LICENSE("GPL"); |