[mirror_ubuntu-bionic-kernel.git] / drivers / net / wan / fsl_ucc_hdlc.h

/* Freescale QUICC Engine HDLC Device Driver
 *
 * Copyright 2014 Freescale Semiconductor Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#ifndef _UCC_HDLC_H_
#define _UCC_HDLC_H_

#include <linux/kernel.h>
#include <linux/list.h>

#include <soc/fsl/qe/immap_qe.h>
#include <soc/fsl/qe/qe.h>

#include <soc/fsl/qe/ucc.h>
#include <soc/fsl/qe/ucc_fast.h>

/* UCC HDLC event register */
#define UCCE_HDLC_RX_EVENTS	\
(UCC_HDLC_UCCE_RXF | UCC_HDLC_UCCE_RXB | UCC_HDLC_UCCE_BSY)
#define UCCE_HDLC_TX_EVENTS	(UCC_HDLC_UCCE_TXB | UCC_HDLC_UCCE_TXE)

struct ucc_hdlc_param {
	__be16 riptr;
	__be16 tiptr;
	__be16 res0;
	__be16 mrblr;
	__be32 rstate;
	__be32 rbase;
	__be16 rbdstat;
	__be16 rbdlen;
	__be32 rdptr;
	__be32 tstate;
	__be32 tbase;
	__be16 tbdstat;
	__be16 tbdlen;
	__be32 tdptr;
	__be32 rbptr;
	__be32 tbptr;
	__be32 rcrc;
	__be32 res1;
	__be32 tcrc;
	__be32 res2;
	__be32 res3;
	__be32 c_mask;
	__be32 c_pres;
	__be16 disfc;
	__be16 crcec;
	__be16 abtsc;
	__be16 nmarc;
	__be32 max_cnt;
	__be16 mflr;
	__be16 rfthr;
	__be16 rfcnt;
	__be16 hmask;
	__be16 haddr1;
	__be16 haddr2;
	__be16 haddr3;
	__be16 haddr4;
	__be16 ts_tmp;
	__be16 tmp_mb;
};

struct ucc_hdlc_private {
	struct ucc_tdm	*utdm;
	struct ucc_tdm_info *ut_info;
	struct ucc_fast_private *uccf;
	struct device *dev;
	struct net_device *ndev;
	struct napi_struct napi;
	struct ucc_fast __iomem *uf_regs;	/* UCC Fast registers */
	struct ucc_hdlc_param __iomem *ucc_pram;
	u16 tsa;
	bool hdlc_busy;
	bool loopback;

	u8 *tx_buffer;
	u8 *rx_buffer;
	dma_addr_t dma_tx_addr;
	dma_addr_t dma_rx_addr;

	struct qe_bd *tx_bd_base;
	struct qe_bd *rx_bd_base;
	dma_addr_t dma_tx_bd;
	dma_addr_t dma_rx_bd;
	struct qe_bd *curtx_bd;
	struct qe_bd *currx_bd;
	struct qe_bd *dirty_tx;
	u16 currx_bdnum;

	struct sk_buff **tx_skbuff;
	struct sk_buff **rx_skbuff;
	u16 skb_curtx;
	u16 skb_currx;
	unsigned short skb_dirtytx;

	unsigned short tx_ring_size;
	unsigned short rx_ring_size;
	u32 ucc_pram_offset;

	unsigned short encoding;
	unsigned short parity;
	u32 clocking;
	spinlock_t lock;	/* lock for Tx BD and Tx buffer */
#ifdef CONFIG_PM
	struct ucc_hdlc_param *ucc_pram_bak;
	u32 gumr;
	u8 guemr;
	u32 cmxsi1cr_l, cmxsi1cr_h;
	u32 cmxsi1syr;
	u32 cmxucr[4];
#endif
};

#define TX_BD_RING_LEN	0x10
#define RX_BD_RING_LEN	0x20
#define RX_CLEAN_MAX	0x10
#define NUM_OF_BUF	4
#define MAX_RX_BUF_LENGTH	(48 * 0x20)
#define MAX_FRAME_LENGTH	(MAX_RX_BUF_LENGTH + 8)
#define ALIGNMENT_OF_UCC_HDLC_PRAM	64
#define SI_BANK_SIZE	128
#define MAX_HDLC_NUM	4
#define HDLC_HEAD_LEN	2
#define HDLC_CRC_SIZE	2
#define TX_RING_MOD_MASK(size) (size - 1)
#define RX_RING_MOD_MASK(size) (size - 1)

#define HDLC_HEAD_MASK		0x0000
#define DEFAULT_HDLC_HEAD	0xff44
#define DEFAULT_ADDR_MASK	0x00ff
#define DEFAULT_HDLC_ADDR	0x00ff

#define BMR_GBL			0x20000000
#define BMR_BIG_ENDIAN		0x10000000
#define CRC_16BIT_MASK		0x0000F0B8
#define CRC_16BIT_PRES		0x0000FFFF
#define DEFAULT_RFTHR		1

#define DEFAULT_PPP_HEAD    0xff03

#endif
Commit	Line	Data
c19b6d24 ZQ	1	/* Freescale QUICC Engine HDLC Device Driver
	2	*
	3	* Copyright 2014 Freescale Semiconductor Inc.
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of the GNU General Public License as published by the
	7	* Free Software Foundation; either version 2 of the License, or (at your
	8	* option) any later version.
	9	*/
	10
c5739767 AZ	11	#ifndef _UCC_HDLC_H_
c5739767 AZ	12	#define _UCC_HDLC_H_
c19b6d24 ZQ	13
	14	#include <linux/kernel.h>
	15	#include <linux/list.h>
	16
	17	#include <soc/fsl/qe/immap_qe.h>
	18	#include <soc/fsl/qe/qe.h>
	19
	20	#include <soc/fsl/qe/ucc.h>
	21	#include <soc/fsl/qe/ucc_fast.h>
	22
	23	/* UCC HDLC event register */
	24	#define UCCE_HDLC_RX_EVENTS \
	25	(UCC_HDLC_UCCE_RXF \| UCC_HDLC_UCCE_RXB \| UCC_HDLC_UCCE_BSY)
	26	#define UCCE_HDLC_TX_EVENTS (UCC_HDLC_UCCE_TXB \| UCC_HDLC_UCCE_TXE)
	27
	28	struct ucc_hdlc_param {
	29	__be16 riptr;
	30	__be16 tiptr;
	31	__be16 res0;
	32	__be16 mrblr;
	33	__be32 rstate;
	34	__be32 rbase;
	35	__be16 rbdstat;
	36	__be16 rbdlen;
	37	__be32 rdptr;
	38	__be32 tstate;
	39	__be32 tbase;
	40	__be16 tbdstat;
	41	__be16 tbdlen;
	42	__be32 tdptr;
	43	__be32 rbptr;
	44	__be32 tbptr;
	45	__be32 rcrc;
	46	__be32 res1;
	47	__be32 tcrc;
	48	__be32 res2;
	49	__be32 res3;
	50	__be32 c_mask;
	51	__be32 c_pres;
	52	__be16 disfc;
	53	__be16 crcec;
	54	__be16 abtsc;
	55	__be16 nmarc;
	56	__be32 max_cnt;
	57	__be16 mflr;
	58	__be16 rfthr;
	59	__be16 rfcnt;
	60	__be16 hmask;
	61	__be16 haddr1;
	62	__be16 haddr2;
	63	__be16 haddr3;
	64	__be16 haddr4;
	65	__be16 ts_tmp;
	66	__be16 tmp_mb;
	67	};
	68
	69	struct ucc_hdlc_private {
	70	struct ucc_tdm *utdm;
	71	struct ucc_tdm_info *ut_info;
	72	struct ucc_fast_private *uccf;
	73	struct device *dev;
	74	struct net_device *ndev;
	75	struct napi_struct napi;
	76	struct ucc_fast __iomem uf_regs; / UCC Fast registers */
77	struct ucc_hdlc_param __iomem *ucc_pram;
78	u16 tsa;
79	bool hdlc_busy;
80	bool loopback;
81
82	u8 *tx_buffer;
83	u8 *rx_buffer;
84	dma_addr_t dma_tx_addr;
85	dma_addr_t dma_rx_addr;
86
87	struct qe_bd *tx_bd_base;
88	struct qe_bd *rx_bd_base;
89	dma_addr_t dma_tx_bd;
90	dma_addr_t dma_rx_bd;
91	struct qe_bd *curtx_bd;
92	struct qe_bd *currx_bd;
93	struct qe_bd *dirty_tx;
94	u16 currx_bdnum;
95
96	struct sk_buff **tx_skbuff;
97	struct sk_buff **rx_skbuff;
98	u16 skb_curtx;
99	u16 skb_currx;
100	unsigned short skb_dirtytx;
101
102	unsigned short tx_ring_size;
103	unsigned short rx_ring_size;
104	u32 ucc_pram_offset;
105
106	unsigned short encoding;
107	unsigned short parity;
108	u32 clocking;
109	spinlock_t lock; /* lock for Tx BD and Tx buffer */
110	#ifdef CONFIG_PM
111	struct ucc_hdlc_param *ucc_pram_bak;
112	u32 gumr;
113	u8 guemr;
114	u32 cmxsi1cr_l, cmxsi1cr_h;
115	u32 cmxsi1syr;
116	u32 cmxucr[4];
117	#endif
118	};
119
120	#define TX_BD_RING_LEN 0x10
121	#define RX_BD_RING_LEN 0x20
122	#define RX_CLEAN_MAX 0x10
123	#define NUM_OF_BUF 4
124	#define MAX_RX_BUF_LENGTH (48 * 0x20)
125	#define MAX_FRAME_LENGTH (MAX_RX_BUF_LENGTH + 8)
126	#define ALIGNMENT_OF_UCC_HDLC_PRAM 64
127	#define SI_BANK_SIZE 128
128	#define MAX_HDLC_NUM 4
129	#define HDLC_HEAD_LEN 2
130	#define HDLC_CRC_SIZE 2
131	#define TX_RING_MOD_MASK(size) (size - 1)
132	#define RX_RING_MOD_MASK(size) (size - 1)
133
134	#define HDLC_HEAD_MASK 0x0000
135	#define DEFAULT_HDLC_HEAD 0xff44
136	#define DEFAULT_ADDR_MASK 0x00ff
137	#define DEFAULT_HDLC_ADDR 0x00ff
138
139	#define BMR_GBL 0x20000000
140	#define BMR_BIG_ENDIAN 0x10000000
141	#define CRC_16BIT_MASK 0x0000F0B8
142	#define CRC_16BIT_PRES 0x0000FFFF
143	#define DEFAULT_RFTHR 1
144
145	#define DEFAULT_PPP_HEAD 0xff03
146
147	#endif