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1da177e4 LT |
1 | /* |
2 | * SDL Inc. RISCom/N2 synchronous serial card driver for Linux | |
3 | * | |
4 | * Copyright (C) 1998-2003 Krzysztof Halasa <khc@pm.waw.pl> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of version 2 of the GNU General Public License | |
8 | * as published by the Free Software Foundation. | |
9 | * | |
467c432a | 10 | * For information see <http://www.kernel.org/pub/linux/utils/net/hdlc/> |
1da177e4 LT |
11 | * |
12 | * Note: integrated CSU/DSU/DDS are not supported by this driver | |
13 | * | |
14 | * Sources of information: | |
15 | * Hitachi HD64570 SCA User's Manual | |
16 | * SDL Inc. PPP/HDLC/CISCO driver | |
17 | */ | |
18 | ||
19 | #include <linux/module.h> | |
20 | #include <linux/kernel.h> | |
86ae13b0 | 21 | #include <linux/capability.h> |
1da177e4 LT |
22 | #include <linux/slab.h> |
23 | #include <linux/types.h> | |
24 | #include <linux/fcntl.h> | |
25 | #include <linux/in.h> | |
26 | #include <linux/string.h> | |
27 | #include <linux/errno.h> | |
28 | #include <linux/init.h> | |
29 | #include <linux/ioport.h> | |
30 | #include <linux/moduleparam.h> | |
31 | #include <linux/netdevice.h> | |
32 | #include <linux/hdlc.h> | |
33 | #include <asm/io.h> | |
34 | #include "hd64570.h" | |
35 | ||
36 | ||
37 | static const char* version = "SDL RISCom/N2 driver version: 1.15"; | |
38 | static const char* devname = "RISCom/N2"; | |
39 | ||
40 | #undef DEBUG_PKT | |
41 | #define DEBUG_RINGS | |
42 | ||
43 | #define USE_WINDOWSIZE 16384 | |
44 | #define USE_BUS16BITS 1 | |
45 | #define CLOCK_BASE 9830400 /* 9.8304 MHz */ | |
46 | #define MAX_PAGES 16 /* 16 RAM pages at max */ | |
47 | #define MAX_RAM_SIZE 0x80000 /* 512 KB */ | |
48 | #if MAX_RAM_SIZE > MAX_PAGES * USE_WINDOWSIZE | |
49 | #undef MAX_RAM_SIZE | |
50 | #define MAX_RAM_SIZE (MAX_PAGES * USE_WINDOWSIZE) | |
51 | #endif | |
52 | #define N2_IOPORTS 0x10 | |
53 | #define NEED_DETECT_RAM | |
54 | #define NEED_SCA_MSCI_INTR | |
55 | #define MAX_TX_BUFFERS 10 | |
56 | ||
88597364 | 57 | static char *hw; /* pointer to hw=xxx command line string */ |
1da177e4 LT |
58 | |
59 | /* RISCom/N2 Board Registers */ | |
60 | ||
61 | /* PC Control Register */ | |
62 | #define N2_PCR 0 | |
63 | #define PCR_RUNSCA 1 /* Run 64570 */ | |
64 | #define PCR_VPM 2 /* Enable VPM - needed if using RAM above 1 MB */ | |
65 | #define PCR_ENWIN 4 /* Open window */ | |
66 | #define PCR_BUS16 8 /* 16-bit bus */ | |
67 | ||
68 | ||
69 | /* Memory Base Address Register */ | |
70 | #define N2_BAR 2 | |
71 | ||
72 | ||
73 | /* Page Scan Register */ | |
74 | #define N2_PSR 4 | |
75 | #define WIN16K 0x00 | |
76 | #define WIN32K 0x20 | |
77 | #define WIN64K 0x40 | |
78 | #define PSR_WINBITS 0x60 | |
79 | #define PSR_DMAEN 0x80 | |
80 | #define PSR_PAGEBITS 0x0F | |
81 | ||
82 | ||
83 | /* Modem Control Reg */ | |
84 | #define N2_MCR 6 | |
85 | #define CLOCK_OUT_PORT1 0x80 | |
86 | #define CLOCK_OUT_PORT0 0x40 | |
87 | #define TX422_PORT1 0x20 | |
88 | #define TX422_PORT0 0x10 | |
89 | #define DSR_PORT1 0x08 | |
90 | #define DSR_PORT0 0x04 | |
91 | #define DTR_PORT1 0x02 | |
92 | #define DTR_PORT0 0x01 | |
93 | ||
94 | ||
95 | typedef struct port_s { | |
96 | struct net_device *dev; | |
97 | struct card_s *card; | |
98 | spinlock_t lock; /* TX lock */ | |
99 | sync_serial_settings settings; | |
100 | int valid; /* port enabled */ | |
101 | int rxpart; /* partial frame received, next frame invalid*/ | |
102 | unsigned short encoding; | |
103 | unsigned short parity; | |
104 | u16 rxin; /* rx ring buffer 'in' pointer */ | |
105 | u16 txin; /* tx ring buffer 'in' and 'last' pointers */ | |
106 | u16 txlast; | |
107 | u8 rxs, txs, tmc; /* SCA registers */ | |
108 | u8 phy_node; /* physical port # - 0 or 1 */ | |
109 | u8 log_node; /* logical port # */ | |
110 | }port_t; | |
111 | ||
112 | ||
113 | ||
114 | typedef struct card_s { | |
115 | u8 __iomem *winbase; /* ISA window base address */ | |
116 | u32 phy_winbase; /* ISA physical base address */ | |
117 | u32 ram_size; /* number of bytes */ | |
118 | u16 io; /* IO Base address */ | |
119 | u16 buff_offset; /* offset of first buffer of first channel */ | |
120 | u16 rx_ring_buffers; /* number of buffers in a ring */ | |
121 | u16 tx_ring_buffers; | |
122 | u8 irq; /* IRQ (3-15) */ | |
123 | ||
124 | port_t ports[2]; | |
125 | struct card_s *next_card; | |
126 | }card_t; | |
127 | ||
128 | ||
129 | static card_t *first_card; | |
130 | static card_t **new_card = &first_card; | |
131 | ||
132 | ||
133 | #define sca_reg(reg, card) (0x8000 | (card)->io | \ | |
134 | ((reg) & 0x0F) | (((reg) & 0xF0) << 6)) | |
135 | #define sca_in(reg, card) inb(sca_reg(reg, card)) | |
136 | #define sca_out(value, reg, card) outb(value, sca_reg(reg, card)) | |
137 | #define sca_inw(reg, card) inw(sca_reg(reg, card)) | |
138 | #define sca_outw(value, reg, card) outw(value, sca_reg(reg, card)) | |
139 | ||
140 | #define port_to_card(port) ((port)->card) | |
141 | #define log_node(port) ((port)->log_node) | |
142 | #define phy_node(port) ((port)->phy_node) | |
143 | #define winsize(card) (USE_WINDOWSIZE) | |
144 | #define winbase(card) ((card)->winbase) | |
145 | #define get_port(card, port) ((card)->ports[port].valid ? \ | |
146 | &(card)->ports[port] : NULL) | |
147 | ||
148 | ||
1da177e4 LT |
149 | static __inline__ u8 sca_get_page(card_t *card) |
150 | { | |
151 | return inb(card->io + N2_PSR) & PSR_PAGEBITS; | |
152 | } | |
153 | ||
154 | ||
155 | static __inline__ void openwin(card_t *card, u8 page) | |
156 | { | |
157 | u8 psr = inb(card->io + N2_PSR); | |
158 | outb((psr & ~PSR_PAGEBITS) | page, card->io + N2_PSR); | |
159 | } | |
160 | ||
161 | ||
6b40aba3 | 162 | #include "hd64570.c" |
1da177e4 LT |
163 | |
164 | ||
1da177e4 LT |
165 | static void n2_set_iface(port_t *port) |
166 | { | |
167 | card_t *card = port->card; | |
168 | int io = card->io; | |
169 | u8 mcr = inb(io + N2_MCR); | |
170 | u8 msci = get_msci(port); | |
171 | u8 rxs = port->rxs & CLK_BRG_MASK; | |
172 | u8 txs = port->txs & CLK_BRG_MASK; | |
173 | ||
174 | switch(port->settings.clock_type) { | |
175 | case CLOCK_INT: | |
176 | mcr |= port->phy_node ? CLOCK_OUT_PORT1 : CLOCK_OUT_PORT0; | |
177 | rxs |= CLK_BRG_RX; /* BRG output */ | |
178 | txs |= CLK_RXCLK_TX; /* RX clock */ | |
179 | break; | |
180 | ||
181 | case CLOCK_TXINT: | |
182 | mcr |= port->phy_node ? CLOCK_OUT_PORT1 : CLOCK_OUT_PORT0; | |
183 | rxs |= CLK_LINE_RX; /* RXC input */ | |
184 | txs |= CLK_BRG_TX; /* BRG output */ | |
185 | break; | |
186 | ||
187 | case CLOCK_TXFROMRX: | |
188 | mcr |= port->phy_node ? CLOCK_OUT_PORT1 : CLOCK_OUT_PORT0; | |
189 | rxs |= CLK_LINE_RX; /* RXC input */ | |
190 | txs |= CLK_RXCLK_TX; /* RX clock */ | |
191 | break; | |
192 | ||
193 | default: /* Clock EXTernal */ | |
194 | mcr &= port->phy_node ? ~CLOCK_OUT_PORT1 : ~CLOCK_OUT_PORT0; | |
195 | rxs |= CLK_LINE_RX; /* RXC input */ | |
196 | txs |= CLK_LINE_TX; /* TXC input */ | |
197 | } | |
198 | ||
199 | outb(mcr, io + N2_MCR); | |
200 | port->rxs = rxs; | |
201 | port->txs = txs; | |
202 | sca_out(rxs, msci + RXS, card); | |
203 | sca_out(txs, msci + TXS, card); | |
204 | sca_set_port(port); | |
205 | } | |
206 | ||
207 | ||
208 | ||
209 | static int n2_open(struct net_device *dev) | |
210 | { | |
211 | port_t *port = dev_to_port(dev); | |
212 | int io = port->card->io; | |
213 | u8 mcr = inb(io + N2_MCR) | (port->phy_node ? TX422_PORT1:TX422_PORT0); | |
214 | int result; | |
215 | ||
216 | result = hdlc_open(dev); | |
217 | if (result) | |
218 | return result; | |
219 | ||
220 | mcr &= port->phy_node ? ~DTR_PORT1 : ~DTR_PORT0; /* set DTR ON */ | |
221 | outb(mcr, io + N2_MCR); | |
222 | ||
223 | outb(inb(io + N2_PCR) | PCR_ENWIN, io + N2_PCR); /* open window */ | |
224 | outb(inb(io + N2_PSR) | PSR_DMAEN, io + N2_PSR); /* enable dma */ | |
225 | sca_open(dev); | |
226 | n2_set_iface(port); | |
227 | return 0; | |
228 | } | |
229 | ||
230 | ||
231 | ||
232 | static int n2_close(struct net_device *dev) | |
233 | { | |
234 | port_t *port = dev_to_port(dev); | |
235 | int io = port->card->io; | |
236 | u8 mcr = inb(io+N2_MCR) | (port->phy_node ? TX422_PORT1 : TX422_PORT0); | |
237 | ||
238 | sca_close(dev); | |
239 | mcr |= port->phy_node ? DTR_PORT1 : DTR_PORT0; /* set DTR OFF */ | |
240 | outb(mcr, io + N2_MCR); | |
241 | hdlc_close(dev); | |
242 | return 0; | |
243 | } | |
244 | ||
245 | ||
246 | ||
247 | static int n2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
248 | { | |
249 | const size_t size = sizeof(sync_serial_settings); | |
250 | sync_serial_settings new_line; | |
251 | sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync; | |
252 | port_t *port = dev_to_port(dev); | |
253 | ||
254 | #ifdef DEBUG_RINGS | |
255 | if (cmd == SIOCDEVPRIVATE) { | |
256 | sca_dump_rings(dev); | |
257 | return 0; | |
258 | } | |
259 | #endif | |
260 | if (cmd != SIOCWANDEV) | |
261 | return hdlc_ioctl(dev, ifr, cmd); | |
262 | ||
263 | switch(ifr->ifr_settings.type) { | |
264 | case IF_GET_IFACE: | |
265 | ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL; | |
266 | if (ifr->ifr_settings.size < size) { | |
267 | ifr->ifr_settings.size = size; /* data size wanted */ | |
268 | return -ENOBUFS; | |
269 | } | |
270 | if (copy_to_user(line, &port->settings, size)) | |
271 | return -EFAULT; | |
272 | return 0; | |
273 | ||
274 | case IF_IFACE_SYNC_SERIAL: | |
275 | if(!capable(CAP_NET_ADMIN)) | |
276 | return -EPERM; | |
277 | ||
278 | if (copy_from_user(&new_line, line, size)) | |
279 | return -EFAULT; | |
280 | ||
281 | if (new_line.clock_type != CLOCK_EXT && | |
282 | new_line.clock_type != CLOCK_TXFROMRX && | |
283 | new_line.clock_type != CLOCK_INT && | |
284 | new_line.clock_type != CLOCK_TXINT) | |
354c8e31 | 285 | return -EINVAL; /* No such clock setting */ |
1da177e4 LT |
286 | |
287 | if (new_line.loopback != 0 && new_line.loopback != 1) | |
288 | return -EINVAL; | |
289 | ||
290 | memcpy(&port->settings, &new_line, size); /* Update settings */ | |
291 | n2_set_iface(port); | |
292 | return 0; | |
293 | ||
294 | default: | |
295 | return hdlc_ioctl(dev, ifr, cmd); | |
296 | } | |
297 | } | |
298 | ||
299 | ||
300 | ||
301 | static void n2_destroy_card(card_t *card) | |
302 | { | |
303 | int cnt; | |
304 | ||
305 | for (cnt = 0; cnt < 2; cnt++) | |
306 | if (card->ports[cnt].card) { | |
307 | struct net_device *dev = port_to_dev(&card->ports[cnt]); | |
308 | unregister_hdlc_device(dev); | |
309 | } | |
310 | ||
311 | if (card->irq) | |
312 | free_irq(card->irq, card); | |
313 | ||
314 | if (card->winbase) { | |
315 | iounmap(card->winbase); | |
316 | release_mem_region(card->phy_winbase, USE_WINDOWSIZE); | |
317 | } | |
318 | ||
319 | if (card->io) | |
320 | release_region(card->io, N2_IOPORTS); | |
321 | if (card->ports[0].dev) | |
322 | free_netdev(card->ports[0].dev); | |
323 | if (card->ports[1].dev) | |
324 | free_netdev(card->ports[1].dev); | |
325 | kfree(card); | |
326 | } | |
327 | ||
991990a1 KH |
328 | static const struct net_device_ops n2_ops = { |
329 | .ndo_open = n2_open, | |
330 | .ndo_stop = n2_close, | |
331 | .ndo_change_mtu = hdlc_change_mtu, | |
332 | .ndo_start_xmit = hdlc_start_xmit, | |
333 | .ndo_do_ioctl = n2_ioctl, | |
334 | }; | |
1da177e4 LT |
335 | |
336 | static int __init n2_run(unsigned long io, unsigned long irq, | |
337 | unsigned long winbase, long valid0, long valid1) | |
338 | { | |
339 | card_t *card; | |
340 | u8 cnt, pcr; | |
341 | int i; | |
342 | ||
343 | if (io < 0x200 || io > 0x3FF || (io % N2_IOPORTS) != 0) { | |
344 | printk(KERN_ERR "n2: invalid I/O port value\n"); | |
345 | return -ENODEV; | |
346 | } | |
347 | ||
348 | if (irq < 3 || irq > 15 || irq == 6) /* FIXME */ { | |
349 | printk(KERN_ERR "n2: invalid IRQ value\n"); | |
350 | return -ENODEV; | |
351 | } | |
352 | ||
353 | if (winbase < 0xA0000 || winbase > 0xFFFFF || (winbase & 0xFFF) != 0) { | |
354 | printk(KERN_ERR "n2: invalid RAM value\n"); | |
355 | return -ENODEV; | |
356 | } | |
357 | ||
dd00cc48 | 358 | card = kzalloc(sizeof(card_t), GFP_KERNEL); |
1da177e4 LT |
359 | if (card == NULL) { |
360 | printk(KERN_ERR "n2: unable to allocate memory\n"); | |
361 | return -ENOBUFS; | |
362 | } | |
1da177e4 LT |
363 | |
364 | card->ports[0].dev = alloc_hdlcdev(&card->ports[0]); | |
365 | card->ports[1].dev = alloc_hdlcdev(&card->ports[1]); | |
366 | if (!card->ports[0].dev || !card->ports[1].dev) { | |
367 | printk(KERN_ERR "n2: unable to allocate memory\n"); | |
368 | n2_destroy_card(card); | |
369 | return -ENOMEM; | |
370 | } | |
371 | ||
372 | if (!request_region(io, N2_IOPORTS, devname)) { | |
373 | printk(KERN_ERR "n2: I/O port region in use\n"); | |
374 | n2_destroy_card(card); | |
375 | return -EBUSY; | |
376 | } | |
377 | card->io = io; | |
378 | ||
a0607fd3 | 379 | if (request_irq(irq, sca_intr, 0, devname, card)) { |
1da177e4 LT |
380 | printk(KERN_ERR "n2: could not allocate IRQ\n"); |
381 | n2_destroy_card(card); | |
807540ba | 382 | return -EBUSY; |
1da177e4 LT |
383 | } |
384 | card->irq = irq; | |
385 | ||
386 | if (!request_mem_region(winbase, USE_WINDOWSIZE, devname)) { | |
387 | printk(KERN_ERR "n2: could not request RAM window\n"); | |
388 | n2_destroy_card(card); | |
807540ba | 389 | return -EBUSY; |
1da177e4 LT |
390 | } |
391 | card->phy_winbase = winbase; | |
392 | card->winbase = ioremap(winbase, USE_WINDOWSIZE); | |
4446065a KH |
393 | if (!card->winbase) { |
394 | printk(KERN_ERR "n2: ioremap() failed\n"); | |
395 | n2_destroy_card(card); | |
396 | return -EFAULT; | |
397 | } | |
1da177e4 LT |
398 | |
399 | outb(0, io + N2_PCR); | |
400 | outb(winbase >> 12, io + N2_BAR); | |
401 | ||
402 | switch (USE_WINDOWSIZE) { | |
403 | case 16384: | |
404 | outb(WIN16K, io + N2_PSR); | |
405 | break; | |
406 | ||
407 | case 32768: | |
408 | outb(WIN32K, io + N2_PSR); | |
409 | break; | |
410 | ||
411 | case 65536: | |
412 | outb(WIN64K, io + N2_PSR); | |
413 | break; | |
414 | ||
415 | default: | |
416 | printk(KERN_ERR "n2: invalid window size\n"); | |
417 | n2_destroy_card(card); | |
418 | return -ENODEV; | |
419 | } | |
420 | ||
421 | pcr = PCR_ENWIN | PCR_VPM | (USE_BUS16BITS ? PCR_BUS16 : 0); | |
422 | outb(pcr, io + N2_PCR); | |
423 | ||
424 | card->ram_size = sca_detect_ram(card, card->winbase, MAX_RAM_SIZE); | |
425 | ||
426 | /* number of TX + RX buffers for one port */ | |
427 | i = card->ram_size / ((valid0 + valid1) * (sizeof(pkt_desc) + | |
428 | HDLC_MAX_MRU)); | |
429 | ||
430 | card->tx_ring_buffers = min(i / 2, MAX_TX_BUFFERS); | |
431 | card->rx_ring_buffers = i - card->tx_ring_buffers; | |
432 | ||
433 | card->buff_offset = (valid0 + valid1) * sizeof(pkt_desc) * | |
434 | (card->tx_ring_buffers + card->rx_ring_buffers); | |
435 | ||
436 | printk(KERN_INFO "n2: RISCom/N2 %u KB RAM, IRQ%u, " | |
437 | "using %u TX + %u RX packets rings\n", card->ram_size / 1024, | |
438 | card->irq, card->tx_ring_buffers, card->rx_ring_buffers); | |
439 | ||
440 | if (card->tx_ring_buffers < 1) { | |
441 | printk(KERN_ERR "n2: RAM test failed\n"); | |
442 | n2_destroy_card(card); | |
443 | return -EIO; | |
444 | } | |
445 | ||
446 | pcr |= PCR_RUNSCA; /* run SCA */ | |
447 | outb(pcr, io + N2_PCR); | |
448 | outb(0, io + N2_MCR); | |
449 | ||
450 | sca_init(card, 0); | |
451 | for (cnt = 0; cnt < 2; cnt++) { | |
452 | port_t *port = &card->ports[cnt]; | |
453 | struct net_device *dev = port_to_dev(port); | |
454 | hdlc_device *hdlc = dev_to_hdlc(dev); | |
455 | ||
456 | if ((cnt == 0 && !valid0) || (cnt == 1 && !valid1)) | |
457 | continue; | |
458 | ||
459 | port->phy_node = cnt; | |
460 | port->valid = 1; | |
461 | ||
462 | if ((cnt == 1) && valid0) | |
463 | port->log_node = 1; | |
464 | ||
465 | spin_lock_init(&port->lock); | |
1da177e4 LT |
466 | dev->irq = irq; |
467 | dev->mem_start = winbase; | |
468 | dev->mem_end = winbase + USE_WINDOWSIZE - 1; | |
469 | dev->tx_queue_len = 50; | |
991990a1 | 470 | dev->netdev_ops = &n2_ops; |
1da177e4 LT |
471 | hdlc->attach = sca_attach; |
472 | hdlc->xmit = sca_xmit; | |
473 | port->settings.clock_type = CLOCK_EXT; | |
474 | port->card = card; | |
475 | ||
476 | if (register_hdlc_device(dev)) { | |
477 | printk(KERN_WARNING "n2: unable to register hdlc " | |
478 | "device\n"); | |
479 | port->card = NULL; | |
480 | n2_destroy_card(card); | |
481 | return -ENOBUFS; | |
482 | } | |
88597364 | 483 | sca_init_port(port); /* Set up SCA memory */ |
1da177e4 LT |
484 | |
485 | printk(KERN_INFO "%s: RISCom/N2 node %d\n", | |
486 | dev->name, port->phy_node); | |
487 | } | |
488 | ||
489 | *new_card = card; | |
490 | new_card = &card->next_card; | |
491 | ||
492 | return 0; | |
493 | } | |
494 | ||
495 | ||
496 | ||
497 | static int __init n2_init(void) | |
498 | { | |
499 | if (hw==NULL) { | |
500 | #ifdef MODULE | |
501 | printk(KERN_INFO "n2: no card initialized\n"); | |
502 | #endif | |
09669585 | 503 | return -EINVAL; /* no parameters specified, abort */ |
1da177e4 LT |
504 | } |
505 | ||
506 | printk(KERN_INFO "%s\n", version); | |
507 | ||
508 | do { | |
509 | unsigned long io, irq, ram; | |
510 | long valid[2] = { 0, 0 }; /* Default = both ports disabled */ | |
511 | ||
512 | io = simple_strtoul(hw, &hw, 0); | |
513 | ||
514 | if (*hw++ != ',') | |
515 | break; | |
516 | irq = simple_strtoul(hw, &hw, 0); | |
517 | ||
518 | if (*hw++ != ',') | |
519 | break; | |
520 | ram = simple_strtoul(hw, &hw, 0); | |
521 | ||
522 | if (*hw++ != ',') | |
523 | break; | |
524 | while(1) { | |
525 | if (*hw == '0' && !valid[0]) | |
526 | valid[0] = 1; /* Port 0 enabled */ | |
527 | else if (*hw == '1' && !valid[1]) | |
528 | valid[1] = 1; /* Port 1 enabled */ | |
529 | else | |
530 | break; | |
531 | hw++; | |
532 | } | |
533 | ||
534 | if (!valid[0] && !valid[1]) | |
535 | break; /* at least one port must be used */ | |
536 | ||
537 | if (*hw == ':' || *hw == '\x0') | |
538 | n2_run(io, irq, ram, valid[0], valid[1]); | |
539 | ||
540 | if (*hw == '\x0') | |
09669585 | 541 | return first_card ? 0 : -EINVAL; |
1da177e4 LT |
542 | }while(*hw++ == ':'); |
543 | ||
544 | printk(KERN_ERR "n2: invalid hardware parameters\n"); | |
09669585 | 545 | return first_card ? 0 : -EINVAL; |
1da177e4 LT |
546 | } |
547 | ||
548 | ||
549 | static void __exit n2_cleanup(void) | |
550 | { | |
551 | card_t *card = first_card; | |
552 | ||
553 | while (card) { | |
554 | card_t *ptr = card; | |
555 | card = card->next_card; | |
556 | n2_destroy_card(ptr); | |
557 | } | |
558 | } | |
559 | ||
560 | ||
561 | module_init(n2_init); | |
562 | module_exit(n2_cleanup); | |
563 | ||
564 | MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>"); | |
565 | MODULE_DESCRIPTION("RISCom/N2 serial port driver"); | |
566 | MODULE_LICENSE("GPL v2"); | |
41b1d174 KH |
567 | module_param(hw, charp, 0444); |
568 | MODULE_PARM_DESC(hw, "io,irq,ram,ports:io,irq,..."); |