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[mirror_ubuntu-eoan-kernel.git] / drivers / net / wireless / ath / ath10k / core.c
CommitLineData
5e3dd157
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1/*
2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18#include <linux/module.h>
19#include <linux/firmware.h>
5aabff05 20#include <linux/of.h>
5e3dd157
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21
22#include "core.h"
23#include "mac.h"
24#include "htc.h"
25#include "hif.h"
26#include "wmi.h"
27#include "bmi.h"
28#include "debug.h"
29#include "htt.h"
43d2a30f 30#include "testmode.h"
d7579d12 31#include "wmi-ops.h"
5e3dd157
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32
33unsigned int ath10k_debug_mask;
ccec9038 34static unsigned int ath10k_cryptmode_param;
5e3dd157 35static bool uart_print;
8868b12c 36static bool skip_otp;
b6c7bafa 37static bool rawmode;
8868b12c 38
5e3dd157 39module_param_named(debug_mask, ath10k_debug_mask, uint, 0644);
ccec9038 40module_param_named(cryptmode, ath10k_cryptmode_param, uint, 0644);
5e3dd157 41module_param(uart_print, bool, 0644);
8868b12c 42module_param(skip_otp, bool, 0644);
b6c7bafa 43module_param(rawmode, bool, 0644);
8868b12c 44
5e3dd157
KV
45MODULE_PARM_DESC(debug_mask, "Debugging mask");
46MODULE_PARM_DESC(uart_print, "Uart target debugging");
8868b12c 47MODULE_PARM_DESC(skip_otp, "Skip otp failure for calibration in testmode");
ccec9038 48MODULE_PARM_DESC(cryptmode, "Crypto mode: 0-hardware, 1-software");
b6c7bafa 49MODULE_PARM_DESC(rawmode, "Use raw 802.11 frame datapath");
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50
51static const struct ath10k_hw_params ath10k_hw_params_list[] = {
5e3dd157
KV
52 {
53 .id = QCA988X_HW_2_0_VERSION,
079a0490 54 .dev_id = QCA988X_2_0_DEVICE_ID,
5e3dd157
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55 .name = "qca988x hw2.0",
56 .patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR,
3a8200b2 57 .uart_pin = 7,
587f7031 58 .has_shifted_cc_wraparound = true,
d772703e 59 .otp_exe_param = 0,
9c8fb548 60 .channel_counters_freq_hz = 88000,
7b7da0a0 61 .max_probe_resp_desc_thres = 0,
b8d55fca 62 .hw_4addr_pad = ATH10K_HW_4ADDR_PAD_AFTER,
0b8e3c4c 63 .cal_data_len = 2116,
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64 .fw = {
65 .dir = QCA988X_HW_2_0_FW_DIR,
5e3dd157 66 .board = QCA988X_HW_2_0_BOARD_DATA_FILE,
9764a2af
MK
67 .board_size = QCA988X_BOARD_DATA_SZ,
68 .board_ext_size = QCA988X_BOARD_EXT_DATA_SZ,
5e3dd157
KV
69 },
70 },
d63955b3
MK
71 {
72 .id = QCA6174_HW_2_1_VERSION,
079a0490
BM
73 .dev_id = QCA6164_2_1_DEVICE_ID,
74 .name = "qca6164 hw2.1",
75 .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR,
76 .uart_pin = 6,
77 .otp_exe_param = 0,
78 .channel_counters_freq_hz = 88000,
79 .max_probe_resp_desc_thres = 0,
0b8e3c4c 80 .cal_data_len = 8124,
079a0490
BM
81 .fw = {
82 .dir = QCA6174_HW_2_1_FW_DIR,
079a0490
BM
83 .board = QCA6174_HW_2_1_BOARD_DATA_FILE,
84 .board_size = QCA6174_BOARD_DATA_SZ,
85 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
86 },
87 },
88 {
89 .id = QCA6174_HW_2_1_VERSION,
90 .dev_id = QCA6174_2_1_DEVICE_ID,
d63955b3
MK
91 .name = "qca6174 hw2.1",
92 .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR,
93 .uart_pin = 6,
d772703e 94 .otp_exe_param = 0,
9c8fb548 95 .channel_counters_freq_hz = 88000,
7b7da0a0 96 .max_probe_resp_desc_thres = 0,
b8d55fca 97 .hw_4addr_pad = ATH10K_HW_4ADDR_PAD_AFTER,
0b8e3c4c 98 .cal_data_len = 8124,
d63955b3
MK
99 .fw = {
100 .dir = QCA6174_HW_2_1_FW_DIR,
d63955b3
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101 .board = QCA6174_HW_2_1_BOARD_DATA_FILE,
102 .board_size = QCA6174_BOARD_DATA_SZ,
103 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
104 },
105 },
106 {
107 .id = QCA6174_HW_3_0_VERSION,
079a0490 108 .dev_id = QCA6174_2_1_DEVICE_ID,
d63955b3
MK
109 .name = "qca6174 hw3.0",
110 .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR,
111 .uart_pin = 6,
d772703e 112 .otp_exe_param = 0,
9c8fb548 113 .channel_counters_freq_hz = 88000,
7b7da0a0 114 .max_probe_resp_desc_thres = 0,
b8d55fca 115 .hw_4addr_pad = ATH10K_HW_4ADDR_PAD_AFTER,
0b8e3c4c 116 .cal_data_len = 8124,
d63955b3
MK
117 .fw = {
118 .dir = QCA6174_HW_3_0_FW_DIR,
d63955b3
MK
119 .board = QCA6174_HW_3_0_BOARD_DATA_FILE,
120 .board_size = QCA6174_BOARD_DATA_SZ,
121 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
122 },
123 },
608b8f73
MK
124 {
125 .id = QCA6174_HW_3_2_VERSION,
079a0490 126 .dev_id = QCA6174_2_1_DEVICE_ID,
608b8f73
MK
127 .name = "qca6174 hw3.2",
128 .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR,
129 .uart_pin = 6,
d772703e 130 .otp_exe_param = 0,
9c8fb548 131 .channel_counters_freq_hz = 88000,
7b7da0a0 132 .max_probe_resp_desc_thres = 0,
b8d55fca 133 .hw_4addr_pad = ATH10K_HW_4ADDR_PAD_AFTER,
0b8e3c4c 134 .cal_data_len = 8124,
608b8f73
MK
135 .fw = {
136 /* uses same binaries as hw3.0 */
137 .dir = QCA6174_HW_3_0_FW_DIR,
608b8f73
MK
138 .board = QCA6174_HW_3_0_BOARD_DATA_FILE,
139 .board_size = QCA6174_BOARD_DATA_SZ,
140 .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
141 },
142 },
8bd47021
VT
143 {
144 .id = QCA99X0_HW_2_0_DEV_VERSION,
079a0490 145 .dev_id = QCA99X0_2_0_DEVICE_ID,
8bd47021
VT
146 .name = "qca99x0 hw2.0",
147 .patch_load_addr = QCA99X0_HW_2_0_PATCH_LOAD_ADDR,
148 .uart_pin = 7,
d772703e 149 .otp_exe_param = 0x00000700,
d9156b5f 150 .continuous_frag_desc = true,
9c8fb548 151 .channel_counters_freq_hz = 150000,
7b7da0a0 152 .max_probe_resp_desc_thres = 24,
b8d55fca 153 .hw_4addr_pad = ATH10K_HW_4ADDR_PAD_BEFORE,
5699a6f2
RM
154 .tx_chain_mask = 0xf,
155 .rx_chain_mask = 0xf,
156 .max_spatial_stream = 4,
0b8e3c4c 157 .cal_data_len = 12064,
8bd47021
VT
158 .fw = {
159 .dir = QCA99X0_HW_2_0_FW_DIR,
8bd47021
VT
160 .board = QCA99X0_HW_2_0_BOARD_DATA_FILE,
161 .board_size = QCA99X0_BOARD_DATA_SZ,
162 .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ,
163 },
164 },
034074f3
BM
165 {
166 .id = QCA9377_HW_1_0_DEV_VERSION,
167 .dev_id = QCA9377_1_0_DEVICE_ID,
168 .name = "qca9377 hw1.0",
169 .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR,
170 .uart_pin = 6,
171 .otp_exe_param = 0,
172 .channel_counters_freq_hz = 88000,
173 .max_probe_resp_desc_thres = 0,
0b8e3c4c 174 .cal_data_len = 8124,
034074f3
BM
175 .fw = {
176 .dir = QCA9377_HW_1_0_FW_DIR,
034074f3
BM
177 .board = QCA9377_HW_1_0_BOARD_DATA_FILE,
178 .board_size = QCA9377_BOARD_DATA_SZ,
179 .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ,
180 },
181 },
a226b519 182 {
12551ced 183 .id = QCA9377_HW_1_1_DEV_VERSION,
079a0490 184 .dev_id = QCA9377_1_0_DEVICE_ID,
12551ced 185 .name = "qca9377 hw1.1",
a226b519 186 .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR,
6cf21395 187 .uart_pin = 6,
a226b519 188 .otp_exe_param = 0,
6cf21395
BM
189 .channel_counters_freq_hz = 88000,
190 .max_probe_resp_desc_thres = 0,
0b8e3c4c 191 .cal_data_len = 8124,
a226b519
BM
192 .fw = {
193 .dir = QCA9377_HW_1_0_FW_DIR,
a226b519
BM
194 .board = QCA9377_HW_1_0_BOARD_DATA_FILE,
195 .board_size = QCA9377_BOARD_DATA_SZ,
196 .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ,
197 },
198 },
b1a958c9
RM
199 {
200 .id = QCA4019_HW_1_0_DEV_VERSION,
201 .dev_id = 0,
202 .name = "qca4019 hw1.0",
203 .patch_load_addr = QCA4019_HW_1_0_PATCH_LOAD_ADDR,
204 .uart_pin = 7,
ee9ca147 205 .has_shifted_cc_wraparound = true,
b1a958c9
RM
206 .otp_exe_param = 0x0010000,
207 .continuous_frag_desc = true,
208 .channel_counters_freq_hz = 125000,
209 .max_probe_resp_desc_thres = 24,
210 .hw_4addr_pad = ATH10K_HW_4ADDR_PAD_BEFORE,
5699a6f2
RM
211 .tx_chain_mask = 0x3,
212 .rx_chain_mask = 0x3,
213 .max_spatial_stream = 2,
0b8e3c4c 214 .cal_data_len = 12064,
b1a958c9
RM
215 .fw = {
216 .dir = QCA4019_HW_1_0_FW_DIR,
b1a958c9
RM
217 .board = QCA4019_HW_1_0_BOARD_DATA_FILE,
218 .board_size = QCA4019_BOARD_DATA_SZ,
219 .board_ext_size = QCA4019_BOARD_EXT_DATA_SZ,
220 },
221 },
5e3dd157
KV
222};
223
b27bc5a4
MK
224static const char *const ath10k_core_fw_feature_str[] = {
225 [ATH10K_FW_FEATURE_EXT_WMI_MGMT_RX] = "wmi-mgmt-rx",
226 [ATH10K_FW_FEATURE_WMI_10X] = "wmi-10.x",
227 [ATH10K_FW_FEATURE_HAS_WMI_MGMT_TX] = "has-wmi-mgmt-tx",
228 [ATH10K_FW_FEATURE_NO_P2P] = "no-p2p",
229 [ATH10K_FW_FEATURE_WMI_10_2] = "wmi-10.2",
230 [ATH10K_FW_FEATURE_MULTI_VIF_PS_SUPPORT] = "multi-vif-ps",
231 [ATH10K_FW_FEATURE_WOWLAN_SUPPORT] = "wowlan",
232 [ATH10K_FW_FEATURE_IGNORE_OTP_RESULT] = "ignore-otp",
233 [ATH10K_FW_FEATURE_NO_NWIFI_DECAP_4ADDR_PADDING] = "no-4addr-pad",
234 [ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT] = "skip-clock-init",
5af82fa6 235 [ATH10K_FW_FEATURE_RAW_MODE_SUPPORT] = "raw-mode",
62f77f09 236 [ATH10K_FW_FEATURE_SUPPORTS_ADAPTIVE_CCA] = "adaptive-cca",
90eceb3b 237 [ATH10K_FW_FEATURE_MFP_SUPPORT] = "mfp",
9b783763 238 [ATH10K_FW_FEATURE_PEER_FLOW_CONTROL] = "peer-flow-ctrl",
b27bc5a4
MK
239};
240
241static unsigned int ath10k_core_get_fw_feature_str(char *buf,
242 size_t buf_len,
243 enum ath10k_fw_features feat)
244{
5af82fa6
KV
245 /* make sure that ath10k_core_fw_feature_str[] gets updated */
246 BUILD_BUG_ON(ARRAY_SIZE(ath10k_core_fw_feature_str) !=
247 ATH10K_FW_FEATURE_COUNT);
248
b27bc5a4
MK
249 if (feat >= ARRAY_SIZE(ath10k_core_fw_feature_str) ||
250 WARN_ON(!ath10k_core_fw_feature_str[feat])) {
251 return scnprintf(buf, buf_len, "bit%d", feat);
252 }
253
254 return scnprintf(buf, buf_len, "%s", ath10k_core_fw_feature_str[feat]);
255}
256
257void ath10k_core_get_fw_features_str(struct ath10k *ar,
258 char *buf,
259 size_t buf_len)
260{
261 unsigned int len = 0;
262 int i;
263
264 for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) {
c4cdf753 265 if (test_bit(i, ar->normal_mode_fw.fw_file.fw_features)) {
b27bc5a4
MK
266 if (len > 0)
267 len += scnprintf(buf + len, buf_len - len, ",");
268
269 len += ath10k_core_get_fw_feature_str(buf + len,
270 buf_len - len,
271 i);
272 }
273 }
274}
275
5e3dd157
KV
276static void ath10k_send_suspend_complete(struct ath10k *ar)
277{
7aa7a72a 278 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot suspend complete\n");
5e3dd157 279
9042e17d 280 complete(&ar->target_suspend);
5e3dd157
KV
281}
282
5e3dd157
KV
283static int ath10k_init_configure_target(struct ath10k *ar)
284{
285 u32 param_host;
286 int ret;
287
288 /* tell target which HTC version it is used*/
289 ret = ath10k_bmi_write32(ar, hi_app_host_interest,
290 HTC_PROTOCOL_VERSION);
291 if (ret) {
7aa7a72a 292 ath10k_err(ar, "settings HTC version failed\n");
5e3dd157
KV
293 return ret;
294 }
295
296 /* set the firmware mode to STA/IBSS/AP */
297 ret = ath10k_bmi_read32(ar, hi_option_flag, &param_host);
298 if (ret) {
7aa7a72a 299 ath10k_err(ar, "setting firmware mode (1/2) failed\n");
5e3dd157
KV
300 return ret;
301 }
302
303 /* TODO following parameters need to be re-visited. */
304 /* num_device */
305 param_host |= (1 << HI_OPTION_NUM_DEV_SHIFT);
306 /* Firmware mode */
307 /* FIXME: Why FW_MODE_AP ??.*/
308 param_host |= (HI_OPTION_FW_MODE_AP << HI_OPTION_FW_MODE_SHIFT);
309 /* mac_addr_method */
310 param_host |= (1 << HI_OPTION_MAC_ADDR_METHOD_SHIFT);
311 /* firmware_bridge */
312 param_host |= (0 << HI_OPTION_FW_BRIDGE_SHIFT);
313 /* fwsubmode */
314 param_host |= (0 << HI_OPTION_FW_SUBMODE_SHIFT);
315
316 ret = ath10k_bmi_write32(ar, hi_option_flag, param_host);
317 if (ret) {
7aa7a72a 318 ath10k_err(ar, "setting firmware mode (2/2) failed\n");
5e3dd157
KV
319 return ret;
320 }
321
322 /* We do all byte-swapping on the host */
323 ret = ath10k_bmi_write32(ar, hi_be, 0);
324 if (ret) {
7aa7a72a 325 ath10k_err(ar, "setting host CPU BE mode failed\n");
5e3dd157
KV
326 return ret;
327 }
328
329 /* FW descriptor/Data swap flags */
330 ret = ath10k_bmi_write32(ar, hi_fw_swap, 0);
331
332 if (ret) {
7aa7a72a 333 ath10k_err(ar, "setting FW data/desc swap flags failed\n");
5e3dd157
KV
334 return ret;
335 }
336
36582e5d
MK
337 /* Some devices have a special sanity check that verifies the PCI
338 * Device ID is written to this host interest var. It is known to be
339 * required to boot QCA6164.
340 */
341 ret = ath10k_bmi_write32(ar, hi_hci_uart_pwr_mgmt_params_ext,
342 ar->dev_id);
343 if (ret) {
344 ath10k_err(ar, "failed to set pwr_mgmt_params: %d\n", ret);
345 return ret;
346 }
347
5e3dd157
KV
348 return 0;
349}
350
351static const struct firmware *ath10k_fetch_fw_file(struct ath10k *ar,
352 const char *dir,
353 const char *file)
354{
355 char filename[100];
356 const struct firmware *fw;
357 int ret;
358
359 if (file == NULL)
360 return ERR_PTR(-ENOENT);
361
362 if (dir == NULL)
363 dir = ".";
364
365 snprintf(filename, sizeof(filename), "%s/%s", dir, file);
366 ret = request_firmware(&fw, filename, ar->dev);
367 if (ret)
368 return ERR_PTR(ret);
369
370 return fw;
371}
372
a58227ef
KV
373static int ath10k_push_board_ext_data(struct ath10k *ar, const void *data,
374 size_t data_len)
5e3dd157 375{
9764a2af
MK
376 u32 board_data_size = ar->hw_params.fw.board_size;
377 u32 board_ext_data_size = ar->hw_params.fw.board_ext_size;
5e3dd157
KV
378 u32 board_ext_data_addr;
379 int ret;
380
381 ret = ath10k_bmi_read32(ar, hi_board_ext_data, &board_ext_data_addr);
382 if (ret) {
7aa7a72a
MK
383 ath10k_err(ar, "could not read board ext data addr (%d)\n",
384 ret);
5e3dd157
KV
385 return ret;
386 }
387
7aa7a72a 388 ath10k_dbg(ar, ATH10K_DBG_BOOT,
effea968 389 "boot push board extended data addr 0x%x\n",
5e3dd157
KV
390 board_ext_data_addr);
391
392 if (board_ext_data_addr == 0)
393 return 0;
394
a58227ef 395 if (data_len != (board_data_size + board_ext_data_size)) {
7aa7a72a 396 ath10k_err(ar, "invalid board (ext) data sizes %zu != %d+%d\n",
a58227ef 397 data_len, board_data_size, board_ext_data_size);
5e3dd157
KV
398 return -EINVAL;
399 }
400
401 ret = ath10k_bmi_write_memory(ar, board_ext_data_addr,
a58227ef 402 data + board_data_size,
5e3dd157
KV
403 board_ext_data_size);
404 if (ret) {
7aa7a72a 405 ath10k_err(ar, "could not write board ext data (%d)\n", ret);
5e3dd157
KV
406 return ret;
407 }
408
409 ret = ath10k_bmi_write32(ar, hi_board_ext_data_config,
410 (board_ext_data_size << 16) | 1);
411 if (ret) {
7aa7a72a
MK
412 ath10k_err(ar, "could not write board ext data bit (%d)\n",
413 ret);
5e3dd157
KV
414 return ret;
415 }
416
417 return 0;
418}
419
a58227ef
KV
420static int ath10k_download_board_data(struct ath10k *ar, const void *data,
421 size_t data_len)
5e3dd157 422{
9764a2af 423 u32 board_data_size = ar->hw_params.fw.board_size;
5e3dd157 424 u32 address;
5e3dd157
KV
425 int ret;
426
a58227ef 427 ret = ath10k_push_board_ext_data(ar, data, data_len);
5e3dd157 428 if (ret) {
7aa7a72a 429 ath10k_err(ar, "could not push board ext data (%d)\n", ret);
5e3dd157
KV
430 goto exit;
431 }
432
433 ret = ath10k_bmi_read32(ar, hi_board_data, &address);
434 if (ret) {
7aa7a72a 435 ath10k_err(ar, "could not read board data addr (%d)\n", ret);
5e3dd157
KV
436 goto exit;
437 }
438
a58227ef 439 ret = ath10k_bmi_write_memory(ar, address, data,
958df3a0 440 min_t(u32, board_data_size,
a58227ef 441 data_len));
5e3dd157 442 if (ret) {
7aa7a72a 443 ath10k_err(ar, "could not write board data (%d)\n", ret);
5e3dd157
KV
444 goto exit;
445 }
446
447 ret = ath10k_bmi_write32(ar, hi_board_data_initialized, 1);
448 if (ret) {
7aa7a72a 449 ath10k_err(ar, "could not write board data bit (%d)\n", ret);
5e3dd157
KV
450 goto exit;
451 }
452
453exit:
5e3dd157
KV
454 return ret;
455}
456
f454add4
RM
457static int ath10k_download_cal_file(struct ath10k *ar,
458 const struct firmware *file)
a58227ef
KV
459{
460 int ret;
461
f454add4 462 if (!file)
a58227ef
KV
463 return -ENOENT;
464
f454add4
RM
465 if (IS_ERR(file))
466 return PTR_ERR(file);
a58227ef 467
f454add4 468 ret = ath10k_download_board_data(ar, file->data, file->size);
a58227ef
KV
469 if (ret) {
470 ath10k_err(ar, "failed to download cal_file data: %d\n", ret);
471 return ret;
472 }
473
474 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cal file downloaded\n");
475
476 return 0;
477}
478
f454add4 479static int ath10k_download_cal_dt(struct ath10k *ar, const char *dt_name)
5aabff05
TK
480{
481 struct device_node *node;
482 int data_len;
483 void *data;
484 int ret;
485
486 node = ar->dev->of_node;
487 if (!node)
488 /* Device Tree is optional, don't print any warnings if
489 * there's no node for ath10k.
490 */
491 return -ENOENT;
492
f454add4 493 if (!of_get_property(node, dt_name, &data_len)) {
5aabff05
TK
494 /* The calibration data node is optional */
495 return -ENOENT;
496 }
497
0b8e3c4c 498 if (data_len != ar->hw_params.cal_data_len) {
5aabff05
TK
499 ath10k_warn(ar, "invalid calibration data length in DT: %d\n",
500 data_len);
501 ret = -EMSGSIZE;
502 goto out;
503 }
504
505 data = kmalloc(data_len, GFP_KERNEL);
506 if (!data) {
507 ret = -ENOMEM;
508 goto out;
509 }
510
f454add4 511 ret = of_property_read_u8_array(node, dt_name, data, data_len);
5aabff05
TK
512 if (ret) {
513 ath10k_warn(ar, "failed to read calibration data from DT: %d\n",
514 ret);
515 goto out_free;
516 }
517
518 ret = ath10k_download_board_data(ar, data, data_len);
519 if (ret) {
520 ath10k_warn(ar, "failed to download calibration data from Device Tree: %d\n",
521 ret);
522 goto out_free;
523 }
524
525 ret = 0;
526
527out_free:
528 kfree(data);
529
530out:
531 return ret;
532}
533
db0984e5
MP
534static int ath10k_core_get_board_id_from_otp(struct ath10k *ar)
535{
536 u32 result, address;
537 u8 board_id, chip_id;
538 int ret;
539
540 address = ar->hw_params.patch_load_addr;
541
7ebf721d
KV
542 if (!ar->normal_mode_fw.fw_file.otp_data ||
543 !ar->normal_mode_fw.fw_file.otp_len) {
db0984e5
MP
544 ath10k_warn(ar,
545 "failed to retrieve board id because of invalid otp\n");
546 return -ENODATA;
547 }
548
549 ath10k_dbg(ar, ATH10K_DBG_BOOT,
550 "boot upload otp to 0x%x len %zd for board id\n",
7ebf721d 551 address, ar->normal_mode_fw.fw_file.otp_len);
db0984e5 552
7ebf721d
KV
553 ret = ath10k_bmi_fast_download(ar, address,
554 ar->normal_mode_fw.fw_file.otp_data,
555 ar->normal_mode_fw.fw_file.otp_len);
db0984e5
MP
556 if (ret) {
557 ath10k_err(ar, "could not write otp for board id check: %d\n",
558 ret);
559 return ret;
560 }
561
562 ret = ath10k_bmi_execute(ar, address, BMI_PARAM_GET_EEPROM_BOARD_ID,
563 &result);
564 if (ret) {
565 ath10k_err(ar, "could not execute otp for board id check: %d\n",
566 ret);
567 return ret;
568 }
569
570 board_id = MS(result, ATH10K_BMI_BOARD_ID_FROM_OTP);
571 chip_id = MS(result, ATH10K_BMI_CHIP_ID_FROM_OTP);
572
573 ath10k_dbg(ar, ATH10K_DBG_BOOT,
574 "boot get otp board id result 0x%08x board_id %d chip_id %d\n",
575 result, board_id, chip_id);
576
577 if ((result & ATH10K_BMI_BOARD_ID_STATUS_MASK) != 0)
578 return -EOPNOTSUPP;
579
580 ar->id.bmi_ids_valid = true;
581 ar->id.bmi_board_id = board_id;
582 ar->id.bmi_chip_id = chip_id;
583
584 return 0;
585}
586
5e3dd157
KV
587static int ath10k_download_and_run_otp(struct ath10k *ar)
588{
d6d4a58d 589 u32 result, address = ar->hw_params.patch_load_addr;
d772703e 590 u32 bmi_otp_exe_param = ar->hw_params.otp_exe_param;
5e3dd157
KV
591 int ret;
592
7ebf721d
KV
593 ret = ath10k_download_board_data(ar,
594 ar->running_fw->board_data,
595 ar->running_fw->board_len);
83091559
KV
596 if (ret) {
597 ath10k_err(ar, "failed to download board data: %d\n", ret);
598 return ret;
599 }
600
5e3dd157
KV
601 /* OTP is optional */
602
7ebf721d
KV
603 if (!ar->running_fw->fw_file.otp_data ||
604 !ar->running_fw->fw_file.otp_len) {
7aa7a72a 605 ath10k_warn(ar, "Not running otp, calibration will be incorrect (otp-data %p otp_len %zd)!\n",
7ebf721d
KV
606 ar->running_fw->fw_file.otp_data,
607 ar->running_fw->fw_file.otp_len);
5e3dd157 608 return 0;
7f06ea1e
KV
609 }
610
7aa7a72a 611 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot upload otp to 0x%x len %zd\n",
7ebf721d 612 address, ar->running_fw->fw_file.otp_len);
5e3dd157 613
7ebf721d
KV
614 ret = ath10k_bmi_fast_download(ar, address,
615 ar->running_fw->fw_file.otp_data,
616 ar->running_fw->fw_file.otp_len);
5e3dd157 617 if (ret) {
7aa7a72a 618 ath10k_err(ar, "could not write otp (%d)\n", ret);
7f06ea1e 619 return ret;
5e3dd157
KV
620 }
621
d772703e 622 ret = ath10k_bmi_execute(ar, address, bmi_otp_exe_param, &result);
5e3dd157 623 if (ret) {
7aa7a72a 624 ath10k_err(ar, "could not execute otp (%d)\n", ret);
7f06ea1e 625 return ret;
5e3dd157
KV
626 }
627
7aa7a72a 628 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot otp execute result %d\n", result);
7f06ea1e 629
d9153546 630 if (!(skip_otp || test_bit(ATH10K_FW_FEATURE_IGNORE_OTP_RESULT,
c4cdf753 631 ar->running_fw->fw_file.fw_features)) &&
be62e92a 632 result != 0) {
7aa7a72a 633 ath10k_err(ar, "otp calibration failed: %d", result);
7f06ea1e
KV
634 return -EINVAL;
635 }
636
637 return 0;
5e3dd157
KV
638}
639
7ebf721d 640static int ath10k_download_fw(struct ath10k *ar)
5e3dd157 641{
43d2a30f 642 u32 address, data_len;
43d2a30f 643 const void *data;
5e3dd157
KV
644 int ret;
645
5e3dd157
KV
646 address = ar->hw_params.patch_load_addr;
647
7ebf721d
KV
648 data = ar->running_fw->fw_file.firmware_data;
649 data_len = ar->running_fw->fw_file.firmware_len;
650
1fe63c9c 651 ret = ath10k_swap_code_seg_configure(ar);
7ebf721d
KV
652 if (ret) {
653 ath10k_err(ar, "failed to configure fw code swap: %d\n",
654 ret);
655 return ret;
43d2a30f
KV
656 }
657
658 ath10k_dbg(ar, ATH10K_DBG_BOOT,
7ebf721d
KV
659 "boot uploading firmware image %p len %d\n",
660 data, data_len);
43d2a30f
KV
661
662 ret = ath10k_bmi_fast_download(ar, address, data, data_len);
5e3dd157 663 if (ret) {
7ebf721d
KV
664 ath10k_err(ar, "failed to download firmware: %d\n",
665 ret);
43d2a30f 666 return ret;
5e3dd157
KV
667 }
668
29385057
MK
669 return ret;
670}
671
0a51b343 672static void ath10k_core_free_board_files(struct ath10k *ar)
29385057 673{
7ebf721d
KV
674 if (!IS_ERR(ar->normal_mode_fw.board))
675 release_firmware(ar->normal_mode_fw.board);
29385057 676
7ebf721d
KV
677 ar->normal_mode_fw.board = NULL;
678 ar->normal_mode_fw.board_data = NULL;
679 ar->normal_mode_fw.board_len = 0;
0a51b343
MP
680}
681
682static void ath10k_core_free_firmware_files(struct ath10k *ar)
683{
7ebf721d
KV
684 if (!IS_ERR(ar->normal_mode_fw.fw_file.firmware))
685 release_firmware(ar->normal_mode_fw.fw_file.firmware);
29385057 686
db2cf865 687 if (!IS_ERR(ar->cal_file))
a58227ef
KV
688 release_firmware(ar->cal_file);
689
9a5f91a1
RM
690 if (!IS_ERR(ar->pre_cal_file))
691 release_firmware(ar->pre_cal_file);
692
dcb02db1
VT
693 ath10k_swap_code_seg_release(ar);
694
7ebf721d
KV
695 ar->normal_mode_fw.fw_file.otp_data = NULL;
696 ar->normal_mode_fw.fw_file.otp_len = 0;
958df3a0 697
7ebf721d
KV
698 ar->normal_mode_fw.fw_file.firmware = NULL;
699 ar->normal_mode_fw.fw_file.firmware_data = NULL;
700 ar->normal_mode_fw.fw_file.firmware_len = 0;
a58227ef
KV
701
702 ar->cal_file = NULL;
9a5f91a1 703 ar->pre_cal_file = NULL;
a58227ef
KV
704}
705
706static int ath10k_fetch_cal_file(struct ath10k *ar)
707{
708 char filename[100];
709
3d9195ea
RM
710 /* pre-cal-<bus>-<id>.bin */
711 scnprintf(filename, sizeof(filename), "pre-cal-%s-%s.bin",
712 ath10k_bus_str(ar->hif.bus), dev_name(ar->dev));
713
714 ar->pre_cal_file = ath10k_fetch_fw_file(ar, ATH10K_FW_DIR, filename);
715 if (!IS_ERR(ar->pre_cal_file))
716 goto success;
717
a58227ef
KV
718 /* cal-<bus>-<id>.bin */
719 scnprintf(filename, sizeof(filename), "cal-%s-%s.bin",
720 ath10k_bus_str(ar->hif.bus), dev_name(ar->dev));
721
722 ar->cal_file = ath10k_fetch_fw_file(ar, ATH10K_FW_DIR, filename);
723 if (IS_ERR(ar->cal_file))
724 /* calibration file is optional, don't print any warnings */
725 return PTR_ERR(ar->cal_file);
3d9195ea 726success:
a58227ef
KV
727 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found calibration file %s/%s\n",
728 ATH10K_FW_DIR, filename);
729
730 return 0;
29385057
MK
731}
732
0a51b343 733static int ath10k_core_fetch_board_data_api_1(struct ath10k *ar)
29385057 734{
0a51b343
MP
735 if (!ar->hw_params.fw.board) {
736 ath10k_err(ar, "failed to find board file fw entry\n");
737 return -EINVAL;
738 }
de57e2c8 739
7ebf721d
KV
740 ar->normal_mode_fw.board = ath10k_fetch_fw_file(ar,
741 ar->hw_params.fw.dir,
742 ar->hw_params.fw.board);
743 if (IS_ERR(ar->normal_mode_fw.board))
744 return PTR_ERR(ar->normal_mode_fw.board);
de57e2c8 745
7ebf721d
KV
746 ar->normal_mode_fw.board_data = ar->normal_mode_fw.board->data;
747 ar->normal_mode_fw.board_len = ar->normal_mode_fw.board->size;
29385057 748
de57e2c8
MK
749 return 0;
750}
751
0a51b343
MP
752static int ath10k_core_parse_bd_ie_board(struct ath10k *ar,
753 const void *buf, size_t buf_len,
754 const char *boardname)
de57e2c8 755{
0a51b343
MP
756 const struct ath10k_fw_ie *hdr;
757 bool name_match_found;
758 int ret, board_ie_id;
759 size_t board_ie_len;
760 const void *board_ie_data;
761
762 name_match_found = false;
763
764 /* go through ATH10K_BD_IE_BOARD_ elements */
765 while (buf_len > sizeof(struct ath10k_fw_ie)) {
766 hdr = buf;
767 board_ie_id = le32_to_cpu(hdr->id);
768 board_ie_len = le32_to_cpu(hdr->len);
769 board_ie_data = hdr->data;
770
771 buf_len -= sizeof(*hdr);
772 buf += sizeof(*hdr);
773
774 if (buf_len < ALIGN(board_ie_len, 4)) {
775 ath10k_err(ar, "invalid ATH10K_BD_IE_BOARD length: %zu < %zu\n",
776 buf_len, ALIGN(board_ie_len, 4));
777 ret = -EINVAL;
778 goto out;
779 }
780
781 switch (board_ie_id) {
782 case ATH10K_BD_IE_BOARD_NAME:
783 ath10k_dbg_dump(ar, ATH10K_DBG_BOOT, "board name", "",
784 board_ie_data, board_ie_len);
785
786 if (board_ie_len != strlen(boardname))
787 break;
788
789 ret = memcmp(board_ie_data, boardname, strlen(boardname));
790 if (ret)
791 break;
792
793 name_match_found = true;
794 ath10k_dbg(ar, ATH10K_DBG_BOOT,
795 "boot found match for name '%s'",
796 boardname);
797 break;
798 case ATH10K_BD_IE_BOARD_DATA:
799 if (!name_match_found)
800 /* no match found */
801 break;
802
803 ath10k_dbg(ar, ATH10K_DBG_BOOT,
804 "boot found board data for '%s'",
805 boardname);
806
7ebf721d
KV
807 ar->normal_mode_fw.board_data = board_ie_data;
808 ar->normal_mode_fw.board_len = board_ie_len;
0a51b343
MP
809
810 ret = 0;
811 goto out;
812 default:
813 ath10k_warn(ar, "unknown ATH10K_BD_IE_BOARD found: %d\n",
814 board_ie_id);
815 break;
816 }
817
818 /* jump over the padding */
819 board_ie_len = ALIGN(board_ie_len, 4);
820
821 buf_len -= board_ie_len;
822 buf += board_ie_len;
29385057
MK
823 }
824
0a51b343
MP
825 /* no match found */
826 ret = -ENOENT;
827
828out:
829 return ret;
830}
831
832static int ath10k_core_fetch_board_data_api_n(struct ath10k *ar,
833 const char *boardname,
834 const char *filename)
835{
836 size_t len, magic_len, ie_len;
837 struct ath10k_fw_ie *hdr;
838 const u8 *data;
839 int ret, ie_id;
840
7ebf721d
KV
841 ar->normal_mode_fw.board = ath10k_fetch_fw_file(ar,
842 ar->hw_params.fw.dir,
843 filename);
844 if (IS_ERR(ar->normal_mode_fw.board))
845 return PTR_ERR(ar->normal_mode_fw.board);
29385057 846
7ebf721d
KV
847 data = ar->normal_mode_fw.board->data;
848 len = ar->normal_mode_fw.board->size;
0a51b343
MP
849
850 /* magic has extra null byte padded */
851 magic_len = strlen(ATH10K_BOARD_MAGIC) + 1;
852 if (len < magic_len) {
853 ath10k_err(ar, "failed to find magic value in %s/%s, file too short: %zu\n",
854 ar->hw_params.fw.dir, filename, len);
855 ret = -EINVAL;
856 goto err;
857 }
858
859 if (memcmp(data, ATH10K_BOARD_MAGIC, magic_len)) {
860 ath10k_err(ar, "found invalid board magic\n");
861 ret = -EINVAL;
862 goto err;
863 }
864
865 /* magic is padded to 4 bytes */
866 magic_len = ALIGN(magic_len, 4);
867 if (len < magic_len) {
868 ath10k_err(ar, "failed: %s/%s too small to contain board data, len: %zu\n",
869 ar->hw_params.fw.dir, filename, len);
870 ret = -EINVAL;
871 goto err;
872 }
873
874 data += magic_len;
875 len -= magic_len;
876
877 while (len > sizeof(struct ath10k_fw_ie)) {
878 hdr = (struct ath10k_fw_ie *)data;
879 ie_id = le32_to_cpu(hdr->id);
880 ie_len = le32_to_cpu(hdr->len);
881
882 len -= sizeof(*hdr);
883 data = hdr->data;
884
885 if (len < ALIGN(ie_len, 4)) {
886 ath10k_err(ar, "invalid length for board ie_id %d ie_len %zu len %zu\n",
887 ie_id, ie_len, len);
888 ret = -EINVAL;
889 goto err;
890 }
891
892 switch (ie_id) {
893 case ATH10K_BD_IE_BOARD:
894 ret = ath10k_core_parse_bd_ie_board(ar, data, ie_len,
895 boardname);
896 if (ret == -ENOENT)
897 /* no match found, continue */
898 break;
899 else if (ret)
900 /* there was an error, bail out */
901 goto err;
902
903 /* board data found */
904 goto out;
905 }
906
907 /* jump over the padding */
908 ie_len = ALIGN(ie_len, 4);
909
910 len -= ie_len;
911 data += ie_len;
912 }
913
914out:
7ebf721d 915 if (!ar->normal_mode_fw.board_data || !ar->normal_mode_fw.board_len) {
0a51b343
MP
916 ath10k_err(ar,
917 "failed to fetch board data for %s from %s/%s\n",
bd5632b0 918 boardname, ar->hw_params.fw.dir, filename);
0a51b343
MP
919 ret = -ENODATA;
920 goto err;
921 }
922
923 return 0;
924
925err:
926 ath10k_core_free_board_files(ar);
927 return ret;
928}
929
930static int ath10k_core_create_board_name(struct ath10k *ar, char *name,
931 size_t name_len)
932{
db0984e5
MP
933 if (ar->id.bmi_ids_valid) {
934 scnprintf(name, name_len,
935 "bus=%s,bmi-chip-id=%d,bmi-board-id=%d",
936 ath10k_bus_str(ar->hif.bus),
937 ar->id.bmi_chip_id,
938 ar->id.bmi_board_id);
939 goto out;
940 }
941
0a51b343
MP
942 scnprintf(name, name_len,
943 "bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x",
944 ath10k_bus_str(ar->hif.bus),
945 ar->id.vendor, ar->id.device,
946 ar->id.subsystem_vendor, ar->id.subsystem_device);
947
db0984e5 948out:
0a51b343 949 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using board name '%s'\n", name);
de57e2c8
MK
950
951 return 0;
952}
953
954static int ath10k_core_fetch_board_file(struct ath10k *ar)
955{
0a51b343 956 char boardname[100];
de57e2c8
MK
957 int ret;
958
0a51b343
MP
959 ret = ath10k_core_create_board_name(ar, boardname, sizeof(boardname));
960 if (ret) {
961 ath10k_err(ar, "failed to create board name: %d", ret);
962 return ret;
de57e2c8
MK
963 }
964
0a51b343
MP
965 ar->bd_api = 2;
966 ret = ath10k_core_fetch_board_data_api_n(ar, boardname,
967 ATH10K_BOARD_API2_FILE);
968 if (!ret)
969 goto success;
970
971 ar->bd_api = 1;
972 ret = ath10k_core_fetch_board_data_api_1(ar);
de57e2c8 973 if (ret) {
0a51b343 974 ath10k_err(ar, "failed to fetch board data\n");
de57e2c8
MK
975 return ret;
976 }
958df3a0 977
0a51b343
MP
978success:
979 ath10k_dbg(ar, ATH10K_DBG_BOOT, "using board api %d\n", ar->bd_api);
d0ed74f3
MK
980 return 0;
981}
982
9dfe240b
KV
983int ath10k_core_fetch_firmware_api_n(struct ath10k *ar, const char *name,
984 struct ath10k_fw_file *fw_file)
1a222435
KV
985{
986 size_t magic_len, len, ie_len;
987 int ie_id, i, index, bit, ret;
988 struct ath10k_fw_ie *hdr;
989 const u8 *data;
202e86e6 990 __le32 *timestamp, *version;
1a222435
KV
991
992 /* first fetch the firmware file (firmware-*.bin) */
7ebf721d
KV
993 fw_file->firmware = ath10k_fetch_fw_file(ar, ar->hw_params.fw.dir,
994 name);
995 if (IS_ERR(fw_file->firmware)) {
7aa7a72a 996 ath10k_err(ar, "could not fetch firmware file '%s/%s': %ld\n",
7ebf721d
KV
997 ar->hw_params.fw.dir, name,
998 PTR_ERR(fw_file->firmware));
999 return PTR_ERR(fw_file->firmware);
1a222435
KV
1000 }
1001
7ebf721d
KV
1002 data = fw_file->firmware->data;
1003 len = fw_file->firmware->size;
1a222435
KV
1004
1005 /* magic also includes the null byte, check that as well */
1006 magic_len = strlen(ATH10K_FIRMWARE_MAGIC) + 1;
1007
1008 if (len < magic_len) {
7aa7a72a 1009 ath10k_err(ar, "firmware file '%s/%s' too small to contain magic: %zu\n",
53c02284 1010 ar->hw_params.fw.dir, name, len);
9bab1cc0
MK
1011 ret = -EINVAL;
1012 goto err;
1a222435
KV
1013 }
1014
1015 if (memcmp(data, ATH10K_FIRMWARE_MAGIC, magic_len) != 0) {
7aa7a72a 1016 ath10k_err(ar, "invalid firmware magic\n");
9bab1cc0
MK
1017 ret = -EINVAL;
1018 goto err;
1a222435
KV
1019 }
1020
1021 /* jump over the padding */
1022 magic_len = ALIGN(magic_len, 4);
1023
1024 len -= magic_len;
1025 data += magic_len;
1026
1027 /* loop elements */
1028 while (len > sizeof(struct ath10k_fw_ie)) {
1029 hdr = (struct ath10k_fw_ie *)data;
1030
1031 ie_id = le32_to_cpu(hdr->id);
1032 ie_len = le32_to_cpu(hdr->len);
1033
1034 len -= sizeof(*hdr);
1035 data += sizeof(*hdr);
1036
1037 if (len < ie_len) {
7aa7a72a 1038 ath10k_err(ar, "invalid length for FW IE %d (%zu < %zu)\n",
1a222435 1039 ie_id, len, ie_len);
9bab1cc0
MK
1040 ret = -EINVAL;
1041 goto err;
1a222435
KV
1042 }
1043
1044 switch (ie_id) {
1045 case ATH10K_FW_IE_FW_VERSION:
45317355 1046 if (ie_len > sizeof(fw_file->fw_version) - 1)
1a222435
KV
1047 break;
1048
45317355
KV
1049 memcpy(fw_file->fw_version, data, ie_len);
1050 fw_file->fw_version[ie_len] = '\0';
1a222435 1051
7aa7a72a 1052 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1a222435 1053 "found fw version %s\n",
45317355 1054 fw_file->fw_version);
1a222435
KV
1055 break;
1056 case ATH10K_FW_IE_TIMESTAMP:
1057 if (ie_len != sizeof(u32))
1058 break;
1059
1060 timestamp = (__le32 *)data;
1061
7aa7a72a 1062 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw timestamp %d\n",
1a222435
KV
1063 le32_to_cpup(timestamp));
1064 break;
1065 case ATH10K_FW_IE_FEATURES:
7aa7a72a 1066 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1a222435
KV
1067 "found firmware features ie (%zd B)\n",
1068 ie_len);
1069
1070 for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) {
1071 index = i / 8;
1072 bit = i % 8;
1073
1074 if (index == ie_len)
1075 break;
1076
f591a1a5 1077 if (data[index] & (1 << bit)) {
7aa7a72a 1078 ath10k_dbg(ar, ATH10K_DBG_BOOT,
f591a1a5
BG
1079 "Enabling feature bit: %i\n",
1080 i);
c4cdf753 1081 __set_bit(i, fw_file->fw_features);
f591a1a5 1082 }
1a222435
KV
1083 }
1084
7aa7a72a 1085 ath10k_dbg_dump(ar, ATH10K_DBG_BOOT, "features", "",
8d0a0710 1086 fw_file->fw_features,
c4cdf753 1087 sizeof(fw_file->fw_features));
1a222435
KV
1088 break;
1089 case ATH10K_FW_IE_FW_IMAGE:
7aa7a72a 1090 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1a222435
KV
1091 "found fw image ie (%zd B)\n",
1092 ie_len);
1093
7ebf721d
KV
1094 fw_file->firmware_data = data;
1095 fw_file->firmware_len = ie_len;
1a222435
KV
1096
1097 break;
1098 case ATH10K_FW_IE_OTP_IMAGE:
7aa7a72a 1099 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1a222435
KV
1100 "found otp image ie (%zd B)\n",
1101 ie_len);
1102
7ebf721d
KV
1103 fw_file->otp_data = data;
1104 fw_file->otp_len = ie_len;
1a222435
KV
1105
1106 break;
202e86e6
KV
1107 case ATH10K_FW_IE_WMI_OP_VERSION:
1108 if (ie_len != sizeof(u32))
1109 break;
1110
1111 version = (__le32 *)data;
1112
bf3c13ab 1113 fw_file->wmi_op_version = le32_to_cpup(version);
202e86e6
KV
1114
1115 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie wmi op version %d\n",
bf3c13ab 1116 fw_file->wmi_op_version);
202e86e6 1117 break;
8348db29
RM
1118 case ATH10K_FW_IE_HTT_OP_VERSION:
1119 if (ie_len != sizeof(u32))
1120 break;
1121
1122 version = (__le32 *)data;
1123
77561f93 1124 fw_file->htt_op_version = le32_to_cpup(version);
8348db29
RM
1125
1126 ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie htt op version %d\n",
77561f93 1127 fw_file->htt_op_version);
8348db29 1128 break;
dcb02db1
VT
1129 case ATH10K_FW_IE_FW_CODE_SWAP_IMAGE:
1130 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1131 "found fw code swap image ie (%zd B)\n",
1132 ie_len);
7ebf721d
KV
1133 fw_file->codeswap_data = data;
1134 fw_file->codeswap_len = ie_len;
dcb02db1 1135 break;
1a222435 1136 default:
7aa7a72a 1137 ath10k_warn(ar, "Unknown FW IE: %u\n",
1a222435
KV
1138 le32_to_cpu(hdr->id));
1139 break;
1140 }
1141
1142 /* jump over the padding */
1143 ie_len = ALIGN(ie_len, 4);
1144
1145 len -= ie_len;
1146 data += ie_len;
e05634ee 1147 }
1a222435 1148
7ebf721d
KV
1149 if (!fw_file->firmware_data ||
1150 !fw_file->firmware_len) {
7aa7a72a 1151 ath10k_warn(ar, "No ATH10K_FW_IE_FW_IMAGE found from '%s/%s', skipping\n",
53c02284 1152 ar->hw_params.fw.dir, name);
1a222435
KV
1153 ret = -ENOMEDIUM;
1154 goto err;
1155 }
1156
1a222435
KV
1157 return 0;
1158
1159err:
1160 ath10k_core_free_firmware_files(ar);
1161 return ret;
1162}
1163
1164static int ath10k_core_fetch_firmware_files(struct ath10k *ar)
1165{
1166 int ret;
1167
a58227ef
KV
1168 /* calibration file is optional, don't check for any errors */
1169 ath10k_fetch_cal_file(ar);
1170
53513c30
KV
1171 ar->fw_api = 5;
1172 ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api);
1173
7ebf721d
KV
1174 ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API5_FILE,
1175 &ar->normal_mode_fw.fw_file);
53513c30
KV
1176 if (ret == 0)
1177 goto success;
1178
4a16fbec
RM
1179 ar->fw_api = 4;
1180 ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api);
1181
7ebf721d
KV
1182 ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API4_FILE,
1183 &ar->normal_mode_fw.fw_file);
4a16fbec
RM
1184 if (ret == 0)
1185 goto success;
1186
24c88f78 1187 ar->fw_api = 3;
7aa7a72a 1188 ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api);
24c88f78 1189
7ebf721d
KV
1190 ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API3_FILE,
1191 &ar->normal_mode_fw.fw_file);
24c88f78
MK
1192 if (ret == 0)
1193 goto success;
1194
53c02284 1195 ar->fw_api = 2;
7aa7a72a 1196 ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api);
53c02284 1197
7ebf721d
KV
1198 ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API2_FILE,
1199 &ar->normal_mode_fw.fw_file);
1a222435
KV
1200 if (ret)
1201 return ret;
1202
53c02284 1203success:
7aa7a72a 1204 ath10k_dbg(ar, ATH10K_DBG_BOOT, "using fw api %d\n", ar->fw_api);
1a222435
KV
1205
1206 return 0;
1207}
1208
3d9195ea
RM
1209static int ath10k_core_pre_cal_download(struct ath10k *ar)
1210{
1211 int ret;
1212
1213 ret = ath10k_download_cal_file(ar, ar->pre_cal_file);
1214 if (ret == 0) {
1215 ar->cal_mode = ATH10K_PRE_CAL_MODE_FILE;
1216 goto success;
1217 }
1218
1219 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1220 "boot did not find a pre calibration file, try DT next: %d\n",
1221 ret);
1222
1223 ret = ath10k_download_cal_dt(ar, "qcom,ath10k-pre-calibration-data");
1224 if (ret) {
1225 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1226 "unable to load pre cal data from DT: %d\n", ret);
1227 return ret;
1228 }
1229 ar->cal_mode = ATH10K_PRE_CAL_MODE_DT;
1230
1231success:
1232 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using calibration mode %s\n",
1233 ath10k_cal_mode_str(ar->cal_mode));
1234
1235 return 0;
1236}
1237
1238static int ath10k_core_pre_cal_config(struct ath10k *ar)
1239{
1240 int ret;
1241
1242 ret = ath10k_core_pre_cal_download(ar);
1243 if (ret) {
1244 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1245 "failed to load pre cal data: %d\n", ret);
1246 return ret;
1247 }
1248
1249 ret = ath10k_core_get_board_id_from_otp(ar);
1250 if (ret) {
1251 ath10k_err(ar, "failed to get board id: %d\n", ret);
1252 return ret;
1253 }
1254
1255 ret = ath10k_download_and_run_otp(ar);
1256 if (ret) {
1257 ath10k_err(ar, "failed to run otp: %d\n", ret);
1258 return ret;
1259 }
1260
1261 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1262 "pre cal configuration done successfully\n");
1263
1264 return 0;
1265}
1266
83091559 1267static int ath10k_download_cal_data(struct ath10k *ar)
5e3dd157
KV
1268{
1269 int ret;
1270
3d9195ea
RM
1271 ret = ath10k_core_pre_cal_config(ar);
1272 if (ret == 0)
1273 return 0;
1274
1275 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1276 "pre cal download procedure failed, try cal file: %d\n",
1277 ret);
1278
f454add4 1279 ret = ath10k_download_cal_file(ar, ar->cal_file);
a58227ef
KV
1280 if (ret == 0) {
1281 ar->cal_mode = ATH10K_CAL_MODE_FILE;
1282 goto done;
1283 }
1284
1285 ath10k_dbg(ar, ATH10K_DBG_BOOT,
5aabff05
TK
1286 "boot did not find a calibration file, try DT next: %d\n",
1287 ret);
1288
f454add4 1289 ret = ath10k_download_cal_dt(ar, "qcom,ath10k-calibration-data");
5aabff05
TK
1290 if (ret == 0) {
1291 ar->cal_mode = ATH10K_CAL_MODE_DT;
1292 goto done;
1293 }
1294
1295 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1296 "boot did not find DT entry, try OTP next: %d\n",
a58227ef
KV
1297 ret);
1298
5e3dd157 1299 ret = ath10k_download_and_run_otp(ar);
36a8f413 1300 if (ret) {
7aa7a72a 1301 ath10k_err(ar, "failed to run otp: %d\n", ret);
5e3dd157 1302 return ret;
36a8f413 1303 }
5e3dd157 1304
a58227ef
KV
1305 ar->cal_mode = ATH10K_CAL_MODE_OTP;
1306
1307done:
1308 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using calibration mode %s\n",
1309 ath10k_cal_mode_str(ar->cal_mode));
1310 return 0;
5e3dd157
KV
1311}
1312
1313static int ath10k_init_uart(struct ath10k *ar)
1314{
1315 int ret;
1316
1317 /*
1318 * Explicitly setting UART prints to zero as target turns it on
1319 * based on scratch registers.
1320 */
1321 ret = ath10k_bmi_write32(ar, hi_serial_enable, 0);
1322 if (ret) {
7aa7a72a 1323 ath10k_warn(ar, "could not disable UART prints (%d)\n", ret);
5e3dd157
KV
1324 return ret;
1325 }
1326
c8c39afe 1327 if (!uart_print)
5e3dd157 1328 return 0;
5e3dd157 1329
3a8200b2 1330 ret = ath10k_bmi_write32(ar, hi_dbg_uart_txpin, ar->hw_params.uart_pin);
5e3dd157 1331 if (ret) {
7aa7a72a 1332 ath10k_warn(ar, "could not enable UART prints (%d)\n", ret);
5e3dd157
KV
1333 return ret;
1334 }
1335
1336 ret = ath10k_bmi_write32(ar, hi_serial_enable, 1);
1337 if (ret) {
7aa7a72a 1338 ath10k_warn(ar, "could not enable UART prints (%d)\n", ret);
5e3dd157
KV
1339 return ret;
1340 }
1341
03fc137b
BM
1342 /* Set the UART baud rate to 19200. */
1343 ret = ath10k_bmi_write32(ar, hi_desired_baud_rate, 19200);
1344 if (ret) {
7aa7a72a 1345 ath10k_warn(ar, "could not set the baud rate (%d)\n", ret);
03fc137b
BM
1346 return ret;
1347 }
1348
7aa7a72a 1349 ath10k_info(ar, "UART prints enabled\n");
5e3dd157
KV
1350 return 0;
1351}
1352
1353static int ath10k_init_hw_params(struct ath10k *ar)
1354{
1355 const struct ath10k_hw_params *uninitialized_var(hw_params);
1356 int i;
1357
1358 for (i = 0; i < ARRAY_SIZE(ath10k_hw_params_list); i++) {
1359 hw_params = &ath10k_hw_params_list[i];
1360
079a0490
BM
1361 if (hw_params->id == ar->target_version &&
1362 hw_params->dev_id == ar->dev_id)
5e3dd157
KV
1363 break;
1364 }
1365
1366 if (i == ARRAY_SIZE(ath10k_hw_params_list)) {
7aa7a72a 1367 ath10k_err(ar, "Unsupported hardware version: 0x%x\n",
5e3dd157
KV
1368 ar->target_version);
1369 return -EINVAL;
1370 }
1371
1372 ar->hw_params = *hw_params;
1373
7aa7a72a 1374 ath10k_dbg(ar, ATH10K_DBG_BOOT, "Hardware name %s version 0x%x\n",
c8c39afe 1375 ar->hw_params.name, ar->target_version);
5e3dd157
KV
1376
1377 return 0;
1378}
1379
affd3217
MK
1380static void ath10k_core_restart(struct work_struct *work)
1381{
1382 struct ath10k *ar = container_of(work, struct ath10k, restart_work);
1383
7962b0d8
MK
1384 set_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags);
1385
1386 /* Place a barrier to make sure the compiler doesn't reorder
1387 * CRASH_FLUSH and calling other functions.
1388 */
1389 barrier();
1390
1391 ieee80211_stop_queues(ar->hw);
1392 ath10k_drain_tx(ar);
1393 complete_all(&ar->scan.started);
1394 complete_all(&ar->scan.completed);
1395 complete_all(&ar->scan.on_channel);
1396 complete_all(&ar->offchan_tx_completed);
1397 complete_all(&ar->install_key_done);
1398 complete_all(&ar->vdev_setup_done);
ac2953fc 1399 complete_all(&ar->thermal.wmi_sync);
fa7937e3 1400 complete_all(&ar->bss_survey_done);
7962b0d8
MK
1401 wake_up(&ar->htt.empty_tx_wq);
1402 wake_up(&ar->wmi.tx_credits_wq);
1403 wake_up(&ar->peer_mapping_wq);
1404
affd3217
MK
1405 mutex_lock(&ar->conf_mutex);
1406
1407 switch (ar->state) {
1408 case ATH10K_STATE_ON:
affd3217 1409 ar->state = ATH10K_STATE_RESTARTING;
61e9aab7 1410 ath10k_hif_stop(ar);
5c81c7fd 1411 ath10k_scan_finish(ar);
affd3217
MK
1412 ieee80211_restart_hw(ar->hw);
1413 break;
1414 case ATH10K_STATE_OFF:
5e90de86
MK
1415 /* this can happen if driver is being unloaded
1416 * or if the crash happens during FW probing */
7aa7a72a 1417 ath10k_warn(ar, "cannot restart a device that hasn't been started\n");
affd3217
MK
1418 break;
1419 case ATH10K_STATE_RESTARTING:
c5058f5b
MK
1420 /* hw restart might be requested from multiple places */
1421 break;
affd3217
MK
1422 case ATH10K_STATE_RESTARTED:
1423 ar->state = ATH10K_STATE_WEDGED;
1424 /* fall through */
1425 case ATH10K_STATE_WEDGED:
7aa7a72a 1426 ath10k_warn(ar, "device is wedged, will not restart\n");
affd3217 1427 break;
43d2a30f
KV
1428 case ATH10K_STATE_UTF:
1429 ath10k_warn(ar, "firmware restart in UTF mode not supported\n");
1430 break;
affd3217
MK
1431 }
1432
1433 mutex_unlock(&ar->conf_mutex);
1434}
1435
5f2144d9 1436static int ath10k_core_init_firmware_features(struct ath10k *ar)
cfd1061e 1437{
c4cdf753
KV
1438 struct ath10k_fw_file *fw_file = &ar->normal_mode_fw.fw_file;
1439
1440 if (test_bit(ATH10K_FW_FEATURE_WMI_10_2, fw_file->fw_features) &&
1441 !test_bit(ATH10K_FW_FEATURE_WMI_10X, fw_file->fw_features)) {
5f2144d9
KV
1442 ath10k_err(ar, "feature bits corrupted: 10.2 feature requires 10.x feature to be set as well");
1443 return -EINVAL;
1444 }
1445
bf3c13ab 1446 if (fw_file->wmi_op_version >= ATH10K_FW_WMI_OP_VERSION_MAX) {
202e86e6 1447 ath10k_err(ar, "unsupported WMI OP version (max %d): %d\n",
bf3c13ab 1448 ATH10K_FW_WMI_OP_VERSION_MAX, fw_file->wmi_op_version);
202e86e6
KV
1449 return -EINVAL;
1450 }
1451
ccec9038
DL
1452 ar->wmi.rx_decap_mode = ATH10K_HW_TXRX_NATIVE_WIFI;
1453 switch (ath10k_cryptmode_param) {
1454 case ATH10K_CRYPT_MODE_HW:
1455 clear_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags);
1456 clear_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags);
1457 break;
1458 case ATH10K_CRYPT_MODE_SW:
1459 if (!test_bit(ATH10K_FW_FEATURE_RAW_MODE_SUPPORT,
c4cdf753 1460 fw_file->fw_features)) {
ccec9038
DL
1461 ath10k_err(ar, "cryptmode > 0 requires raw mode support from firmware");
1462 return -EINVAL;
1463 }
1464
1465 set_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags);
1466 set_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags);
1467 break;
1468 default:
1469 ath10k_info(ar, "invalid cryptmode: %d\n",
1470 ath10k_cryptmode_param);
1471 return -EINVAL;
1472 }
1473
1474 ar->htt.max_num_amsdu = ATH10K_HTT_MAX_NUM_AMSDU_DEFAULT;
1475 ar->htt.max_num_ampdu = ATH10K_HTT_MAX_NUM_AMPDU_DEFAULT;
1476
b6c7bafa
BC
1477 if (rawmode) {
1478 if (!test_bit(ATH10K_FW_FEATURE_RAW_MODE_SUPPORT,
c4cdf753 1479 fw_file->fw_features)) {
b6c7bafa
BC
1480 ath10k_err(ar, "rawmode = 1 requires support from firmware");
1481 return -EINVAL;
1482 }
1483 set_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags);
1484 }
1485
ccec9038
DL
1486 if (test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) {
1487 ar->wmi.rx_decap_mode = ATH10K_HW_TXRX_RAW;
1488
1489 /* Workaround:
1490 *
1491 * Firmware A-MSDU aggregation breaks with RAW Tx encap mode
1492 * and causes enormous performance issues (malformed frames,
1493 * etc).
1494 *
1495 * Disabling A-MSDU makes RAW mode stable with heavy traffic
1496 * albeit a bit slower compared to regular operation.
1497 */
1498 ar->htt.max_num_amsdu = 1;
1499 }
1500
202e86e6
KV
1501 /* Backwards compatibility for firmwares without
1502 * ATH10K_FW_IE_WMI_OP_VERSION.
1503 */
bf3c13ab 1504 if (fw_file->wmi_op_version == ATH10K_FW_WMI_OP_VERSION_UNSET) {
c4cdf753 1505 if (test_bit(ATH10K_FW_FEATURE_WMI_10X, fw_file->fw_features)) {
4a16fbec 1506 if (test_bit(ATH10K_FW_FEATURE_WMI_10_2,
c4cdf753 1507 fw_file->fw_features))
bf3c13ab 1508 fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_10_2;
202e86e6 1509 else
bf3c13ab 1510 fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_10_1;
202e86e6 1511 } else {
bf3c13ab 1512 fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_MAIN;
202e86e6
KV
1513 }
1514 }
1515
bf3c13ab 1516 switch (fw_file->wmi_op_version) {
202e86e6 1517 case ATH10K_FW_WMI_OP_VERSION_MAIN:
cfd1061e
MK
1518 ar->max_num_peers = TARGET_NUM_PEERS;
1519 ar->max_num_stations = TARGET_NUM_STATIONS;
30c78167 1520 ar->max_num_vdevs = TARGET_NUM_VDEVS;
91ad5f56 1521 ar->htt.max_num_pending_tx = TARGET_NUM_MSDU_DESC;
6274cd41
YL
1522 ar->fw_stats_req_mask = WMI_STAT_PDEV | WMI_STAT_VDEV |
1523 WMI_STAT_PEER;
5c8726ec 1524 ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM;
202e86e6
KV
1525 break;
1526 case ATH10K_FW_WMI_OP_VERSION_10_1:
1527 case ATH10K_FW_WMI_OP_VERSION_10_2:
4a16fbec 1528 case ATH10K_FW_WMI_OP_VERSION_10_2_4:
cc61a1bb 1529 if (ath10k_peer_stats_enabled(ar)) {
af9a6a3a
AK
1530 ar->max_num_peers = TARGET_10X_TX_STATS_NUM_PEERS;
1531 ar->max_num_stations = TARGET_10X_TX_STATS_NUM_STATIONS;
1532 } else {
1533 ar->max_num_peers = TARGET_10X_NUM_PEERS;
1534 ar->max_num_stations = TARGET_10X_NUM_STATIONS;
1535 }
30c78167 1536 ar->max_num_vdevs = TARGET_10X_NUM_VDEVS;
91ad5f56 1537 ar->htt.max_num_pending_tx = TARGET_10X_NUM_MSDU_DESC;
6274cd41 1538 ar->fw_stats_req_mask = WMI_STAT_PEER;
5c8726ec 1539 ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM;
202e86e6 1540 break;
ca996ec5
MK
1541 case ATH10K_FW_WMI_OP_VERSION_TLV:
1542 ar->max_num_peers = TARGET_TLV_NUM_PEERS;
1543 ar->max_num_stations = TARGET_TLV_NUM_STATIONS;
49274332 1544 ar->max_num_vdevs = TARGET_TLV_NUM_VDEVS;
8cca3d60 1545 ar->max_num_tdls_vdevs = TARGET_TLV_NUM_TDLS_VDEVS;
ca996ec5 1546 ar->htt.max_num_pending_tx = TARGET_TLV_NUM_MSDU_DESC;
25c86619 1547 ar->wow.max_num_patterns = TARGET_TLV_NUM_WOW_PATTERNS;
6274cd41
YL
1548 ar->fw_stats_req_mask = WMI_STAT_PDEV | WMI_STAT_VDEV |
1549 WMI_STAT_PEER;
5c8726ec 1550 ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM;
ca996ec5 1551 break;
9bd21322 1552 case ATH10K_FW_WMI_OP_VERSION_10_4:
d1e52a8e
RM
1553 ar->max_num_peers = TARGET_10_4_NUM_PEERS;
1554 ar->max_num_stations = TARGET_10_4_NUM_STATIONS;
1555 ar->num_active_peers = TARGET_10_4_ACTIVE_PEERS;
1556 ar->max_num_vdevs = TARGET_10_4_NUM_VDEVS;
1557 ar->num_tids = TARGET_10_4_TGT_NUM_TIDS;
f9575793
MSS
1558 ar->fw_stats_req_mask = WMI_10_4_STAT_PEER |
1559 WMI_10_4_STAT_PEER_EXTD;
5699a6f2 1560 ar->max_spatial_stream = ar->hw_params.max_spatial_stream;
99ad1cba
MK
1561
1562 if (test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL,
c4cdf753 1563 fw_file->fw_features))
99ad1cba
MK
1564 ar->htt.max_num_pending_tx = TARGET_10_4_NUM_MSDU_DESC_PFC;
1565 else
1566 ar->htt.max_num_pending_tx = TARGET_10_4_NUM_MSDU_DESC;
d1e52a8e 1567 break;
202e86e6
KV
1568 case ATH10K_FW_WMI_OP_VERSION_UNSET:
1569 case ATH10K_FW_WMI_OP_VERSION_MAX:
1570 WARN_ON(1);
1571 return -EINVAL;
cfd1061e 1572 }
5f2144d9 1573
dc3632a1
KV
1574 /* Backwards compatibility for firmwares without
1575 * ATH10K_FW_IE_HTT_OP_VERSION.
1576 */
77561f93 1577 if (fw_file->htt_op_version == ATH10K_FW_HTT_OP_VERSION_UNSET) {
bf3c13ab 1578 switch (fw_file->wmi_op_version) {
dc3632a1 1579 case ATH10K_FW_WMI_OP_VERSION_MAIN:
77561f93 1580 fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_MAIN;
dc3632a1
KV
1581 break;
1582 case ATH10K_FW_WMI_OP_VERSION_10_1:
1583 case ATH10K_FW_WMI_OP_VERSION_10_2:
1584 case ATH10K_FW_WMI_OP_VERSION_10_2_4:
77561f93 1585 fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_10_1;
dc3632a1
KV
1586 break;
1587 case ATH10K_FW_WMI_OP_VERSION_TLV:
77561f93 1588 fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_TLV;
dc3632a1 1589 break;
9bd21322 1590 case ATH10K_FW_WMI_OP_VERSION_10_4:
dc3632a1
KV
1591 case ATH10K_FW_WMI_OP_VERSION_UNSET:
1592 case ATH10K_FW_WMI_OP_VERSION_MAX:
1593 WARN_ON(1);
1594 return -EINVAL;
1595 }
1596 }
1597
5f2144d9 1598 return 0;
cfd1061e
MK
1599}
1600
7ebf721d
KV
1601int ath10k_core_start(struct ath10k *ar, enum ath10k_firmware_mode mode,
1602 const struct ath10k_fw_components *fw)
5e3dd157 1603{
5e3dd157 1604 int status;
f9575793 1605 u32 val;
5e3dd157 1606
60631c5c
KV
1607 lockdep_assert_held(&ar->conf_mutex);
1608
7962b0d8
MK
1609 clear_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags);
1610
7ebf721d
KV
1611 ar->running_fw = fw;
1612
64d151d4
MK
1613 ath10k_bmi_start(ar);
1614
5e3dd157
KV
1615 if (ath10k_init_configure_target(ar)) {
1616 status = -EINVAL;
1617 goto err;
1618 }
1619
83091559
KV
1620 status = ath10k_download_cal_data(ar);
1621 if (status)
1622 goto err;
1623
163f5264 1624 /* Some of of qca988x solutions are having global reset issue
617b0f4d
KV
1625 * during target initialization. Bypassing PLL setting before
1626 * downloading firmware and letting the SoC run on REF_CLK is
1627 * fixing the problem. Corresponding firmware change is also needed
1628 * to set the clock source once the target is initialized.
163f5264
RM
1629 */
1630 if (test_bit(ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT,
c4cdf753 1631 ar->running_fw->fw_file.fw_features)) {
163f5264
RM
1632 status = ath10k_bmi_write32(ar, hi_skip_clock_init, 1);
1633 if (status) {
1634 ath10k_err(ar, "could not write to skip_clock_init: %d\n",
1635 status);
1636 goto err;
1637 }
1638 }
1639
7ebf721d 1640 status = ath10k_download_fw(ar);
5e3dd157
KV
1641 if (status)
1642 goto err;
1643
1644 status = ath10k_init_uart(ar);
1645 if (status)
1646 goto err;
1647
cd003fad
MK
1648 ar->htc.htc_ops.target_send_suspend_complete =
1649 ath10k_send_suspend_complete;
5e3dd157 1650
cd003fad
MK
1651 status = ath10k_htc_init(ar);
1652 if (status) {
7aa7a72a 1653 ath10k_err(ar, "could not init HTC (%d)\n", status);
5e3dd157
KV
1654 goto err;
1655 }
1656
1657 status = ath10k_bmi_done(ar);
1658 if (status)
cd003fad 1659 goto err;
5e3dd157
KV
1660
1661 status = ath10k_wmi_attach(ar);
1662 if (status) {
7aa7a72a 1663 ath10k_err(ar, "WMI attach failed: %d\n", status);
cd003fad 1664 goto err;
5e3dd157
KV
1665 }
1666
95bf21f9
MK
1667 status = ath10k_htt_init(ar);
1668 if (status) {
7aa7a72a 1669 ath10k_err(ar, "failed to init htt: %d\n", status);
95bf21f9
MK
1670 goto err_wmi_detach;
1671 }
1672
1673 status = ath10k_htt_tx_alloc(&ar->htt);
1674 if (status) {
7aa7a72a 1675 ath10k_err(ar, "failed to alloc htt tx: %d\n", status);
95bf21f9
MK
1676 goto err_wmi_detach;
1677 }
1678
1679 status = ath10k_htt_rx_alloc(&ar->htt);
1680 if (status) {
7aa7a72a 1681 ath10k_err(ar, "failed to alloc htt rx: %d\n", status);
95bf21f9
MK
1682 goto err_htt_tx_detach;
1683 }
1684
67e3c63f
MK
1685 status = ath10k_hif_start(ar);
1686 if (status) {
7aa7a72a 1687 ath10k_err(ar, "could not start HIF: %d\n", status);
95bf21f9 1688 goto err_htt_rx_detach;
67e3c63f
MK
1689 }
1690
1691 status = ath10k_htc_wait_target(&ar->htc);
1692 if (status) {
7aa7a72a 1693 ath10k_err(ar, "failed to connect to HTC: %d\n", status);
67e3c63f
MK
1694 goto err_hif_stop;
1695 }
5e3dd157 1696
43d2a30f
KV
1697 if (mode == ATH10K_FIRMWARE_MODE_NORMAL) {
1698 status = ath10k_htt_connect(&ar->htt);
1699 if (status) {
1700 ath10k_err(ar, "failed to connect htt (%d)\n", status);
1701 goto err_hif_stop;
1702 }
5e3dd157
KV
1703 }
1704
95bf21f9
MK
1705 status = ath10k_wmi_connect(ar);
1706 if (status) {
7aa7a72a 1707 ath10k_err(ar, "could not connect wmi: %d\n", status);
95bf21f9
MK
1708 goto err_hif_stop;
1709 }
1710
1711 status = ath10k_htc_start(&ar->htc);
1712 if (status) {
7aa7a72a 1713 ath10k_err(ar, "failed to start htc: %d\n", status);
95bf21f9
MK
1714 goto err_hif_stop;
1715 }
1716
43d2a30f
KV
1717 if (mode == ATH10K_FIRMWARE_MODE_NORMAL) {
1718 status = ath10k_wmi_wait_for_service_ready(ar);
9eea5689 1719 if (status) {
43d2a30f 1720 ath10k_warn(ar, "wmi service ready event not received");
43d2a30f
KV
1721 goto err_hif_stop;
1722 }
95bf21f9 1723 }
5e3dd157 1724
7aa7a72a 1725 ath10k_dbg(ar, ATH10K_DBG_BOOT, "firmware %s booted\n",
c8c39afe 1726 ar->hw->wiphy->fw_version);
5e3dd157 1727
f9575793
MSS
1728 if (test_bit(WMI_SERVICE_EXT_RES_CFG_SUPPORT, ar->wmi.svc_map)) {
1729 val = 0;
1730 if (ath10k_peer_stats_enabled(ar))
1731 val = WMI_10_4_PEER_STATS;
1732
fa7937e3
RM
1733 if (test_bit(WMI_SERVICE_BSS_CHANNEL_INFO_64, ar->wmi.svc_map))
1734 val |= WMI_10_4_BSS_CHANNEL_INFO_64;
1735
7e247a9e 1736 status = ath10k_mac_ext_resource_config(ar, val);
f9575793
MSS
1737 if (status) {
1738 ath10k_err(ar,
1739 "failed to send ext resource cfg command : %d\n",
1740 status);
1741 goto err_hif_stop;
1742 }
1743 }
1744
5e3dd157
KV
1745 status = ath10k_wmi_cmd_init(ar);
1746 if (status) {
7aa7a72a
MK
1747 ath10k_err(ar, "could not send WMI init command (%d)\n",
1748 status);
b7967dc7 1749 goto err_hif_stop;
5e3dd157
KV
1750 }
1751
1752 status = ath10k_wmi_wait_for_unified_ready(ar);
9eea5689 1753 if (status) {
7aa7a72a 1754 ath10k_err(ar, "wmi unified ready event not received\n");
b7967dc7 1755 goto err_hif_stop;
5e3dd157
KV
1756 }
1757
c545070e
MK
1758 /* If firmware indicates Full Rx Reorder support it must be used in a
1759 * slightly different manner. Let HTT code know.
1760 */
1761 ar->htt.rx_ring.in_ord_rx = !!(test_bit(WMI_SERVICE_RX_FULL_REORDER,
1762 ar->wmi.svc_map));
1763
1764 status = ath10k_htt_rx_ring_refill(ar);
1765 if (status) {
1766 ath10k_err(ar, "failed to refill htt rx ring: %d\n", status);
1767 goto err_hif_stop;
1768 }
1769
4ad24a9d
AK
1770 ar->free_vdev_map = (1LL << ar->max_num_vdevs) - 1;
1771
1772 INIT_LIST_HEAD(&ar->arvifs);
1773
43d2a30f
KV
1774 /* we don't care about HTT in UTF mode */
1775 if (mode == ATH10K_FIRMWARE_MODE_NORMAL) {
1776 status = ath10k_htt_setup(&ar->htt);
1777 if (status) {
1778 ath10k_err(ar, "failed to setup htt: %d\n", status);
1779 goto err_hif_stop;
1780 }
95bf21f9 1781 }
5e3dd157 1782
db66ea04
KV
1783 status = ath10k_debug_start(ar);
1784 if (status)
b7967dc7 1785 goto err_hif_stop;
db66ea04 1786
dd30a36e
MK
1787 return 0;
1788
67e3c63f
MK
1789err_hif_stop:
1790 ath10k_hif_stop(ar);
95bf21f9
MK
1791err_htt_rx_detach:
1792 ath10k_htt_rx_free(&ar->htt);
1793err_htt_tx_detach:
1794 ath10k_htt_tx_free(&ar->htt);
dd30a36e
MK
1795err_wmi_detach:
1796 ath10k_wmi_detach(ar);
1797err:
1798 return status;
1799}
818bdd16 1800EXPORT_SYMBOL(ath10k_core_start);
dd30a36e 1801
00f5482b
MP
1802int ath10k_wait_for_suspend(struct ath10k *ar, u32 suspend_opt)
1803{
1804 int ret;
a7a42849 1805 unsigned long time_left;
00f5482b
MP
1806
1807 reinit_completion(&ar->target_suspend);
1808
1809 ret = ath10k_wmi_pdev_suspend_target(ar, suspend_opt);
1810 if (ret) {
7aa7a72a 1811 ath10k_warn(ar, "could not suspend target (%d)\n", ret);
00f5482b
MP
1812 return ret;
1813 }
1814
a7a42849 1815 time_left = wait_for_completion_timeout(&ar->target_suspend, 1 * HZ);
00f5482b 1816
a7a42849 1817 if (!time_left) {
7aa7a72a 1818 ath10k_warn(ar, "suspend timed out - target pause event never came\n");
00f5482b
MP
1819 return -ETIMEDOUT;
1820 }
1821
1822 return 0;
1823}
1824
dd30a36e
MK
1825void ath10k_core_stop(struct ath10k *ar)
1826{
60631c5c 1827 lockdep_assert_held(&ar->conf_mutex);
f1ee2682 1828 ath10k_debug_stop(ar);
60631c5c 1829
00f5482b 1830 /* try to suspend target */
43d2a30f
KV
1831 if (ar->state != ATH10K_STATE_RESTARTING &&
1832 ar->state != ATH10K_STATE_UTF)
216a1836
MK
1833 ath10k_wait_for_suspend(ar, WMI_PDEV_SUSPEND_AND_DISABLE_INTR);
1834
95bf21f9
MK
1835 ath10k_hif_stop(ar);
1836 ath10k_htt_tx_free(&ar->htt);
1837 ath10k_htt_rx_free(&ar->htt);
dd30a36e
MK
1838 ath10k_wmi_detach(ar);
1839}
818bdd16
MK
1840EXPORT_SYMBOL(ath10k_core_stop);
1841
1842/* mac80211 manages fw/hw initialization through start/stop hooks. However in
1843 * order to know what hw capabilities should be advertised to mac80211 it is
1844 * necessary to load the firmware (and tear it down immediately since start
1845 * hook will try to init it again) before registering */
1846static int ath10k_core_probe_fw(struct ath10k *ar)
1847{
29385057
MK
1848 struct bmi_target_info target_info;
1849 int ret = 0;
818bdd16
MK
1850
1851 ret = ath10k_hif_power_up(ar);
1852 if (ret) {
7aa7a72a 1853 ath10k_err(ar, "could not start pci hif (%d)\n", ret);
818bdd16
MK
1854 return ret;
1855 }
1856
29385057
MK
1857 memset(&target_info, 0, sizeof(target_info));
1858 ret = ath10k_bmi_get_target_info(ar, &target_info);
1859 if (ret) {
7aa7a72a 1860 ath10k_err(ar, "could not get target info (%d)\n", ret);
c6ce492d 1861 goto err_power_down;
29385057
MK
1862 }
1863
1864 ar->target_version = target_info.version;
1865 ar->hw->wiphy->hw_version = target_info.version;
1866
1867 ret = ath10k_init_hw_params(ar);
1868 if (ret) {
7aa7a72a 1869 ath10k_err(ar, "could not get hw params (%d)\n", ret);
c6ce492d 1870 goto err_power_down;
29385057
MK
1871 }
1872
1873 ret = ath10k_core_fetch_firmware_files(ar);
1874 if (ret) {
7aa7a72a 1875 ath10k_err(ar, "could not fetch firmware files (%d)\n", ret);
c6ce492d 1876 goto err_power_down;
29385057
MK
1877 }
1878
45317355
KV
1879 BUILD_BUG_ON(sizeof(ar->hw->wiphy->fw_version) !=
1880 sizeof(ar->normal_mode_fw.fw_file.fw_version));
1881 memcpy(ar->hw->wiphy->fw_version, ar->normal_mode_fw.fw_file.fw_version,
1882 sizeof(ar->hw->wiphy->fw_version));
1883
23f591ea
KV
1884 ath10k_debug_print_hwfw_info(ar);
1885
3d9195ea
RM
1886 ret = ath10k_core_pre_cal_download(ar);
1887 if (ret) {
1888 /* pre calibration data download is not necessary
1889 * for all the chipsets. Ignore failures and continue.
1890 */
1891 ath10k_dbg(ar, ATH10K_DBG_BOOT,
1892 "could not load pre cal data: %d\n", ret);
1893 }
1894
db0984e5
MP
1895 ret = ath10k_core_get_board_id_from_otp(ar);
1896 if (ret && ret != -EOPNOTSUPP) {
b091f369 1897 ath10k_err(ar, "failed to get board id from otp: %d\n",
db0984e5 1898 ret);
b9c191be 1899 goto err_free_firmware_files;
db0984e5
MP
1900 }
1901
1902 ret = ath10k_core_fetch_board_file(ar);
1903 if (ret) {
1904 ath10k_err(ar, "failed to fetch board file: %d\n", ret);
1905 goto err_free_firmware_files;
1906 }
1907
23f591ea
KV
1908 ath10k_debug_print_board_info(ar);
1909
5f2144d9
KV
1910 ret = ath10k_core_init_firmware_features(ar);
1911 if (ret) {
1912 ath10k_err(ar, "fatal problem with firmware features: %d\n",
1913 ret);
1914 goto err_free_firmware_files;
1915 }
cfd1061e 1916
dcb02db1
VT
1917 ret = ath10k_swap_code_seg_init(ar);
1918 if (ret) {
1919 ath10k_err(ar, "failed to initialize code swap segment: %d\n",
1920 ret);
1921 goto err_free_firmware_files;
1922 }
1923
60631c5c
KV
1924 mutex_lock(&ar->conf_mutex);
1925
7ebf721d
KV
1926 ret = ath10k_core_start(ar, ATH10K_FIRMWARE_MODE_NORMAL,
1927 &ar->normal_mode_fw);
818bdd16 1928 if (ret) {
7aa7a72a 1929 ath10k_err(ar, "could not init core (%d)\n", ret);
c6ce492d 1930 goto err_unlock;
818bdd16
MK
1931 }
1932
23f591ea 1933 ath10k_debug_print_boot_info(ar);
818bdd16 1934 ath10k_core_stop(ar);
60631c5c
KV
1935
1936 mutex_unlock(&ar->conf_mutex);
1937
818bdd16
MK
1938 ath10k_hif_power_down(ar);
1939 return 0;
c6ce492d
KV
1940
1941err_unlock:
1942 mutex_unlock(&ar->conf_mutex);
1943
5f2144d9 1944err_free_firmware_files:
c6ce492d
KV
1945 ath10k_core_free_firmware_files(ar);
1946
1947err_power_down:
1948 ath10k_hif_power_down(ar);
1949
1950 return ret;
818bdd16 1951}
dd30a36e 1952
6782cb69 1953static void ath10k_core_register_work(struct work_struct *work)
dd30a36e 1954{
6782cb69 1955 struct ath10k *ar = container_of(work, struct ath10k, register_work);
dd30a36e
MK
1956 int status;
1957
818bdd16
MK
1958 status = ath10k_core_probe_fw(ar);
1959 if (status) {
7aa7a72a 1960 ath10k_err(ar, "could not probe fw (%d)\n", status);
6782cb69 1961 goto err;
818bdd16 1962 }
dd30a36e 1963
5e3dd157 1964 status = ath10k_mac_register(ar);
818bdd16 1965 if (status) {
7aa7a72a 1966 ath10k_err(ar, "could not register to mac80211 (%d)\n", status);
29385057 1967 goto err_release_fw;
818bdd16 1968 }
5e3dd157 1969
e13cf7a3 1970 status = ath10k_debug_register(ar);
5e3dd157 1971 if (status) {
7aa7a72a 1972 ath10k_err(ar, "unable to initialize debugfs\n");
5e3dd157
KV
1973 goto err_unregister_mac;
1974 }
1975
855aed12
SW
1976 status = ath10k_spectral_create(ar);
1977 if (status) {
7aa7a72a 1978 ath10k_err(ar, "failed to initialize spectral\n");
855aed12
SW
1979 goto err_debug_destroy;
1980 }
1981
fe6f36d6
RM
1982 status = ath10k_thermal_register(ar);
1983 if (status) {
1984 ath10k_err(ar, "could not register thermal device: %d\n",
1985 status);
1986 goto err_spectral_destroy;
1987 }
1988
6782cb69
MK
1989 set_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags);
1990 return;
5e3dd157 1991
fe6f36d6
RM
1992err_spectral_destroy:
1993 ath10k_spectral_destroy(ar);
855aed12
SW
1994err_debug_destroy:
1995 ath10k_debug_destroy(ar);
5e3dd157
KV
1996err_unregister_mac:
1997 ath10k_mac_unregister(ar);
29385057
MK
1998err_release_fw:
1999 ath10k_core_free_firmware_files(ar);
6782cb69 2000err:
a491a920
MK
2001 /* TODO: It's probably a good idea to release device from the driver
2002 * but calling device_release_driver() here will cause a deadlock.
2003 */
6782cb69
MK
2004 return;
2005}
2006
2007int ath10k_core_register(struct ath10k *ar, u32 chip_id)
2008{
6782cb69 2009 ar->chip_id = chip_id;
6782cb69
MK
2010 queue_work(ar->workqueue, &ar->register_work);
2011
2012 return 0;
5e3dd157
KV
2013}
2014EXPORT_SYMBOL(ath10k_core_register);
2015
2016void ath10k_core_unregister(struct ath10k *ar)
2017{
6782cb69
MK
2018 cancel_work_sync(&ar->register_work);
2019
2020 if (!test_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags))
2021 return;
2022
fe6f36d6 2023 ath10k_thermal_unregister(ar);
804eef14
SW
2024 /* Stop spectral before unregistering from mac80211 to remove the
2025 * relayfs debugfs file cleanly. Otherwise the parent debugfs tree
2026 * would be already be free'd recursively, leading to a double free.
2027 */
2028 ath10k_spectral_destroy(ar);
2029
5e3dd157
KV
2030 /* We must unregister from mac80211 before we stop HTC and HIF.
2031 * Otherwise we will fail to submit commands to FW and mac80211 will be
2032 * unhappy about callback failures. */
2033 ath10k_mac_unregister(ar);
db66ea04 2034
43d2a30f
KV
2035 ath10k_testmode_destroy(ar);
2036
29385057 2037 ath10k_core_free_firmware_files(ar);
0a51b343 2038 ath10k_core_free_board_files(ar);
6f1f56ea 2039
e13cf7a3 2040 ath10k_debug_unregister(ar);
5e3dd157
KV
2041}
2042EXPORT_SYMBOL(ath10k_core_unregister);
2043
e7b54194 2044struct ath10k *ath10k_core_create(size_t priv_size, struct device *dev,
e07db352 2045 enum ath10k_bus bus,
d63955b3 2046 enum ath10k_hw_rev hw_rev,
0d0a6939
MK
2047 const struct ath10k_hif_ops *hif_ops)
2048{
2049 struct ath10k *ar;
e13cf7a3 2050 int ret;
0d0a6939 2051
e7b54194 2052 ar = ath10k_mac_create(priv_size);
0d0a6939
MK
2053 if (!ar)
2054 return NULL;
2055
2056 ar->ath_common.priv = ar;
2057 ar->ath_common.hw = ar->hw;
0d0a6939 2058 ar->dev = dev;
d63955b3 2059 ar->hw_rev = hw_rev;
0d0a6939 2060 ar->hif.ops = hif_ops;
e07db352 2061 ar->hif.bus = bus;
0d0a6939 2062
d63955b3
MK
2063 switch (hw_rev) {
2064 case ATH10K_HW_QCA988X:
2065 ar->regs = &qca988x_regs;
2f2cfc4a 2066 ar->hw_values = &qca988x_values;
d63955b3
MK
2067 break;
2068 case ATH10K_HW_QCA6174:
a226b519 2069 case ATH10K_HW_QCA9377:
d63955b3 2070 ar->regs = &qca6174_regs;
2f2cfc4a 2071 ar->hw_values = &qca6174_values;
d63955b3 2072 break;
8bd47021
VT
2073 case ATH10K_HW_QCA99X0:
2074 ar->regs = &qca99x0_regs;
2075 ar->hw_values = &qca99x0_values;
2076 break;
37a219a5
RM
2077 case ATH10K_HW_QCA4019:
2078 ar->regs = &qca4019_regs;
2079 ar->hw_values = &qca4019_values;
2080 break;
d63955b3
MK
2081 default:
2082 ath10k_err(ar, "unsupported core hardware revision %d\n",
2083 hw_rev);
2084 ret = -ENOTSUPP;
2085 goto err_free_mac;
2086 }
2087
0d0a6939
MK
2088 init_completion(&ar->scan.started);
2089 init_completion(&ar->scan.completed);
2090 init_completion(&ar->scan.on_channel);
2091 init_completion(&ar->target_suspend);
5fd3ac3c 2092 init_completion(&ar->wow.wakeup_completed);
0d0a6939
MK
2093
2094 init_completion(&ar->install_key_done);
2095 init_completion(&ar->vdev_setup_done);
ac2953fc 2096 init_completion(&ar->thermal.wmi_sync);
fa7937e3 2097 init_completion(&ar->bss_survey_done);
0d0a6939 2098
5c81c7fd 2099 INIT_DELAYED_WORK(&ar->scan.timeout, ath10k_scan_timeout_work);
0d0a6939
MK
2100
2101 ar->workqueue = create_singlethread_workqueue("ath10k_wq");
2102 if (!ar->workqueue)
e13cf7a3 2103 goto err_free_mac;
0d0a6939 2104
c8ecfc1c
RM
2105 ar->workqueue_aux = create_singlethread_workqueue("ath10k_aux_wq");
2106 if (!ar->workqueue_aux)
2107 goto err_free_wq;
2108
0d0a6939
MK
2109 mutex_init(&ar->conf_mutex);
2110 spin_lock_init(&ar->data_lock);
29946878 2111 spin_lock_init(&ar->txqs_lock);
0d0a6939 2112
29946878 2113 INIT_LIST_HEAD(&ar->txqs);
0d0a6939
MK
2114 INIT_LIST_HEAD(&ar->peers);
2115 init_waitqueue_head(&ar->peer_mapping_wq);
7962b0d8
MK
2116 init_waitqueue_head(&ar->htt.empty_tx_wq);
2117 init_waitqueue_head(&ar->wmi.tx_credits_wq);
0d0a6939
MK
2118
2119 init_completion(&ar->offchan_tx_completed);
2120 INIT_WORK(&ar->offchan_tx_work, ath10k_offchan_tx_work);
2121 skb_queue_head_init(&ar->offchan_tx_queue);
2122
2123 INIT_WORK(&ar->wmi_mgmt_tx_work, ath10k_mgmt_over_wmi_tx_work);
2124 skb_queue_head_init(&ar->wmi_mgmt_tx_queue);
2125
6782cb69 2126 INIT_WORK(&ar->register_work, ath10k_core_register_work);
0d0a6939
MK
2127 INIT_WORK(&ar->restart_work, ath10k_core_restart);
2128
e13cf7a3
MK
2129 ret = ath10k_debug_create(ar);
2130 if (ret)
c8ecfc1c 2131 goto err_free_aux_wq;
e13cf7a3 2132
0d0a6939
MK
2133 return ar;
2134
c8ecfc1c
RM
2135err_free_aux_wq:
2136 destroy_workqueue(ar->workqueue_aux);
e13cf7a3
MK
2137err_free_wq:
2138 destroy_workqueue(ar->workqueue);
2139
2140err_free_mac:
0d0a6939 2141 ath10k_mac_destroy(ar);
e13cf7a3 2142
0d0a6939
MK
2143 return NULL;
2144}
2145EXPORT_SYMBOL(ath10k_core_create);
2146
2147void ath10k_core_destroy(struct ath10k *ar)
2148{
2149 flush_workqueue(ar->workqueue);
2150 destroy_workqueue(ar->workqueue);
2151
c8ecfc1c
RM
2152 flush_workqueue(ar->workqueue_aux);
2153 destroy_workqueue(ar->workqueue_aux);
2154
e13cf7a3 2155 ath10k_debug_destroy(ar);
a925a376 2156 ath10k_wmi_free_host_mem(ar);
0d0a6939
MK
2157 ath10k_mac_destroy(ar);
2158}
2159EXPORT_SYMBOL(ath10k_core_destroy);
2160
5e3dd157
KV
2161MODULE_AUTHOR("Qualcomm Atheros");
2162MODULE_DESCRIPTION("Core module for QCA988X PCIe devices.");
2163MODULE_LICENSE("Dual BSD/GPL");