]>
Commit | Line | Data |
---|---|---|
5e3dd157 KV |
1 | /* |
2 | * Copyright (c) 2005-2011 Atheros Communications Inc. | |
3 | * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. | |
4 | * | |
5 | * Permission to use, copy, modify, and/or distribute this software for any | |
6 | * purpose with or without fee is hereby granted, provided that the above | |
7 | * copyright notice and this permission notice appear in all copies. | |
8 | * | |
9 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
10 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
11 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
12 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
13 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
14 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
15 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
16 | */ | |
17 | ||
18 | #include <linux/module.h> | |
19 | #include <linux/firmware.h> | |
5aabff05 | 20 | #include <linux/of.h> |
6847f967 | 21 | #include <asm/byteorder.h> |
5e3dd157 KV |
22 | |
23 | #include "core.h" | |
24 | #include "mac.h" | |
25 | #include "htc.h" | |
26 | #include "hif.h" | |
27 | #include "wmi.h" | |
28 | #include "bmi.h" | |
29 | #include "debug.h" | |
30 | #include "htt.h" | |
43d2a30f | 31 | #include "testmode.h" |
d7579d12 | 32 | #include "wmi-ops.h" |
5e3dd157 KV |
33 | |
34 | unsigned int ath10k_debug_mask; | |
ccec9038 | 35 | static unsigned int ath10k_cryptmode_param; |
5e3dd157 | 36 | static bool uart_print; |
8868b12c | 37 | static bool skip_otp; |
b6c7bafa | 38 | static bool rawmode; |
8868b12c | 39 | |
5e3dd157 | 40 | module_param_named(debug_mask, ath10k_debug_mask, uint, 0644); |
ccec9038 | 41 | module_param_named(cryptmode, ath10k_cryptmode_param, uint, 0644); |
5e3dd157 | 42 | module_param(uart_print, bool, 0644); |
8868b12c | 43 | module_param(skip_otp, bool, 0644); |
b6c7bafa | 44 | module_param(rawmode, bool, 0644); |
8868b12c | 45 | |
5e3dd157 KV |
46 | MODULE_PARM_DESC(debug_mask, "Debugging mask"); |
47 | MODULE_PARM_DESC(uart_print, "Uart target debugging"); | |
8868b12c | 48 | MODULE_PARM_DESC(skip_otp, "Skip otp failure for calibration in testmode"); |
ccec9038 | 49 | MODULE_PARM_DESC(cryptmode, "Crypto mode: 0-hardware, 1-software"); |
b6c7bafa | 50 | MODULE_PARM_DESC(rawmode, "Use raw 802.11 frame datapath"); |
5e3dd157 KV |
51 | |
52 | static const struct ath10k_hw_params ath10k_hw_params_list[] = { | |
5e3dd157 KV |
53 | { |
54 | .id = QCA988X_HW_2_0_VERSION, | |
079a0490 | 55 | .dev_id = QCA988X_2_0_DEVICE_ID, |
5e3dd157 KV |
56 | .name = "qca988x hw2.0", |
57 | .patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR, | |
3a8200b2 | 58 | .uart_pin = 7, |
26c19760 | 59 | .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL, |
d772703e | 60 | .otp_exe_param = 0, |
9c8fb548 | 61 | .channel_counters_freq_hz = 88000, |
7b7da0a0 | 62 | .max_probe_resp_desc_thres = 0, |
0b8e3c4c | 63 | .cal_data_len = 2116, |
5e3dd157 KV |
64 | .fw = { |
65 | .dir = QCA988X_HW_2_0_FW_DIR, | |
5e3dd157 | 66 | .board = QCA988X_HW_2_0_BOARD_DATA_FILE, |
9764a2af MK |
67 | .board_size = QCA988X_BOARD_DATA_SZ, |
68 | .board_ext_size = QCA988X_BOARD_EXT_DATA_SZ, | |
5e3dd157 | 69 | }, |
ae02c871 | 70 | .hw_ops = &qca988x_ops, |
2f38c3c0 | 71 | .decap_align_bytes = 4, |
5e3dd157 | 72 | }, |
6fd3dd71 SE |
73 | { |
74 | .id = QCA9887_HW_1_0_VERSION, | |
75 | .dev_id = QCA9887_1_0_DEVICE_ID, | |
76 | .name = "qca9887 hw1.0", | |
77 | .patch_load_addr = QCA9887_HW_1_0_PATCH_LOAD_ADDR, | |
78 | .uart_pin = 7, | |
26c19760 | 79 | .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_ALL, |
6fd3dd71 SE |
80 | .otp_exe_param = 0, |
81 | .channel_counters_freq_hz = 88000, | |
82 | .max_probe_resp_desc_thres = 0, | |
6fd3dd71 SE |
83 | .cal_data_len = 2116, |
84 | .fw = { | |
85 | .dir = QCA9887_HW_1_0_FW_DIR, | |
86 | .board = QCA9887_HW_1_0_BOARD_DATA_FILE, | |
87 | .board_size = QCA9887_BOARD_DATA_SZ, | |
88 | .board_ext_size = QCA9887_BOARD_EXT_DATA_SZ, | |
89 | }, | |
ae02c871 | 90 | .hw_ops = &qca988x_ops, |
2f38c3c0 | 91 | .decap_align_bytes = 4, |
6fd3dd71 | 92 | }, |
d63955b3 MK |
93 | { |
94 | .id = QCA6174_HW_2_1_VERSION, | |
079a0490 BM |
95 | .dev_id = QCA6164_2_1_DEVICE_ID, |
96 | .name = "qca6164 hw2.1", | |
97 | .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR, | |
98 | .uart_pin = 6, | |
99 | .otp_exe_param = 0, | |
100 | .channel_counters_freq_hz = 88000, | |
101 | .max_probe_resp_desc_thres = 0, | |
0b8e3c4c | 102 | .cal_data_len = 8124, |
079a0490 BM |
103 | .fw = { |
104 | .dir = QCA6174_HW_2_1_FW_DIR, | |
079a0490 BM |
105 | .board = QCA6174_HW_2_1_BOARD_DATA_FILE, |
106 | .board_size = QCA6174_BOARD_DATA_SZ, | |
107 | .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, | |
108 | }, | |
ae02c871 | 109 | .hw_ops = &qca988x_ops, |
2f38c3c0 | 110 | .decap_align_bytes = 4, |
079a0490 BM |
111 | }, |
112 | { | |
113 | .id = QCA6174_HW_2_1_VERSION, | |
114 | .dev_id = QCA6174_2_1_DEVICE_ID, | |
d63955b3 MK |
115 | .name = "qca6174 hw2.1", |
116 | .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR, | |
117 | .uart_pin = 6, | |
d772703e | 118 | .otp_exe_param = 0, |
9c8fb548 | 119 | .channel_counters_freq_hz = 88000, |
7b7da0a0 | 120 | .max_probe_resp_desc_thres = 0, |
0b8e3c4c | 121 | .cal_data_len = 8124, |
d63955b3 MK |
122 | .fw = { |
123 | .dir = QCA6174_HW_2_1_FW_DIR, | |
d63955b3 MK |
124 | .board = QCA6174_HW_2_1_BOARD_DATA_FILE, |
125 | .board_size = QCA6174_BOARD_DATA_SZ, | |
126 | .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, | |
127 | }, | |
ae02c871 | 128 | .hw_ops = &qca988x_ops, |
2f38c3c0 | 129 | .decap_align_bytes = 4, |
d63955b3 MK |
130 | }, |
131 | { | |
132 | .id = QCA6174_HW_3_0_VERSION, | |
079a0490 | 133 | .dev_id = QCA6174_2_1_DEVICE_ID, |
d63955b3 MK |
134 | .name = "qca6174 hw3.0", |
135 | .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR, | |
136 | .uart_pin = 6, | |
d772703e | 137 | .otp_exe_param = 0, |
9c8fb548 | 138 | .channel_counters_freq_hz = 88000, |
7b7da0a0 | 139 | .max_probe_resp_desc_thres = 0, |
0b8e3c4c | 140 | .cal_data_len = 8124, |
d63955b3 MK |
141 | .fw = { |
142 | .dir = QCA6174_HW_3_0_FW_DIR, | |
d63955b3 MK |
143 | .board = QCA6174_HW_3_0_BOARD_DATA_FILE, |
144 | .board_size = QCA6174_BOARD_DATA_SZ, | |
145 | .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, | |
146 | }, | |
ae02c871 | 147 | .hw_ops = &qca988x_ops, |
2f38c3c0 | 148 | .decap_align_bytes = 4, |
d63955b3 | 149 | }, |
608b8f73 MK |
150 | { |
151 | .id = QCA6174_HW_3_2_VERSION, | |
079a0490 | 152 | .dev_id = QCA6174_2_1_DEVICE_ID, |
608b8f73 MK |
153 | .name = "qca6174 hw3.2", |
154 | .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR, | |
155 | .uart_pin = 6, | |
d772703e | 156 | .otp_exe_param = 0, |
9c8fb548 | 157 | .channel_counters_freq_hz = 88000, |
7b7da0a0 | 158 | .max_probe_resp_desc_thres = 0, |
0b8e3c4c | 159 | .cal_data_len = 8124, |
608b8f73 MK |
160 | .fw = { |
161 | /* uses same binaries as hw3.0 */ | |
162 | .dir = QCA6174_HW_3_0_FW_DIR, | |
608b8f73 MK |
163 | .board = QCA6174_HW_3_0_BOARD_DATA_FILE, |
164 | .board_size = QCA6174_BOARD_DATA_SZ, | |
165 | .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, | |
166 | }, | |
ae02c871 | 167 | .hw_ops = &qca988x_ops, |
2f38c3c0 | 168 | .decap_align_bytes = 4, |
608b8f73 | 169 | }, |
8bd47021 VT |
170 | { |
171 | .id = QCA99X0_HW_2_0_DEV_VERSION, | |
079a0490 | 172 | .dev_id = QCA99X0_2_0_DEVICE_ID, |
8bd47021 VT |
173 | .name = "qca99x0 hw2.0", |
174 | .patch_load_addr = QCA99X0_HW_2_0_PATCH_LOAD_ADDR, | |
175 | .uart_pin = 7, | |
d772703e | 176 | .otp_exe_param = 0x00000700, |
d9156b5f | 177 | .continuous_frag_desc = true, |
5269c659 | 178 | .cck_rate_map_rev2 = true, |
9c8fb548 | 179 | .channel_counters_freq_hz = 150000, |
7b7da0a0 | 180 | .max_probe_resp_desc_thres = 24, |
5699a6f2 RM |
181 | .tx_chain_mask = 0xf, |
182 | .rx_chain_mask = 0xf, | |
183 | .max_spatial_stream = 4, | |
0b8e3c4c | 184 | .cal_data_len = 12064, |
8bd47021 VT |
185 | .fw = { |
186 | .dir = QCA99X0_HW_2_0_FW_DIR, | |
8bd47021 VT |
187 | .board = QCA99X0_HW_2_0_BOARD_DATA_FILE, |
188 | .board_size = QCA99X0_BOARD_DATA_SZ, | |
189 | .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ, | |
190 | }, | |
7d42298e | 191 | .sw_decrypt_mcast_mgmt = true, |
ae02c871 | 192 | .hw_ops = &qca99x0_ops, |
2f38c3c0 | 193 | .decap_align_bytes = 1, |
8bd47021 | 194 | }, |
651b4cdc VT |
195 | { |
196 | .id = QCA9984_HW_1_0_DEV_VERSION, | |
197 | .dev_id = QCA9984_1_0_DEVICE_ID, | |
198 | .name = "qca9984/qca9994 hw1.0", | |
199 | .patch_load_addr = QCA9984_HW_1_0_PATCH_LOAD_ADDR, | |
200 | .uart_pin = 7, | |
201 | .otp_exe_param = 0x00000700, | |
202 | .continuous_frag_desc = true, | |
5269c659 | 203 | .cck_rate_map_rev2 = true, |
651b4cdc VT |
204 | .channel_counters_freq_hz = 150000, |
205 | .max_probe_resp_desc_thres = 24, | |
651b4cdc VT |
206 | .tx_chain_mask = 0xf, |
207 | .rx_chain_mask = 0xf, | |
208 | .max_spatial_stream = 4, | |
209 | .cal_data_len = 12064, | |
210 | .fw = { | |
211 | .dir = QCA9984_HW_1_0_FW_DIR, | |
212 | .board = QCA9984_HW_1_0_BOARD_DATA_FILE, | |
213 | .board_size = QCA99X0_BOARD_DATA_SZ, | |
214 | .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ, | |
215 | }, | |
7d42298e | 216 | .sw_decrypt_mcast_mgmt = true, |
ae02c871 | 217 | .hw_ops = &qca99x0_ops, |
2f38c3c0 | 218 | .decap_align_bytes = 1, |
651b4cdc | 219 | }, |
e565c312 AK |
220 | { |
221 | .id = QCA9888_HW_2_0_DEV_VERSION, | |
222 | .dev_id = QCA9888_2_0_DEVICE_ID, | |
223 | .name = "qca9888 hw2.0", | |
224 | .patch_load_addr = QCA9888_HW_2_0_PATCH_LOAD_ADDR, | |
225 | .uart_pin = 7, | |
226 | .otp_exe_param = 0x00000700, | |
227 | .continuous_frag_desc = true, | |
228 | .channel_counters_freq_hz = 150000, | |
229 | .max_probe_resp_desc_thres = 24, | |
e565c312 AK |
230 | .tx_chain_mask = 3, |
231 | .rx_chain_mask = 3, | |
232 | .max_spatial_stream = 2, | |
233 | .cal_data_len = 12064, | |
234 | .fw = { | |
235 | .dir = QCA9888_HW_2_0_FW_DIR, | |
236 | .board = QCA9888_HW_2_0_BOARD_DATA_FILE, | |
237 | .board_size = QCA99X0_BOARD_DATA_SZ, | |
238 | .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ, | |
239 | }, | |
7d42298e | 240 | .sw_decrypt_mcast_mgmt = true, |
ae02c871 | 241 | .hw_ops = &qca99x0_ops, |
2f38c3c0 | 242 | .decap_align_bytes = 1, |
e565c312 | 243 | }, |
034074f3 BM |
244 | { |
245 | .id = QCA9377_HW_1_0_DEV_VERSION, | |
246 | .dev_id = QCA9377_1_0_DEVICE_ID, | |
247 | .name = "qca9377 hw1.0", | |
248 | .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR, | |
249 | .uart_pin = 6, | |
250 | .otp_exe_param = 0, | |
251 | .channel_counters_freq_hz = 88000, | |
252 | .max_probe_resp_desc_thres = 0, | |
0b8e3c4c | 253 | .cal_data_len = 8124, |
034074f3 BM |
254 | .fw = { |
255 | .dir = QCA9377_HW_1_0_FW_DIR, | |
034074f3 BM |
256 | .board = QCA9377_HW_1_0_BOARD_DATA_FILE, |
257 | .board_size = QCA9377_BOARD_DATA_SZ, | |
258 | .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ, | |
259 | }, | |
ae02c871 | 260 | .hw_ops = &qca988x_ops, |
2f38c3c0 | 261 | .decap_align_bytes = 4, |
034074f3 | 262 | }, |
a226b519 | 263 | { |
12551ced | 264 | .id = QCA9377_HW_1_1_DEV_VERSION, |
079a0490 | 265 | .dev_id = QCA9377_1_0_DEVICE_ID, |
12551ced | 266 | .name = "qca9377 hw1.1", |
a226b519 | 267 | .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR, |
6cf21395 | 268 | .uart_pin = 6, |
a226b519 | 269 | .otp_exe_param = 0, |
6cf21395 BM |
270 | .channel_counters_freq_hz = 88000, |
271 | .max_probe_resp_desc_thres = 0, | |
0b8e3c4c | 272 | .cal_data_len = 8124, |
a226b519 BM |
273 | .fw = { |
274 | .dir = QCA9377_HW_1_0_FW_DIR, | |
a226b519 BM |
275 | .board = QCA9377_HW_1_0_BOARD_DATA_FILE, |
276 | .board_size = QCA9377_BOARD_DATA_SZ, | |
277 | .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ, | |
278 | }, | |
ae02c871 | 279 | .hw_ops = &qca988x_ops, |
2f38c3c0 | 280 | .decap_align_bytes = 4, |
a226b519 | 281 | }, |
b1a958c9 RM |
282 | { |
283 | .id = QCA4019_HW_1_0_DEV_VERSION, | |
284 | .dev_id = 0, | |
285 | .name = "qca4019 hw1.0", | |
286 | .patch_load_addr = QCA4019_HW_1_0_PATCH_LOAD_ADDR, | |
287 | .uart_pin = 7, | |
8e100354 | 288 | .cc_wraparound_type = ATH10K_HW_CC_WRAP_SHIFTED_EACH, |
b1a958c9 RM |
289 | .otp_exe_param = 0x0010000, |
290 | .continuous_frag_desc = true, | |
5269c659 | 291 | .cck_rate_map_rev2 = true, |
b1a958c9 RM |
292 | .channel_counters_freq_hz = 125000, |
293 | .max_probe_resp_desc_thres = 24, | |
5699a6f2 RM |
294 | .tx_chain_mask = 0x3, |
295 | .rx_chain_mask = 0x3, | |
296 | .max_spatial_stream = 2, | |
0b8e3c4c | 297 | .cal_data_len = 12064, |
b1a958c9 RM |
298 | .fw = { |
299 | .dir = QCA4019_HW_1_0_FW_DIR, | |
b1a958c9 RM |
300 | .board = QCA4019_HW_1_0_BOARD_DATA_FILE, |
301 | .board_size = QCA4019_BOARD_DATA_SZ, | |
302 | .board_ext_size = QCA4019_BOARD_EXT_DATA_SZ, | |
303 | }, | |
7d42298e | 304 | .sw_decrypt_mcast_mgmt = true, |
ae02c871 | 305 | .hw_ops = &qca99x0_ops, |
2f38c3c0 | 306 | .decap_align_bytes = 1, |
b1a958c9 | 307 | }, |
5e3dd157 KV |
308 | }; |
309 | ||
b27bc5a4 MK |
310 | static const char *const ath10k_core_fw_feature_str[] = { |
311 | [ATH10K_FW_FEATURE_EXT_WMI_MGMT_RX] = "wmi-mgmt-rx", | |
312 | [ATH10K_FW_FEATURE_WMI_10X] = "wmi-10.x", | |
313 | [ATH10K_FW_FEATURE_HAS_WMI_MGMT_TX] = "has-wmi-mgmt-tx", | |
314 | [ATH10K_FW_FEATURE_NO_P2P] = "no-p2p", | |
315 | [ATH10K_FW_FEATURE_WMI_10_2] = "wmi-10.2", | |
316 | [ATH10K_FW_FEATURE_MULTI_VIF_PS_SUPPORT] = "multi-vif-ps", | |
317 | [ATH10K_FW_FEATURE_WOWLAN_SUPPORT] = "wowlan", | |
318 | [ATH10K_FW_FEATURE_IGNORE_OTP_RESULT] = "ignore-otp", | |
319 | [ATH10K_FW_FEATURE_NO_NWIFI_DECAP_4ADDR_PADDING] = "no-4addr-pad", | |
320 | [ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT] = "skip-clock-init", | |
5af82fa6 | 321 | [ATH10K_FW_FEATURE_RAW_MODE_SUPPORT] = "raw-mode", |
62f77f09 | 322 | [ATH10K_FW_FEATURE_SUPPORTS_ADAPTIVE_CCA] = "adaptive-cca", |
90eceb3b | 323 | [ATH10K_FW_FEATURE_MFP_SUPPORT] = "mfp", |
9b783763 | 324 | [ATH10K_FW_FEATURE_PEER_FLOW_CONTROL] = "peer-flow-ctrl", |
64e001f4 | 325 | [ATH10K_FW_FEATURE_BTCOEX_PARAM] = "btcoex-param", |
2cdce425 | 326 | [ATH10K_FW_FEATURE_SKIP_NULL_FUNC_WAR] = "skip-null-func-war", |
b27bc5a4 MK |
327 | }; |
328 | ||
329 | static unsigned int ath10k_core_get_fw_feature_str(char *buf, | |
330 | size_t buf_len, | |
331 | enum ath10k_fw_features feat) | |
332 | { | |
5af82fa6 KV |
333 | /* make sure that ath10k_core_fw_feature_str[] gets updated */ |
334 | BUILD_BUG_ON(ARRAY_SIZE(ath10k_core_fw_feature_str) != | |
335 | ATH10K_FW_FEATURE_COUNT); | |
336 | ||
b27bc5a4 MK |
337 | if (feat >= ARRAY_SIZE(ath10k_core_fw_feature_str) || |
338 | WARN_ON(!ath10k_core_fw_feature_str[feat])) { | |
339 | return scnprintf(buf, buf_len, "bit%d", feat); | |
340 | } | |
341 | ||
342 | return scnprintf(buf, buf_len, "%s", ath10k_core_fw_feature_str[feat]); | |
343 | } | |
344 | ||
345 | void ath10k_core_get_fw_features_str(struct ath10k *ar, | |
346 | char *buf, | |
347 | size_t buf_len) | |
348 | { | |
349 | unsigned int len = 0; | |
350 | int i; | |
351 | ||
352 | for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) { | |
c4cdf753 | 353 | if (test_bit(i, ar->normal_mode_fw.fw_file.fw_features)) { |
b27bc5a4 MK |
354 | if (len > 0) |
355 | len += scnprintf(buf + len, buf_len - len, ","); | |
356 | ||
357 | len += ath10k_core_get_fw_feature_str(buf + len, | |
358 | buf_len - len, | |
359 | i); | |
360 | } | |
361 | } | |
362 | } | |
363 | ||
5e3dd157 KV |
364 | static void ath10k_send_suspend_complete(struct ath10k *ar) |
365 | { | |
7aa7a72a | 366 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot suspend complete\n"); |
5e3dd157 | 367 | |
9042e17d | 368 | complete(&ar->target_suspend); |
5e3dd157 KV |
369 | } |
370 | ||
5e3dd157 KV |
371 | static int ath10k_init_configure_target(struct ath10k *ar) |
372 | { | |
373 | u32 param_host; | |
374 | int ret; | |
375 | ||
376 | /* tell target which HTC version it is used*/ | |
377 | ret = ath10k_bmi_write32(ar, hi_app_host_interest, | |
378 | HTC_PROTOCOL_VERSION); | |
379 | if (ret) { | |
7aa7a72a | 380 | ath10k_err(ar, "settings HTC version failed\n"); |
5e3dd157 KV |
381 | return ret; |
382 | } | |
383 | ||
384 | /* set the firmware mode to STA/IBSS/AP */ | |
385 | ret = ath10k_bmi_read32(ar, hi_option_flag, ¶m_host); | |
386 | if (ret) { | |
7aa7a72a | 387 | ath10k_err(ar, "setting firmware mode (1/2) failed\n"); |
5e3dd157 KV |
388 | return ret; |
389 | } | |
390 | ||
391 | /* TODO following parameters need to be re-visited. */ | |
392 | /* num_device */ | |
393 | param_host |= (1 << HI_OPTION_NUM_DEV_SHIFT); | |
394 | /* Firmware mode */ | |
395 | /* FIXME: Why FW_MODE_AP ??.*/ | |
396 | param_host |= (HI_OPTION_FW_MODE_AP << HI_OPTION_FW_MODE_SHIFT); | |
397 | /* mac_addr_method */ | |
398 | param_host |= (1 << HI_OPTION_MAC_ADDR_METHOD_SHIFT); | |
399 | /* firmware_bridge */ | |
400 | param_host |= (0 << HI_OPTION_FW_BRIDGE_SHIFT); | |
401 | /* fwsubmode */ | |
402 | param_host |= (0 << HI_OPTION_FW_SUBMODE_SHIFT); | |
403 | ||
404 | ret = ath10k_bmi_write32(ar, hi_option_flag, param_host); | |
405 | if (ret) { | |
7aa7a72a | 406 | ath10k_err(ar, "setting firmware mode (2/2) failed\n"); |
5e3dd157 KV |
407 | return ret; |
408 | } | |
409 | ||
410 | /* We do all byte-swapping on the host */ | |
411 | ret = ath10k_bmi_write32(ar, hi_be, 0); | |
412 | if (ret) { | |
7aa7a72a | 413 | ath10k_err(ar, "setting host CPU BE mode failed\n"); |
5e3dd157 KV |
414 | return ret; |
415 | } | |
416 | ||
417 | /* FW descriptor/Data swap flags */ | |
418 | ret = ath10k_bmi_write32(ar, hi_fw_swap, 0); | |
419 | ||
420 | if (ret) { | |
7aa7a72a | 421 | ath10k_err(ar, "setting FW data/desc swap flags failed\n"); |
5e3dd157 KV |
422 | return ret; |
423 | } | |
424 | ||
36582e5d MK |
425 | /* Some devices have a special sanity check that verifies the PCI |
426 | * Device ID is written to this host interest var. It is known to be | |
427 | * required to boot QCA6164. | |
428 | */ | |
429 | ret = ath10k_bmi_write32(ar, hi_hci_uart_pwr_mgmt_params_ext, | |
430 | ar->dev_id); | |
431 | if (ret) { | |
432 | ath10k_err(ar, "failed to set pwr_mgmt_params: %d\n", ret); | |
433 | return ret; | |
434 | } | |
435 | ||
5e3dd157 KV |
436 | return 0; |
437 | } | |
438 | ||
439 | static const struct firmware *ath10k_fetch_fw_file(struct ath10k *ar, | |
440 | const char *dir, | |
441 | const char *file) | |
442 | { | |
443 | char filename[100]; | |
444 | const struct firmware *fw; | |
445 | int ret; | |
446 | ||
447 | if (file == NULL) | |
448 | return ERR_PTR(-ENOENT); | |
449 | ||
450 | if (dir == NULL) | |
451 | dir = "."; | |
452 | ||
453 | snprintf(filename, sizeof(filename), "%s/%s", dir, file); | |
454 | ret = request_firmware(&fw, filename, ar->dev); | |
455 | if (ret) | |
456 | return ERR_PTR(ret); | |
457 | ||
458 | return fw; | |
459 | } | |
460 | ||
a58227ef KV |
461 | static int ath10k_push_board_ext_data(struct ath10k *ar, const void *data, |
462 | size_t data_len) | |
5e3dd157 | 463 | { |
9764a2af MK |
464 | u32 board_data_size = ar->hw_params.fw.board_size; |
465 | u32 board_ext_data_size = ar->hw_params.fw.board_ext_size; | |
5e3dd157 KV |
466 | u32 board_ext_data_addr; |
467 | int ret; | |
468 | ||
469 | ret = ath10k_bmi_read32(ar, hi_board_ext_data, &board_ext_data_addr); | |
470 | if (ret) { | |
7aa7a72a MK |
471 | ath10k_err(ar, "could not read board ext data addr (%d)\n", |
472 | ret); | |
5e3dd157 KV |
473 | return ret; |
474 | } | |
475 | ||
7aa7a72a | 476 | ath10k_dbg(ar, ATH10K_DBG_BOOT, |
effea968 | 477 | "boot push board extended data addr 0x%x\n", |
5e3dd157 KV |
478 | board_ext_data_addr); |
479 | ||
480 | if (board_ext_data_addr == 0) | |
481 | return 0; | |
482 | ||
a58227ef | 483 | if (data_len != (board_data_size + board_ext_data_size)) { |
7aa7a72a | 484 | ath10k_err(ar, "invalid board (ext) data sizes %zu != %d+%d\n", |
a58227ef | 485 | data_len, board_data_size, board_ext_data_size); |
5e3dd157 KV |
486 | return -EINVAL; |
487 | } | |
488 | ||
489 | ret = ath10k_bmi_write_memory(ar, board_ext_data_addr, | |
a58227ef | 490 | data + board_data_size, |
5e3dd157 KV |
491 | board_ext_data_size); |
492 | if (ret) { | |
7aa7a72a | 493 | ath10k_err(ar, "could not write board ext data (%d)\n", ret); |
5e3dd157 KV |
494 | return ret; |
495 | } | |
496 | ||
497 | ret = ath10k_bmi_write32(ar, hi_board_ext_data_config, | |
498 | (board_ext_data_size << 16) | 1); | |
499 | if (ret) { | |
7aa7a72a MK |
500 | ath10k_err(ar, "could not write board ext data bit (%d)\n", |
501 | ret); | |
5e3dd157 KV |
502 | return ret; |
503 | } | |
504 | ||
505 | return 0; | |
506 | } | |
507 | ||
a58227ef KV |
508 | static int ath10k_download_board_data(struct ath10k *ar, const void *data, |
509 | size_t data_len) | |
5e3dd157 | 510 | { |
9764a2af | 511 | u32 board_data_size = ar->hw_params.fw.board_size; |
5e3dd157 | 512 | u32 address; |
5e3dd157 KV |
513 | int ret; |
514 | ||
a58227ef | 515 | ret = ath10k_push_board_ext_data(ar, data, data_len); |
5e3dd157 | 516 | if (ret) { |
7aa7a72a | 517 | ath10k_err(ar, "could not push board ext data (%d)\n", ret); |
5e3dd157 KV |
518 | goto exit; |
519 | } | |
520 | ||
521 | ret = ath10k_bmi_read32(ar, hi_board_data, &address); | |
522 | if (ret) { | |
7aa7a72a | 523 | ath10k_err(ar, "could not read board data addr (%d)\n", ret); |
5e3dd157 KV |
524 | goto exit; |
525 | } | |
526 | ||
a58227ef | 527 | ret = ath10k_bmi_write_memory(ar, address, data, |
958df3a0 | 528 | min_t(u32, board_data_size, |
a58227ef | 529 | data_len)); |
5e3dd157 | 530 | if (ret) { |
7aa7a72a | 531 | ath10k_err(ar, "could not write board data (%d)\n", ret); |
5e3dd157 KV |
532 | goto exit; |
533 | } | |
534 | ||
535 | ret = ath10k_bmi_write32(ar, hi_board_data_initialized, 1); | |
536 | if (ret) { | |
7aa7a72a | 537 | ath10k_err(ar, "could not write board data bit (%d)\n", ret); |
5e3dd157 KV |
538 | goto exit; |
539 | } | |
540 | ||
541 | exit: | |
5e3dd157 KV |
542 | return ret; |
543 | } | |
544 | ||
f454add4 RM |
545 | static int ath10k_download_cal_file(struct ath10k *ar, |
546 | const struct firmware *file) | |
a58227ef KV |
547 | { |
548 | int ret; | |
549 | ||
f454add4 | 550 | if (!file) |
a58227ef KV |
551 | return -ENOENT; |
552 | ||
f454add4 RM |
553 | if (IS_ERR(file)) |
554 | return PTR_ERR(file); | |
a58227ef | 555 | |
f454add4 | 556 | ret = ath10k_download_board_data(ar, file->data, file->size); |
a58227ef KV |
557 | if (ret) { |
558 | ath10k_err(ar, "failed to download cal_file data: %d\n", ret); | |
559 | return ret; | |
560 | } | |
561 | ||
562 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cal file downloaded\n"); | |
563 | ||
564 | return 0; | |
565 | } | |
566 | ||
f454add4 | 567 | static int ath10k_download_cal_dt(struct ath10k *ar, const char *dt_name) |
5aabff05 TK |
568 | { |
569 | struct device_node *node; | |
570 | int data_len; | |
571 | void *data; | |
572 | int ret; | |
573 | ||
574 | node = ar->dev->of_node; | |
575 | if (!node) | |
576 | /* Device Tree is optional, don't print any warnings if | |
577 | * there's no node for ath10k. | |
578 | */ | |
579 | return -ENOENT; | |
580 | ||
f454add4 | 581 | if (!of_get_property(node, dt_name, &data_len)) { |
5aabff05 TK |
582 | /* The calibration data node is optional */ |
583 | return -ENOENT; | |
584 | } | |
585 | ||
0b8e3c4c | 586 | if (data_len != ar->hw_params.cal_data_len) { |
5aabff05 TK |
587 | ath10k_warn(ar, "invalid calibration data length in DT: %d\n", |
588 | data_len); | |
589 | ret = -EMSGSIZE; | |
590 | goto out; | |
591 | } | |
592 | ||
593 | data = kmalloc(data_len, GFP_KERNEL); | |
594 | if (!data) { | |
595 | ret = -ENOMEM; | |
596 | goto out; | |
597 | } | |
598 | ||
f454add4 | 599 | ret = of_property_read_u8_array(node, dt_name, data, data_len); |
5aabff05 TK |
600 | if (ret) { |
601 | ath10k_warn(ar, "failed to read calibration data from DT: %d\n", | |
602 | ret); | |
603 | goto out_free; | |
604 | } | |
605 | ||
606 | ret = ath10k_download_board_data(ar, data, data_len); | |
607 | if (ret) { | |
608 | ath10k_warn(ar, "failed to download calibration data from Device Tree: %d\n", | |
609 | ret); | |
610 | goto out_free; | |
611 | } | |
612 | ||
613 | ret = 0; | |
614 | ||
615 | out_free: | |
616 | kfree(data); | |
617 | ||
618 | out: | |
619 | return ret; | |
620 | } | |
621 | ||
6847f967 SE |
622 | static int ath10k_download_cal_eeprom(struct ath10k *ar) |
623 | { | |
624 | size_t data_len; | |
625 | void *data = NULL; | |
626 | int ret; | |
627 | ||
628 | ret = ath10k_hif_fetch_cal_eeprom(ar, &data, &data_len); | |
629 | if (ret) { | |
630 | if (ret != -EOPNOTSUPP) | |
631 | ath10k_warn(ar, "failed to read calibration data from EEPROM: %d\n", | |
632 | ret); | |
633 | goto out_free; | |
634 | } | |
635 | ||
636 | ret = ath10k_download_board_data(ar, data, data_len); | |
637 | if (ret) { | |
638 | ath10k_warn(ar, "failed to download calibration data from EEPROM: %d\n", | |
639 | ret); | |
640 | goto out_free; | |
641 | } | |
642 | ||
643 | ret = 0; | |
644 | ||
645 | out_free: | |
646 | kfree(data); | |
647 | ||
648 | return ret; | |
649 | } | |
650 | ||
db0984e5 MP |
651 | static int ath10k_core_get_board_id_from_otp(struct ath10k *ar) |
652 | { | |
653 | u32 result, address; | |
654 | u8 board_id, chip_id; | |
655 | int ret; | |
656 | ||
657 | address = ar->hw_params.patch_load_addr; | |
658 | ||
7ebf721d KV |
659 | if (!ar->normal_mode_fw.fw_file.otp_data || |
660 | !ar->normal_mode_fw.fw_file.otp_len) { | |
db0984e5 MP |
661 | ath10k_warn(ar, |
662 | "failed to retrieve board id because of invalid otp\n"); | |
663 | return -ENODATA; | |
664 | } | |
665 | ||
666 | ath10k_dbg(ar, ATH10K_DBG_BOOT, | |
667 | "boot upload otp to 0x%x len %zd for board id\n", | |
7ebf721d | 668 | address, ar->normal_mode_fw.fw_file.otp_len); |
db0984e5 | 669 | |
7ebf721d KV |
670 | ret = ath10k_bmi_fast_download(ar, address, |
671 | ar->normal_mode_fw.fw_file.otp_data, | |
672 | ar->normal_mode_fw.fw_file.otp_len); | |
db0984e5 MP |
673 | if (ret) { |
674 | ath10k_err(ar, "could not write otp for board id check: %d\n", | |
675 | ret); | |
676 | return ret; | |
677 | } | |
678 | ||
679 | ret = ath10k_bmi_execute(ar, address, BMI_PARAM_GET_EEPROM_BOARD_ID, | |
680 | &result); | |
681 | if (ret) { | |
682 | ath10k_err(ar, "could not execute otp for board id check: %d\n", | |
683 | ret); | |
684 | return ret; | |
685 | } | |
686 | ||
687 | board_id = MS(result, ATH10K_BMI_BOARD_ID_FROM_OTP); | |
688 | chip_id = MS(result, ATH10K_BMI_CHIP_ID_FROM_OTP); | |
689 | ||
690 | ath10k_dbg(ar, ATH10K_DBG_BOOT, | |
691 | "boot get otp board id result 0x%08x board_id %d chip_id %d\n", | |
692 | result, board_id, chip_id); | |
693 | ||
694 | if ((result & ATH10K_BMI_BOARD_ID_STATUS_MASK) != 0) | |
695 | return -EOPNOTSUPP; | |
696 | ||
697 | ar->id.bmi_ids_valid = true; | |
698 | ar->id.bmi_board_id = board_id; | |
699 | ar->id.bmi_chip_id = chip_id; | |
700 | ||
701 | return 0; | |
702 | } | |
703 | ||
5e3dd157 KV |
704 | static int ath10k_download_and_run_otp(struct ath10k *ar) |
705 | { | |
d6d4a58d | 706 | u32 result, address = ar->hw_params.patch_load_addr; |
d772703e | 707 | u32 bmi_otp_exe_param = ar->hw_params.otp_exe_param; |
5e3dd157 KV |
708 | int ret; |
709 | ||
7ebf721d KV |
710 | ret = ath10k_download_board_data(ar, |
711 | ar->running_fw->board_data, | |
712 | ar->running_fw->board_len); | |
83091559 KV |
713 | if (ret) { |
714 | ath10k_err(ar, "failed to download board data: %d\n", ret); | |
715 | return ret; | |
716 | } | |
717 | ||
5e3dd157 KV |
718 | /* OTP is optional */ |
719 | ||
7ebf721d KV |
720 | if (!ar->running_fw->fw_file.otp_data || |
721 | !ar->running_fw->fw_file.otp_len) { | |
75b34800 | 722 | ath10k_warn(ar, "Not running otp, calibration will be incorrect (otp-data %pK otp_len %zd)!\n", |
7ebf721d KV |
723 | ar->running_fw->fw_file.otp_data, |
724 | ar->running_fw->fw_file.otp_len); | |
5e3dd157 | 725 | return 0; |
7f06ea1e KV |
726 | } |
727 | ||
7aa7a72a | 728 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot upload otp to 0x%x len %zd\n", |
7ebf721d | 729 | address, ar->running_fw->fw_file.otp_len); |
5e3dd157 | 730 | |
7ebf721d KV |
731 | ret = ath10k_bmi_fast_download(ar, address, |
732 | ar->running_fw->fw_file.otp_data, | |
733 | ar->running_fw->fw_file.otp_len); | |
5e3dd157 | 734 | if (ret) { |
7aa7a72a | 735 | ath10k_err(ar, "could not write otp (%d)\n", ret); |
7f06ea1e | 736 | return ret; |
5e3dd157 KV |
737 | } |
738 | ||
d772703e | 739 | ret = ath10k_bmi_execute(ar, address, bmi_otp_exe_param, &result); |
5e3dd157 | 740 | if (ret) { |
7aa7a72a | 741 | ath10k_err(ar, "could not execute otp (%d)\n", ret); |
7f06ea1e | 742 | return ret; |
5e3dd157 KV |
743 | } |
744 | ||
7aa7a72a | 745 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot otp execute result %d\n", result); |
7f06ea1e | 746 | |
d9153546 | 747 | if (!(skip_otp || test_bit(ATH10K_FW_FEATURE_IGNORE_OTP_RESULT, |
c4cdf753 | 748 | ar->running_fw->fw_file.fw_features)) && |
be62e92a | 749 | result != 0) { |
7aa7a72a | 750 | ath10k_err(ar, "otp calibration failed: %d", result); |
7f06ea1e KV |
751 | return -EINVAL; |
752 | } | |
753 | ||
754 | return 0; | |
5e3dd157 KV |
755 | } |
756 | ||
7ebf721d | 757 | static int ath10k_download_fw(struct ath10k *ar) |
5e3dd157 | 758 | { |
43d2a30f | 759 | u32 address, data_len; |
43d2a30f | 760 | const void *data; |
5e3dd157 KV |
761 | int ret; |
762 | ||
5e3dd157 KV |
763 | address = ar->hw_params.patch_load_addr; |
764 | ||
7ebf721d KV |
765 | data = ar->running_fw->fw_file.firmware_data; |
766 | data_len = ar->running_fw->fw_file.firmware_len; | |
767 | ||
5459c5d4 | 768 | ret = ath10k_swap_code_seg_configure(ar, &ar->running_fw->fw_file); |
7ebf721d KV |
769 | if (ret) { |
770 | ath10k_err(ar, "failed to configure fw code swap: %d\n", | |
771 | ret); | |
772 | return ret; | |
43d2a30f KV |
773 | } |
774 | ||
775 | ath10k_dbg(ar, ATH10K_DBG_BOOT, | |
75b34800 | 776 | "boot uploading firmware image %pK len %d\n", |
7ebf721d | 777 | data, data_len); |
43d2a30f KV |
778 | |
779 | ret = ath10k_bmi_fast_download(ar, address, data, data_len); | |
5e3dd157 | 780 | if (ret) { |
7ebf721d KV |
781 | ath10k_err(ar, "failed to download firmware: %d\n", |
782 | ret); | |
43d2a30f | 783 | return ret; |
5e3dd157 KV |
784 | } |
785 | ||
29385057 MK |
786 | return ret; |
787 | } | |
788 | ||
0a51b343 | 789 | static void ath10k_core_free_board_files(struct ath10k *ar) |
29385057 | 790 | { |
7ebf721d KV |
791 | if (!IS_ERR(ar->normal_mode_fw.board)) |
792 | release_firmware(ar->normal_mode_fw.board); | |
29385057 | 793 | |
7ebf721d KV |
794 | ar->normal_mode_fw.board = NULL; |
795 | ar->normal_mode_fw.board_data = NULL; | |
796 | ar->normal_mode_fw.board_len = 0; | |
0a51b343 MP |
797 | } |
798 | ||
799 | static void ath10k_core_free_firmware_files(struct ath10k *ar) | |
800 | { | |
7ebf721d KV |
801 | if (!IS_ERR(ar->normal_mode_fw.fw_file.firmware)) |
802 | release_firmware(ar->normal_mode_fw.fw_file.firmware); | |
29385057 | 803 | |
db2cf865 | 804 | if (!IS_ERR(ar->cal_file)) |
a58227ef KV |
805 | release_firmware(ar->cal_file); |
806 | ||
9a5f91a1 RM |
807 | if (!IS_ERR(ar->pre_cal_file)) |
808 | release_firmware(ar->pre_cal_file); | |
809 | ||
5459c5d4 | 810 | ath10k_swap_code_seg_release(ar, &ar->normal_mode_fw.fw_file); |
dcb02db1 | 811 | |
7ebf721d KV |
812 | ar->normal_mode_fw.fw_file.otp_data = NULL; |
813 | ar->normal_mode_fw.fw_file.otp_len = 0; | |
958df3a0 | 814 | |
7ebf721d KV |
815 | ar->normal_mode_fw.fw_file.firmware = NULL; |
816 | ar->normal_mode_fw.fw_file.firmware_data = NULL; | |
817 | ar->normal_mode_fw.fw_file.firmware_len = 0; | |
a58227ef KV |
818 | |
819 | ar->cal_file = NULL; | |
9a5f91a1 | 820 | ar->pre_cal_file = NULL; |
a58227ef KV |
821 | } |
822 | ||
823 | static int ath10k_fetch_cal_file(struct ath10k *ar) | |
824 | { | |
825 | char filename[100]; | |
826 | ||
3d9195ea RM |
827 | /* pre-cal-<bus>-<id>.bin */ |
828 | scnprintf(filename, sizeof(filename), "pre-cal-%s-%s.bin", | |
829 | ath10k_bus_str(ar->hif.bus), dev_name(ar->dev)); | |
830 | ||
831 | ar->pre_cal_file = ath10k_fetch_fw_file(ar, ATH10K_FW_DIR, filename); | |
832 | if (!IS_ERR(ar->pre_cal_file)) | |
833 | goto success; | |
834 | ||
a58227ef KV |
835 | /* cal-<bus>-<id>.bin */ |
836 | scnprintf(filename, sizeof(filename), "cal-%s-%s.bin", | |
837 | ath10k_bus_str(ar->hif.bus), dev_name(ar->dev)); | |
838 | ||
839 | ar->cal_file = ath10k_fetch_fw_file(ar, ATH10K_FW_DIR, filename); | |
840 | if (IS_ERR(ar->cal_file)) | |
841 | /* calibration file is optional, don't print any warnings */ | |
842 | return PTR_ERR(ar->cal_file); | |
3d9195ea | 843 | success: |
a58227ef KV |
844 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "found calibration file %s/%s\n", |
845 | ATH10K_FW_DIR, filename); | |
846 | ||
847 | return 0; | |
29385057 MK |
848 | } |
849 | ||
0a51b343 | 850 | static int ath10k_core_fetch_board_data_api_1(struct ath10k *ar) |
29385057 | 851 | { |
0a51b343 MP |
852 | if (!ar->hw_params.fw.board) { |
853 | ath10k_err(ar, "failed to find board file fw entry\n"); | |
854 | return -EINVAL; | |
855 | } | |
de57e2c8 | 856 | |
7ebf721d KV |
857 | ar->normal_mode_fw.board = ath10k_fetch_fw_file(ar, |
858 | ar->hw_params.fw.dir, | |
859 | ar->hw_params.fw.board); | |
860 | if (IS_ERR(ar->normal_mode_fw.board)) | |
861 | return PTR_ERR(ar->normal_mode_fw.board); | |
de57e2c8 | 862 | |
7ebf721d KV |
863 | ar->normal_mode_fw.board_data = ar->normal_mode_fw.board->data; |
864 | ar->normal_mode_fw.board_len = ar->normal_mode_fw.board->size; | |
29385057 | 865 | |
de57e2c8 MK |
866 | return 0; |
867 | } | |
868 | ||
0a51b343 MP |
869 | static int ath10k_core_parse_bd_ie_board(struct ath10k *ar, |
870 | const void *buf, size_t buf_len, | |
871 | const char *boardname) | |
de57e2c8 | 872 | { |
0a51b343 MP |
873 | const struct ath10k_fw_ie *hdr; |
874 | bool name_match_found; | |
875 | int ret, board_ie_id; | |
876 | size_t board_ie_len; | |
877 | const void *board_ie_data; | |
878 | ||
879 | name_match_found = false; | |
880 | ||
881 | /* go through ATH10K_BD_IE_BOARD_ elements */ | |
882 | while (buf_len > sizeof(struct ath10k_fw_ie)) { | |
883 | hdr = buf; | |
884 | board_ie_id = le32_to_cpu(hdr->id); | |
885 | board_ie_len = le32_to_cpu(hdr->len); | |
886 | board_ie_data = hdr->data; | |
887 | ||
888 | buf_len -= sizeof(*hdr); | |
889 | buf += sizeof(*hdr); | |
890 | ||
891 | if (buf_len < ALIGN(board_ie_len, 4)) { | |
892 | ath10k_err(ar, "invalid ATH10K_BD_IE_BOARD length: %zu < %zu\n", | |
893 | buf_len, ALIGN(board_ie_len, 4)); | |
894 | ret = -EINVAL; | |
895 | goto out; | |
896 | } | |
897 | ||
898 | switch (board_ie_id) { | |
899 | case ATH10K_BD_IE_BOARD_NAME: | |
900 | ath10k_dbg_dump(ar, ATH10K_DBG_BOOT, "board name", "", | |
901 | board_ie_data, board_ie_len); | |
902 | ||
903 | if (board_ie_len != strlen(boardname)) | |
904 | break; | |
905 | ||
906 | ret = memcmp(board_ie_data, boardname, strlen(boardname)); | |
907 | if (ret) | |
908 | break; | |
909 | ||
910 | name_match_found = true; | |
911 | ath10k_dbg(ar, ATH10K_DBG_BOOT, | |
912 | "boot found match for name '%s'", | |
913 | boardname); | |
914 | break; | |
915 | case ATH10K_BD_IE_BOARD_DATA: | |
916 | if (!name_match_found) | |
917 | /* no match found */ | |
918 | break; | |
919 | ||
920 | ath10k_dbg(ar, ATH10K_DBG_BOOT, | |
921 | "boot found board data for '%s'", | |
922 | boardname); | |
923 | ||
7ebf721d KV |
924 | ar->normal_mode_fw.board_data = board_ie_data; |
925 | ar->normal_mode_fw.board_len = board_ie_len; | |
0a51b343 MP |
926 | |
927 | ret = 0; | |
928 | goto out; | |
929 | default: | |
930 | ath10k_warn(ar, "unknown ATH10K_BD_IE_BOARD found: %d\n", | |
931 | board_ie_id); | |
932 | break; | |
933 | } | |
934 | ||
935 | /* jump over the padding */ | |
936 | board_ie_len = ALIGN(board_ie_len, 4); | |
937 | ||
938 | buf_len -= board_ie_len; | |
939 | buf += board_ie_len; | |
29385057 MK |
940 | } |
941 | ||
0a51b343 MP |
942 | /* no match found */ |
943 | ret = -ENOENT; | |
944 | ||
945 | out: | |
946 | return ret; | |
947 | } | |
948 | ||
949 | static int ath10k_core_fetch_board_data_api_n(struct ath10k *ar, | |
950 | const char *boardname, | |
951 | const char *filename) | |
952 | { | |
953 | size_t len, magic_len, ie_len; | |
954 | struct ath10k_fw_ie *hdr; | |
955 | const u8 *data; | |
956 | int ret, ie_id; | |
957 | ||
7ebf721d KV |
958 | ar->normal_mode_fw.board = ath10k_fetch_fw_file(ar, |
959 | ar->hw_params.fw.dir, | |
960 | filename); | |
961 | if (IS_ERR(ar->normal_mode_fw.board)) | |
962 | return PTR_ERR(ar->normal_mode_fw.board); | |
29385057 | 963 | |
7ebf721d KV |
964 | data = ar->normal_mode_fw.board->data; |
965 | len = ar->normal_mode_fw.board->size; | |
0a51b343 MP |
966 | |
967 | /* magic has extra null byte padded */ | |
968 | magic_len = strlen(ATH10K_BOARD_MAGIC) + 1; | |
969 | if (len < magic_len) { | |
970 | ath10k_err(ar, "failed to find magic value in %s/%s, file too short: %zu\n", | |
971 | ar->hw_params.fw.dir, filename, len); | |
972 | ret = -EINVAL; | |
973 | goto err; | |
974 | } | |
975 | ||
976 | if (memcmp(data, ATH10K_BOARD_MAGIC, magic_len)) { | |
977 | ath10k_err(ar, "found invalid board magic\n"); | |
978 | ret = -EINVAL; | |
979 | goto err; | |
980 | } | |
981 | ||
982 | /* magic is padded to 4 bytes */ | |
983 | magic_len = ALIGN(magic_len, 4); | |
984 | if (len < magic_len) { | |
985 | ath10k_err(ar, "failed: %s/%s too small to contain board data, len: %zu\n", | |
986 | ar->hw_params.fw.dir, filename, len); | |
987 | ret = -EINVAL; | |
988 | goto err; | |
989 | } | |
990 | ||
991 | data += magic_len; | |
992 | len -= magic_len; | |
993 | ||
994 | while (len > sizeof(struct ath10k_fw_ie)) { | |
995 | hdr = (struct ath10k_fw_ie *)data; | |
996 | ie_id = le32_to_cpu(hdr->id); | |
997 | ie_len = le32_to_cpu(hdr->len); | |
998 | ||
999 | len -= sizeof(*hdr); | |
1000 | data = hdr->data; | |
1001 | ||
1002 | if (len < ALIGN(ie_len, 4)) { | |
1003 | ath10k_err(ar, "invalid length for board ie_id %d ie_len %zu len %zu\n", | |
1004 | ie_id, ie_len, len); | |
1005 | ret = -EINVAL; | |
1006 | goto err; | |
1007 | } | |
1008 | ||
1009 | switch (ie_id) { | |
1010 | case ATH10K_BD_IE_BOARD: | |
1011 | ret = ath10k_core_parse_bd_ie_board(ar, data, ie_len, | |
1012 | boardname); | |
1013 | if (ret == -ENOENT) | |
1014 | /* no match found, continue */ | |
1015 | break; | |
1016 | else if (ret) | |
1017 | /* there was an error, bail out */ | |
1018 | goto err; | |
1019 | ||
1020 | /* board data found */ | |
1021 | goto out; | |
1022 | } | |
1023 | ||
1024 | /* jump over the padding */ | |
1025 | ie_len = ALIGN(ie_len, 4); | |
1026 | ||
1027 | len -= ie_len; | |
1028 | data += ie_len; | |
1029 | } | |
1030 | ||
1031 | out: | |
7ebf721d | 1032 | if (!ar->normal_mode_fw.board_data || !ar->normal_mode_fw.board_len) { |
0a51b343 MP |
1033 | ath10k_err(ar, |
1034 | "failed to fetch board data for %s from %s/%s\n", | |
bd5632b0 | 1035 | boardname, ar->hw_params.fw.dir, filename); |
0a51b343 MP |
1036 | ret = -ENODATA; |
1037 | goto err; | |
1038 | } | |
1039 | ||
1040 | return 0; | |
1041 | ||
1042 | err: | |
1043 | ath10k_core_free_board_files(ar); | |
1044 | return ret; | |
1045 | } | |
1046 | ||
1047 | static int ath10k_core_create_board_name(struct ath10k *ar, char *name, | |
1048 | size_t name_len) | |
1049 | { | |
db0984e5 MP |
1050 | if (ar->id.bmi_ids_valid) { |
1051 | scnprintf(name, name_len, | |
1052 | "bus=%s,bmi-chip-id=%d,bmi-board-id=%d", | |
1053 | ath10k_bus_str(ar->hif.bus), | |
1054 | ar->id.bmi_chip_id, | |
1055 | ar->id.bmi_board_id); | |
1056 | goto out; | |
1057 | } | |
1058 | ||
0a51b343 MP |
1059 | scnprintf(name, name_len, |
1060 | "bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x", | |
1061 | ath10k_bus_str(ar->hif.bus), | |
1062 | ar->id.vendor, ar->id.device, | |
1063 | ar->id.subsystem_vendor, ar->id.subsystem_device); | |
1064 | ||
db0984e5 | 1065 | out: |
0a51b343 | 1066 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using board name '%s'\n", name); |
de57e2c8 MK |
1067 | |
1068 | return 0; | |
1069 | } | |
1070 | ||
1071 | static int ath10k_core_fetch_board_file(struct ath10k *ar) | |
1072 | { | |
0a51b343 | 1073 | char boardname[100]; |
de57e2c8 MK |
1074 | int ret; |
1075 | ||
0a51b343 MP |
1076 | ret = ath10k_core_create_board_name(ar, boardname, sizeof(boardname)); |
1077 | if (ret) { | |
1078 | ath10k_err(ar, "failed to create board name: %d", ret); | |
1079 | return ret; | |
de57e2c8 MK |
1080 | } |
1081 | ||
0a51b343 MP |
1082 | ar->bd_api = 2; |
1083 | ret = ath10k_core_fetch_board_data_api_n(ar, boardname, | |
1084 | ATH10K_BOARD_API2_FILE); | |
1085 | if (!ret) | |
1086 | goto success; | |
1087 | ||
1088 | ar->bd_api = 1; | |
1089 | ret = ath10k_core_fetch_board_data_api_1(ar); | |
de57e2c8 | 1090 | if (ret) { |
0a51b343 | 1091 | ath10k_err(ar, "failed to fetch board data\n"); |
de57e2c8 MK |
1092 | return ret; |
1093 | } | |
958df3a0 | 1094 | |
0a51b343 MP |
1095 | success: |
1096 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "using board api %d\n", ar->bd_api); | |
d0ed74f3 MK |
1097 | return 0; |
1098 | } | |
1099 | ||
9dfe240b KV |
1100 | int ath10k_core_fetch_firmware_api_n(struct ath10k *ar, const char *name, |
1101 | struct ath10k_fw_file *fw_file) | |
1a222435 KV |
1102 | { |
1103 | size_t magic_len, len, ie_len; | |
1104 | int ie_id, i, index, bit, ret; | |
1105 | struct ath10k_fw_ie *hdr; | |
1106 | const u8 *data; | |
202e86e6 | 1107 | __le32 *timestamp, *version; |
1a222435 KV |
1108 | |
1109 | /* first fetch the firmware file (firmware-*.bin) */ | |
7ebf721d KV |
1110 | fw_file->firmware = ath10k_fetch_fw_file(ar, ar->hw_params.fw.dir, |
1111 | name); | |
1112 | if (IS_ERR(fw_file->firmware)) { | |
7aa7a72a | 1113 | ath10k_err(ar, "could not fetch firmware file '%s/%s': %ld\n", |
7ebf721d KV |
1114 | ar->hw_params.fw.dir, name, |
1115 | PTR_ERR(fw_file->firmware)); | |
1116 | return PTR_ERR(fw_file->firmware); | |
1a222435 KV |
1117 | } |
1118 | ||
7ebf721d KV |
1119 | data = fw_file->firmware->data; |
1120 | len = fw_file->firmware->size; | |
1a222435 KV |
1121 | |
1122 | /* magic also includes the null byte, check that as well */ | |
1123 | magic_len = strlen(ATH10K_FIRMWARE_MAGIC) + 1; | |
1124 | ||
1125 | if (len < magic_len) { | |
7aa7a72a | 1126 | ath10k_err(ar, "firmware file '%s/%s' too small to contain magic: %zu\n", |
53c02284 | 1127 | ar->hw_params.fw.dir, name, len); |
9bab1cc0 MK |
1128 | ret = -EINVAL; |
1129 | goto err; | |
1a222435 KV |
1130 | } |
1131 | ||
1132 | if (memcmp(data, ATH10K_FIRMWARE_MAGIC, magic_len) != 0) { | |
7aa7a72a | 1133 | ath10k_err(ar, "invalid firmware magic\n"); |
9bab1cc0 MK |
1134 | ret = -EINVAL; |
1135 | goto err; | |
1a222435 KV |
1136 | } |
1137 | ||
1138 | /* jump over the padding */ | |
1139 | magic_len = ALIGN(magic_len, 4); | |
1140 | ||
1141 | len -= magic_len; | |
1142 | data += magic_len; | |
1143 | ||
1144 | /* loop elements */ | |
1145 | while (len > sizeof(struct ath10k_fw_ie)) { | |
1146 | hdr = (struct ath10k_fw_ie *)data; | |
1147 | ||
1148 | ie_id = le32_to_cpu(hdr->id); | |
1149 | ie_len = le32_to_cpu(hdr->len); | |
1150 | ||
1151 | len -= sizeof(*hdr); | |
1152 | data += sizeof(*hdr); | |
1153 | ||
1154 | if (len < ie_len) { | |
7aa7a72a | 1155 | ath10k_err(ar, "invalid length for FW IE %d (%zu < %zu)\n", |
1a222435 | 1156 | ie_id, len, ie_len); |
9bab1cc0 MK |
1157 | ret = -EINVAL; |
1158 | goto err; | |
1a222435 KV |
1159 | } |
1160 | ||
1161 | switch (ie_id) { | |
1162 | case ATH10K_FW_IE_FW_VERSION: | |
45317355 | 1163 | if (ie_len > sizeof(fw_file->fw_version) - 1) |
1a222435 KV |
1164 | break; |
1165 | ||
45317355 KV |
1166 | memcpy(fw_file->fw_version, data, ie_len); |
1167 | fw_file->fw_version[ie_len] = '\0'; | |
1a222435 | 1168 | |
7aa7a72a | 1169 | ath10k_dbg(ar, ATH10K_DBG_BOOT, |
1a222435 | 1170 | "found fw version %s\n", |
45317355 | 1171 | fw_file->fw_version); |
1a222435 KV |
1172 | break; |
1173 | case ATH10K_FW_IE_TIMESTAMP: | |
1174 | if (ie_len != sizeof(u32)) | |
1175 | break; | |
1176 | ||
1177 | timestamp = (__le32 *)data; | |
1178 | ||
7aa7a72a | 1179 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw timestamp %d\n", |
1a222435 KV |
1180 | le32_to_cpup(timestamp)); |
1181 | break; | |
1182 | case ATH10K_FW_IE_FEATURES: | |
7aa7a72a | 1183 | ath10k_dbg(ar, ATH10K_DBG_BOOT, |
1a222435 KV |
1184 | "found firmware features ie (%zd B)\n", |
1185 | ie_len); | |
1186 | ||
1187 | for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) { | |
1188 | index = i / 8; | |
1189 | bit = i % 8; | |
1190 | ||
1191 | if (index == ie_len) | |
1192 | break; | |
1193 | ||
f591a1a5 | 1194 | if (data[index] & (1 << bit)) { |
7aa7a72a | 1195 | ath10k_dbg(ar, ATH10K_DBG_BOOT, |
f591a1a5 BG |
1196 | "Enabling feature bit: %i\n", |
1197 | i); | |
c4cdf753 | 1198 | __set_bit(i, fw_file->fw_features); |
f591a1a5 | 1199 | } |
1a222435 KV |
1200 | } |
1201 | ||
7aa7a72a | 1202 | ath10k_dbg_dump(ar, ATH10K_DBG_BOOT, "features", "", |
8d0a0710 | 1203 | fw_file->fw_features, |
c4cdf753 | 1204 | sizeof(fw_file->fw_features)); |
1a222435 KV |
1205 | break; |
1206 | case ATH10K_FW_IE_FW_IMAGE: | |
7aa7a72a | 1207 | ath10k_dbg(ar, ATH10K_DBG_BOOT, |
1a222435 KV |
1208 | "found fw image ie (%zd B)\n", |
1209 | ie_len); | |
1210 | ||
7ebf721d KV |
1211 | fw_file->firmware_data = data; |
1212 | fw_file->firmware_len = ie_len; | |
1a222435 KV |
1213 | |
1214 | break; | |
1215 | case ATH10K_FW_IE_OTP_IMAGE: | |
7aa7a72a | 1216 | ath10k_dbg(ar, ATH10K_DBG_BOOT, |
1a222435 KV |
1217 | "found otp image ie (%zd B)\n", |
1218 | ie_len); | |
1219 | ||
7ebf721d KV |
1220 | fw_file->otp_data = data; |
1221 | fw_file->otp_len = ie_len; | |
1a222435 KV |
1222 | |
1223 | break; | |
202e86e6 KV |
1224 | case ATH10K_FW_IE_WMI_OP_VERSION: |
1225 | if (ie_len != sizeof(u32)) | |
1226 | break; | |
1227 | ||
1228 | version = (__le32 *)data; | |
1229 | ||
bf3c13ab | 1230 | fw_file->wmi_op_version = le32_to_cpup(version); |
202e86e6 KV |
1231 | |
1232 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie wmi op version %d\n", | |
bf3c13ab | 1233 | fw_file->wmi_op_version); |
202e86e6 | 1234 | break; |
8348db29 RM |
1235 | case ATH10K_FW_IE_HTT_OP_VERSION: |
1236 | if (ie_len != sizeof(u32)) | |
1237 | break; | |
1238 | ||
1239 | version = (__le32 *)data; | |
1240 | ||
77561f93 | 1241 | fw_file->htt_op_version = le32_to_cpup(version); |
8348db29 RM |
1242 | |
1243 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie htt op version %d\n", | |
77561f93 | 1244 | fw_file->htt_op_version); |
8348db29 | 1245 | break; |
dcb02db1 VT |
1246 | case ATH10K_FW_IE_FW_CODE_SWAP_IMAGE: |
1247 | ath10k_dbg(ar, ATH10K_DBG_BOOT, | |
1248 | "found fw code swap image ie (%zd B)\n", | |
1249 | ie_len); | |
7ebf721d KV |
1250 | fw_file->codeswap_data = data; |
1251 | fw_file->codeswap_len = ie_len; | |
dcb02db1 | 1252 | break; |
1a222435 | 1253 | default: |
7aa7a72a | 1254 | ath10k_warn(ar, "Unknown FW IE: %u\n", |
1a222435 KV |
1255 | le32_to_cpu(hdr->id)); |
1256 | break; | |
1257 | } | |
1258 | ||
1259 | /* jump over the padding */ | |
1260 | ie_len = ALIGN(ie_len, 4); | |
1261 | ||
1262 | len -= ie_len; | |
1263 | data += ie_len; | |
e05634ee | 1264 | } |
1a222435 | 1265 | |
7ebf721d KV |
1266 | if (!fw_file->firmware_data || |
1267 | !fw_file->firmware_len) { | |
7aa7a72a | 1268 | ath10k_warn(ar, "No ATH10K_FW_IE_FW_IMAGE found from '%s/%s', skipping\n", |
53c02284 | 1269 | ar->hw_params.fw.dir, name); |
1a222435 KV |
1270 | ret = -ENOMEDIUM; |
1271 | goto err; | |
1272 | } | |
1273 | ||
1a222435 KV |
1274 | return 0; |
1275 | ||
1276 | err: | |
1277 | ath10k_core_free_firmware_files(ar); | |
1278 | return ret; | |
1279 | } | |
1280 | ||
1281 | static int ath10k_core_fetch_firmware_files(struct ath10k *ar) | |
1282 | { | |
1283 | int ret; | |
1284 | ||
a58227ef KV |
1285 | /* calibration file is optional, don't check for any errors */ |
1286 | ath10k_fetch_cal_file(ar); | |
1287 | ||
53513c30 KV |
1288 | ar->fw_api = 5; |
1289 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api); | |
1290 | ||
7ebf721d KV |
1291 | ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API5_FILE, |
1292 | &ar->normal_mode_fw.fw_file); | |
53513c30 KV |
1293 | if (ret == 0) |
1294 | goto success; | |
1295 | ||
4a16fbec RM |
1296 | ar->fw_api = 4; |
1297 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api); | |
1298 | ||
7ebf721d KV |
1299 | ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API4_FILE, |
1300 | &ar->normal_mode_fw.fw_file); | |
4a16fbec RM |
1301 | if (ret == 0) |
1302 | goto success; | |
1303 | ||
24c88f78 | 1304 | ar->fw_api = 3; |
7aa7a72a | 1305 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api); |
24c88f78 | 1306 | |
7ebf721d KV |
1307 | ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API3_FILE, |
1308 | &ar->normal_mode_fw.fw_file); | |
24c88f78 MK |
1309 | if (ret == 0) |
1310 | goto success; | |
1311 | ||
53c02284 | 1312 | ar->fw_api = 2; |
7aa7a72a | 1313 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api); |
53c02284 | 1314 | |
7ebf721d KV |
1315 | ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API2_FILE, |
1316 | &ar->normal_mode_fw.fw_file); | |
1a222435 KV |
1317 | if (ret) |
1318 | return ret; | |
1319 | ||
53c02284 | 1320 | success: |
7aa7a72a | 1321 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "using fw api %d\n", ar->fw_api); |
1a222435 KV |
1322 | |
1323 | return 0; | |
1324 | } | |
1325 | ||
3d9195ea RM |
1326 | static int ath10k_core_pre_cal_download(struct ath10k *ar) |
1327 | { | |
1328 | int ret; | |
1329 | ||
1330 | ret = ath10k_download_cal_file(ar, ar->pre_cal_file); | |
1331 | if (ret == 0) { | |
1332 | ar->cal_mode = ATH10K_PRE_CAL_MODE_FILE; | |
1333 | goto success; | |
1334 | } | |
1335 | ||
1336 | ath10k_dbg(ar, ATH10K_DBG_BOOT, | |
1337 | "boot did not find a pre calibration file, try DT next: %d\n", | |
1338 | ret); | |
1339 | ||
1340 | ret = ath10k_download_cal_dt(ar, "qcom,ath10k-pre-calibration-data"); | |
1341 | if (ret) { | |
1342 | ath10k_dbg(ar, ATH10K_DBG_BOOT, | |
1343 | "unable to load pre cal data from DT: %d\n", ret); | |
1344 | return ret; | |
1345 | } | |
1346 | ar->cal_mode = ATH10K_PRE_CAL_MODE_DT; | |
1347 | ||
1348 | success: | |
1349 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using calibration mode %s\n", | |
1350 | ath10k_cal_mode_str(ar->cal_mode)); | |
1351 | ||
1352 | return 0; | |
1353 | } | |
1354 | ||
1355 | static int ath10k_core_pre_cal_config(struct ath10k *ar) | |
1356 | { | |
1357 | int ret; | |
1358 | ||
1359 | ret = ath10k_core_pre_cal_download(ar); | |
1360 | if (ret) { | |
1361 | ath10k_dbg(ar, ATH10K_DBG_BOOT, | |
1362 | "failed to load pre cal data: %d\n", ret); | |
1363 | return ret; | |
1364 | } | |
1365 | ||
1366 | ret = ath10k_core_get_board_id_from_otp(ar); | |
1367 | if (ret) { | |
1368 | ath10k_err(ar, "failed to get board id: %d\n", ret); | |
1369 | return ret; | |
1370 | } | |
1371 | ||
1372 | ret = ath10k_download_and_run_otp(ar); | |
1373 | if (ret) { | |
1374 | ath10k_err(ar, "failed to run otp: %d\n", ret); | |
1375 | return ret; | |
1376 | } | |
1377 | ||
1378 | ath10k_dbg(ar, ATH10K_DBG_BOOT, | |
1379 | "pre cal configuration done successfully\n"); | |
1380 | ||
1381 | return 0; | |
1382 | } | |
1383 | ||
83091559 | 1384 | static int ath10k_download_cal_data(struct ath10k *ar) |
5e3dd157 KV |
1385 | { |
1386 | int ret; | |
1387 | ||
3d9195ea RM |
1388 | ret = ath10k_core_pre_cal_config(ar); |
1389 | if (ret == 0) | |
1390 | return 0; | |
1391 | ||
1392 | ath10k_dbg(ar, ATH10K_DBG_BOOT, | |
1393 | "pre cal download procedure failed, try cal file: %d\n", | |
1394 | ret); | |
1395 | ||
f454add4 | 1396 | ret = ath10k_download_cal_file(ar, ar->cal_file); |
a58227ef KV |
1397 | if (ret == 0) { |
1398 | ar->cal_mode = ATH10K_CAL_MODE_FILE; | |
1399 | goto done; | |
1400 | } | |
1401 | ||
1402 | ath10k_dbg(ar, ATH10K_DBG_BOOT, | |
5aabff05 TK |
1403 | "boot did not find a calibration file, try DT next: %d\n", |
1404 | ret); | |
1405 | ||
f454add4 | 1406 | ret = ath10k_download_cal_dt(ar, "qcom,ath10k-calibration-data"); |
5aabff05 TK |
1407 | if (ret == 0) { |
1408 | ar->cal_mode = ATH10K_CAL_MODE_DT; | |
1409 | goto done; | |
1410 | } | |
1411 | ||
1412 | ath10k_dbg(ar, ATH10K_DBG_BOOT, | |
6847f967 SE |
1413 | "boot did not find DT entry, try target EEPROM next: %d\n", |
1414 | ret); | |
1415 | ||
1416 | ret = ath10k_download_cal_eeprom(ar); | |
1417 | if (ret == 0) { | |
1418 | ar->cal_mode = ATH10K_CAL_MODE_EEPROM; | |
1419 | goto done; | |
1420 | } | |
1421 | ||
1422 | ath10k_dbg(ar, ATH10K_DBG_BOOT, | |
1423 | "boot did not find target EEPROM entry, try OTP next: %d\n", | |
a58227ef KV |
1424 | ret); |
1425 | ||
5e3dd157 | 1426 | ret = ath10k_download_and_run_otp(ar); |
36a8f413 | 1427 | if (ret) { |
7aa7a72a | 1428 | ath10k_err(ar, "failed to run otp: %d\n", ret); |
5e3dd157 | 1429 | return ret; |
36a8f413 | 1430 | } |
5e3dd157 | 1431 | |
a58227ef KV |
1432 | ar->cal_mode = ATH10K_CAL_MODE_OTP; |
1433 | ||
1434 | done: | |
1435 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using calibration mode %s\n", | |
1436 | ath10k_cal_mode_str(ar->cal_mode)); | |
1437 | return 0; | |
5e3dd157 KV |
1438 | } |
1439 | ||
1440 | static int ath10k_init_uart(struct ath10k *ar) | |
1441 | { | |
1442 | int ret; | |
1443 | ||
1444 | /* | |
1445 | * Explicitly setting UART prints to zero as target turns it on | |
1446 | * based on scratch registers. | |
1447 | */ | |
1448 | ret = ath10k_bmi_write32(ar, hi_serial_enable, 0); | |
1449 | if (ret) { | |
7aa7a72a | 1450 | ath10k_warn(ar, "could not disable UART prints (%d)\n", ret); |
5e3dd157 KV |
1451 | return ret; |
1452 | } | |
1453 | ||
c8c39afe | 1454 | if (!uart_print) |
5e3dd157 | 1455 | return 0; |
5e3dd157 | 1456 | |
3a8200b2 | 1457 | ret = ath10k_bmi_write32(ar, hi_dbg_uart_txpin, ar->hw_params.uart_pin); |
5e3dd157 | 1458 | if (ret) { |
7aa7a72a | 1459 | ath10k_warn(ar, "could not enable UART prints (%d)\n", ret); |
5e3dd157 KV |
1460 | return ret; |
1461 | } | |
1462 | ||
1463 | ret = ath10k_bmi_write32(ar, hi_serial_enable, 1); | |
1464 | if (ret) { | |
7aa7a72a | 1465 | ath10k_warn(ar, "could not enable UART prints (%d)\n", ret); |
5e3dd157 KV |
1466 | return ret; |
1467 | } | |
1468 | ||
03fc137b BM |
1469 | /* Set the UART baud rate to 19200. */ |
1470 | ret = ath10k_bmi_write32(ar, hi_desired_baud_rate, 19200); | |
1471 | if (ret) { | |
7aa7a72a | 1472 | ath10k_warn(ar, "could not set the baud rate (%d)\n", ret); |
03fc137b BM |
1473 | return ret; |
1474 | } | |
1475 | ||
7aa7a72a | 1476 | ath10k_info(ar, "UART prints enabled\n"); |
5e3dd157 KV |
1477 | return 0; |
1478 | } | |
1479 | ||
1480 | static int ath10k_init_hw_params(struct ath10k *ar) | |
1481 | { | |
1482 | const struct ath10k_hw_params *uninitialized_var(hw_params); | |
1483 | int i; | |
1484 | ||
1485 | for (i = 0; i < ARRAY_SIZE(ath10k_hw_params_list); i++) { | |
1486 | hw_params = &ath10k_hw_params_list[i]; | |
1487 | ||
079a0490 BM |
1488 | if (hw_params->id == ar->target_version && |
1489 | hw_params->dev_id == ar->dev_id) | |
5e3dd157 KV |
1490 | break; |
1491 | } | |
1492 | ||
1493 | if (i == ARRAY_SIZE(ath10k_hw_params_list)) { | |
7aa7a72a | 1494 | ath10k_err(ar, "Unsupported hardware version: 0x%x\n", |
5e3dd157 KV |
1495 | ar->target_version); |
1496 | return -EINVAL; | |
1497 | } | |
1498 | ||
1499 | ar->hw_params = *hw_params; | |
1500 | ||
7aa7a72a | 1501 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "Hardware name %s version 0x%x\n", |
c8c39afe | 1502 | ar->hw_params.name, ar->target_version); |
5e3dd157 KV |
1503 | |
1504 | return 0; | |
1505 | } | |
1506 | ||
affd3217 MK |
1507 | static void ath10k_core_restart(struct work_struct *work) |
1508 | { | |
1509 | struct ath10k *ar = container_of(work, struct ath10k, restart_work); | |
1510 | ||
7962b0d8 MK |
1511 | set_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags); |
1512 | ||
1513 | /* Place a barrier to make sure the compiler doesn't reorder | |
1514 | * CRASH_FLUSH and calling other functions. | |
1515 | */ | |
1516 | barrier(); | |
1517 | ||
1518 | ieee80211_stop_queues(ar->hw); | |
1519 | ath10k_drain_tx(ar); | |
881ed54e DW |
1520 | complete(&ar->scan.started); |
1521 | complete(&ar->scan.completed); | |
1522 | complete(&ar->scan.on_channel); | |
1523 | complete(&ar->offchan_tx_completed); | |
1524 | complete(&ar->install_key_done); | |
1525 | complete(&ar->vdev_setup_done); | |
1526 | complete(&ar->thermal.wmi_sync); | |
1527 | complete(&ar->bss_survey_done); | |
7962b0d8 MK |
1528 | wake_up(&ar->htt.empty_tx_wq); |
1529 | wake_up(&ar->wmi.tx_credits_wq); | |
1530 | wake_up(&ar->peer_mapping_wq); | |
1531 | ||
affd3217 MK |
1532 | mutex_lock(&ar->conf_mutex); |
1533 | ||
1534 | switch (ar->state) { | |
1535 | case ATH10K_STATE_ON: | |
affd3217 | 1536 | ar->state = ATH10K_STATE_RESTARTING; |
61e9aab7 | 1537 | ath10k_hif_stop(ar); |
5c81c7fd | 1538 | ath10k_scan_finish(ar); |
affd3217 MK |
1539 | ieee80211_restart_hw(ar->hw); |
1540 | break; | |
1541 | case ATH10K_STATE_OFF: | |
5e90de86 MK |
1542 | /* this can happen if driver is being unloaded |
1543 | * or if the crash happens during FW probing */ | |
7aa7a72a | 1544 | ath10k_warn(ar, "cannot restart a device that hasn't been started\n"); |
affd3217 MK |
1545 | break; |
1546 | case ATH10K_STATE_RESTARTING: | |
c5058f5b MK |
1547 | /* hw restart might be requested from multiple places */ |
1548 | break; | |
affd3217 MK |
1549 | case ATH10K_STATE_RESTARTED: |
1550 | ar->state = ATH10K_STATE_WEDGED; | |
1551 | /* fall through */ | |
1552 | case ATH10K_STATE_WEDGED: | |
7aa7a72a | 1553 | ath10k_warn(ar, "device is wedged, will not restart\n"); |
affd3217 | 1554 | break; |
43d2a30f KV |
1555 | case ATH10K_STATE_UTF: |
1556 | ath10k_warn(ar, "firmware restart in UTF mode not supported\n"); | |
1557 | break; | |
affd3217 MK |
1558 | } |
1559 | ||
1560 | mutex_unlock(&ar->conf_mutex); | |
1561 | } | |
1562 | ||
5f2144d9 | 1563 | static int ath10k_core_init_firmware_features(struct ath10k *ar) |
cfd1061e | 1564 | { |
c4cdf753 KV |
1565 | struct ath10k_fw_file *fw_file = &ar->normal_mode_fw.fw_file; |
1566 | ||
1567 | if (test_bit(ATH10K_FW_FEATURE_WMI_10_2, fw_file->fw_features) && | |
1568 | !test_bit(ATH10K_FW_FEATURE_WMI_10X, fw_file->fw_features)) { | |
5f2144d9 KV |
1569 | ath10k_err(ar, "feature bits corrupted: 10.2 feature requires 10.x feature to be set as well"); |
1570 | return -EINVAL; | |
1571 | } | |
1572 | ||
bf3c13ab | 1573 | if (fw_file->wmi_op_version >= ATH10K_FW_WMI_OP_VERSION_MAX) { |
202e86e6 | 1574 | ath10k_err(ar, "unsupported WMI OP version (max %d): %d\n", |
bf3c13ab | 1575 | ATH10K_FW_WMI_OP_VERSION_MAX, fw_file->wmi_op_version); |
202e86e6 KV |
1576 | return -EINVAL; |
1577 | } | |
1578 | ||
ccec9038 DL |
1579 | ar->wmi.rx_decap_mode = ATH10K_HW_TXRX_NATIVE_WIFI; |
1580 | switch (ath10k_cryptmode_param) { | |
1581 | case ATH10K_CRYPT_MODE_HW: | |
1582 | clear_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags); | |
1583 | clear_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags); | |
1584 | break; | |
1585 | case ATH10K_CRYPT_MODE_SW: | |
1586 | if (!test_bit(ATH10K_FW_FEATURE_RAW_MODE_SUPPORT, | |
c4cdf753 | 1587 | fw_file->fw_features)) { |
ccec9038 DL |
1588 | ath10k_err(ar, "cryptmode > 0 requires raw mode support from firmware"); |
1589 | return -EINVAL; | |
1590 | } | |
1591 | ||
1592 | set_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags); | |
1593 | set_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags); | |
1594 | break; | |
1595 | default: | |
1596 | ath10k_info(ar, "invalid cryptmode: %d\n", | |
1597 | ath10k_cryptmode_param); | |
1598 | return -EINVAL; | |
1599 | } | |
1600 | ||
1601 | ar->htt.max_num_amsdu = ATH10K_HTT_MAX_NUM_AMSDU_DEFAULT; | |
1602 | ar->htt.max_num_ampdu = ATH10K_HTT_MAX_NUM_AMPDU_DEFAULT; | |
1603 | ||
b6c7bafa BC |
1604 | if (rawmode) { |
1605 | if (!test_bit(ATH10K_FW_FEATURE_RAW_MODE_SUPPORT, | |
c4cdf753 | 1606 | fw_file->fw_features)) { |
b6c7bafa BC |
1607 | ath10k_err(ar, "rawmode = 1 requires support from firmware"); |
1608 | return -EINVAL; | |
1609 | } | |
1610 | set_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags); | |
1611 | } | |
1612 | ||
ccec9038 DL |
1613 | if (test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) { |
1614 | ar->wmi.rx_decap_mode = ATH10K_HW_TXRX_RAW; | |
1615 | ||
1616 | /* Workaround: | |
1617 | * | |
1618 | * Firmware A-MSDU aggregation breaks with RAW Tx encap mode | |
1619 | * and causes enormous performance issues (malformed frames, | |
1620 | * etc). | |
1621 | * | |
1622 | * Disabling A-MSDU makes RAW mode stable with heavy traffic | |
1623 | * albeit a bit slower compared to regular operation. | |
1624 | */ | |
1625 | ar->htt.max_num_amsdu = 1; | |
1626 | } | |
1627 | ||
202e86e6 KV |
1628 | /* Backwards compatibility for firmwares without |
1629 | * ATH10K_FW_IE_WMI_OP_VERSION. | |
1630 | */ | |
bf3c13ab | 1631 | if (fw_file->wmi_op_version == ATH10K_FW_WMI_OP_VERSION_UNSET) { |
c4cdf753 | 1632 | if (test_bit(ATH10K_FW_FEATURE_WMI_10X, fw_file->fw_features)) { |
4a16fbec | 1633 | if (test_bit(ATH10K_FW_FEATURE_WMI_10_2, |
c4cdf753 | 1634 | fw_file->fw_features)) |
bf3c13ab | 1635 | fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_10_2; |
202e86e6 | 1636 | else |
bf3c13ab | 1637 | fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_10_1; |
202e86e6 | 1638 | } else { |
bf3c13ab | 1639 | fw_file->wmi_op_version = ATH10K_FW_WMI_OP_VERSION_MAIN; |
202e86e6 KV |
1640 | } |
1641 | } | |
1642 | ||
bf3c13ab | 1643 | switch (fw_file->wmi_op_version) { |
202e86e6 | 1644 | case ATH10K_FW_WMI_OP_VERSION_MAIN: |
cfd1061e MK |
1645 | ar->max_num_peers = TARGET_NUM_PEERS; |
1646 | ar->max_num_stations = TARGET_NUM_STATIONS; | |
30c78167 | 1647 | ar->max_num_vdevs = TARGET_NUM_VDEVS; |
91ad5f56 | 1648 | ar->htt.max_num_pending_tx = TARGET_NUM_MSDU_DESC; |
6274cd41 YL |
1649 | ar->fw_stats_req_mask = WMI_STAT_PDEV | WMI_STAT_VDEV | |
1650 | WMI_STAT_PEER; | |
5c8726ec | 1651 | ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM; |
202e86e6 KV |
1652 | break; |
1653 | case ATH10K_FW_WMI_OP_VERSION_10_1: | |
1654 | case ATH10K_FW_WMI_OP_VERSION_10_2: | |
4a16fbec | 1655 | case ATH10K_FW_WMI_OP_VERSION_10_2_4: |
cc61a1bb | 1656 | if (ath10k_peer_stats_enabled(ar)) { |
af9a6a3a AK |
1657 | ar->max_num_peers = TARGET_10X_TX_STATS_NUM_PEERS; |
1658 | ar->max_num_stations = TARGET_10X_TX_STATS_NUM_STATIONS; | |
1659 | } else { | |
1660 | ar->max_num_peers = TARGET_10X_NUM_PEERS; | |
1661 | ar->max_num_stations = TARGET_10X_NUM_STATIONS; | |
1662 | } | |
30c78167 | 1663 | ar->max_num_vdevs = TARGET_10X_NUM_VDEVS; |
91ad5f56 | 1664 | ar->htt.max_num_pending_tx = TARGET_10X_NUM_MSDU_DESC; |
6274cd41 | 1665 | ar->fw_stats_req_mask = WMI_STAT_PEER; |
5c8726ec | 1666 | ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM; |
202e86e6 | 1667 | break; |
ca996ec5 MK |
1668 | case ATH10K_FW_WMI_OP_VERSION_TLV: |
1669 | ar->max_num_peers = TARGET_TLV_NUM_PEERS; | |
1670 | ar->max_num_stations = TARGET_TLV_NUM_STATIONS; | |
49274332 | 1671 | ar->max_num_vdevs = TARGET_TLV_NUM_VDEVS; |
8cca3d60 | 1672 | ar->max_num_tdls_vdevs = TARGET_TLV_NUM_TDLS_VDEVS; |
ca996ec5 | 1673 | ar->htt.max_num_pending_tx = TARGET_TLV_NUM_MSDU_DESC; |
25c86619 | 1674 | ar->wow.max_num_patterns = TARGET_TLV_NUM_WOW_PATTERNS; |
6274cd41 YL |
1675 | ar->fw_stats_req_mask = WMI_STAT_PDEV | WMI_STAT_VDEV | |
1676 | WMI_STAT_PEER; | |
5c8726ec | 1677 | ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM; |
ca996ec5 | 1678 | break; |
9bd21322 | 1679 | case ATH10K_FW_WMI_OP_VERSION_10_4: |
d1e52a8e RM |
1680 | ar->max_num_peers = TARGET_10_4_NUM_PEERS; |
1681 | ar->max_num_stations = TARGET_10_4_NUM_STATIONS; | |
1682 | ar->num_active_peers = TARGET_10_4_ACTIVE_PEERS; | |
1683 | ar->max_num_vdevs = TARGET_10_4_NUM_VDEVS; | |
1684 | ar->num_tids = TARGET_10_4_TGT_NUM_TIDS; | |
f9575793 MSS |
1685 | ar->fw_stats_req_mask = WMI_10_4_STAT_PEER | |
1686 | WMI_10_4_STAT_PEER_EXTD; | |
5699a6f2 | 1687 | ar->max_spatial_stream = ar->hw_params.max_spatial_stream; |
99ad1cba MK |
1688 | |
1689 | if (test_bit(ATH10K_FW_FEATURE_PEER_FLOW_CONTROL, | |
c4cdf753 | 1690 | fw_file->fw_features)) |
99ad1cba MK |
1691 | ar->htt.max_num_pending_tx = TARGET_10_4_NUM_MSDU_DESC_PFC; |
1692 | else | |
1693 | ar->htt.max_num_pending_tx = TARGET_10_4_NUM_MSDU_DESC; | |
d1e52a8e | 1694 | break; |
202e86e6 KV |
1695 | case ATH10K_FW_WMI_OP_VERSION_UNSET: |
1696 | case ATH10K_FW_WMI_OP_VERSION_MAX: | |
1697 | WARN_ON(1); | |
1698 | return -EINVAL; | |
cfd1061e | 1699 | } |
5f2144d9 | 1700 | |
dc3632a1 KV |
1701 | /* Backwards compatibility for firmwares without |
1702 | * ATH10K_FW_IE_HTT_OP_VERSION. | |
1703 | */ | |
77561f93 | 1704 | if (fw_file->htt_op_version == ATH10K_FW_HTT_OP_VERSION_UNSET) { |
bf3c13ab | 1705 | switch (fw_file->wmi_op_version) { |
dc3632a1 | 1706 | case ATH10K_FW_WMI_OP_VERSION_MAIN: |
77561f93 | 1707 | fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_MAIN; |
dc3632a1 KV |
1708 | break; |
1709 | case ATH10K_FW_WMI_OP_VERSION_10_1: | |
1710 | case ATH10K_FW_WMI_OP_VERSION_10_2: | |
1711 | case ATH10K_FW_WMI_OP_VERSION_10_2_4: | |
77561f93 | 1712 | fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_10_1; |
dc3632a1 KV |
1713 | break; |
1714 | case ATH10K_FW_WMI_OP_VERSION_TLV: | |
77561f93 | 1715 | fw_file->htt_op_version = ATH10K_FW_HTT_OP_VERSION_TLV; |
dc3632a1 | 1716 | break; |
9bd21322 | 1717 | case ATH10K_FW_WMI_OP_VERSION_10_4: |
dc3632a1 KV |
1718 | case ATH10K_FW_WMI_OP_VERSION_UNSET: |
1719 | case ATH10K_FW_WMI_OP_VERSION_MAX: | |
ce30c4fe | 1720 | ath10k_err(ar, "htt op version not found from fw meta data"); |
dc3632a1 KV |
1721 | return -EINVAL; |
1722 | } | |
1723 | } | |
1724 | ||
5f2144d9 | 1725 | return 0; |
cfd1061e MK |
1726 | } |
1727 | ||
47b1848d MK |
1728 | static int ath10k_core_reset_rx_filter(struct ath10k *ar) |
1729 | { | |
1730 | int ret; | |
1731 | int vdev_id; | |
1732 | int vdev_type; | |
1733 | int vdev_subtype; | |
1734 | const u8 *vdev_addr; | |
1735 | ||
1736 | vdev_id = 0; | |
1737 | vdev_type = WMI_VDEV_TYPE_STA; | |
1738 | vdev_subtype = ath10k_wmi_get_vdev_subtype(ar, WMI_VDEV_SUBTYPE_NONE); | |
1739 | vdev_addr = ar->mac_addr; | |
1740 | ||
1741 | ret = ath10k_wmi_vdev_create(ar, vdev_id, vdev_type, vdev_subtype, | |
1742 | vdev_addr); | |
1743 | if (ret) { | |
1744 | ath10k_err(ar, "failed to create dummy vdev: %d\n", ret); | |
1745 | return ret; | |
1746 | } | |
1747 | ||
1748 | ret = ath10k_wmi_vdev_delete(ar, vdev_id); | |
1749 | if (ret) { | |
1750 | ath10k_err(ar, "failed to delete dummy vdev: %d\n", ret); | |
1751 | return ret; | |
1752 | } | |
1753 | ||
1754 | /* WMI and HTT may use separate HIF pipes and are not guaranteed to be | |
1755 | * serialized properly implicitly. | |
1756 | * | |
1757 | * Moreover (most) WMI commands have no explicit acknowledges. It is | |
1758 | * possible to infer it implicitly by poking firmware with echo | |
1759 | * command - getting a reply means all preceding comments have been | |
1760 | * (mostly) processed. | |
1761 | * | |
1762 | * In case of vdev create/delete this is sufficient. | |
1763 | * | |
1764 | * Without this it's possible to end up with a race when HTT Rx ring is | |
1765 | * started before vdev create/delete hack is complete allowing a short | |
1766 | * window of opportunity to receive (and Tx ACK) a bunch of frames. | |
1767 | */ | |
1768 | ret = ath10k_wmi_barrier(ar); | |
1769 | if (ret) { | |
1770 | ath10k_err(ar, "failed to ping firmware: %d\n", ret); | |
1771 | return ret; | |
1772 | } | |
1773 | ||
1774 | return 0; | |
1775 | } | |
1776 | ||
7ebf721d KV |
1777 | int ath10k_core_start(struct ath10k *ar, enum ath10k_firmware_mode mode, |
1778 | const struct ath10k_fw_components *fw) | |
5e3dd157 | 1779 | { |
5e3dd157 | 1780 | int status; |
f9575793 | 1781 | u32 val; |
5e3dd157 | 1782 | |
60631c5c KV |
1783 | lockdep_assert_held(&ar->conf_mutex); |
1784 | ||
7962b0d8 MK |
1785 | clear_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags); |
1786 | ||
7ebf721d KV |
1787 | ar->running_fw = fw; |
1788 | ||
64d151d4 MK |
1789 | ath10k_bmi_start(ar); |
1790 | ||
5e3dd157 KV |
1791 | if (ath10k_init_configure_target(ar)) { |
1792 | status = -EINVAL; | |
1793 | goto err; | |
1794 | } | |
1795 | ||
83091559 KV |
1796 | status = ath10k_download_cal_data(ar); |
1797 | if (status) | |
1798 | goto err; | |
1799 | ||
163f5264 | 1800 | /* Some of of qca988x solutions are having global reset issue |
617b0f4d KV |
1801 | * during target initialization. Bypassing PLL setting before |
1802 | * downloading firmware and letting the SoC run on REF_CLK is | |
1803 | * fixing the problem. Corresponding firmware change is also needed | |
1804 | * to set the clock source once the target is initialized. | |
163f5264 RM |
1805 | */ |
1806 | if (test_bit(ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT, | |
c4cdf753 | 1807 | ar->running_fw->fw_file.fw_features)) { |
163f5264 RM |
1808 | status = ath10k_bmi_write32(ar, hi_skip_clock_init, 1); |
1809 | if (status) { | |
1810 | ath10k_err(ar, "could not write to skip_clock_init: %d\n", | |
1811 | status); | |
1812 | goto err; | |
1813 | } | |
1814 | } | |
1815 | ||
7ebf721d | 1816 | status = ath10k_download_fw(ar); |
5e3dd157 KV |
1817 | if (status) |
1818 | goto err; | |
1819 | ||
1820 | status = ath10k_init_uart(ar); | |
1821 | if (status) | |
1822 | goto err; | |
1823 | ||
cd003fad MK |
1824 | ar->htc.htc_ops.target_send_suspend_complete = |
1825 | ath10k_send_suspend_complete; | |
5e3dd157 | 1826 | |
cd003fad MK |
1827 | status = ath10k_htc_init(ar); |
1828 | if (status) { | |
7aa7a72a | 1829 | ath10k_err(ar, "could not init HTC (%d)\n", status); |
5e3dd157 KV |
1830 | goto err; |
1831 | } | |
1832 | ||
1833 | status = ath10k_bmi_done(ar); | |
1834 | if (status) | |
cd003fad | 1835 | goto err; |
5e3dd157 KV |
1836 | |
1837 | status = ath10k_wmi_attach(ar); | |
1838 | if (status) { | |
7aa7a72a | 1839 | ath10k_err(ar, "WMI attach failed: %d\n", status); |
cd003fad | 1840 | goto err; |
5e3dd157 KV |
1841 | } |
1842 | ||
95bf21f9 MK |
1843 | status = ath10k_htt_init(ar); |
1844 | if (status) { | |
7aa7a72a | 1845 | ath10k_err(ar, "failed to init htt: %d\n", status); |
95bf21f9 MK |
1846 | goto err_wmi_detach; |
1847 | } | |
1848 | ||
1849 | status = ath10k_htt_tx_alloc(&ar->htt); | |
1850 | if (status) { | |
7aa7a72a | 1851 | ath10k_err(ar, "failed to alloc htt tx: %d\n", status); |
95bf21f9 MK |
1852 | goto err_wmi_detach; |
1853 | } | |
1854 | ||
1855 | status = ath10k_htt_rx_alloc(&ar->htt); | |
1856 | if (status) { | |
7aa7a72a | 1857 | ath10k_err(ar, "failed to alloc htt rx: %d\n", status); |
95bf21f9 MK |
1858 | goto err_htt_tx_detach; |
1859 | } | |
1860 | ||
67e3c63f MK |
1861 | status = ath10k_hif_start(ar); |
1862 | if (status) { | |
7aa7a72a | 1863 | ath10k_err(ar, "could not start HIF: %d\n", status); |
95bf21f9 | 1864 | goto err_htt_rx_detach; |
67e3c63f MK |
1865 | } |
1866 | ||
1867 | status = ath10k_htc_wait_target(&ar->htc); | |
1868 | if (status) { | |
7aa7a72a | 1869 | ath10k_err(ar, "failed to connect to HTC: %d\n", status); |
67e3c63f MK |
1870 | goto err_hif_stop; |
1871 | } | |
5e3dd157 | 1872 | |
43d2a30f KV |
1873 | if (mode == ATH10K_FIRMWARE_MODE_NORMAL) { |
1874 | status = ath10k_htt_connect(&ar->htt); | |
1875 | if (status) { | |
1876 | ath10k_err(ar, "failed to connect htt (%d)\n", status); | |
1877 | goto err_hif_stop; | |
1878 | } | |
5e3dd157 KV |
1879 | } |
1880 | ||
95bf21f9 MK |
1881 | status = ath10k_wmi_connect(ar); |
1882 | if (status) { | |
7aa7a72a | 1883 | ath10k_err(ar, "could not connect wmi: %d\n", status); |
95bf21f9 MK |
1884 | goto err_hif_stop; |
1885 | } | |
1886 | ||
1887 | status = ath10k_htc_start(&ar->htc); | |
1888 | if (status) { | |
7aa7a72a | 1889 | ath10k_err(ar, "failed to start htc: %d\n", status); |
95bf21f9 MK |
1890 | goto err_hif_stop; |
1891 | } | |
1892 | ||
43d2a30f KV |
1893 | if (mode == ATH10K_FIRMWARE_MODE_NORMAL) { |
1894 | status = ath10k_wmi_wait_for_service_ready(ar); | |
9eea5689 | 1895 | if (status) { |
43d2a30f | 1896 | ath10k_warn(ar, "wmi service ready event not received"); |
43d2a30f KV |
1897 | goto err_hif_stop; |
1898 | } | |
95bf21f9 | 1899 | } |
5e3dd157 | 1900 | |
7aa7a72a | 1901 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "firmware %s booted\n", |
c8c39afe | 1902 | ar->hw->wiphy->fw_version); |
5e3dd157 | 1903 | |
f9575793 MSS |
1904 | if (test_bit(WMI_SERVICE_EXT_RES_CFG_SUPPORT, ar->wmi.svc_map)) { |
1905 | val = 0; | |
1906 | if (ath10k_peer_stats_enabled(ar)) | |
1907 | val = WMI_10_4_PEER_STATS; | |
1908 | ||
fa7937e3 RM |
1909 | if (test_bit(WMI_SERVICE_BSS_CHANNEL_INFO_64, ar->wmi.svc_map)) |
1910 | val |= WMI_10_4_BSS_CHANNEL_INFO_64; | |
1911 | ||
39136248 RM |
1912 | /* 10.4 firmware supports BT-Coex without reloading firmware |
1913 | * via pdev param. To support Bluetooth coexistence pdev param, | |
1914 | * WMI_COEX_GPIO_SUPPORT of extended resource config should be | |
1915 | * enabled always. | |
1916 | */ | |
1917 | if (test_bit(WMI_SERVICE_COEX_GPIO, ar->wmi.svc_map) && | |
1918 | test_bit(ATH10K_FW_FEATURE_BTCOEX_PARAM, | |
1919 | ar->running_fw->fw_file.fw_features)) | |
1920 | val |= WMI_10_4_COEX_GPIO_SUPPORT; | |
1921 | ||
7e247a9e | 1922 | status = ath10k_mac_ext_resource_config(ar, val); |
f9575793 MSS |
1923 | if (status) { |
1924 | ath10k_err(ar, | |
1925 | "failed to send ext resource cfg command : %d\n", | |
1926 | status); | |
1927 | goto err_hif_stop; | |
1928 | } | |
1929 | } | |
1930 | ||
5e3dd157 KV |
1931 | status = ath10k_wmi_cmd_init(ar); |
1932 | if (status) { | |
7aa7a72a MK |
1933 | ath10k_err(ar, "could not send WMI init command (%d)\n", |
1934 | status); | |
b7967dc7 | 1935 | goto err_hif_stop; |
5e3dd157 KV |
1936 | } |
1937 | ||
1938 | status = ath10k_wmi_wait_for_unified_ready(ar); | |
9eea5689 | 1939 | if (status) { |
7aa7a72a | 1940 | ath10k_err(ar, "wmi unified ready event not received\n"); |
b7967dc7 | 1941 | goto err_hif_stop; |
5e3dd157 KV |
1942 | } |
1943 | ||
47b1848d MK |
1944 | /* Some firmware revisions do not properly set up hardware rx filter |
1945 | * registers. | |
1946 | * | |
1947 | * A known example from QCA9880 and 10.2.4 is that MAC_PCU_ADDR1_MASK | |
1948 | * is filled with 0s instead of 1s allowing HW to respond with ACKs to | |
1949 | * any frames that matches MAC_PCU_RX_FILTER which is also | |
1950 | * misconfigured to accept anything. | |
1951 | * | |
1952 | * The ADDR1 is programmed using internal firmware structure field and | |
1953 | * can't be (easily/sanely) reached from the driver explicitly. It is | |
1954 | * possible to implicitly make it correct by creating a dummy vdev and | |
1955 | * then deleting it. | |
1956 | */ | |
1957 | status = ath10k_core_reset_rx_filter(ar); | |
1958 | if (status) { | |
1959 | ath10k_err(ar, "failed to reset rx filter: %d\n", status); | |
1960 | goto err_hif_stop; | |
1961 | } | |
1962 | ||
c545070e MK |
1963 | /* If firmware indicates Full Rx Reorder support it must be used in a |
1964 | * slightly different manner. Let HTT code know. | |
1965 | */ | |
1966 | ar->htt.rx_ring.in_ord_rx = !!(test_bit(WMI_SERVICE_RX_FULL_REORDER, | |
1967 | ar->wmi.svc_map)); | |
1968 | ||
1969 | status = ath10k_htt_rx_ring_refill(ar); | |
1970 | if (status) { | |
1971 | ath10k_err(ar, "failed to refill htt rx ring: %d\n", status); | |
1972 | goto err_hif_stop; | |
1973 | } | |
1974 | ||
4ad24a9d AK |
1975 | ar->free_vdev_map = (1LL << ar->max_num_vdevs) - 1; |
1976 | ||
1977 | INIT_LIST_HEAD(&ar->arvifs); | |
1978 | ||
43d2a30f KV |
1979 | /* we don't care about HTT in UTF mode */ |
1980 | if (mode == ATH10K_FIRMWARE_MODE_NORMAL) { | |
1981 | status = ath10k_htt_setup(&ar->htt); | |
1982 | if (status) { | |
1983 | ath10k_err(ar, "failed to setup htt: %d\n", status); | |
1984 | goto err_hif_stop; | |
1985 | } | |
95bf21f9 | 1986 | } |
5e3dd157 | 1987 | |
db66ea04 KV |
1988 | status = ath10k_debug_start(ar); |
1989 | if (status) | |
b7967dc7 | 1990 | goto err_hif_stop; |
db66ea04 | 1991 | |
dd30a36e MK |
1992 | return 0; |
1993 | ||
67e3c63f MK |
1994 | err_hif_stop: |
1995 | ath10k_hif_stop(ar); | |
95bf21f9 MK |
1996 | err_htt_rx_detach: |
1997 | ath10k_htt_rx_free(&ar->htt); | |
1998 | err_htt_tx_detach: | |
1999 | ath10k_htt_tx_free(&ar->htt); | |
dd30a36e MK |
2000 | err_wmi_detach: |
2001 | ath10k_wmi_detach(ar); | |
2002 | err: | |
2003 | return status; | |
2004 | } | |
818bdd16 | 2005 | EXPORT_SYMBOL(ath10k_core_start); |
dd30a36e | 2006 | |
00f5482b MP |
2007 | int ath10k_wait_for_suspend(struct ath10k *ar, u32 suspend_opt) |
2008 | { | |
2009 | int ret; | |
a7a42849 | 2010 | unsigned long time_left; |
00f5482b MP |
2011 | |
2012 | reinit_completion(&ar->target_suspend); | |
2013 | ||
2014 | ret = ath10k_wmi_pdev_suspend_target(ar, suspend_opt); | |
2015 | if (ret) { | |
7aa7a72a | 2016 | ath10k_warn(ar, "could not suspend target (%d)\n", ret); |
00f5482b MP |
2017 | return ret; |
2018 | } | |
2019 | ||
a7a42849 | 2020 | time_left = wait_for_completion_timeout(&ar->target_suspend, 1 * HZ); |
00f5482b | 2021 | |
a7a42849 | 2022 | if (!time_left) { |
7aa7a72a | 2023 | ath10k_warn(ar, "suspend timed out - target pause event never came\n"); |
00f5482b MP |
2024 | return -ETIMEDOUT; |
2025 | } | |
2026 | ||
2027 | return 0; | |
2028 | } | |
2029 | ||
dd30a36e MK |
2030 | void ath10k_core_stop(struct ath10k *ar) |
2031 | { | |
60631c5c | 2032 | lockdep_assert_held(&ar->conf_mutex); |
f1ee2682 | 2033 | ath10k_debug_stop(ar); |
60631c5c | 2034 | |
00f5482b | 2035 | /* try to suspend target */ |
43d2a30f KV |
2036 | if (ar->state != ATH10K_STATE_RESTARTING && |
2037 | ar->state != ATH10K_STATE_UTF) | |
216a1836 MK |
2038 | ath10k_wait_for_suspend(ar, WMI_PDEV_SUSPEND_AND_DISABLE_INTR); |
2039 | ||
95bf21f9 MK |
2040 | ath10k_hif_stop(ar); |
2041 | ath10k_htt_tx_free(&ar->htt); | |
2042 | ath10k_htt_rx_free(&ar->htt); | |
dd30a36e MK |
2043 | ath10k_wmi_detach(ar); |
2044 | } | |
818bdd16 MK |
2045 | EXPORT_SYMBOL(ath10k_core_stop); |
2046 | ||
2047 | /* mac80211 manages fw/hw initialization through start/stop hooks. However in | |
2048 | * order to know what hw capabilities should be advertised to mac80211 it is | |
2049 | * necessary to load the firmware (and tear it down immediately since start | |
2050 | * hook will try to init it again) before registering */ | |
2051 | static int ath10k_core_probe_fw(struct ath10k *ar) | |
2052 | { | |
29385057 MK |
2053 | struct bmi_target_info target_info; |
2054 | int ret = 0; | |
818bdd16 MK |
2055 | |
2056 | ret = ath10k_hif_power_up(ar); | |
2057 | if (ret) { | |
7aa7a72a | 2058 | ath10k_err(ar, "could not start pci hif (%d)\n", ret); |
818bdd16 MK |
2059 | return ret; |
2060 | } | |
2061 | ||
29385057 MK |
2062 | memset(&target_info, 0, sizeof(target_info)); |
2063 | ret = ath10k_bmi_get_target_info(ar, &target_info); | |
2064 | if (ret) { | |
7aa7a72a | 2065 | ath10k_err(ar, "could not get target info (%d)\n", ret); |
c6ce492d | 2066 | goto err_power_down; |
29385057 MK |
2067 | } |
2068 | ||
2069 | ar->target_version = target_info.version; | |
2070 | ar->hw->wiphy->hw_version = target_info.version; | |
2071 | ||
2072 | ret = ath10k_init_hw_params(ar); | |
2073 | if (ret) { | |
7aa7a72a | 2074 | ath10k_err(ar, "could not get hw params (%d)\n", ret); |
c6ce492d | 2075 | goto err_power_down; |
29385057 MK |
2076 | } |
2077 | ||
2078 | ret = ath10k_core_fetch_firmware_files(ar); | |
2079 | if (ret) { | |
7aa7a72a | 2080 | ath10k_err(ar, "could not fetch firmware files (%d)\n", ret); |
c6ce492d | 2081 | goto err_power_down; |
29385057 MK |
2082 | } |
2083 | ||
45317355 KV |
2084 | BUILD_BUG_ON(sizeof(ar->hw->wiphy->fw_version) != |
2085 | sizeof(ar->normal_mode_fw.fw_file.fw_version)); | |
2086 | memcpy(ar->hw->wiphy->fw_version, ar->normal_mode_fw.fw_file.fw_version, | |
2087 | sizeof(ar->hw->wiphy->fw_version)); | |
2088 | ||
23f591ea KV |
2089 | ath10k_debug_print_hwfw_info(ar); |
2090 | ||
3d9195ea RM |
2091 | ret = ath10k_core_pre_cal_download(ar); |
2092 | if (ret) { | |
2093 | /* pre calibration data download is not necessary | |
2094 | * for all the chipsets. Ignore failures and continue. | |
2095 | */ | |
2096 | ath10k_dbg(ar, ATH10K_DBG_BOOT, | |
2097 | "could not load pre cal data: %d\n", ret); | |
2098 | } | |
2099 | ||
db0984e5 MP |
2100 | ret = ath10k_core_get_board_id_from_otp(ar); |
2101 | if (ret && ret != -EOPNOTSUPP) { | |
b091f369 | 2102 | ath10k_err(ar, "failed to get board id from otp: %d\n", |
db0984e5 | 2103 | ret); |
b9c191be | 2104 | goto err_free_firmware_files; |
db0984e5 MP |
2105 | } |
2106 | ||
2107 | ret = ath10k_core_fetch_board_file(ar); | |
2108 | if (ret) { | |
2109 | ath10k_err(ar, "failed to fetch board file: %d\n", ret); | |
2110 | goto err_free_firmware_files; | |
2111 | } | |
2112 | ||
23f591ea KV |
2113 | ath10k_debug_print_board_info(ar); |
2114 | ||
5f2144d9 KV |
2115 | ret = ath10k_core_init_firmware_features(ar); |
2116 | if (ret) { | |
2117 | ath10k_err(ar, "fatal problem with firmware features: %d\n", | |
2118 | ret); | |
2119 | goto err_free_firmware_files; | |
2120 | } | |
cfd1061e | 2121 | |
5459c5d4 | 2122 | ret = ath10k_swap_code_seg_init(ar, &ar->normal_mode_fw.fw_file); |
dcb02db1 VT |
2123 | if (ret) { |
2124 | ath10k_err(ar, "failed to initialize code swap segment: %d\n", | |
2125 | ret); | |
2126 | goto err_free_firmware_files; | |
2127 | } | |
2128 | ||
60631c5c KV |
2129 | mutex_lock(&ar->conf_mutex); |
2130 | ||
7ebf721d KV |
2131 | ret = ath10k_core_start(ar, ATH10K_FIRMWARE_MODE_NORMAL, |
2132 | &ar->normal_mode_fw); | |
818bdd16 | 2133 | if (ret) { |
7aa7a72a | 2134 | ath10k_err(ar, "could not init core (%d)\n", ret); |
c6ce492d | 2135 | goto err_unlock; |
818bdd16 MK |
2136 | } |
2137 | ||
23f591ea | 2138 | ath10k_debug_print_boot_info(ar); |
818bdd16 | 2139 | ath10k_core_stop(ar); |
60631c5c KV |
2140 | |
2141 | mutex_unlock(&ar->conf_mutex); | |
2142 | ||
818bdd16 MK |
2143 | ath10k_hif_power_down(ar); |
2144 | return 0; | |
c6ce492d KV |
2145 | |
2146 | err_unlock: | |
2147 | mutex_unlock(&ar->conf_mutex); | |
2148 | ||
5f2144d9 | 2149 | err_free_firmware_files: |
c6ce492d KV |
2150 | ath10k_core_free_firmware_files(ar); |
2151 | ||
2152 | err_power_down: | |
2153 | ath10k_hif_power_down(ar); | |
2154 | ||
2155 | return ret; | |
818bdd16 | 2156 | } |
dd30a36e | 2157 | |
6782cb69 | 2158 | static void ath10k_core_register_work(struct work_struct *work) |
dd30a36e | 2159 | { |
6782cb69 | 2160 | struct ath10k *ar = container_of(work, struct ath10k, register_work); |
dd30a36e MK |
2161 | int status; |
2162 | ||
8c1d7fa5 TP |
2163 | /* peer stats are enabled by default */ |
2164 | set_bit(ATH10K_FLAG_PEER_STATS, &ar->dev_flags); | |
2165 | ||
818bdd16 MK |
2166 | status = ath10k_core_probe_fw(ar); |
2167 | if (status) { | |
7aa7a72a | 2168 | ath10k_err(ar, "could not probe fw (%d)\n", status); |
6782cb69 | 2169 | goto err; |
818bdd16 | 2170 | } |
dd30a36e | 2171 | |
5e3dd157 | 2172 | status = ath10k_mac_register(ar); |
818bdd16 | 2173 | if (status) { |
7aa7a72a | 2174 | ath10k_err(ar, "could not register to mac80211 (%d)\n", status); |
29385057 | 2175 | goto err_release_fw; |
818bdd16 | 2176 | } |
5e3dd157 | 2177 | |
e13cf7a3 | 2178 | status = ath10k_debug_register(ar); |
5e3dd157 | 2179 | if (status) { |
7aa7a72a | 2180 | ath10k_err(ar, "unable to initialize debugfs\n"); |
5e3dd157 KV |
2181 | goto err_unregister_mac; |
2182 | } | |
2183 | ||
855aed12 SW |
2184 | status = ath10k_spectral_create(ar); |
2185 | if (status) { | |
7aa7a72a | 2186 | ath10k_err(ar, "failed to initialize spectral\n"); |
855aed12 SW |
2187 | goto err_debug_destroy; |
2188 | } | |
2189 | ||
fe6f36d6 RM |
2190 | status = ath10k_thermal_register(ar); |
2191 | if (status) { | |
2192 | ath10k_err(ar, "could not register thermal device: %d\n", | |
2193 | status); | |
2194 | goto err_spectral_destroy; | |
2195 | } | |
2196 | ||
6782cb69 MK |
2197 | set_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags); |
2198 | return; | |
5e3dd157 | 2199 | |
fe6f36d6 RM |
2200 | err_spectral_destroy: |
2201 | ath10k_spectral_destroy(ar); | |
855aed12 SW |
2202 | err_debug_destroy: |
2203 | ath10k_debug_destroy(ar); | |
5e3dd157 KV |
2204 | err_unregister_mac: |
2205 | ath10k_mac_unregister(ar); | |
29385057 MK |
2206 | err_release_fw: |
2207 | ath10k_core_free_firmware_files(ar); | |
6782cb69 | 2208 | err: |
a491a920 MK |
2209 | /* TODO: It's probably a good idea to release device from the driver |
2210 | * but calling device_release_driver() here will cause a deadlock. | |
2211 | */ | |
6782cb69 MK |
2212 | return; |
2213 | } | |
2214 | ||
2215 | int ath10k_core_register(struct ath10k *ar, u32 chip_id) | |
2216 | { | |
6782cb69 | 2217 | ar->chip_id = chip_id; |
6782cb69 MK |
2218 | queue_work(ar->workqueue, &ar->register_work); |
2219 | ||
2220 | return 0; | |
5e3dd157 KV |
2221 | } |
2222 | EXPORT_SYMBOL(ath10k_core_register); | |
2223 | ||
2224 | void ath10k_core_unregister(struct ath10k *ar) | |
2225 | { | |
6782cb69 MK |
2226 | cancel_work_sync(&ar->register_work); |
2227 | ||
2228 | if (!test_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags)) | |
2229 | return; | |
2230 | ||
fe6f36d6 | 2231 | ath10k_thermal_unregister(ar); |
804eef14 SW |
2232 | /* Stop spectral before unregistering from mac80211 to remove the |
2233 | * relayfs debugfs file cleanly. Otherwise the parent debugfs tree | |
2234 | * would be already be free'd recursively, leading to a double free. | |
2235 | */ | |
2236 | ath10k_spectral_destroy(ar); | |
2237 | ||
5e3dd157 KV |
2238 | /* We must unregister from mac80211 before we stop HTC and HIF. |
2239 | * Otherwise we will fail to submit commands to FW and mac80211 will be | |
2240 | * unhappy about callback failures. */ | |
2241 | ath10k_mac_unregister(ar); | |
db66ea04 | 2242 | |
43d2a30f KV |
2243 | ath10k_testmode_destroy(ar); |
2244 | ||
29385057 | 2245 | ath10k_core_free_firmware_files(ar); |
0a51b343 | 2246 | ath10k_core_free_board_files(ar); |
6f1f56ea | 2247 | |
e13cf7a3 | 2248 | ath10k_debug_unregister(ar); |
5e3dd157 KV |
2249 | } |
2250 | EXPORT_SYMBOL(ath10k_core_unregister); | |
2251 | ||
e7b54194 | 2252 | struct ath10k *ath10k_core_create(size_t priv_size, struct device *dev, |
e07db352 | 2253 | enum ath10k_bus bus, |
d63955b3 | 2254 | enum ath10k_hw_rev hw_rev, |
0d0a6939 MK |
2255 | const struct ath10k_hif_ops *hif_ops) |
2256 | { | |
2257 | struct ath10k *ar; | |
e13cf7a3 | 2258 | int ret; |
0d0a6939 | 2259 | |
e7b54194 | 2260 | ar = ath10k_mac_create(priv_size); |
0d0a6939 MK |
2261 | if (!ar) |
2262 | return NULL; | |
2263 | ||
2264 | ar->ath_common.priv = ar; | |
2265 | ar->ath_common.hw = ar->hw; | |
0d0a6939 | 2266 | ar->dev = dev; |
d63955b3 | 2267 | ar->hw_rev = hw_rev; |
0d0a6939 | 2268 | ar->hif.ops = hif_ops; |
e07db352 | 2269 | ar->hif.bus = bus; |
0d0a6939 | 2270 | |
d63955b3 MK |
2271 | switch (hw_rev) { |
2272 | case ATH10K_HW_QCA988X: | |
6fd3dd71 | 2273 | case ATH10K_HW_QCA9887: |
d63955b3 | 2274 | ar->regs = &qca988x_regs; |
2f2cfc4a | 2275 | ar->hw_values = &qca988x_values; |
d63955b3 MK |
2276 | break; |
2277 | case ATH10K_HW_QCA6174: | |
a226b519 | 2278 | case ATH10K_HW_QCA9377: |
d63955b3 | 2279 | ar->regs = &qca6174_regs; |
2f2cfc4a | 2280 | ar->hw_values = &qca6174_values; |
d63955b3 | 2281 | break; |
8bd47021 | 2282 | case ATH10K_HW_QCA99X0: |
651b4cdc | 2283 | case ATH10K_HW_QCA9984: |
8bd47021 VT |
2284 | ar->regs = &qca99x0_regs; |
2285 | ar->hw_values = &qca99x0_values; | |
2286 | break; | |
e565c312 AK |
2287 | case ATH10K_HW_QCA9888: |
2288 | ar->regs = &qca99x0_regs; | |
2289 | ar->hw_values = &qca9888_values; | |
2290 | break; | |
37a219a5 RM |
2291 | case ATH10K_HW_QCA4019: |
2292 | ar->regs = &qca4019_regs; | |
2293 | ar->hw_values = &qca4019_values; | |
2294 | break; | |
d63955b3 MK |
2295 | default: |
2296 | ath10k_err(ar, "unsupported core hardware revision %d\n", | |
2297 | hw_rev); | |
2298 | ret = -ENOTSUPP; | |
2299 | goto err_free_mac; | |
2300 | } | |
2301 | ||
0d0a6939 MK |
2302 | init_completion(&ar->scan.started); |
2303 | init_completion(&ar->scan.completed); | |
2304 | init_completion(&ar->scan.on_channel); | |
2305 | init_completion(&ar->target_suspend); | |
5fd3ac3c | 2306 | init_completion(&ar->wow.wakeup_completed); |
0d0a6939 MK |
2307 | |
2308 | init_completion(&ar->install_key_done); | |
2309 | init_completion(&ar->vdev_setup_done); | |
ac2953fc | 2310 | init_completion(&ar->thermal.wmi_sync); |
fa7937e3 | 2311 | init_completion(&ar->bss_survey_done); |
0d0a6939 | 2312 | |
5c81c7fd | 2313 | INIT_DELAYED_WORK(&ar->scan.timeout, ath10k_scan_timeout_work); |
0d0a6939 MK |
2314 | |
2315 | ar->workqueue = create_singlethread_workqueue("ath10k_wq"); | |
2316 | if (!ar->workqueue) | |
e13cf7a3 | 2317 | goto err_free_mac; |
0d0a6939 | 2318 | |
c8ecfc1c RM |
2319 | ar->workqueue_aux = create_singlethread_workqueue("ath10k_aux_wq"); |
2320 | if (!ar->workqueue_aux) | |
2321 | goto err_free_wq; | |
2322 | ||
0d0a6939 MK |
2323 | mutex_init(&ar->conf_mutex); |
2324 | spin_lock_init(&ar->data_lock); | |
29946878 | 2325 | spin_lock_init(&ar->txqs_lock); |
0d0a6939 | 2326 | |
29946878 | 2327 | INIT_LIST_HEAD(&ar->txqs); |
0d0a6939 MK |
2328 | INIT_LIST_HEAD(&ar->peers); |
2329 | init_waitqueue_head(&ar->peer_mapping_wq); | |
7962b0d8 MK |
2330 | init_waitqueue_head(&ar->htt.empty_tx_wq); |
2331 | init_waitqueue_head(&ar->wmi.tx_credits_wq); | |
0d0a6939 MK |
2332 | |
2333 | init_completion(&ar->offchan_tx_completed); | |
2334 | INIT_WORK(&ar->offchan_tx_work, ath10k_offchan_tx_work); | |
2335 | skb_queue_head_init(&ar->offchan_tx_queue); | |
2336 | ||
2337 | INIT_WORK(&ar->wmi_mgmt_tx_work, ath10k_mgmt_over_wmi_tx_work); | |
2338 | skb_queue_head_init(&ar->wmi_mgmt_tx_queue); | |
2339 | ||
6782cb69 | 2340 | INIT_WORK(&ar->register_work, ath10k_core_register_work); |
0d0a6939 MK |
2341 | INIT_WORK(&ar->restart_work, ath10k_core_restart); |
2342 | ||
3c97f5de RM |
2343 | init_dummy_netdev(&ar->napi_dev); |
2344 | ||
e13cf7a3 MK |
2345 | ret = ath10k_debug_create(ar); |
2346 | if (ret) | |
c8ecfc1c | 2347 | goto err_free_aux_wq; |
e13cf7a3 | 2348 | |
0d0a6939 MK |
2349 | return ar; |
2350 | ||
c8ecfc1c RM |
2351 | err_free_aux_wq: |
2352 | destroy_workqueue(ar->workqueue_aux); | |
e13cf7a3 MK |
2353 | err_free_wq: |
2354 | destroy_workqueue(ar->workqueue); | |
2355 | ||
2356 | err_free_mac: | |
0d0a6939 | 2357 | ath10k_mac_destroy(ar); |
e13cf7a3 | 2358 | |
0d0a6939 MK |
2359 | return NULL; |
2360 | } | |
2361 | EXPORT_SYMBOL(ath10k_core_create); | |
2362 | ||
2363 | void ath10k_core_destroy(struct ath10k *ar) | |
2364 | { | |
2365 | flush_workqueue(ar->workqueue); | |
2366 | destroy_workqueue(ar->workqueue); | |
2367 | ||
c8ecfc1c RM |
2368 | flush_workqueue(ar->workqueue_aux); |
2369 | destroy_workqueue(ar->workqueue_aux); | |
2370 | ||
e13cf7a3 | 2371 | ath10k_debug_destroy(ar); |
a925a376 | 2372 | ath10k_wmi_free_host_mem(ar); |
0d0a6939 MK |
2373 | ath10k_mac_destroy(ar); |
2374 | } | |
2375 | EXPORT_SYMBOL(ath10k_core_destroy); | |
2376 | ||
5e3dd157 | 2377 | MODULE_AUTHOR("Qualcomm Atheros"); |
b855de0f | 2378 | MODULE_DESCRIPTION("Core module for Qualcomm Atheros 802.11ac wireless LAN cards."); |
5e3dd157 | 2379 | MODULE_LICENSE("Dual BSD/GPL"); |