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5e3dd157 KV |
1 | /* |
2 | * Copyright (c) 2005-2011 Atheros Communications Inc. | |
3 | * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. | |
4 | * | |
5 | * Permission to use, copy, modify, and/or distribute this software for any | |
6 | * purpose with or without fee is hereby granted, provided that the above | |
7 | * copyright notice and this permission notice appear in all copies. | |
8 | * | |
9 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
10 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
11 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
12 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
13 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
14 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
15 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
16 | */ | |
17 | ||
18 | #include <linux/module.h> | |
19 | #include <linux/firmware.h> | |
5aabff05 | 20 | #include <linux/of.h> |
5e3dd157 KV |
21 | |
22 | #include "core.h" | |
23 | #include "mac.h" | |
24 | #include "htc.h" | |
25 | #include "hif.h" | |
26 | #include "wmi.h" | |
27 | #include "bmi.h" | |
28 | #include "debug.h" | |
29 | #include "htt.h" | |
43d2a30f | 30 | #include "testmode.h" |
d7579d12 | 31 | #include "wmi-ops.h" |
5e3dd157 KV |
32 | |
33 | unsigned int ath10k_debug_mask; | |
ccec9038 | 34 | static unsigned int ath10k_cryptmode_param; |
5e3dd157 | 35 | static bool uart_print; |
8868b12c RM |
36 | static bool skip_otp; |
37 | ||
5e3dd157 | 38 | module_param_named(debug_mask, ath10k_debug_mask, uint, 0644); |
ccec9038 | 39 | module_param_named(cryptmode, ath10k_cryptmode_param, uint, 0644); |
5e3dd157 | 40 | module_param(uart_print, bool, 0644); |
8868b12c RM |
41 | module_param(skip_otp, bool, 0644); |
42 | ||
5e3dd157 KV |
43 | MODULE_PARM_DESC(debug_mask, "Debugging mask"); |
44 | MODULE_PARM_DESC(uart_print, "Uart target debugging"); | |
8868b12c | 45 | MODULE_PARM_DESC(skip_otp, "Skip otp failure for calibration in testmode"); |
ccec9038 | 46 | MODULE_PARM_DESC(cryptmode, "Crypto mode: 0-hardware, 1-software"); |
5e3dd157 KV |
47 | |
48 | static const struct ath10k_hw_params ath10k_hw_params_list[] = { | |
5e3dd157 KV |
49 | { |
50 | .id = QCA988X_HW_2_0_VERSION, | |
51 | .name = "qca988x hw2.0", | |
52 | .patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR, | |
3a8200b2 | 53 | .uart_pin = 7, |
587f7031 | 54 | .has_shifted_cc_wraparound = true, |
d772703e | 55 | .otp_exe_param = 0, |
9c8fb548 | 56 | .channel_counters_freq_hz = 88000, |
7b7da0a0 | 57 | .max_probe_resp_desc_thres = 0, |
5e3dd157 KV |
58 | .fw = { |
59 | .dir = QCA988X_HW_2_0_FW_DIR, | |
60 | .fw = QCA988X_HW_2_0_FW_FILE, | |
61 | .otp = QCA988X_HW_2_0_OTP_FILE, | |
62 | .board = QCA988X_HW_2_0_BOARD_DATA_FILE, | |
9764a2af MK |
63 | .board_size = QCA988X_BOARD_DATA_SZ, |
64 | .board_ext_size = QCA988X_BOARD_EXT_DATA_SZ, | |
5e3dd157 KV |
65 | }, |
66 | }, | |
d63955b3 MK |
67 | { |
68 | .id = QCA6174_HW_2_1_VERSION, | |
69 | .name = "qca6174 hw2.1", | |
70 | .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR, | |
71 | .uart_pin = 6, | |
d772703e | 72 | .otp_exe_param = 0, |
9c8fb548 | 73 | .channel_counters_freq_hz = 88000, |
7b7da0a0 | 74 | .max_probe_resp_desc_thres = 0, |
d63955b3 MK |
75 | .fw = { |
76 | .dir = QCA6174_HW_2_1_FW_DIR, | |
77 | .fw = QCA6174_HW_2_1_FW_FILE, | |
78 | .otp = QCA6174_HW_2_1_OTP_FILE, | |
79 | .board = QCA6174_HW_2_1_BOARD_DATA_FILE, | |
80 | .board_size = QCA6174_BOARD_DATA_SZ, | |
81 | .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, | |
82 | }, | |
83 | }, | |
84 | { | |
85 | .id = QCA6174_HW_3_0_VERSION, | |
86 | .name = "qca6174 hw3.0", | |
87 | .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR, | |
88 | .uart_pin = 6, | |
d772703e | 89 | .otp_exe_param = 0, |
9c8fb548 | 90 | .channel_counters_freq_hz = 88000, |
7b7da0a0 | 91 | .max_probe_resp_desc_thres = 0, |
d63955b3 MK |
92 | .fw = { |
93 | .dir = QCA6174_HW_3_0_FW_DIR, | |
94 | .fw = QCA6174_HW_3_0_FW_FILE, | |
95 | .otp = QCA6174_HW_3_0_OTP_FILE, | |
96 | .board = QCA6174_HW_3_0_BOARD_DATA_FILE, | |
97 | .board_size = QCA6174_BOARD_DATA_SZ, | |
98 | .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, | |
99 | }, | |
100 | }, | |
608b8f73 MK |
101 | { |
102 | .id = QCA6174_HW_3_2_VERSION, | |
103 | .name = "qca6174 hw3.2", | |
104 | .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR, | |
105 | .uart_pin = 6, | |
d772703e | 106 | .otp_exe_param = 0, |
9c8fb548 | 107 | .channel_counters_freq_hz = 88000, |
7b7da0a0 | 108 | .max_probe_resp_desc_thres = 0, |
608b8f73 MK |
109 | .fw = { |
110 | /* uses same binaries as hw3.0 */ | |
111 | .dir = QCA6174_HW_3_0_FW_DIR, | |
112 | .fw = QCA6174_HW_3_0_FW_FILE, | |
113 | .otp = QCA6174_HW_3_0_OTP_FILE, | |
114 | .board = QCA6174_HW_3_0_BOARD_DATA_FILE, | |
115 | .board_size = QCA6174_BOARD_DATA_SZ, | |
116 | .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ, | |
117 | }, | |
118 | }, | |
8bd47021 VT |
119 | { |
120 | .id = QCA99X0_HW_2_0_DEV_VERSION, | |
121 | .name = "qca99x0 hw2.0", | |
122 | .patch_load_addr = QCA99X0_HW_2_0_PATCH_LOAD_ADDR, | |
123 | .uart_pin = 7, | |
d772703e | 124 | .otp_exe_param = 0x00000700, |
d9156b5f | 125 | .continuous_frag_desc = true, |
9c8fb548 | 126 | .channel_counters_freq_hz = 150000, |
7b7da0a0 | 127 | .max_probe_resp_desc_thres = 24, |
8bd47021 VT |
128 | .fw = { |
129 | .dir = QCA99X0_HW_2_0_FW_DIR, | |
130 | .fw = QCA99X0_HW_2_0_FW_FILE, | |
131 | .otp = QCA99X0_HW_2_0_OTP_FILE, | |
132 | .board = QCA99X0_HW_2_0_BOARD_DATA_FILE, | |
133 | .board_size = QCA99X0_BOARD_DATA_SZ, | |
134 | .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ, | |
135 | }, | |
136 | }, | |
5e3dd157 KV |
137 | }; |
138 | ||
b27bc5a4 MK |
139 | static const char *const ath10k_core_fw_feature_str[] = { |
140 | [ATH10K_FW_FEATURE_EXT_WMI_MGMT_RX] = "wmi-mgmt-rx", | |
141 | [ATH10K_FW_FEATURE_WMI_10X] = "wmi-10.x", | |
142 | [ATH10K_FW_FEATURE_HAS_WMI_MGMT_TX] = "has-wmi-mgmt-tx", | |
143 | [ATH10K_FW_FEATURE_NO_P2P] = "no-p2p", | |
144 | [ATH10K_FW_FEATURE_WMI_10_2] = "wmi-10.2", | |
145 | [ATH10K_FW_FEATURE_MULTI_VIF_PS_SUPPORT] = "multi-vif-ps", | |
146 | [ATH10K_FW_FEATURE_WOWLAN_SUPPORT] = "wowlan", | |
147 | [ATH10K_FW_FEATURE_IGNORE_OTP_RESULT] = "ignore-otp", | |
148 | [ATH10K_FW_FEATURE_NO_NWIFI_DECAP_4ADDR_PADDING] = "no-4addr-pad", | |
149 | [ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT] = "skip-clock-init", | |
150 | }; | |
151 | ||
152 | static unsigned int ath10k_core_get_fw_feature_str(char *buf, | |
153 | size_t buf_len, | |
154 | enum ath10k_fw_features feat) | |
155 | { | |
156 | if (feat >= ARRAY_SIZE(ath10k_core_fw_feature_str) || | |
157 | WARN_ON(!ath10k_core_fw_feature_str[feat])) { | |
158 | return scnprintf(buf, buf_len, "bit%d", feat); | |
159 | } | |
160 | ||
161 | return scnprintf(buf, buf_len, "%s", ath10k_core_fw_feature_str[feat]); | |
162 | } | |
163 | ||
164 | void ath10k_core_get_fw_features_str(struct ath10k *ar, | |
165 | char *buf, | |
166 | size_t buf_len) | |
167 | { | |
168 | unsigned int len = 0; | |
169 | int i; | |
170 | ||
171 | for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) { | |
172 | if (test_bit(i, ar->fw_features)) { | |
173 | if (len > 0) | |
174 | len += scnprintf(buf + len, buf_len - len, ","); | |
175 | ||
176 | len += ath10k_core_get_fw_feature_str(buf + len, | |
177 | buf_len - len, | |
178 | i); | |
179 | } | |
180 | } | |
181 | } | |
182 | ||
5e3dd157 KV |
183 | static void ath10k_send_suspend_complete(struct ath10k *ar) |
184 | { | |
7aa7a72a | 185 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot suspend complete\n"); |
5e3dd157 | 186 | |
9042e17d | 187 | complete(&ar->target_suspend); |
5e3dd157 KV |
188 | } |
189 | ||
5e3dd157 KV |
190 | static int ath10k_init_configure_target(struct ath10k *ar) |
191 | { | |
192 | u32 param_host; | |
193 | int ret; | |
194 | ||
195 | /* tell target which HTC version it is used*/ | |
196 | ret = ath10k_bmi_write32(ar, hi_app_host_interest, | |
197 | HTC_PROTOCOL_VERSION); | |
198 | if (ret) { | |
7aa7a72a | 199 | ath10k_err(ar, "settings HTC version failed\n"); |
5e3dd157 KV |
200 | return ret; |
201 | } | |
202 | ||
203 | /* set the firmware mode to STA/IBSS/AP */ | |
204 | ret = ath10k_bmi_read32(ar, hi_option_flag, ¶m_host); | |
205 | if (ret) { | |
7aa7a72a | 206 | ath10k_err(ar, "setting firmware mode (1/2) failed\n"); |
5e3dd157 KV |
207 | return ret; |
208 | } | |
209 | ||
210 | /* TODO following parameters need to be re-visited. */ | |
211 | /* num_device */ | |
212 | param_host |= (1 << HI_OPTION_NUM_DEV_SHIFT); | |
213 | /* Firmware mode */ | |
214 | /* FIXME: Why FW_MODE_AP ??.*/ | |
215 | param_host |= (HI_OPTION_FW_MODE_AP << HI_OPTION_FW_MODE_SHIFT); | |
216 | /* mac_addr_method */ | |
217 | param_host |= (1 << HI_OPTION_MAC_ADDR_METHOD_SHIFT); | |
218 | /* firmware_bridge */ | |
219 | param_host |= (0 << HI_OPTION_FW_BRIDGE_SHIFT); | |
220 | /* fwsubmode */ | |
221 | param_host |= (0 << HI_OPTION_FW_SUBMODE_SHIFT); | |
222 | ||
223 | ret = ath10k_bmi_write32(ar, hi_option_flag, param_host); | |
224 | if (ret) { | |
7aa7a72a | 225 | ath10k_err(ar, "setting firmware mode (2/2) failed\n"); |
5e3dd157 KV |
226 | return ret; |
227 | } | |
228 | ||
229 | /* We do all byte-swapping on the host */ | |
230 | ret = ath10k_bmi_write32(ar, hi_be, 0); | |
231 | if (ret) { | |
7aa7a72a | 232 | ath10k_err(ar, "setting host CPU BE mode failed\n"); |
5e3dd157 KV |
233 | return ret; |
234 | } | |
235 | ||
236 | /* FW descriptor/Data swap flags */ | |
237 | ret = ath10k_bmi_write32(ar, hi_fw_swap, 0); | |
238 | ||
239 | if (ret) { | |
7aa7a72a | 240 | ath10k_err(ar, "setting FW data/desc swap flags failed\n"); |
5e3dd157 KV |
241 | return ret; |
242 | } | |
243 | ||
36582e5d MK |
244 | /* Some devices have a special sanity check that verifies the PCI |
245 | * Device ID is written to this host interest var. It is known to be | |
246 | * required to boot QCA6164. | |
247 | */ | |
248 | ret = ath10k_bmi_write32(ar, hi_hci_uart_pwr_mgmt_params_ext, | |
249 | ar->dev_id); | |
250 | if (ret) { | |
251 | ath10k_err(ar, "failed to set pwr_mgmt_params: %d\n", ret); | |
252 | return ret; | |
253 | } | |
254 | ||
5e3dd157 KV |
255 | return 0; |
256 | } | |
257 | ||
258 | static const struct firmware *ath10k_fetch_fw_file(struct ath10k *ar, | |
259 | const char *dir, | |
260 | const char *file) | |
261 | { | |
262 | char filename[100]; | |
263 | const struct firmware *fw; | |
264 | int ret; | |
265 | ||
266 | if (file == NULL) | |
267 | return ERR_PTR(-ENOENT); | |
268 | ||
269 | if (dir == NULL) | |
270 | dir = "."; | |
271 | ||
272 | snprintf(filename, sizeof(filename), "%s/%s", dir, file); | |
273 | ret = request_firmware(&fw, filename, ar->dev); | |
274 | if (ret) | |
275 | return ERR_PTR(ret); | |
276 | ||
277 | return fw; | |
278 | } | |
279 | ||
a58227ef KV |
280 | static int ath10k_push_board_ext_data(struct ath10k *ar, const void *data, |
281 | size_t data_len) | |
5e3dd157 | 282 | { |
9764a2af MK |
283 | u32 board_data_size = ar->hw_params.fw.board_size; |
284 | u32 board_ext_data_size = ar->hw_params.fw.board_ext_size; | |
5e3dd157 KV |
285 | u32 board_ext_data_addr; |
286 | int ret; | |
287 | ||
288 | ret = ath10k_bmi_read32(ar, hi_board_ext_data, &board_ext_data_addr); | |
289 | if (ret) { | |
7aa7a72a MK |
290 | ath10k_err(ar, "could not read board ext data addr (%d)\n", |
291 | ret); | |
5e3dd157 KV |
292 | return ret; |
293 | } | |
294 | ||
7aa7a72a | 295 | ath10k_dbg(ar, ATH10K_DBG_BOOT, |
effea968 | 296 | "boot push board extended data addr 0x%x\n", |
5e3dd157 KV |
297 | board_ext_data_addr); |
298 | ||
299 | if (board_ext_data_addr == 0) | |
300 | return 0; | |
301 | ||
a58227ef | 302 | if (data_len != (board_data_size + board_ext_data_size)) { |
7aa7a72a | 303 | ath10k_err(ar, "invalid board (ext) data sizes %zu != %d+%d\n", |
a58227ef | 304 | data_len, board_data_size, board_ext_data_size); |
5e3dd157 KV |
305 | return -EINVAL; |
306 | } | |
307 | ||
308 | ret = ath10k_bmi_write_memory(ar, board_ext_data_addr, | |
a58227ef | 309 | data + board_data_size, |
5e3dd157 KV |
310 | board_ext_data_size); |
311 | if (ret) { | |
7aa7a72a | 312 | ath10k_err(ar, "could not write board ext data (%d)\n", ret); |
5e3dd157 KV |
313 | return ret; |
314 | } | |
315 | ||
316 | ret = ath10k_bmi_write32(ar, hi_board_ext_data_config, | |
317 | (board_ext_data_size << 16) | 1); | |
318 | if (ret) { | |
7aa7a72a MK |
319 | ath10k_err(ar, "could not write board ext data bit (%d)\n", |
320 | ret); | |
5e3dd157 KV |
321 | return ret; |
322 | } | |
323 | ||
324 | return 0; | |
325 | } | |
326 | ||
a58227ef KV |
327 | static int ath10k_download_board_data(struct ath10k *ar, const void *data, |
328 | size_t data_len) | |
5e3dd157 | 329 | { |
9764a2af | 330 | u32 board_data_size = ar->hw_params.fw.board_size; |
5e3dd157 | 331 | u32 address; |
5e3dd157 KV |
332 | int ret; |
333 | ||
a58227ef | 334 | ret = ath10k_push_board_ext_data(ar, data, data_len); |
5e3dd157 | 335 | if (ret) { |
7aa7a72a | 336 | ath10k_err(ar, "could not push board ext data (%d)\n", ret); |
5e3dd157 KV |
337 | goto exit; |
338 | } | |
339 | ||
340 | ret = ath10k_bmi_read32(ar, hi_board_data, &address); | |
341 | if (ret) { | |
7aa7a72a | 342 | ath10k_err(ar, "could not read board data addr (%d)\n", ret); |
5e3dd157 KV |
343 | goto exit; |
344 | } | |
345 | ||
a58227ef | 346 | ret = ath10k_bmi_write_memory(ar, address, data, |
958df3a0 | 347 | min_t(u32, board_data_size, |
a58227ef | 348 | data_len)); |
5e3dd157 | 349 | if (ret) { |
7aa7a72a | 350 | ath10k_err(ar, "could not write board data (%d)\n", ret); |
5e3dd157 KV |
351 | goto exit; |
352 | } | |
353 | ||
354 | ret = ath10k_bmi_write32(ar, hi_board_data_initialized, 1); | |
355 | if (ret) { | |
7aa7a72a | 356 | ath10k_err(ar, "could not write board data bit (%d)\n", ret); |
5e3dd157 KV |
357 | goto exit; |
358 | } | |
359 | ||
360 | exit: | |
5e3dd157 KV |
361 | return ret; |
362 | } | |
363 | ||
a58227ef KV |
364 | static int ath10k_download_cal_file(struct ath10k *ar) |
365 | { | |
366 | int ret; | |
367 | ||
368 | if (!ar->cal_file) | |
369 | return -ENOENT; | |
370 | ||
371 | if (IS_ERR(ar->cal_file)) | |
372 | return PTR_ERR(ar->cal_file); | |
373 | ||
374 | ret = ath10k_download_board_data(ar, ar->cal_file->data, | |
375 | ar->cal_file->size); | |
376 | if (ret) { | |
377 | ath10k_err(ar, "failed to download cal_file data: %d\n", ret); | |
378 | return ret; | |
379 | } | |
380 | ||
381 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cal file downloaded\n"); | |
382 | ||
383 | return 0; | |
384 | } | |
385 | ||
5aabff05 TK |
386 | static int ath10k_download_cal_dt(struct ath10k *ar) |
387 | { | |
388 | struct device_node *node; | |
389 | int data_len; | |
390 | void *data; | |
391 | int ret; | |
392 | ||
393 | node = ar->dev->of_node; | |
394 | if (!node) | |
395 | /* Device Tree is optional, don't print any warnings if | |
396 | * there's no node for ath10k. | |
397 | */ | |
398 | return -ENOENT; | |
399 | ||
400 | if (!of_get_property(node, "qcom,ath10k-calibration-data", | |
401 | &data_len)) { | |
402 | /* The calibration data node is optional */ | |
403 | return -ENOENT; | |
404 | } | |
405 | ||
406 | if (data_len != QCA988X_CAL_DATA_LEN) { | |
407 | ath10k_warn(ar, "invalid calibration data length in DT: %d\n", | |
408 | data_len); | |
409 | ret = -EMSGSIZE; | |
410 | goto out; | |
411 | } | |
412 | ||
413 | data = kmalloc(data_len, GFP_KERNEL); | |
414 | if (!data) { | |
415 | ret = -ENOMEM; | |
416 | goto out; | |
417 | } | |
418 | ||
419 | ret = of_property_read_u8_array(node, "qcom,ath10k-calibration-data", | |
420 | data, data_len); | |
421 | if (ret) { | |
422 | ath10k_warn(ar, "failed to read calibration data from DT: %d\n", | |
423 | ret); | |
424 | goto out_free; | |
425 | } | |
426 | ||
427 | ret = ath10k_download_board_data(ar, data, data_len); | |
428 | if (ret) { | |
429 | ath10k_warn(ar, "failed to download calibration data from Device Tree: %d\n", | |
430 | ret); | |
431 | goto out_free; | |
432 | } | |
433 | ||
434 | ret = 0; | |
435 | ||
436 | out_free: | |
437 | kfree(data); | |
438 | ||
439 | out: | |
440 | return ret; | |
441 | } | |
442 | ||
5e3dd157 KV |
443 | static int ath10k_download_and_run_otp(struct ath10k *ar) |
444 | { | |
d6d4a58d | 445 | u32 result, address = ar->hw_params.patch_load_addr; |
d772703e | 446 | u32 bmi_otp_exe_param = ar->hw_params.otp_exe_param; |
5e3dd157 KV |
447 | int ret; |
448 | ||
a58227ef | 449 | ret = ath10k_download_board_data(ar, ar->board_data, ar->board_len); |
83091559 KV |
450 | if (ret) { |
451 | ath10k_err(ar, "failed to download board data: %d\n", ret); | |
452 | return ret; | |
453 | } | |
454 | ||
5e3dd157 KV |
455 | /* OTP is optional */ |
456 | ||
7f06ea1e | 457 | if (!ar->otp_data || !ar->otp_len) { |
7aa7a72a | 458 | ath10k_warn(ar, "Not running otp, calibration will be incorrect (otp-data %p otp_len %zd)!\n", |
36a8f413 | 459 | ar->otp_data, ar->otp_len); |
5e3dd157 | 460 | return 0; |
7f06ea1e KV |
461 | } |
462 | ||
7aa7a72a | 463 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot upload otp to 0x%x len %zd\n", |
7f06ea1e | 464 | address, ar->otp_len); |
5e3dd157 | 465 | |
958df3a0 | 466 | ret = ath10k_bmi_fast_download(ar, address, ar->otp_data, ar->otp_len); |
5e3dd157 | 467 | if (ret) { |
7aa7a72a | 468 | ath10k_err(ar, "could not write otp (%d)\n", ret); |
7f06ea1e | 469 | return ret; |
5e3dd157 KV |
470 | } |
471 | ||
d772703e | 472 | ret = ath10k_bmi_execute(ar, address, bmi_otp_exe_param, &result); |
5e3dd157 | 473 | if (ret) { |
7aa7a72a | 474 | ath10k_err(ar, "could not execute otp (%d)\n", ret); |
7f06ea1e | 475 | return ret; |
5e3dd157 KV |
476 | } |
477 | ||
7aa7a72a | 478 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot otp execute result %d\n", result); |
7f06ea1e | 479 | |
d9153546 KV |
480 | if (!(skip_otp || test_bit(ATH10K_FW_FEATURE_IGNORE_OTP_RESULT, |
481 | ar->fw_features)) | |
482 | && result != 0) { | |
7aa7a72a | 483 | ath10k_err(ar, "otp calibration failed: %d", result); |
7f06ea1e KV |
484 | return -EINVAL; |
485 | } | |
486 | ||
487 | return 0; | |
5e3dd157 KV |
488 | } |
489 | ||
43d2a30f | 490 | static int ath10k_download_fw(struct ath10k *ar, enum ath10k_firmware_mode mode) |
5e3dd157 | 491 | { |
43d2a30f KV |
492 | u32 address, data_len; |
493 | const char *mode_name; | |
494 | const void *data; | |
5e3dd157 KV |
495 | int ret; |
496 | ||
5e3dd157 KV |
497 | address = ar->hw_params.patch_load_addr; |
498 | ||
43d2a30f KV |
499 | switch (mode) { |
500 | case ATH10K_FIRMWARE_MODE_NORMAL: | |
501 | data = ar->firmware_data; | |
502 | data_len = ar->firmware_len; | |
503 | mode_name = "normal"; | |
dcb02db1 VT |
504 | ret = ath10k_swap_code_seg_configure(ar, |
505 | ATH10K_SWAP_CODE_SEG_BIN_TYPE_FW); | |
506 | if (ret) { | |
507 | ath10k_err(ar, "failed to configure fw code swap: %d\n", | |
508 | ret); | |
509 | return ret; | |
510 | } | |
43d2a30f KV |
511 | break; |
512 | case ATH10K_FIRMWARE_MODE_UTF: | |
513 | data = ar->testmode.utf->data; | |
514 | data_len = ar->testmode.utf->size; | |
515 | mode_name = "utf"; | |
516 | break; | |
517 | default: | |
518 | ath10k_err(ar, "unknown firmware mode: %d\n", mode); | |
519 | return -EINVAL; | |
520 | } | |
521 | ||
522 | ath10k_dbg(ar, ATH10K_DBG_BOOT, | |
523 | "boot uploading firmware image %p len %d mode %s\n", | |
524 | data, data_len, mode_name); | |
525 | ||
526 | ret = ath10k_bmi_fast_download(ar, address, data, data_len); | |
5e3dd157 | 527 | if (ret) { |
43d2a30f KV |
528 | ath10k_err(ar, "failed to download %s firmware: %d\n", |
529 | mode_name, ret); | |
530 | return ret; | |
5e3dd157 KV |
531 | } |
532 | ||
29385057 MK |
533 | return ret; |
534 | } | |
535 | ||
536 | static void ath10k_core_free_firmware_files(struct ath10k *ar) | |
537 | { | |
db2cf865 | 538 | if (!IS_ERR(ar->board)) |
36527916 | 539 | release_firmware(ar->board); |
29385057 | 540 | |
db2cf865 | 541 | if (!IS_ERR(ar->otp)) |
29385057 MK |
542 | release_firmware(ar->otp); |
543 | ||
db2cf865 | 544 | if (!IS_ERR(ar->firmware)) |
29385057 MK |
545 | release_firmware(ar->firmware); |
546 | ||
db2cf865 | 547 | if (!IS_ERR(ar->cal_file)) |
a58227ef KV |
548 | release_firmware(ar->cal_file); |
549 | ||
dcb02db1 VT |
550 | ath10k_swap_code_seg_release(ar); |
551 | ||
36527916 | 552 | ar->board = NULL; |
958df3a0 KV |
553 | ar->board_data = NULL; |
554 | ar->board_len = 0; | |
555 | ||
29385057 | 556 | ar->otp = NULL; |
958df3a0 KV |
557 | ar->otp_data = NULL; |
558 | ar->otp_len = 0; | |
559 | ||
29385057 | 560 | ar->firmware = NULL; |
958df3a0 KV |
561 | ar->firmware_data = NULL; |
562 | ar->firmware_len = 0; | |
a58227ef KV |
563 | |
564 | ar->cal_file = NULL; | |
dcb02db1 | 565 | |
a58227ef KV |
566 | } |
567 | ||
568 | static int ath10k_fetch_cal_file(struct ath10k *ar) | |
569 | { | |
570 | char filename[100]; | |
571 | ||
572 | /* cal-<bus>-<id>.bin */ | |
573 | scnprintf(filename, sizeof(filename), "cal-%s-%s.bin", | |
574 | ath10k_bus_str(ar->hif.bus), dev_name(ar->dev)); | |
575 | ||
576 | ar->cal_file = ath10k_fetch_fw_file(ar, ATH10K_FW_DIR, filename); | |
577 | if (IS_ERR(ar->cal_file)) | |
578 | /* calibration file is optional, don't print any warnings */ | |
579 | return PTR_ERR(ar->cal_file); | |
580 | ||
581 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "found calibration file %s/%s\n", | |
582 | ATH10K_FW_DIR, filename); | |
583 | ||
584 | return 0; | |
29385057 MK |
585 | } |
586 | ||
de57e2c8 | 587 | static int ath10k_core_fetch_spec_board_file(struct ath10k *ar) |
29385057 | 588 | { |
de57e2c8 MK |
589 | char filename[100]; |
590 | ||
591 | scnprintf(filename, sizeof(filename), "board-%s-%s.bin", | |
592 | ath10k_bus_str(ar->hif.bus), ar->spec_board_id); | |
593 | ||
594 | ar->board = ath10k_fetch_fw_file(ar, ar->hw_params.fw.dir, filename); | |
595 | if (IS_ERR(ar->board)) | |
596 | return PTR_ERR(ar->board); | |
597 | ||
598 | ar->board_data = ar->board->data; | |
599 | ar->board_len = ar->board->size; | |
600 | ar->spec_board_loaded = true; | |
29385057 | 601 | |
de57e2c8 MK |
602 | return 0; |
603 | } | |
604 | ||
605 | static int ath10k_core_fetch_generic_board_file(struct ath10k *ar) | |
606 | { | |
d0ed74f3 MK |
607 | if (!ar->hw_params.fw.board) { |
608 | ath10k_err(ar, "failed to find board file fw entry\n"); | |
29385057 MK |
609 | return -EINVAL; |
610 | } | |
611 | ||
36527916 KV |
612 | ar->board = ath10k_fetch_fw_file(ar, |
613 | ar->hw_params.fw.dir, | |
614 | ar->hw_params.fw.board); | |
de57e2c8 MK |
615 | if (IS_ERR(ar->board)) |
616 | return PTR_ERR(ar->board); | |
29385057 | 617 | |
958df3a0 KV |
618 | ar->board_data = ar->board->data; |
619 | ar->board_len = ar->board->size; | |
de57e2c8 MK |
620 | ar->spec_board_loaded = false; |
621 | ||
622 | return 0; | |
623 | } | |
624 | ||
625 | static int ath10k_core_fetch_board_file(struct ath10k *ar) | |
626 | { | |
627 | int ret; | |
628 | ||
629 | if (strlen(ar->spec_board_id) > 0) { | |
630 | ret = ath10k_core_fetch_spec_board_file(ar); | |
631 | if (ret) { | |
632 | ath10k_info(ar, "failed to load spec board file, falling back to generic: %d\n", | |
633 | ret); | |
634 | goto generic; | |
635 | } | |
636 | ||
637 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "found specific board file for %s\n", | |
638 | ar->spec_board_id); | |
639 | return 0; | |
640 | } | |
641 | ||
642 | generic: | |
643 | ret = ath10k_core_fetch_generic_board_file(ar); | |
644 | if (ret) { | |
645 | ath10k_err(ar, "failed to fetch generic board data: %d\n", ret); | |
646 | return ret; | |
647 | } | |
958df3a0 | 648 | |
d0ed74f3 MK |
649 | return 0; |
650 | } | |
651 | ||
652 | static int ath10k_core_fetch_firmware_api_1(struct ath10k *ar) | |
653 | { | |
654 | int ret = 0; | |
655 | ||
656 | if (ar->hw_params.fw.fw == NULL) { | |
657 | ath10k_err(ar, "firmware file not defined\n"); | |
658 | return -EINVAL; | |
659 | } | |
660 | ||
29385057 MK |
661 | ar->firmware = ath10k_fetch_fw_file(ar, |
662 | ar->hw_params.fw.dir, | |
663 | ar->hw_params.fw.fw); | |
664 | if (IS_ERR(ar->firmware)) { | |
665 | ret = PTR_ERR(ar->firmware); | |
7aa7a72a | 666 | ath10k_err(ar, "could not fetch firmware (%d)\n", ret); |
29385057 MK |
667 | goto err; |
668 | } | |
669 | ||
958df3a0 KV |
670 | ar->firmware_data = ar->firmware->data; |
671 | ar->firmware_len = ar->firmware->size; | |
672 | ||
29385057 MK |
673 | /* OTP may be undefined. If so, don't fetch it at all */ |
674 | if (ar->hw_params.fw.otp == NULL) | |
675 | return 0; | |
676 | ||
677 | ar->otp = ath10k_fetch_fw_file(ar, | |
678 | ar->hw_params.fw.dir, | |
679 | ar->hw_params.fw.otp); | |
680 | if (IS_ERR(ar->otp)) { | |
681 | ret = PTR_ERR(ar->otp); | |
7aa7a72a | 682 | ath10k_err(ar, "could not fetch otp (%d)\n", ret); |
29385057 MK |
683 | goto err; |
684 | } | |
685 | ||
958df3a0 KV |
686 | ar->otp_data = ar->otp->data; |
687 | ar->otp_len = ar->otp->size; | |
688 | ||
29385057 MK |
689 | return 0; |
690 | ||
691 | err: | |
692 | ath10k_core_free_firmware_files(ar); | |
5e3dd157 KV |
693 | return ret; |
694 | } | |
695 | ||
1a222435 KV |
696 | static int ath10k_core_fetch_firmware_api_n(struct ath10k *ar, const char *name) |
697 | { | |
698 | size_t magic_len, len, ie_len; | |
699 | int ie_id, i, index, bit, ret; | |
700 | struct ath10k_fw_ie *hdr; | |
701 | const u8 *data; | |
202e86e6 | 702 | __le32 *timestamp, *version; |
1a222435 KV |
703 | |
704 | /* first fetch the firmware file (firmware-*.bin) */ | |
705 | ar->firmware = ath10k_fetch_fw_file(ar, ar->hw_params.fw.dir, name); | |
706 | if (IS_ERR(ar->firmware)) { | |
7aa7a72a | 707 | ath10k_err(ar, "could not fetch firmware file '%s/%s': %ld\n", |
53c02284 | 708 | ar->hw_params.fw.dir, name, PTR_ERR(ar->firmware)); |
1a222435 KV |
709 | return PTR_ERR(ar->firmware); |
710 | } | |
711 | ||
712 | data = ar->firmware->data; | |
713 | len = ar->firmware->size; | |
714 | ||
715 | /* magic also includes the null byte, check that as well */ | |
716 | magic_len = strlen(ATH10K_FIRMWARE_MAGIC) + 1; | |
717 | ||
718 | if (len < magic_len) { | |
7aa7a72a | 719 | ath10k_err(ar, "firmware file '%s/%s' too small to contain magic: %zu\n", |
53c02284 | 720 | ar->hw_params.fw.dir, name, len); |
9bab1cc0 MK |
721 | ret = -EINVAL; |
722 | goto err; | |
1a222435 KV |
723 | } |
724 | ||
725 | if (memcmp(data, ATH10K_FIRMWARE_MAGIC, magic_len) != 0) { | |
7aa7a72a | 726 | ath10k_err(ar, "invalid firmware magic\n"); |
9bab1cc0 MK |
727 | ret = -EINVAL; |
728 | goto err; | |
1a222435 KV |
729 | } |
730 | ||
731 | /* jump over the padding */ | |
732 | magic_len = ALIGN(magic_len, 4); | |
733 | ||
734 | len -= magic_len; | |
735 | data += magic_len; | |
736 | ||
737 | /* loop elements */ | |
738 | while (len > sizeof(struct ath10k_fw_ie)) { | |
739 | hdr = (struct ath10k_fw_ie *)data; | |
740 | ||
741 | ie_id = le32_to_cpu(hdr->id); | |
742 | ie_len = le32_to_cpu(hdr->len); | |
743 | ||
744 | len -= sizeof(*hdr); | |
745 | data += sizeof(*hdr); | |
746 | ||
747 | if (len < ie_len) { | |
7aa7a72a | 748 | ath10k_err(ar, "invalid length for FW IE %d (%zu < %zu)\n", |
1a222435 | 749 | ie_id, len, ie_len); |
9bab1cc0 MK |
750 | ret = -EINVAL; |
751 | goto err; | |
1a222435 KV |
752 | } |
753 | ||
754 | switch (ie_id) { | |
755 | case ATH10K_FW_IE_FW_VERSION: | |
756 | if (ie_len > sizeof(ar->hw->wiphy->fw_version) - 1) | |
757 | break; | |
758 | ||
759 | memcpy(ar->hw->wiphy->fw_version, data, ie_len); | |
760 | ar->hw->wiphy->fw_version[ie_len] = '\0'; | |
761 | ||
7aa7a72a | 762 | ath10k_dbg(ar, ATH10K_DBG_BOOT, |
1a222435 KV |
763 | "found fw version %s\n", |
764 | ar->hw->wiphy->fw_version); | |
765 | break; | |
766 | case ATH10K_FW_IE_TIMESTAMP: | |
767 | if (ie_len != sizeof(u32)) | |
768 | break; | |
769 | ||
770 | timestamp = (__le32 *)data; | |
771 | ||
7aa7a72a | 772 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw timestamp %d\n", |
1a222435 KV |
773 | le32_to_cpup(timestamp)); |
774 | break; | |
775 | case ATH10K_FW_IE_FEATURES: | |
7aa7a72a | 776 | ath10k_dbg(ar, ATH10K_DBG_BOOT, |
1a222435 KV |
777 | "found firmware features ie (%zd B)\n", |
778 | ie_len); | |
779 | ||
780 | for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) { | |
781 | index = i / 8; | |
782 | bit = i % 8; | |
783 | ||
784 | if (index == ie_len) | |
785 | break; | |
786 | ||
f591a1a5 | 787 | if (data[index] & (1 << bit)) { |
7aa7a72a | 788 | ath10k_dbg(ar, ATH10K_DBG_BOOT, |
f591a1a5 BG |
789 | "Enabling feature bit: %i\n", |
790 | i); | |
1a222435 | 791 | __set_bit(i, ar->fw_features); |
f591a1a5 | 792 | } |
1a222435 KV |
793 | } |
794 | ||
7aa7a72a | 795 | ath10k_dbg_dump(ar, ATH10K_DBG_BOOT, "features", "", |
1a222435 KV |
796 | ar->fw_features, |
797 | sizeof(ar->fw_features)); | |
798 | break; | |
799 | case ATH10K_FW_IE_FW_IMAGE: | |
7aa7a72a | 800 | ath10k_dbg(ar, ATH10K_DBG_BOOT, |
1a222435 KV |
801 | "found fw image ie (%zd B)\n", |
802 | ie_len); | |
803 | ||
804 | ar->firmware_data = data; | |
805 | ar->firmware_len = ie_len; | |
806 | ||
807 | break; | |
808 | case ATH10K_FW_IE_OTP_IMAGE: | |
7aa7a72a | 809 | ath10k_dbg(ar, ATH10K_DBG_BOOT, |
1a222435 KV |
810 | "found otp image ie (%zd B)\n", |
811 | ie_len); | |
812 | ||
813 | ar->otp_data = data; | |
814 | ar->otp_len = ie_len; | |
815 | ||
816 | break; | |
202e86e6 KV |
817 | case ATH10K_FW_IE_WMI_OP_VERSION: |
818 | if (ie_len != sizeof(u32)) | |
819 | break; | |
820 | ||
821 | version = (__le32 *)data; | |
822 | ||
823 | ar->wmi.op_version = le32_to_cpup(version); | |
824 | ||
825 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie wmi op version %d\n", | |
826 | ar->wmi.op_version); | |
827 | break; | |
8348db29 RM |
828 | case ATH10K_FW_IE_HTT_OP_VERSION: |
829 | if (ie_len != sizeof(u32)) | |
830 | break; | |
831 | ||
832 | version = (__le32 *)data; | |
833 | ||
834 | ar->htt.op_version = le32_to_cpup(version); | |
835 | ||
836 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie htt op version %d\n", | |
837 | ar->htt.op_version); | |
838 | break; | |
dcb02db1 VT |
839 | case ATH10K_FW_IE_FW_CODE_SWAP_IMAGE: |
840 | ath10k_dbg(ar, ATH10K_DBG_BOOT, | |
841 | "found fw code swap image ie (%zd B)\n", | |
842 | ie_len); | |
843 | ar->swap.firmware_codeswap_data = data; | |
844 | ar->swap.firmware_codeswap_len = ie_len; | |
845 | break; | |
1a222435 | 846 | default: |
7aa7a72a | 847 | ath10k_warn(ar, "Unknown FW IE: %u\n", |
1a222435 KV |
848 | le32_to_cpu(hdr->id)); |
849 | break; | |
850 | } | |
851 | ||
852 | /* jump over the padding */ | |
853 | ie_len = ALIGN(ie_len, 4); | |
854 | ||
855 | len -= ie_len; | |
856 | data += ie_len; | |
e05634ee | 857 | } |
1a222435 KV |
858 | |
859 | if (!ar->firmware_data || !ar->firmware_len) { | |
7aa7a72a | 860 | ath10k_warn(ar, "No ATH10K_FW_IE_FW_IMAGE found from '%s/%s', skipping\n", |
53c02284 | 861 | ar->hw_params.fw.dir, name); |
1a222435 KV |
862 | ret = -ENOMEDIUM; |
863 | goto err; | |
864 | } | |
865 | ||
1a222435 KV |
866 | return 0; |
867 | ||
868 | err: | |
869 | ath10k_core_free_firmware_files(ar); | |
870 | return ret; | |
871 | } | |
872 | ||
873 | static int ath10k_core_fetch_firmware_files(struct ath10k *ar) | |
874 | { | |
875 | int ret; | |
876 | ||
a58227ef KV |
877 | /* calibration file is optional, don't check for any errors */ |
878 | ath10k_fetch_cal_file(ar); | |
879 | ||
d0ed74f3 MK |
880 | ret = ath10k_core_fetch_board_file(ar); |
881 | if (ret) { | |
882 | ath10k_err(ar, "failed to fetch board file: %d\n", ret); | |
883 | return ret; | |
884 | } | |
885 | ||
53513c30 KV |
886 | ar->fw_api = 5; |
887 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api); | |
888 | ||
889 | ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API5_FILE); | |
890 | if (ret == 0) | |
891 | goto success; | |
892 | ||
4a16fbec RM |
893 | ar->fw_api = 4; |
894 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api); | |
895 | ||
896 | ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API4_FILE); | |
897 | if (ret == 0) | |
898 | goto success; | |
899 | ||
24c88f78 | 900 | ar->fw_api = 3; |
7aa7a72a | 901 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api); |
24c88f78 MK |
902 | |
903 | ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API3_FILE); | |
904 | if (ret == 0) | |
905 | goto success; | |
906 | ||
53c02284 | 907 | ar->fw_api = 2; |
7aa7a72a | 908 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api); |
53c02284 | 909 | |
1a222435 | 910 | ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API2_FILE); |
53c02284 BG |
911 | if (ret == 0) |
912 | goto success; | |
913 | ||
914 | ar->fw_api = 1; | |
7aa7a72a | 915 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api); |
1a222435 KV |
916 | |
917 | ret = ath10k_core_fetch_firmware_api_1(ar); | |
918 | if (ret) | |
919 | return ret; | |
920 | ||
53c02284 | 921 | success: |
7aa7a72a | 922 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "using fw api %d\n", ar->fw_api); |
1a222435 KV |
923 | |
924 | return 0; | |
925 | } | |
926 | ||
83091559 | 927 | static int ath10k_download_cal_data(struct ath10k *ar) |
5e3dd157 KV |
928 | { |
929 | int ret; | |
930 | ||
a58227ef KV |
931 | ret = ath10k_download_cal_file(ar); |
932 | if (ret == 0) { | |
933 | ar->cal_mode = ATH10K_CAL_MODE_FILE; | |
934 | goto done; | |
935 | } | |
936 | ||
937 | ath10k_dbg(ar, ATH10K_DBG_BOOT, | |
5aabff05 TK |
938 | "boot did not find a calibration file, try DT next: %d\n", |
939 | ret); | |
940 | ||
941 | ret = ath10k_download_cal_dt(ar); | |
942 | if (ret == 0) { | |
943 | ar->cal_mode = ATH10K_CAL_MODE_DT; | |
944 | goto done; | |
945 | } | |
946 | ||
947 | ath10k_dbg(ar, ATH10K_DBG_BOOT, | |
948 | "boot did not find DT entry, try OTP next: %d\n", | |
a58227ef KV |
949 | ret); |
950 | ||
5e3dd157 | 951 | ret = ath10k_download_and_run_otp(ar); |
36a8f413 | 952 | if (ret) { |
7aa7a72a | 953 | ath10k_err(ar, "failed to run otp: %d\n", ret); |
5e3dd157 | 954 | return ret; |
36a8f413 | 955 | } |
5e3dd157 | 956 | |
a58227ef KV |
957 | ar->cal_mode = ATH10K_CAL_MODE_OTP; |
958 | ||
959 | done: | |
960 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using calibration mode %s\n", | |
961 | ath10k_cal_mode_str(ar->cal_mode)); | |
962 | return 0; | |
5e3dd157 KV |
963 | } |
964 | ||
965 | static int ath10k_init_uart(struct ath10k *ar) | |
966 | { | |
967 | int ret; | |
968 | ||
969 | /* | |
970 | * Explicitly setting UART prints to zero as target turns it on | |
971 | * based on scratch registers. | |
972 | */ | |
973 | ret = ath10k_bmi_write32(ar, hi_serial_enable, 0); | |
974 | if (ret) { | |
7aa7a72a | 975 | ath10k_warn(ar, "could not disable UART prints (%d)\n", ret); |
5e3dd157 KV |
976 | return ret; |
977 | } | |
978 | ||
c8c39afe | 979 | if (!uart_print) |
5e3dd157 | 980 | return 0; |
5e3dd157 | 981 | |
3a8200b2 | 982 | ret = ath10k_bmi_write32(ar, hi_dbg_uart_txpin, ar->hw_params.uart_pin); |
5e3dd157 | 983 | if (ret) { |
7aa7a72a | 984 | ath10k_warn(ar, "could not enable UART prints (%d)\n", ret); |
5e3dd157 KV |
985 | return ret; |
986 | } | |
987 | ||
988 | ret = ath10k_bmi_write32(ar, hi_serial_enable, 1); | |
989 | if (ret) { | |
7aa7a72a | 990 | ath10k_warn(ar, "could not enable UART prints (%d)\n", ret); |
5e3dd157 KV |
991 | return ret; |
992 | } | |
993 | ||
03fc137b BM |
994 | /* Set the UART baud rate to 19200. */ |
995 | ret = ath10k_bmi_write32(ar, hi_desired_baud_rate, 19200); | |
996 | if (ret) { | |
7aa7a72a | 997 | ath10k_warn(ar, "could not set the baud rate (%d)\n", ret); |
03fc137b BM |
998 | return ret; |
999 | } | |
1000 | ||
7aa7a72a | 1001 | ath10k_info(ar, "UART prints enabled\n"); |
5e3dd157 KV |
1002 | return 0; |
1003 | } | |
1004 | ||
1005 | static int ath10k_init_hw_params(struct ath10k *ar) | |
1006 | { | |
1007 | const struct ath10k_hw_params *uninitialized_var(hw_params); | |
1008 | int i; | |
1009 | ||
1010 | for (i = 0; i < ARRAY_SIZE(ath10k_hw_params_list); i++) { | |
1011 | hw_params = &ath10k_hw_params_list[i]; | |
1012 | ||
1013 | if (hw_params->id == ar->target_version) | |
1014 | break; | |
1015 | } | |
1016 | ||
1017 | if (i == ARRAY_SIZE(ath10k_hw_params_list)) { | |
7aa7a72a | 1018 | ath10k_err(ar, "Unsupported hardware version: 0x%x\n", |
5e3dd157 KV |
1019 | ar->target_version); |
1020 | return -EINVAL; | |
1021 | } | |
1022 | ||
1023 | ar->hw_params = *hw_params; | |
1024 | ||
7aa7a72a | 1025 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "Hardware name %s version 0x%x\n", |
c8c39afe | 1026 | ar->hw_params.name, ar->target_version); |
5e3dd157 KV |
1027 | |
1028 | return 0; | |
1029 | } | |
1030 | ||
affd3217 MK |
1031 | static void ath10k_core_restart(struct work_struct *work) |
1032 | { | |
1033 | struct ath10k *ar = container_of(work, struct ath10k, restart_work); | |
1034 | ||
7962b0d8 MK |
1035 | set_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags); |
1036 | ||
1037 | /* Place a barrier to make sure the compiler doesn't reorder | |
1038 | * CRASH_FLUSH and calling other functions. | |
1039 | */ | |
1040 | barrier(); | |
1041 | ||
1042 | ieee80211_stop_queues(ar->hw); | |
1043 | ath10k_drain_tx(ar); | |
1044 | complete_all(&ar->scan.started); | |
1045 | complete_all(&ar->scan.completed); | |
1046 | complete_all(&ar->scan.on_channel); | |
1047 | complete_all(&ar->offchan_tx_completed); | |
1048 | complete_all(&ar->install_key_done); | |
1049 | complete_all(&ar->vdev_setup_done); | |
ac2953fc | 1050 | complete_all(&ar->thermal.wmi_sync); |
7962b0d8 MK |
1051 | wake_up(&ar->htt.empty_tx_wq); |
1052 | wake_up(&ar->wmi.tx_credits_wq); | |
1053 | wake_up(&ar->peer_mapping_wq); | |
1054 | ||
affd3217 MK |
1055 | mutex_lock(&ar->conf_mutex); |
1056 | ||
1057 | switch (ar->state) { | |
1058 | case ATH10K_STATE_ON: | |
affd3217 | 1059 | ar->state = ATH10K_STATE_RESTARTING; |
61e9aab7 | 1060 | ath10k_hif_stop(ar); |
5c81c7fd | 1061 | ath10k_scan_finish(ar); |
affd3217 MK |
1062 | ieee80211_restart_hw(ar->hw); |
1063 | break; | |
1064 | case ATH10K_STATE_OFF: | |
5e90de86 MK |
1065 | /* this can happen if driver is being unloaded |
1066 | * or if the crash happens during FW probing */ | |
7aa7a72a | 1067 | ath10k_warn(ar, "cannot restart a device that hasn't been started\n"); |
affd3217 MK |
1068 | break; |
1069 | case ATH10K_STATE_RESTARTING: | |
c5058f5b MK |
1070 | /* hw restart might be requested from multiple places */ |
1071 | break; | |
affd3217 MK |
1072 | case ATH10K_STATE_RESTARTED: |
1073 | ar->state = ATH10K_STATE_WEDGED; | |
1074 | /* fall through */ | |
1075 | case ATH10K_STATE_WEDGED: | |
7aa7a72a | 1076 | ath10k_warn(ar, "device is wedged, will not restart\n"); |
affd3217 | 1077 | break; |
43d2a30f KV |
1078 | case ATH10K_STATE_UTF: |
1079 | ath10k_warn(ar, "firmware restart in UTF mode not supported\n"); | |
1080 | break; | |
affd3217 MK |
1081 | } |
1082 | ||
1083 | mutex_unlock(&ar->conf_mutex); | |
1084 | } | |
1085 | ||
5f2144d9 | 1086 | static int ath10k_core_init_firmware_features(struct ath10k *ar) |
cfd1061e | 1087 | { |
5f2144d9 KV |
1088 | if (test_bit(ATH10K_FW_FEATURE_WMI_10_2, ar->fw_features) && |
1089 | !test_bit(ATH10K_FW_FEATURE_WMI_10X, ar->fw_features)) { | |
1090 | ath10k_err(ar, "feature bits corrupted: 10.2 feature requires 10.x feature to be set as well"); | |
1091 | return -EINVAL; | |
1092 | } | |
1093 | ||
202e86e6 KV |
1094 | if (ar->wmi.op_version >= ATH10K_FW_WMI_OP_VERSION_MAX) { |
1095 | ath10k_err(ar, "unsupported WMI OP version (max %d): %d\n", | |
1096 | ATH10K_FW_WMI_OP_VERSION_MAX, ar->wmi.op_version); | |
1097 | return -EINVAL; | |
1098 | } | |
1099 | ||
ccec9038 DL |
1100 | ar->wmi.rx_decap_mode = ATH10K_HW_TXRX_NATIVE_WIFI; |
1101 | switch (ath10k_cryptmode_param) { | |
1102 | case ATH10K_CRYPT_MODE_HW: | |
1103 | clear_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags); | |
1104 | clear_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags); | |
1105 | break; | |
1106 | case ATH10K_CRYPT_MODE_SW: | |
1107 | if (!test_bit(ATH10K_FW_FEATURE_RAW_MODE_SUPPORT, | |
1108 | ar->fw_features)) { | |
1109 | ath10k_err(ar, "cryptmode > 0 requires raw mode support from firmware"); | |
1110 | return -EINVAL; | |
1111 | } | |
1112 | ||
1113 | set_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags); | |
1114 | set_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags); | |
1115 | break; | |
1116 | default: | |
1117 | ath10k_info(ar, "invalid cryptmode: %d\n", | |
1118 | ath10k_cryptmode_param); | |
1119 | return -EINVAL; | |
1120 | } | |
1121 | ||
1122 | ar->htt.max_num_amsdu = ATH10K_HTT_MAX_NUM_AMSDU_DEFAULT; | |
1123 | ar->htt.max_num_ampdu = ATH10K_HTT_MAX_NUM_AMPDU_DEFAULT; | |
1124 | ||
1125 | if (test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) { | |
1126 | ar->wmi.rx_decap_mode = ATH10K_HW_TXRX_RAW; | |
1127 | ||
1128 | /* Workaround: | |
1129 | * | |
1130 | * Firmware A-MSDU aggregation breaks with RAW Tx encap mode | |
1131 | * and causes enormous performance issues (malformed frames, | |
1132 | * etc). | |
1133 | * | |
1134 | * Disabling A-MSDU makes RAW mode stable with heavy traffic | |
1135 | * albeit a bit slower compared to regular operation. | |
1136 | */ | |
1137 | ar->htt.max_num_amsdu = 1; | |
1138 | } | |
1139 | ||
202e86e6 KV |
1140 | /* Backwards compatibility for firmwares without |
1141 | * ATH10K_FW_IE_WMI_OP_VERSION. | |
1142 | */ | |
1143 | if (ar->wmi.op_version == ATH10K_FW_WMI_OP_VERSION_UNSET) { | |
1144 | if (test_bit(ATH10K_FW_FEATURE_WMI_10X, ar->fw_features)) { | |
4a16fbec RM |
1145 | if (test_bit(ATH10K_FW_FEATURE_WMI_10_2, |
1146 | ar->fw_features)) | |
202e86e6 KV |
1147 | ar->wmi.op_version = ATH10K_FW_WMI_OP_VERSION_10_2; |
1148 | else | |
1149 | ar->wmi.op_version = ATH10K_FW_WMI_OP_VERSION_10_1; | |
1150 | } else { | |
1151 | ar->wmi.op_version = ATH10K_FW_WMI_OP_VERSION_MAIN; | |
1152 | } | |
1153 | } | |
1154 | ||
1155 | switch (ar->wmi.op_version) { | |
1156 | case ATH10K_FW_WMI_OP_VERSION_MAIN: | |
cfd1061e MK |
1157 | ar->max_num_peers = TARGET_NUM_PEERS; |
1158 | ar->max_num_stations = TARGET_NUM_STATIONS; | |
30c78167 | 1159 | ar->max_num_vdevs = TARGET_NUM_VDEVS; |
91ad5f56 | 1160 | ar->htt.max_num_pending_tx = TARGET_NUM_MSDU_DESC; |
6274cd41 YL |
1161 | ar->fw_stats_req_mask = WMI_STAT_PDEV | WMI_STAT_VDEV | |
1162 | WMI_STAT_PEER; | |
5c8726ec | 1163 | ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM; |
202e86e6 KV |
1164 | break; |
1165 | case ATH10K_FW_WMI_OP_VERSION_10_1: | |
1166 | case ATH10K_FW_WMI_OP_VERSION_10_2: | |
4a16fbec | 1167 | case ATH10K_FW_WMI_OP_VERSION_10_2_4: |
202e86e6 KV |
1168 | ar->max_num_peers = TARGET_10X_NUM_PEERS; |
1169 | ar->max_num_stations = TARGET_10X_NUM_STATIONS; | |
30c78167 | 1170 | ar->max_num_vdevs = TARGET_10X_NUM_VDEVS; |
91ad5f56 | 1171 | ar->htt.max_num_pending_tx = TARGET_10X_NUM_MSDU_DESC; |
6274cd41 | 1172 | ar->fw_stats_req_mask = WMI_STAT_PEER; |
5c8726ec | 1173 | ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM; |
202e86e6 | 1174 | break; |
ca996ec5 MK |
1175 | case ATH10K_FW_WMI_OP_VERSION_TLV: |
1176 | ar->max_num_peers = TARGET_TLV_NUM_PEERS; | |
1177 | ar->max_num_stations = TARGET_TLV_NUM_STATIONS; | |
49274332 | 1178 | ar->max_num_vdevs = TARGET_TLV_NUM_VDEVS; |
8cca3d60 | 1179 | ar->max_num_tdls_vdevs = TARGET_TLV_NUM_TDLS_VDEVS; |
ca996ec5 | 1180 | ar->htt.max_num_pending_tx = TARGET_TLV_NUM_MSDU_DESC; |
25c86619 | 1181 | ar->wow.max_num_patterns = TARGET_TLV_NUM_WOW_PATTERNS; |
6274cd41 YL |
1182 | ar->fw_stats_req_mask = WMI_STAT_PDEV | WMI_STAT_VDEV | |
1183 | WMI_STAT_PEER; | |
5c8726ec | 1184 | ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM; |
ca996ec5 | 1185 | break; |
9bd21322 | 1186 | case ATH10K_FW_WMI_OP_VERSION_10_4: |
d1e52a8e RM |
1187 | ar->max_num_peers = TARGET_10_4_NUM_PEERS; |
1188 | ar->max_num_stations = TARGET_10_4_NUM_STATIONS; | |
1189 | ar->num_active_peers = TARGET_10_4_ACTIVE_PEERS; | |
1190 | ar->max_num_vdevs = TARGET_10_4_NUM_VDEVS; | |
1191 | ar->num_tids = TARGET_10_4_TGT_NUM_TIDS; | |
721ad3ca | 1192 | ar->htt.max_num_pending_tx = TARGET_10_4_NUM_MSDU_DESC; |
d1e52a8e | 1193 | ar->fw_stats_req_mask = WMI_STAT_PEER; |
5c8726ec | 1194 | ar->max_spatial_stream = WMI_10_4_MAX_SPATIAL_STREAM; |
d1e52a8e | 1195 | break; |
202e86e6 KV |
1196 | case ATH10K_FW_WMI_OP_VERSION_UNSET: |
1197 | case ATH10K_FW_WMI_OP_VERSION_MAX: | |
1198 | WARN_ON(1); | |
1199 | return -EINVAL; | |
cfd1061e | 1200 | } |
5f2144d9 | 1201 | |
dc3632a1 KV |
1202 | /* Backwards compatibility for firmwares without |
1203 | * ATH10K_FW_IE_HTT_OP_VERSION. | |
1204 | */ | |
1205 | if (ar->htt.op_version == ATH10K_FW_HTT_OP_VERSION_UNSET) { | |
1206 | switch (ar->wmi.op_version) { | |
1207 | case ATH10K_FW_WMI_OP_VERSION_MAIN: | |
1208 | ar->htt.op_version = ATH10K_FW_HTT_OP_VERSION_MAIN; | |
1209 | break; | |
1210 | case ATH10K_FW_WMI_OP_VERSION_10_1: | |
1211 | case ATH10K_FW_WMI_OP_VERSION_10_2: | |
1212 | case ATH10K_FW_WMI_OP_VERSION_10_2_4: | |
1213 | ar->htt.op_version = ATH10K_FW_HTT_OP_VERSION_10_1; | |
1214 | break; | |
1215 | case ATH10K_FW_WMI_OP_VERSION_TLV: | |
1216 | ar->htt.op_version = ATH10K_FW_HTT_OP_VERSION_TLV; | |
1217 | break; | |
9bd21322 | 1218 | case ATH10K_FW_WMI_OP_VERSION_10_4: |
dc3632a1 KV |
1219 | case ATH10K_FW_WMI_OP_VERSION_UNSET: |
1220 | case ATH10K_FW_WMI_OP_VERSION_MAX: | |
1221 | WARN_ON(1); | |
1222 | return -EINVAL; | |
1223 | } | |
1224 | } | |
1225 | ||
5f2144d9 | 1226 | return 0; |
cfd1061e MK |
1227 | } |
1228 | ||
43d2a30f | 1229 | int ath10k_core_start(struct ath10k *ar, enum ath10k_firmware_mode mode) |
5e3dd157 | 1230 | { |
5e3dd157 KV |
1231 | int status; |
1232 | ||
60631c5c KV |
1233 | lockdep_assert_held(&ar->conf_mutex); |
1234 | ||
7962b0d8 MK |
1235 | clear_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags); |
1236 | ||
64d151d4 MK |
1237 | ath10k_bmi_start(ar); |
1238 | ||
5e3dd157 KV |
1239 | if (ath10k_init_configure_target(ar)) { |
1240 | status = -EINVAL; | |
1241 | goto err; | |
1242 | } | |
1243 | ||
83091559 KV |
1244 | status = ath10k_download_cal_data(ar); |
1245 | if (status) | |
1246 | goto err; | |
1247 | ||
163f5264 RM |
1248 | /* Some of of qca988x solutions are having global reset issue |
1249 | * during target initialization. Bypassing PLL setting before | |
1250 | * downloading firmware and letting the SoC run on REF_CLK is | |
1251 | * fixing the problem. Corresponding firmware change is also needed | |
1252 | * to set the clock source once the target is initialized. | |
1253 | */ | |
1254 | if (test_bit(ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT, | |
1255 | ar->fw_features)) { | |
1256 | status = ath10k_bmi_write32(ar, hi_skip_clock_init, 1); | |
1257 | if (status) { | |
1258 | ath10k_err(ar, "could not write to skip_clock_init: %d\n", | |
1259 | status); | |
1260 | goto err; | |
1261 | } | |
1262 | } | |
1263 | ||
83091559 | 1264 | status = ath10k_download_fw(ar, mode); |
5e3dd157 KV |
1265 | if (status) |
1266 | goto err; | |
1267 | ||
1268 | status = ath10k_init_uart(ar); | |
1269 | if (status) | |
1270 | goto err; | |
1271 | ||
cd003fad MK |
1272 | ar->htc.htc_ops.target_send_suspend_complete = |
1273 | ath10k_send_suspend_complete; | |
5e3dd157 | 1274 | |
cd003fad MK |
1275 | status = ath10k_htc_init(ar); |
1276 | if (status) { | |
7aa7a72a | 1277 | ath10k_err(ar, "could not init HTC (%d)\n", status); |
5e3dd157 KV |
1278 | goto err; |
1279 | } | |
1280 | ||
1281 | status = ath10k_bmi_done(ar); | |
1282 | if (status) | |
cd003fad | 1283 | goto err; |
5e3dd157 KV |
1284 | |
1285 | status = ath10k_wmi_attach(ar); | |
1286 | if (status) { | |
7aa7a72a | 1287 | ath10k_err(ar, "WMI attach failed: %d\n", status); |
cd003fad | 1288 | goto err; |
5e3dd157 KV |
1289 | } |
1290 | ||
95bf21f9 MK |
1291 | status = ath10k_htt_init(ar); |
1292 | if (status) { | |
7aa7a72a | 1293 | ath10k_err(ar, "failed to init htt: %d\n", status); |
95bf21f9 MK |
1294 | goto err_wmi_detach; |
1295 | } | |
1296 | ||
1297 | status = ath10k_htt_tx_alloc(&ar->htt); | |
1298 | if (status) { | |
7aa7a72a | 1299 | ath10k_err(ar, "failed to alloc htt tx: %d\n", status); |
95bf21f9 MK |
1300 | goto err_wmi_detach; |
1301 | } | |
1302 | ||
1303 | status = ath10k_htt_rx_alloc(&ar->htt); | |
1304 | if (status) { | |
7aa7a72a | 1305 | ath10k_err(ar, "failed to alloc htt rx: %d\n", status); |
95bf21f9 MK |
1306 | goto err_htt_tx_detach; |
1307 | } | |
1308 | ||
67e3c63f MK |
1309 | status = ath10k_hif_start(ar); |
1310 | if (status) { | |
7aa7a72a | 1311 | ath10k_err(ar, "could not start HIF: %d\n", status); |
95bf21f9 | 1312 | goto err_htt_rx_detach; |
67e3c63f MK |
1313 | } |
1314 | ||
1315 | status = ath10k_htc_wait_target(&ar->htc); | |
1316 | if (status) { | |
7aa7a72a | 1317 | ath10k_err(ar, "failed to connect to HTC: %d\n", status); |
67e3c63f MK |
1318 | goto err_hif_stop; |
1319 | } | |
5e3dd157 | 1320 | |
43d2a30f KV |
1321 | if (mode == ATH10K_FIRMWARE_MODE_NORMAL) { |
1322 | status = ath10k_htt_connect(&ar->htt); | |
1323 | if (status) { | |
1324 | ath10k_err(ar, "failed to connect htt (%d)\n", status); | |
1325 | goto err_hif_stop; | |
1326 | } | |
5e3dd157 KV |
1327 | } |
1328 | ||
95bf21f9 MK |
1329 | status = ath10k_wmi_connect(ar); |
1330 | if (status) { | |
7aa7a72a | 1331 | ath10k_err(ar, "could not connect wmi: %d\n", status); |
95bf21f9 MK |
1332 | goto err_hif_stop; |
1333 | } | |
1334 | ||
1335 | status = ath10k_htc_start(&ar->htc); | |
1336 | if (status) { | |
7aa7a72a | 1337 | ath10k_err(ar, "failed to start htc: %d\n", status); |
95bf21f9 MK |
1338 | goto err_hif_stop; |
1339 | } | |
1340 | ||
43d2a30f KV |
1341 | if (mode == ATH10K_FIRMWARE_MODE_NORMAL) { |
1342 | status = ath10k_wmi_wait_for_service_ready(ar); | |
9eea5689 | 1343 | if (status) { |
43d2a30f | 1344 | ath10k_warn(ar, "wmi service ready event not received"); |
43d2a30f KV |
1345 | goto err_hif_stop; |
1346 | } | |
95bf21f9 | 1347 | } |
5e3dd157 | 1348 | |
7aa7a72a | 1349 | ath10k_dbg(ar, ATH10K_DBG_BOOT, "firmware %s booted\n", |
c8c39afe | 1350 | ar->hw->wiphy->fw_version); |
5e3dd157 | 1351 | |
5e3dd157 KV |
1352 | status = ath10k_wmi_cmd_init(ar); |
1353 | if (status) { | |
7aa7a72a MK |
1354 | ath10k_err(ar, "could not send WMI init command (%d)\n", |
1355 | status); | |
b7967dc7 | 1356 | goto err_hif_stop; |
5e3dd157 KV |
1357 | } |
1358 | ||
1359 | status = ath10k_wmi_wait_for_unified_ready(ar); | |
9eea5689 | 1360 | if (status) { |
7aa7a72a | 1361 | ath10k_err(ar, "wmi unified ready event not received\n"); |
b7967dc7 | 1362 | goto err_hif_stop; |
5e3dd157 KV |
1363 | } |
1364 | ||
c545070e MK |
1365 | /* If firmware indicates Full Rx Reorder support it must be used in a |
1366 | * slightly different manner. Let HTT code know. | |
1367 | */ | |
1368 | ar->htt.rx_ring.in_ord_rx = !!(test_bit(WMI_SERVICE_RX_FULL_REORDER, | |
1369 | ar->wmi.svc_map)); | |
1370 | ||
1371 | status = ath10k_htt_rx_ring_refill(ar); | |
1372 | if (status) { | |
1373 | ath10k_err(ar, "failed to refill htt rx ring: %d\n", status); | |
1374 | goto err_hif_stop; | |
1375 | } | |
1376 | ||
43d2a30f KV |
1377 | /* we don't care about HTT in UTF mode */ |
1378 | if (mode == ATH10K_FIRMWARE_MODE_NORMAL) { | |
1379 | status = ath10k_htt_setup(&ar->htt); | |
1380 | if (status) { | |
1381 | ath10k_err(ar, "failed to setup htt: %d\n", status); | |
1382 | goto err_hif_stop; | |
1383 | } | |
95bf21f9 | 1384 | } |
5e3dd157 | 1385 | |
db66ea04 KV |
1386 | status = ath10k_debug_start(ar); |
1387 | if (status) | |
b7967dc7 | 1388 | goto err_hif_stop; |
db66ea04 | 1389 | |
30c78167 | 1390 | ar->free_vdev_map = (1LL << ar->max_num_vdevs) - 1; |
dfa413de | 1391 | |
0579119f | 1392 | INIT_LIST_HEAD(&ar->arvifs); |
1a1b8a88 | 1393 | |
dd30a36e MK |
1394 | return 0; |
1395 | ||
67e3c63f MK |
1396 | err_hif_stop: |
1397 | ath10k_hif_stop(ar); | |
95bf21f9 MK |
1398 | err_htt_rx_detach: |
1399 | ath10k_htt_rx_free(&ar->htt); | |
1400 | err_htt_tx_detach: | |
1401 | ath10k_htt_tx_free(&ar->htt); | |
dd30a36e MK |
1402 | err_wmi_detach: |
1403 | ath10k_wmi_detach(ar); | |
1404 | err: | |
1405 | return status; | |
1406 | } | |
818bdd16 | 1407 | EXPORT_SYMBOL(ath10k_core_start); |
dd30a36e | 1408 | |
00f5482b MP |
1409 | int ath10k_wait_for_suspend(struct ath10k *ar, u32 suspend_opt) |
1410 | { | |
1411 | int ret; | |
a7a42849 | 1412 | unsigned long time_left; |
00f5482b MP |
1413 | |
1414 | reinit_completion(&ar->target_suspend); | |
1415 | ||
1416 | ret = ath10k_wmi_pdev_suspend_target(ar, suspend_opt); | |
1417 | if (ret) { | |
7aa7a72a | 1418 | ath10k_warn(ar, "could not suspend target (%d)\n", ret); |
00f5482b MP |
1419 | return ret; |
1420 | } | |
1421 | ||
a7a42849 | 1422 | time_left = wait_for_completion_timeout(&ar->target_suspend, 1 * HZ); |
00f5482b | 1423 | |
a7a42849 | 1424 | if (!time_left) { |
7aa7a72a | 1425 | ath10k_warn(ar, "suspend timed out - target pause event never came\n"); |
00f5482b MP |
1426 | return -ETIMEDOUT; |
1427 | } | |
1428 | ||
1429 | return 0; | |
1430 | } | |
1431 | ||
dd30a36e MK |
1432 | void ath10k_core_stop(struct ath10k *ar) |
1433 | { | |
60631c5c | 1434 | lockdep_assert_held(&ar->conf_mutex); |
f1ee2682 | 1435 | ath10k_debug_stop(ar); |
60631c5c | 1436 | |
00f5482b | 1437 | /* try to suspend target */ |
43d2a30f KV |
1438 | if (ar->state != ATH10K_STATE_RESTARTING && |
1439 | ar->state != ATH10K_STATE_UTF) | |
216a1836 MK |
1440 | ath10k_wait_for_suspend(ar, WMI_PDEV_SUSPEND_AND_DISABLE_INTR); |
1441 | ||
95bf21f9 MK |
1442 | ath10k_hif_stop(ar); |
1443 | ath10k_htt_tx_free(&ar->htt); | |
1444 | ath10k_htt_rx_free(&ar->htt); | |
dd30a36e MK |
1445 | ath10k_wmi_detach(ar); |
1446 | } | |
818bdd16 MK |
1447 | EXPORT_SYMBOL(ath10k_core_stop); |
1448 | ||
1449 | /* mac80211 manages fw/hw initialization through start/stop hooks. However in | |
1450 | * order to know what hw capabilities should be advertised to mac80211 it is | |
1451 | * necessary to load the firmware (and tear it down immediately since start | |
1452 | * hook will try to init it again) before registering */ | |
1453 | static int ath10k_core_probe_fw(struct ath10k *ar) | |
1454 | { | |
29385057 MK |
1455 | struct bmi_target_info target_info; |
1456 | int ret = 0; | |
818bdd16 MK |
1457 | |
1458 | ret = ath10k_hif_power_up(ar); | |
1459 | if (ret) { | |
7aa7a72a | 1460 | ath10k_err(ar, "could not start pci hif (%d)\n", ret); |
818bdd16 MK |
1461 | return ret; |
1462 | } | |
1463 | ||
29385057 MK |
1464 | memset(&target_info, 0, sizeof(target_info)); |
1465 | ret = ath10k_bmi_get_target_info(ar, &target_info); | |
1466 | if (ret) { | |
7aa7a72a | 1467 | ath10k_err(ar, "could not get target info (%d)\n", ret); |
c6ce492d | 1468 | goto err_power_down; |
29385057 MK |
1469 | } |
1470 | ||
1471 | ar->target_version = target_info.version; | |
1472 | ar->hw->wiphy->hw_version = target_info.version; | |
1473 | ||
1474 | ret = ath10k_init_hw_params(ar); | |
1475 | if (ret) { | |
7aa7a72a | 1476 | ath10k_err(ar, "could not get hw params (%d)\n", ret); |
c6ce492d | 1477 | goto err_power_down; |
29385057 MK |
1478 | } |
1479 | ||
1480 | ret = ath10k_core_fetch_firmware_files(ar); | |
1481 | if (ret) { | |
7aa7a72a | 1482 | ath10k_err(ar, "could not fetch firmware files (%d)\n", ret); |
c6ce492d | 1483 | goto err_power_down; |
29385057 MK |
1484 | } |
1485 | ||
5f2144d9 KV |
1486 | ret = ath10k_core_init_firmware_features(ar); |
1487 | if (ret) { | |
1488 | ath10k_err(ar, "fatal problem with firmware features: %d\n", | |
1489 | ret); | |
1490 | goto err_free_firmware_files; | |
1491 | } | |
cfd1061e | 1492 | |
dcb02db1 VT |
1493 | ret = ath10k_swap_code_seg_init(ar); |
1494 | if (ret) { | |
1495 | ath10k_err(ar, "failed to initialize code swap segment: %d\n", | |
1496 | ret); | |
1497 | goto err_free_firmware_files; | |
1498 | } | |
1499 | ||
60631c5c KV |
1500 | mutex_lock(&ar->conf_mutex); |
1501 | ||
43d2a30f | 1502 | ret = ath10k_core_start(ar, ATH10K_FIRMWARE_MODE_NORMAL); |
818bdd16 | 1503 | if (ret) { |
7aa7a72a | 1504 | ath10k_err(ar, "could not init core (%d)\n", ret); |
c6ce492d | 1505 | goto err_unlock; |
818bdd16 MK |
1506 | } |
1507 | ||
8079de0d | 1508 | ath10k_print_driver_info(ar); |
818bdd16 | 1509 | ath10k_core_stop(ar); |
60631c5c KV |
1510 | |
1511 | mutex_unlock(&ar->conf_mutex); | |
1512 | ||
818bdd16 MK |
1513 | ath10k_hif_power_down(ar); |
1514 | return 0; | |
c6ce492d KV |
1515 | |
1516 | err_unlock: | |
1517 | mutex_unlock(&ar->conf_mutex); | |
1518 | ||
5f2144d9 | 1519 | err_free_firmware_files: |
c6ce492d KV |
1520 | ath10k_core_free_firmware_files(ar); |
1521 | ||
1522 | err_power_down: | |
1523 | ath10k_hif_power_down(ar); | |
1524 | ||
1525 | return ret; | |
818bdd16 | 1526 | } |
dd30a36e | 1527 | |
6782cb69 | 1528 | static void ath10k_core_register_work(struct work_struct *work) |
dd30a36e | 1529 | { |
6782cb69 | 1530 | struct ath10k *ar = container_of(work, struct ath10k, register_work); |
dd30a36e MK |
1531 | int status; |
1532 | ||
818bdd16 MK |
1533 | status = ath10k_core_probe_fw(ar); |
1534 | if (status) { | |
7aa7a72a | 1535 | ath10k_err(ar, "could not probe fw (%d)\n", status); |
6782cb69 | 1536 | goto err; |
818bdd16 | 1537 | } |
dd30a36e | 1538 | |
5e3dd157 | 1539 | status = ath10k_mac_register(ar); |
818bdd16 | 1540 | if (status) { |
7aa7a72a | 1541 | ath10k_err(ar, "could not register to mac80211 (%d)\n", status); |
29385057 | 1542 | goto err_release_fw; |
818bdd16 | 1543 | } |
5e3dd157 | 1544 | |
e13cf7a3 | 1545 | status = ath10k_debug_register(ar); |
5e3dd157 | 1546 | if (status) { |
7aa7a72a | 1547 | ath10k_err(ar, "unable to initialize debugfs\n"); |
5e3dd157 KV |
1548 | goto err_unregister_mac; |
1549 | } | |
1550 | ||
855aed12 SW |
1551 | status = ath10k_spectral_create(ar); |
1552 | if (status) { | |
7aa7a72a | 1553 | ath10k_err(ar, "failed to initialize spectral\n"); |
855aed12 SW |
1554 | goto err_debug_destroy; |
1555 | } | |
1556 | ||
fe6f36d6 RM |
1557 | status = ath10k_thermal_register(ar); |
1558 | if (status) { | |
1559 | ath10k_err(ar, "could not register thermal device: %d\n", | |
1560 | status); | |
1561 | goto err_spectral_destroy; | |
1562 | } | |
1563 | ||
6782cb69 MK |
1564 | set_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags); |
1565 | return; | |
5e3dd157 | 1566 | |
fe6f36d6 RM |
1567 | err_spectral_destroy: |
1568 | ath10k_spectral_destroy(ar); | |
855aed12 SW |
1569 | err_debug_destroy: |
1570 | ath10k_debug_destroy(ar); | |
5e3dd157 KV |
1571 | err_unregister_mac: |
1572 | ath10k_mac_unregister(ar); | |
29385057 MK |
1573 | err_release_fw: |
1574 | ath10k_core_free_firmware_files(ar); | |
6782cb69 | 1575 | err: |
a491a920 MK |
1576 | /* TODO: It's probably a good idea to release device from the driver |
1577 | * but calling device_release_driver() here will cause a deadlock. | |
1578 | */ | |
6782cb69 MK |
1579 | return; |
1580 | } | |
1581 | ||
1582 | int ath10k_core_register(struct ath10k *ar, u32 chip_id) | |
1583 | { | |
6782cb69 | 1584 | ar->chip_id = chip_id; |
6782cb69 MK |
1585 | queue_work(ar->workqueue, &ar->register_work); |
1586 | ||
1587 | return 0; | |
5e3dd157 KV |
1588 | } |
1589 | EXPORT_SYMBOL(ath10k_core_register); | |
1590 | ||
1591 | void ath10k_core_unregister(struct ath10k *ar) | |
1592 | { | |
6782cb69 MK |
1593 | cancel_work_sync(&ar->register_work); |
1594 | ||
1595 | if (!test_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags)) | |
1596 | return; | |
1597 | ||
fe6f36d6 | 1598 | ath10k_thermal_unregister(ar); |
804eef14 SW |
1599 | /* Stop spectral before unregistering from mac80211 to remove the |
1600 | * relayfs debugfs file cleanly. Otherwise the parent debugfs tree | |
1601 | * would be already be free'd recursively, leading to a double free. | |
1602 | */ | |
1603 | ath10k_spectral_destroy(ar); | |
1604 | ||
5e3dd157 KV |
1605 | /* We must unregister from mac80211 before we stop HTC and HIF. |
1606 | * Otherwise we will fail to submit commands to FW and mac80211 will be | |
1607 | * unhappy about callback failures. */ | |
1608 | ath10k_mac_unregister(ar); | |
db66ea04 | 1609 | |
43d2a30f KV |
1610 | ath10k_testmode_destroy(ar); |
1611 | ||
29385057 | 1612 | ath10k_core_free_firmware_files(ar); |
6f1f56ea | 1613 | |
e13cf7a3 | 1614 | ath10k_debug_unregister(ar); |
5e3dd157 KV |
1615 | } |
1616 | EXPORT_SYMBOL(ath10k_core_unregister); | |
1617 | ||
e7b54194 | 1618 | struct ath10k *ath10k_core_create(size_t priv_size, struct device *dev, |
e07db352 | 1619 | enum ath10k_bus bus, |
d63955b3 | 1620 | enum ath10k_hw_rev hw_rev, |
0d0a6939 MK |
1621 | const struct ath10k_hif_ops *hif_ops) |
1622 | { | |
1623 | struct ath10k *ar; | |
e13cf7a3 | 1624 | int ret; |
0d0a6939 | 1625 | |
e7b54194 | 1626 | ar = ath10k_mac_create(priv_size); |
0d0a6939 MK |
1627 | if (!ar) |
1628 | return NULL; | |
1629 | ||
1630 | ar->ath_common.priv = ar; | |
1631 | ar->ath_common.hw = ar->hw; | |
0d0a6939 | 1632 | ar->dev = dev; |
d63955b3 | 1633 | ar->hw_rev = hw_rev; |
0d0a6939 | 1634 | ar->hif.ops = hif_ops; |
e07db352 | 1635 | ar->hif.bus = bus; |
0d0a6939 | 1636 | |
d63955b3 MK |
1637 | switch (hw_rev) { |
1638 | case ATH10K_HW_QCA988X: | |
1639 | ar->regs = &qca988x_regs; | |
2f2cfc4a | 1640 | ar->hw_values = &qca988x_values; |
d63955b3 MK |
1641 | break; |
1642 | case ATH10K_HW_QCA6174: | |
1643 | ar->regs = &qca6174_regs; | |
2f2cfc4a | 1644 | ar->hw_values = &qca6174_values; |
d63955b3 | 1645 | break; |
8bd47021 VT |
1646 | case ATH10K_HW_QCA99X0: |
1647 | ar->regs = &qca99x0_regs; | |
1648 | ar->hw_values = &qca99x0_values; | |
1649 | break; | |
d63955b3 MK |
1650 | default: |
1651 | ath10k_err(ar, "unsupported core hardware revision %d\n", | |
1652 | hw_rev); | |
1653 | ret = -ENOTSUPP; | |
1654 | goto err_free_mac; | |
1655 | } | |
1656 | ||
0d0a6939 MK |
1657 | init_completion(&ar->scan.started); |
1658 | init_completion(&ar->scan.completed); | |
1659 | init_completion(&ar->scan.on_channel); | |
1660 | init_completion(&ar->target_suspend); | |
5fd3ac3c | 1661 | init_completion(&ar->wow.wakeup_completed); |
0d0a6939 MK |
1662 | |
1663 | init_completion(&ar->install_key_done); | |
1664 | init_completion(&ar->vdev_setup_done); | |
ac2953fc | 1665 | init_completion(&ar->thermal.wmi_sync); |
0d0a6939 | 1666 | |
5c81c7fd | 1667 | INIT_DELAYED_WORK(&ar->scan.timeout, ath10k_scan_timeout_work); |
0d0a6939 MK |
1668 | |
1669 | ar->workqueue = create_singlethread_workqueue("ath10k_wq"); | |
1670 | if (!ar->workqueue) | |
e13cf7a3 | 1671 | goto err_free_mac; |
0d0a6939 | 1672 | |
c8ecfc1c RM |
1673 | ar->workqueue_aux = create_singlethread_workqueue("ath10k_aux_wq"); |
1674 | if (!ar->workqueue_aux) | |
1675 | goto err_free_wq; | |
1676 | ||
0d0a6939 MK |
1677 | mutex_init(&ar->conf_mutex); |
1678 | spin_lock_init(&ar->data_lock); | |
1679 | ||
1680 | INIT_LIST_HEAD(&ar->peers); | |
1681 | init_waitqueue_head(&ar->peer_mapping_wq); | |
7962b0d8 MK |
1682 | init_waitqueue_head(&ar->htt.empty_tx_wq); |
1683 | init_waitqueue_head(&ar->wmi.tx_credits_wq); | |
0d0a6939 MK |
1684 | |
1685 | init_completion(&ar->offchan_tx_completed); | |
1686 | INIT_WORK(&ar->offchan_tx_work, ath10k_offchan_tx_work); | |
1687 | skb_queue_head_init(&ar->offchan_tx_queue); | |
1688 | ||
1689 | INIT_WORK(&ar->wmi_mgmt_tx_work, ath10k_mgmt_over_wmi_tx_work); | |
1690 | skb_queue_head_init(&ar->wmi_mgmt_tx_queue); | |
1691 | ||
6782cb69 | 1692 | INIT_WORK(&ar->register_work, ath10k_core_register_work); |
0d0a6939 MK |
1693 | INIT_WORK(&ar->restart_work, ath10k_core_restart); |
1694 | ||
e13cf7a3 MK |
1695 | ret = ath10k_debug_create(ar); |
1696 | if (ret) | |
c8ecfc1c | 1697 | goto err_free_aux_wq; |
e13cf7a3 | 1698 | |
0d0a6939 MK |
1699 | return ar; |
1700 | ||
c8ecfc1c RM |
1701 | err_free_aux_wq: |
1702 | destroy_workqueue(ar->workqueue_aux); | |
e13cf7a3 MK |
1703 | err_free_wq: |
1704 | destroy_workqueue(ar->workqueue); | |
1705 | ||
1706 | err_free_mac: | |
0d0a6939 | 1707 | ath10k_mac_destroy(ar); |
e13cf7a3 | 1708 | |
0d0a6939 MK |
1709 | return NULL; |
1710 | } | |
1711 | EXPORT_SYMBOL(ath10k_core_create); | |
1712 | ||
1713 | void ath10k_core_destroy(struct ath10k *ar) | |
1714 | { | |
1715 | flush_workqueue(ar->workqueue); | |
1716 | destroy_workqueue(ar->workqueue); | |
1717 | ||
c8ecfc1c RM |
1718 | flush_workqueue(ar->workqueue_aux); |
1719 | destroy_workqueue(ar->workqueue_aux); | |
1720 | ||
e13cf7a3 | 1721 | ath10k_debug_destroy(ar); |
a925a376 | 1722 | ath10k_wmi_free_host_mem(ar); |
0d0a6939 MK |
1723 | ath10k_mac_destroy(ar); |
1724 | } | |
1725 | EXPORT_SYMBOL(ath10k_core_destroy); | |
1726 | ||
5e3dd157 KV |
1727 | MODULE_AUTHOR("Qualcomm Atheros"); |
1728 | MODULE_DESCRIPTION("Core module for QCA988X PCIe devices."); | |
1729 | MODULE_LICENSE("Dual BSD/GPL"); |