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f0553ca9 | 1 | /* SPDX-License-Identifier: ISC */ |
5e3dd157 KV |
2 | /* |
3 | * Copyright (c) 2005-2011 Atheros Communications Inc. | |
8b1083d6 | 4 | * Copyright (c) 2011-2017 Qualcomm Atheros, Inc. |
fe36e70f | 5 | * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. |
5e3dd157 KV |
6 | */ |
7 | ||
8 | #ifndef _CORE_H_ | |
9 | #define _CORE_H_ | |
10 | ||
11 | #include <linux/completion.h> | |
12 | #include <linux/if_ether.h> | |
13 | #include <linux/types.h> | |
14 | #include <linux/pci.h> | |
384914b2 BG |
15 | #include <linux/uuid.h> |
16 | #include <linux/time.h> | |
5e3dd157 | 17 | |
edb8236d | 18 | #include "htt.h" |
5e3dd157 KV |
19 | #include "htc.h" |
20 | #include "hw.h" | |
21 | #include "targaddrs.h" | |
22 | #include "wmi.h" | |
23 | #include "../ath.h" | |
24 | #include "../regd.h" | |
9702c686 | 25 | #include "../dfs_pattern_detector.h" |
855aed12 | 26 | #include "spectral.h" |
fe6f36d6 | 27 | #include "thermal.h" |
5fd3ac3c | 28 | #include "wow.h" |
dcb02db1 | 29 | #include "swap.h" |
5e3dd157 KV |
30 | |
31 | #define MS(_v, _f) (((_v) & _f##_MASK) >> _f##_LSB) | |
32 | #define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK) | |
33 | #define WO(_f) ((_f##_OFFSET) >> 2) | |
34 | ||
35 | #define ATH10K_SCAN_ID 0 | |
be8cce96 | 36 | #define ATH10K_SCAN_CHANNEL_SWITCH_WMI_EVT_OVERHEAD 10 /* msec */ |
5e3dd157 | 37 | #define WMI_READY_TIMEOUT (5 * HZ) |
14e105cd KV |
38 | #define ATH10K_FLUSH_TIMEOUT_HZ (5 * HZ) |
39 | #define ATH10K_CONNECTION_LOSS_HZ (3 * HZ) | |
38441fb6 BG |
40 | #define ATH10K_NUM_CHANS 41 |
41 | #define ATH10K_MAX_5G_CHAN 173 | |
5e3dd157 KV |
42 | |
43 | /* Antenna noise floor */ | |
44 | #define ATH10K_DEFAULT_NOISE_FLOOR -95 | |
45 | ||
235b9c42 VN |
46 | #define ATH10K_INVALID_RSSI 128 |
47 | ||
71098615 | 48 | #define ATH10K_MAX_NUM_MGMT_PENDING 128 |
5e00d31a | 49 | |
4705e34e RM |
50 | /* number of failed packets (20 packets with 16 sw reties each) */ |
51 | #define ATH10K_KICKOUT_THRESHOLD (20 * 16) | |
5a13e76e KV |
52 | |
53 | /* | |
54 | * Use insanely high numbers to make sure that the firmware implementation | |
55 | * won't start, we have the same functionality already in hostapd. Unit | |
56 | * is seconds. | |
57 | */ | |
58 | #define ATH10K_KEEPALIVE_MIN_IDLE 3747 | |
59 | #define ATH10K_KEEPALIVE_MAX_IDLE 3895 | |
60 | #define ATH10K_KEEPALIVE_MAX_UNRESPONSIVE 3900 | |
61 | ||
3c97f5de RM |
62 | /* NAPI poll budget */ |
63 | #define ATH10K_NAPI_BUDGET 64 | |
3c97f5de | 64 | |
1657b8f8 WR |
65 | /* SMBIOS type containing Board Data File Name Extension */ |
66 | #define ATH10K_SMBIOS_BDF_EXT_TYPE 0xF8 | |
67 | ||
68 | /* SMBIOS type structure length (excluding strings-set) */ | |
69 | #define ATH10K_SMBIOS_BDF_EXT_LENGTH 0x9 | |
70 | ||
71 | /* Offset pointing to Board Data File Name Extension */ | |
72 | #define ATH10K_SMBIOS_BDF_EXT_OFFSET 0x8 | |
73 | ||
74 | /* Board Data File Name Extension string length. | |
75 | * String format: BDF_<Customer ID>_<Extension>\0 | |
76 | */ | |
77 | #define ATH10K_SMBIOS_BDF_EXT_STR_LENGTH 0x20 | |
78 | ||
79 | /* The magic used by QCA spec */ | |
80 | #define ATH10K_SMBIOS_BDF_EXT_MAGIC "BDF_" | |
81 | ||
bb2edb73 THJ |
82 | /* Default Airtime weight multipler (Tuned for multiclient performance) */ |
83 | #define ATH10K_AIRTIME_WEIGHT_MULTIPLIER 4 | |
84 | ||
5e3dd157 KV |
85 | struct ath10k; |
86 | ||
e07db352 KV |
87 | static inline const char *ath10k_bus_str(enum ath10k_bus bus) |
88 | { | |
89 | switch (bus) { | |
90 | case ATH10K_BUS_PCI: | |
91 | return "pci"; | |
0b523ced RM |
92 | case ATH10K_BUS_AHB: |
93 | return "ahb"; | |
01d6fd69 ES |
94 | case ATH10K_BUS_SDIO: |
95 | return "sdio"; | |
b00435e6 ES |
96 | case ATH10K_BUS_USB: |
97 | return "usb"; | |
63855e3d GS |
98 | case ATH10K_BUS_SNOC: |
99 | return "snoc"; | |
e07db352 KV |
100 | } |
101 | ||
102 | return "unknown"; | |
103 | } | |
104 | ||
66b8a010 MK |
105 | enum ath10k_skb_flags { |
106 | ATH10K_SKB_F_NO_HWCRYPT = BIT(0), | |
107 | ATH10K_SKB_F_DTIM_ZERO = BIT(1), | |
108 | ATH10K_SKB_F_DELIVER_CAB = BIT(2), | |
d668dbae | 109 | ATH10K_SKB_F_MGMT = BIT(3), |
609db229 | 110 | ATH10K_SKB_F_QOS = BIT(4), |
4920ce3b | 111 | ATH10K_SKB_F_RAW_TX = BIT(5), |
66b8a010 MK |
112 | }; |
113 | ||
5e3dd157 KV |
114 | struct ath10k_skb_cb { |
115 | dma_addr_t paddr; | |
66b8a010 | 116 | u8 flags; |
d84a512d | 117 | u8 eid; |
aca146af | 118 | u16 msdu_id; |
d1ce37b7 | 119 | u16 airtime_est; |
609db229 | 120 | struct ieee80211_vif *vif; |
dd4717b6 | 121 | struct ieee80211_txq *txq; |
5e3dd157 KV |
122 | } __packed; |
123 | ||
8582bf3b MK |
124 | struct ath10k_skb_rxcb { |
125 | dma_addr_t paddr; | |
c545070e | 126 | struct hlist_node hlist; |
8582bf3b MK |
127 | }; |
128 | ||
5e3dd157 KV |
129 | static inline struct ath10k_skb_cb *ATH10K_SKB_CB(struct sk_buff *skb) |
130 | { | |
131 | BUILD_BUG_ON(sizeof(struct ath10k_skb_cb) > | |
132 | IEEE80211_TX_INFO_DRIVER_DATA_SIZE); | |
133 | return (struct ath10k_skb_cb *)&IEEE80211_SKB_CB(skb)->driver_data; | |
134 | } | |
135 | ||
8582bf3b MK |
136 | static inline struct ath10k_skb_rxcb *ATH10K_SKB_RXCB(struct sk_buff *skb) |
137 | { | |
138 | BUILD_BUG_ON(sizeof(struct ath10k_skb_rxcb) > sizeof(skb->cb)); | |
139 | return (struct ath10k_skb_rxcb *)skb->cb; | |
140 | } | |
141 | ||
c545070e MK |
142 | #define ATH10K_RXCB_SKB(rxcb) \ |
143 | container_of((void *)rxcb, struct sk_buff, cb) | |
144 | ||
5e3dd157 KV |
145 | static inline u32 host_interest_item_address(u32 item_offset) |
146 | { | |
147 | return QCA988X_HOST_INTEREST_ADDRESS + item_offset; | |
148 | } | |
149 | ||
150 | struct ath10k_bmi { | |
151 | bool done_sent; | |
152 | }; | |
153 | ||
b3effe61 BM |
154 | struct ath10k_mem_chunk { |
155 | void *vaddr; | |
156 | dma_addr_t paddr; | |
157 | u32 len; | |
158 | u32 req_id; | |
159 | }; | |
160 | ||
5e3dd157 KV |
161 | struct ath10k_wmi { |
162 | enum ath10k_htc_ep_id eid; | |
163 | struct completion service_ready; | |
164 | struct completion unified_ready; | |
20ddca21 | 165 | struct completion barrier; |
6f6eb1bc | 166 | struct completion radar_confirm; |
be8b3943 | 167 | wait_queue_head_t tx_credits_wq; |
acfe7ecf | 168 | DECLARE_BITMAP(svc_map, WMI_SERVICE_MAX); |
ce42870e | 169 | struct wmi_cmd_map *cmd; |
6d1506e7 | 170 | struct wmi_vdev_param_map *vdev_param; |
226a339b | 171 | struct wmi_pdev_param_map *pdev_param; |
c0e33fe6 | 172 | struct wmi_peer_param_map *peer_param; |
d7579d12 | 173 | const struct wmi_ops *ops; |
3fab30f7 | 174 | const struct wmi_peer_flags_map *peer_flags; |
b3effe61 | 175 | |
dc405152 RP |
176 | u32 mgmt_max_num_pending_tx; |
177 | ||
178 | /* Protected by data_lock */ | |
179 | struct idr mgmt_pending_tx; | |
180 | ||
b3effe61 | 181 | u32 num_mem_chunks; |
ccec9038 | 182 | u32 rx_decap_mode; |
5c01aa3d | 183 | struct ath10k_mem_chunk mem_chunks[WMI_MAX_MEM_REQS]; |
5e3dd157 KV |
184 | }; |
185 | ||
60ef401a | 186 | struct ath10k_fw_stats_peer { |
5326849a MK |
187 | struct list_head list; |
188 | ||
5e3dd157 KV |
189 | u8 peer_macaddr[ETH_ALEN]; |
190 | u32 peer_rssi; | |
191 | u32 peer_tx_rate; | |
23c3aae4 | 192 | u32 peer_rx_rate; /* 10x only */ |
f40a307e | 193 | u64 rx_duration; |
5e3dd157 KV |
194 | }; |
195 | ||
4a49ae94 MSS |
196 | struct ath10k_fw_extd_stats_peer { |
197 | struct list_head list; | |
198 | ||
199 | u8 peer_macaddr[ETH_ALEN]; | |
5c51875c | 200 | u64 rx_duration; |
4a49ae94 MSS |
201 | }; |
202 | ||
7b6b153a MK |
203 | struct ath10k_fw_stats_vdev { |
204 | struct list_head list; | |
205 | ||
206 | u32 vdev_id; | |
207 | u32 beacon_snr; | |
208 | u32 data_snr; | |
209 | u32 num_tx_frames[4]; | |
210 | u32 num_rx_frames; | |
211 | u32 num_tx_frames_retries[4]; | |
212 | u32 num_tx_frames_failures[4]; | |
213 | u32 num_rts_fail; | |
214 | u32 num_rts_success; | |
215 | u32 num_rx_err; | |
216 | u32 num_rx_discard; | |
217 | u32 num_tx_not_acked; | |
218 | u32 tx_rate_history[10]; | |
219 | u32 beacon_rssi_history[10]; | |
220 | }; | |
221 | ||
1b3fdb50 RM |
222 | struct ath10k_fw_stats_vdev_extd { |
223 | struct list_head list; | |
224 | ||
225 | u32 vdev_id; | |
226 | u32 ppdu_aggr_cnt; | |
227 | u32 ppdu_noack; | |
228 | u32 mpdu_queued; | |
229 | u32 ppdu_nonaggr_cnt; | |
230 | u32 mpdu_sw_requeued; | |
231 | u32 mpdu_suc_retry; | |
232 | u32 mpdu_suc_multitry; | |
233 | u32 mpdu_fail_retry; | |
234 | u32 tx_ftm_suc; | |
235 | u32 tx_ftm_suc_retry; | |
236 | u32 tx_ftm_fail; | |
237 | u32 rx_ftmr_cnt; | |
238 | u32 rx_ftmr_dup_cnt; | |
239 | u32 rx_iftmr_cnt; | |
240 | u32 rx_iftmr_dup_cnt; | |
241 | }; | |
242 | ||
5326849a MK |
243 | struct ath10k_fw_stats_pdev { |
244 | struct list_head list; | |
245 | ||
5e3dd157 KV |
246 | /* PDEV stats */ |
247 | s32 ch_noise_floor; | |
15138fdf BG |
248 | u32 tx_frame_count; /* Cycles spent transmitting frames */ |
249 | u32 rx_frame_count; /* Cycles spent receiving frames */ | |
250 | u32 rx_clear_count; /* Total channel busy time, evidently */ | |
251 | u32 cycle_count; /* Total on-channel time */ | |
5e3dd157 KV |
252 | u32 phy_err_count; |
253 | u32 chan_tx_power; | |
52e346d1 CYY |
254 | u32 ack_rx_bad; |
255 | u32 rts_bad; | |
256 | u32 rts_good; | |
257 | u32 fcs_bad; | |
258 | u32 no_beacons; | |
259 | u32 mib_int_count; | |
5e3dd157 KV |
260 | |
261 | /* PDEV TX stats */ | |
262 | s32 comp_queued; | |
263 | s32 comp_delivered; | |
264 | s32 msdu_enqued; | |
265 | s32 mpdu_enqued; | |
266 | s32 wmm_drop; | |
267 | s32 local_enqued; | |
268 | s32 local_freed; | |
269 | s32 hw_queued; | |
270 | s32 hw_reaped; | |
271 | s32 underrun; | |
98dd2b92 | 272 | u32 hw_paused; |
5e3dd157 KV |
273 | s32 tx_abort; |
274 | s32 mpdus_requed; | |
275 | u32 tx_ko; | |
276 | u32 data_rc; | |
277 | u32 self_triggers; | |
278 | u32 sw_retry_failure; | |
279 | u32 illgl_rate_phy_err; | |
280 | u32 pdev_cont_xretry; | |
281 | u32 pdev_tx_timeout; | |
282 | u32 pdev_resets; | |
283 | u32 phy_underrun; | |
284 | u32 txop_ovf; | |
98dd2b92 MP |
285 | u32 seq_posted; |
286 | u32 seq_failed_queueing; | |
287 | u32 seq_completed; | |
288 | u32 seq_restarted; | |
289 | u32 mu_seq_posted; | |
290 | u32 mpdus_sw_flush; | |
291 | u32 mpdus_hw_filter; | |
292 | u32 mpdus_truncated; | |
293 | u32 mpdus_ack_failed; | |
294 | u32 mpdus_expired; | |
5e3dd157 KV |
295 | |
296 | /* PDEV RX stats */ | |
297 | s32 mid_ppdu_route_change; | |
298 | s32 status_rcvd; | |
299 | s32 r0_frags; | |
300 | s32 r1_frags; | |
301 | s32 r2_frags; | |
302 | s32 r3_frags; | |
303 | s32 htt_msdus; | |
304 | s32 htt_mpdus; | |
305 | s32 loc_msdus; | |
306 | s32 loc_mpdus; | |
307 | s32 oversize_amsdu; | |
308 | s32 phy_errs; | |
309 | s32 phy_err_drop; | |
310 | s32 mpdu_errs; | |
98dd2b92 | 311 | s32 rx_ovfl_errs; |
5326849a | 312 | }; |
5e3dd157 | 313 | |
5326849a | 314 | struct ath10k_fw_stats { |
4a49ae94 | 315 | bool extended; |
5326849a | 316 | struct list_head pdevs; |
7b6b153a | 317 | struct list_head vdevs; |
5326849a | 318 | struct list_head peers; |
4a49ae94 | 319 | struct list_head peers_extd; |
5e3dd157 KV |
320 | }; |
321 | ||
29542666 MK |
322 | #define ATH10K_TPC_TABLE_TYPE_FLAG 1 |
323 | #define ATH10K_TPC_PREAM_TABLE_END 0xFFFF | |
324 | ||
325 | struct ath10k_tpc_table { | |
326 | u32 pream_idx[WMI_TPC_RATE_MAX]; | |
327 | u8 rate_code[WMI_TPC_RATE_MAX]; | |
328 | char tpc_value[WMI_TPC_RATE_MAX][WMI_TPC_TX_N_CHAIN * WMI_TPC_BUF_SIZE]; | |
329 | }; | |
330 | ||
331 | struct ath10k_tpc_stats { | |
332 | u32 reg_domain; | |
333 | u32 chan_freq; | |
334 | u32 phy_mode; | |
335 | u32 twice_antenna_reduction; | |
336 | u32 twice_max_rd_power; | |
337 | s32 twice_antenna_gain; | |
338 | u32 power_limit; | |
339 | u32 num_tx_chain; | |
340 | u32 ctl; | |
341 | u32 rate_max; | |
342 | u8 flag[WMI_TPC_FLAG]; | |
343 | struct ath10k_tpc_table tpc_table[WMI_TPC_FLAG]; | |
344 | }; | |
345 | ||
bc64d052 MK |
346 | struct ath10k_tpc_table_final { |
347 | u32 pream_idx[WMI_TPC_FINAL_RATE_MAX]; | |
348 | u8 rate_code[WMI_TPC_FINAL_RATE_MAX]; | |
349 | char tpc_value[WMI_TPC_FINAL_RATE_MAX][WMI_TPC_TX_N_CHAIN * WMI_TPC_BUF_SIZE]; | |
350 | }; | |
351 | ||
352 | struct ath10k_tpc_stats_final { | |
353 | u32 reg_domain; | |
354 | u32 chan_freq; | |
355 | u32 phy_mode; | |
356 | u32 twice_antenna_reduction; | |
357 | u32 twice_max_rd_power; | |
358 | s32 twice_antenna_gain; | |
359 | u32 power_limit; | |
360 | u32 num_tx_chain; | |
361 | u32 ctl; | |
362 | u32 rate_max; | |
363 | u8 flag[WMI_TPC_FLAG]; | |
364 | struct ath10k_tpc_table_final tpc_table_final[WMI_TPC_FLAG]; | |
365 | }; | |
366 | ||
9702c686 JD |
367 | struct ath10k_dfs_stats { |
368 | u32 phy_errors; | |
369 | u32 pulses_total; | |
370 | u32 pulses_detected; | |
371 | u32 pulses_discarded; | |
372 | u32 radar_detected; | |
373 | }; | |
374 | ||
6f6eb1bc S |
375 | enum ath10k_radar_confirmation_state { |
376 | ATH10K_RADAR_CONFIRMATION_IDLE = 0, | |
377 | ATH10K_RADAR_CONFIRMATION_INPROGRESS, | |
378 | ATH10K_RADAR_CONFIRMATION_STOPPED, | |
379 | }; | |
380 | ||
381 | struct ath10k_radar_found_info { | |
382 | u32 pri_min; | |
383 | u32 pri_max; | |
384 | u32 width_min; | |
385 | u32 width_max; | |
386 | u32 sidx_min; | |
387 | u32 sidx_max; | |
388 | }; | |
389 | ||
5e3dd157 KV |
390 | #define ATH10K_MAX_NUM_PEER_IDS (1 << 11) /* htt rx_desc limit */ |
391 | ||
392 | struct ath10k_peer { | |
393 | struct list_head list; | |
6942726f MK |
394 | struct ieee80211_vif *vif; |
395 | struct ieee80211_sta *sta; | |
396 | ||
0a744d92 | 397 | bool removed; |
5e3dd157 KV |
398 | int vdev_id; |
399 | u8 addr[ETH_ALEN]; | |
400 | DECLARE_BITMAP(peer_ids, ATH10K_MAX_NUM_PEER_IDS); | |
ae167131 SM |
401 | |
402 | /* protected by ar->data_lock */ | |
5e3dd157 | 403 | struct ieee80211_key_conf *keys[WMI_MAX_KEY_INDEX + 1]; |
e1bddde9 WG |
404 | union htt_rx_pn_t tids_last_pn[ATH10K_TXRX_NUM_EXT_TIDS]; |
405 | bool tids_last_pn_valid[ATH10K_TXRX_NUM_EXT_TIDS]; | |
406 | union htt_rx_pn_t frag_tids_last_pn[ATH10K_TXRX_NUM_EXT_TIDS]; | |
407 | u32 frag_tids_seq[ATH10K_TXRX_NUM_EXT_TIDS]; | |
408 | struct { | |
409 | enum htt_security_types sec_type; | |
410 | int pn_len; | |
411 | } rx_pn[ATH10K_HTT_TXRX_PEER_SECURITY_MAX]; | |
5e3dd157 KV |
412 | }; |
413 | ||
29946878 MK |
414 | struct ath10k_txq { |
415 | struct list_head list; | |
3cc0fef6 | 416 | unsigned long num_fw_queued; |
426e10ea | 417 | unsigned long num_push_allowed; |
29946878 MK |
418 | }; |
419 | ||
caee728a VT |
420 | enum ath10k_pkt_rx_err { |
421 | ATH10K_PKT_RX_ERR_FCS, | |
422 | ATH10K_PKT_RX_ERR_TKIP, | |
423 | ATH10K_PKT_RX_ERR_CRYPT, | |
424 | ATH10K_PKT_RX_ERR_PEER_IDX_INVAL, | |
425 | ATH10K_PKT_RX_ERR_MAX, | |
426 | }; | |
427 | ||
428 | enum ath10k_ampdu_subfrm_num { | |
429 | ATH10K_AMPDU_SUBFRM_NUM_10, | |
430 | ATH10K_AMPDU_SUBFRM_NUM_20, | |
431 | ATH10K_AMPDU_SUBFRM_NUM_30, | |
432 | ATH10K_AMPDU_SUBFRM_NUM_40, | |
433 | ATH10K_AMPDU_SUBFRM_NUM_50, | |
434 | ATH10K_AMPDU_SUBFRM_NUM_60, | |
435 | ATH10K_AMPDU_SUBFRM_NUM_MORE, | |
436 | ATH10K_AMPDU_SUBFRM_NUM_MAX, | |
437 | }; | |
438 | ||
439 | enum ath10k_amsdu_subfrm_num { | |
440 | ATH10K_AMSDU_SUBFRM_NUM_1, | |
441 | ATH10K_AMSDU_SUBFRM_NUM_2, | |
442 | ATH10K_AMSDU_SUBFRM_NUM_3, | |
443 | ATH10K_AMSDU_SUBFRM_NUM_4, | |
444 | ATH10K_AMSDU_SUBFRM_NUM_MORE, | |
445 | ATH10K_AMSDU_SUBFRM_NUM_MAX, | |
446 | }; | |
447 | ||
448 | struct ath10k_sta_tid_stats { | |
28bbe237 KV |
449 | unsigned long rx_pkt_from_fw; |
450 | unsigned long rx_pkt_unchained; | |
451 | unsigned long rx_pkt_drop_chained; | |
452 | unsigned long rx_pkt_drop_filter; | |
453 | unsigned long rx_pkt_err[ATH10K_PKT_RX_ERR_MAX]; | |
454 | unsigned long rx_pkt_queued_for_mac; | |
455 | unsigned long rx_pkt_ampdu[ATH10K_AMPDU_SUBFRM_NUM_MAX]; | |
456 | unsigned long rx_pkt_amsdu[ATH10K_AMSDU_SUBFRM_NUM_MAX]; | |
caee728a VT |
457 | }; |
458 | ||
a904417f AK |
459 | enum ath10k_counter_type { |
460 | ATH10K_COUNTER_TYPE_BYTES, | |
461 | ATH10K_COUNTER_TYPE_PKTS, | |
462 | ATH10K_COUNTER_TYPE_MAX, | |
463 | }; | |
464 | ||
465 | enum ath10k_stats_type { | |
466 | ATH10K_STATS_TYPE_SUCC, | |
467 | ATH10K_STATS_TYPE_FAIL, | |
468 | ATH10K_STATS_TYPE_RETRY, | |
469 | ATH10K_STATS_TYPE_AMPDU, | |
470 | ATH10K_STATS_TYPE_MAX, | |
471 | }; | |
472 | ||
473 | struct ath10k_htt_data_stats { | |
474 | u64 legacy[ATH10K_COUNTER_TYPE_MAX][ATH10K_LEGACY_NUM]; | |
475 | u64 ht[ATH10K_COUNTER_TYPE_MAX][ATH10K_HT_MCS_NUM]; | |
476 | u64 vht[ATH10K_COUNTER_TYPE_MAX][ATH10K_VHT_MCS_NUM]; | |
477 | u64 bw[ATH10K_COUNTER_TYPE_MAX][ATH10K_BW_NUM]; | |
478 | u64 nss[ATH10K_COUNTER_TYPE_MAX][ATH10K_NSS_NUM]; | |
479 | u64 gi[ATH10K_COUNTER_TYPE_MAX][ATH10K_GI_NUM]; | |
e88975ca | 480 | u64 rate_table[ATH10K_COUNTER_TYPE_MAX][ATH10K_RATE_TABLE_NUM]; |
a904417f AK |
481 | }; |
482 | ||
483 | struct ath10k_htt_tx_stats { | |
484 | struct ath10k_htt_data_stats stats[ATH10K_STATS_TYPE_MAX]; | |
485 | u64 tx_duration; | |
486 | u64 ba_fails; | |
487 | u64 ack_fails; | |
488 | }; | |
489 | ||
9797febc MK |
490 | struct ath10k_sta { |
491 | struct ath10k_vif *arvif; | |
492 | ||
493 | /* the following are protected by ar->data_lock */ | |
494 | u32 changed; /* IEEE80211_RC_* */ | |
495 | u32 bw; | |
496 | u32 nss; | |
497 | u32 smps; | |
bb8f0c6a | 498 | u16 peer_id; |
cec17c38 | 499 | struct rate_info txrate; |
9a9cf0e6 | 500 | struct ieee80211_tx_info tx_info; |
d1ce37b7 | 501 | u32 last_tx_bitrate; |
9797febc MK |
502 | |
503 | struct work_struct update_wk; | |
6a7f8911 | 504 | u64 rx_duration; |
a904417f | 505 | struct ath10k_htt_tx_stats *tx_stats; |
f5045988 RM |
506 | |
507 | #ifdef CONFIG_MAC80211_DEBUGFS | |
508 | /* protected by conf_mutex */ | |
509 | bool aggr_mode; | |
caee728a VT |
510 | |
511 | /* Protected with ar->data_lock */ | |
512 | struct ath10k_sta_tid_stats tid_stats[IEEE80211_NUM_TIDS + 1]; | |
f5045988 | 513 | #endif |
d70c0d46 MK |
514 | /* Protected with ar->data_lock */ |
515 | u32 peer_ps_state; | |
9797febc MK |
516 | }; |
517 | ||
fe36e70f RP |
518 | #define ATH10K_VDEV_SETUP_TIMEOUT_HZ (5 * HZ) |
519 | #define ATH10K_VDEV_DELETE_TIMEOUT_HZ (5 * HZ) | |
5e3dd157 | 520 | |
af21319f MK |
521 | enum ath10k_beacon_state { |
522 | ATH10K_BEACON_SCHEDULED = 0, | |
523 | ATH10K_BEACON_SENDING, | |
524 | ATH10K_BEACON_SENT, | |
525 | }; | |
526 | ||
5e3dd157 | 527 | struct ath10k_vif { |
0579119f MK |
528 | struct list_head list; |
529 | ||
5e3dd157 | 530 | u32 vdev_id; |
bb8f0c6a | 531 | u16 peer_id; |
5e3dd157 KV |
532 | enum wmi_vdev_type vdev_type; |
533 | enum wmi_vdev_subtype vdev_subtype; | |
534 | u32 beacon_interval; | |
535 | u32 dtim_period; | |
ed54388a | 536 | struct sk_buff *beacon; |
748afc47 | 537 | /* protected by data_lock */ |
af21319f | 538 | enum ath10k_beacon_state beacon_state; |
64badcb6 MK |
539 | void *beacon_buf; |
540 | dma_addr_t beacon_paddr; | |
96d828d4 | 541 | unsigned long tx_paused; /* arbitrary values defined by target */ |
5e3dd157 KV |
542 | |
543 | struct ath10k *ar; | |
544 | struct ieee80211_vif *vif; | |
545 | ||
c930f744 MK |
546 | bool is_started; |
547 | bool is_up; | |
855aed12 | 548 | bool spectral_enabled; |
cffb41f3 | 549 | bool ps; |
c930f744 MK |
550 | u32 aid; |
551 | u8 bssid[ETH_ALEN]; | |
552 | ||
5e3dd157 | 553 | struct ieee80211_key_conf *wep_keys[WMI_MAX_KEY_INDEX + 1]; |
627613f8 | 554 | s8 def_wep_key_idx; |
5e3dd157 KV |
555 | |
556 | u16 tx_seq_no; | |
557 | ||
558 | union { | |
559 | struct { | |
5e3dd157 KV |
560 | u32 uapsd; |
561 | } sta; | |
562 | struct { | |
3cec3be3 RM |
563 | /* 512 stations */ |
564 | u8 tim_bitmap[64]; | |
5e3dd157 KV |
565 | u8 tim_len; |
566 | u32 ssid_len; | |
567 | u8 ssid[IEEE80211_MAX_SSID_LEN]; | |
568 | bool hidden_ssid; | |
569 | /* P2P_IE with NoA attribute for P2P_GO case */ | |
570 | u32 noa_len; | |
571 | u8 *noa_data; | |
572 | } ap; | |
5e3dd157 | 573 | } u; |
51ab1a0a | 574 | |
e81bd104 | 575 | bool use_cts_prot; |
ccec9038 | 576 | bool nohwcrypt; |
e81bd104 | 577 | int num_legacy_stations; |
7d9d5587 | 578 | int txpower; |
059104bf | 579 | bool ftm_responder; |
5e752e42 | 580 | struct wmi_wmm_params_all_arg wmm_params; |
81a9a17d | 581 | struct work_struct ap_csa_work; |
cc9904e6 | 582 | struct delayed_work connection_loss_work; |
45c9abc0 | 583 | struct cfg80211_bitrate_mask bitrate_mask; |
8b97b055 MP |
584 | |
585 | /* For setting VHT peer fixed rate, protected by conf_mutex */ | |
586 | int vht_num_rates; | |
587 | u8 vht_pfr; | |
5e3dd157 KV |
588 | }; |
589 | ||
590 | struct ath10k_vif_iter { | |
591 | u32 vdev_id; | |
592 | struct ath10k_vif *arvif; | |
593 | }; | |
594 | ||
c75c398b MSS |
595 | /* Copy Engine register dump, protected by ce-lock */ |
596 | struct ath10k_ce_crash_data { | |
597 | __le32 base_addr; | |
598 | __le32 src_wr_idx; | |
599 | __le32 src_r_idx; | |
600 | __le32 dst_wr_idx; | |
601 | __le32 dst_r_idx; | |
602 | }; | |
603 | ||
604 | struct ath10k_ce_crash_hdr { | |
605 | __le32 ce_count; | |
606 | __le32 reserved[3]; /* for future use */ | |
607 | struct ath10k_ce_crash_data entries[]; | |
608 | }; | |
609 | ||
703f261d AL |
610 | #define MAX_MEM_DUMP_TYPE 5 |
611 | ||
384914b2 BG |
612 | /* used for crash-dump storage, protected by data-lock */ |
613 | struct ath10k_fw_crash_data { | |
ab3f9c88 | 614 | guid_t guid; |
dafa4203 | 615 | struct timespec64 timestamp; |
384914b2 | 616 | __le32 registers[REG_DUMP_COUNT_QCA988X]; |
c75c398b | 617 | struct ath10k_ce_crash_data ce_crash_data[CE_COUNT_MAX]; |
703f261d AL |
618 | |
619 | u8 *ramdump_buf; | |
620 | size_t ramdump_buf_len; | |
384914b2 BG |
621 | }; |
622 | ||
5e3dd157 KV |
623 | struct ath10k_debug { |
624 | struct dentry *debugfs_phy; | |
625 | ||
60ef401a MK |
626 | struct ath10k_fw_stats fw_stats; |
627 | struct completion fw_stats_complete; | |
5326849a | 628 | bool fw_stats_done; |
5e3dd157 | 629 | |
a3d135e5 | 630 | unsigned long htt_stats_mask; |
473a4084 | 631 | unsigned long reset_htt_stats; |
a3d135e5 | 632 | struct delayed_work htt_stats_dwork; |
9702c686 JD |
633 | struct ath10k_dfs_stats dfs_stats; |
634 | struct ath_dfs_pool_stats dfs_pool_stats; | |
f118a3e5 | 635 | |
29542666 MK |
636 | /* used for tpc-dump storage, protected by data-lock */ |
637 | struct ath10k_tpc_stats *tpc_stats; | |
bc64d052 | 638 | struct ath10k_tpc_stats_final *tpc_stats_final; |
29542666 MK |
639 | |
640 | struct completion tpc_complete; | |
641 | ||
90174455 | 642 | /* protected by conf_mutex */ |
afcbc82c | 643 | u64 fw_dbglog_mask; |
467210a6 | 644 | u32 fw_dbglog_level; |
077a3804 | 645 | u32 reg_addr; |
a7bd3e99 | 646 | u32 nf_cal_period; |
f67b107d | 647 | void *cal_data; |
348cd95c | 648 | u32 enable_extd_tx_stats; |
d9e47698 | 649 | u8 fw_dbglog_mode; |
5e3dd157 KV |
650 | }; |
651 | ||
f7843d7f MK |
652 | enum ath10k_state { |
653 | ATH10K_STATE_OFF = 0, | |
654 | ATH10K_STATE_ON, | |
affd3217 MK |
655 | |
656 | /* When doing firmware recovery the device is first powered down. | |
657 | * mac80211 is supposed to call in to start() hook later on. It is | |
658 | * however possible that driver unloading and firmware crash overlap. | |
659 | * mac80211 can wait on conf_mutex in stop() while the device is | |
660 | * stopped in ath10k_core_restart() work holding conf_mutex. The state | |
661 | * RESTARTED means that the device is up and mac80211 has started hw | |
662 | * reconfiguration. Once mac80211 is done with the reconfiguration we | |
37ff1b0d MR |
663 | * set the state to STATE_ON in reconfig_complete(). |
664 | */ | |
affd3217 MK |
665 | ATH10K_STATE_RESTARTING, |
666 | ATH10K_STATE_RESTARTED, | |
667 | ||
668 | /* The device has crashed while restarting hw. This state is like ON | |
669 | * but commands are blocked in HTC and -ECOMM response is given. This | |
670 | * prevents completion timeouts and makes the driver more responsive to | |
37ff1b0d MR |
671 | * userspace commands. This is also prevents recursive recovery. |
672 | */ | |
affd3217 | 673 | ATH10K_STATE_WEDGED, |
43d2a30f KV |
674 | |
675 | /* factory tests */ | |
676 | ATH10K_STATE_UTF, | |
677 | }; | |
678 | ||
679 | enum ath10k_firmware_mode { | |
680 | /* the default mode, standard 802.11 functionality */ | |
681 | ATH10K_FIRMWARE_MODE_NORMAL, | |
682 | ||
683 | /* factory tests etc */ | |
684 | ATH10K_FIRMWARE_MODE_UTF, | |
f7843d7f MK |
685 | }; |
686 | ||
0d9b0438 MK |
687 | enum ath10k_fw_features { |
688 | /* wmi_mgmt_rx_hdr contains extra RSSI information */ | |
689 | ATH10K_FW_FEATURE_EXT_WMI_MGMT_RX = 0, | |
690 | ||
202e86e6 | 691 | /* Firmware from 10X branch. Deprecated, don't use in new code. */ |
ce42870e BM |
692 | ATH10K_FW_FEATURE_WMI_10X = 1, |
693 | ||
5e00d31a BM |
694 | /* firmware support tx frame management over WMI, otherwise it's HTT */ |
695 | ATH10K_FW_FEATURE_HAS_WMI_MGMT_TX = 2, | |
696 | ||
d354181f BM |
697 | /* Firmware does not support P2P */ |
698 | ATH10K_FW_FEATURE_NO_P2P = 3, | |
699 | ||
202e86e6 KV |
700 | /* Firmware 10.2 feature bit. The ATH10K_FW_FEATURE_WMI_10X feature |
701 | * bit is required to be set as well. Deprecated, don't use in new | |
702 | * code. | |
24c88f78 MK |
703 | */ |
704 | ATH10K_FW_FEATURE_WMI_10_2 = 4, | |
705 | ||
cffb41f3 MK |
706 | /* Some firmware revisions lack proper multi-interface client powersave |
707 | * implementation. Enabling PS could result in connection drops, | |
708 | * traffic stalls, etc. | |
709 | */ | |
710 | ATH10K_FW_FEATURE_MULTI_VIF_PS_SUPPORT = 5, | |
711 | ||
5fd3ac3c JD |
712 | /* Some firmware revisions have an incomplete WoWLAN implementation |
713 | * despite WMI service bit being advertised. This feature flag is used | |
714 | * to distinguish whether WoWLAN is really supported or not. | |
715 | */ | |
716 | ATH10K_FW_FEATURE_WOWLAN_SUPPORT = 6, | |
717 | ||
d9153546 | 718 | /* Don't trust error code from otp.bin */ |
ccec9038 | 719 | ATH10K_FW_FEATURE_IGNORE_OTP_RESULT = 7, |
d9153546 | 720 | |
48f4ca34 MK |
721 | /* Some firmware revisions pad 4th hw address to 4 byte boundary making |
722 | * it 8 bytes long in Native Wifi Rx decap. | |
723 | */ | |
ccec9038 | 724 | ATH10K_FW_FEATURE_NO_NWIFI_DECAP_4ADDR_PADDING = 8, |
48f4ca34 | 725 | |
163f5264 RM |
726 | /* Firmware supports bypassing PLL setting on init. */ |
727 | ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT = 9, | |
728 | ||
ccec9038 DL |
729 | /* Raw mode support. If supported, FW supports receiving and trasmitting |
730 | * frames in raw mode. | |
731 | */ | |
732 | ATH10K_FW_FEATURE_RAW_MODE_SUPPORT = 10, | |
733 | ||
62f77f09 M |
734 | /* Firmware Supports Adaptive CCA*/ |
735 | ATH10K_FW_FEATURE_SUPPORTS_ADAPTIVE_CCA = 11, | |
736 | ||
90eceb3b T |
737 | /* Firmware supports management frame protection */ |
738 | ATH10K_FW_FEATURE_MFP_SUPPORT = 12, | |
739 | ||
9b783763 MK |
740 | /* Firmware supports pull-push model where host shares it's software |
741 | * queue state with firmware and firmware generates fetch requests | |
742 | * telling host which queues to dequeue tx from. | |
743 | * | |
744 | * Primary function of this is improved MU-MIMO performance with | |
745 | * multiple clients. | |
746 | */ | |
747 | ATH10K_FW_FEATURE_PEER_FLOW_CONTROL = 13, | |
748 | ||
64e001f4 RM |
749 | /* Firmware supports BT-Coex without reloading firmware via pdev param. |
750 | * To support Bluetooth coexistence pdev param, WMI_COEX_GPIO_SUPPORT of | |
751 | * extended resource config should be enabled always. This firmware IE | |
752 | * is used to configure WMI_COEX_GPIO_SUPPORT. | |
753 | */ | |
754 | ATH10K_FW_FEATURE_BTCOEX_PARAM = 14, | |
755 | ||
fcf7cf15 MSS |
756 | /* Unused flag and proven to be not working, enable this if you want |
757 | * to experiment sending NULL func data frames in HTT TX | |
2cdce425 MSS |
758 | */ |
759 | ATH10K_FW_FEATURE_SKIP_NULL_FUNC_WAR = 15, | |
760 | ||
705d7aa0 MR |
761 | /* Firmware allow other BSS mesh broadcast/multicast frames without |
762 | * creating monitor interface. Appropriate rxfilters are programmed for | |
763 | * mesh vdev by firmware itself. This feature flags will be used for | |
764 | * not creating monitor vdev while configuring mesh node. | |
765 | */ | |
766 | ATH10K_FW_FEATURE_ALLOWS_MESH_BCAST = 16, | |
767 | ||
36d9cdb6 VN |
768 | /* Firmware does not support power save in station mode. */ |
769 | ATH10K_FW_FEATURE_NO_PS = 17, | |
770 | ||
1807da49 RP |
771 | /* Firmware allows management tx by reference instead of by value. */ |
772 | ATH10K_FW_FEATURE_MGMT_TX_BY_REF = 18, | |
773 | ||
71e9c29f RP |
774 | /* Firmware load is done externally, not by bmi */ |
775 | ATH10K_FW_FEATURE_NON_BMI = 19, | |
776 | ||
13104929 RP |
777 | /* Firmware sends only one chan_info event per channel */ |
778 | ATH10K_FW_FEATURE_SINGLE_CHAN_INFO_PER_CHANNEL = 20, | |
779 | ||
8b97b055 MP |
780 | /* Firmware allows setting peer fixed rate */ |
781 | ATH10K_FW_FEATURE_PEER_FIXED_RATE = 21, | |
782 | ||
0d9b0438 MK |
783 | /* keep last */ |
784 | ATH10K_FW_FEATURE_COUNT, | |
785 | }; | |
786 | ||
e8a50f8b MP |
787 | enum ath10k_dev_flags { |
788 | /* Indicates that ath10k device is during CAC phase of DFS */ | |
789 | ATH10K_CAC_RUNNING, | |
6782cb69 | 790 | ATH10K_FLAG_CORE_REGISTERED, |
7962b0d8 MK |
791 | |
792 | /* Device has crashed and needs to restart. This indicates any pending | |
793 | * waiters should immediately cancel instead of waiting for a time out. | |
794 | */ | |
795 | ATH10K_FLAG_CRASH_FLUSH, | |
ccec9038 DL |
796 | |
797 | /* Use Raw mode instead of native WiFi Tx/Rx encap mode. | |
798 | * Raw mode supports both hardware and software crypto. Native WiFi only | |
799 | * supports hardware crypto. | |
800 | */ | |
801 | ATH10K_FLAG_RAW_MODE, | |
802 | ||
803 | /* Disable HW crypto engine */ | |
804 | ATH10K_FLAG_HW_CRYPTO_DISABLED, | |
844fa572 YL |
805 | |
806 | /* Bluetooth coexistance enabled */ | |
807 | ATH10K_FLAG_BTCOEX, | |
cc61a1bb MSS |
808 | |
809 | /* Per Station statistics service */ | |
810 | ATH10K_FLAG_PEER_STATS, | |
e8a50f8b MP |
811 | }; |
812 | ||
a58227ef KV |
813 | enum ath10k_cal_mode { |
814 | ATH10K_CAL_MODE_FILE, | |
815 | ATH10K_CAL_MODE_OTP, | |
5aabff05 | 816 | ATH10K_CAL_MODE_DT, |
3d9195ea RM |
817 | ATH10K_PRE_CAL_MODE_FILE, |
818 | ATH10K_PRE_CAL_MODE_DT, | |
6847f967 | 819 | ATH10K_CAL_MODE_EEPROM, |
a58227ef KV |
820 | }; |
821 | ||
ccec9038 DL |
822 | enum ath10k_crypt_mode { |
823 | /* Only use hardware crypto engine */ | |
824 | ATH10K_CRYPT_MODE_HW, | |
825 | /* Only use software crypto engine */ | |
826 | ATH10K_CRYPT_MODE_SW, | |
827 | }; | |
828 | ||
a58227ef KV |
829 | static inline const char *ath10k_cal_mode_str(enum ath10k_cal_mode mode) |
830 | { | |
831 | switch (mode) { | |
832 | case ATH10K_CAL_MODE_FILE: | |
833 | return "file"; | |
834 | case ATH10K_CAL_MODE_OTP: | |
835 | return "otp"; | |
5aabff05 TK |
836 | case ATH10K_CAL_MODE_DT: |
837 | return "dt"; | |
3d9195ea RM |
838 | case ATH10K_PRE_CAL_MODE_FILE: |
839 | return "pre-cal-file"; | |
840 | case ATH10K_PRE_CAL_MODE_DT: | |
841 | return "pre-cal-dt"; | |
6847f967 SE |
842 | case ATH10K_CAL_MODE_EEPROM: |
843 | return "eeprom"; | |
a58227ef KV |
844 | } |
845 | ||
846 | return "unknown"; | |
847 | } | |
848 | ||
5c81c7fd MK |
849 | enum ath10k_scan_state { |
850 | ATH10K_SCAN_IDLE, | |
851 | ATH10K_SCAN_STARTING, | |
852 | ATH10K_SCAN_RUNNING, | |
853 | ATH10K_SCAN_ABORTING, | |
854 | }; | |
855 | ||
856 | static inline const char *ath10k_scan_state_str(enum ath10k_scan_state state) | |
857 | { | |
858 | switch (state) { | |
859 | case ATH10K_SCAN_IDLE: | |
860 | return "idle"; | |
861 | case ATH10K_SCAN_STARTING: | |
862 | return "starting"; | |
863 | case ATH10K_SCAN_RUNNING: | |
864 | return "running"; | |
865 | case ATH10K_SCAN_ABORTING: | |
866 | return "aborting"; | |
867 | } | |
868 | ||
869 | return "unknown"; | |
870 | } | |
871 | ||
96d828d4 MK |
872 | enum ath10k_tx_pause_reason { |
873 | ATH10K_TX_PAUSE_Q_FULL, | |
874 | ATH10K_TX_PAUSE_MAX, | |
875 | }; | |
876 | ||
7ebf721d KV |
877 | struct ath10k_fw_file { |
878 | const struct firmware *firmware; | |
879 | ||
45317355 KV |
880 | char fw_version[ETHTOOL_FWVERS_LEN]; |
881 | ||
c4cdf753 KV |
882 | DECLARE_BITMAP(fw_features, ATH10K_FW_FEATURE_COUNT); |
883 | ||
bf3c13ab | 884 | enum ath10k_fw_wmi_op_version wmi_op_version; |
77561f93 | 885 | enum ath10k_fw_htt_op_version htt_op_version; |
bf3c13ab | 886 | |
7ebf721d KV |
887 | const void *firmware_data; |
888 | size_t firmware_len; | |
889 | ||
890 | const void *otp_data; | |
891 | size_t otp_len; | |
892 | ||
893 | const void *codeswap_data; | |
894 | size_t codeswap_len; | |
5459c5d4 T |
895 | |
896 | /* The original idea of struct ath10k_fw_file was that it only | |
897 | * contains struct firmware and pointers to various parts (actual | |
898 | * firmware binary, otp, metadata etc) of the file. This seg_info | |
899 | * is actually created separate but as this is used similarly as | |
900 | * the other firmware components it's more convenient to have it | |
901 | * here. | |
902 | */ | |
903 | struct ath10k_swap_code_seg_info *firmware_swap_code_seg_info; | |
7ebf721d KV |
904 | }; |
905 | ||
906 | struct ath10k_fw_components { | |
907 | const struct firmware *board; | |
908 | const void *board_data; | |
909 | size_t board_len; | |
31324d17 SM |
910 | const struct firmware *ext_board; |
911 | const void *ext_board_data; | |
912 | size_t ext_board_len; | |
7ebf721d KV |
913 | |
914 | struct ath10k_fw_file fw_file; | |
915 | }; | |
916 | ||
cec17c38 AK |
917 | struct ath10k_per_peer_tx_stats { |
918 | u32 succ_bytes; | |
919 | u32 retry_bytes; | |
920 | u32 failed_bytes; | |
921 | u8 ratecode; | |
922 | u8 flags; | |
923 | u16 peer_id; | |
924 | u16 succ_pkts; | |
925 | u16 retry_pkts; | |
926 | u16 failed_pkts; | |
927 | u16 duration; | |
928 | u32 reserved1; | |
929 | u32 reserved2; | |
930 | }; | |
931 | ||
7c2dd615 ES |
932 | enum ath10k_dev_type { |
933 | ATH10K_DEV_TYPE_LL, | |
934 | ATH10K_DEV_TYPE_HL, | |
935 | }; | |
936 | ||
c0d8d565 ES |
937 | struct ath10k_bus_params { |
938 | u32 chip_id; | |
7c2dd615 | 939 | enum ath10k_dev_type dev_type; |
de8781d7 | 940 | bool link_can_suspend; |
8ea51e40 | 941 | bool hl_msdu_ids; |
c0d8d565 ES |
942 | }; |
943 | ||
5e3dd157 KV |
944 | struct ath10k { |
945 | struct ath_common ath_common; | |
946 | struct ieee80211_hw *hw; | |
4ca18078 | 947 | struct ieee80211_ops *ops; |
5e3dd157 KV |
948 | struct device *dev; |
949 | u8 mac_addr[ETH_ALEN]; | |
950 | ||
d63955b3 | 951 | enum ath10k_hw_rev hw_rev; |
36582e5d | 952 | u16 dev_id; |
e01ae68c | 953 | u32 chip_id; |
7c2dd615 | 954 | enum ath10k_dev_type dev_type; |
5e3dd157 KV |
955 | u32 target_version; |
956 | u8 fw_version_major; | |
957 | u32 fw_version_minor; | |
958 | u16 fw_version_release; | |
959 | u16 fw_version_build; | |
6274cd41 | 960 | u32 fw_stats_req_mask; |
5e3dd157 KV |
961 | u32 phy_capability; |
962 | u32 hw_min_tx_power; | |
963 | u32 hw_max_tx_power; | |
209b2a68 | 964 | u32 hw_eeprom_rd; |
5e3dd157 KV |
965 | u32 ht_cap_info; |
966 | u32 vht_cap_info; | |
73690c48 | 967 | u32 vht_supp_mcs; |
8865bee4 | 968 | u32 num_rf_chains; |
5c8726ec | 969 | u32 max_spatial_stream; |
b3e71d7a | 970 | /* protected by conf_mutex */ |
fa879490 TP |
971 | u32 low_2ghz_chan; |
972 | u32 high_2ghz_chan; | |
523f6701 T |
973 | u32 low_5ghz_chan; |
974 | u32 high_5ghz_chan; | |
b3e71d7a | 975 | bool ani_enabled; |
1382993f WG |
976 | u32 sys_cap_info; |
977 | ||
978 | /* protected by data_lock */ | |
979 | bool hw_rfkill_on; | |
980 | ||
d70c0d46 MK |
981 | /* protected by conf_mutex */ |
982 | u8 ps_state_enable; | |
5e3dd157 | 983 | |
ce834e28 | 984 | bool nlo_enabled; |
5e3dd157 KV |
985 | bool p2p; |
986 | ||
987 | struct { | |
e07db352 | 988 | enum ath10k_bus bus; |
5e3dd157 KV |
989 | const struct ath10k_hif_ops *ops; |
990 | } hif; | |
991 | ||
9042e17d | 992 | struct completion target_suspend; |
0e622f67 | 993 | struct completion driver_recovery; |
5e3dd157 | 994 | |
d63955b3 | 995 | const struct ath10k_hw_regs *regs; |
03a016f8 | 996 | const struct ath10k_hw_ce_regs *hw_ce_regs; |
2f2cfc4a | 997 | const struct ath10k_hw_values *hw_values; |
5e3dd157 | 998 | struct ath10k_bmi bmi; |
edb8236d | 999 | struct ath10k_wmi wmi; |
cd003fad | 1000 | struct ath10k_htc htc; |
edb8236d | 1001 | struct ath10k_htt htt; |
5e3dd157 | 1002 | |
43d923e2 | 1003 | struct ath10k_hw_params hw_params; |
5e3dd157 | 1004 | |
7ebf721d KV |
1005 | /* contains the firmware images used with ATH10K_FIRMWARE_MODE_NORMAL */ |
1006 | struct ath10k_fw_components normal_mode_fw; | |
958df3a0 | 1007 | |
7ebf721d KV |
1008 | /* READ-ONLY images of the running firmware, which can be either |
1009 | * normal or UTF. Do not modify, release etc! | |
1010 | */ | |
1011 | const struct ath10k_fw_components *running_fw; | |
29385057 | 1012 | |
b131129d RM |
1013 | const struct firmware *pre_cal_file; |
1014 | const struct firmware *cal_file; | |
a58227ef | 1015 | |
0a51b343 MP |
1016 | struct { |
1017 | u32 vendor; | |
1018 | u32 device; | |
1019 | u32 subsystem_vendor; | |
1020 | u32 subsystem_device; | |
db0984e5 MP |
1021 | |
1022 | bool bmi_ids_valid; | |
22e8a460 RP |
1023 | bool qmi_ids_valid; |
1024 | u32 qmi_board_id; | |
db0984e5 | 1025 | u8 bmi_board_id; |
31324d17 | 1026 | u8 bmi_eboard_id; |
db0984e5 | 1027 | u8 bmi_chip_id; |
31324d17 | 1028 | bool ext_bid_supported; |
1657b8f8 WR |
1029 | |
1030 | char bdf_ext[ATH10K_SMBIOS_BDF_EXT_STR_LENGTH]; | |
0a51b343 | 1031 | } id; |
de57e2c8 | 1032 | |
1a222435 | 1033 | int fw_api; |
0a51b343 | 1034 | int bd_api; |
a58227ef | 1035 | enum ath10k_cal_mode cal_mode; |
1a222435 | 1036 | |
5e3dd157 KV |
1037 | struct { |
1038 | struct completion started; | |
1039 | struct completion completed; | |
1040 | struct completion on_channel; | |
5c81c7fd MK |
1041 | struct delayed_work timeout; |
1042 | enum ath10k_scan_state state; | |
5e3dd157 | 1043 | bool is_roc; |
5e3dd157 KV |
1044 | int vdev_id; |
1045 | int roc_freq; | |
d710e75d | 1046 | bool roc_notify; |
5e3dd157 KV |
1047 | } scan; |
1048 | ||
1049 | struct { | |
57fbcce3 | 1050 | struct ieee80211_supported_band sbands[NUM_NL80211_BANDS]; |
5e3dd157 KV |
1051 | } mac; |
1052 | ||
1053 | /* should never be NULL; needed for regular htt rx */ | |
1054 | struct ieee80211_channel *rx_channel; | |
1055 | ||
1056 | /* valid during scan; needed for mgmt rx during scan */ | |
1057 | struct ieee80211_channel *scan_channel; | |
1058 | ||
c930f744 MK |
1059 | /* current operating channel definition */ |
1060 | struct cfg80211_chan_def chandef; | |
1061 | ||
2ce9b25c RM |
1062 | /* currently configured operating channel in firmware */ |
1063 | struct ieee80211_channel *tgt_oper_chan; | |
1064 | ||
16c11176 | 1065 | unsigned long long free_vdev_map; |
500ff9f9 | 1066 | struct ath10k_vif *monitor_arvif; |
1bbc0975 | 1067 | bool monitor; |
5e3dd157 | 1068 | int monitor_vdev_id; |
1bbc0975 | 1069 | bool monitor_started; |
5e3dd157 | 1070 | unsigned int filter_flags; |
e8a50f8b | 1071 | unsigned long dev_flags; |
621a5f7a | 1072 | bool dfs_block_radar_events; |
5e3dd157 | 1073 | |
d650097b MK |
1074 | /* protected by conf_mutex */ |
1075 | bool radar_enabled; | |
1076 | int num_started_vdevs; | |
1077 | ||
46acf7bb | 1078 | /* Protected by conf-mutex */ |
46acf7bb BG |
1079 | u8 cfg_tx_chainmask; |
1080 | u8 cfg_rx_chainmask; | |
1081 | ||
5e3dd157 KV |
1082 | struct completion install_key_done; |
1083 | ||
833fd34d | 1084 | int last_wmi_vdev_start_status; |
5e3dd157 | 1085 | struct completion vdev_setup_done; |
fe36e70f | 1086 | struct completion vdev_delete_done; |
5e3dd157 KV |
1087 | |
1088 | struct workqueue_struct *workqueue; | |
c8ecfc1c RM |
1089 | /* Auxiliary workqueue */ |
1090 | struct workqueue_struct *workqueue_aux; | |
5e3dd157 KV |
1091 | |
1092 | /* prevents concurrent FW reconfiguration */ | |
1093 | struct mutex conf_mutex; | |
1094 | ||
38faed15 BN |
1095 | /* protects coredump data */ |
1096 | struct mutex dump_mutex; | |
1097 | ||
5e3dd157 KV |
1098 | /* protects shared structure data */ |
1099 | spinlock_t data_lock; | |
1100 | ||
0579119f | 1101 | struct list_head arvifs; |
5e3dd157 | 1102 | struct list_head peers; |
6942726f | 1103 | struct ath10k_peer *peer_map[ATH10K_MAX_NUM_PEER_IDS]; |
5e3dd157 KV |
1104 | wait_queue_head_t peer_mapping_wq; |
1105 | ||
292a753d | 1106 | /* protected by conf_mutex */ |
0e759f36 | 1107 | int num_peers; |
cfd1061e MK |
1108 | int num_stations; |
1109 | ||
1110 | int max_num_peers; | |
1111 | int max_num_stations; | |
30c78167 | 1112 | int max_num_vdevs; |
8cca3d60 | 1113 | int max_num_tdls_vdevs; |
d1e52a8e RM |
1114 | int num_active_peers; |
1115 | int num_tids; | |
0e759f36 | 1116 | |
c8ecfc1c RM |
1117 | struct work_struct svc_rdy_work; |
1118 | struct sk_buff *svc_rdy_skb; | |
1119 | ||
5e3dd157 KV |
1120 | struct work_struct offchan_tx_work; |
1121 | struct sk_buff_head offchan_tx_queue; | |
1122 | struct completion offchan_tx_completed; | |
1123 | struct sk_buff *offchan_tx_skb; | |
1124 | ||
5e00d31a BM |
1125 | struct work_struct wmi_mgmt_tx_work; |
1126 | struct sk_buff_head wmi_mgmt_tx_queue; | |
1127 | ||
f7843d7f MK |
1128 | enum ath10k_state state; |
1129 | ||
6782cb69 | 1130 | struct work_struct register_work; |
affd3217 MK |
1131 | struct work_struct restart_work; |
1132 | ||
2e1dea40 | 1133 | /* cycle count is reported twice for each visited channel during scan. |
37ff1b0d MR |
1134 | * access protected by data_lock |
1135 | */ | |
2e1dea40 MK |
1136 | u32 survey_last_rx_clear_count; |
1137 | u32 survey_last_cycle_count; | |
1138 | struct survey_info survey[ATH10K_NUM_CHANS]; | |
1139 | ||
44b7d483 MK |
1140 | /* Channel info events are expected to come in pairs without and with |
1141 | * COMPLETE flag set respectively for each channel visit during scan. | |
1142 | * | |
1143 | * However there are deviations from this rule. This flag is used to | |
1144 | * avoid reporting garbage data. | |
1145 | */ | |
1146 | bool ch_info_can_report_survey; | |
fa7937e3 | 1147 | struct completion bss_survey_done; |
44b7d483 | 1148 | |
9702c686 JD |
1149 | struct dfs_pattern_detector *dfs_detector; |
1150 | ||
96d828d4 MK |
1151 | unsigned long tx_paused; /* see ATH10K_TX_PAUSE_ */ |
1152 | ||
5e3dd157 KV |
1153 | #ifdef CONFIG_ATH10K_DEBUGFS |
1154 | struct ath10k_debug debug; | |
855aed12 SW |
1155 | struct { |
1156 | /* relay(fs) channel for spectral scan */ | |
1157 | struct rchan *rfs_chan_spec_scan; | |
1158 | ||
1159 | /* spectral_mode and spec_config are protected by conf_mutex */ | |
1160 | enum ath10k_spectral_mode mode; | |
1161 | struct ath10k_spec_scan config; | |
1162 | } spectral; | |
de46d165 | 1163 | #endif |
e7b54194 | 1164 | |
7f9befbb | 1165 | u32 pktlog_filter; |
e2fcf60c KV |
1166 | |
1167 | #ifdef CONFIG_DEV_COREDUMP | |
1168 | struct { | |
1169 | struct ath10k_fw_crash_data *fw_crash_data; | |
1170 | } coredump; | |
1171 | #endif | |
1172 | ||
43d2a30f KV |
1173 | struct { |
1174 | /* protected by conf_mutex */ | |
7ebf721d | 1175 | struct ath10k_fw_components utf_mode_fw; |
7ebf721d | 1176 | |
43d2a30f KV |
1177 | /* protected by data_lock */ |
1178 | bool utf_monitor; | |
1179 | } testmode; | |
1180 | ||
f51dbe73 BG |
1181 | struct { |
1182 | /* protected by data_lock */ | |
1183 | u32 fw_crash_counter; | |
1184 | u32 fw_warm_reset_counter; | |
1185 | u32 fw_cold_reset_counter; | |
1186 | } stats; | |
1187 | ||
fe6f36d6 | 1188 | struct ath10k_thermal thermal; |
5fd3ac3c | 1189 | struct ath10k_wow wow; |
cec17c38 | 1190 | struct ath10k_per_peer_tx_stats peer_tx_stats; |
fe6f36d6 | 1191 | |
3c97f5de RM |
1192 | /* NAPI */ |
1193 | struct net_device napi_dev; | |
1194 | struct napi_struct napi; | |
1195 | ||
ebee76f7 BB |
1196 | struct work_struct set_coverage_class_work; |
1197 | /* protected by conf_mutex */ | |
1198 | struct { | |
1199 | /* writing also protected by data_lock */ | |
1200 | s16 coverage_class; | |
1201 | ||
1202 | u32 reg_phyclk; | |
1203 | u32 reg_slottime_conf; | |
1204 | u32 reg_slottime_orig; | |
1205 | u32 reg_ack_cts_timeout_conf; | |
1206 | u32 reg_ack_cts_timeout_orig; | |
1207 | } fw_coverage; | |
1208 | ||
47cc0ca9 MF |
1209 | u32 ampdu_reference; |
1210 | ||
7d94f862 | 1211 | const u8 *wmi_key_cipher; |
641fe28a GS |
1212 | void *ce_priv; |
1213 | ||
caee728a VT |
1214 | u32 sta_tid_stats_mask; |
1215 | ||
6f6eb1bc S |
1216 | /* protected by data_lock */ |
1217 | enum ath10k_radar_confirmation_state radar_conf_state; | |
1218 | struct ath10k_radar_found_info last_radar_info; | |
1219 | struct work_struct radar_confirmation_work; | |
de8781d7 | 1220 | struct ath10k_bus_params bus_param; |
c6f537a1 | 1221 | struct completion peer_delete_done; |
6f6eb1bc | 1222 | |
e7b54194 MK |
1223 | /* must be last */ |
1224 | u8 drv_priv[0] __aligned(sizeof(void *)); | |
5e3dd157 KV |
1225 | }; |
1226 | ||
cc61a1bb MSS |
1227 | static inline bool ath10k_peer_stats_enabled(struct ath10k *ar) |
1228 | { | |
1229 | if (test_bit(ATH10K_FLAG_PEER_STATS, &ar->dev_flags) && | |
1230 | test_bit(WMI_SERVICE_PEER_STATS, ar->wmi.svc_map)) | |
1231 | return true; | |
1232 | ||
1233 | return false; | |
1234 | } | |
1235 | ||
5c9d0a20 KV |
1236 | extern unsigned long ath10k_coredump_mask; |
1237 | ||
e7b54194 | 1238 | struct ath10k *ath10k_core_create(size_t priv_size, struct device *dev, |
e07db352 | 1239 | enum ath10k_bus bus, |
d63955b3 | 1240 | enum ath10k_hw_rev hw_rev, |
5e3dd157 KV |
1241 | const struct ath10k_hif_ops *hif_ops); |
1242 | void ath10k_core_destroy(struct ath10k *ar); | |
b27bc5a4 MK |
1243 | void ath10k_core_get_fw_features_str(struct ath10k *ar, |
1244 | char *buf, | |
1245 | size_t max_len); | |
9dfe240b KV |
1246 | int ath10k_core_fetch_firmware_api_n(struct ath10k *ar, const char *name, |
1247 | struct ath10k_fw_file *fw_file); | |
5e3dd157 | 1248 | |
7ebf721d KV |
1249 | int ath10k_core_start(struct ath10k *ar, enum ath10k_firmware_mode mode, |
1250 | const struct ath10k_fw_components *fw_components); | |
00f5482b | 1251 | int ath10k_wait_for_suspend(struct ath10k *ar, u32 suspend_opt); |
dd30a36e | 1252 | void ath10k_core_stop(struct ath10k *ar); |
c0d8d565 ES |
1253 | int ath10k_core_register(struct ath10k *ar, |
1254 | const struct ath10k_bus_params *bus_params); | |
5e3dd157 | 1255 | void ath10k_core_unregister(struct ath10k *ar); |
ba94c753 GS |
1256 | int ath10k_core_fetch_board_file(struct ath10k *ar, int bd_ie_type); |
1257 | void ath10k_core_free_board_files(struct ath10k *ar); | |
5e3dd157 | 1258 | |
5e3dd157 | 1259 | #endif /* _CORE_H_ */ |