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ath10k: setup rx channel per ppdu
[mirror_ubuntu-zesty-kernel.git] / drivers / net / wireless / ath / ath10k / htt_rx.c
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1/*
2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
edb8236d 18#include "core.h"
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19#include "htc.h"
20#include "htt.h"
21#include "txrx.h"
22#include "debug.h"
a9bf0506 23#include "trace.h"
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24
25#include <linux/log2.h>
26
27/* slightly larger than one large A-MPDU */
28#define HTT_RX_RING_SIZE_MIN 128
29
30/* roughly 20 ms @ 1 Gbps of 1500B MSDUs */
31#define HTT_RX_RING_SIZE_MAX 2048
32
33#define HTT_RX_AVG_FRM_BYTES 1000
34
35/* ms, very conservative */
36#define HTT_RX_HOST_LATENCY_MAX_MS 20
37
38/* ms, conservative */
39#define HTT_RX_HOST_LATENCY_WORST_LIKELY_MS 10
40
41/* when under memory pressure rx ring refill may fail and needs a retry */
42#define HTT_RX_RING_REFILL_RETRY_MS 50
43
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44
45static int ath10k_htt_rx_get_csum_state(struct sk_buff *skb);
6c5151a9 46static void ath10k_htt_txrx_compl_task(unsigned long ptr);
f6dc2095 47
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48static int ath10k_htt_rx_ring_size(struct ath10k_htt *htt)
49{
50 int size;
51
52 /*
53 * It is expected that the host CPU will typically be able to
54 * service the rx indication from one A-MPDU before the rx
55 * indication from the subsequent A-MPDU happens, roughly 1-2 ms
56 * later. However, the rx ring should be sized very conservatively,
57 * to accomodate the worst reasonable delay before the host CPU
58 * services a rx indication interrupt.
59 *
60 * The rx ring need not be kept full of empty buffers. In theory,
61 * the htt host SW can dynamically track the low-water mark in the
62 * rx ring, and dynamically adjust the level to which the rx ring
63 * is filled with empty buffers, to dynamically meet the desired
64 * low-water mark.
65 *
66 * In contrast, it's difficult to resize the rx ring itself, once
67 * it's in use. Thus, the ring itself should be sized very
68 * conservatively, while the degree to which the ring is filled
69 * with empty buffers should be sized moderately conservatively.
70 */
71
72 /* 1e6 bps/mbps / 1e3 ms per sec = 1000 */
73 size =
74 htt->max_throughput_mbps +
75 1000 /
76 (8 * HTT_RX_AVG_FRM_BYTES) * HTT_RX_HOST_LATENCY_MAX_MS;
77
78 if (size < HTT_RX_RING_SIZE_MIN)
79 size = HTT_RX_RING_SIZE_MIN;
80
81 if (size > HTT_RX_RING_SIZE_MAX)
82 size = HTT_RX_RING_SIZE_MAX;
83
84 size = roundup_pow_of_two(size);
85
86 return size;
87}
88
89static int ath10k_htt_rx_ring_fill_level(struct ath10k_htt *htt)
90{
91 int size;
92
93 /* 1e6 bps/mbps / 1e3 ms per sec = 1000 */
94 size =
95 htt->max_throughput_mbps *
96 1000 /
97 (8 * HTT_RX_AVG_FRM_BYTES) * HTT_RX_HOST_LATENCY_WORST_LIKELY_MS;
98
99 /*
100 * Make sure the fill level is at least 1 less than the ring size.
101 * Leaving 1 element empty allows the SW to easily distinguish
102 * between a full ring vs. an empty ring.
103 */
104 if (size >= htt->rx_ring.size)
105 size = htt->rx_ring.size - 1;
106
107 return size;
108}
109
110static void ath10k_htt_rx_ring_free(struct ath10k_htt *htt)
111{
112 struct sk_buff *skb;
113 struct ath10k_skb_cb *cb;
114 int i;
115
116 for (i = 0; i < htt->rx_ring.fill_cnt; i++) {
117 skb = htt->rx_ring.netbufs_ring[i];
118 cb = ATH10K_SKB_CB(skb);
119 dma_unmap_single(htt->ar->dev, cb->paddr,
120 skb->len + skb_tailroom(skb),
121 DMA_FROM_DEVICE);
122 dev_kfree_skb_any(skb);
123 }
124
125 htt->rx_ring.fill_cnt = 0;
126}
127
128static int __ath10k_htt_rx_ring_fill_n(struct ath10k_htt *htt, int num)
129{
130 struct htt_rx_desc *rx_desc;
131 struct sk_buff *skb;
132 dma_addr_t paddr;
133 int ret = 0, idx;
134
135 idx = __le32_to_cpu(*(htt->rx_ring.alloc_idx.vaddr));
136 while (num > 0) {
137 skb = dev_alloc_skb(HTT_RX_BUF_SIZE + HTT_RX_DESC_ALIGN);
138 if (!skb) {
139 ret = -ENOMEM;
140 goto fail;
141 }
142
143 if (!IS_ALIGNED((unsigned long)skb->data, HTT_RX_DESC_ALIGN))
144 skb_pull(skb,
145 PTR_ALIGN(skb->data, HTT_RX_DESC_ALIGN) -
146 skb->data);
147
148 /* Clear rx_desc attention word before posting to Rx ring */
149 rx_desc = (struct htt_rx_desc *)skb->data;
150 rx_desc->attention.flags = __cpu_to_le32(0);
151
152 paddr = dma_map_single(htt->ar->dev, skb->data,
153 skb->len + skb_tailroom(skb),
154 DMA_FROM_DEVICE);
155
156 if (unlikely(dma_mapping_error(htt->ar->dev, paddr))) {
157 dev_kfree_skb_any(skb);
158 ret = -ENOMEM;
159 goto fail;
160 }
161
162 ATH10K_SKB_CB(skb)->paddr = paddr;
163 htt->rx_ring.netbufs_ring[idx] = skb;
164 htt->rx_ring.paddrs_ring[idx] = __cpu_to_le32(paddr);
165 htt->rx_ring.fill_cnt++;
166
167 num--;
168 idx++;
169 idx &= htt->rx_ring.size_mask;
170 }
171
172fail:
173 *(htt->rx_ring.alloc_idx.vaddr) = __cpu_to_le32(idx);
174 return ret;
175}
176
177static int ath10k_htt_rx_ring_fill_n(struct ath10k_htt *htt, int num)
178{
179 lockdep_assert_held(&htt->rx_ring.lock);
180 return __ath10k_htt_rx_ring_fill_n(htt, num);
181}
182
183static void ath10k_htt_rx_msdu_buff_replenish(struct ath10k_htt *htt)
184{
6e712d42 185 int ret, num_deficit, num_to_fill;
5e3dd157 186
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187 /* Refilling the whole RX ring buffer proves to be a bad idea. The
188 * reason is RX may take up significant amount of CPU cycles and starve
189 * other tasks, e.g. TX on an ethernet device while acting as a bridge
190 * with ath10k wlan interface. This ended up with very poor performance
191 * once CPU the host system was overwhelmed with RX on ath10k.
192 *
193 * By limiting the number of refills the replenishing occurs
194 * progressively. This in turns makes use of the fact tasklets are
195 * processed in FIFO order. This means actual RX processing can starve
196 * out refilling. If there's not enough buffers on RX ring FW will not
197 * report RX until it is refilled with enough buffers. This
198 * automatically balances load wrt to CPU power.
199 *
200 * This probably comes at a cost of lower maximum throughput but
201 * improves the avarage and stability. */
5e3dd157 202 spin_lock_bh(&htt->rx_ring.lock);
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203 num_deficit = htt->rx_ring.fill_level - htt->rx_ring.fill_cnt;
204 num_to_fill = min(ATH10K_HTT_MAX_NUM_REFILL, num_deficit);
205 num_deficit -= num_to_fill;
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206 ret = ath10k_htt_rx_ring_fill_n(htt, num_to_fill);
207 if (ret == -ENOMEM) {
208 /*
209 * Failed to fill it to the desired level -
210 * we'll start a timer and try again next time.
211 * As long as enough buffers are left in the ring for
212 * another A-MPDU rx, no special recovery is needed.
213 */
214 mod_timer(&htt->rx_ring.refill_retry_timer, jiffies +
215 msecs_to_jiffies(HTT_RX_RING_REFILL_RETRY_MS));
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216 } else if (num_deficit > 0) {
217 tasklet_schedule(&htt->rx_replenish_task);
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218 }
219 spin_unlock_bh(&htt->rx_ring.lock);
220}
221
222static void ath10k_htt_rx_ring_refill_retry(unsigned long arg)
223{
224 struct ath10k_htt *htt = (struct ath10k_htt *)arg;
225 ath10k_htt_rx_msdu_buff_replenish(htt);
226}
227
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228void ath10k_htt_rx_detach(struct ath10k_htt *htt)
229{
230 int sw_rd_idx = htt->rx_ring.sw_rd_idx.msdu_payld;
231
232 del_timer_sync(&htt->rx_ring.refill_retry_timer);
6e712d42 233 tasklet_kill(&htt->rx_replenish_task);
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234 tasklet_kill(&htt->txrx_compl_task);
235
236 skb_queue_purge(&htt->tx_compl_q);
237 skb_queue_purge(&htt->rx_compl_q);
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238
239 while (sw_rd_idx != __le32_to_cpu(*(htt->rx_ring.alloc_idx.vaddr))) {
240 struct sk_buff *skb =
241 htt->rx_ring.netbufs_ring[sw_rd_idx];
242 struct ath10k_skb_cb *cb = ATH10K_SKB_CB(skb);
243
244 dma_unmap_single(htt->ar->dev, cb->paddr,
245 skb->len + skb_tailroom(skb),
246 DMA_FROM_DEVICE);
247 dev_kfree_skb_any(htt->rx_ring.netbufs_ring[sw_rd_idx]);
248 sw_rd_idx++;
249 sw_rd_idx &= htt->rx_ring.size_mask;
250 }
251
252 dma_free_coherent(htt->ar->dev,
253 (htt->rx_ring.size *
254 sizeof(htt->rx_ring.paddrs_ring)),
255 htt->rx_ring.paddrs_ring,
256 htt->rx_ring.base_paddr);
257
258 dma_free_coherent(htt->ar->dev,
259 sizeof(*htt->rx_ring.alloc_idx.vaddr),
260 htt->rx_ring.alloc_idx.vaddr,
261 htt->rx_ring.alloc_idx.paddr);
262
263 kfree(htt->rx_ring.netbufs_ring);
264}
265
266static inline struct sk_buff *ath10k_htt_rx_netbuf_pop(struct ath10k_htt *htt)
267{
268 int idx;
269 struct sk_buff *msdu;
270
45967089 271 lockdep_assert_held(&htt->rx_ring.lock);
5e3dd157 272
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273 if (htt->rx_ring.fill_cnt == 0) {
274 ath10k_warn("tried to pop sk_buff from an empty rx ring\n");
275 return NULL;
276 }
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277
278 idx = htt->rx_ring.sw_rd_idx.msdu_payld;
279 msdu = htt->rx_ring.netbufs_ring[idx];
280
281 idx++;
282 idx &= htt->rx_ring.size_mask;
283 htt->rx_ring.sw_rd_idx.msdu_payld = idx;
284 htt->rx_ring.fill_cnt--;
285
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286 return msdu;
287}
288
289static void ath10k_htt_rx_free_msdu_chain(struct sk_buff *skb)
290{
291 struct sk_buff *next;
292
293 while (skb) {
294 next = skb->next;
295 dev_kfree_skb_any(skb);
296 skb = next;
297 }
298}
299
300static int ath10k_htt_rx_amsdu_pop(struct ath10k_htt *htt,
301 u8 **fw_desc, int *fw_desc_len,
302 struct sk_buff **head_msdu,
303 struct sk_buff **tail_msdu)
304{
305 int msdu_len, msdu_chaining = 0;
306 struct sk_buff *msdu;
307 struct htt_rx_desc *rx_desc;
308
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309 lockdep_assert_held(&htt->rx_ring.lock);
310
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311 if (htt->rx_confused) {
312 ath10k_warn("htt is confused. refusing rx\n");
313 return 0;
314 }
315
316 msdu = *head_msdu = ath10k_htt_rx_netbuf_pop(htt);
317 while (msdu) {
318 int last_msdu, msdu_len_invalid, msdu_chained;
319
320 dma_unmap_single(htt->ar->dev,
321 ATH10K_SKB_CB(msdu)->paddr,
322 msdu->len + skb_tailroom(msdu),
323 DMA_FROM_DEVICE);
324
75fb2f94 325 ath10k_dbg_dump(ATH10K_DBG_HTT_DUMP, NULL, "htt rx pop: ",
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326 msdu->data, msdu->len + skb_tailroom(msdu));
327
328 rx_desc = (struct htt_rx_desc *)msdu->data;
329
330 /* FIXME: we must report msdu payload since this is what caller
331 * expects now */
332 skb_put(msdu, offsetof(struct htt_rx_desc, msdu_payload));
333 skb_pull(msdu, offsetof(struct htt_rx_desc, msdu_payload));
334
335 /*
336 * Sanity check - confirm the HW is finished filling in the
337 * rx data.
338 * If the HW and SW are working correctly, then it's guaranteed
339 * that the HW's MAC DMA is done before this point in the SW.
340 * To prevent the case that we handle a stale Rx descriptor,
341 * just assert for now until we have a way to recover.
342 */
343 if (!(__le32_to_cpu(rx_desc->attention.flags)
344 & RX_ATTENTION_FLAGS_MSDU_DONE)) {
345 ath10k_htt_rx_free_msdu_chain(*head_msdu);
346 *head_msdu = NULL;
347 msdu = NULL;
348 ath10k_err("htt rx stopped. cannot recover\n");
349 htt->rx_confused = true;
350 break;
351 }
352
353 /*
354 * Copy the FW rx descriptor for this MSDU from the rx
355 * indication message into the MSDU's netbuf. HL uses the
356 * same rx indication message definition as LL, and simply
357 * appends new info (fields from the HW rx desc, and the
358 * MSDU payload itself). So, the offset into the rx
359 * indication message only has to account for the standard
360 * offset of the per-MSDU FW rx desc info within the
361 * message, and how many bytes of the per-MSDU FW rx desc
362 * info have already been consumed. (And the endianness of
363 * the host, since for a big-endian host, the rx ind
364 * message contents, including the per-MSDU rx desc bytes,
365 * were byteswapped during upload.)
366 */
367 if (*fw_desc_len > 0) {
368 rx_desc->fw_desc.info0 = **fw_desc;
369 /*
370 * The target is expected to only provide the basic
371 * per-MSDU rx descriptors. Just to be sure, verify
372 * that the target has not attached extension data
373 * (e.g. LRO flow ID).
374 */
375
376 /* or more, if there's extension data */
377 (*fw_desc)++;
378 (*fw_desc_len)--;
379 } else {
380 /*
381 * When an oversized AMSDU happened, FW will lost
382 * some of MSDU status - in this case, the FW
383 * descriptors provided will be less than the
384 * actual MSDUs inside this MPDU. Mark the FW
385 * descriptors so that it will still deliver to
386 * upper stack, if no CRC error for this MPDU.
387 *
388 * FIX THIS - the FW descriptors are actually for
389 * MSDUs in the end of this A-MSDU instead of the
390 * beginning.
391 */
392 rx_desc->fw_desc.info0 = 0;
393 }
394
395 msdu_len_invalid = !!(__le32_to_cpu(rx_desc->attention.flags)
396 & (RX_ATTENTION_FLAGS_MPDU_LENGTH_ERR |
397 RX_ATTENTION_FLAGS_MSDU_LENGTH_ERR));
398 msdu_len = MS(__le32_to_cpu(rx_desc->msdu_start.info0),
399 RX_MSDU_START_INFO0_MSDU_LENGTH);
400 msdu_chained = rx_desc->frag_info.ring2_more_count;
bfa35368 401 msdu_chaining = msdu_chained;
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402
403 if (msdu_len_invalid)
404 msdu_len = 0;
405
406 skb_trim(msdu, 0);
407 skb_put(msdu, min(msdu_len, HTT_RX_MSDU_SIZE));
408 msdu_len -= msdu->len;
409
410 /* FIXME: Do chained buffers include htt_rx_desc or not? */
411 while (msdu_chained--) {
412 struct sk_buff *next = ath10k_htt_rx_netbuf_pop(htt);
413
414 dma_unmap_single(htt->ar->dev,
415 ATH10K_SKB_CB(next)->paddr,
416 next->len + skb_tailroom(next),
417 DMA_FROM_DEVICE);
418
75fb2f94
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419 ath10k_dbg_dump(ATH10K_DBG_HTT_DUMP, NULL,
420 "htt rx chained: ", next->data,
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421 next->len + skb_tailroom(next));
422
423 skb_trim(next, 0);
424 skb_put(next, min(msdu_len, HTT_RX_BUF_SIZE));
425 msdu_len -= next->len;
426
427 msdu->next = next;
428 msdu = next;
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429 }
430
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431 last_msdu = __le32_to_cpu(rx_desc->msdu_end.info0) &
432 RX_MSDU_END_INFO0_LAST_MSDU;
433
434 if (last_msdu) {
435 msdu->next = NULL;
436 break;
437 } else {
438 struct sk_buff *next = ath10k_htt_rx_netbuf_pop(htt);
439 msdu->next = next;
440 msdu = next;
441 }
442 }
443 *tail_msdu = msdu;
444
445 /*
446 * Don't refill the ring yet.
447 *
448 * First, the elements popped here are still in use - it is not
449 * safe to overwrite them until the matching call to
450 * mpdu_desc_list_next. Second, for efficiency it is preferable to
451 * refill the rx ring with 1 PPDU's worth of rx buffers (something
452 * like 32 x 3 buffers), rather than one MPDU's worth of rx buffers
453 * (something like 3 buffers). Consequently, we'll rely on the txrx
454 * SW to tell us when it is done pulling all the PPDU's rx buffers
455 * out of the rx ring, and then refill it just once.
456 */
457
458 return msdu_chaining;
459}
460
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461static void ath10k_htt_rx_replenish_task(unsigned long ptr)
462{
463 struct ath10k_htt *htt = (struct ath10k_htt *)ptr;
464 ath10k_htt_rx_msdu_buff_replenish(htt);
465}
466
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467int ath10k_htt_rx_attach(struct ath10k_htt *htt)
468{
469 dma_addr_t paddr;
470 void *vaddr;
471 struct timer_list *timer = &htt->rx_ring.refill_retry_timer;
472
473 htt->rx_ring.size = ath10k_htt_rx_ring_size(htt);
474 if (!is_power_of_2(htt->rx_ring.size)) {
475 ath10k_warn("htt rx ring size is not power of 2\n");
476 return -EINVAL;
477 }
478
479 htt->rx_ring.size_mask = htt->rx_ring.size - 1;
480
481 /*
482 * Set the initial value for the level to which the rx ring
483 * should be filled, based on the max throughput and the
484 * worst likely latency for the host to fill the rx ring
485 * with new buffers. In theory, this fill level can be
486 * dynamically adjusted from the initial value set here, to
487 * reflect the actual host latency rather than a
488 * conservative assumption about the host latency.
489 */
490 htt->rx_ring.fill_level = ath10k_htt_rx_ring_fill_level(htt);
491
492 htt->rx_ring.netbufs_ring =
493 kmalloc(htt->rx_ring.size * sizeof(struct sk_buff *),
494 GFP_KERNEL);
495 if (!htt->rx_ring.netbufs_ring)
496 goto err_netbuf;
497
498 vaddr = dma_alloc_coherent(htt->ar->dev,
499 (htt->rx_ring.size * sizeof(htt->rx_ring.paddrs_ring)),
500 &paddr, GFP_DMA);
501 if (!vaddr)
502 goto err_dma_ring;
503
504 htt->rx_ring.paddrs_ring = vaddr;
505 htt->rx_ring.base_paddr = paddr;
506
507 vaddr = dma_alloc_coherent(htt->ar->dev,
508 sizeof(*htt->rx_ring.alloc_idx.vaddr),
509 &paddr, GFP_DMA);
510 if (!vaddr)
511 goto err_dma_idx;
512
513 htt->rx_ring.alloc_idx.vaddr = vaddr;
514 htt->rx_ring.alloc_idx.paddr = paddr;
515 htt->rx_ring.sw_rd_idx.msdu_payld = 0;
516 *htt->rx_ring.alloc_idx.vaddr = 0;
517
518 /* Initialize the Rx refill retry timer */
519 setup_timer(timer, ath10k_htt_rx_ring_refill_retry, (unsigned long)htt);
520
521 spin_lock_init(&htt->rx_ring.lock);
522
523 htt->rx_ring.fill_cnt = 0;
524 if (__ath10k_htt_rx_ring_fill_n(htt, htt->rx_ring.fill_level))
525 goto err_fill_ring;
526
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527 tasklet_init(&htt->rx_replenish_task, ath10k_htt_rx_replenish_task,
528 (unsigned long)htt);
529
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530 skb_queue_head_init(&htt->tx_compl_q);
531 skb_queue_head_init(&htt->rx_compl_q);
532
533 tasklet_init(&htt->txrx_compl_task, ath10k_htt_txrx_compl_task,
534 (unsigned long)htt);
535
aad0b65f 536 ath10k_dbg(ATH10K_DBG_BOOT, "htt rx ring size %d fill_level %d\n",
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537 htt->rx_ring.size, htt->rx_ring.fill_level);
538 return 0;
539
540err_fill_ring:
541 ath10k_htt_rx_ring_free(htt);
542 dma_free_coherent(htt->ar->dev,
543 sizeof(*htt->rx_ring.alloc_idx.vaddr),
544 htt->rx_ring.alloc_idx.vaddr,
545 htt->rx_ring.alloc_idx.paddr);
546err_dma_idx:
547 dma_free_coherent(htt->ar->dev,
548 (htt->rx_ring.size *
549 sizeof(htt->rx_ring.paddrs_ring)),
550 htt->rx_ring.paddrs_ring,
551 htt->rx_ring.base_paddr);
552err_dma_ring:
553 kfree(htt->rx_ring.netbufs_ring);
554err_netbuf:
555 return -ENOMEM;
556}
557
558static int ath10k_htt_rx_crypto_param_len(enum htt_rx_mpdu_encrypt_type type)
559{
560 switch (type) {
561 case HTT_RX_MPDU_ENCRYPT_WEP40:
562 case HTT_RX_MPDU_ENCRYPT_WEP104:
563 return 4;
564 case HTT_RX_MPDU_ENCRYPT_TKIP_WITHOUT_MIC:
565 case HTT_RX_MPDU_ENCRYPT_WEP128: /* not tested */
566 case HTT_RX_MPDU_ENCRYPT_TKIP_WPA:
567 case HTT_RX_MPDU_ENCRYPT_WAPI: /* not tested */
568 case HTT_RX_MPDU_ENCRYPT_AES_CCM_WPA2:
569 return 8;
570 case HTT_RX_MPDU_ENCRYPT_NONE:
571 return 0;
572 }
573
574 ath10k_warn("unknown encryption type %d\n", type);
575 return 0;
576}
577
578static int ath10k_htt_rx_crypto_tail_len(enum htt_rx_mpdu_encrypt_type type)
579{
580 switch (type) {
581 case HTT_RX_MPDU_ENCRYPT_NONE:
582 case HTT_RX_MPDU_ENCRYPT_WEP40:
583 case HTT_RX_MPDU_ENCRYPT_WEP104:
584 case HTT_RX_MPDU_ENCRYPT_WEP128:
585 case HTT_RX_MPDU_ENCRYPT_WAPI:
586 return 0;
587 case HTT_RX_MPDU_ENCRYPT_TKIP_WITHOUT_MIC:
588 case HTT_RX_MPDU_ENCRYPT_TKIP_WPA:
589 return 4;
590 case HTT_RX_MPDU_ENCRYPT_AES_CCM_WPA2:
591 return 8;
592 }
593
594 ath10k_warn("unknown encryption type %d\n", type);
595 return 0;
596}
597
598/* Applies for first msdu in chain, before altering it. */
599static struct ieee80211_hdr *ath10k_htt_rx_skb_get_hdr(struct sk_buff *skb)
600{
601 struct htt_rx_desc *rxd;
602 enum rx_msdu_decap_format fmt;
603
604 rxd = (void *)skb->data - sizeof(*rxd);
605 fmt = MS(__le32_to_cpu(rxd->msdu_start.info1),
606 RX_MSDU_START_INFO1_DECAP_FORMAT);
607
608 if (fmt == RX_MSDU_DECAP_RAW)
609 return (void *)skb->data;
610 else
611 return (void *)skb->data - RX_HTT_HDR_STATUS_LEN;
612}
613
614/* This function only applies for first msdu in an msdu chain */
615static bool ath10k_htt_rx_hdr_is_amsdu(struct ieee80211_hdr *hdr)
616{
617 if (ieee80211_is_data_qos(hdr->frame_control)) {
618 u8 *qc = ieee80211_get_qos_ctl(hdr);
619 if (qc[0] & 0x80)
620 return true;
621 }
622 return false;
623}
624
f6dc2095
MK
625struct rfc1042_hdr {
626 u8 llc_dsap;
627 u8 llc_ssap;
628 u8 llc_ctrl;
629 u8 snap_oui[3];
630 __be16 snap_type;
631} __packed;
632
633struct amsdu_subframe_hdr {
634 u8 dst[ETH_ALEN];
635 u8 src[ETH_ALEN];
636 __be16 len;
637} __packed;
638
73539b40
JD
639static const u8 rx_legacy_rate_idx[] = {
640 3, /* 0x00 - 11Mbps */
641 2, /* 0x01 - 5.5Mbps */
642 1, /* 0x02 - 2Mbps */
643 0, /* 0x03 - 1Mbps */
644 3, /* 0x04 - 11Mbps */
645 2, /* 0x05 - 5.5Mbps */
646 1, /* 0x06 - 2Mbps */
647 0, /* 0x07 - 1Mbps */
648 10, /* 0x08 - 48Mbps */
649 8, /* 0x09 - 24Mbps */
650 6, /* 0x0A - 12Mbps */
651 4, /* 0x0B - 6Mbps */
652 11, /* 0x0C - 54Mbps */
653 9, /* 0x0D - 36Mbps */
654 7, /* 0x0E - 18Mbps */
655 5, /* 0x0F - 9Mbps */
656};
657
cfadd9ba
JD
658static void ath10k_htt_rx_h_rates(struct ath10k *ar, struct htt_rx_info *info,
659 enum ieee80211_band band,
660 struct ieee80211_rx_status *status)
73539b40
JD
661{
662 u8 cck, rate, rate_idx, bw, sgi, mcs, nss;
663 u8 info0 = info->rate.info0;
664 u32 info1 = info->rate.info1;
665 u32 info2 = info->rate.info2;
666 u8 preamble = 0;
667
668 /* Check if valid fields */
669 if (!(info0 & HTT_RX_INDICATION_INFO0_START_VALID))
670 return;
671
672 preamble = MS(info1, HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE);
673
674 switch (preamble) {
675 case HTT_RX_LEGACY:
676 cck = info0 & HTT_RX_INDICATION_INFO0_LEGACY_RATE_CCK;
677 rate = MS(info0, HTT_RX_INDICATION_INFO0_LEGACY_RATE);
678 rate_idx = 0;
679
680 if (rate < 0x08 || rate > 0x0F)
681 break;
682
683 switch (band) {
684 case IEEE80211_BAND_2GHZ:
685 if (cck)
686 rate &= ~BIT(3);
687 rate_idx = rx_legacy_rate_idx[rate];
688 break;
689 case IEEE80211_BAND_5GHZ:
690 rate_idx = rx_legacy_rate_idx[rate];
691 /* We are using same rate table registering
692 HW - ath10k_rates[]. In case of 5GHz skip
693 CCK rates, so -4 here */
694 rate_idx -= 4;
695 break;
696 default:
697 break;
698 }
699
700 status->rate_idx = rate_idx;
701 break;
702 case HTT_RX_HT:
703 case HTT_RX_HT_WITH_TXBF:
704 /* HT-SIG - Table 20-11 in info1 and info2 */
705 mcs = info1 & 0x1F;
706 nss = mcs >> 3;
707 bw = (info1 >> 7) & 1;
708 sgi = (info2 >> 7) & 1;
709
710 status->rate_idx = mcs;
711 status->flag |= RX_FLAG_HT;
712 if (sgi)
713 status->flag |= RX_FLAG_SHORT_GI;
714 if (bw)
715 status->flag |= RX_FLAG_40MHZ;
716 break;
717 case HTT_RX_VHT:
718 case HTT_RX_VHT_WITH_TXBF:
719 /* VHT-SIG-A1 in info 1, VHT-SIG-A2 in info2
720 TODO check this */
721 mcs = (info2 >> 4) & 0x0F;
722 nss = ((info1 >> 10) & 0x07) + 1;
723 bw = info1 & 3;
724 sgi = info2 & 1;
725
726 status->rate_idx = mcs;
727 status->vht_nss = nss;
728
729 if (sgi)
730 status->flag |= RX_FLAG_SHORT_GI;
731
732 switch (bw) {
733 /* 20MHZ */
734 case 0:
735 break;
736 /* 40MHZ */
737 case 1:
738 status->flag |= RX_FLAG_40MHZ;
739 break;
740 /* 80MHZ */
741 case 2:
742 status->vht_flag |= RX_VHT_FLAG_80MHZ;
743 }
744
745 status->flag |= RX_FLAG_VHT;
746 break;
747 default:
748 break;
749 }
750}
751
36653f05
JD
752static bool ath10k_htt_rx_h_channel(struct ath10k *ar,
753 struct ieee80211_rx_status *status)
754{
755 struct ieee80211_channel *ch;
756
757 spin_lock_bh(&ar->data_lock);
758 ch = ar->scan_channel;
759 if (!ch)
760 ch = ar->rx_channel;
761 spin_unlock_bh(&ar->data_lock);
762
763 if (!ch)
764 return false;
765
766 status->band = ch->band;
767 status->freq = ch->center_freq;
768
769 return true;
770}
771
73539b40
JD
772static void ath10k_process_rx(struct ath10k *ar, struct htt_rx_info *info)
773{
774 struct ieee80211_rx_status *status;
73539b40
JD
775 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)info->skb->data;
776
777 status = IEEE80211_SKB_RXCB(info->skb);
8f739db0 778 memcpy(status, &info->rx_status, sizeof(*status));
73539b40
JD
779
780 if (info->encrypt_type != HTT_RX_MPDU_ENCRYPT_NONE) {
781 status->flag |= RX_FLAG_DECRYPTED | RX_FLAG_IV_STRIPPED |
782 RX_FLAG_MMIC_STRIPPED;
783 hdr->frame_control = __cpu_to_le16(
784 __le16_to_cpu(hdr->frame_control) &
785 ~IEEE80211_FCTL_PROTECTED);
786 }
787
788 if (info->mic_err)
789 status->flag |= RX_FLAG_MMIC_ERROR;
790
791 if (info->fcs_err)
792 status->flag |= RX_FLAG_FAILED_FCS_CRC;
793
794 if (info->amsdu_more)
795 status->flag |= RX_FLAG_AMSDU_MORE;
796
797 status->signal = info->signal;
798
36653f05 799 ath10k_htt_rx_h_rates(ar, info, status->band, status);
73539b40
JD
800
801 if (info->rate.info0 & HTT_RX_INDICATION_INFO0_END_VALID) {
802 /* TSF available only in 32-bit */
803 status->mactime = info->tsf & 0xffffffff;
804 status->flag |= RX_FLAG_MACTIME_END;
805 }
806
807 ath10k_dbg(ATH10K_DBG_DATA,
808 "rx skb %p len %u %s%s%s%s%s %srate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i\n",
809 info->skb,
810 info->skb->len,
811 status->flag == 0 ? "legacy" : "",
812 status->flag & RX_FLAG_HT ? "ht" : "",
813 status->flag & RX_FLAG_VHT ? "vht" : "",
814 status->flag & RX_FLAG_40MHZ ? "40" : "",
815 status->vht_flag & RX_VHT_FLAG_80MHZ ? "80" : "",
816 status->flag & RX_FLAG_SHORT_GI ? "sgi " : "",
817 status->rate_idx,
818 status->vht_nss,
819 status->freq,
820 status->band, status->flag, info->fcs_err);
821 ath10k_dbg_dump(ATH10K_DBG_HTT_DUMP, NULL, "rx skb: ",
822 info->skb->data, info->skb->len);
823
824 ieee80211_rx(ar->hw, info->skb);
825}
826
d960c369
MK
827static int ath10k_htt_rx_nwifi_hdrlen(struct ieee80211_hdr *hdr)
828{
829 /* nwifi header is padded to 4 bytes. this fixes 4addr rx */
830 return round_up(ieee80211_hdrlen(hdr->frame_control), 4);
831}
832
f6dc2095
MK
833static void ath10k_htt_rx_amsdu(struct ath10k_htt *htt,
834 struct htt_rx_info *info)
5e3dd157
KV
835{
836 struct htt_rx_desc *rxd;
5e3dd157 837 struct sk_buff *first;
5e3dd157
KV
838 struct sk_buff *skb = info->skb;
839 enum rx_msdu_decap_format fmt;
840 enum htt_rx_mpdu_encrypt_type enctype;
f6dc2095 841 struct ieee80211_hdr *hdr;
784f69d3 842 u8 hdr_buf[64], addr[ETH_ALEN], *qos;
5e3dd157 843 unsigned int hdr_len;
5e3dd157
KV
844
845 rxd = (void *)skb->data - sizeof(*rxd);
5e3dd157
KV
846 enctype = MS(__le32_to_cpu(rxd->mpdu_start.info0),
847 RX_MPDU_START_INFO0_ENCRYPT_TYPE);
848
f6dc2095
MK
849 hdr = (struct ieee80211_hdr *)rxd->rx_hdr_status;
850 hdr_len = ieee80211_hdrlen(hdr->frame_control);
851 memcpy(hdr_buf, hdr, hdr_len);
852 hdr = (struct ieee80211_hdr *)hdr_buf;
5e3dd157 853
5e3dd157
KV
854 first = skb;
855 while (skb) {
856 void *decap_hdr;
f6dc2095 857 int len;
5e3dd157
KV
858
859 rxd = (void *)skb->data - sizeof(*rxd);
860 fmt = MS(__le32_to_cpu(rxd->msdu_start.info1),
f6dc2095 861 RX_MSDU_START_INFO1_DECAP_FORMAT);
5e3dd157
KV
862 decap_hdr = (void *)rxd->rx_hdr_status;
863
f6dc2095 864 skb->ip_summed = ath10k_htt_rx_get_csum_state(skb);
5e3dd157 865
f6dc2095
MK
866 /* First frame in an A-MSDU chain has more decapped data. */
867 if (skb == first) {
868 len = round_up(ieee80211_hdrlen(hdr->frame_control), 4);
869 len += round_up(ath10k_htt_rx_crypto_param_len(enctype),
870 4);
871 decap_hdr += len;
5e3dd157
KV
872 }
873
f6dc2095
MK
874 switch (fmt) {
875 case RX_MSDU_DECAP_RAW:
e3fbf8d2 876 /* remove trailing FCS */
f6dc2095
MK
877 skb_trim(skb, skb->len - FCS_LEN);
878 break;
879 case RX_MSDU_DECAP_NATIVE_WIFI:
784f69d3
MK
880 /* pull decapped header and copy DA */
881 hdr = (struct ieee80211_hdr *)skb->data;
d960c369 882 hdr_len = ath10k_htt_rx_nwifi_hdrlen(hdr);
784f69d3
MK
883 memcpy(addr, ieee80211_get_DA(hdr), ETH_ALEN);
884 skb_pull(skb, hdr_len);
885
886 /* push original 802.11 header */
887 hdr = (struct ieee80211_hdr *)hdr_buf;
888 hdr_len = ieee80211_hdrlen(hdr->frame_control);
889 memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
890
891 /* original A-MSDU header has the bit set but we're
892 * not including A-MSDU subframe header */
893 hdr = (struct ieee80211_hdr *)skb->data;
894 qos = ieee80211_get_qos_ctl(hdr);
895 qos[0] &= ~IEEE80211_QOS_CTL_A_MSDU_PRESENT;
896
897 /* original 802.11 header has a different DA */
898 memcpy(ieee80211_get_DA(hdr), addr, ETH_ALEN);
f6dc2095
MK
899 break;
900 case RX_MSDU_DECAP_ETHERNET2_DIX:
e3fbf8d2
MK
901 /* strip ethernet header and insert decapped 802.11
902 * header, amsdu subframe header and rfc1042 header */
903
f6dc2095
MK
904 len = 0;
905 len += sizeof(struct rfc1042_hdr);
906 len += sizeof(struct amsdu_subframe_hdr);
907
908 skb_pull(skb, sizeof(struct ethhdr));
909 memcpy(skb_push(skb, len), decap_hdr, len);
910 memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
911 break;
912 case RX_MSDU_DECAP_8023_SNAP_LLC:
e3fbf8d2
MK
913 /* insert decapped 802.11 header making a singly
914 * A-MSDU */
f6dc2095
MK
915 memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
916 break;
5e3dd157
KV
917 }
918
f6dc2095
MK
919 info->skb = skb;
920 info->encrypt_type = enctype;
5e3dd157 921 skb = skb->next;
f6dc2095 922 info->skb->next = NULL;
5e3dd157 923
652de35e
KV
924 if (skb)
925 info->amsdu_more = true;
926
f6dc2095
MK
927 ath10k_process_rx(htt->ar, info);
928 }
5e3dd157 929
f6dc2095
MK
930 /* FIXME: It might be nice to re-assemble the A-MSDU when there's a
931 * monitor interface active for sniffing purposes. */
5e3dd157
KV
932}
933
f6dc2095 934static void ath10k_htt_rx_msdu(struct ath10k_htt *htt, struct htt_rx_info *info)
5e3dd157
KV
935{
936 struct sk_buff *skb = info->skb;
937 struct htt_rx_desc *rxd;
938 struct ieee80211_hdr *hdr;
939 enum rx_msdu_decap_format fmt;
940 enum htt_rx_mpdu_encrypt_type enctype;
e3fbf8d2
MK
941 int hdr_len;
942 void *rfc1042;
5e3dd157
KV
943
944 /* This shouldn't happen. If it does than it may be a FW bug. */
945 if (skb->next) {
75fb2f94 946 ath10k_warn("htt rx received chained non A-MSDU frame\n");
5e3dd157
KV
947 ath10k_htt_rx_free_msdu_chain(skb->next);
948 skb->next = NULL;
949 }
950
951 rxd = (void *)skb->data - sizeof(*rxd);
952 fmt = MS(__le32_to_cpu(rxd->msdu_start.info1),
953 RX_MSDU_START_INFO1_DECAP_FORMAT);
954 enctype = MS(__le32_to_cpu(rxd->mpdu_start.info0),
955 RX_MPDU_START_INFO0_ENCRYPT_TYPE);
e3fbf8d2
MK
956 hdr = (struct ieee80211_hdr *)rxd->rx_hdr_status;
957 hdr_len = ieee80211_hdrlen(hdr->frame_control);
5e3dd157 958
f6dc2095
MK
959 skb->ip_summed = ath10k_htt_rx_get_csum_state(skb);
960
5e3dd157
KV
961 switch (fmt) {
962 case RX_MSDU_DECAP_RAW:
963 /* remove trailing FCS */
e3fbf8d2 964 skb_trim(skb, skb->len - FCS_LEN);
5e3dd157
KV
965 break;
966 case RX_MSDU_DECAP_NATIVE_WIFI:
784f69d3
MK
967 /* Pull decapped header */
968 hdr = (struct ieee80211_hdr *)skb->data;
d960c369 969 hdr_len = ath10k_htt_rx_nwifi_hdrlen(hdr);
784f69d3
MK
970 skb_pull(skb, hdr_len);
971
972 /* Push original header */
973 hdr = (struct ieee80211_hdr *)rxd->rx_hdr_status;
974 hdr_len = ieee80211_hdrlen(hdr->frame_control);
975 memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
5e3dd157
KV
976 break;
977 case RX_MSDU_DECAP_ETHERNET2_DIX:
e3fbf8d2
MK
978 /* strip ethernet header and insert decapped 802.11 header and
979 * rfc1042 header */
5e3dd157 980
e3fbf8d2
MK
981 rfc1042 = hdr;
982 rfc1042 += roundup(hdr_len, 4);
983 rfc1042 += roundup(ath10k_htt_rx_crypto_param_len(enctype), 4);
5e3dd157 984
e3fbf8d2
MK
985 skb_pull(skb, sizeof(struct ethhdr));
986 memcpy(skb_push(skb, sizeof(struct rfc1042_hdr)),
987 rfc1042, sizeof(struct rfc1042_hdr));
988 memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
989 break;
990 case RX_MSDU_DECAP_8023_SNAP_LLC:
991 /* remove A-MSDU subframe header and insert
992 * decapped 802.11 header. rfc1042 header is already there */
5e3dd157 993
e3fbf8d2
MK
994 skb_pull(skb, sizeof(struct amsdu_subframe_hdr));
995 memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
996 break;
5e3dd157
KV
997 }
998
999 info->skb = skb;
1000 info->encrypt_type = enctype;
f6dc2095
MK
1001
1002 ath10k_process_rx(htt->ar, info);
5e3dd157
KV
1003}
1004
1005static bool ath10k_htt_rx_has_decrypt_err(struct sk_buff *skb)
1006{
1007 struct htt_rx_desc *rxd;
1008 u32 flags;
1009
1010 rxd = (void *)skb->data - sizeof(*rxd);
1011 flags = __le32_to_cpu(rxd->attention.flags);
1012
1013 if (flags & RX_ATTENTION_FLAGS_DECRYPT_ERR)
1014 return true;
1015
1016 return false;
1017}
1018
1019static bool ath10k_htt_rx_has_fcs_err(struct sk_buff *skb)
1020{
1021 struct htt_rx_desc *rxd;
1022 u32 flags;
1023
1024 rxd = (void *)skb->data - sizeof(*rxd);
1025 flags = __le32_to_cpu(rxd->attention.flags);
1026
1027 if (flags & RX_ATTENTION_FLAGS_FCS_ERR)
1028 return true;
1029
1030 return false;
1031}
1032
22569400
JD
1033static bool ath10k_htt_rx_has_mic_err(struct sk_buff *skb)
1034{
1035 struct htt_rx_desc *rxd;
1036 u32 flags;
1037
1038 rxd = (void *)skb->data - sizeof(*rxd);
1039 flags = __le32_to_cpu(rxd->attention.flags);
1040
1041 if (flags & RX_ATTENTION_FLAGS_TKIP_MIC_ERR)
1042 return true;
1043
1044 return false;
1045}
1046
a80ddb00
JD
1047static bool ath10k_htt_rx_is_mgmt(struct sk_buff *skb)
1048{
1049 struct htt_rx_desc *rxd;
1050 u32 flags;
1051
1052 rxd = (void *)skb->data - sizeof(*rxd);
1053 flags = __le32_to_cpu(rxd->attention.flags);
1054
1055 if (flags & RX_ATTENTION_FLAGS_MGMT_TYPE)
1056 return true;
1057
1058 return false;
1059}
1060
605f81aa
MK
1061static int ath10k_htt_rx_get_csum_state(struct sk_buff *skb)
1062{
1063 struct htt_rx_desc *rxd;
1064 u32 flags, info;
1065 bool is_ip4, is_ip6;
1066 bool is_tcp, is_udp;
1067 bool ip_csum_ok, tcpudp_csum_ok;
1068
1069 rxd = (void *)skb->data - sizeof(*rxd);
1070 flags = __le32_to_cpu(rxd->attention.flags);
1071 info = __le32_to_cpu(rxd->msdu_start.info1);
1072
1073 is_ip4 = !!(info & RX_MSDU_START_INFO1_IPV4_PROTO);
1074 is_ip6 = !!(info & RX_MSDU_START_INFO1_IPV6_PROTO);
1075 is_tcp = !!(info & RX_MSDU_START_INFO1_TCP_PROTO);
1076 is_udp = !!(info & RX_MSDU_START_INFO1_UDP_PROTO);
1077 ip_csum_ok = !(flags & RX_ATTENTION_FLAGS_IP_CHKSUM_FAIL);
1078 tcpudp_csum_ok = !(flags & RX_ATTENTION_FLAGS_TCP_UDP_CHKSUM_FAIL);
1079
1080 if (!is_ip4 && !is_ip6)
1081 return CHECKSUM_NONE;
1082 if (!is_tcp && !is_udp)
1083 return CHECKSUM_NONE;
1084 if (!ip_csum_ok)
1085 return CHECKSUM_NONE;
1086 if (!tcpudp_csum_ok)
1087 return CHECKSUM_NONE;
1088
1089 return CHECKSUM_UNNECESSARY;
1090}
1091
bfa35368
BG
1092static int ath10k_unchain_msdu(struct sk_buff *msdu_head)
1093{
1094 struct sk_buff *next = msdu_head->next;
1095 struct sk_buff *to_free = next;
1096 int space;
1097 int total_len = 0;
1098
1099 /* TODO: Might could optimize this by using
1100 * skb_try_coalesce or similar method to
1101 * decrease copying, or maybe get mac80211 to
1102 * provide a way to just receive a list of
1103 * skb?
1104 */
1105
1106 msdu_head->next = NULL;
1107
1108 /* Allocate total length all at once. */
1109 while (next) {
1110 total_len += next->len;
1111 next = next->next;
1112 }
1113
1114 space = total_len - skb_tailroom(msdu_head);
1115 if ((space > 0) &&
1116 (pskb_expand_head(msdu_head, 0, space, GFP_ATOMIC) < 0)) {
1117 /* TODO: bump some rx-oom error stat */
1118 /* put it back together so we can free the
1119 * whole list at once.
1120 */
1121 msdu_head->next = to_free;
1122 return -1;
1123 }
1124
1125 /* Walk list again, copying contents into
1126 * msdu_head
1127 */
1128 next = to_free;
1129 while (next) {
1130 skb_copy_from_linear_data(next, skb_put(msdu_head, next->len),
1131 next->len);
1132 next = next->next;
1133 }
1134
1135 /* If here, we have consolidated skb. Free the
1136 * fragments and pass the main skb on up the
1137 * stack.
1138 */
1139 ath10k_htt_rx_free_msdu_chain(to_free);
1140 return 0;
1141}
1142
2acc4eb2
JD
1143static bool ath10k_htt_rx_amsdu_allowed(struct ath10k_htt *htt,
1144 struct sk_buff *head,
36653f05
JD
1145 struct htt_rx_info *info,
1146 bool channel_set)
2acc4eb2
JD
1147{
1148 enum htt_rx_mpdu_status status = info->status;
1149
1150 if (!head) {
1151 ath10k_warn("htt rx no data!\n");
1152 return false;
1153 }
1154
1155 if (head->len == 0) {
1156 ath10k_dbg(ATH10K_DBG_HTT,
1157 "htt rx dropping due to zero-len\n");
1158 return false;
1159 }
1160
1161 if (ath10k_htt_rx_has_decrypt_err(head)) {
1162 ath10k_dbg(ATH10K_DBG_HTT,
1163 "htt rx dropping due to decrypt-err\n");
1164 return false;
1165 }
1166
36653f05
JD
1167 if (!channel_set) {
1168 ath10k_warn("no channel configured; ignoring frame!\n");
1169 return false;
1170 }
1171
2acc4eb2
JD
1172 /* Skip mgmt frames while we handle this in WMI */
1173 if (status == HTT_RX_IND_MPDU_STATUS_MGMT_CTRL ||
1174 ath10k_htt_rx_is_mgmt(head)) {
1175 ath10k_dbg(ATH10K_DBG_HTT, "htt rx mgmt ctrl\n");
1176 return false;
1177 }
1178
1179 if (status != HTT_RX_IND_MPDU_STATUS_OK &&
1180 status != HTT_RX_IND_MPDU_STATUS_TKIP_MIC_ERR &&
1181 status != HTT_RX_IND_MPDU_STATUS_ERR_INV_PEER &&
1182 !htt->ar->monitor_enabled) {
1183 ath10k_dbg(ATH10K_DBG_HTT,
1184 "htt rx ignoring frame w/ status %d\n",
1185 status);
1186 return false;
1187 }
1188
1189 if (test_bit(ATH10K_CAC_RUNNING, &htt->ar->dev_flags)) {
1190 ath10k_dbg(ATH10K_DBG_HTT,
1191 "htt rx CAC running\n");
1192 return false;
1193 }
1194
1195 return true;
1196}
1197
5e3dd157
KV
1198static void ath10k_htt_rx_handler(struct ath10k_htt *htt,
1199 struct htt_rx_indication *rx)
1200{
1201 struct htt_rx_info info;
1202 struct htt_rx_indication_mpdu_range *mpdu_ranges;
1203 struct ieee80211_hdr *hdr;
1204 int num_mpdu_ranges;
1205 int fw_desc_len;
1206 u8 *fw_desc;
36653f05 1207 bool channel_set;
5e3dd157 1208 int i, j;
5e3dd157 1209
45967089
MK
1210 lockdep_assert_held(&htt->rx_ring.lock);
1211
5e3dd157
KV
1212 memset(&info, 0, sizeof(info));
1213
1214 fw_desc_len = __le16_to_cpu(rx->prefix.fw_rx_desc_bytes);
1215 fw_desc = (u8 *)&rx->fw_desc;
1216
1217 num_mpdu_ranges = MS(__le32_to_cpu(rx->hdr.info1),
1218 HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES);
1219 mpdu_ranges = htt_rx_ind_get_mpdu_ranges(rx);
1220
e8dc1a96
JD
1221 /* Fill this once, while this is per-ppdu */
1222 info.signal = ATH10K_DEFAULT_NOISE_FLOOR;
1223 info.signal += rx->ppdu.combined_rssi;
1224
36653f05
JD
1225 channel_set = ath10k_htt_rx_h_channel(htt->ar, &info.rx_status);
1226
e8dc1a96
JD
1227 info.rate.info0 = rx->ppdu.info0;
1228 info.rate.info1 = __le32_to_cpu(rx->ppdu.info1);
1229 info.rate.info2 = __le32_to_cpu(rx->ppdu.info2);
1230 info.tsf = __le32_to_cpu(rx->ppdu.tsf);
1231
5e3dd157
KV
1232 ath10k_dbg_dump(ATH10K_DBG_HTT_DUMP, NULL, "htt rx ind: ",
1233 rx, sizeof(*rx) +
1234 (sizeof(struct htt_rx_indication_mpdu_range) *
1235 num_mpdu_ranges));
1236
1237 for (i = 0; i < num_mpdu_ranges; i++) {
1238 info.status = mpdu_ranges[i].mpdu_range_status;
1239
1240 for (j = 0; j < mpdu_ranges[i].mpdu_count; j++) {
1241 struct sk_buff *msdu_head, *msdu_tail;
5e3dd157
KV
1242 int msdu_chaining;
1243
1244 msdu_head = NULL;
1245 msdu_tail = NULL;
1246 msdu_chaining = ath10k_htt_rx_amsdu_pop(htt,
1247 &fw_desc,
1248 &fw_desc_len,
1249 &msdu_head,
1250 &msdu_tail);
1251
2acc4eb2 1252 if (!ath10k_htt_rx_amsdu_allowed(htt, msdu_head,
36653f05
JD
1253 &info,
1254 channel_set)) {
e8a50f8b
MP
1255 ath10k_htt_rx_free_msdu_chain(msdu_head);
1256 continue;
1257 }
1258
bfa35368
BG
1259 if (msdu_chaining &&
1260 (ath10k_unchain_msdu(msdu_head) < 0)) {
5e3dd157
KV
1261 ath10k_htt_rx_free_msdu_chain(msdu_head);
1262 continue;
1263 }
1264
1265 info.skb = msdu_head;
1266 info.fcs_err = ath10k_htt_rx_has_fcs_err(msdu_head);
22569400 1267 info.mic_err = ath10k_htt_rx_has_mic_err(msdu_head);
c6b56b03
BG
1268
1269 if (info.fcs_err)
1270 ath10k_dbg(ATH10K_DBG_HTT,
1271 "htt rx has FCS err\n");
1272
1273 if (info.mic_err)
1274 ath10k_dbg(ATH10K_DBG_HTT,
1275 "htt rx has MIC err\n");
1276
5e3dd157
KV
1277 hdr = ath10k_htt_rx_skb_get_hdr(msdu_head);
1278
1279 if (ath10k_htt_rx_hdr_is_amsdu(hdr))
f6dc2095 1280 ath10k_htt_rx_amsdu(htt, &info);
5e3dd157 1281 else
f6dc2095 1282 ath10k_htt_rx_msdu(htt, &info);
5e3dd157
KV
1283 }
1284 }
1285
6e712d42 1286 tasklet_schedule(&htt->rx_replenish_task);
5e3dd157
KV
1287}
1288
1289static void ath10k_htt_rx_frag_handler(struct ath10k_htt *htt,
1290 struct htt_rx_fragment_indication *frag)
1291{
1292 struct sk_buff *msdu_head, *msdu_tail;
1293 struct htt_rx_desc *rxd;
1294 enum rx_msdu_decap_format fmt;
1295 struct htt_rx_info info = {};
1296 struct ieee80211_hdr *hdr;
1297 int msdu_chaining;
1298 bool tkip_mic_err;
1299 bool decrypt_err;
1300 u8 *fw_desc;
1301 int fw_desc_len, hdrlen, paramlen;
1302 int trim;
1303
1304 fw_desc_len = __le16_to_cpu(frag->fw_rx_desc_bytes);
1305 fw_desc = (u8 *)frag->fw_msdu_rx_desc;
1306
1307 msdu_head = NULL;
1308 msdu_tail = NULL;
45967089
MK
1309
1310 spin_lock_bh(&htt->rx_ring.lock);
5e3dd157
KV
1311 msdu_chaining = ath10k_htt_rx_amsdu_pop(htt, &fw_desc, &fw_desc_len,
1312 &msdu_head, &msdu_tail);
45967089 1313 spin_unlock_bh(&htt->rx_ring.lock);
5e3dd157
KV
1314
1315 ath10k_dbg(ATH10K_DBG_HTT_DUMP, "htt rx frag ahead\n");
1316
1317 if (!msdu_head) {
1318 ath10k_warn("htt rx frag no data\n");
1319 return;
1320 }
1321
1322 if (msdu_chaining || msdu_head != msdu_tail) {
1323 ath10k_warn("aggregation with fragmentation?!\n");
1324 ath10k_htt_rx_free_msdu_chain(msdu_head);
1325 return;
1326 }
1327
1328 /* FIXME: implement signal strength */
1329
1330 hdr = (struct ieee80211_hdr *)msdu_head->data;
1331 rxd = (void *)msdu_head->data - sizeof(*rxd);
1332 tkip_mic_err = !!(__le32_to_cpu(rxd->attention.flags) &
1333 RX_ATTENTION_FLAGS_TKIP_MIC_ERR);
1334 decrypt_err = !!(__le32_to_cpu(rxd->attention.flags) &
1335 RX_ATTENTION_FLAGS_DECRYPT_ERR);
1336 fmt = MS(__le32_to_cpu(rxd->msdu_start.info1),
1337 RX_MSDU_START_INFO1_DECAP_FORMAT);
1338
1339 if (fmt != RX_MSDU_DECAP_RAW) {
1340 ath10k_warn("we dont support non-raw fragmented rx yet\n");
1341 dev_kfree_skb_any(msdu_head);
1342 goto end;
1343 }
1344
1345 info.skb = msdu_head;
1346 info.status = HTT_RX_IND_MPDU_STATUS_OK;
1347 info.encrypt_type = MS(__le32_to_cpu(rxd->mpdu_start.info0),
1348 RX_MPDU_START_INFO0_ENCRYPT_TYPE);
605f81aa 1349 info.skb->ip_summed = ath10k_htt_rx_get_csum_state(info.skb);
5e3dd157
KV
1350
1351 if (tkip_mic_err) {
1352 ath10k_warn("tkip mic error\n");
1353 info.status = HTT_RX_IND_MPDU_STATUS_TKIP_MIC_ERR;
1354 }
1355
1356 if (decrypt_err) {
1357 ath10k_warn("decryption err in fragmented rx\n");
1358 dev_kfree_skb_any(info.skb);
1359 goto end;
1360 }
1361
1362 if (info.encrypt_type != HTT_RX_MPDU_ENCRYPT_NONE) {
1363 hdrlen = ieee80211_hdrlen(hdr->frame_control);
1364 paramlen = ath10k_htt_rx_crypto_param_len(info.encrypt_type);
1365
1366 /* It is more efficient to move the header than the payload */
1367 memmove((void *)info.skb->data + paramlen,
1368 (void *)info.skb->data,
1369 hdrlen);
1370 skb_pull(info.skb, paramlen);
1371 hdr = (struct ieee80211_hdr *)info.skb->data;
1372 }
1373
1374 /* remove trailing FCS */
1375 trim = 4;
1376
1377 /* remove crypto trailer */
1378 trim += ath10k_htt_rx_crypto_tail_len(info.encrypt_type);
1379
1380 /* last fragment of TKIP frags has MIC */
1381 if (!ieee80211_has_morefrags(hdr->frame_control) &&
1382 info.encrypt_type == HTT_RX_MPDU_ENCRYPT_TKIP_WPA)
1383 trim += 8;
1384
1385 if (trim > info.skb->len) {
1386 ath10k_warn("htt rx fragment: trailer longer than the frame itself? drop\n");
1387 dev_kfree_skb_any(info.skb);
1388 goto end;
1389 }
1390
1391 skb_trim(info.skb, info.skb->len - trim);
1392
75fb2f94 1393 ath10k_dbg_dump(ATH10K_DBG_HTT_DUMP, NULL, "htt rx frag mpdu: ",
5e3dd157
KV
1394 info.skb->data, info.skb->len);
1395 ath10k_process_rx(htt->ar, &info);
1396
1397end:
1398 if (fw_desc_len > 0) {
1399 ath10k_dbg(ATH10K_DBG_HTT,
1400 "expecting more fragmented rx in one indication %d\n",
1401 fw_desc_len);
1402 }
1403}
1404
6c5151a9
MK
1405static void ath10k_htt_rx_frm_tx_compl(struct ath10k *ar,
1406 struct sk_buff *skb)
1407{
1408 struct ath10k_htt *htt = &ar->htt;
1409 struct htt_resp *resp = (struct htt_resp *)skb->data;
1410 struct htt_tx_done tx_done = {};
1411 int status = MS(resp->data_tx_completion.flags, HTT_DATA_TX_STATUS);
1412 __le16 msdu_id;
1413 int i;
1414
45967089
MK
1415 lockdep_assert_held(&htt->tx_lock);
1416
6c5151a9
MK
1417 switch (status) {
1418 case HTT_DATA_TX_STATUS_NO_ACK:
1419 tx_done.no_ack = true;
1420 break;
1421 case HTT_DATA_TX_STATUS_OK:
1422 break;
1423 case HTT_DATA_TX_STATUS_DISCARD:
1424 case HTT_DATA_TX_STATUS_POSTPONE:
1425 case HTT_DATA_TX_STATUS_DOWNLOAD_FAIL:
1426 tx_done.discard = true;
1427 break;
1428 default:
1429 ath10k_warn("unhandled tx completion status %d\n", status);
1430 tx_done.discard = true;
1431 break;
1432 }
1433
1434 ath10k_dbg(ATH10K_DBG_HTT, "htt tx completion num_msdus %d\n",
1435 resp->data_tx_completion.num_msdus);
1436
1437 for (i = 0; i < resp->data_tx_completion.num_msdus; i++) {
1438 msdu_id = resp->data_tx_completion.msdus[i];
1439 tx_done.msdu_id = __le16_to_cpu(msdu_id);
1440 ath10k_txrx_tx_unref(htt, &tx_done);
1441 }
1442}
1443
5e3dd157
KV
1444void ath10k_htt_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb)
1445{
edb8236d 1446 struct ath10k_htt *htt = &ar->htt;
5e3dd157
KV
1447 struct htt_resp *resp = (struct htt_resp *)skb->data;
1448
1449 /* confirm alignment */
1450 if (!IS_ALIGNED((unsigned long)skb->data, 4))
1451 ath10k_warn("unaligned htt message, expect trouble\n");
1452
75fb2f94 1453 ath10k_dbg(ATH10K_DBG_HTT, "htt rx, msg_type: 0x%0X\n",
5e3dd157
KV
1454 resp->hdr.msg_type);
1455 switch (resp->hdr.msg_type) {
1456 case HTT_T2H_MSG_TYPE_VERSION_CONF: {
1457 htt->target_version_major = resp->ver_resp.major;
1458 htt->target_version_minor = resp->ver_resp.minor;
1459 complete(&htt->target_version_received);
1460 break;
1461 }
6c5151a9 1462 case HTT_T2H_MSG_TYPE_RX_IND:
45967089
MK
1463 spin_lock_bh(&htt->rx_ring.lock);
1464 __skb_queue_tail(&htt->rx_compl_q, skb);
1465 spin_unlock_bh(&htt->rx_ring.lock);
6c5151a9
MK
1466 tasklet_schedule(&htt->txrx_compl_task);
1467 return;
5e3dd157
KV
1468 case HTT_T2H_MSG_TYPE_PEER_MAP: {
1469 struct htt_peer_map_event ev = {
1470 .vdev_id = resp->peer_map.vdev_id,
1471 .peer_id = __le16_to_cpu(resp->peer_map.peer_id),
1472 };
1473 memcpy(ev.addr, resp->peer_map.addr, sizeof(ev.addr));
1474 ath10k_peer_map_event(htt, &ev);
1475 break;
1476 }
1477 case HTT_T2H_MSG_TYPE_PEER_UNMAP: {
1478 struct htt_peer_unmap_event ev = {
1479 .peer_id = __le16_to_cpu(resp->peer_unmap.peer_id),
1480 };
1481 ath10k_peer_unmap_event(htt, &ev);
1482 break;
1483 }
1484 case HTT_T2H_MSG_TYPE_MGMT_TX_COMPLETION: {
1485 struct htt_tx_done tx_done = {};
1486 int status = __le32_to_cpu(resp->mgmt_tx_completion.status);
1487
1488 tx_done.msdu_id =
1489 __le32_to_cpu(resp->mgmt_tx_completion.desc_id);
1490
1491 switch (status) {
1492 case HTT_MGMT_TX_STATUS_OK:
1493 break;
1494 case HTT_MGMT_TX_STATUS_RETRY:
1495 tx_done.no_ack = true;
1496 break;
1497 case HTT_MGMT_TX_STATUS_DROP:
1498 tx_done.discard = true;
1499 break;
1500 }
1501
6c5151a9 1502 spin_lock_bh(&htt->tx_lock);
0a89f8a0 1503 ath10k_txrx_tx_unref(htt, &tx_done);
6c5151a9 1504 spin_unlock_bh(&htt->tx_lock);
5e3dd157
KV
1505 break;
1506 }
6c5151a9
MK
1507 case HTT_T2H_MSG_TYPE_TX_COMPL_IND:
1508 spin_lock_bh(&htt->tx_lock);
1509 __skb_queue_tail(&htt->tx_compl_q, skb);
1510 spin_unlock_bh(&htt->tx_lock);
1511 tasklet_schedule(&htt->txrx_compl_task);
1512 return;
5e3dd157
KV
1513 case HTT_T2H_MSG_TYPE_SEC_IND: {
1514 struct ath10k *ar = htt->ar;
1515 struct htt_security_indication *ev = &resp->security_indication;
1516
1517 ath10k_dbg(ATH10K_DBG_HTT,
1518 "sec ind peer_id %d unicast %d type %d\n",
1519 __le16_to_cpu(ev->peer_id),
1520 !!(ev->flags & HTT_SECURITY_IS_UNICAST),
1521 MS(ev->flags, HTT_SECURITY_TYPE));
1522 complete(&ar->install_key_done);
1523 break;
1524 }
1525 case HTT_T2H_MSG_TYPE_RX_FRAG_IND: {
1526 ath10k_dbg_dump(ATH10K_DBG_HTT_DUMP, NULL, "htt event: ",
1527 skb->data, skb->len);
1528 ath10k_htt_rx_frag_handler(htt, &resp->rx_frag_ind);
1529 break;
1530 }
1531 case HTT_T2H_MSG_TYPE_TEST:
1532 /* FIX THIS */
1533 break;
5e3dd157 1534 case HTT_T2H_MSG_TYPE_STATS_CONF:
a9bf0506
KV
1535 trace_ath10k_htt_stats(skb->data, skb->len);
1536 break;
1537 case HTT_T2H_MSG_TYPE_TX_INSPECT_IND:
5e3dd157
KV
1538 case HTT_T2H_MSG_TYPE_RX_ADDBA:
1539 case HTT_T2H_MSG_TYPE_RX_DELBA:
1540 case HTT_T2H_MSG_TYPE_RX_FLUSH:
1541 default:
1542 ath10k_dbg(ATH10K_DBG_HTT, "htt event (%d) not handled\n",
1543 resp->hdr.msg_type);
1544 ath10k_dbg_dump(ATH10K_DBG_HTT_DUMP, NULL, "htt event: ",
1545 skb->data, skb->len);
1546 break;
1547 };
1548
1549 /* Free the indication buffer */
1550 dev_kfree_skb_any(skb);
1551}
6c5151a9
MK
1552
1553static void ath10k_htt_txrx_compl_task(unsigned long ptr)
1554{
1555 struct ath10k_htt *htt = (struct ath10k_htt *)ptr;
1556 struct htt_resp *resp;
1557 struct sk_buff *skb;
1558
45967089
MK
1559 spin_lock_bh(&htt->tx_lock);
1560 while ((skb = __skb_dequeue(&htt->tx_compl_q))) {
6c5151a9
MK
1561 ath10k_htt_rx_frm_tx_compl(htt->ar, skb);
1562 dev_kfree_skb_any(skb);
1563 }
45967089 1564 spin_unlock_bh(&htt->tx_lock);
6c5151a9 1565
45967089
MK
1566 spin_lock_bh(&htt->rx_ring.lock);
1567 while ((skb = __skb_dequeue(&htt->rx_compl_q))) {
6c5151a9
MK
1568 resp = (struct htt_resp *)skb->data;
1569 ath10k_htt_rx_handler(htt, &resp->rx_ind);
1570 dev_kfree_skb_any(skb);
1571 }
45967089 1572 spin_unlock_bh(&htt->rx_ring.lock);
6c5151a9 1573}