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ath10k: support get/set antenna configurations.
[mirror_ubuntu-zesty-kernel.git] / drivers / net / wireless / ath / ath10k / htt_rx.c
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1/*
2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
edb8236d 18#include "core.h"
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19#include "htc.h"
20#include "htt.h"
21#include "txrx.h"
22#include "debug.h"
a9bf0506 23#include "trace.h"
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24
25#include <linux/log2.h>
26
27/* slightly larger than one large A-MPDU */
28#define HTT_RX_RING_SIZE_MIN 128
29
30/* roughly 20 ms @ 1 Gbps of 1500B MSDUs */
31#define HTT_RX_RING_SIZE_MAX 2048
32
33#define HTT_RX_AVG_FRM_BYTES 1000
34
35/* ms, very conservative */
36#define HTT_RX_HOST_LATENCY_MAX_MS 20
37
38/* ms, conservative */
39#define HTT_RX_HOST_LATENCY_WORST_LIKELY_MS 10
40
41/* when under memory pressure rx ring refill may fail and needs a retry */
42#define HTT_RX_RING_REFILL_RETRY_MS 50
43
f6dc2095
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44
45static int ath10k_htt_rx_get_csum_state(struct sk_buff *skb);
6c5151a9 46static void ath10k_htt_txrx_compl_task(unsigned long ptr);
f6dc2095 47
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48static int ath10k_htt_rx_ring_size(struct ath10k_htt *htt)
49{
50 int size;
51
52 /*
53 * It is expected that the host CPU will typically be able to
54 * service the rx indication from one A-MPDU before the rx
55 * indication from the subsequent A-MPDU happens, roughly 1-2 ms
56 * later. However, the rx ring should be sized very conservatively,
57 * to accomodate the worst reasonable delay before the host CPU
58 * services a rx indication interrupt.
59 *
60 * The rx ring need not be kept full of empty buffers. In theory,
61 * the htt host SW can dynamically track the low-water mark in the
62 * rx ring, and dynamically adjust the level to which the rx ring
63 * is filled with empty buffers, to dynamically meet the desired
64 * low-water mark.
65 *
66 * In contrast, it's difficult to resize the rx ring itself, once
67 * it's in use. Thus, the ring itself should be sized very
68 * conservatively, while the degree to which the ring is filled
69 * with empty buffers should be sized moderately conservatively.
70 */
71
72 /* 1e6 bps/mbps / 1e3 ms per sec = 1000 */
73 size =
74 htt->max_throughput_mbps +
75 1000 /
76 (8 * HTT_RX_AVG_FRM_BYTES) * HTT_RX_HOST_LATENCY_MAX_MS;
77
78 if (size < HTT_RX_RING_SIZE_MIN)
79 size = HTT_RX_RING_SIZE_MIN;
80
81 if (size > HTT_RX_RING_SIZE_MAX)
82 size = HTT_RX_RING_SIZE_MAX;
83
84 size = roundup_pow_of_two(size);
85
86 return size;
87}
88
89static int ath10k_htt_rx_ring_fill_level(struct ath10k_htt *htt)
90{
91 int size;
92
93 /* 1e6 bps/mbps / 1e3 ms per sec = 1000 */
94 size =
95 htt->max_throughput_mbps *
96 1000 /
97 (8 * HTT_RX_AVG_FRM_BYTES) * HTT_RX_HOST_LATENCY_WORST_LIKELY_MS;
98
99 /*
100 * Make sure the fill level is at least 1 less than the ring size.
101 * Leaving 1 element empty allows the SW to easily distinguish
102 * between a full ring vs. an empty ring.
103 */
104 if (size >= htt->rx_ring.size)
105 size = htt->rx_ring.size - 1;
106
107 return size;
108}
109
110static void ath10k_htt_rx_ring_free(struct ath10k_htt *htt)
111{
112 struct sk_buff *skb;
113 struct ath10k_skb_cb *cb;
114 int i;
115
116 for (i = 0; i < htt->rx_ring.fill_cnt; i++) {
117 skb = htt->rx_ring.netbufs_ring[i];
118 cb = ATH10K_SKB_CB(skb);
119 dma_unmap_single(htt->ar->dev, cb->paddr,
120 skb->len + skb_tailroom(skb),
121 DMA_FROM_DEVICE);
122 dev_kfree_skb_any(skb);
123 }
124
125 htt->rx_ring.fill_cnt = 0;
126}
127
128static int __ath10k_htt_rx_ring_fill_n(struct ath10k_htt *htt, int num)
129{
130 struct htt_rx_desc *rx_desc;
131 struct sk_buff *skb;
132 dma_addr_t paddr;
133 int ret = 0, idx;
134
135 idx = __le32_to_cpu(*(htt->rx_ring.alloc_idx.vaddr));
136 while (num > 0) {
137 skb = dev_alloc_skb(HTT_RX_BUF_SIZE + HTT_RX_DESC_ALIGN);
138 if (!skb) {
139 ret = -ENOMEM;
140 goto fail;
141 }
142
143 if (!IS_ALIGNED((unsigned long)skb->data, HTT_RX_DESC_ALIGN))
144 skb_pull(skb,
145 PTR_ALIGN(skb->data, HTT_RX_DESC_ALIGN) -
146 skb->data);
147
148 /* Clear rx_desc attention word before posting to Rx ring */
149 rx_desc = (struct htt_rx_desc *)skb->data;
150 rx_desc->attention.flags = __cpu_to_le32(0);
151
152 paddr = dma_map_single(htt->ar->dev, skb->data,
153 skb->len + skb_tailroom(skb),
154 DMA_FROM_DEVICE);
155
156 if (unlikely(dma_mapping_error(htt->ar->dev, paddr))) {
157 dev_kfree_skb_any(skb);
158 ret = -ENOMEM;
159 goto fail;
160 }
161
162 ATH10K_SKB_CB(skb)->paddr = paddr;
163 htt->rx_ring.netbufs_ring[idx] = skb;
164 htt->rx_ring.paddrs_ring[idx] = __cpu_to_le32(paddr);
165 htt->rx_ring.fill_cnt++;
166
167 num--;
168 idx++;
169 idx &= htt->rx_ring.size_mask;
170 }
171
172fail:
173 *(htt->rx_ring.alloc_idx.vaddr) = __cpu_to_le32(idx);
174 return ret;
175}
176
177static int ath10k_htt_rx_ring_fill_n(struct ath10k_htt *htt, int num)
178{
179 lockdep_assert_held(&htt->rx_ring.lock);
180 return __ath10k_htt_rx_ring_fill_n(htt, num);
181}
182
183static void ath10k_htt_rx_msdu_buff_replenish(struct ath10k_htt *htt)
184{
6e712d42 185 int ret, num_deficit, num_to_fill;
5e3dd157 186
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187 /* Refilling the whole RX ring buffer proves to be a bad idea. The
188 * reason is RX may take up significant amount of CPU cycles and starve
189 * other tasks, e.g. TX on an ethernet device while acting as a bridge
190 * with ath10k wlan interface. This ended up with very poor performance
191 * once CPU the host system was overwhelmed with RX on ath10k.
192 *
193 * By limiting the number of refills the replenishing occurs
194 * progressively. This in turns makes use of the fact tasklets are
195 * processed in FIFO order. This means actual RX processing can starve
196 * out refilling. If there's not enough buffers on RX ring FW will not
197 * report RX until it is refilled with enough buffers. This
198 * automatically balances load wrt to CPU power.
199 *
200 * This probably comes at a cost of lower maximum throughput but
201 * improves the avarage and stability. */
5e3dd157 202 spin_lock_bh(&htt->rx_ring.lock);
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203 num_deficit = htt->rx_ring.fill_level - htt->rx_ring.fill_cnt;
204 num_to_fill = min(ATH10K_HTT_MAX_NUM_REFILL, num_deficit);
205 num_deficit -= num_to_fill;
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206 ret = ath10k_htt_rx_ring_fill_n(htt, num_to_fill);
207 if (ret == -ENOMEM) {
208 /*
209 * Failed to fill it to the desired level -
210 * we'll start a timer and try again next time.
211 * As long as enough buffers are left in the ring for
212 * another A-MPDU rx, no special recovery is needed.
213 */
214 mod_timer(&htt->rx_ring.refill_retry_timer, jiffies +
215 msecs_to_jiffies(HTT_RX_RING_REFILL_RETRY_MS));
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216 } else if (num_deficit > 0) {
217 tasklet_schedule(&htt->rx_replenish_task);
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218 }
219 spin_unlock_bh(&htt->rx_ring.lock);
220}
221
222static void ath10k_htt_rx_ring_refill_retry(unsigned long arg)
223{
224 struct ath10k_htt *htt = (struct ath10k_htt *)arg;
225 ath10k_htt_rx_msdu_buff_replenish(htt);
226}
227
3e841fd0 228static void ath10k_htt_rx_ring_clean_up(struct ath10k_htt *htt)
5e3dd157 229{
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230 struct sk_buff *skb;
231 int i;
232
233 for (i = 0; i < htt->rx_ring.size; i++) {
234 skb = htt->rx_ring.netbufs_ring[i];
235 if (!skb)
236 continue;
237
238 dma_unmap_single(htt->ar->dev, ATH10K_SKB_CB(skb)->paddr,
239 skb->len + skb_tailroom(skb),
240 DMA_FROM_DEVICE);
241 dev_kfree_skb_any(skb);
242 htt->rx_ring.netbufs_ring[i] = NULL;
243 }
244}
5e3dd157 245
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246void ath10k_htt_rx_detach(struct ath10k_htt *htt)
247{
5e3dd157 248 del_timer_sync(&htt->rx_ring.refill_retry_timer);
6e712d42 249 tasklet_kill(&htt->rx_replenish_task);
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250 tasklet_kill(&htt->txrx_compl_task);
251
252 skb_queue_purge(&htt->tx_compl_q);
253 skb_queue_purge(&htt->rx_compl_q);
5e3dd157 254
3e841fd0 255 ath10k_htt_rx_ring_clean_up(htt);
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256
257 dma_free_coherent(htt->ar->dev,
258 (htt->rx_ring.size *
259 sizeof(htt->rx_ring.paddrs_ring)),
260 htt->rx_ring.paddrs_ring,
261 htt->rx_ring.base_paddr);
262
263 dma_free_coherent(htt->ar->dev,
264 sizeof(*htt->rx_ring.alloc_idx.vaddr),
265 htt->rx_ring.alloc_idx.vaddr,
266 htt->rx_ring.alloc_idx.paddr);
267
268 kfree(htt->rx_ring.netbufs_ring);
269}
270
271static inline struct sk_buff *ath10k_htt_rx_netbuf_pop(struct ath10k_htt *htt)
272{
273 int idx;
274 struct sk_buff *msdu;
275
45967089 276 lockdep_assert_held(&htt->rx_ring.lock);
5e3dd157 277
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278 if (htt->rx_ring.fill_cnt == 0) {
279 ath10k_warn("tried to pop sk_buff from an empty rx ring\n");
280 return NULL;
281 }
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282
283 idx = htt->rx_ring.sw_rd_idx.msdu_payld;
284 msdu = htt->rx_ring.netbufs_ring[idx];
3e841fd0 285 htt->rx_ring.netbufs_ring[idx] = NULL;
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286
287 idx++;
288 idx &= htt->rx_ring.size_mask;
289 htt->rx_ring.sw_rd_idx.msdu_payld = idx;
290 htt->rx_ring.fill_cnt--;
291
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292 return msdu;
293}
294
295static void ath10k_htt_rx_free_msdu_chain(struct sk_buff *skb)
296{
297 struct sk_buff *next;
298
299 while (skb) {
300 next = skb->next;
301 dev_kfree_skb_any(skb);
302 skb = next;
303 }
304}
305
d84dd60f 306/* return: < 0 fatal error, 0 - non chained msdu, 1 chained msdu */
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307static int ath10k_htt_rx_amsdu_pop(struct ath10k_htt *htt,
308 u8 **fw_desc, int *fw_desc_len,
309 struct sk_buff **head_msdu,
310 struct sk_buff **tail_msdu)
311{
312 int msdu_len, msdu_chaining = 0;
313 struct sk_buff *msdu;
314 struct htt_rx_desc *rx_desc;
ede9c8e0 315 bool corrupted = false;
5e3dd157 316
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317 lockdep_assert_held(&htt->rx_ring.lock);
318
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319 if (htt->rx_confused) {
320 ath10k_warn("htt is confused. refusing rx\n");
d84dd60f 321 return -1;
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322 }
323
324 msdu = *head_msdu = ath10k_htt_rx_netbuf_pop(htt);
325 while (msdu) {
326 int last_msdu, msdu_len_invalid, msdu_chained;
327
328 dma_unmap_single(htt->ar->dev,
329 ATH10K_SKB_CB(msdu)->paddr,
330 msdu->len + skb_tailroom(msdu),
331 DMA_FROM_DEVICE);
332
75fb2f94 333 ath10k_dbg_dump(ATH10K_DBG_HTT_DUMP, NULL, "htt rx pop: ",
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334 msdu->data, msdu->len + skb_tailroom(msdu));
335
336 rx_desc = (struct htt_rx_desc *)msdu->data;
337
338 /* FIXME: we must report msdu payload since this is what caller
339 * expects now */
340 skb_put(msdu, offsetof(struct htt_rx_desc, msdu_payload));
341 skb_pull(msdu, offsetof(struct htt_rx_desc, msdu_payload));
342
343 /*
344 * Sanity check - confirm the HW is finished filling in the
345 * rx data.
346 * If the HW and SW are working correctly, then it's guaranteed
347 * that the HW's MAC DMA is done before this point in the SW.
348 * To prevent the case that we handle a stale Rx descriptor,
349 * just assert for now until we have a way to recover.
350 */
351 if (!(__le32_to_cpu(rx_desc->attention.flags)
352 & RX_ATTENTION_FLAGS_MSDU_DONE)) {
353 ath10k_htt_rx_free_msdu_chain(*head_msdu);
354 *head_msdu = NULL;
355 msdu = NULL;
356 ath10k_err("htt rx stopped. cannot recover\n");
357 htt->rx_confused = true;
358 break;
359 }
360
361 /*
362 * Copy the FW rx descriptor for this MSDU from the rx
363 * indication message into the MSDU's netbuf. HL uses the
364 * same rx indication message definition as LL, and simply
365 * appends new info (fields from the HW rx desc, and the
366 * MSDU payload itself). So, the offset into the rx
367 * indication message only has to account for the standard
368 * offset of the per-MSDU FW rx desc info within the
369 * message, and how many bytes of the per-MSDU FW rx desc
370 * info have already been consumed. (And the endianness of
371 * the host, since for a big-endian host, the rx ind
372 * message contents, including the per-MSDU rx desc bytes,
373 * were byteswapped during upload.)
374 */
375 if (*fw_desc_len > 0) {
376 rx_desc->fw_desc.info0 = **fw_desc;
377 /*
378 * The target is expected to only provide the basic
379 * per-MSDU rx descriptors. Just to be sure, verify
380 * that the target has not attached extension data
381 * (e.g. LRO flow ID).
382 */
383
384 /* or more, if there's extension data */
385 (*fw_desc)++;
386 (*fw_desc_len)--;
387 } else {
388 /*
389 * When an oversized AMSDU happened, FW will lost
390 * some of MSDU status - in this case, the FW
391 * descriptors provided will be less than the
392 * actual MSDUs inside this MPDU. Mark the FW
393 * descriptors so that it will still deliver to
394 * upper stack, if no CRC error for this MPDU.
395 *
396 * FIX THIS - the FW descriptors are actually for
397 * MSDUs in the end of this A-MSDU instead of the
398 * beginning.
399 */
400 rx_desc->fw_desc.info0 = 0;
401 }
402
403 msdu_len_invalid = !!(__le32_to_cpu(rx_desc->attention.flags)
404 & (RX_ATTENTION_FLAGS_MPDU_LENGTH_ERR |
405 RX_ATTENTION_FLAGS_MSDU_LENGTH_ERR));
406 msdu_len = MS(__le32_to_cpu(rx_desc->msdu_start.info0),
407 RX_MSDU_START_INFO0_MSDU_LENGTH);
408 msdu_chained = rx_desc->frag_info.ring2_more_count;
409
410 if (msdu_len_invalid)
411 msdu_len = 0;
412
413 skb_trim(msdu, 0);
414 skb_put(msdu, min(msdu_len, HTT_RX_MSDU_SIZE));
415 msdu_len -= msdu->len;
416
417 /* FIXME: Do chained buffers include htt_rx_desc or not? */
418 while (msdu_chained--) {
419 struct sk_buff *next = ath10k_htt_rx_netbuf_pop(htt);
420
421 dma_unmap_single(htt->ar->dev,
422 ATH10K_SKB_CB(next)->paddr,
423 next->len + skb_tailroom(next),
424 DMA_FROM_DEVICE);
425
75fb2f94
BG
426 ath10k_dbg_dump(ATH10K_DBG_HTT_DUMP, NULL,
427 "htt rx chained: ", next->data,
5e3dd157
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428 next->len + skb_tailroom(next));
429
430 skb_trim(next, 0);
431 skb_put(next, min(msdu_len, HTT_RX_BUF_SIZE));
432 msdu_len -= next->len;
433
434 msdu->next = next;
435 msdu = next;
ede9c8e0 436 msdu_chaining = 1;
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437 }
438
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439 last_msdu = __le32_to_cpu(rx_desc->msdu_end.info0) &
440 RX_MSDU_END_INFO0_LAST_MSDU;
441
ede9c8e0
MK
442 if (msdu_chaining && !last_msdu)
443 corrupted = true;
444
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445 if (last_msdu) {
446 msdu->next = NULL;
447 break;
448 } else {
449 struct sk_buff *next = ath10k_htt_rx_netbuf_pop(htt);
450 msdu->next = next;
451 msdu = next;
452 }
453 }
454 *tail_msdu = msdu;
455
d84dd60f
JD
456 if (*head_msdu == NULL)
457 msdu_chaining = -1;
458
ede9c8e0
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459 /*
460 * Apparently FW sometimes reports weird chained MSDU sequences with
461 * more than one rx descriptor. This seems like a bug but needs more
462 * analyzing. For the time being fix it by dropping such sequences to
463 * avoid blowing up the host system.
464 */
465 if (corrupted) {
466 ath10k_warn("failed to pop chained msdus, dropping\n");
467 ath10k_htt_rx_free_msdu_chain(*head_msdu);
468 *head_msdu = NULL;
469 *tail_msdu = NULL;
470 msdu_chaining = -EINVAL;
471 }
472
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473 /*
474 * Don't refill the ring yet.
475 *
476 * First, the elements popped here are still in use - it is not
477 * safe to overwrite them until the matching call to
478 * mpdu_desc_list_next. Second, for efficiency it is preferable to
479 * refill the rx ring with 1 PPDU's worth of rx buffers (something
480 * like 32 x 3 buffers), rather than one MPDU's worth of rx buffers
481 * (something like 3 buffers). Consequently, we'll rely on the txrx
482 * SW to tell us when it is done pulling all the PPDU's rx buffers
483 * out of the rx ring, and then refill it just once.
484 */
485
486 return msdu_chaining;
487}
488
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489static void ath10k_htt_rx_replenish_task(unsigned long ptr)
490{
491 struct ath10k_htt *htt = (struct ath10k_htt *)ptr;
492 ath10k_htt_rx_msdu_buff_replenish(htt);
493}
494
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495int ath10k_htt_rx_attach(struct ath10k_htt *htt)
496{
497 dma_addr_t paddr;
498 void *vaddr;
499 struct timer_list *timer = &htt->rx_ring.refill_retry_timer;
500
501 htt->rx_ring.size = ath10k_htt_rx_ring_size(htt);
502 if (!is_power_of_2(htt->rx_ring.size)) {
503 ath10k_warn("htt rx ring size is not power of 2\n");
504 return -EINVAL;
505 }
506
507 htt->rx_ring.size_mask = htt->rx_ring.size - 1;
508
509 /*
510 * Set the initial value for the level to which the rx ring
511 * should be filled, based on the max throughput and the
512 * worst likely latency for the host to fill the rx ring
513 * with new buffers. In theory, this fill level can be
514 * dynamically adjusted from the initial value set here, to
515 * reflect the actual host latency rather than a
516 * conservative assumption about the host latency.
517 */
518 htt->rx_ring.fill_level = ath10k_htt_rx_ring_fill_level(htt);
519
520 htt->rx_ring.netbufs_ring =
3e841fd0 521 kzalloc(htt->rx_ring.size * sizeof(struct sk_buff *),
5e3dd157
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522 GFP_KERNEL);
523 if (!htt->rx_ring.netbufs_ring)
524 goto err_netbuf;
525
526 vaddr = dma_alloc_coherent(htt->ar->dev,
527 (htt->rx_ring.size * sizeof(htt->rx_ring.paddrs_ring)),
528 &paddr, GFP_DMA);
529 if (!vaddr)
530 goto err_dma_ring;
531
532 htt->rx_ring.paddrs_ring = vaddr;
533 htt->rx_ring.base_paddr = paddr;
534
535 vaddr = dma_alloc_coherent(htt->ar->dev,
536 sizeof(*htt->rx_ring.alloc_idx.vaddr),
537 &paddr, GFP_DMA);
538 if (!vaddr)
539 goto err_dma_idx;
540
541 htt->rx_ring.alloc_idx.vaddr = vaddr;
542 htt->rx_ring.alloc_idx.paddr = paddr;
543 htt->rx_ring.sw_rd_idx.msdu_payld = 0;
544 *htt->rx_ring.alloc_idx.vaddr = 0;
545
546 /* Initialize the Rx refill retry timer */
547 setup_timer(timer, ath10k_htt_rx_ring_refill_retry, (unsigned long)htt);
548
549 spin_lock_init(&htt->rx_ring.lock);
550
551 htt->rx_ring.fill_cnt = 0;
552 if (__ath10k_htt_rx_ring_fill_n(htt, htt->rx_ring.fill_level))
553 goto err_fill_ring;
554
6e712d42
MK
555 tasklet_init(&htt->rx_replenish_task, ath10k_htt_rx_replenish_task,
556 (unsigned long)htt);
557
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MK
558 skb_queue_head_init(&htt->tx_compl_q);
559 skb_queue_head_init(&htt->rx_compl_q);
560
561 tasklet_init(&htt->txrx_compl_task, ath10k_htt_txrx_compl_task,
562 (unsigned long)htt);
563
aad0b65f 564 ath10k_dbg(ATH10K_DBG_BOOT, "htt rx ring size %d fill_level %d\n",
5e3dd157
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565 htt->rx_ring.size, htt->rx_ring.fill_level);
566 return 0;
567
568err_fill_ring:
569 ath10k_htt_rx_ring_free(htt);
570 dma_free_coherent(htt->ar->dev,
571 sizeof(*htt->rx_ring.alloc_idx.vaddr),
572 htt->rx_ring.alloc_idx.vaddr,
573 htt->rx_ring.alloc_idx.paddr);
574err_dma_idx:
575 dma_free_coherent(htt->ar->dev,
576 (htt->rx_ring.size *
577 sizeof(htt->rx_ring.paddrs_ring)),
578 htt->rx_ring.paddrs_ring,
579 htt->rx_ring.base_paddr);
580err_dma_ring:
581 kfree(htt->rx_ring.netbufs_ring);
582err_netbuf:
583 return -ENOMEM;
584}
585
586static int ath10k_htt_rx_crypto_param_len(enum htt_rx_mpdu_encrypt_type type)
587{
588 switch (type) {
589 case HTT_RX_MPDU_ENCRYPT_WEP40:
590 case HTT_RX_MPDU_ENCRYPT_WEP104:
591 return 4;
592 case HTT_RX_MPDU_ENCRYPT_TKIP_WITHOUT_MIC:
593 case HTT_RX_MPDU_ENCRYPT_WEP128: /* not tested */
594 case HTT_RX_MPDU_ENCRYPT_TKIP_WPA:
595 case HTT_RX_MPDU_ENCRYPT_WAPI: /* not tested */
596 case HTT_RX_MPDU_ENCRYPT_AES_CCM_WPA2:
597 return 8;
598 case HTT_RX_MPDU_ENCRYPT_NONE:
599 return 0;
600 }
601
602 ath10k_warn("unknown encryption type %d\n", type);
603 return 0;
604}
605
606static int ath10k_htt_rx_crypto_tail_len(enum htt_rx_mpdu_encrypt_type type)
607{
608 switch (type) {
609 case HTT_RX_MPDU_ENCRYPT_NONE:
610 case HTT_RX_MPDU_ENCRYPT_WEP40:
611 case HTT_RX_MPDU_ENCRYPT_WEP104:
612 case HTT_RX_MPDU_ENCRYPT_WEP128:
613 case HTT_RX_MPDU_ENCRYPT_WAPI:
614 return 0;
615 case HTT_RX_MPDU_ENCRYPT_TKIP_WITHOUT_MIC:
616 case HTT_RX_MPDU_ENCRYPT_TKIP_WPA:
617 return 4;
618 case HTT_RX_MPDU_ENCRYPT_AES_CCM_WPA2:
619 return 8;
620 }
621
622 ath10k_warn("unknown encryption type %d\n", type);
623 return 0;
624}
625
626/* Applies for first msdu in chain, before altering it. */
627static struct ieee80211_hdr *ath10k_htt_rx_skb_get_hdr(struct sk_buff *skb)
628{
629 struct htt_rx_desc *rxd;
630 enum rx_msdu_decap_format fmt;
631
632 rxd = (void *)skb->data - sizeof(*rxd);
633 fmt = MS(__le32_to_cpu(rxd->msdu_start.info1),
634 RX_MSDU_START_INFO1_DECAP_FORMAT);
635
636 if (fmt == RX_MSDU_DECAP_RAW)
637 return (void *)skb->data;
638 else
639 return (void *)skb->data - RX_HTT_HDR_STATUS_LEN;
640}
641
642/* This function only applies for first msdu in an msdu chain */
643static bool ath10k_htt_rx_hdr_is_amsdu(struct ieee80211_hdr *hdr)
644{
645 if (ieee80211_is_data_qos(hdr->frame_control)) {
646 u8 *qc = ieee80211_get_qos_ctl(hdr);
647 if (qc[0] & 0x80)
648 return true;
649 }
650 return false;
651}
652
f6dc2095
MK
653struct rfc1042_hdr {
654 u8 llc_dsap;
655 u8 llc_ssap;
656 u8 llc_ctrl;
657 u8 snap_oui[3];
658 __be16 snap_type;
659} __packed;
660
661struct amsdu_subframe_hdr {
662 u8 dst[ETH_ALEN];
663 u8 src[ETH_ALEN];
664 __be16 len;
665} __packed;
666
73539b40
JD
667static const u8 rx_legacy_rate_idx[] = {
668 3, /* 0x00 - 11Mbps */
669 2, /* 0x01 - 5.5Mbps */
670 1, /* 0x02 - 2Mbps */
671 0, /* 0x03 - 1Mbps */
672 3, /* 0x04 - 11Mbps */
673 2, /* 0x05 - 5.5Mbps */
674 1, /* 0x06 - 2Mbps */
675 0, /* 0x07 - 1Mbps */
676 10, /* 0x08 - 48Mbps */
677 8, /* 0x09 - 24Mbps */
678 6, /* 0x0A - 12Mbps */
679 4, /* 0x0B - 6Mbps */
680 11, /* 0x0C - 54Mbps */
681 9, /* 0x0D - 36Mbps */
682 7, /* 0x0E - 18Mbps */
683 5, /* 0x0F - 9Mbps */
684};
685
87326c97 686static void ath10k_htt_rx_h_rates(struct ath10k *ar,
cfadd9ba 687 enum ieee80211_band band,
87326c97 688 u8 info0, u32 info1, u32 info2,
cfadd9ba 689 struct ieee80211_rx_status *status)
73539b40
JD
690{
691 u8 cck, rate, rate_idx, bw, sgi, mcs, nss;
73539b40
JD
692 u8 preamble = 0;
693
694 /* Check if valid fields */
695 if (!(info0 & HTT_RX_INDICATION_INFO0_START_VALID))
696 return;
697
698 preamble = MS(info1, HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE);
699
700 switch (preamble) {
701 case HTT_RX_LEGACY:
702 cck = info0 & HTT_RX_INDICATION_INFO0_LEGACY_RATE_CCK;
703 rate = MS(info0, HTT_RX_INDICATION_INFO0_LEGACY_RATE);
704 rate_idx = 0;
705
706 if (rate < 0x08 || rate > 0x0F)
707 break;
708
709 switch (band) {
710 case IEEE80211_BAND_2GHZ:
711 if (cck)
712 rate &= ~BIT(3);
713 rate_idx = rx_legacy_rate_idx[rate];
714 break;
715 case IEEE80211_BAND_5GHZ:
716 rate_idx = rx_legacy_rate_idx[rate];
717 /* We are using same rate table registering
718 HW - ath10k_rates[]. In case of 5GHz skip
719 CCK rates, so -4 here */
720 rate_idx -= 4;
721 break;
722 default:
723 break;
724 }
725
726 status->rate_idx = rate_idx;
727 break;
728 case HTT_RX_HT:
729 case HTT_RX_HT_WITH_TXBF:
730 /* HT-SIG - Table 20-11 in info1 and info2 */
731 mcs = info1 & 0x1F;
732 nss = mcs >> 3;
733 bw = (info1 >> 7) & 1;
734 sgi = (info2 >> 7) & 1;
735
736 status->rate_idx = mcs;
737 status->flag |= RX_FLAG_HT;
738 if (sgi)
739 status->flag |= RX_FLAG_SHORT_GI;
740 if (bw)
741 status->flag |= RX_FLAG_40MHZ;
742 break;
743 case HTT_RX_VHT:
744 case HTT_RX_VHT_WITH_TXBF:
745 /* VHT-SIG-A1 in info 1, VHT-SIG-A2 in info2
746 TODO check this */
747 mcs = (info2 >> 4) & 0x0F;
748 nss = ((info1 >> 10) & 0x07) + 1;
749 bw = info1 & 3;
750 sgi = info2 & 1;
751
752 status->rate_idx = mcs;
753 status->vht_nss = nss;
754
755 if (sgi)
756 status->flag |= RX_FLAG_SHORT_GI;
757
758 switch (bw) {
759 /* 20MHZ */
760 case 0:
761 break;
762 /* 40MHZ */
763 case 1:
764 status->flag |= RX_FLAG_40MHZ;
765 break;
766 /* 80MHZ */
767 case 2:
768 status->vht_flag |= RX_VHT_FLAG_80MHZ;
769 }
770
771 status->flag |= RX_FLAG_VHT;
772 break;
773 default:
774 break;
775 }
776}
777
87326c97 778static void ath10k_htt_rx_h_protected(struct ath10k_htt *htt,
85f6d7cf
JD
779 struct ieee80211_rx_status *rx_status,
780 struct sk_buff *skb,
87326c97
JD
781 enum htt_rx_mpdu_encrypt_type enctype)
782{
85f6d7cf 783 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
87326c97
JD
784
785
786 if (enctype == HTT_RX_MPDU_ENCRYPT_NONE) {
85f6d7cf
JD
787 rx_status->flag &= ~(RX_FLAG_DECRYPTED |
788 RX_FLAG_IV_STRIPPED |
789 RX_FLAG_MMIC_STRIPPED);
87326c97
JD
790 return;
791 }
792
85f6d7cf
JD
793 rx_status->flag |= RX_FLAG_DECRYPTED |
794 RX_FLAG_IV_STRIPPED |
795 RX_FLAG_MMIC_STRIPPED;
87326c97
JD
796 hdr->frame_control = __cpu_to_le16(__le16_to_cpu(hdr->frame_control) &
797 ~IEEE80211_FCTL_PROTECTED);
798}
799
36653f05
JD
800static bool ath10k_htt_rx_h_channel(struct ath10k *ar,
801 struct ieee80211_rx_status *status)
802{
803 struct ieee80211_channel *ch;
804
805 spin_lock_bh(&ar->data_lock);
806 ch = ar->scan_channel;
807 if (!ch)
808 ch = ar->rx_channel;
809 spin_unlock_bh(&ar->data_lock);
810
811 if (!ch)
812 return false;
813
814 status->band = ch->band;
815 status->freq = ch->center_freq;
816
817 return true;
818}
819
85f6d7cf
JD
820static void ath10k_process_rx(struct ath10k *ar,
821 struct ieee80211_rx_status *rx_status,
822 struct sk_buff *skb)
73539b40
JD
823{
824 struct ieee80211_rx_status *status;
73539b40 825
85f6d7cf
JD
826 status = IEEE80211_SKB_RXCB(skb);
827 *status = *rx_status;
73539b40 828
73539b40 829 ath10k_dbg(ATH10K_DBG_DATA,
78433f96 830 "rx skb %p len %u %s%s%s%s%s %srate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %imic-err %i\n",
85f6d7cf
JD
831 skb,
832 skb->len,
73539b40
JD
833 status->flag == 0 ? "legacy" : "",
834 status->flag & RX_FLAG_HT ? "ht" : "",
835 status->flag & RX_FLAG_VHT ? "vht" : "",
836 status->flag & RX_FLAG_40MHZ ? "40" : "",
837 status->vht_flag & RX_VHT_FLAG_80MHZ ? "80" : "",
838 status->flag & RX_FLAG_SHORT_GI ? "sgi " : "",
839 status->rate_idx,
840 status->vht_nss,
841 status->freq,
87326c97 842 status->band, status->flag,
78433f96
JD
843 !!(status->flag & RX_FLAG_FAILED_FCS_CRC),
844 !!(status->flag & RX_FLAG_MMIC_ERROR));
73539b40 845 ath10k_dbg_dump(ATH10K_DBG_HTT_DUMP, NULL, "rx skb: ",
85f6d7cf 846 skb->data, skb->len);
73539b40 847
85f6d7cf 848 ieee80211_rx(ar->hw, skb);
73539b40
JD
849}
850
d960c369
MK
851static int ath10k_htt_rx_nwifi_hdrlen(struct ieee80211_hdr *hdr)
852{
853 /* nwifi header is padded to 4 bytes. this fixes 4addr rx */
854 return round_up(ieee80211_hdrlen(hdr->frame_control), 4);
855}
856
f6dc2095 857static void ath10k_htt_rx_amsdu(struct ath10k_htt *htt,
85f6d7cf
JD
858 struct ieee80211_rx_status *rx_status,
859 struct sk_buff *skb_in)
5e3dd157
KV
860{
861 struct htt_rx_desc *rxd;
85f6d7cf 862 struct sk_buff *skb = skb_in;
5e3dd157 863 struct sk_buff *first;
5e3dd157
KV
864 enum rx_msdu_decap_format fmt;
865 enum htt_rx_mpdu_encrypt_type enctype;
f6dc2095 866 struct ieee80211_hdr *hdr;
784f69d3 867 u8 hdr_buf[64], addr[ETH_ALEN], *qos;
5e3dd157 868 unsigned int hdr_len;
5e3dd157
KV
869
870 rxd = (void *)skb->data - sizeof(*rxd);
5e3dd157
KV
871 enctype = MS(__le32_to_cpu(rxd->mpdu_start.info0),
872 RX_MPDU_START_INFO0_ENCRYPT_TYPE);
873
f6dc2095
MK
874 hdr = (struct ieee80211_hdr *)rxd->rx_hdr_status;
875 hdr_len = ieee80211_hdrlen(hdr->frame_control);
876 memcpy(hdr_buf, hdr, hdr_len);
877 hdr = (struct ieee80211_hdr *)hdr_buf;
5e3dd157 878
5e3dd157
KV
879 first = skb;
880 while (skb) {
881 void *decap_hdr;
f6dc2095 882 int len;
5e3dd157
KV
883
884 rxd = (void *)skb->data - sizeof(*rxd);
885 fmt = MS(__le32_to_cpu(rxd->msdu_start.info1),
f6dc2095 886 RX_MSDU_START_INFO1_DECAP_FORMAT);
5e3dd157
KV
887 decap_hdr = (void *)rxd->rx_hdr_status;
888
f6dc2095 889 skb->ip_summed = ath10k_htt_rx_get_csum_state(skb);
5e3dd157 890
f6dc2095
MK
891 /* First frame in an A-MSDU chain has more decapped data. */
892 if (skb == first) {
893 len = round_up(ieee80211_hdrlen(hdr->frame_control), 4);
894 len += round_up(ath10k_htt_rx_crypto_param_len(enctype),
895 4);
896 decap_hdr += len;
5e3dd157
KV
897 }
898
f6dc2095
MK
899 switch (fmt) {
900 case RX_MSDU_DECAP_RAW:
e3fbf8d2 901 /* remove trailing FCS */
f6dc2095
MK
902 skb_trim(skb, skb->len - FCS_LEN);
903 break;
904 case RX_MSDU_DECAP_NATIVE_WIFI:
784f69d3
MK
905 /* pull decapped header and copy DA */
906 hdr = (struct ieee80211_hdr *)skb->data;
d960c369 907 hdr_len = ath10k_htt_rx_nwifi_hdrlen(hdr);
784f69d3
MK
908 memcpy(addr, ieee80211_get_DA(hdr), ETH_ALEN);
909 skb_pull(skb, hdr_len);
910
911 /* push original 802.11 header */
912 hdr = (struct ieee80211_hdr *)hdr_buf;
913 hdr_len = ieee80211_hdrlen(hdr->frame_control);
914 memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
915
916 /* original A-MSDU header has the bit set but we're
917 * not including A-MSDU subframe header */
918 hdr = (struct ieee80211_hdr *)skb->data;
919 qos = ieee80211_get_qos_ctl(hdr);
920 qos[0] &= ~IEEE80211_QOS_CTL_A_MSDU_PRESENT;
921
922 /* original 802.11 header has a different DA */
923 memcpy(ieee80211_get_DA(hdr), addr, ETH_ALEN);
f6dc2095
MK
924 break;
925 case RX_MSDU_DECAP_ETHERNET2_DIX:
e3fbf8d2
MK
926 /* strip ethernet header and insert decapped 802.11
927 * header, amsdu subframe header and rfc1042 header */
928
f6dc2095
MK
929 len = 0;
930 len += sizeof(struct rfc1042_hdr);
931 len += sizeof(struct amsdu_subframe_hdr);
932
933 skb_pull(skb, sizeof(struct ethhdr));
934 memcpy(skb_push(skb, len), decap_hdr, len);
935 memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
936 break;
937 case RX_MSDU_DECAP_8023_SNAP_LLC:
e3fbf8d2
MK
938 /* insert decapped 802.11 header making a singly
939 * A-MSDU */
f6dc2095
MK
940 memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
941 break;
5e3dd157
KV
942 }
943
85f6d7cf
JD
944 skb_in = skb;
945 ath10k_htt_rx_h_protected(htt, rx_status, skb_in, enctype);
5e3dd157 946 skb = skb->next;
85f6d7cf 947 skb_in->next = NULL;
5e3dd157 948
652de35e 949 if (skb)
85f6d7cf 950 rx_status->flag |= RX_FLAG_AMSDU_MORE;
87326c97 951 else
85f6d7cf 952 rx_status->flag &= ~RX_FLAG_AMSDU_MORE;
652de35e 953
85f6d7cf 954 ath10k_process_rx(htt->ar, rx_status, skb_in);
f6dc2095 955 }
5e3dd157 956
f6dc2095
MK
957 /* FIXME: It might be nice to re-assemble the A-MSDU when there's a
958 * monitor interface active for sniffing purposes. */
5e3dd157
KV
959}
960
85f6d7cf
JD
961static void ath10k_htt_rx_msdu(struct ath10k_htt *htt,
962 struct ieee80211_rx_status *rx_status,
963 struct sk_buff *skb)
5e3dd157 964{
5e3dd157
KV
965 struct htt_rx_desc *rxd;
966 struct ieee80211_hdr *hdr;
967 enum rx_msdu_decap_format fmt;
968 enum htt_rx_mpdu_encrypt_type enctype;
e3fbf8d2
MK
969 int hdr_len;
970 void *rfc1042;
5e3dd157
KV
971
972 /* This shouldn't happen. If it does than it may be a FW bug. */
973 if (skb->next) {
75fb2f94 974 ath10k_warn("htt rx received chained non A-MSDU frame\n");
5e3dd157
KV
975 ath10k_htt_rx_free_msdu_chain(skb->next);
976 skb->next = NULL;
977 }
978
979 rxd = (void *)skb->data - sizeof(*rxd);
980 fmt = MS(__le32_to_cpu(rxd->msdu_start.info1),
981 RX_MSDU_START_INFO1_DECAP_FORMAT);
982 enctype = MS(__le32_to_cpu(rxd->mpdu_start.info0),
983 RX_MPDU_START_INFO0_ENCRYPT_TYPE);
e3fbf8d2
MK
984 hdr = (struct ieee80211_hdr *)rxd->rx_hdr_status;
985 hdr_len = ieee80211_hdrlen(hdr->frame_control);
5e3dd157 986
f6dc2095
MK
987 skb->ip_summed = ath10k_htt_rx_get_csum_state(skb);
988
5e3dd157
KV
989 switch (fmt) {
990 case RX_MSDU_DECAP_RAW:
991 /* remove trailing FCS */
e3fbf8d2 992 skb_trim(skb, skb->len - FCS_LEN);
5e3dd157
KV
993 break;
994 case RX_MSDU_DECAP_NATIVE_WIFI:
784f69d3
MK
995 /* Pull decapped header */
996 hdr = (struct ieee80211_hdr *)skb->data;
d960c369 997 hdr_len = ath10k_htt_rx_nwifi_hdrlen(hdr);
784f69d3
MK
998 skb_pull(skb, hdr_len);
999
1000 /* Push original header */
1001 hdr = (struct ieee80211_hdr *)rxd->rx_hdr_status;
1002 hdr_len = ieee80211_hdrlen(hdr->frame_control);
1003 memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
5e3dd157
KV
1004 break;
1005 case RX_MSDU_DECAP_ETHERNET2_DIX:
e3fbf8d2
MK
1006 /* strip ethernet header and insert decapped 802.11 header and
1007 * rfc1042 header */
5e3dd157 1008
e3fbf8d2
MK
1009 rfc1042 = hdr;
1010 rfc1042 += roundup(hdr_len, 4);
1011 rfc1042 += roundup(ath10k_htt_rx_crypto_param_len(enctype), 4);
5e3dd157 1012
e3fbf8d2
MK
1013 skb_pull(skb, sizeof(struct ethhdr));
1014 memcpy(skb_push(skb, sizeof(struct rfc1042_hdr)),
1015 rfc1042, sizeof(struct rfc1042_hdr));
1016 memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
1017 break;
1018 case RX_MSDU_DECAP_8023_SNAP_LLC:
1019 /* remove A-MSDU subframe header and insert
1020 * decapped 802.11 header. rfc1042 header is already there */
5e3dd157 1021
e3fbf8d2
MK
1022 skb_pull(skb, sizeof(struct amsdu_subframe_hdr));
1023 memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
1024 break;
5e3dd157
KV
1025 }
1026
85f6d7cf 1027 ath10k_htt_rx_h_protected(htt, rx_status, skb, enctype);
f6dc2095 1028
85f6d7cf 1029 ath10k_process_rx(htt->ar, rx_status, skb);
5e3dd157
KV
1030}
1031
605f81aa
MK
1032static int ath10k_htt_rx_get_csum_state(struct sk_buff *skb)
1033{
1034 struct htt_rx_desc *rxd;
1035 u32 flags, info;
1036 bool is_ip4, is_ip6;
1037 bool is_tcp, is_udp;
1038 bool ip_csum_ok, tcpudp_csum_ok;
1039
1040 rxd = (void *)skb->data - sizeof(*rxd);
1041 flags = __le32_to_cpu(rxd->attention.flags);
1042 info = __le32_to_cpu(rxd->msdu_start.info1);
1043
1044 is_ip4 = !!(info & RX_MSDU_START_INFO1_IPV4_PROTO);
1045 is_ip6 = !!(info & RX_MSDU_START_INFO1_IPV6_PROTO);
1046 is_tcp = !!(info & RX_MSDU_START_INFO1_TCP_PROTO);
1047 is_udp = !!(info & RX_MSDU_START_INFO1_UDP_PROTO);
1048 ip_csum_ok = !(flags & RX_ATTENTION_FLAGS_IP_CHKSUM_FAIL);
1049 tcpudp_csum_ok = !(flags & RX_ATTENTION_FLAGS_TCP_UDP_CHKSUM_FAIL);
1050
1051 if (!is_ip4 && !is_ip6)
1052 return CHECKSUM_NONE;
1053 if (!is_tcp && !is_udp)
1054 return CHECKSUM_NONE;
1055 if (!ip_csum_ok)
1056 return CHECKSUM_NONE;
1057 if (!tcpudp_csum_ok)
1058 return CHECKSUM_NONE;
1059
1060 return CHECKSUM_UNNECESSARY;
1061}
1062
bfa35368
BG
1063static int ath10k_unchain_msdu(struct sk_buff *msdu_head)
1064{
1065 struct sk_buff *next = msdu_head->next;
1066 struct sk_buff *to_free = next;
1067 int space;
1068 int total_len = 0;
1069
1070 /* TODO: Might could optimize this by using
1071 * skb_try_coalesce or similar method to
1072 * decrease copying, or maybe get mac80211 to
1073 * provide a way to just receive a list of
1074 * skb?
1075 */
1076
1077 msdu_head->next = NULL;
1078
1079 /* Allocate total length all at once. */
1080 while (next) {
1081 total_len += next->len;
1082 next = next->next;
1083 }
1084
1085 space = total_len - skb_tailroom(msdu_head);
1086 if ((space > 0) &&
1087 (pskb_expand_head(msdu_head, 0, space, GFP_ATOMIC) < 0)) {
1088 /* TODO: bump some rx-oom error stat */
1089 /* put it back together so we can free the
1090 * whole list at once.
1091 */
1092 msdu_head->next = to_free;
1093 return -1;
1094 }
1095
1096 /* Walk list again, copying contents into
1097 * msdu_head
1098 */
1099 next = to_free;
1100 while (next) {
1101 skb_copy_from_linear_data(next, skb_put(msdu_head, next->len),
1102 next->len);
1103 next = next->next;
1104 }
1105
1106 /* If here, we have consolidated skb. Free the
1107 * fragments and pass the main skb on up the
1108 * stack.
1109 */
1110 ath10k_htt_rx_free_msdu_chain(to_free);
1111 return 0;
1112}
1113
2acc4eb2
JD
1114static bool ath10k_htt_rx_amsdu_allowed(struct ath10k_htt *htt,
1115 struct sk_buff *head,
87326c97 1116 enum htt_rx_mpdu_status status,
78433f96
JD
1117 bool channel_set,
1118 u32 attention)
2acc4eb2 1119{
2acc4eb2
JD
1120 if (head->len == 0) {
1121 ath10k_dbg(ATH10K_DBG_HTT,
1122 "htt rx dropping due to zero-len\n");
1123 return false;
1124 }
1125
78433f96 1126 if (attention & RX_ATTENTION_FLAGS_DECRYPT_ERR) {
2acc4eb2
JD
1127 ath10k_dbg(ATH10K_DBG_HTT,
1128 "htt rx dropping due to decrypt-err\n");
1129 return false;
1130 }
1131
36653f05
JD
1132 if (!channel_set) {
1133 ath10k_warn("no channel configured; ignoring frame!\n");
1134 return false;
1135 }
1136
2acc4eb2
JD
1137 /* Skip mgmt frames while we handle this in WMI */
1138 if (status == HTT_RX_IND_MPDU_STATUS_MGMT_CTRL ||
78433f96 1139 attention & RX_ATTENTION_FLAGS_MGMT_TYPE) {
2acc4eb2
JD
1140 ath10k_dbg(ATH10K_DBG_HTT, "htt rx mgmt ctrl\n");
1141 return false;
1142 }
1143
1144 if (status != HTT_RX_IND_MPDU_STATUS_OK &&
1145 status != HTT_RX_IND_MPDU_STATUS_TKIP_MIC_ERR &&
1146 status != HTT_RX_IND_MPDU_STATUS_ERR_INV_PEER &&
1bbc0975 1147 !htt->ar->monitor_started) {
2acc4eb2
JD
1148 ath10k_dbg(ATH10K_DBG_HTT,
1149 "htt rx ignoring frame w/ status %d\n",
1150 status);
1151 return false;
1152 }
1153
1154 if (test_bit(ATH10K_CAC_RUNNING, &htt->ar->dev_flags)) {
1155 ath10k_dbg(ATH10K_DBG_HTT,
1156 "htt rx CAC running\n");
1157 return false;
1158 }
1159
1160 return true;
1161}
1162
5e3dd157
KV
1163static void ath10k_htt_rx_handler(struct ath10k_htt *htt,
1164 struct htt_rx_indication *rx)
1165{
6df92a3d 1166 struct ieee80211_rx_status *rx_status = &htt->rx_status;
5e3dd157 1167 struct htt_rx_indication_mpdu_range *mpdu_ranges;
78433f96 1168 struct htt_rx_desc *rxd;
87326c97 1169 enum htt_rx_mpdu_status status;
5e3dd157
KV
1170 struct ieee80211_hdr *hdr;
1171 int num_mpdu_ranges;
78433f96 1172 u32 attention;
5e3dd157
KV
1173 int fw_desc_len;
1174 u8 *fw_desc;
78433f96 1175 bool channel_set;
5e3dd157 1176 int i, j;
d84dd60f 1177 int ret;
5e3dd157 1178
45967089
MK
1179 lockdep_assert_held(&htt->rx_ring.lock);
1180
5e3dd157
KV
1181 fw_desc_len = __le16_to_cpu(rx->prefix.fw_rx_desc_bytes);
1182 fw_desc = (u8 *)&rx->fw_desc;
1183
1184 num_mpdu_ranges = MS(__le32_to_cpu(rx->hdr.info1),
1185 HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES);
1186 mpdu_ranges = htt_rx_ind_get_mpdu_ranges(rx);
1187
e8dc1a96 1188 /* Fill this once, while this is per-ppdu */
2289188c
JD
1189 if (rx->ppdu.info0 & HTT_RX_INDICATION_INFO0_START_VALID) {
1190 memset(rx_status, 0, sizeof(*rx_status));
1191 rx_status->signal = ATH10K_DEFAULT_NOISE_FLOOR +
1192 rx->ppdu.combined_rssi;
1193 }
87326c97
JD
1194
1195 if (rx->ppdu.info0 & HTT_RX_INDICATION_INFO0_END_VALID) {
1196 /* TSF available only in 32-bit */
6df92a3d
JD
1197 rx_status->mactime = __le32_to_cpu(rx->ppdu.tsf) & 0xffffffff;
1198 rx_status->flag |= RX_FLAG_MACTIME_END;
87326c97 1199 }
e8dc1a96 1200
6df92a3d 1201 channel_set = ath10k_htt_rx_h_channel(htt->ar, rx_status);
36653f05 1202
87326c97 1203 if (channel_set) {
6df92a3d 1204 ath10k_htt_rx_h_rates(htt->ar, rx_status->band,
87326c97
JD
1205 rx->ppdu.info0,
1206 __le32_to_cpu(rx->ppdu.info1),
1207 __le32_to_cpu(rx->ppdu.info2),
6df92a3d 1208 rx_status);
87326c97 1209 }
e8dc1a96 1210
5e3dd157
KV
1211 ath10k_dbg_dump(ATH10K_DBG_HTT_DUMP, NULL, "htt rx ind: ",
1212 rx, sizeof(*rx) +
1213 (sizeof(struct htt_rx_indication_mpdu_range) *
1214 num_mpdu_ranges));
1215
1216 for (i = 0; i < num_mpdu_ranges; i++) {
87326c97 1217 status = mpdu_ranges[i].mpdu_range_status;
5e3dd157
KV
1218
1219 for (j = 0; j < mpdu_ranges[i].mpdu_count; j++) {
1220 struct sk_buff *msdu_head, *msdu_tail;
5e3dd157
KV
1221
1222 msdu_head = NULL;
1223 msdu_tail = NULL;
d84dd60f
JD
1224 ret = ath10k_htt_rx_amsdu_pop(htt,
1225 &fw_desc,
1226 &fw_desc_len,
1227 &msdu_head,
1228 &msdu_tail);
1229
1230 if (ret < 0) {
1231 ath10k_warn("failed to pop amsdu from htt rx ring %d\n",
1232 ret);
1233 ath10k_htt_rx_free_msdu_chain(msdu_head);
1234 continue;
1235 }
5e3dd157 1236
78433f96
JD
1237 rxd = container_of((void *)msdu_head->data,
1238 struct htt_rx_desc,
1239 msdu_payload);
1240 attention = __le32_to_cpu(rxd->attention.flags);
1241
2acc4eb2 1242 if (!ath10k_htt_rx_amsdu_allowed(htt, msdu_head,
87326c97 1243 status,
78433f96
JD
1244 channel_set,
1245 attention)) {
e8a50f8b
MP
1246 ath10k_htt_rx_free_msdu_chain(msdu_head);
1247 continue;
1248 }
1249
d84dd60f
JD
1250 if (ret > 0 &&
1251 ath10k_unchain_msdu(msdu_head) < 0) {
5e3dd157
KV
1252 ath10k_htt_rx_free_msdu_chain(msdu_head);
1253 continue;
1254 }
1255
78433f96 1256 if (attention & RX_ATTENTION_FLAGS_FCS_ERR)
6df92a3d 1257 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
87326c97 1258 else
6df92a3d 1259 rx_status->flag &= ~RX_FLAG_FAILED_FCS_CRC;
87326c97 1260
78433f96 1261 if (attention & RX_ATTENTION_FLAGS_TKIP_MIC_ERR)
6df92a3d 1262 rx_status->flag |= RX_FLAG_MMIC_ERROR;
87326c97 1263 else
6df92a3d 1264 rx_status->flag &= ~RX_FLAG_MMIC_ERROR;
87326c97 1265
5e3dd157
KV
1266 hdr = ath10k_htt_rx_skb_get_hdr(msdu_head);
1267
1268 if (ath10k_htt_rx_hdr_is_amsdu(hdr))
6df92a3d 1269 ath10k_htt_rx_amsdu(htt, rx_status, msdu_head);
5e3dd157 1270 else
6df92a3d 1271 ath10k_htt_rx_msdu(htt, rx_status, msdu_head);
5e3dd157
KV
1272 }
1273 }
1274
6e712d42 1275 tasklet_schedule(&htt->rx_replenish_task);
5e3dd157
KV
1276}
1277
1278static void ath10k_htt_rx_frag_handler(struct ath10k_htt *htt,
1279 struct htt_rx_fragment_indication *frag)
1280{
1281 struct sk_buff *msdu_head, *msdu_tail;
87326c97 1282 enum htt_rx_mpdu_encrypt_type enctype;
5e3dd157
KV
1283 struct htt_rx_desc *rxd;
1284 enum rx_msdu_decap_format fmt;
6df92a3d 1285 struct ieee80211_rx_status *rx_status = &htt->rx_status;
5e3dd157 1286 struct ieee80211_hdr *hdr;
d84dd60f 1287 int ret;
5e3dd157
KV
1288 bool tkip_mic_err;
1289 bool decrypt_err;
1290 u8 *fw_desc;
1291 int fw_desc_len, hdrlen, paramlen;
1292 int trim;
1293
1294 fw_desc_len = __le16_to_cpu(frag->fw_rx_desc_bytes);
1295 fw_desc = (u8 *)frag->fw_msdu_rx_desc;
1296
1297 msdu_head = NULL;
1298 msdu_tail = NULL;
45967089
MK
1299
1300 spin_lock_bh(&htt->rx_ring.lock);
d84dd60f
JD
1301 ret = ath10k_htt_rx_amsdu_pop(htt, &fw_desc, &fw_desc_len,
1302 &msdu_head, &msdu_tail);
45967089 1303 spin_unlock_bh(&htt->rx_ring.lock);
5e3dd157
KV
1304
1305 ath10k_dbg(ATH10K_DBG_HTT_DUMP, "htt rx frag ahead\n");
1306
d84dd60f
JD
1307 if (ret) {
1308 ath10k_warn("failed to pop amsdu from httr rx ring for fragmented rx %d\n",
1309 ret);
5e3dd157
KV
1310 ath10k_htt_rx_free_msdu_chain(msdu_head);
1311 return;
1312 }
1313
1314 /* FIXME: implement signal strength */
1315
1316 hdr = (struct ieee80211_hdr *)msdu_head->data;
1317 rxd = (void *)msdu_head->data - sizeof(*rxd);
1318 tkip_mic_err = !!(__le32_to_cpu(rxd->attention.flags) &
1319 RX_ATTENTION_FLAGS_TKIP_MIC_ERR);
1320 decrypt_err = !!(__le32_to_cpu(rxd->attention.flags) &
1321 RX_ATTENTION_FLAGS_DECRYPT_ERR);
1322 fmt = MS(__le32_to_cpu(rxd->msdu_start.info1),
1323 RX_MSDU_START_INFO1_DECAP_FORMAT);
1324
1325 if (fmt != RX_MSDU_DECAP_RAW) {
1326 ath10k_warn("we dont support non-raw fragmented rx yet\n");
1327 dev_kfree_skb_any(msdu_head);
1328 goto end;
1329 }
1330
87326c97
JD
1331 enctype = MS(__le32_to_cpu(rxd->mpdu_start.info0),
1332 RX_MPDU_START_INFO0_ENCRYPT_TYPE);
6df92a3d 1333 ath10k_htt_rx_h_protected(htt, rx_status, msdu_head, enctype);
85f6d7cf 1334 msdu_head->ip_summed = ath10k_htt_rx_get_csum_state(msdu_head);
5e3dd157 1335
87326c97 1336 if (tkip_mic_err)
5e3dd157 1337 ath10k_warn("tkip mic error\n");
5e3dd157
KV
1338
1339 if (decrypt_err) {
1340 ath10k_warn("decryption err in fragmented rx\n");
85f6d7cf 1341 dev_kfree_skb_any(msdu_head);
5e3dd157
KV
1342 goto end;
1343 }
1344
87326c97 1345 if (enctype != HTT_RX_MPDU_ENCRYPT_NONE) {
5e3dd157 1346 hdrlen = ieee80211_hdrlen(hdr->frame_control);
87326c97 1347 paramlen = ath10k_htt_rx_crypto_param_len(enctype);
5e3dd157
KV
1348
1349 /* It is more efficient to move the header than the payload */
85f6d7cf
JD
1350 memmove((void *)msdu_head->data + paramlen,
1351 (void *)msdu_head->data,
5e3dd157 1352 hdrlen);
85f6d7cf
JD
1353 skb_pull(msdu_head, paramlen);
1354 hdr = (struct ieee80211_hdr *)msdu_head->data;
5e3dd157
KV
1355 }
1356
1357 /* remove trailing FCS */
1358 trim = 4;
1359
1360 /* remove crypto trailer */
87326c97 1361 trim += ath10k_htt_rx_crypto_tail_len(enctype);
5e3dd157
KV
1362
1363 /* last fragment of TKIP frags has MIC */
1364 if (!ieee80211_has_morefrags(hdr->frame_control) &&
87326c97 1365 enctype == HTT_RX_MPDU_ENCRYPT_TKIP_WPA)
5e3dd157
KV
1366 trim += 8;
1367
85f6d7cf 1368 if (trim > msdu_head->len) {
5e3dd157 1369 ath10k_warn("htt rx fragment: trailer longer than the frame itself? drop\n");
85f6d7cf 1370 dev_kfree_skb_any(msdu_head);
5e3dd157
KV
1371 goto end;
1372 }
1373
85f6d7cf 1374 skb_trim(msdu_head, msdu_head->len - trim);
5e3dd157 1375
75fb2f94 1376 ath10k_dbg_dump(ATH10K_DBG_HTT_DUMP, NULL, "htt rx frag mpdu: ",
85f6d7cf 1377 msdu_head->data, msdu_head->len);
6df92a3d 1378 ath10k_process_rx(htt->ar, rx_status, msdu_head);
5e3dd157
KV
1379
1380end:
1381 if (fw_desc_len > 0) {
1382 ath10k_dbg(ATH10K_DBG_HTT,
1383 "expecting more fragmented rx in one indication %d\n",
1384 fw_desc_len);
1385 }
1386}
1387
6c5151a9
MK
1388static void ath10k_htt_rx_frm_tx_compl(struct ath10k *ar,
1389 struct sk_buff *skb)
1390{
1391 struct ath10k_htt *htt = &ar->htt;
1392 struct htt_resp *resp = (struct htt_resp *)skb->data;
1393 struct htt_tx_done tx_done = {};
1394 int status = MS(resp->data_tx_completion.flags, HTT_DATA_TX_STATUS);
1395 __le16 msdu_id;
1396 int i;
1397
45967089
MK
1398 lockdep_assert_held(&htt->tx_lock);
1399
6c5151a9
MK
1400 switch (status) {
1401 case HTT_DATA_TX_STATUS_NO_ACK:
1402 tx_done.no_ack = true;
1403 break;
1404 case HTT_DATA_TX_STATUS_OK:
1405 break;
1406 case HTT_DATA_TX_STATUS_DISCARD:
1407 case HTT_DATA_TX_STATUS_POSTPONE:
1408 case HTT_DATA_TX_STATUS_DOWNLOAD_FAIL:
1409 tx_done.discard = true;
1410 break;
1411 default:
1412 ath10k_warn("unhandled tx completion status %d\n", status);
1413 tx_done.discard = true;
1414 break;
1415 }
1416
1417 ath10k_dbg(ATH10K_DBG_HTT, "htt tx completion num_msdus %d\n",
1418 resp->data_tx_completion.num_msdus);
1419
1420 for (i = 0; i < resp->data_tx_completion.num_msdus; i++) {
1421 msdu_id = resp->data_tx_completion.msdus[i];
1422 tx_done.msdu_id = __le16_to_cpu(msdu_id);
1423 ath10k_txrx_tx_unref(htt, &tx_done);
1424 }
1425}
1426
5e3dd157
KV
1427void ath10k_htt_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb)
1428{
edb8236d 1429 struct ath10k_htt *htt = &ar->htt;
5e3dd157
KV
1430 struct htt_resp *resp = (struct htt_resp *)skb->data;
1431
1432 /* confirm alignment */
1433 if (!IS_ALIGNED((unsigned long)skb->data, 4))
1434 ath10k_warn("unaligned htt message, expect trouble\n");
1435
75fb2f94 1436 ath10k_dbg(ATH10K_DBG_HTT, "htt rx, msg_type: 0x%0X\n",
5e3dd157
KV
1437 resp->hdr.msg_type);
1438 switch (resp->hdr.msg_type) {
1439 case HTT_T2H_MSG_TYPE_VERSION_CONF: {
1440 htt->target_version_major = resp->ver_resp.major;
1441 htt->target_version_minor = resp->ver_resp.minor;
1442 complete(&htt->target_version_received);
1443 break;
1444 }
6c5151a9 1445 case HTT_T2H_MSG_TYPE_RX_IND:
45967089
MK
1446 spin_lock_bh(&htt->rx_ring.lock);
1447 __skb_queue_tail(&htt->rx_compl_q, skb);
1448 spin_unlock_bh(&htt->rx_ring.lock);
6c5151a9
MK
1449 tasklet_schedule(&htt->txrx_compl_task);
1450 return;
5e3dd157
KV
1451 case HTT_T2H_MSG_TYPE_PEER_MAP: {
1452 struct htt_peer_map_event ev = {
1453 .vdev_id = resp->peer_map.vdev_id,
1454 .peer_id = __le16_to_cpu(resp->peer_map.peer_id),
1455 };
1456 memcpy(ev.addr, resp->peer_map.addr, sizeof(ev.addr));
1457 ath10k_peer_map_event(htt, &ev);
1458 break;
1459 }
1460 case HTT_T2H_MSG_TYPE_PEER_UNMAP: {
1461 struct htt_peer_unmap_event ev = {
1462 .peer_id = __le16_to_cpu(resp->peer_unmap.peer_id),
1463 };
1464 ath10k_peer_unmap_event(htt, &ev);
1465 break;
1466 }
1467 case HTT_T2H_MSG_TYPE_MGMT_TX_COMPLETION: {
1468 struct htt_tx_done tx_done = {};
1469 int status = __le32_to_cpu(resp->mgmt_tx_completion.status);
1470
1471 tx_done.msdu_id =
1472 __le32_to_cpu(resp->mgmt_tx_completion.desc_id);
1473
1474 switch (status) {
1475 case HTT_MGMT_TX_STATUS_OK:
1476 break;
1477 case HTT_MGMT_TX_STATUS_RETRY:
1478 tx_done.no_ack = true;
1479 break;
1480 case HTT_MGMT_TX_STATUS_DROP:
1481 tx_done.discard = true;
1482 break;
1483 }
1484
6c5151a9 1485 spin_lock_bh(&htt->tx_lock);
0a89f8a0 1486 ath10k_txrx_tx_unref(htt, &tx_done);
6c5151a9 1487 spin_unlock_bh(&htt->tx_lock);
5e3dd157
KV
1488 break;
1489 }
6c5151a9
MK
1490 case HTT_T2H_MSG_TYPE_TX_COMPL_IND:
1491 spin_lock_bh(&htt->tx_lock);
1492 __skb_queue_tail(&htt->tx_compl_q, skb);
1493 spin_unlock_bh(&htt->tx_lock);
1494 tasklet_schedule(&htt->txrx_compl_task);
1495 return;
5e3dd157
KV
1496 case HTT_T2H_MSG_TYPE_SEC_IND: {
1497 struct ath10k *ar = htt->ar;
1498 struct htt_security_indication *ev = &resp->security_indication;
1499
1500 ath10k_dbg(ATH10K_DBG_HTT,
1501 "sec ind peer_id %d unicast %d type %d\n",
1502 __le16_to_cpu(ev->peer_id),
1503 !!(ev->flags & HTT_SECURITY_IS_UNICAST),
1504 MS(ev->flags, HTT_SECURITY_TYPE));
1505 complete(&ar->install_key_done);
1506 break;
1507 }
1508 case HTT_T2H_MSG_TYPE_RX_FRAG_IND: {
1509 ath10k_dbg_dump(ATH10K_DBG_HTT_DUMP, NULL, "htt event: ",
1510 skb->data, skb->len);
1511 ath10k_htt_rx_frag_handler(htt, &resp->rx_frag_ind);
1512 break;
1513 }
1514 case HTT_T2H_MSG_TYPE_TEST:
1515 /* FIX THIS */
1516 break;
5e3dd157 1517 case HTT_T2H_MSG_TYPE_STATS_CONF:
a9bf0506
KV
1518 trace_ath10k_htt_stats(skb->data, skb->len);
1519 break;
1520 case HTT_T2H_MSG_TYPE_TX_INSPECT_IND:
5e3dd157
KV
1521 case HTT_T2H_MSG_TYPE_RX_ADDBA:
1522 case HTT_T2H_MSG_TYPE_RX_DELBA:
1523 case HTT_T2H_MSG_TYPE_RX_FLUSH:
1524 default:
1525 ath10k_dbg(ATH10K_DBG_HTT, "htt event (%d) not handled\n",
1526 resp->hdr.msg_type);
1527 ath10k_dbg_dump(ATH10K_DBG_HTT_DUMP, NULL, "htt event: ",
1528 skb->data, skb->len);
1529 break;
1530 };
1531
1532 /* Free the indication buffer */
1533 dev_kfree_skb_any(skb);
1534}
6c5151a9
MK
1535
1536static void ath10k_htt_txrx_compl_task(unsigned long ptr)
1537{
1538 struct ath10k_htt *htt = (struct ath10k_htt *)ptr;
1539 struct htt_resp *resp;
1540 struct sk_buff *skb;
1541
45967089
MK
1542 spin_lock_bh(&htt->tx_lock);
1543 while ((skb = __skb_dequeue(&htt->tx_compl_q))) {
6c5151a9
MK
1544 ath10k_htt_rx_frm_tx_compl(htt->ar, skb);
1545 dev_kfree_skb_any(skb);
1546 }
45967089 1547 spin_unlock_bh(&htt->tx_lock);
6c5151a9 1548
45967089
MK
1549 spin_lock_bh(&htt->rx_ring.lock);
1550 while ((skb = __skb_dequeue(&htt->rx_compl_q))) {
6c5151a9
MK
1551 resp = (struct htt_resp *)skb->data;
1552 ath10k_htt_rx_handler(htt, &resp->rx_ind);
1553 dev_kfree_skb_any(skb);
1554 }
45967089 1555 spin_unlock_bh(&htt->rx_ring.lock);
6c5151a9 1556}