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ath9k: Move roc completion to the offchannel timer
[mirror_ubuntu-eoan-kernel.git] / drivers / net / wireless / ath / ath10k / htt_rx.c
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1/*
2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
edb8236d 18#include "core.h"
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19#include "htc.h"
20#include "htt.h"
21#include "txrx.h"
22#include "debug.h"
a9bf0506 23#include "trace.h"
aa5b4fbc 24#include "mac.h"
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25
26#include <linux/log2.h>
27
28/* slightly larger than one large A-MPDU */
29#define HTT_RX_RING_SIZE_MIN 128
30
31/* roughly 20 ms @ 1 Gbps of 1500B MSDUs */
32#define HTT_RX_RING_SIZE_MAX 2048
33
34#define HTT_RX_AVG_FRM_BYTES 1000
35
36/* ms, very conservative */
37#define HTT_RX_HOST_LATENCY_MAX_MS 20
38
39/* ms, conservative */
40#define HTT_RX_HOST_LATENCY_WORST_LIKELY_MS 10
41
42/* when under memory pressure rx ring refill may fail and needs a retry */
43#define HTT_RX_RING_REFILL_RETRY_MS 50
44
f6dc2095 45static int ath10k_htt_rx_get_csum_state(struct sk_buff *skb);
6c5151a9 46static void ath10k_htt_txrx_compl_task(unsigned long ptr);
f6dc2095 47
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48static int ath10k_htt_rx_ring_size(struct ath10k_htt *htt)
49{
50 int size;
51
52 /*
53 * It is expected that the host CPU will typically be able to
54 * service the rx indication from one A-MPDU before the rx
55 * indication from the subsequent A-MPDU happens, roughly 1-2 ms
56 * later. However, the rx ring should be sized very conservatively,
57 * to accomodate the worst reasonable delay before the host CPU
58 * services a rx indication interrupt.
59 *
60 * The rx ring need not be kept full of empty buffers. In theory,
61 * the htt host SW can dynamically track the low-water mark in the
62 * rx ring, and dynamically adjust the level to which the rx ring
63 * is filled with empty buffers, to dynamically meet the desired
64 * low-water mark.
65 *
66 * In contrast, it's difficult to resize the rx ring itself, once
67 * it's in use. Thus, the ring itself should be sized very
68 * conservatively, while the degree to which the ring is filled
69 * with empty buffers should be sized moderately conservatively.
70 */
71
72 /* 1e6 bps/mbps / 1e3 ms per sec = 1000 */
73 size =
74 htt->max_throughput_mbps +
75 1000 /
76 (8 * HTT_RX_AVG_FRM_BYTES) * HTT_RX_HOST_LATENCY_MAX_MS;
77
78 if (size < HTT_RX_RING_SIZE_MIN)
79 size = HTT_RX_RING_SIZE_MIN;
80
81 if (size > HTT_RX_RING_SIZE_MAX)
82 size = HTT_RX_RING_SIZE_MAX;
83
84 size = roundup_pow_of_two(size);
85
86 return size;
87}
88
89static int ath10k_htt_rx_ring_fill_level(struct ath10k_htt *htt)
90{
91 int size;
92
93 /* 1e6 bps/mbps / 1e3 ms per sec = 1000 */
94 size =
95 htt->max_throughput_mbps *
96 1000 /
97 (8 * HTT_RX_AVG_FRM_BYTES) * HTT_RX_HOST_LATENCY_WORST_LIKELY_MS;
98
99 /*
100 * Make sure the fill level is at least 1 less than the ring size.
101 * Leaving 1 element empty allows the SW to easily distinguish
102 * between a full ring vs. an empty ring.
103 */
104 if (size >= htt->rx_ring.size)
105 size = htt->rx_ring.size - 1;
106
107 return size;
108}
109
110static void ath10k_htt_rx_ring_free(struct ath10k_htt *htt)
111{
112 struct sk_buff *skb;
113 struct ath10k_skb_cb *cb;
114 int i;
115
116 for (i = 0; i < htt->rx_ring.fill_cnt; i++) {
117 skb = htt->rx_ring.netbufs_ring[i];
118 cb = ATH10K_SKB_CB(skb);
119 dma_unmap_single(htt->ar->dev, cb->paddr,
120 skb->len + skb_tailroom(skb),
121 DMA_FROM_DEVICE);
122 dev_kfree_skb_any(skb);
123 }
124
125 htt->rx_ring.fill_cnt = 0;
126}
127
128static int __ath10k_htt_rx_ring_fill_n(struct ath10k_htt *htt, int num)
129{
130 struct htt_rx_desc *rx_desc;
131 struct sk_buff *skb;
132 dma_addr_t paddr;
133 int ret = 0, idx;
134
8cc7f26c 135 idx = __le32_to_cpu(*htt->rx_ring.alloc_idx.vaddr);
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136 while (num > 0) {
137 skb = dev_alloc_skb(HTT_RX_BUF_SIZE + HTT_RX_DESC_ALIGN);
138 if (!skb) {
139 ret = -ENOMEM;
140 goto fail;
141 }
142
143 if (!IS_ALIGNED((unsigned long)skb->data, HTT_RX_DESC_ALIGN))
144 skb_pull(skb,
145 PTR_ALIGN(skb->data, HTT_RX_DESC_ALIGN) -
146 skb->data);
147
148 /* Clear rx_desc attention word before posting to Rx ring */
149 rx_desc = (struct htt_rx_desc *)skb->data;
150 rx_desc->attention.flags = __cpu_to_le32(0);
151
152 paddr = dma_map_single(htt->ar->dev, skb->data,
153 skb->len + skb_tailroom(skb),
154 DMA_FROM_DEVICE);
155
156 if (unlikely(dma_mapping_error(htt->ar->dev, paddr))) {
157 dev_kfree_skb_any(skb);
158 ret = -ENOMEM;
159 goto fail;
160 }
161
162 ATH10K_SKB_CB(skb)->paddr = paddr;
163 htt->rx_ring.netbufs_ring[idx] = skb;
164 htt->rx_ring.paddrs_ring[idx] = __cpu_to_le32(paddr);
165 htt->rx_ring.fill_cnt++;
166
167 num--;
168 idx++;
169 idx &= htt->rx_ring.size_mask;
170 }
171
172fail:
8cc7f26c 173 *htt->rx_ring.alloc_idx.vaddr = __cpu_to_le32(idx);
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174 return ret;
175}
176
177static int ath10k_htt_rx_ring_fill_n(struct ath10k_htt *htt, int num)
178{
179 lockdep_assert_held(&htt->rx_ring.lock);
180 return __ath10k_htt_rx_ring_fill_n(htt, num);
181}
182
183static void ath10k_htt_rx_msdu_buff_replenish(struct ath10k_htt *htt)
184{
6e712d42 185 int ret, num_deficit, num_to_fill;
5e3dd157 186
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187 /* Refilling the whole RX ring buffer proves to be a bad idea. The
188 * reason is RX may take up significant amount of CPU cycles and starve
189 * other tasks, e.g. TX on an ethernet device while acting as a bridge
190 * with ath10k wlan interface. This ended up with very poor performance
191 * once CPU the host system was overwhelmed with RX on ath10k.
192 *
193 * By limiting the number of refills the replenishing occurs
194 * progressively. This in turns makes use of the fact tasklets are
195 * processed in FIFO order. This means actual RX processing can starve
196 * out refilling. If there's not enough buffers on RX ring FW will not
197 * report RX until it is refilled with enough buffers. This
198 * automatically balances load wrt to CPU power.
199 *
200 * This probably comes at a cost of lower maximum throughput but
201 * improves the avarage and stability. */
5e3dd157 202 spin_lock_bh(&htt->rx_ring.lock);
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203 num_deficit = htt->rx_ring.fill_level - htt->rx_ring.fill_cnt;
204 num_to_fill = min(ATH10K_HTT_MAX_NUM_REFILL, num_deficit);
205 num_deficit -= num_to_fill;
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206 ret = ath10k_htt_rx_ring_fill_n(htt, num_to_fill);
207 if (ret == -ENOMEM) {
208 /*
209 * Failed to fill it to the desired level -
210 * we'll start a timer and try again next time.
211 * As long as enough buffers are left in the ring for
212 * another A-MPDU rx, no special recovery is needed.
213 */
214 mod_timer(&htt->rx_ring.refill_retry_timer, jiffies +
215 msecs_to_jiffies(HTT_RX_RING_REFILL_RETRY_MS));
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216 } else if (num_deficit > 0) {
217 tasklet_schedule(&htt->rx_replenish_task);
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218 }
219 spin_unlock_bh(&htt->rx_ring.lock);
220}
221
222static void ath10k_htt_rx_ring_refill_retry(unsigned long arg)
223{
224 struct ath10k_htt *htt = (struct ath10k_htt *)arg;
af762c0b 225
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226 ath10k_htt_rx_msdu_buff_replenish(htt);
227}
228
3e841fd0 229static void ath10k_htt_rx_ring_clean_up(struct ath10k_htt *htt)
5e3dd157 230{
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231 struct sk_buff *skb;
232 int i;
233
234 for (i = 0; i < htt->rx_ring.size; i++) {
235 skb = htt->rx_ring.netbufs_ring[i];
236 if (!skb)
237 continue;
238
239 dma_unmap_single(htt->ar->dev, ATH10K_SKB_CB(skb)->paddr,
240 skb->len + skb_tailroom(skb),
241 DMA_FROM_DEVICE);
242 dev_kfree_skb_any(skb);
243 htt->rx_ring.netbufs_ring[i] = NULL;
244 }
245}
5e3dd157 246
95bf21f9 247void ath10k_htt_rx_free(struct ath10k_htt *htt)
3e841fd0 248{
5e3dd157 249 del_timer_sync(&htt->rx_ring.refill_retry_timer);
6e712d42 250 tasklet_kill(&htt->rx_replenish_task);
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MK
251 tasklet_kill(&htt->txrx_compl_task);
252
253 skb_queue_purge(&htt->tx_compl_q);
254 skb_queue_purge(&htt->rx_compl_q);
5e3dd157 255
3e841fd0 256 ath10k_htt_rx_ring_clean_up(htt);
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257
258 dma_free_coherent(htt->ar->dev,
259 (htt->rx_ring.size *
260 sizeof(htt->rx_ring.paddrs_ring)),
261 htt->rx_ring.paddrs_ring,
262 htt->rx_ring.base_paddr);
263
264 dma_free_coherent(htt->ar->dev,
265 sizeof(*htt->rx_ring.alloc_idx.vaddr),
266 htt->rx_ring.alloc_idx.vaddr,
267 htt->rx_ring.alloc_idx.paddr);
268
269 kfree(htt->rx_ring.netbufs_ring);
270}
271
272static inline struct sk_buff *ath10k_htt_rx_netbuf_pop(struct ath10k_htt *htt)
273{
7aa7a72a 274 struct ath10k *ar = htt->ar;
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275 int idx;
276 struct sk_buff *msdu;
277
45967089 278 lockdep_assert_held(&htt->rx_ring.lock);
5e3dd157 279
8d60ee87 280 if (htt->rx_ring.fill_cnt == 0) {
7aa7a72a 281 ath10k_warn(ar, "tried to pop sk_buff from an empty rx ring\n");
8d60ee87
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282 return NULL;
283 }
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284
285 idx = htt->rx_ring.sw_rd_idx.msdu_payld;
286 msdu = htt->rx_ring.netbufs_ring[idx];
3e841fd0 287 htt->rx_ring.netbufs_ring[idx] = NULL;
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288
289 idx++;
290 idx &= htt->rx_ring.size_mask;
291 htt->rx_ring.sw_rd_idx.msdu_payld = idx;
292 htt->rx_ring.fill_cnt--;
293
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MK
294 dma_unmap_single(htt->ar->dev,
295 ATH10K_SKB_CB(msdu)->paddr,
296 msdu->len + skb_tailroom(msdu),
297 DMA_FROM_DEVICE);
298 ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt rx netbuf pop: ",
299 msdu->data, msdu->len + skb_tailroom(msdu));
4de02806 300
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301 return msdu;
302}
303
304static void ath10k_htt_rx_free_msdu_chain(struct sk_buff *skb)
305{
306 struct sk_buff *next;
307
308 while (skb) {
309 next = skb->next;
310 dev_kfree_skb_any(skb);
311 skb = next;
312 }
313}
314
d84dd60f 315/* return: < 0 fatal error, 0 - non chained msdu, 1 chained msdu */
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316static int ath10k_htt_rx_amsdu_pop(struct ath10k_htt *htt,
317 u8 **fw_desc, int *fw_desc_len,
318 struct sk_buff **head_msdu,
0ccb7a34
JD
319 struct sk_buff **tail_msdu,
320 u32 *attention)
5e3dd157 321{
7aa7a72a 322 struct ath10k *ar = htt->ar;
5e3dd157 323 int msdu_len, msdu_chaining = 0;
af762c0b 324 struct sk_buff *msdu, *next;
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325 struct htt_rx_desc *rx_desc;
326
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MK
327 lockdep_assert_held(&htt->rx_ring.lock);
328
5e3dd157 329 if (htt->rx_confused) {
7aa7a72a 330 ath10k_warn(ar, "htt is confused. refusing rx\n");
d84dd60f 331 return -1;
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332 }
333
334 msdu = *head_msdu = ath10k_htt_rx_netbuf_pop(htt);
335 while (msdu) {
336 int last_msdu, msdu_len_invalid, msdu_chained;
337
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338 rx_desc = (struct htt_rx_desc *)msdu->data;
339
340 /* FIXME: we must report msdu payload since this is what caller
341 * expects now */
342 skb_put(msdu, offsetof(struct htt_rx_desc, msdu_payload));
343 skb_pull(msdu, offsetof(struct htt_rx_desc, msdu_payload));
344
345 /*
346 * Sanity check - confirm the HW is finished filling in the
347 * rx data.
348 * If the HW and SW are working correctly, then it's guaranteed
349 * that the HW's MAC DMA is done before this point in the SW.
350 * To prevent the case that we handle a stale Rx descriptor,
351 * just assert for now until we have a way to recover.
352 */
353 if (!(__le32_to_cpu(rx_desc->attention.flags)
354 & RX_ATTENTION_FLAGS_MSDU_DONE)) {
355 ath10k_htt_rx_free_msdu_chain(*head_msdu);
356 *head_msdu = NULL;
357 msdu = NULL;
7aa7a72a 358 ath10k_err(ar, "htt rx stopped. cannot recover\n");
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359 htt->rx_confused = true;
360 break;
361 }
362
0ccb7a34
JD
363 *attention |= __le32_to_cpu(rx_desc->attention.flags) &
364 (RX_ATTENTION_FLAGS_TKIP_MIC_ERR |
365 RX_ATTENTION_FLAGS_DECRYPT_ERR |
366 RX_ATTENTION_FLAGS_FCS_ERR |
367 RX_ATTENTION_FLAGS_MGMT_TYPE);
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368 /*
369 * Copy the FW rx descriptor for this MSDU from the rx
370 * indication message into the MSDU's netbuf. HL uses the
371 * same rx indication message definition as LL, and simply
372 * appends new info (fields from the HW rx desc, and the
373 * MSDU payload itself). So, the offset into the rx
374 * indication message only has to account for the standard
375 * offset of the per-MSDU FW rx desc info within the
376 * message, and how many bytes of the per-MSDU FW rx desc
377 * info have already been consumed. (And the endianness of
378 * the host, since for a big-endian host, the rx ind
379 * message contents, including the per-MSDU rx desc bytes,
380 * were byteswapped during upload.)
381 */
382 if (*fw_desc_len > 0) {
383 rx_desc->fw_desc.info0 = **fw_desc;
384 /*
385 * The target is expected to only provide the basic
386 * per-MSDU rx descriptors. Just to be sure, verify
387 * that the target has not attached extension data
388 * (e.g. LRO flow ID).
389 */
390
391 /* or more, if there's extension data */
392 (*fw_desc)++;
393 (*fw_desc_len)--;
394 } else {
395 /*
396 * When an oversized AMSDU happened, FW will lost
397 * some of MSDU status - in this case, the FW
398 * descriptors provided will be less than the
399 * actual MSDUs inside this MPDU. Mark the FW
400 * descriptors so that it will still deliver to
401 * upper stack, if no CRC error for this MPDU.
402 *
403 * FIX THIS - the FW descriptors are actually for
404 * MSDUs in the end of this A-MSDU instead of the
405 * beginning.
406 */
407 rx_desc->fw_desc.info0 = 0;
408 }
409
410 msdu_len_invalid = !!(__le32_to_cpu(rx_desc->attention.flags)
411 & (RX_ATTENTION_FLAGS_MPDU_LENGTH_ERR |
412 RX_ATTENTION_FLAGS_MSDU_LENGTH_ERR));
413 msdu_len = MS(__le32_to_cpu(rx_desc->msdu_start.info0),
414 RX_MSDU_START_INFO0_MSDU_LENGTH);
415 msdu_chained = rx_desc->frag_info.ring2_more_count;
416
417 if (msdu_len_invalid)
418 msdu_len = 0;
419
420 skb_trim(msdu, 0);
421 skb_put(msdu, min(msdu_len, HTT_RX_MSDU_SIZE));
422 msdu_len -= msdu->len;
423
424 /* FIXME: Do chained buffers include htt_rx_desc or not? */
425 while (msdu_chained--) {
426 struct sk_buff *next = ath10k_htt_rx_netbuf_pop(htt);
427
b30595ae
MK
428 if (!next) {
429 ath10k_warn(ar, "failed to pop chained msdu\n");
430 ath10k_htt_rx_free_msdu_chain(*head_msdu);
431 *head_msdu = NULL;
432 msdu = NULL;
433 htt->rx_confused = true;
434 break;
435 }
436
5e3dd157
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437 skb_trim(next, 0);
438 skb_put(next, min(msdu_len, HTT_RX_BUF_SIZE));
439 msdu_len -= next->len;
440
441 msdu->next = next;
442 msdu = next;
ede9c8e0 443 msdu_chaining = 1;
5e3dd157
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444 }
445
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446 last_msdu = __le32_to_cpu(rx_desc->msdu_end.info0) &
447 RX_MSDU_END_INFO0_LAST_MSDU;
448
b04e204f 449 trace_ath10k_htt_rx_desc(ar, &rx_desc->attention,
a0883cf7 450 sizeof(*rx_desc) - sizeof(u32));
5e3dd157
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451 if (last_msdu) {
452 msdu->next = NULL;
453 break;
5e3dd157 454 }
d8bb26b9
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455
456 next = ath10k_htt_rx_netbuf_pop(htt);
457 msdu->next = next;
458 msdu = next;
5e3dd157
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459 }
460 *tail_msdu = msdu;
461
d84dd60f
JD
462 if (*head_msdu == NULL)
463 msdu_chaining = -1;
464
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465 /*
466 * Don't refill the ring yet.
467 *
468 * First, the elements popped here are still in use - it is not
469 * safe to overwrite them until the matching call to
470 * mpdu_desc_list_next. Second, for efficiency it is preferable to
471 * refill the rx ring with 1 PPDU's worth of rx buffers (something
472 * like 32 x 3 buffers), rather than one MPDU's worth of rx buffers
473 * (something like 3 buffers). Consequently, we'll rely on the txrx
474 * SW to tell us when it is done pulling all the PPDU's rx buffers
475 * out of the rx ring, and then refill it just once.
476 */
477
478 return msdu_chaining;
479}
480
6e712d42
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481static void ath10k_htt_rx_replenish_task(unsigned long ptr)
482{
483 struct ath10k_htt *htt = (struct ath10k_htt *)ptr;
af762c0b 484
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MK
485 ath10k_htt_rx_msdu_buff_replenish(htt);
486}
487
95bf21f9 488int ath10k_htt_rx_alloc(struct ath10k_htt *htt)
5e3dd157 489{
7aa7a72a 490 struct ath10k *ar = htt->ar;
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491 dma_addr_t paddr;
492 void *vaddr;
bd8bdbb6 493 size_t size;
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494 struct timer_list *timer = &htt->rx_ring.refill_retry_timer;
495
51fc7d74
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496 htt->rx_confused = false;
497
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498 htt->rx_ring.size = ath10k_htt_rx_ring_size(htt);
499 if (!is_power_of_2(htt->rx_ring.size)) {
7aa7a72a 500 ath10k_warn(ar, "htt rx ring size is not power of 2\n");
5e3dd157
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501 return -EINVAL;
502 }
503
504 htt->rx_ring.size_mask = htt->rx_ring.size - 1;
505
506 /*
507 * Set the initial value for the level to which the rx ring
508 * should be filled, based on the max throughput and the
509 * worst likely latency for the host to fill the rx ring
510 * with new buffers. In theory, this fill level can be
511 * dynamically adjusted from the initial value set here, to
512 * reflect the actual host latency rather than a
513 * conservative assumption about the host latency.
514 */
515 htt->rx_ring.fill_level = ath10k_htt_rx_ring_fill_level(htt);
516
517 htt->rx_ring.netbufs_ring =
3e841fd0 518 kzalloc(htt->rx_ring.size * sizeof(struct sk_buff *),
5e3dd157
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519 GFP_KERNEL);
520 if (!htt->rx_ring.netbufs_ring)
521 goto err_netbuf;
522
bd8bdbb6
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523 size = htt->rx_ring.size * sizeof(htt->rx_ring.paddrs_ring);
524
525 vaddr = dma_alloc_coherent(htt->ar->dev, size, &paddr, GFP_DMA);
5e3dd157
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526 if (!vaddr)
527 goto err_dma_ring;
528
529 htt->rx_ring.paddrs_ring = vaddr;
530 htt->rx_ring.base_paddr = paddr;
531
532 vaddr = dma_alloc_coherent(htt->ar->dev,
533 sizeof(*htt->rx_ring.alloc_idx.vaddr),
534 &paddr, GFP_DMA);
535 if (!vaddr)
536 goto err_dma_idx;
537
538 htt->rx_ring.alloc_idx.vaddr = vaddr;
539 htt->rx_ring.alloc_idx.paddr = paddr;
540 htt->rx_ring.sw_rd_idx.msdu_payld = 0;
541 *htt->rx_ring.alloc_idx.vaddr = 0;
542
543 /* Initialize the Rx refill retry timer */
544 setup_timer(timer, ath10k_htt_rx_ring_refill_retry, (unsigned long)htt);
545
546 spin_lock_init(&htt->rx_ring.lock);
547
548 htt->rx_ring.fill_cnt = 0;
549 if (__ath10k_htt_rx_ring_fill_n(htt, htt->rx_ring.fill_level))
550 goto err_fill_ring;
551
6e712d42
MK
552 tasklet_init(&htt->rx_replenish_task, ath10k_htt_rx_replenish_task,
553 (unsigned long)htt);
554
6c5151a9
MK
555 skb_queue_head_init(&htt->tx_compl_q);
556 skb_queue_head_init(&htt->rx_compl_q);
557
558 tasklet_init(&htt->txrx_compl_task, ath10k_htt_txrx_compl_task,
559 (unsigned long)htt);
560
7aa7a72a 561 ath10k_dbg(ar, ATH10K_DBG_BOOT, "htt rx ring size %d fill_level %d\n",
5e3dd157
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562 htt->rx_ring.size, htt->rx_ring.fill_level);
563 return 0;
564
565err_fill_ring:
566 ath10k_htt_rx_ring_free(htt);
567 dma_free_coherent(htt->ar->dev,
568 sizeof(*htt->rx_ring.alloc_idx.vaddr),
569 htt->rx_ring.alloc_idx.vaddr,
570 htt->rx_ring.alloc_idx.paddr);
571err_dma_idx:
572 dma_free_coherent(htt->ar->dev,
573 (htt->rx_ring.size *
574 sizeof(htt->rx_ring.paddrs_ring)),
575 htt->rx_ring.paddrs_ring,
576 htt->rx_ring.base_paddr);
577err_dma_ring:
578 kfree(htt->rx_ring.netbufs_ring);
579err_netbuf:
580 return -ENOMEM;
581}
582
7aa7a72a
MK
583static int ath10k_htt_rx_crypto_param_len(struct ath10k *ar,
584 enum htt_rx_mpdu_encrypt_type type)
5e3dd157
KV
585{
586 switch (type) {
890d3b2a
MK
587 case HTT_RX_MPDU_ENCRYPT_NONE:
588 return 0;
5e3dd157
KV
589 case HTT_RX_MPDU_ENCRYPT_WEP40:
590 case HTT_RX_MPDU_ENCRYPT_WEP104:
890d3b2a 591 return IEEE80211_WEP_IV_LEN;
5e3dd157 592 case HTT_RX_MPDU_ENCRYPT_TKIP_WITHOUT_MIC:
5e3dd157 593 case HTT_RX_MPDU_ENCRYPT_TKIP_WPA:
890d3b2a 594 return IEEE80211_TKIP_IV_LEN;
5e3dd157 595 case HTT_RX_MPDU_ENCRYPT_AES_CCM_WPA2:
890d3b2a
MK
596 return IEEE80211_CCMP_HDR_LEN;
597 case HTT_RX_MPDU_ENCRYPT_WEP128:
598 case HTT_RX_MPDU_ENCRYPT_WAPI:
599 break;
5e3dd157
KV
600 }
601
890d3b2a 602 ath10k_warn(ar, "unsupported encryption type %d\n", type);
5e3dd157
KV
603 return 0;
604}
605
890d3b2a
MK
606#define MICHAEL_MIC_LEN 8
607
7aa7a72a
MK
608static int ath10k_htt_rx_crypto_tail_len(struct ath10k *ar,
609 enum htt_rx_mpdu_encrypt_type type)
5e3dd157
KV
610{
611 switch (type) {
612 case HTT_RX_MPDU_ENCRYPT_NONE:
890d3b2a 613 return 0;
5e3dd157
KV
614 case HTT_RX_MPDU_ENCRYPT_WEP40:
615 case HTT_RX_MPDU_ENCRYPT_WEP104:
890d3b2a 616 return IEEE80211_WEP_ICV_LEN;
5e3dd157
KV
617 case HTT_RX_MPDU_ENCRYPT_TKIP_WITHOUT_MIC:
618 case HTT_RX_MPDU_ENCRYPT_TKIP_WPA:
890d3b2a 619 return IEEE80211_TKIP_ICV_LEN;
5e3dd157 620 case HTT_RX_MPDU_ENCRYPT_AES_CCM_WPA2:
890d3b2a
MK
621 return IEEE80211_CCMP_MIC_LEN;
622 case HTT_RX_MPDU_ENCRYPT_WEP128:
623 case HTT_RX_MPDU_ENCRYPT_WAPI:
624 break;
5e3dd157
KV
625 }
626
890d3b2a 627 ath10k_warn(ar, "unsupported encryption type %d\n", type);
5e3dd157
KV
628 return 0;
629}
630
631/* Applies for first msdu in chain, before altering it. */
632static struct ieee80211_hdr *ath10k_htt_rx_skb_get_hdr(struct sk_buff *skb)
633{
634 struct htt_rx_desc *rxd;
635 enum rx_msdu_decap_format fmt;
636
637 rxd = (void *)skb->data - sizeof(*rxd);
638 fmt = MS(__le32_to_cpu(rxd->msdu_start.info1),
5b07e07f 639 RX_MSDU_START_INFO1_DECAP_FORMAT);
5e3dd157
KV
640
641 if (fmt == RX_MSDU_DECAP_RAW)
642 return (void *)skb->data;
d8bb26b9
KV
643
644 return (void *)skb->data - RX_HTT_HDR_STATUS_LEN;
5e3dd157
KV
645}
646
647/* This function only applies for first msdu in an msdu chain */
648static bool ath10k_htt_rx_hdr_is_amsdu(struct ieee80211_hdr *hdr)
649{
af762c0b
KV
650 u8 *qc;
651
5e3dd157 652 if (ieee80211_is_data_qos(hdr->frame_control)) {
af762c0b 653 qc = ieee80211_get_qos_ctl(hdr);
5e3dd157
KV
654 if (qc[0] & 0x80)
655 return true;
656 }
657 return false;
658}
659
f6dc2095
MK
660struct rfc1042_hdr {
661 u8 llc_dsap;
662 u8 llc_ssap;
663 u8 llc_ctrl;
664 u8 snap_oui[3];
665 __be16 snap_type;
666} __packed;
667
668struct amsdu_subframe_hdr {
669 u8 dst[ETH_ALEN];
670 u8 src[ETH_ALEN];
671 __be16 len;
672} __packed;
673
73539b40
JD
674static const u8 rx_legacy_rate_idx[] = {
675 3, /* 0x00 - 11Mbps */
676 2, /* 0x01 - 5.5Mbps */
677 1, /* 0x02 - 2Mbps */
678 0, /* 0x03 - 1Mbps */
679 3, /* 0x04 - 11Mbps */
680 2, /* 0x05 - 5.5Mbps */
681 1, /* 0x06 - 2Mbps */
682 0, /* 0x07 - 1Mbps */
683 10, /* 0x08 - 48Mbps */
684 8, /* 0x09 - 24Mbps */
685 6, /* 0x0A - 12Mbps */
686 4, /* 0x0B - 6Mbps */
687 11, /* 0x0C - 54Mbps */
688 9, /* 0x0D - 36Mbps */
689 7, /* 0x0E - 18Mbps */
690 5, /* 0x0F - 9Mbps */
691};
692
87326c97 693static void ath10k_htt_rx_h_rates(struct ath10k *ar,
cfadd9ba 694 enum ieee80211_band band,
87326c97 695 u8 info0, u32 info1, u32 info2,
cfadd9ba 696 struct ieee80211_rx_status *status)
73539b40
JD
697{
698 u8 cck, rate, rate_idx, bw, sgi, mcs, nss;
73539b40
JD
699 u8 preamble = 0;
700
701 /* Check if valid fields */
702 if (!(info0 & HTT_RX_INDICATION_INFO0_START_VALID))
703 return;
704
705 preamble = MS(info1, HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE);
706
707 switch (preamble) {
708 case HTT_RX_LEGACY:
709 cck = info0 & HTT_RX_INDICATION_INFO0_LEGACY_RATE_CCK;
710 rate = MS(info0, HTT_RX_INDICATION_INFO0_LEGACY_RATE);
711 rate_idx = 0;
712
713 if (rate < 0x08 || rate > 0x0F)
714 break;
715
716 switch (band) {
717 case IEEE80211_BAND_2GHZ:
718 if (cck)
719 rate &= ~BIT(3);
720 rate_idx = rx_legacy_rate_idx[rate];
721 break;
722 case IEEE80211_BAND_5GHZ:
723 rate_idx = rx_legacy_rate_idx[rate];
724 /* We are using same rate table registering
725 HW - ath10k_rates[]. In case of 5GHz skip
726 CCK rates, so -4 here */
727 rate_idx -= 4;
728 break;
729 default:
730 break;
731 }
732
733 status->rate_idx = rate_idx;
734 break;
735 case HTT_RX_HT:
736 case HTT_RX_HT_WITH_TXBF:
737 /* HT-SIG - Table 20-11 in info1 and info2 */
738 mcs = info1 & 0x1F;
739 nss = mcs >> 3;
740 bw = (info1 >> 7) & 1;
741 sgi = (info2 >> 7) & 1;
742
743 status->rate_idx = mcs;
744 status->flag |= RX_FLAG_HT;
745 if (sgi)
746 status->flag |= RX_FLAG_SHORT_GI;
747 if (bw)
748 status->flag |= RX_FLAG_40MHZ;
749 break;
750 case HTT_RX_VHT:
751 case HTT_RX_VHT_WITH_TXBF:
752 /* VHT-SIG-A1 in info 1, VHT-SIG-A2 in info2
753 TODO check this */
754 mcs = (info2 >> 4) & 0x0F;
755 nss = ((info1 >> 10) & 0x07) + 1;
756 bw = info1 & 3;
757 sgi = info2 & 1;
758
759 status->rate_idx = mcs;
760 status->vht_nss = nss;
761
762 if (sgi)
763 status->flag |= RX_FLAG_SHORT_GI;
764
765 switch (bw) {
766 /* 20MHZ */
767 case 0:
768 break;
769 /* 40MHZ */
770 case 1:
771 status->flag |= RX_FLAG_40MHZ;
772 break;
773 /* 80MHZ */
774 case 2:
775 status->vht_flag |= RX_VHT_FLAG_80MHZ;
776 }
777
778 status->flag |= RX_FLAG_VHT;
779 break;
780 default:
781 break;
782 }
783}
784
87326c97 785static void ath10k_htt_rx_h_protected(struct ath10k_htt *htt,
85f6d7cf
JD
786 struct ieee80211_rx_status *rx_status,
787 struct sk_buff *skb,
c071dcb2
MK
788 enum htt_rx_mpdu_encrypt_type enctype,
789 enum rx_msdu_decap_format fmt,
790 bool dot11frag)
87326c97 791{
85f6d7cf 792 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
87326c97 793
c071dcb2
MK
794 rx_status->flag &= ~(RX_FLAG_DECRYPTED |
795 RX_FLAG_IV_STRIPPED |
796 RX_FLAG_MMIC_STRIPPED);
87326c97 797
c071dcb2
MK
798 if (enctype == HTT_RX_MPDU_ENCRYPT_NONE)
799 return;
800
801 /*
802 * There's no explicit rx descriptor flag to indicate whether a given
803 * frame has been decrypted or not. We're forced to use the decap
804 * format as an implicit indication. However fragmentation rx is always
805 * raw and it probably never reports undecrypted raws.
806 *
807 * This makes sure sniffed frames are reported as-is without stripping
808 * the protected flag.
809 */
810 if (fmt == RX_MSDU_DECAP_RAW && !dot11frag)
87326c97 811 return;
87326c97 812
85f6d7cf
JD
813 rx_status->flag |= RX_FLAG_DECRYPTED |
814 RX_FLAG_IV_STRIPPED |
815 RX_FLAG_MMIC_STRIPPED;
87326c97
JD
816 hdr->frame_control = __cpu_to_le16(__le16_to_cpu(hdr->frame_control) &
817 ~IEEE80211_FCTL_PROTECTED);
818}
819
36653f05
JD
820static bool ath10k_htt_rx_h_channel(struct ath10k *ar,
821 struct ieee80211_rx_status *status)
822{
823 struct ieee80211_channel *ch;
824
825 spin_lock_bh(&ar->data_lock);
826 ch = ar->scan_channel;
827 if (!ch)
828 ch = ar->rx_channel;
829 spin_unlock_bh(&ar->data_lock);
830
831 if (!ch)
832 return false;
833
834 status->band = ch->band;
835 status->freq = ch->center_freq;
836
837 return true;
838}
839
76f5329a
JD
840static const char * const tid_to_ac[] = {
841 "BE",
842 "BK",
843 "BK",
844 "BE",
845 "VI",
846 "VI",
847 "VO",
848 "VO",
849};
850
851static char *ath10k_get_tid(struct ieee80211_hdr *hdr, char *out, size_t size)
852{
853 u8 *qc;
854 int tid;
855
856 if (!ieee80211_is_data_qos(hdr->frame_control))
857 return "";
858
859 qc = ieee80211_get_qos_ctl(hdr);
860 tid = *qc & IEEE80211_QOS_CTL_TID_MASK;
861 if (tid < 8)
862 snprintf(out, size, "tid %d (%s)", tid, tid_to_ac[tid]);
863 else
864 snprintf(out, size, "tid %d", tid);
865
866 return out;
867}
868
85f6d7cf
JD
869static void ath10k_process_rx(struct ath10k *ar,
870 struct ieee80211_rx_status *rx_status,
871 struct sk_buff *skb)
73539b40
JD
872{
873 struct ieee80211_rx_status *status;
76f5329a
JD
874 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
875 char tid[32];
73539b40 876
85f6d7cf
JD
877 status = IEEE80211_SKB_RXCB(skb);
878 *status = *rx_status;
73539b40 879
7aa7a72a 880 ath10k_dbg(ar, ATH10K_DBG_DATA,
76f5329a 881 "rx skb %p len %u peer %pM %s %s sn %u %s%s%s%s%s %srate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n",
85f6d7cf
JD
882 skb,
883 skb->len,
76f5329a
JD
884 ieee80211_get_SA(hdr),
885 ath10k_get_tid(hdr, tid, sizeof(tid)),
886 is_multicast_ether_addr(ieee80211_get_DA(hdr)) ?
887 "mcast" : "ucast",
888 (__le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4,
73539b40
JD
889 status->flag == 0 ? "legacy" : "",
890 status->flag & RX_FLAG_HT ? "ht" : "",
891 status->flag & RX_FLAG_VHT ? "vht" : "",
892 status->flag & RX_FLAG_40MHZ ? "40" : "",
893 status->vht_flag & RX_VHT_FLAG_80MHZ ? "80" : "",
894 status->flag & RX_FLAG_SHORT_GI ? "sgi " : "",
895 status->rate_idx,
896 status->vht_nss,
897 status->freq,
87326c97 898 status->band, status->flag,
78433f96 899 !!(status->flag & RX_FLAG_FAILED_FCS_CRC),
76f5329a
JD
900 !!(status->flag & RX_FLAG_MMIC_ERROR),
901 !!(status->flag & RX_FLAG_AMSDU_MORE));
7aa7a72a 902 ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "rx skb: ",
85f6d7cf 903 skb->data, skb->len);
5ce8e7fd
RM
904 trace_ath10k_rx_hdr(ar, skb->data, skb->len);
905 trace_ath10k_rx_payload(ar, skb->data, skb->len);
73539b40 906
85f6d7cf 907 ieee80211_rx(ar->hw, skb);
73539b40
JD
908}
909
d960c369
MK
910static int ath10k_htt_rx_nwifi_hdrlen(struct ieee80211_hdr *hdr)
911{
912 /* nwifi header is padded to 4 bytes. this fixes 4addr rx */
913 return round_up(ieee80211_hdrlen(hdr->frame_control), 4);
914}
915
f6dc2095 916static void ath10k_htt_rx_amsdu(struct ath10k_htt *htt,
85f6d7cf
JD
917 struct ieee80211_rx_status *rx_status,
918 struct sk_buff *skb_in)
5e3dd157 919{
7aa7a72a 920 struct ath10k *ar = htt->ar;
5e3dd157 921 struct htt_rx_desc *rxd;
85f6d7cf 922 struct sk_buff *skb = skb_in;
5e3dd157 923 struct sk_buff *first;
5e3dd157
KV
924 enum rx_msdu_decap_format fmt;
925 enum htt_rx_mpdu_encrypt_type enctype;
f6dc2095 926 struct ieee80211_hdr *hdr;
72bdeb86 927 u8 hdr_buf[64], da[ETH_ALEN], sa[ETH_ALEN], *qos;
5e3dd157 928 unsigned int hdr_len;
5e3dd157
KV
929
930 rxd = (void *)skb->data - sizeof(*rxd);
5e3dd157 931 enctype = MS(__le32_to_cpu(rxd->mpdu_start.info0),
5b07e07f 932 RX_MPDU_START_INFO0_ENCRYPT_TYPE);
5e3dd157 933
f6dc2095
MK
934 hdr = (struct ieee80211_hdr *)rxd->rx_hdr_status;
935 hdr_len = ieee80211_hdrlen(hdr->frame_control);
936 memcpy(hdr_buf, hdr, hdr_len);
937 hdr = (struct ieee80211_hdr *)hdr_buf;
5e3dd157 938
5e3dd157
KV
939 first = skb;
940 while (skb) {
941 void *decap_hdr;
f6dc2095 942 int len;
5e3dd157
KV
943
944 rxd = (void *)skb->data - sizeof(*rxd);
945 fmt = MS(__le32_to_cpu(rxd->msdu_start.info1),
f6dc2095 946 RX_MSDU_START_INFO1_DECAP_FORMAT);
5e3dd157
KV
947 decap_hdr = (void *)rxd->rx_hdr_status;
948
f6dc2095 949 skb->ip_summed = ath10k_htt_rx_get_csum_state(skb);
5e3dd157 950
f6dc2095
MK
951 /* First frame in an A-MSDU chain has more decapped data. */
952 if (skb == first) {
953 len = round_up(ieee80211_hdrlen(hdr->frame_control), 4);
7aa7a72a
MK
954 len += round_up(ath10k_htt_rx_crypto_param_len(ar,
955 enctype), 4);
f6dc2095 956 decap_hdr += len;
5e3dd157
KV
957 }
958
f6dc2095
MK
959 switch (fmt) {
960 case RX_MSDU_DECAP_RAW:
e3fbf8d2 961 /* remove trailing FCS */
f6dc2095
MK
962 skb_trim(skb, skb->len - FCS_LEN);
963 break;
964 case RX_MSDU_DECAP_NATIVE_WIFI:
72bdeb86 965 /* pull decapped header and copy SA & DA */
784f69d3 966 hdr = (struct ieee80211_hdr *)skb->data;
d960c369 967 hdr_len = ath10k_htt_rx_nwifi_hdrlen(hdr);
b25f32cb
KV
968 ether_addr_copy(da, ieee80211_get_DA(hdr));
969 ether_addr_copy(sa, ieee80211_get_SA(hdr));
784f69d3
MK
970 skb_pull(skb, hdr_len);
971
972 /* push original 802.11 header */
973 hdr = (struct ieee80211_hdr *)hdr_buf;
974 hdr_len = ieee80211_hdrlen(hdr->frame_control);
975 memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
976
977 /* original A-MSDU header has the bit set but we're
978 * not including A-MSDU subframe header */
979 hdr = (struct ieee80211_hdr *)skb->data;
980 qos = ieee80211_get_qos_ctl(hdr);
981 qos[0] &= ~IEEE80211_QOS_CTL_A_MSDU_PRESENT;
982
72bdeb86
MK
983 /* original 802.11 header has a different DA and in
984 * case of 4addr it may also have different SA
985 */
b25f32cb
KV
986 ether_addr_copy(ieee80211_get_DA(hdr), da);
987 ether_addr_copy(ieee80211_get_SA(hdr), sa);
f6dc2095
MK
988 break;
989 case RX_MSDU_DECAP_ETHERNET2_DIX:
e3fbf8d2
MK
990 /* strip ethernet header and insert decapped 802.11
991 * header, amsdu subframe header and rfc1042 header */
992
f6dc2095
MK
993 len = 0;
994 len += sizeof(struct rfc1042_hdr);
995 len += sizeof(struct amsdu_subframe_hdr);
996
997 skb_pull(skb, sizeof(struct ethhdr));
998 memcpy(skb_push(skb, len), decap_hdr, len);
999 memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
1000 break;
1001 case RX_MSDU_DECAP_8023_SNAP_LLC:
e3fbf8d2
MK
1002 /* insert decapped 802.11 header making a singly
1003 * A-MSDU */
f6dc2095
MK
1004 memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
1005 break;
5e3dd157
KV
1006 }
1007
85f6d7cf 1008 skb_in = skb;
c071dcb2
MK
1009 ath10k_htt_rx_h_protected(htt, rx_status, skb_in, enctype, fmt,
1010 false);
5e3dd157 1011 skb = skb->next;
85f6d7cf 1012 skb_in->next = NULL;
5e3dd157 1013
652de35e 1014 if (skb)
85f6d7cf 1015 rx_status->flag |= RX_FLAG_AMSDU_MORE;
87326c97 1016 else
85f6d7cf 1017 rx_status->flag &= ~RX_FLAG_AMSDU_MORE;
652de35e 1018
85f6d7cf 1019 ath10k_process_rx(htt->ar, rx_status, skb_in);
f6dc2095 1020 }
5e3dd157 1021
f6dc2095
MK
1022 /* FIXME: It might be nice to re-assemble the A-MSDU when there's a
1023 * monitor interface active for sniffing purposes. */
5e3dd157
KV
1024}
1025
85f6d7cf
JD
1026static void ath10k_htt_rx_msdu(struct ath10k_htt *htt,
1027 struct ieee80211_rx_status *rx_status,
1028 struct sk_buff *skb)
5e3dd157 1029{
7aa7a72a 1030 struct ath10k *ar = htt->ar;
5e3dd157
KV
1031 struct htt_rx_desc *rxd;
1032 struct ieee80211_hdr *hdr;
1033 enum rx_msdu_decap_format fmt;
1034 enum htt_rx_mpdu_encrypt_type enctype;
e3fbf8d2
MK
1035 int hdr_len;
1036 void *rfc1042;
5e3dd157
KV
1037
1038 /* This shouldn't happen. If it does than it may be a FW bug. */
1039 if (skb->next) {
7aa7a72a 1040 ath10k_warn(ar, "htt rx received chained non A-MSDU frame\n");
5e3dd157
KV
1041 ath10k_htt_rx_free_msdu_chain(skb->next);
1042 skb->next = NULL;
1043 }
1044
1045 rxd = (void *)skb->data - sizeof(*rxd);
1046 fmt = MS(__le32_to_cpu(rxd->msdu_start.info1),
5b07e07f 1047 RX_MSDU_START_INFO1_DECAP_FORMAT);
5e3dd157 1048 enctype = MS(__le32_to_cpu(rxd->mpdu_start.info0),
5b07e07f 1049 RX_MPDU_START_INFO0_ENCRYPT_TYPE);
e3fbf8d2
MK
1050 hdr = (struct ieee80211_hdr *)rxd->rx_hdr_status;
1051 hdr_len = ieee80211_hdrlen(hdr->frame_control);
5e3dd157 1052
f6dc2095
MK
1053 skb->ip_summed = ath10k_htt_rx_get_csum_state(skb);
1054
5e3dd157
KV
1055 switch (fmt) {
1056 case RX_MSDU_DECAP_RAW:
1057 /* remove trailing FCS */
e3fbf8d2 1058 skb_trim(skb, skb->len - FCS_LEN);
5e3dd157
KV
1059 break;
1060 case RX_MSDU_DECAP_NATIVE_WIFI:
784f69d3
MK
1061 /* Pull decapped header */
1062 hdr = (struct ieee80211_hdr *)skb->data;
d960c369 1063 hdr_len = ath10k_htt_rx_nwifi_hdrlen(hdr);
784f69d3
MK
1064 skb_pull(skb, hdr_len);
1065
1066 /* Push original header */
1067 hdr = (struct ieee80211_hdr *)rxd->rx_hdr_status;
1068 hdr_len = ieee80211_hdrlen(hdr->frame_control);
1069 memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
5e3dd157
KV
1070 break;
1071 case RX_MSDU_DECAP_ETHERNET2_DIX:
e3fbf8d2
MK
1072 /* strip ethernet header and insert decapped 802.11 header and
1073 * rfc1042 header */
5e3dd157 1074
e3fbf8d2
MK
1075 rfc1042 = hdr;
1076 rfc1042 += roundup(hdr_len, 4);
7aa7a72a
MK
1077 rfc1042 += roundup(ath10k_htt_rx_crypto_param_len(ar,
1078 enctype), 4);
5e3dd157 1079
e3fbf8d2
MK
1080 skb_pull(skb, sizeof(struct ethhdr));
1081 memcpy(skb_push(skb, sizeof(struct rfc1042_hdr)),
1082 rfc1042, sizeof(struct rfc1042_hdr));
1083 memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
1084 break;
1085 case RX_MSDU_DECAP_8023_SNAP_LLC:
1086 /* remove A-MSDU subframe header and insert
1087 * decapped 802.11 header. rfc1042 header is already there */
5e3dd157 1088
e3fbf8d2
MK
1089 skb_pull(skb, sizeof(struct amsdu_subframe_hdr));
1090 memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
1091 break;
5e3dd157
KV
1092 }
1093
c071dcb2 1094 ath10k_htt_rx_h_protected(htt, rx_status, skb, enctype, fmt, false);
f6dc2095 1095
85f6d7cf 1096 ath10k_process_rx(htt->ar, rx_status, skb);
5e3dd157
KV
1097}
1098
605f81aa
MK
1099static int ath10k_htt_rx_get_csum_state(struct sk_buff *skb)
1100{
1101 struct htt_rx_desc *rxd;
1102 u32 flags, info;
1103 bool is_ip4, is_ip6;
1104 bool is_tcp, is_udp;
1105 bool ip_csum_ok, tcpudp_csum_ok;
1106
1107 rxd = (void *)skb->data - sizeof(*rxd);
1108 flags = __le32_to_cpu(rxd->attention.flags);
1109 info = __le32_to_cpu(rxd->msdu_start.info1);
1110
1111 is_ip4 = !!(info & RX_MSDU_START_INFO1_IPV4_PROTO);
1112 is_ip6 = !!(info & RX_MSDU_START_INFO1_IPV6_PROTO);
1113 is_tcp = !!(info & RX_MSDU_START_INFO1_TCP_PROTO);
1114 is_udp = !!(info & RX_MSDU_START_INFO1_UDP_PROTO);
1115 ip_csum_ok = !(flags & RX_ATTENTION_FLAGS_IP_CHKSUM_FAIL);
1116 tcpudp_csum_ok = !(flags & RX_ATTENTION_FLAGS_TCP_UDP_CHKSUM_FAIL);
1117
1118 if (!is_ip4 && !is_ip6)
1119 return CHECKSUM_NONE;
1120 if (!is_tcp && !is_udp)
1121 return CHECKSUM_NONE;
1122 if (!ip_csum_ok)
1123 return CHECKSUM_NONE;
1124 if (!tcpudp_csum_ok)
1125 return CHECKSUM_NONE;
1126
1127 return CHECKSUM_UNNECESSARY;
1128}
1129
bfa35368
BG
1130static int ath10k_unchain_msdu(struct sk_buff *msdu_head)
1131{
1132 struct sk_buff *next = msdu_head->next;
1133 struct sk_buff *to_free = next;
1134 int space;
1135 int total_len = 0;
1136
1137 /* TODO: Might could optimize this by using
1138 * skb_try_coalesce or similar method to
1139 * decrease copying, or maybe get mac80211 to
1140 * provide a way to just receive a list of
1141 * skb?
1142 */
1143
1144 msdu_head->next = NULL;
1145
1146 /* Allocate total length all at once. */
1147 while (next) {
1148 total_len += next->len;
1149 next = next->next;
1150 }
1151
1152 space = total_len - skb_tailroom(msdu_head);
1153 if ((space > 0) &&
1154 (pskb_expand_head(msdu_head, 0, space, GFP_ATOMIC) < 0)) {
1155 /* TODO: bump some rx-oom error stat */
1156 /* put it back together so we can free the
1157 * whole list at once.
1158 */
1159 msdu_head->next = to_free;
1160 return -1;
1161 }
1162
1163 /* Walk list again, copying contents into
1164 * msdu_head
1165 */
1166 next = to_free;
1167 while (next) {
1168 skb_copy_from_linear_data(next, skb_put(msdu_head, next->len),
1169 next->len);
1170 next = next->next;
1171 }
1172
1173 /* If here, we have consolidated skb. Free the
1174 * fragments and pass the main skb on up the
1175 * stack.
1176 */
1177 ath10k_htt_rx_free_msdu_chain(to_free);
1178 return 0;
1179}
1180
2acc4eb2
JD
1181static bool ath10k_htt_rx_amsdu_allowed(struct ath10k_htt *htt,
1182 struct sk_buff *head,
78433f96
JD
1183 bool channel_set,
1184 u32 attention)
2acc4eb2 1185{
7aa7a72a
MK
1186 struct ath10k *ar = htt->ar;
1187
2acc4eb2 1188 if (head->len == 0) {
7aa7a72a 1189 ath10k_dbg(ar, ATH10K_DBG_HTT,
2acc4eb2
JD
1190 "htt rx dropping due to zero-len\n");
1191 return false;
1192 }
1193
78433f96 1194 if (attention & RX_ATTENTION_FLAGS_DECRYPT_ERR) {
7aa7a72a 1195 ath10k_dbg(ar, ATH10K_DBG_HTT,
2acc4eb2
JD
1196 "htt rx dropping due to decrypt-err\n");
1197 return false;
1198 }
1199
36653f05 1200 if (!channel_set) {
7aa7a72a 1201 ath10k_warn(ar, "no channel configured; ignoring frame!\n");
36653f05
JD
1202 return false;
1203 }
1204
2acc4eb2 1205 /* Skip mgmt frames while we handle this in WMI */
f6b946ef 1206 if (attention & RX_ATTENTION_FLAGS_MGMT_TYPE) {
7aa7a72a 1207 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt rx mgmt ctrl\n");
2acc4eb2
JD
1208 return false;
1209 }
1210
2acc4eb2 1211 if (test_bit(ATH10K_CAC_RUNNING, &htt->ar->dev_flags)) {
7aa7a72a 1212 ath10k_dbg(ar, ATH10K_DBG_HTT,
2acc4eb2
JD
1213 "htt rx CAC running\n");
1214 return false;
1215 }
1216
1217 return true;
1218}
1219
5e3dd157
KV
1220static void ath10k_htt_rx_handler(struct ath10k_htt *htt,
1221 struct htt_rx_indication *rx)
1222{
7aa7a72a 1223 struct ath10k *ar = htt->ar;
6df92a3d 1224 struct ieee80211_rx_status *rx_status = &htt->rx_status;
5e3dd157
KV
1225 struct htt_rx_indication_mpdu_range *mpdu_ranges;
1226 struct ieee80211_hdr *hdr;
1227 int num_mpdu_ranges;
78433f96 1228 u32 attention;
5e3dd157
KV
1229 int fw_desc_len;
1230 u8 *fw_desc;
78433f96 1231 bool channel_set;
5e3dd157 1232 int i, j;
d84dd60f 1233 int ret;
5e3dd157 1234
45967089
MK
1235 lockdep_assert_held(&htt->rx_ring.lock);
1236
5e3dd157
KV
1237 fw_desc_len = __le16_to_cpu(rx->prefix.fw_rx_desc_bytes);
1238 fw_desc = (u8 *)&rx->fw_desc;
1239
1240 num_mpdu_ranges = MS(__le32_to_cpu(rx->hdr.info1),
1241 HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES);
1242 mpdu_ranges = htt_rx_ind_get_mpdu_ranges(rx);
1243
e8dc1a96 1244 /* Fill this once, while this is per-ppdu */
2289188c
JD
1245 if (rx->ppdu.info0 & HTT_RX_INDICATION_INFO0_START_VALID) {
1246 memset(rx_status, 0, sizeof(*rx_status));
1247 rx_status->signal = ATH10K_DEFAULT_NOISE_FLOOR +
1248 rx->ppdu.combined_rssi;
1249 }
87326c97
JD
1250
1251 if (rx->ppdu.info0 & HTT_RX_INDICATION_INFO0_END_VALID) {
1252 /* TSF available only in 32-bit */
6df92a3d
JD
1253 rx_status->mactime = __le32_to_cpu(rx->ppdu.tsf) & 0xffffffff;
1254 rx_status->flag |= RX_FLAG_MACTIME_END;
87326c97 1255 }
e8dc1a96 1256
6df92a3d 1257 channel_set = ath10k_htt_rx_h_channel(htt->ar, rx_status);
36653f05 1258
87326c97 1259 if (channel_set) {
6df92a3d 1260 ath10k_htt_rx_h_rates(htt->ar, rx_status->band,
87326c97
JD
1261 rx->ppdu.info0,
1262 __le32_to_cpu(rx->ppdu.info1),
1263 __le32_to_cpu(rx->ppdu.info2),
6df92a3d 1264 rx_status);
87326c97 1265 }
e8dc1a96 1266
7aa7a72a 1267 ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt rx ind: ",
5e3dd157
KV
1268 rx, sizeof(*rx) +
1269 (sizeof(struct htt_rx_indication_mpdu_range) *
1270 num_mpdu_ranges));
1271
1272 for (i = 0; i < num_mpdu_ranges; i++) {
5e3dd157
KV
1273 for (j = 0; j < mpdu_ranges[i].mpdu_count; j++) {
1274 struct sk_buff *msdu_head, *msdu_tail;
5e3dd157 1275
0ccb7a34 1276 attention = 0;
5e3dd157
KV
1277 msdu_head = NULL;
1278 msdu_tail = NULL;
d84dd60f
JD
1279 ret = ath10k_htt_rx_amsdu_pop(htt,
1280 &fw_desc,
1281 &fw_desc_len,
1282 &msdu_head,
0ccb7a34
JD
1283 &msdu_tail,
1284 &attention);
d84dd60f
JD
1285
1286 if (ret < 0) {
7aa7a72a 1287 ath10k_warn(ar, "failed to pop amsdu from htt rx ring %d\n",
d84dd60f
JD
1288 ret);
1289 ath10k_htt_rx_free_msdu_chain(msdu_head);
1290 continue;
1291 }
5e3dd157 1292
2acc4eb2 1293 if (!ath10k_htt_rx_amsdu_allowed(htt, msdu_head,
78433f96
JD
1294 channel_set,
1295 attention)) {
e8a50f8b
MP
1296 ath10k_htt_rx_free_msdu_chain(msdu_head);
1297 continue;
1298 }
1299
d84dd60f
JD
1300 if (ret > 0 &&
1301 ath10k_unchain_msdu(msdu_head) < 0) {
5e3dd157
KV
1302 ath10k_htt_rx_free_msdu_chain(msdu_head);
1303 continue;
1304 }
1305
78433f96 1306 if (attention & RX_ATTENTION_FLAGS_FCS_ERR)
6df92a3d 1307 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
87326c97 1308 else
6df92a3d 1309 rx_status->flag &= ~RX_FLAG_FAILED_FCS_CRC;
87326c97 1310
78433f96 1311 if (attention & RX_ATTENTION_FLAGS_TKIP_MIC_ERR)
6df92a3d 1312 rx_status->flag |= RX_FLAG_MMIC_ERROR;
87326c97 1313 else
6df92a3d 1314 rx_status->flag &= ~RX_FLAG_MMIC_ERROR;
87326c97 1315
5e3dd157
KV
1316 hdr = ath10k_htt_rx_skb_get_hdr(msdu_head);
1317
1318 if (ath10k_htt_rx_hdr_is_amsdu(hdr))
6df92a3d 1319 ath10k_htt_rx_amsdu(htt, rx_status, msdu_head);
5e3dd157 1320 else
6df92a3d 1321 ath10k_htt_rx_msdu(htt, rx_status, msdu_head);
5e3dd157
KV
1322 }
1323 }
1324
6e712d42 1325 tasklet_schedule(&htt->rx_replenish_task);
5e3dd157
KV
1326}
1327
1328static void ath10k_htt_rx_frag_handler(struct ath10k_htt *htt,
5b07e07f 1329 struct htt_rx_fragment_indication *frag)
5e3dd157 1330{
7aa7a72a 1331 struct ath10k *ar = htt->ar;
5e3dd157 1332 struct sk_buff *msdu_head, *msdu_tail;
87326c97 1333 enum htt_rx_mpdu_encrypt_type enctype;
5e3dd157
KV
1334 struct htt_rx_desc *rxd;
1335 enum rx_msdu_decap_format fmt;
6df92a3d 1336 struct ieee80211_rx_status *rx_status = &htt->rx_status;
5e3dd157 1337 struct ieee80211_hdr *hdr;
d84dd60f 1338 int ret;
5e3dd157
KV
1339 bool tkip_mic_err;
1340 bool decrypt_err;
1341 u8 *fw_desc;
1342 int fw_desc_len, hdrlen, paramlen;
1343 int trim;
0ccb7a34 1344 u32 attention = 0;
5e3dd157
KV
1345
1346 fw_desc_len = __le16_to_cpu(frag->fw_rx_desc_bytes);
1347 fw_desc = (u8 *)frag->fw_msdu_rx_desc;
1348
1349 msdu_head = NULL;
1350 msdu_tail = NULL;
45967089
MK
1351
1352 spin_lock_bh(&htt->rx_ring.lock);
d84dd60f 1353 ret = ath10k_htt_rx_amsdu_pop(htt, &fw_desc, &fw_desc_len,
0ccb7a34
JD
1354 &msdu_head, &msdu_tail,
1355 &attention);
45967089 1356 spin_unlock_bh(&htt->rx_ring.lock);
5e3dd157 1357
686687c9
MK
1358 tasklet_schedule(&htt->rx_replenish_task);
1359
7aa7a72a 1360 ath10k_dbg(ar, ATH10K_DBG_HTT_DUMP, "htt rx frag ahead\n");
5e3dd157 1361
d84dd60f 1362 if (ret) {
7aa7a72a 1363 ath10k_warn(ar, "failed to pop amsdu from httr rx ring for fragmented rx %d\n",
d84dd60f 1364 ret);
5e3dd157
KV
1365 ath10k_htt_rx_free_msdu_chain(msdu_head);
1366 return;
1367 }
1368
1369 /* FIXME: implement signal strength */
4b81d177 1370 rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL;
5e3dd157
KV
1371
1372 hdr = (struct ieee80211_hdr *)msdu_head->data;
1373 rxd = (void *)msdu_head->data - sizeof(*rxd);
0ccb7a34
JD
1374 tkip_mic_err = !!(attention & RX_ATTENTION_FLAGS_TKIP_MIC_ERR);
1375 decrypt_err = !!(attention & RX_ATTENTION_FLAGS_DECRYPT_ERR);
5e3dd157 1376 fmt = MS(__le32_to_cpu(rxd->msdu_start.info1),
5b07e07f 1377 RX_MSDU_START_INFO1_DECAP_FORMAT);
5e3dd157
KV
1378
1379 if (fmt != RX_MSDU_DECAP_RAW) {
7aa7a72a 1380 ath10k_warn(ar, "we dont support non-raw fragmented rx yet\n");
5e3dd157
KV
1381 dev_kfree_skb_any(msdu_head);
1382 goto end;
1383 }
1384
87326c97
JD
1385 enctype = MS(__le32_to_cpu(rxd->mpdu_start.info0),
1386 RX_MPDU_START_INFO0_ENCRYPT_TYPE);
c071dcb2
MK
1387 ath10k_htt_rx_h_protected(htt, rx_status, msdu_head, enctype, fmt,
1388 true);
85f6d7cf 1389 msdu_head->ip_summed = ath10k_htt_rx_get_csum_state(msdu_head);
5e3dd157 1390
87326c97 1391 if (tkip_mic_err)
7aa7a72a 1392 ath10k_warn(ar, "tkip mic error\n");
5e3dd157
KV
1393
1394 if (decrypt_err) {
7aa7a72a 1395 ath10k_warn(ar, "decryption err in fragmented rx\n");
85f6d7cf 1396 dev_kfree_skb_any(msdu_head);
5e3dd157
KV
1397 goto end;
1398 }
1399
87326c97 1400 if (enctype != HTT_RX_MPDU_ENCRYPT_NONE) {
5e3dd157 1401 hdrlen = ieee80211_hdrlen(hdr->frame_control);
7aa7a72a 1402 paramlen = ath10k_htt_rx_crypto_param_len(ar, enctype);
5e3dd157
KV
1403
1404 /* It is more efficient to move the header than the payload */
85f6d7cf
JD
1405 memmove((void *)msdu_head->data + paramlen,
1406 (void *)msdu_head->data,
5e3dd157 1407 hdrlen);
85f6d7cf
JD
1408 skb_pull(msdu_head, paramlen);
1409 hdr = (struct ieee80211_hdr *)msdu_head->data;
5e3dd157
KV
1410 }
1411
1412 /* remove trailing FCS */
1413 trim = 4;
1414
1415 /* remove crypto trailer */
7aa7a72a 1416 trim += ath10k_htt_rx_crypto_tail_len(ar, enctype);
5e3dd157
KV
1417
1418 /* last fragment of TKIP frags has MIC */
1419 if (!ieee80211_has_morefrags(hdr->frame_control) &&
87326c97 1420 enctype == HTT_RX_MPDU_ENCRYPT_TKIP_WPA)
890d3b2a 1421 trim += MICHAEL_MIC_LEN;
5e3dd157 1422
85f6d7cf 1423 if (trim > msdu_head->len) {
7aa7a72a 1424 ath10k_warn(ar, "htt rx fragment: trailer longer than the frame itself? drop\n");
85f6d7cf 1425 dev_kfree_skb_any(msdu_head);
5e3dd157
KV
1426 goto end;
1427 }
1428
85f6d7cf 1429 skb_trim(msdu_head, msdu_head->len - trim);
5e3dd157 1430
7aa7a72a 1431 ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt rx frag mpdu: ",
85f6d7cf 1432 msdu_head->data, msdu_head->len);
6df92a3d 1433 ath10k_process_rx(htt->ar, rx_status, msdu_head);
5e3dd157
KV
1434
1435end:
1436 if (fw_desc_len > 0) {
7aa7a72a 1437 ath10k_dbg(ar, ATH10K_DBG_HTT,
5e3dd157
KV
1438 "expecting more fragmented rx in one indication %d\n",
1439 fw_desc_len);
1440 }
1441}
1442
6c5151a9
MK
1443static void ath10k_htt_rx_frm_tx_compl(struct ath10k *ar,
1444 struct sk_buff *skb)
1445{
1446 struct ath10k_htt *htt = &ar->htt;
1447 struct htt_resp *resp = (struct htt_resp *)skb->data;
1448 struct htt_tx_done tx_done = {};
1449 int status = MS(resp->data_tx_completion.flags, HTT_DATA_TX_STATUS);
1450 __le16 msdu_id;
1451 int i;
1452
45967089
MK
1453 lockdep_assert_held(&htt->tx_lock);
1454
6c5151a9
MK
1455 switch (status) {
1456 case HTT_DATA_TX_STATUS_NO_ACK:
1457 tx_done.no_ack = true;
1458 break;
1459 case HTT_DATA_TX_STATUS_OK:
1460 break;
1461 case HTT_DATA_TX_STATUS_DISCARD:
1462 case HTT_DATA_TX_STATUS_POSTPONE:
1463 case HTT_DATA_TX_STATUS_DOWNLOAD_FAIL:
1464 tx_done.discard = true;
1465 break;
1466 default:
7aa7a72a 1467 ath10k_warn(ar, "unhandled tx completion status %d\n", status);
6c5151a9
MK
1468 tx_done.discard = true;
1469 break;
1470 }
1471
7aa7a72a 1472 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx completion num_msdus %d\n",
6c5151a9
MK
1473 resp->data_tx_completion.num_msdus);
1474
1475 for (i = 0; i < resp->data_tx_completion.num_msdus; i++) {
1476 msdu_id = resp->data_tx_completion.msdus[i];
1477 tx_done.msdu_id = __le16_to_cpu(msdu_id);
1478 ath10k_txrx_tx_unref(htt, &tx_done);
1479 }
1480}
1481
aa5b4fbc
MK
1482static void ath10k_htt_rx_addba(struct ath10k *ar, struct htt_resp *resp)
1483{
1484 struct htt_rx_addba *ev = &resp->rx_addba;
1485 struct ath10k_peer *peer;
1486 struct ath10k_vif *arvif;
1487 u16 info0, tid, peer_id;
1488
1489 info0 = __le16_to_cpu(ev->info0);
1490 tid = MS(info0, HTT_RX_BA_INFO0_TID);
1491 peer_id = MS(info0, HTT_RX_BA_INFO0_PEER_ID);
1492
7aa7a72a 1493 ath10k_dbg(ar, ATH10K_DBG_HTT,
aa5b4fbc
MK
1494 "htt rx addba tid %hu peer_id %hu size %hhu\n",
1495 tid, peer_id, ev->window_size);
1496
1497 spin_lock_bh(&ar->data_lock);
1498 peer = ath10k_peer_find_by_id(ar, peer_id);
1499 if (!peer) {
7aa7a72a 1500 ath10k_warn(ar, "received addba event for invalid peer_id: %hu\n",
aa5b4fbc
MK
1501 peer_id);
1502 spin_unlock_bh(&ar->data_lock);
1503 return;
1504 }
1505
1506 arvif = ath10k_get_arvif(ar, peer->vdev_id);
1507 if (!arvif) {
7aa7a72a 1508 ath10k_warn(ar, "received addba event for invalid vdev_id: %u\n",
aa5b4fbc
MK
1509 peer->vdev_id);
1510 spin_unlock_bh(&ar->data_lock);
1511 return;
1512 }
1513
7aa7a72a 1514 ath10k_dbg(ar, ATH10K_DBG_HTT,
aa5b4fbc
MK
1515 "htt rx start rx ba session sta %pM tid %hu size %hhu\n",
1516 peer->addr, tid, ev->window_size);
1517
1518 ieee80211_start_rx_ba_session_offl(arvif->vif, peer->addr, tid);
1519 spin_unlock_bh(&ar->data_lock);
1520}
1521
1522static void ath10k_htt_rx_delba(struct ath10k *ar, struct htt_resp *resp)
1523{
1524 struct htt_rx_delba *ev = &resp->rx_delba;
1525 struct ath10k_peer *peer;
1526 struct ath10k_vif *arvif;
1527 u16 info0, tid, peer_id;
1528
1529 info0 = __le16_to_cpu(ev->info0);
1530 tid = MS(info0, HTT_RX_BA_INFO0_TID);
1531 peer_id = MS(info0, HTT_RX_BA_INFO0_PEER_ID);
1532
7aa7a72a 1533 ath10k_dbg(ar, ATH10K_DBG_HTT,
aa5b4fbc
MK
1534 "htt rx delba tid %hu peer_id %hu\n",
1535 tid, peer_id);
1536
1537 spin_lock_bh(&ar->data_lock);
1538 peer = ath10k_peer_find_by_id(ar, peer_id);
1539 if (!peer) {
7aa7a72a 1540 ath10k_warn(ar, "received addba event for invalid peer_id: %hu\n",
aa5b4fbc
MK
1541 peer_id);
1542 spin_unlock_bh(&ar->data_lock);
1543 return;
1544 }
1545
1546 arvif = ath10k_get_arvif(ar, peer->vdev_id);
1547 if (!arvif) {
7aa7a72a 1548 ath10k_warn(ar, "received addba event for invalid vdev_id: %u\n",
aa5b4fbc
MK
1549 peer->vdev_id);
1550 spin_unlock_bh(&ar->data_lock);
1551 return;
1552 }
1553
7aa7a72a 1554 ath10k_dbg(ar, ATH10K_DBG_HTT,
aa5b4fbc
MK
1555 "htt rx stop rx ba session sta %pM tid %hu\n",
1556 peer->addr, tid);
1557
1558 ieee80211_stop_rx_ba_session_offl(arvif->vif, peer->addr, tid);
1559 spin_unlock_bh(&ar->data_lock);
1560}
1561
5e3dd157
KV
1562void ath10k_htt_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb)
1563{
edb8236d 1564 struct ath10k_htt *htt = &ar->htt;
5e3dd157
KV
1565 struct htt_resp *resp = (struct htt_resp *)skb->data;
1566
1567 /* confirm alignment */
1568 if (!IS_ALIGNED((unsigned long)skb->data, 4))
7aa7a72a 1569 ath10k_warn(ar, "unaligned htt message, expect trouble\n");
5e3dd157 1570
7aa7a72a 1571 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt rx, msg_type: 0x%0X\n",
5e3dd157
KV
1572 resp->hdr.msg_type);
1573 switch (resp->hdr.msg_type) {
1574 case HTT_T2H_MSG_TYPE_VERSION_CONF: {
1575 htt->target_version_major = resp->ver_resp.major;
1576 htt->target_version_minor = resp->ver_resp.minor;
1577 complete(&htt->target_version_received);
1578 break;
1579 }
6c5151a9 1580 case HTT_T2H_MSG_TYPE_RX_IND:
45967089
MK
1581 spin_lock_bh(&htt->rx_ring.lock);
1582 __skb_queue_tail(&htt->rx_compl_q, skb);
1583 spin_unlock_bh(&htt->rx_ring.lock);
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MK
1584 tasklet_schedule(&htt->txrx_compl_task);
1585 return;
5e3dd157
KV
1586 case HTT_T2H_MSG_TYPE_PEER_MAP: {
1587 struct htt_peer_map_event ev = {
1588 .vdev_id = resp->peer_map.vdev_id,
1589 .peer_id = __le16_to_cpu(resp->peer_map.peer_id),
1590 };
1591 memcpy(ev.addr, resp->peer_map.addr, sizeof(ev.addr));
1592 ath10k_peer_map_event(htt, &ev);
1593 break;
1594 }
1595 case HTT_T2H_MSG_TYPE_PEER_UNMAP: {
1596 struct htt_peer_unmap_event ev = {
1597 .peer_id = __le16_to_cpu(resp->peer_unmap.peer_id),
1598 };
1599 ath10k_peer_unmap_event(htt, &ev);
1600 break;
1601 }
1602 case HTT_T2H_MSG_TYPE_MGMT_TX_COMPLETION: {
1603 struct htt_tx_done tx_done = {};
1604 int status = __le32_to_cpu(resp->mgmt_tx_completion.status);
1605
1606 tx_done.msdu_id =
1607 __le32_to_cpu(resp->mgmt_tx_completion.desc_id);
1608
1609 switch (status) {
1610 case HTT_MGMT_TX_STATUS_OK:
1611 break;
1612 case HTT_MGMT_TX_STATUS_RETRY:
1613 tx_done.no_ack = true;
1614 break;
1615 case HTT_MGMT_TX_STATUS_DROP:
1616 tx_done.discard = true;
1617 break;
1618 }
1619
6c5151a9 1620 spin_lock_bh(&htt->tx_lock);
0a89f8a0 1621 ath10k_txrx_tx_unref(htt, &tx_done);
6c5151a9 1622 spin_unlock_bh(&htt->tx_lock);
5e3dd157
KV
1623 break;
1624 }
6c5151a9
MK
1625 case HTT_T2H_MSG_TYPE_TX_COMPL_IND:
1626 spin_lock_bh(&htt->tx_lock);
1627 __skb_queue_tail(&htt->tx_compl_q, skb);
1628 spin_unlock_bh(&htt->tx_lock);
1629 tasklet_schedule(&htt->txrx_compl_task);
1630 return;
5e3dd157
KV
1631 case HTT_T2H_MSG_TYPE_SEC_IND: {
1632 struct ath10k *ar = htt->ar;
1633 struct htt_security_indication *ev = &resp->security_indication;
1634
7aa7a72a 1635 ath10k_dbg(ar, ATH10K_DBG_HTT,
5e3dd157
KV
1636 "sec ind peer_id %d unicast %d type %d\n",
1637 __le16_to_cpu(ev->peer_id),
1638 !!(ev->flags & HTT_SECURITY_IS_UNICAST),
1639 MS(ev->flags, HTT_SECURITY_TYPE));
1640 complete(&ar->install_key_done);
1641 break;
1642 }
1643 case HTT_T2H_MSG_TYPE_RX_FRAG_IND: {
7aa7a72a 1644 ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt event: ",
5e3dd157
KV
1645 skb->data, skb->len);
1646 ath10k_htt_rx_frag_handler(htt, &resp->rx_frag_ind);
1647 break;
1648 }
1649 case HTT_T2H_MSG_TYPE_TEST:
1650 /* FIX THIS */
1651 break;
5e3dd157 1652 case HTT_T2H_MSG_TYPE_STATS_CONF:
d35a6c18 1653 trace_ath10k_htt_stats(ar, skb->data, skb->len);
a9bf0506
KV
1654 break;
1655 case HTT_T2H_MSG_TYPE_TX_INSPECT_IND:
708b9bde
MK
1656 /* Firmware can return tx frames if it's unable to fully
1657 * process them and suspects host may be able to fix it. ath10k
1658 * sends all tx frames as already inspected so this shouldn't
1659 * happen unless fw has a bug.
1660 */
7aa7a72a 1661 ath10k_warn(ar, "received an unexpected htt tx inspect event\n");
708b9bde 1662 break;
5e3dd157 1663 case HTT_T2H_MSG_TYPE_RX_ADDBA:
aa5b4fbc
MK
1664 ath10k_htt_rx_addba(ar, resp);
1665 break;
5e3dd157 1666 case HTT_T2H_MSG_TYPE_RX_DELBA:
aa5b4fbc
MK
1667 ath10k_htt_rx_delba(ar, resp);
1668 break;
bfdd7937
RM
1669 case HTT_T2H_MSG_TYPE_PKTLOG: {
1670 struct ath10k_pktlog_hdr *hdr =
1671 (struct ath10k_pktlog_hdr *)resp->pktlog_msg.payload;
1672
1673 trace_ath10k_htt_pktlog(ar, resp->pktlog_msg.payload,
1674 sizeof(*hdr) +
1675 __le16_to_cpu(hdr->size));
1676 break;
1677 }
aa5b4fbc
MK
1678 case HTT_T2H_MSG_TYPE_RX_FLUSH: {
1679 /* Ignore this event because mac80211 takes care of Rx
1680 * aggregation reordering.
1681 */
1682 break;
1683 }
5e3dd157 1684 default:
2358a544
MK
1685 ath10k_warn(ar, "htt event (%d) not handled\n",
1686 resp->hdr.msg_type);
7aa7a72a 1687 ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt event: ",
5e3dd157
KV
1688 skb->data, skb->len);
1689 break;
1690 };
1691
1692 /* Free the indication buffer */
1693 dev_kfree_skb_any(skb);
1694}
6c5151a9
MK
1695
1696static void ath10k_htt_txrx_compl_task(unsigned long ptr)
1697{
1698 struct ath10k_htt *htt = (struct ath10k_htt *)ptr;
1699 struct htt_resp *resp;
1700 struct sk_buff *skb;
1701
45967089
MK
1702 spin_lock_bh(&htt->tx_lock);
1703 while ((skb = __skb_dequeue(&htt->tx_compl_q))) {
6c5151a9
MK
1704 ath10k_htt_rx_frm_tx_compl(htt->ar, skb);
1705 dev_kfree_skb_any(skb);
1706 }
45967089 1707 spin_unlock_bh(&htt->tx_lock);
6c5151a9 1708
45967089
MK
1709 spin_lock_bh(&htt->rx_ring.lock);
1710 while ((skb = __skb_dequeue(&htt->rx_compl_q))) {
6c5151a9
MK
1711 resp = (struct htt_resp *)skb->data;
1712 ath10k_htt_rx_handler(htt, &resp->rx_ind);
1713 dev_kfree_skb_any(skb);
1714 }
45967089 1715 spin_unlock_bh(&htt->rx_ring.lock);
6c5151a9 1716}