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ath10k: simplify Rx loop
[mirror_ubuntu-zesty-kernel.git] / drivers / net / wireless / ath / ath10k / htt_rx.c
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1/*
2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
edb8236d 18#include "core.h"
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19#include "htc.h"
20#include "htt.h"
21#include "txrx.h"
22#include "debug.h"
a9bf0506 23#include "trace.h"
aa5b4fbc 24#include "mac.h"
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25
26#include <linux/log2.h>
27
28/* slightly larger than one large A-MPDU */
29#define HTT_RX_RING_SIZE_MIN 128
30
31/* roughly 20 ms @ 1 Gbps of 1500B MSDUs */
32#define HTT_RX_RING_SIZE_MAX 2048
33
34#define HTT_RX_AVG_FRM_BYTES 1000
35
36/* ms, very conservative */
37#define HTT_RX_HOST_LATENCY_MAX_MS 20
38
39/* ms, conservative */
40#define HTT_RX_HOST_LATENCY_WORST_LIKELY_MS 10
41
42/* when under memory pressure rx ring refill may fail and needs a retry */
43#define HTT_RX_RING_REFILL_RETRY_MS 50
44
f6dc2095 45static int ath10k_htt_rx_get_csum_state(struct sk_buff *skb);
6c5151a9 46static void ath10k_htt_txrx_compl_task(unsigned long ptr);
f6dc2095 47
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48static int ath10k_htt_rx_ring_size(struct ath10k_htt *htt)
49{
50 int size;
51
52 /*
53 * It is expected that the host CPU will typically be able to
54 * service the rx indication from one A-MPDU before the rx
55 * indication from the subsequent A-MPDU happens, roughly 1-2 ms
56 * later. However, the rx ring should be sized very conservatively,
57 * to accomodate the worst reasonable delay before the host CPU
58 * services a rx indication interrupt.
59 *
60 * The rx ring need not be kept full of empty buffers. In theory,
61 * the htt host SW can dynamically track the low-water mark in the
62 * rx ring, and dynamically adjust the level to which the rx ring
63 * is filled with empty buffers, to dynamically meet the desired
64 * low-water mark.
65 *
66 * In contrast, it's difficult to resize the rx ring itself, once
67 * it's in use. Thus, the ring itself should be sized very
68 * conservatively, while the degree to which the ring is filled
69 * with empty buffers should be sized moderately conservatively.
70 */
71
72 /* 1e6 bps/mbps / 1e3 ms per sec = 1000 */
73 size =
74 htt->max_throughput_mbps +
75 1000 /
76 (8 * HTT_RX_AVG_FRM_BYTES) * HTT_RX_HOST_LATENCY_MAX_MS;
77
78 if (size < HTT_RX_RING_SIZE_MIN)
79 size = HTT_RX_RING_SIZE_MIN;
80
81 if (size > HTT_RX_RING_SIZE_MAX)
82 size = HTT_RX_RING_SIZE_MAX;
83
84 size = roundup_pow_of_two(size);
85
86 return size;
87}
88
89static int ath10k_htt_rx_ring_fill_level(struct ath10k_htt *htt)
90{
91 int size;
92
93 /* 1e6 bps/mbps / 1e3 ms per sec = 1000 */
94 size =
95 htt->max_throughput_mbps *
96 1000 /
97 (8 * HTT_RX_AVG_FRM_BYTES) * HTT_RX_HOST_LATENCY_WORST_LIKELY_MS;
98
99 /*
100 * Make sure the fill level is at least 1 less than the ring size.
101 * Leaving 1 element empty allows the SW to easily distinguish
102 * between a full ring vs. an empty ring.
103 */
104 if (size >= htt->rx_ring.size)
105 size = htt->rx_ring.size - 1;
106
107 return size;
108}
109
110static void ath10k_htt_rx_ring_free(struct ath10k_htt *htt)
111{
112 struct sk_buff *skb;
113 struct ath10k_skb_cb *cb;
114 int i;
115
116 for (i = 0; i < htt->rx_ring.fill_cnt; i++) {
117 skb = htt->rx_ring.netbufs_ring[i];
118 cb = ATH10K_SKB_CB(skb);
119 dma_unmap_single(htt->ar->dev, cb->paddr,
120 skb->len + skb_tailroom(skb),
121 DMA_FROM_DEVICE);
122 dev_kfree_skb_any(skb);
123 }
124
125 htt->rx_ring.fill_cnt = 0;
126}
127
128static int __ath10k_htt_rx_ring_fill_n(struct ath10k_htt *htt, int num)
129{
130 struct htt_rx_desc *rx_desc;
131 struct sk_buff *skb;
132 dma_addr_t paddr;
133 int ret = 0, idx;
134
8cc7f26c 135 idx = __le32_to_cpu(*htt->rx_ring.alloc_idx.vaddr);
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136 while (num > 0) {
137 skb = dev_alloc_skb(HTT_RX_BUF_SIZE + HTT_RX_DESC_ALIGN);
138 if (!skb) {
139 ret = -ENOMEM;
140 goto fail;
141 }
142
143 if (!IS_ALIGNED((unsigned long)skb->data, HTT_RX_DESC_ALIGN))
144 skb_pull(skb,
145 PTR_ALIGN(skb->data, HTT_RX_DESC_ALIGN) -
146 skb->data);
147
148 /* Clear rx_desc attention word before posting to Rx ring */
149 rx_desc = (struct htt_rx_desc *)skb->data;
150 rx_desc->attention.flags = __cpu_to_le32(0);
151
152 paddr = dma_map_single(htt->ar->dev, skb->data,
153 skb->len + skb_tailroom(skb),
154 DMA_FROM_DEVICE);
155
156 if (unlikely(dma_mapping_error(htt->ar->dev, paddr))) {
157 dev_kfree_skb_any(skb);
158 ret = -ENOMEM;
159 goto fail;
160 }
161
162 ATH10K_SKB_CB(skb)->paddr = paddr;
163 htt->rx_ring.netbufs_ring[idx] = skb;
164 htt->rx_ring.paddrs_ring[idx] = __cpu_to_le32(paddr);
165 htt->rx_ring.fill_cnt++;
166
167 num--;
168 idx++;
169 idx &= htt->rx_ring.size_mask;
170 }
171
172fail:
8cc7f26c 173 *htt->rx_ring.alloc_idx.vaddr = __cpu_to_le32(idx);
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174 return ret;
175}
176
177static int ath10k_htt_rx_ring_fill_n(struct ath10k_htt *htt, int num)
178{
179 lockdep_assert_held(&htt->rx_ring.lock);
180 return __ath10k_htt_rx_ring_fill_n(htt, num);
181}
182
183static void ath10k_htt_rx_msdu_buff_replenish(struct ath10k_htt *htt)
184{
6e712d42 185 int ret, num_deficit, num_to_fill;
5e3dd157 186
6e712d42
MK
187 /* Refilling the whole RX ring buffer proves to be a bad idea. The
188 * reason is RX may take up significant amount of CPU cycles and starve
189 * other tasks, e.g. TX on an ethernet device while acting as a bridge
190 * with ath10k wlan interface. This ended up with very poor performance
191 * once CPU the host system was overwhelmed with RX on ath10k.
192 *
193 * By limiting the number of refills the replenishing occurs
194 * progressively. This in turns makes use of the fact tasklets are
195 * processed in FIFO order. This means actual RX processing can starve
196 * out refilling. If there's not enough buffers on RX ring FW will not
197 * report RX until it is refilled with enough buffers. This
198 * automatically balances load wrt to CPU power.
199 *
200 * This probably comes at a cost of lower maximum throughput but
201 * improves the avarage and stability. */
5e3dd157 202 spin_lock_bh(&htt->rx_ring.lock);
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203 num_deficit = htt->rx_ring.fill_level - htt->rx_ring.fill_cnt;
204 num_to_fill = min(ATH10K_HTT_MAX_NUM_REFILL, num_deficit);
205 num_deficit -= num_to_fill;
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206 ret = ath10k_htt_rx_ring_fill_n(htt, num_to_fill);
207 if (ret == -ENOMEM) {
208 /*
209 * Failed to fill it to the desired level -
210 * we'll start a timer and try again next time.
211 * As long as enough buffers are left in the ring for
212 * another A-MPDU rx, no special recovery is needed.
213 */
214 mod_timer(&htt->rx_ring.refill_retry_timer, jiffies +
215 msecs_to_jiffies(HTT_RX_RING_REFILL_RETRY_MS));
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216 } else if (num_deficit > 0) {
217 tasklet_schedule(&htt->rx_replenish_task);
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218 }
219 spin_unlock_bh(&htt->rx_ring.lock);
220}
221
222static void ath10k_htt_rx_ring_refill_retry(unsigned long arg)
223{
224 struct ath10k_htt *htt = (struct ath10k_htt *)arg;
af762c0b 225
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226 ath10k_htt_rx_msdu_buff_replenish(htt);
227}
228
3e841fd0 229static void ath10k_htt_rx_ring_clean_up(struct ath10k_htt *htt)
5e3dd157 230{
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231 struct sk_buff *skb;
232 int i;
233
234 for (i = 0; i < htt->rx_ring.size; i++) {
235 skb = htt->rx_ring.netbufs_ring[i];
236 if (!skb)
237 continue;
238
239 dma_unmap_single(htt->ar->dev, ATH10K_SKB_CB(skb)->paddr,
240 skb->len + skb_tailroom(skb),
241 DMA_FROM_DEVICE);
242 dev_kfree_skb_any(skb);
243 htt->rx_ring.netbufs_ring[i] = NULL;
244 }
245}
5e3dd157 246
95bf21f9 247void ath10k_htt_rx_free(struct ath10k_htt *htt)
3e841fd0 248{
5e3dd157 249 del_timer_sync(&htt->rx_ring.refill_retry_timer);
6e712d42 250 tasklet_kill(&htt->rx_replenish_task);
6c5151a9
MK
251 tasklet_kill(&htt->txrx_compl_task);
252
253 skb_queue_purge(&htt->tx_compl_q);
254 skb_queue_purge(&htt->rx_compl_q);
5e3dd157 255
3e841fd0 256 ath10k_htt_rx_ring_clean_up(htt);
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257
258 dma_free_coherent(htt->ar->dev,
259 (htt->rx_ring.size *
260 sizeof(htt->rx_ring.paddrs_ring)),
261 htt->rx_ring.paddrs_ring,
262 htt->rx_ring.base_paddr);
263
264 dma_free_coherent(htt->ar->dev,
265 sizeof(*htt->rx_ring.alloc_idx.vaddr),
266 htt->rx_ring.alloc_idx.vaddr,
267 htt->rx_ring.alloc_idx.paddr);
268
269 kfree(htt->rx_ring.netbufs_ring);
270}
271
272static inline struct sk_buff *ath10k_htt_rx_netbuf_pop(struct ath10k_htt *htt)
273{
7aa7a72a 274 struct ath10k *ar = htt->ar;
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275 int idx;
276 struct sk_buff *msdu;
277
45967089 278 lockdep_assert_held(&htt->rx_ring.lock);
5e3dd157 279
8d60ee87 280 if (htt->rx_ring.fill_cnt == 0) {
7aa7a72a 281 ath10k_warn(ar, "tried to pop sk_buff from an empty rx ring\n");
8d60ee87
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282 return NULL;
283 }
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284
285 idx = htt->rx_ring.sw_rd_idx.msdu_payld;
286 msdu = htt->rx_ring.netbufs_ring[idx];
3e841fd0 287 htt->rx_ring.netbufs_ring[idx] = NULL;
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288
289 idx++;
290 idx &= htt->rx_ring.size_mask;
291 htt->rx_ring.sw_rd_idx.msdu_payld = idx;
292 htt->rx_ring.fill_cnt--;
293
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MK
294 dma_unmap_single(htt->ar->dev,
295 ATH10K_SKB_CB(msdu)->paddr,
296 msdu->len + skb_tailroom(msdu),
297 DMA_FROM_DEVICE);
298 ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt rx netbuf pop: ",
299 msdu->data, msdu->len + skb_tailroom(msdu));
4de02806 300
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301 return msdu;
302}
303
d84dd60f 304/* return: < 0 fatal error, 0 - non chained msdu, 1 chained msdu */
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305static int ath10k_htt_rx_amsdu_pop(struct ath10k_htt *htt,
306 u8 **fw_desc, int *fw_desc_len,
9aa505d2 307 struct sk_buff_head *amsdu,
0ccb7a34 308 u32 *attention)
5e3dd157 309{
7aa7a72a 310 struct ath10k *ar = htt->ar;
5e3dd157 311 int msdu_len, msdu_chaining = 0;
9aa505d2 312 struct sk_buff *msdu;
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313 struct htt_rx_desc *rx_desc;
314
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MK
315 lockdep_assert_held(&htt->rx_ring.lock);
316
5e3dd157 317 if (htt->rx_confused) {
7aa7a72a 318 ath10k_warn(ar, "htt is confused. refusing rx\n");
d84dd60f 319 return -1;
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320 }
321
9aa505d2 322 for (;;) {
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323 int last_msdu, msdu_len_invalid, msdu_chained;
324
9aa505d2
MK
325 msdu = ath10k_htt_rx_netbuf_pop(htt);
326 if (!msdu) {
327 ath10k_err(ar, "failed to pop msdu\n");
328 __skb_queue_purge(amsdu);
329 htt->rx_confused = true;
330 break;
331 }
332
333 __skb_queue_tail(amsdu, msdu);
334
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335 rx_desc = (struct htt_rx_desc *)msdu->data;
336
337 /* FIXME: we must report msdu payload since this is what caller
338 * expects now */
339 skb_put(msdu, offsetof(struct htt_rx_desc, msdu_payload));
340 skb_pull(msdu, offsetof(struct htt_rx_desc, msdu_payload));
341
342 /*
343 * Sanity check - confirm the HW is finished filling in the
344 * rx data.
345 * If the HW and SW are working correctly, then it's guaranteed
346 * that the HW's MAC DMA is done before this point in the SW.
347 * To prevent the case that we handle a stale Rx descriptor,
348 * just assert for now until we have a way to recover.
349 */
350 if (!(__le32_to_cpu(rx_desc->attention.flags)
351 & RX_ATTENTION_FLAGS_MSDU_DONE)) {
9aa505d2
MK
352 ath10k_err(ar, "popped an incomplete msdu\n");
353 __skb_queue_purge(amsdu);
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354 htt->rx_confused = true;
355 break;
356 }
357
0ccb7a34
JD
358 *attention |= __le32_to_cpu(rx_desc->attention.flags) &
359 (RX_ATTENTION_FLAGS_TKIP_MIC_ERR |
360 RX_ATTENTION_FLAGS_DECRYPT_ERR |
361 RX_ATTENTION_FLAGS_FCS_ERR |
362 RX_ATTENTION_FLAGS_MGMT_TYPE);
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363 /*
364 * Copy the FW rx descriptor for this MSDU from the rx
365 * indication message into the MSDU's netbuf. HL uses the
366 * same rx indication message definition as LL, and simply
367 * appends new info (fields from the HW rx desc, and the
368 * MSDU payload itself). So, the offset into the rx
369 * indication message only has to account for the standard
370 * offset of the per-MSDU FW rx desc info within the
371 * message, and how many bytes of the per-MSDU FW rx desc
372 * info have already been consumed. (And the endianness of
373 * the host, since for a big-endian host, the rx ind
374 * message contents, including the per-MSDU rx desc bytes,
375 * were byteswapped during upload.)
376 */
377 if (*fw_desc_len > 0) {
378 rx_desc->fw_desc.info0 = **fw_desc;
379 /*
380 * The target is expected to only provide the basic
381 * per-MSDU rx descriptors. Just to be sure, verify
382 * that the target has not attached extension data
383 * (e.g. LRO flow ID).
384 */
385
386 /* or more, if there's extension data */
387 (*fw_desc)++;
388 (*fw_desc_len)--;
389 } else {
390 /*
391 * When an oversized AMSDU happened, FW will lost
392 * some of MSDU status - in this case, the FW
393 * descriptors provided will be less than the
394 * actual MSDUs inside this MPDU. Mark the FW
395 * descriptors so that it will still deliver to
396 * upper stack, if no CRC error for this MPDU.
397 *
398 * FIX THIS - the FW descriptors are actually for
399 * MSDUs in the end of this A-MSDU instead of the
400 * beginning.
401 */
402 rx_desc->fw_desc.info0 = 0;
403 }
404
405 msdu_len_invalid = !!(__le32_to_cpu(rx_desc->attention.flags)
406 & (RX_ATTENTION_FLAGS_MPDU_LENGTH_ERR |
407 RX_ATTENTION_FLAGS_MSDU_LENGTH_ERR));
408 msdu_len = MS(__le32_to_cpu(rx_desc->msdu_start.info0),
409 RX_MSDU_START_INFO0_MSDU_LENGTH);
410 msdu_chained = rx_desc->frag_info.ring2_more_count;
411
412 if (msdu_len_invalid)
413 msdu_len = 0;
414
415 skb_trim(msdu, 0);
416 skb_put(msdu, min(msdu_len, HTT_RX_MSDU_SIZE));
417 msdu_len -= msdu->len;
418
9aa505d2 419 /* Note: Chained buffers do not contain rx descriptor */
5e3dd157 420 while (msdu_chained--) {
9aa505d2
MK
421 msdu = ath10k_htt_rx_netbuf_pop(htt);
422 if (!msdu) {
b30595ae 423 ath10k_warn(ar, "failed to pop chained msdu\n");
9aa505d2 424 __skb_queue_purge(amsdu);
b30595ae
MK
425 htt->rx_confused = true;
426 break;
427 }
428
9aa505d2
MK
429 __skb_queue_tail(amsdu, msdu);
430 skb_trim(msdu, 0);
431 skb_put(msdu, min(msdu_len, HTT_RX_BUF_SIZE));
432 msdu_len -= msdu->len;
ede9c8e0 433 msdu_chaining = 1;
5e3dd157
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434 }
435
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436 last_msdu = __le32_to_cpu(rx_desc->msdu_end.info0) &
437 RX_MSDU_END_INFO0_LAST_MSDU;
438
b04e204f 439 trace_ath10k_htt_rx_desc(ar, &rx_desc->attention,
a0883cf7 440 sizeof(*rx_desc) - sizeof(u32));
d8bb26b9 441
9aa505d2
MK
442 if (last_msdu)
443 break;
5e3dd157 444 }
5e3dd157 445
9aa505d2 446 if (skb_queue_empty(amsdu))
d84dd60f
JD
447 msdu_chaining = -1;
448
5e3dd157
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449 /*
450 * Don't refill the ring yet.
451 *
452 * First, the elements popped here are still in use - it is not
453 * safe to overwrite them until the matching call to
454 * mpdu_desc_list_next. Second, for efficiency it is preferable to
455 * refill the rx ring with 1 PPDU's worth of rx buffers (something
456 * like 32 x 3 buffers), rather than one MPDU's worth of rx buffers
457 * (something like 3 buffers). Consequently, we'll rely on the txrx
458 * SW to tell us when it is done pulling all the PPDU's rx buffers
459 * out of the rx ring, and then refill it just once.
460 */
461
462 return msdu_chaining;
463}
464
6e712d42
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465static void ath10k_htt_rx_replenish_task(unsigned long ptr)
466{
467 struct ath10k_htt *htt = (struct ath10k_htt *)ptr;
af762c0b 468
6e712d42
MK
469 ath10k_htt_rx_msdu_buff_replenish(htt);
470}
471
95bf21f9 472int ath10k_htt_rx_alloc(struct ath10k_htt *htt)
5e3dd157 473{
7aa7a72a 474 struct ath10k *ar = htt->ar;
5e3dd157
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475 dma_addr_t paddr;
476 void *vaddr;
bd8bdbb6 477 size_t size;
5e3dd157
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478 struct timer_list *timer = &htt->rx_ring.refill_retry_timer;
479
51fc7d74
MK
480 htt->rx_confused = false;
481
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482 htt->rx_ring.size = ath10k_htt_rx_ring_size(htt);
483 if (!is_power_of_2(htt->rx_ring.size)) {
7aa7a72a 484 ath10k_warn(ar, "htt rx ring size is not power of 2\n");
5e3dd157
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485 return -EINVAL;
486 }
487
488 htt->rx_ring.size_mask = htt->rx_ring.size - 1;
489
490 /*
491 * Set the initial value for the level to which the rx ring
492 * should be filled, based on the max throughput and the
493 * worst likely latency for the host to fill the rx ring
494 * with new buffers. In theory, this fill level can be
495 * dynamically adjusted from the initial value set here, to
496 * reflect the actual host latency rather than a
497 * conservative assumption about the host latency.
498 */
499 htt->rx_ring.fill_level = ath10k_htt_rx_ring_fill_level(htt);
500
501 htt->rx_ring.netbufs_ring =
3e841fd0 502 kzalloc(htt->rx_ring.size * sizeof(struct sk_buff *),
5e3dd157
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503 GFP_KERNEL);
504 if (!htt->rx_ring.netbufs_ring)
505 goto err_netbuf;
506
bd8bdbb6
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507 size = htt->rx_ring.size * sizeof(htt->rx_ring.paddrs_ring);
508
509 vaddr = dma_alloc_coherent(htt->ar->dev, size, &paddr, GFP_DMA);
5e3dd157
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510 if (!vaddr)
511 goto err_dma_ring;
512
513 htt->rx_ring.paddrs_ring = vaddr;
514 htt->rx_ring.base_paddr = paddr;
515
516 vaddr = dma_alloc_coherent(htt->ar->dev,
517 sizeof(*htt->rx_ring.alloc_idx.vaddr),
518 &paddr, GFP_DMA);
519 if (!vaddr)
520 goto err_dma_idx;
521
522 htt->rx_ring.alloc_idx.vaddr = vaddr;
523 htt->rx_ring.alloc_idx.paddr = paddr;
524 htt->rx_ring.sw_rd_idx.msdu_payld = 0;
525 *htt->rx_ring.alloc_idx.vaddr = 0;
526
527 /* Initialize the Rx refill retry timer */
528 setup_timer(timer, ath10k_htt_rx_ring_refill_retry, (unsigned long)htt);
529
530 spin_lock_init(&htt->rx_ring.lock);
531
532 htt->rx_ring.fill_cnt = 0;
533 if (__ath10k_htt_rx_ring_fill_n(htt, htt->rx_ring.fill_level))
534 goto err_fill_ring;
535
6e712d42
MK
536 tasklet_init(&htt->rx_replenish_task, ath10k_htt_rx_replenish_task,
537 (unsigned long)htt);
538
6c5151a9
MK
539 skb_queue_head_init(&htt->tx_compl_q);
540 skb_queue_head_init(&htt->rx_compl_q);
541
542 tasklet_init(&htt->txrx_compl_task, ath10k_htt_txrx_compl_task,
543 (unsigned long)htt);
544
7aa7a72a 545 ath10k_dbg(ar, ATH10K_DBG_BOOT, "htt rx ring size %d fill_level %d\n",
5e3dd157
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546 htt->rx_ring.size, htt->rx_ring.fill_level);
547 return 0;
548
549err_fill_ring:
550 ath10k_htt_rx_ring_free(htt);
551 dma_free_coherent(htt->ar->dev,
552 sizeof(*htt->rx_ring.alloc_idx.vaddr),
553 htt->rx_ring.alloc_idx.vaddr,
554 htt->rx_ring.alloc_idx.paddr);
555err_dma_idx:
556 dma_free_coherent(htt->ar->dev,
557 (htt->rx_ring.size *
558 sizeof(htt->rx_ring.paddrs_ring)),
559 htt->rx_ring.paddrs_ring,
560 htt->rx_ring.base_paddr);
561err_dma_ring:
562 kfree(htt->rx_ring.netbufs_ring);
563err_netbuf:
564 return -ENOMEM;
565}
566
7aa7a72a
MK
567static int ath10k_htt_rx_crypto_param_len(struct ath10k *ar,
568 enum htt_rx_mpdu_encrypt_type type)
5e3dd157
KV
569{
570 switch (type) {
890d3b2a
MK
571 case HTT_RX_MPDU_ENCRYPT_NONE:
572 return 0;
5e3dd157
KV
573 case HTT_RX_MPDU_ENCRYPT_WEP40:
574 case HTT_RX_MPDU_ENCRYPT_WEP104:
890d3b2a 575 return IEEE80211_WEP_IV_LEN;
5e3dd157 576 case HTT_RX_MPDU_ENCRYPT_TKIP_WITHOUT_MIC:
5e3dd157 577 case HTT_RX_MPDU_ENCRYPT_TKIP_WPA:
890d3b2a 578 return IEEE80211_TKIP_IV_LEN;
5e3dd157 579 case HTT_RX_MPDU_ENCRYPT_AES_CCM_WPA2:
890d3b2a
MK
580 return IEEE80211_CCMP_HDR_LEN;
581 case HTT_RX_MPDU_ENCRYPT_WEP128:
582 case HTT_RX_MPDU_ENCRYPT_WAPI:
583 break;
5e3dd157
KV
584 }
585
890d3b2a 586 ath10k_warn(ar, "unsupported encryption type %d\n", type);
5e3dd157
KV
587 return 0;
588}
589
890d3b2a
MK
590#define MICHAEL_MIC_LEN 8
591
7aa7a72a
MK
592static int ath10k_htt_rx_crypto_tail_len(struct ath10k *ar,
593 enum htt_rx_mpdu_encrypt_type type)
5e3dd157
KV
594{
595 switch (type) {
596 case HTT_RX_MPDU_ENCRYPT_NONE:
890d3b2a 597 return 0;
5e3dd157
KV
598 case HTT_RX_MPDU_ENCRYPT_WEP40:
599 case HTT_RX_MPDU_ENCRYPT_WEP104:
890d3b2a 600 return IEEE80211_WEP_ICV_LEN;
5e3dd157
KV
601 case HTT_RX_MPDU_ENCRYPT_TKIP_WITHOUT_MIC:
602 case HTT_RX_MPDU_ENCRYPT_TKIP_WPA:
890d3b2a 603 return IEEE80211_TKIP_ICV_LEN;
5e3dd157 604 case HTT_RX_MPDU_ENCRYPT_AES_CCM_WPA2:
890d3b2a
MK
605 return IEEE80211_CCMP_MIC_LEN;
606 case HTT_RX_MPDU_ENCRYPT_WEP128:
607 case HTT_RX_MPDU_ENCRYPT_WAPI:
608 break;
5e3dd157
KV
609 }
610
890d3b2a 611 ath10k_warn(ar, "unsupported encryption type %d\n", type);
5e3dd157
KV
612 return 0;
613}
614
615/* Applies for first msdu in chain, before altering it. */
616static struct ieee80211_hdr *ath10k_htt_rx_skb_get_hdr(struct sk_buff *skb)
617{
618 struct htt_rx_desc *rxd;
619 enum rx_msdu_decap_format fmt;
620
621 rxd = (void *)skb->data - sizeof(*rxd);
622 fmt = MS(__le32_to_cpu(rxd->msdu_start.info1),
5b07e07f 623 RX_MSDU_START_INFO1_DECAP_FORMAT);
5e3dd157
KV
624
625 if (fmt == RX_MSDU_DECAP_RAW)
626 return (void *)skb->data;
d8bb26b9
KV
627
628 return (void *)skb->data - RX_HTT_HDR_STATUS_LEN;
5e3dd157
KV
629}
630
631/* This function only applies for first msdu in an msdu chain */
632static bool ath10k_htt_rx_hdr_is_amsdu(struct ieee80211_hdr *hdr)
633{
af762c0b
KV
634 u8 *qc;
635
5e3dd157 636 if (ieee80211_is_data_qos(hdr->frame_control)) {
af762c0b 637 qc = ieee80211_get_qos_ctl(hdr);
5e3dd157
KV
638 if (qc[0] & 0x80)
639 return true;
640 }
641 return false;
642}
643
f6dc2095
MK
644struct rfc1042_hdr {
645 u8 llc_dsap;
646 u8 llc_ssap;
647 u8 llc_ctrl;
648 u8 snap_oui[3];
649 __be16 snap_type;
650} __packed;
651
652struct amsdu_subframe_hdr {
653 u8 dst[ETH_ALEN];
654 u8 src[ETH_ALEN];
655 __be16 len;
656} __packed;
657
73539b40
JD
658static const u8 rx_legacy_rate_idx[] = {
659 3, /* 0x00 - 11Mbps */
660 2, /* 0x01 - 5.5Mbps */
661 1, /* 0x02 - 2Mbps */
662 0, /* 0x03 - 1Mbps */
663 3, /* 0x04 - 11Mbps */
664 2, /* 0x05 - 5.5Mbps */
665 1, /* 0x06 - 2Mbps */
666 0, /* 0x07 - 1Mbps */
667 10, /* 0x08 - 48Mbps */
668 8, /* 0x09 - 24Mbps */
669 6, /* 0x0A - 12Mbps */
670 4, /* 0x0B - 6Mbps */
671 11, /* 0x0C - 54Mbps */
672 9, /* 0x0D - 36Mbps */
673 7, /* 0x0E - 18Mbps */
674 5, /* 0x0F - 9Mbps */
675};
676
87326c97 677static void ath10k_htt_rx_h_rates(struct ath10k *ar,
cfadd9ba 678 enum ieee80211_band band,
87326c97 679 u8 info0, u32 info1, u32 info2,
cfadd9ba 680 struct ieee80211_rx_status *status)
73539b40
JD
681{
682 u8 cck, rate, rate_idx, bw, sgi, mcs, nss;
73539b40
JD
683 u8 preamble = 0;
684
685 /* Check if valid fields */
686 if (!(info0 & HTT_RX_INDICATION_INFO0_START_VALID))
687 return;
688
689 preamble = MS(info1, HTT_RX_INDICATION_INFO1_PREAMBLE_TYPE);
690
691 switch (preamble) {
692 case HTT_RX_LEGACY:
693 cck = info0 & HTT_RX_INDICATION_INFO0_LEGACY_RATE_CCK;
694 rate = MS(info0, HTT_RX_INDICATION_INFO0_LEGACY_RATE);
695 rate_idx = 0;
696
697 if (rate < 0x08 || rate > 0x0F)
698 break;
699
700 switch (band) {
701 case IEEE80211_BAND_2GHZ:
702 if (cck)
703 rate &= ~BIT(3);
704 rate_idx = rx_legacy_rate_idx[rate];
705 break;
706 case IEEE80211_BAND_5GHZ:
707 rate_idx = rx_legacy_rate_idx[rate];
708 /* We are using same rate table registering
709 HW - ath10k_rates[]. In case of 5GHz skip
710 CCK rates, so -4 here */
711 rate_idx -= 4;
712 break;
713 default:
714 break;
715 }
716
717 status->rate_idx = rate_idx;
718 break;
719 case HTT_RX_HT:
720 case HTT_RX_HT_WITH_TXBF:
721 /* HT-SIG - Table 20-11 in info1 and info2 */
722 mcs = info1 & 0x1F;
723 nss = mcs >> 3;
724 bw = (info1 >> 7) & 1;
725 sgi = (info2 >> 7) & 1;
726
727 status->rate_idx = mcs;
728 status->flag |= RX_FLAG_HT;
729 if (sgi)
730 status->flag |= RX_FLAG_SHORT_GI;
731 if (bw)
732 status->flag |= RX_FLAG_40MHZ;
733 break;
734 case HTT_RX_VHT:
735 case HTT_RX_VHT_WITH_TXBF:
736 /* VHT-SIG-A1 in info 1, VHT-SIG-A2 in info2
737 TODO check this */
738 mcs = (info2 >> 4) & 0x0F;
739 nss = ((info1 >> 10) & 0x07) + 1;
740 bw = info1 & 3;
741 sgi = info2 & 1;
742
743 status->rate_idx = mcs;
744 status->vht_nss = nss;
745
746 if (sgi)
747 status->flag |= RX_FLAG_SHORT_GI;
748
749 switch (bw) {
750 /* 20MHZ */
751 case 0:
752 break;
753 /* 40MHZ */
754 case 1:
755 status->flag |= RX_FLAG_40MHZ;
756 break;
757 /* 80MHZ */
758 case 2:
759 status->vht_flag |= RX_VHT_FLAG_80MHZ;
760 }
761
762 status->flag |= RX_FLAG_VHT;
763 break;
764 default:
765 break;
766 }
767}
768
87326c97 769static void ath10k_htt_rx_h_protected(struct ath10k_htt *htt,
85f6d7cf
JD
770 struct ieee80211_rx_status *rx_status,
771 struct sk_buff *skb,
c071dcb2
MK
772 enum htt_rx_mpdu_encrypt_type enctype,
773 enum rx_msdu_decap_format fmt,
774 bool dot11frag)
87326c97 775{
85f6d7cf 776 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
87326c97 777
c071dcb2
MK
778 rx_status->flag &= ~(RX_FLAG_DECRYPTED |
779 RX_FLAG_IV_STRIPPED |
780 RX_FLAG_MMIC_STRIPPED);
87326c97 781
c071dcb2
MK
782 if (enctype == HTT_RX_MPDU_ENCRYPT_NONE)
783 return;
784
785 /*
786 * There's no explicit rx descriptor flag to indicate whether a given
787 * frame has been decrypted or not. We're forced to use the decap
788 * format as an implicit indication. However fragmentation rx is always
789 * raw and it probably never reports undecrypted raws.
790 *
791 * This makes sure sniffed frames are reported as-is without stripping
792 * the protected flag.
793 */
794 if (fmt == RX_MSDU_DECAP_RAW && !dot11frag)
87326c97 795 return;
87326c97 796
85f6d7cf
JD
797 rx_status->flag |= RX_FLAG_DECRYPTED |
798 RX_FLAG_IV_STRIPPED |
799 RX_FLAG_MMIC_STRIPPED;
87326c97
JD
800 hdr->frame_control = __cpu_to_le16(__le16_to_cpu(hdr->frame_control) &
801 ~IEEE80211_FCTL_PROTECTED);
802}
803
36653f05
JD
804static bool ath10k_htt_rx_h_channel(struct ath10k *ar,
805 struct ieee80211_rx_status *status)
806{
807 struct ieee80211_channel *ch;
808
809 spin_lock_bh(&ar->data_lock);
810 ch = ar->scan_channel;
811 if (!ch)
812 ch = ar->rx_channel;
813 spin_unlock_bh(&ar->data_lock);
814
815 if (!ch)
816 return false;
817
818 status->band = ch->band;
819 status->freq = ch->center_freq;
820
821 return true;
822}
823
76f5329a
JD
824static const char * const tid_to_ac[] = {
825 "BE",
826 "BK",
827 "BK",
828 "BE",
829 "VI",
830 "VI",
831 "VO",
832 "VO",
833};
834
835static char *ath10k_get_tid(struct ieee80211_hdr *hdr, char *out, size_t size)
836{
837 u8 *qc;
838 int tid;
839
840 if (!ieee80211_is_data_qos(hdr->frame_control))
841 return "";
842
843 qc = ieee80211_get_qos_ctl(hdr);
844 tid = *qc & IEEE80211_QOS_CTL_TID_MASK;
845 if (tid < 8)
846 snprintf(out, size, "tid %d (%s)", tid, tid_to_ac[tid]);
847 else
848 snprintf(out, size, "tid %d", tid);
849
850 return out;
851}
852
85f6d7cf
JD
853static void ath10k_process_rx(struct ath10k *ar,
854 struct ieee80211_rx_status *rx_status,
855 struct sk_buff *skb)
73539b40
JD
856{
857 struct ieee80211_rx_status *status;
76f5329a
JD
858 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
859 char tid[32];
73539b40 860
85f6d7cf
JD
861 status = IEEE80211_SKB_RXCB(skb);
862 *status = *rx_status;
73539b40 863
7aa7a72a 864 ath10k_dbg(ar, ATH10K_DBG_DATA,
76f5329a 865 "rx skb %p len %u peer %pM %s %s sn %u %s%s%s%s%s %srate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n",
85f6d7cf
JD
866 skb,
867 skb->len,
76f5329a
JD
868 ieee80211_get_SA(hdr),
869 ath10k_get_tid(hdr, tid, sizeof(tid)),
870 is_multicast_ether_addr(ieee80211_get_DA(hdr)) ?
871 "mcast" : "ucast",
872 (__le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4,
73539b40
JD
873 status->flag == 0 ? "legacy" : "",
874 status->flag & RX_FLAG_HT ? "ht" : "",
875 status->flag & RX_FLAG_VHT ? "vht" : "",
876 status->flag & RX_FLAG_40MHZ ? "40" : "",
877 status->vht_flag & RX_VHT_FLAG_80MHZ ? "80" : "",
878 status->flag & RX_FLAG_SHORT_GI ? "sgi " : "",
879 status->rate_idx,
880 status->vht_nss,
881 status->freq,
87326c97 882 status->band, status->flag,
78433f96 883 !!(status->flag & RX_FLAG_FAILED_FCS_CRC),
76f5329a
JD
884 !!(status->flag & RX_FLAG_MMIC_ERROR),
885 !!(status->flag & RX_FLAG_AMSDU_MORE));
7aa7a72a 886 ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "rx skb: ",
85f6d7cf 887 skb->data, skb->len);
5ce8e7fd
RM
888 trace_ath10k_rx_hdr(ar, skb->data, skb->len);
889 trace_ath10k_rx_payload(ar, skb->data, skb->len);
73539b40 890
85f6d7cf 891 ieee80211_rx(ar->hw, skb);
73539b40
JD
892}
893
d960c369
MK
894static int ath10k_htt_rx_nwifi_hdrlen(struct ieee80211_hdr *hdr)
895{
896 /* nwifi header is padded to 4 bytes. this fixes 4addr rx */
897 return round_up(ieee80211_hdrlen(hdr->frame_control), 4);
898}
899
f6dc2095 900static void ath10k_htt_rx_amsdu(struct ath10k_htt *htt,
85f6d7cf 901 struct ieee80211_rx_status *rx_status,
9aa505d2 902 struct sk_buff_head *amsdu)
5e3dd157 903{
7aa7a72a 904 struct ath10k *ar = htt->ar;
5e3dd157 905 struct htt_rx_desc *rxd;
9aa505d2 906 struct sk_buff *skb;
5e3dd157 907 struct sk_buff *first;
5e3dd157
KV
908 enum rx_msdu_decap_format fmt;
909 enum htt_rx_mpdu_encrypt_type enctype;
f6dc2095 910 struct ieee80211_hdr *hdr;
72bdeb86 911 u8 hdr_buf[64], da[ETH_ALEN], sa[ETH_ALEN], *qos;
5e3dd157 912 unsigned int hdr_len;
5e3dd157 913
9aa505d2
MK
914 first = skb_peek(amsdu);
915
916 rxd = (void *)first->data - sizeof(*rxd);
5e3dd157 917 enctype = MS(__le32_to_cpu(rxd->mpdu_start.info0),
5b07e07f 918 RX_MPDU_START_INFO0_ENCRYPT_TYPE);
5e3dd157 919
f6dc2095
MK
920 hdr = (struct ieee80211_hdr *)rxd->rx_hdr_status;
921 hdr_len = ieee80211_hdrlen(hdr->frame_control);
922 memcpy(hdr_buf, hdr, hdr_len);
923 hdr = (struct ieee80211_hdr *)hdr_buf;
5e3dd157 924
9aa505d2 925 while ((skb = __skb_dequeue(amsdu))) {
5e3dd157 926 void *decap_hdr;
f6dc2095 927 int len;
5e3dd157
KV
928
929 rxd = (void *)skb->data - sizeof(*rxd);
930 fmt = MS(__le32_to_cpu(rxd->msdu_start.info1),
f6dc2095 931 RX_MSDU_START_INFO1_DECAP_FORMAT);
5e3dd157
KV
932 decap_hdr = (void *)rxd->rx_hdr_status;
933
f6dc2095 934 skb->ip_summed = ath10k_htt_rx_get_csum_state(skb);
5e3dd157 935
f6dc2095
MK
936 /* First frame in an A-MSDU chain has more decapped data. */
937 if (skb == first) {
938 len = round_up(ieee80211_hdrlen(hdr->frame_control), 4);
7aa7a72a
MK
939 len += round_up(ath10k_htt_rx_crypto_param_len(ar,
940 enctype), 4);
f6dc2095 941 decap_hdr += len;
5e3dd157
KV
942 }
943
f6dc2095
MK
944 switch (fmt) {
945 case RX_MSDU_DECAP_RAW:
e3fbf8d2 946 /* remove trailing FCS */
f6dc2095
MK
947 skb_trim(skb, skb->len - FCS_LEN);
948 break;
949 case RX_MSDU_DECAP_NATIVE_WIFI:
72bdeb86 950 /* pull decapped header and copy SA & DA */
784f69d3 951 hdr = (struct ieee80211_hdr *)skb->data;
d960c369 952 hdr_len = ath10k_htt_rx_nwifi_hdrlen(hdr);
b25f32cb
KV
953 ether_addr_copy(da, ieee80211_get_DA(hdr));
954 ether_addr_copy(sa, ieee80211_get_SA(hdr));
784f69d3
MK
955 skb_pull(skb, hdr_len);
956
957 /* push original 802.11 header */
958 hdr = (struct ieee80211_hdr *)hdr_buf;
959 hdr_len = ieee80211_hdrlen(hdr->frame_control);
960 memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
961
962 /* original A-MSDU header has the bit set but we're
963 * not including A-MSDU subframe header */
964 hdr = (struct ieee80211_hdr *)skb->data;
965 qos = ieee80211_get_qos_ctl(hdr);
966 qos[0] &= ~IEEE80211_QOS_CTL_A_MSDU_PRESENT;
967
72bdeb86
MK
968 /* original 802.11 header has a different DA and in
969 * case of 4addr it may also have different SA
970 */
b25f32cb
KV
971 ether_addr_copy(ieee80211_get_DA(hdr), da);
972 ether_addr_copy(ieee80211_get_SA(hdr), sa);
f6dc2095
MK
973 break;
974 case RX_MSDU_DECAP_ETHERNET2_DIX:
e3fbf8d2
MK
975 /* strip ethernet header and insert decapped 802.11
976 * header, amsdu subframe header and rfc1042 header */
977
f6dc2095
MK
978 len = 0;
979 len += sizeof(struct rfc1042_hdr);
980 len += sizeof(struct amsdu_subframe_hdr);
981
982 skb_pull(skb, sizeof(struct ethhdr));
983 memcpy(skb_push(skb, len), decap_hdr, len);
984 memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
985 break;
986 case RX_MSDU_DECAP_8023_SNAP_LLC:
e3fbf8d2
MK
987 /* insert decapped 802.11 header making a singly
988 * A-MSDU */
f6dc2095
MK
989 memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
990 break;
5e3dd157
KV
991 }
992
9aa505d2 993 ath10k_htt_rx_h_protected(htt, rx_status, skb, enctype, fmt,
c071dcb2 994 false);
5e3dd157 995
9aa505d2 996 if (skb_queue_empty(amsdu))
85f6d7cf 997 rx_status->flag &= ~RX_FLAG_AMSDU_MORE;
9aa505d2
MK
998 else
999 rx_status->flag |= RX_FLAG_AMSDU_MORE;
652de35e 1000
9aa505d2 1001 ath10k_process_rx(htt->ar, rx_status, skb);
f6dc2095 1002 }
5e3dd157 1003
f6dc2095
MK
1004 /* FIXME: It might be nice to re-assemble the A-MSDU when there's a
1005 * monitor interface active for sniffing purposes. */
5e3dd157
KV
1006}
1007
85f6d7cf
JD
1008static void ath10k_htt_rx_msdu(struct ath10k_htt *htt,
1009 struct ieee80211_rx_status *rx_status,
1010 struct sk_buff *skb)
5e3dd157 1011{
7aa7a72a 1012 struct ath10k *ar = htt->ar;
5e3dd157
KV
1013 struct htt_rx_desc *rxd;
1014 struct ieee80211_hdr *hdr;
1015 enum rx_msdu_decap_format fmt;
1016 enum htt_rx_mpdu_encrypt_type enctype;
e3fbf8d2
MK
1017 int hdr_len;
1018 void *rfc1042;
5e3dd157 1019
5e3dd157
KV
1020 rxd = (void *)skb->data - sizeof(*rxd);
1021 fmt = MS(__le32_to_cpu(rxd->msdu_start.info1),
5b07e07f 1022 RX_MSDU_START_INFO1_DECAP_FORMAT);
5e3dd157 1023 enctype = MS(__le32_to_cpu(rxd->mpdu_start.info0),
5b07e07f 1024 RX_MPDU_START_INFO0_ENCRYPT_TYPE);
e3fbf8d2
MK
1025 hdr = (struct ieee80211_hdr *)rxd->rx_hdr_status;
1026 hdr_len = ieee80211_hdrlen(hdr->frame_control);
5e3dd157 1027
f6dc2095
MK
1028 skb->ip_summed = ath10k_htt_rx_get_csum_state(skb);
1029
5e3dd157
KV
1030 switch (fmt) {
1031 case RX_MSDU_DECAP_RAW:
1032 /* remove trailing FCS */
e3fbf8d2 1033 skb_trim(skb, skb->len - FCS_LEN);
5e3dd157
KV
1034 break;
1035 case RX_MSDU_DECAP_NATIVE_WIFI:
784f69d3
MK
1036 /* Pull decapped header */
1037 hdr = (struct ieee80211_hdr *)skb->data;
d960c369 1038 hdr_len = ath10k_htt_rx_nwifi_hdrlen(hdr);
784f69d3
MK
1039 skb_pull(skb, hdr_len);
1040
1041 /* Push original header */
1042 hdr = (struct ieee80211_hdr *)rxd->rx_hdr_status;
1043 hdr_len = ieee80211_hdrlen(hdr->frame_control);
1044 memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
5e3dd157
KV
1045 break;
1046 case RX_MSDU_DECAP_ETHERNET2_DIX:
e3fbf8d2
MK
1047 /* strip ethernet header and insert decapped 802.11 header and
1048 * rfc1042 header */
5e3dd157 1049
e3fbf8d2
MK
1050 rfc1042 = hdr;
1051 rfc1042 += roundup(hdr_len, 4);
7aa7a72a
MK
1052 rfc1042 += roundup(ath10k_htt_rx_crypto_param_len(ar,
1053 enctype), 4);
5e3dd157 1054
e3fbf8d2
MK
1055 skb_pull(skb, sizeof(struct ethhdr));
1056 memcpy(skb_push(skb, sizeof(struct rfc1042_hdr)),
1057 rfc1042, sizeof(struct rfc1042_hdr));
1058 memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
1059 break;
1060 case RX_MSDU_DECAP_8023_SNAP_LLC:
1061 /* remove A-MSDU subframe header and insert
1062 * decapped 802.11 header. rfc1042 header is already there */
5e3dd157 1063
e3fbf8d2
MK
1064 skb_pull(skb, sizeof(struct amsdu_subframe_hdr));
1065 memcpy(skb_push(skb, hdr_len), hdr, hdr_len);
1066 break;
5e3dd157
KV
1067 }
1068
c071dcb2 1069 ath10k_htt_rx_h_protected(htt, rx_status, skb, enctype, fmt, false);
f6dc2095 1070
85f6d7cf 1071 ath10k_process_rx(htt->ar, rx_status, skb);
5e3dd157
KV
1072}
1073
605f81aa
MK
1074static int ath10k_htt_rx_get_csum_state(struct sk_buff *skb)
1075{
1076 struct htt_rx_desc *rxd;
1077 u32 flags, info;
1078 bool is_ip4, is_ip6;
1079 bool is_tcp, is_udp;
1080 bool ip_csum_ok, tcpudp_csum_ok;
1081
1082 rxd = (void *)skb->data - sizeof(*rxd);
1083 flags = __le32_to_cpu(rxd->attention.flags);
1084 info = __le32_to_cpu(rxd->msdu_start.info1);
1085
1086 is_ip4 = !!(info & RX_MSDU_START_INFO1_IPV4_PROTO);
1087 is_ip6 = !!(info & RX_MSDU_START_INFO1_IPV6_PROTO);
1088 is_tcp = !!(info & RX_MSDU_START_INFO1_TCP_PROTO);
1089 is_udp = !!(info & RX_MSDU_START_INFO1_UDP_PROTO);
1090 ip_csum_ok = !(flags & RX_ATTENTION_FLAGS_IP_CHKSUM_FAIL);
1091 tcpudp_csum_ok = !(flags & RX_ATTENTION_FLAGS_TCP_UDP_CHKSUM_FAIL);
1092
1093 if (!is_ip4 && !is_ip6)
1094 return CHECKSUM_NONE;
1095 if (!is_tcp && !is_udp)
1096 return CHECKSUM_NONE;
1097 if (!ip_csum_ok)
1098 return CHECKSUM_NONE;
1099 if (!tcpudp_csum_ok)
1100 return CHECKSUM_NONE;
1101
1102 return CHECKSUM_UNNECESSARY;
1103}
1104
9aa505d2 1105static int ath10k_unchain_msdu(struct sk_buff_head *amsdu)
bfa35368 1106{
9aa505d2 1107 struct sk_buff *skb, *first;
bfa35368
BG
1108 int space;
1109 int total_len = 0;
1110
1111 /* TODO: Might could optimize this by using
1112 * skb_try_coalesce or similar method to
1113 * decrease copying, or maybe get mac80211 to
1114 * provide a way to just receive a list of
1115 * skb?
1116 */
1117
9aa505d2 1118 first = __skb_dequeue(amsdu);
bfa35368
BG
1119
1120 /* Allocate total length all at once. */
9aa505d2
MK
1121 skb_queue_walk(amsdu, skb)
1122 total_len += skb->len;
bfa35368 1123
9aa505d2 1124 space = total_len - skb_tailroom(first);
bfa35368 1125 if ((space > 0) &&
9aa505d2 1126 (pskb_expand_head(first, 0, space, GFP_ATOMIC) < 0)) {
bfa35368
BG
1127 /* TODO: bump some rx-oom error stat */
1128 /* put it back together so we can free the
1129 * whole list at once.
1130 */
9aa505d2 1131 __skb_queue_head(amsdu, first);
bfa35368
BG
1132 return -1;
1133 }
1134
1135 /* Walk list again, copying contents into
1136 * msdu_head
1137 */
9aa505d2
MK
1138 while ((skb = __skb_dequeue(amsdu))) {
1139 skb_copy_from_linear_data(skb, skb_put(first, skb->len),
1140 skb->len);
1141 dev_kfree_skb_any(skb);
bfa35368
BG
1142 }
1143
9aa505d2 1144 __skb_queue_head(amsdu, first);
bfa35368
BG
1145 return 0;
1146}
1147
2acc4eb2
JD
1148static bool ath10k_htt_rx_amsdu_allowed(struct ath10k_htt *htt,
1149 struct sk_buff *head,
78433f96
JD
1150 bool channel_set,
1151 u32 attention)
2acc4eb2 1152{
7aa7a72a
MK
1153 struct ath10k *ar = htt->ar;
1154
2acc4eb2 1155 if (head->len == 0) {
7aa7a72a 1156 ath10k_dbg(ar, ATH10K_DBG_HTT,
2acc4eb2
JD
1157 "htt rx dropping due to zero-len\n");
1158 return false;
1159 }
1160
78433f96 1161 if (attention & RX_ATTENTION_FLAGS_DECRYPT_ERR) {
7aa7a72a 1162 ath10k_dbg(ar, ATH10K_DBG_HTT,
2acc4eb2
JD
1163 "htt rx dropping due to decrypt-err\n");
1164 return false;
1165 }
1166
36653f05 1167 if (!channel_set) {
7aa7a72a 1168 ath10k_warn(ar, "no channel configured; ignoring frame!\n");
36653f05
JD
1169 return false;
1170 }
1171
2acc4eb2 1172 /* Skip mgmt frames while we handle this in WMI */
f6b946ef 1173 if (attention & RX_ATTENTION_FLAGS_MGMT_TYPE) {
7aa7a72a 1174 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt rx mgmt ctrl\n");
2acc4eb2
JD
1175 return false;
1176 }
1177
2acc4eb2 1178 if (test_bit(ATH10K_CAC_RUNNING, &htt->ar->dev_flags)) {
7aa7a72a 1179 ath10k_dbg(ar, ATH10K_DBG_HTT,
2acc4eb2
JD
1180 "htt rx CAC running\n");
1181 return false;
1182 }
1183
1184 return true;
1185}
1186
5e3dd157
KV
1187static void ath10k_htt_rx_handler(struct ath10k_htt *htt,
1188 struct htt_rx_indication *rx)
1189{
7aa7a72a 1190 struct ath10k *ar = htt->ar;
6df92a3d 1191 struct ieee80211_rx_status *rx_status = &htt->rx_status;
5e3dd157 1192 struct htt_rx_indication_mpdu_range *mpdu_ranges;
9aa505d2 1193 struct sk_buff_head amsdu;
5e3dd157
KV
1194 struct ieee80211_hdr *hdr;
1195 int num_mpdu_ranges;
78433f96 1196 u32 attention;
5e3dd157
KV
1197 int fw_desc_len;
1198 u8 *fw_desc;
78433f96 1199 bool channel_set;
d540690d 1200 int i, ret, mpdu_count = 0;
5e3dd157 1201
45967089
MK
1202 lockdep_assert_held(&htt->rx_ring.lock);
1203
5e3dd157
KV
1204 fw_desc_len = __le16_to_cpu(rx->prefix.fw_rx_desc_bytes);
1205 fw_desc = (u8 *)&rx->fw_desc;
1206
1207 num_mpdu_ranges = MS(__le32_to_cpu(rx->hdr.info1),
1208 HTT_RX_INDICATION_INFO1_NUM_MPDU_RANGES);
1209 mpdu_ranges = htt_rx_ind_get_mpdu_ranges(rx);
1210
e8dc1a96 1211 /* Fill this once, while this is per-ppdu */
2289188c
JD
1212 if (rx->ppdu.info0 & HTT_RX_INDICATION_INFO0_START_VALID) {
1213 memset(rx_status, 0, sizeof(*rx_status));
1214 rx_status->signal = ATH10K_DEFAULT_NOISE_FLOOR +
1215 rx->ppdu.combined_rssi;
1216 }
87326c97
JD
1217
1218 if (rx->ppdu.info0 & HTT_RX_INDICATION_INFO0_END_VALID) {
1219 /* TSF available only in 32-bit */
6df92a3d
JD
1220 rx_status->mactime = __le32_to_cpu(rx->ppdu.tsf) & 0xffffffff;
1221 rx_status->flag |= RX_FLAG_MACTIME_END;
87326c97 1222 }
e8dc1a96 1223
6df92a3d 1224 channel_set = ath10k_htt_rx_h_channel(htt->ar, rx_status);
36653f05 1225
87326c97 1226 if (channel_set) {
6df92a3d 1227 ath10k_htt_rx_h_rates(htt->ar, rx_status->band,
87326c97
JD
1228 rx->ppdu.info0,
1229 __le32_to_cpu(rx->ppdu.info1),
1230 __le32_to_cpu(rx->ppdu.info2),
6df92a3d 1231 rx_status);
87326c97 1232 }
e8dc1a96 1233
7aa7a72a 1234 ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt rx ind: ",
5e3dd157
KV
1235 rx, sizeof(*rx) +
1236 (sizeof(struct htt_rx_indication_mpdu_range) *
1237 num_mpdu_ranges));
1238
d540690d
MK
1239 for (i = 0; i < num_mpdu_ranges; i++)
1240 mpdu_count += mpdu_ranges[i].mpdu_count;
1241
1242 while (mpdu_count--) {
1243 attention = 0;
1244 __skb_queue_head_init(&amsdu);
1245 ret = ath10k_htt_rx_amsdu_pop(htt, &fw_desc,
1246 &fw_desc_len, &amsdu,
1247 &attention);
1248 if (ret < 0) {
1249 ath10k_warn(ar, "failed to pop amsdu from htt rx ring %d\n",
1250 ret);
1251 __skb_queue_purge(&amsdu);
1252 continue;
1253 }
5e3dd157 1254
d540690d
MK
1255 if (!ath10k_htt_rx_amsdu_allowed(htt, skb_peek(&amsdu),
1256 channel_set, attention)) {
1257 __skb_queue_purge(&amsdu);
1258 continue;
1259 }
e8a50f8b 1260
d540690d
MK
1261 if (ret > 0 && ath10k_unchain_msdu(&amsdu) < 0) {
1262 __skb_queue_purge(&amsdu);
1263 continue;
1264 }
5e3dd157 1265
d540690d
MK
1266 if (attention & RX_ATTENTION_FLAGS_FCS_ERR)
1267 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
1268 else
1269 rx_status->flag &= ~RX_FLAG_FAILED_FCS_CRC;
87326c97 1270
d540690d
MK
1271 if (attention & RX_ATTENTION_FLAGS_TKIP_MIC_ERR)
1272 rx_status->flag |= RX_FLAG_MMIC_ERROR;
1273 else
1274 rx_status->flag &= ~RX_FLAG_MMIC_ERROR;
87326c97 1275
d540690d 1276 hdr = ath10k_htt_rx_skb_get_hdr(skb_peek(&amsdu));
5e3dd157 1277
d540690d
MK
1278 if (ath10k_htt_rx_hdr_is_amsdu(hdr))
1279 ath10k_htt_rx_amsdu(htt, rx_status, &amsdu);
1280 else
1281 ath10k_htt_rx_msdu(htt, rx_status,
1282 __skb_dequeue(&amsdu));
5e3dd157
KV
1283 }
1284
6e712d42 1285 tasklet_schedule(&htt->rx_replenish_task);
5e3dd157
KV
1286}
1287
1288static void ath10k_htt_rx_frag_handler(struct ath10k_htt *htt,
5b07e07f 1289 struct htt_rx_fragment_indication *frag)
5e3dd157 1290{
7aa7a72a 1291 struct ath10k *ar = htt->ar;
9aa505d2 1292 struct sk_buff *msdu;
87326c97 1293 enum htt_rx_mpdu_encrypt_type enctype;
5e3dd157
KV
1294 struct htt_rx_desc *rxd;
1295 enum rx_msdu_decap_format fmt;
6df92a3d 1296 struct ieee80211_rx_status *rx_status = &htt->rx_status;
5e3dd157 1297 struct ieee80211_hdr *hdr;
9aa505d2 1298 struct sk_buff_head amsdu;
d84dd60f 1299 int ret;
5e3dd157
KV
1300 bool tkip_mic_err;
1301 bool decrypt_err;
1302 u8 *fw_desc;
1303 int fw_desc_len, hdrlen, paramlen;
1304 int trim;
0ccb7a34 1305 u32 attention = 0;
5e3dd157
KV
1306
1307 fw_desc_len = __le16_to_cpu(frag->fw_rx_desc_bytes);
1308 fw_desc = (u8 *)frag->fw_msdu_rx_desc;
1309
9aa505d2 1310 __skb_queue_head_init(&amsdu);
45967089
MK
1311
1312 spin_lock_bh(&htt->rx_ring.lock);
d84dd60f 1313 ret = ath10k_htt_rx_amsdu_pop(htt, &fw_desc, &fw_desc_len,
9aa505d2 1314 &amsdu, &attention);
45967089 1315 spin_unlock_bh(&htt->rx_ring.lock);
5e3dd157 1316
686687c9
MK
1317 tasklet_schedule(&htt->rx_replenish_task);
1318
7aa7a72a 1319 ath10k_dbg(ar, ATH10K_DBG_HTT_DUMP, "htt rx frag ahead\n");
5e3dd157 1320
d84dd60f 1321 if (ret) {
7aa7a72a 1322 ath10k_warn(ar, "failed to pop amsdu from httr rx ring for fragmented rx %d\n",
d84dd60f 1323 ret);
9aa505d2 1324 __skb_queue_purge(&amsdu);
5e3dd157
KV
1325 return;
1326 }
1327
9aa505d2
MK
1328 if (skb_queue_len(&amsdu) != 1) {
1329 ath10k_warn(ar, "failed to pop frag amsdu: too many msdus\n");
1330 __skb_queue_purge(&amsdu);
1331 return;
1332 }
1333
1334 msdu = __skb_dequeue(&amsdu);
1335
5e3dd157 1336 /* FIXME: implement signal strength */
4b81d177 1337 rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL;
5e3dd157 1338
9aa505d2
MK
1339 hdr = (struct ieee80211_hdr *)msdu->data;
1340 rxd = (void *)msdu->data - sizeof(*rxd);
0ccb7a34
JD
1341 tkip_mic_err = !!(attention & RX_ATTENTION_FLAGS_TKIP_MIC_ERR);
1342 decrypt_err = !!(attention & RX_ATTENTION_FLAGS_DECRYPT_ERR);
5e3dd157 1343 fmt = MS(__le32_to_cpu(rxd->msdu_start.info1),
5b07e07f 1344 RX_MSDU_START_INFO1_DECAP_FORMAT);
5e3dd157
KV
1345
1346 if (fmt != RX_MSDU_DECAP_RAW) {
7aa7a72a 1347 ath10k_warn(ar, "we dont support non-raw fragmented rx yet\n");
9aa505d2 1348 dev_kfree_skb_any(msdu);
5e3dd157
KV
1349 goto end;
1350 }
1351
87326c97
JD
1352 enctype = MS(__le32_to_cpu(rxd->mpdu_start.info0),
1353 RX_MPDU_START_INFO0_ENCRYPT_TYPE);
9aa505d2 1354 ath10k_htt_rx_h_protected(htt, rx_status, msdu, enctype, fmt,
c071dcb2 1355 true);
9aa505d2 1356 msdu->ip_summed = ath10k_htt_rx_get_csum_state(msdu);
5e3dd157 1357
87326c97 1358 if (tkip_mic_err)
7aa7a72a 1359 ath10k_warn(ar, "tkip mic error\n");
5e3dd157
KV
1360
1361 if (decrypt_err) {
7aa7a72a 1362 ath10k_warn(ar, "decryption err in fragmented rx\n");
9aa505d2 1363 dev_kfree_skb_any(msdu);
5e3dd157
KV
1364 goto end;
1365 }
1366
87326c97 1367 if (enctype != HTT_RX_MPDU_ENCRYPT_NONE) {
5e3dd157 1368 hdrlen = ieee80211_hdrlen(hdr->frame_control);
7aa7a72a 1369 paramlen = ath10k_htt_rx_crypto_param_len(ar, enctype);
5e3dd157
KV
1370
1371 /* It is more efficient to move the header than the payload */
9aa505d2
MK
1372 memmove((void *)msdu->data + paramlen,
1373 (void *)msdu->data,
5e3dd157 1374 hdrlen);
9aa505d2
MK
1375 skb_pull(msdu, paramlen);
1376 hdr = (struct ieee80211_hdr *)msdu->data;
5e3dd157
KV
1377 }
1378
1379 /* remove trailing FCS */
1380 trim = 4;
1381
1382 /* remove crypto trailer */
7aa7a72a 1383 trim += ath10k_htt_rx_crypto_tail_len(ar, enctype);
5e3dd157
KV
1384
1385 /* last fragment of TKIP frags has MIC */
1386 if (!ieee80211_has_morefrags(hdr->frame_control) &&
87326c97 1387 enctype == HTT_RX_MPDU_ENCRYPT_TKIP_WPA)
890d3b2a 1388 trim += MICHAEL_MIC_LEN;
5e3dd157 1389
9aa505d2 1390 if (trim > msdu->len) {
7aa7a72a 1391 ath10k_warn(ar, "htt rx fragment: trailer longer than the frame itself? drop\n");
9aa505d2 1392 dev_kfree_skb_any(msdu);
5e3dd157
KV
1393 goto end;
1394 }
1395
9aa505d2 1396 skb_trim(msdu, msdu->len - trim);
5e3dd157 1397
7aa7a72a 1398 ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt rx frag mpdu: ",
9aa505d2
MK
1399 msdu->data, msdu->len);
1400 ath10k_process_rx(htt->ar, rx_status, msdu);
5e3dd157
KV
1401
1402end:
1403 if (fw_desc_len > 0) {
7aa7a72a 1404 ath10k_dbg(ar, ATH10K_DBG_HTT,
5e3dd157
KV
1405 "expecting more fragmented rx in one indication %d\n",
1406 fw_desc_len);
1407 }
1408}
1409
6c5151a9
MK
1410static void ath10k_htt_rx_frm_tx_compl(struct ath10k *ar,
1411 struct sk_buff *skb)
1412{
1413 struct ath10k_htt *htt = &ar->htt;
1414 struct htt_resp *resp = (struct htt_resp *)skb->data;
1415 struct htt_tx_done tx_done = {};
1416 int status = MS(resp->data_tx_completion.flags, HTT_DATA_TX_STATUS);
1417 __le16 msdu_id;
1418 int i;
1419
45967089
MK
1420 lockdep_assert_held(&htt->tx_lock);
1421
6c5151a9
MK
1422 switch (status) {
1423 case HTT_DATA_TX_STATUS_NO_ACK:
1424 tx_done.no_ack = true;
1425 break;
1426 case HTT_DATA_TX_STATUS_OK:
1427 break;
1428 case HTT_DATA_TX_STATUS_DISCARD:
1429 case HTT_DATA_TX_STATUS_POSTPONE:
1430 case HTT_DATA_TX_STATUS_DOWNLOAD_FAIL:
1431 tx_done.discard = true;
1432 break;
1433 default:
7aa7a72a 1434 ath10k_warn(ar, "unhandled tx completion status %d\n", status);
6c5151a9
MK
1435 tx_done.discard = true;
1436 break;
1437 }
1438
7aa7a72a 1439 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt tx completion num_msdus %d\n",
6c5151a9
MK
1440 resp->data_tx_completion.num_msdus);
1441
1442 for (i = 0; i < resp->data_tx_completion.num_msdus; i++) {
1443 msdu_id = resp->data_tx_completion.msdus[i];
1444 tx_done.msdu_id = __le16_to_cpu(msdu_id);
1445 ath10k_txrx_tx_unref(htt, &tx_done);
1446 }
1447}
1448
aa5b4fbc
MK
1449static void ath10k_htt_rx_addba(struct ath10k *ar, struct htt_resp *resp)
1450{
1451 struct htt_rx_addba *ev = &resp->rx_addba;
1452 struct ath10k_peer *peer;
1453 struct ath10k_vif *arvif;
1454 u16 info0, tid, peer_id;
1455
1456 info0 = __le16_to_cpu(ev->info0);
1457 tid = MS(info0, HTT_RX_BA_INFO0_TID);
1458 peer_id = MS(info0, HTT_RX_BA_INFO0_PEER_ID);
1459
7aa7a72a 1460 ath10k_dbg(ar, ATH10K_DBG_HTT,
aa5b4fbc
MK
1461 "htt rx addba tid %hu peer_id %hu size %hhu\n",
1462 tid, peer_id, ev->window_size);
1463
1464 spin_lock_bh(&ar->data_lock);
1465 peer = ath10k_peer_find_by_id(ar, peer_id);
1466 if (!peer) {
7aa7a72a 1467 ath10k_warn(ar, "received addba event for invalid peer_id: %hu\n",
aa5b4fbc
MK
1468 peer_id);
1469 spin_unlock_bh(&ar->data_lock);
1470 return;
1471 }
1472
1473 arvif = ath10k_get_arvif(ar, peer->vdev_id);
1474 if (!arvif) {
7aa7a72a 1475 ath10k_warn(ar, "received addba event for invalid vdev_id: %u\n",
aa5b4fbc
MK
1476 peer->vdev_id);
1477 spin_unlock_bh(&ar->data_lock);
1478 return;
1479 }
1480
7aa7a72a 1481 ath10k_dbg(ar, ATH10K_DBG_HTT,
aa5b4fbc
MK
1482 "htt rx start rx ba session sta %pM tid %hu size %hhu\n",
1483 peer->addr, tid, ev->window_size);
1484
1485 ieee80211_start_rx_ba_session_offl(arvif->vif, peer->addr, tid);
1486 spin_unlock_bh(&ar->data_lock);
1487}
1488
1489static void ath10k_htt_rx_delba(struct ath10k *ar, struct htt_resp *resp)
1490{
1491 struct htt_rx_delba *ev = &resp->rx_delba;
1492 struct ath10k_peer *peer;
1493 struct ath10k_vif *arvif;
1494 u16 info0, tid, peer_id;
1495
1496 info0 = __le16_to_cpu(ev->info0);
1497 tid = MS(info0, HTT_RX_BA_INFO0_TID);
1498 peer_id = MS(info0, HTT_RX_BA_INFO0_PEER_ID);
1499
7aa7a72a 1500 ath10k_dbg(ar, ATH10K_DBG_HTT,
aa5b4fbc
MK
1501 "htt rx delba tid %hu peer_id %hu\n",
1502 tid, peer_id);
1503
1504 spin_lock_bh(&ar->data_lock);
1505 peer = ath10k_peer_find_by_id(ar, peer_id);
1506 if (!peer) {
7aa7a72a 1507 ath10k_warn(ar, "received addba event for invalid peer_id: %hu\n",
aa5b4fbc
MK
1508 peer_id);
1509 spin_unlock_bh(&ar->data_lock);
1510 return;
1511 }
1512
1513 arvif = ath10k_get_arvif(ar, peer->vdev_id);
1514 if (!arvif) {
7aa7a72a 1515 ath10k_warn(ar, "received addba event for invalid vdev_id: %u\n",
aa5b4fbc
MK
1516 peer->vdev_id);
1517 spin_unlock_bh(&ar->data_lock);
1518 return;
1519 }
1520
7aa7a72a 1521 ath10k_dbg(ar, ATH10K_DBG_HTT,
aa5b4fbc
MK
1522 "htt rx stop rx ba session sta %pM tid %hu\n",
1523 peer->addr, tid);
1524
1525 ieee80211_stop_rx_ba_session_offl(arvif->vif, peer->addr, tid);
1526 spin_unlock_bh(&ar->data_lock);
1527}
1528
5e3dd157
KV
1529void ath10k_htt_t2h_msg_handler(struct ath10k *ar, struct sk_buff *skb)
1530{
edb8236d 1531 struct ath10k_htt *htt = &ar->htt;
5e3dd157
KV
1532 struct htt_resp *resp = (struct htt_resp *)skb->data;
1533
1534 /* confirm alignment */
1535 if (!IS_ALIGNED((unsigned long)skb->data, 4))
7aa7a72a 1536 ath10k_warn(ar, "unaligned htt message, expect trouble\n");
5e3dd157 1537
7aa7a72a 1538 ath10k_dbg(ar, ATH10K_DBG_HTT, "htt rx, msg_type: 0x%0X\n",
5e3dd157
KV
1539 resp->hdr.msg_type);
1540 switch (resp->hdr.msg_type) {
1541 case HTT_T2H_MSG_TYPE_VERSION_CONF: {
1542 htt->target_version_major = resp->ver_resp.major;
1543 htt->target_version_minor = resp->ver_resp.minor;
1544 complete(&htt->target_version_received);
1545 break;
1546 }
6c5151a9 1547 case HTT_T2H_MSG_TYPE_RX_IND:
45967089
MK
1548 spin_lock_bh(&htt->rx_ring.lock);
1549 __skb_queue_tail(&htt->rx_compl_q, skb);
1550 spin_unlock_bh(&htt->rx_ring.lock);
6c5151a9
MK
1551 tasklet_schedule(&htt->txrx_compl_task);
1552 return;
5e3dd157
KV
1553 case HTT_T2H_MSG_TYPE_PEER_MAP: {
1554 struct htt_peer_map_event ev = {
1555 .vdev_id = resp->peer_map.vdev_id,
1556 .peer_id = __le16_to_cpu(resp->peer_map.peer_id),
1557 };
1558 memcpy(ev.addr, resp->peer_map.addr, sizeof(ev.addr));
1559 ath10k_peer_map_event(htt, &ev);
1560 break;
1561 }
1562 case HTT_T2H_MSG_TYPE_PEER_UNMAP: {
1563 struct htt_peer_unmap_event ev = {
1564 .peer_id = __le16_to_cpu(resp->peer_unmap.peer_id),
1565 };
1566 ath10k_peer_unmap_event(htt, &ev);
1567 break;
1568 }
1569 case HTT_T2H_MSG_TYPE_MGMT_TX_COMPLETION: {
1570 struct htt_tx_done tx_done = {};
1571 int status = __le32_to_cpu(resp->mgmt_tx_completion.status);
1572
1573 tx_done.msdu_id =
1574 __le32_to_cpu(resp->mgmt_tx_completion.desc_id);
1575
1576 switch (status) {
1577 case HTT_MGMT_TX_STATUS_OK:
1578 break;
1579 case HTT_MGMT_TX_STATUS_RETRY:
1580 tx_done.no_ack = true;
1581 break;
1582 case HTT_MGMT_TX_STATUS_DROP:
1583 tx_done.discard = true;
1584 break;
1585 }
1586
6c5151a9 1587 spin_lock_bh(&htt->tx_lock);
0a89f8a0 1588 ath10k_txrx_tx_unref(htt, &tx_done);
6c5151a9 1589 spin_unlock_bh(&htt->tx_lock);
5e3dd157
KV
1590 break;
1591 }
6c5151a9
MK
1592 case HTT_T2H_MSG_TYPE_TX_COMPL_IND:
1593 spin_lock_bh(&htt->tx_lock);
1594 __skb_queue_tail(&htt->tx_compl_q, skb);
1595 spin_unlock_bh(&htt->tx_lock);
1596 tasklet_schedule(&htt->txrx_compl_task);
1597 return;
5e3dd157
KV
1598 case HTT_T2H_MSG_TYPE_SEC_IND: {
1599 struct ath10k *ar = htt->ar;
1600 struct htt_security_indication *ev = &resp->security_indication;
1601
7aa7a72a 1602 ath10k_dbg(ar, ATH10K_DBG_HTT,
5e3dd157
KV
1603 "sec ind peer_id %d unicast %d type %d\n",
1604 __le16_to_cpu(ev->peer_id),
1605 !!(ev->flags & HTT_SECURITY_IS_UNICAST),
1606 MS(ev->flags, HTT_SECURITY_TYPE));
1607 complete(&ar->install_key_done);
1608 break;
1609 }
1610 case HTT_T2H_MSG_TYPE_RX_FRAG_IND: {
7aa7a72a 1611 ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt event: ",
5e3dd157
KV
1612 skb->data, skb->len);
1613 ath10k_htt_rx_frag_handler(htt, &resp->rx_frag_ind);
1614 break;
1615 }
1616 case HTT_T2H_MSG_TYPE_TEST:
1617 /* FIX THIS */
1618 break;
5e3dd157 1619 case HTT_T2H_MSG_TYPE_STATS_CONF:
d35a6c18 1620 trace_ath10k_htt_stats(ar, skb->data, skb->len);
a9bf0506
KV
1621 break;
1622 case HTT_T2H_MSG_TYPE_TX_INSPECT_IND:
708b9bde
MK
1623 /* Firmware can return tx frames if it's unable to fully
1624 * process them and suspects host may be able to fix it. ath10k
1625 * sends all tx frames as already inspected so this shouldn't
1626 * happen unless fw has a bug.
1627 */
7aa7a72a 1628 ath10k_warn(ar, "received an unexpected htt tx inspect event\n");
708b9bde 1629 break;
5e3dd157 1630 case HTT_T2H_MSG_TYPE_RX_ADDBA:
aa5b4fbc
MK
1631 ath10k_htt_rx_addba(ar, resp);
1632 break;
5e3dd157 1633 case HTT_T2H_MSG_TYPE_RX_DELBA:
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MK
1634 ath10k_htt_rx_delba(ar, resp);
1635 break;
bfdd7937
RM
1636 case HTT_T2H_MSG_TYPE_PKTLOG: {
1637 struct ath10k_pktlog_hdr *hdr =
1638 (struct ath10k_pktlog_hdr *)resp->pktlog_msg.payload;
1639
1640 trace_ath10k_htt_pktlog(ar, resp->pktlog_msg.payload,
1641 sizeof(*hdr) +
1642 __le16_to_cpu(hdr->size));
1643 break;
1644 }
aa5b4fbc
MK
1645 case HTT_T2H_MSG_TYPE_RX_FLUSH: {
1646 /* Ignore this event because mac80211 takes care of Rx
1647 * aggregation reordering.
1648 */
1649 break;
1650 }
5e3dd157 1651 default:
2358a544
MK
1652 ath10k_warn(ar, "htt event (%d) not handled\n",
1653 resp->hdr.msg_type);
7aa7a72a 1654 ath10k_dbg_dump(ar, ATH10K_DBG_HTT_DUMP, NULL, "htt event: ",
5e3dd157
KV
1655 skb->data, skb->len);
1656 break;
1657 };
1658
1659 /* Free the indication buffer */
1660 dev_kfree_skb_any(skb);
1661}
6c5151a9
MK
1662
1663static void ath10k_htt_txrx_compl_task(unsigned long ptr)
1664{
1665 struct ath10k_htt *htt = (struct ath10k_htt *)ptr;
1666 struct htt_resp *resp;
1667 struct sk_buff *skb;
1668
45967089
MK
1669 spin_lock_bh(&htt->tx_lock);
1670 while ((skb = __skb_dequeue(&htt->tx_compl_q))) {
6c5151a9
MK
1671 ath10k_htt_rx_frm_tx_compl(htt->ar, skb);
1672 dev_kfree_skb_any(skb);
1673 }
45967089 1674 spin_unlock_bh(&htt->tx_lock);
6c5151a9 1675
45967089
MK
1676 spin_lock_bh(&htt->rx_ring.lock);
1677 while ((skb = __skb_dequeue(&htt->rx_compl_q))) {
6c5151a9
MK
1678 resp = (struct htt_resp *)skb->data;
1679 ath10k_htt_rx_handler(htt, &resp->rx_ind);
1680 dev_kfree_skb_any(skb);
1681 }
45967089 1682 spin_unlock_bh(&htt->rx_ring.lock);
6c5151a9 1683}