[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / ath / ath10k / hw.h

/*
 * Copyright (c) 2005-2011 Atheros Communications Inc.
 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

#ifndef _HW_H_
#define _HW_H_

#include "targaddrs.h"

#define ATH10K_FW_DIR			"ath10k"

/* QCA988X 1.0 definitions (unsupported) */
#define QCA988X_HW_1_0_CHIP_ID_REV	0x0

/* QCA988X 2.0 definitions */
#define QCA988X_HW_2_0_VERSION		0x4100016c
#define QCA988X_HW_2_0_CHIP_ID_REV	0x2
#define QCA988X_HW_2_0_FW_DIR		ATH10K_FW_DIR "/QCA988X/hw2.0"
#define QCA988X_HW_2_0_FW_FILE		"firmware.bin"
#define QCA988X_HW_2_0_OTP_FILE		"otp.bin"
#define QCA988X_HW_2_0_BOARD_DATA_FILE	"board.bin"
#define QCA988X_HW_2_0_PATCH_LOAD_ADDR	0x1234

/* QCA6174 target BMI version signatures */
#define QCA6174_HW_1_0_VERSION		0x05000000
#define QCA6174_HW_1_1_VERSION		0x05000001
#define QCA6174_HW_1_3_VERSION		0x05000003
#define QCA6174_HW_2_1_VERSION		0x05010000
#define QCA6174_HW_3_0_VERSION		0x05020000
#define QCA6174_HW_3_2_VERSION		0x05030000

enum qca6174_pci_rev {
	QCA6174_PCI_REV_1_1 = 0x11,
	QCA6174_PCI_REV_1_3 = 0x13,
	QCA6174_PCI_REV_2_0 = 0x20,
	QCA6174_PCI_REV_3_0 = 0x30,
};

enum qca6174_chip_id_rev {
	QCA6174_HW_1_0_CHIP_ID_REV = 0,
	QCA6174_HW_1_1_CHIP_ID_REV = 1,
	QCA6174_HW_1_3_CHIP_ID_REV = 2,
	QCA6174_HW_2_1_CHIP_ID_REV = 4,
	QCA6174_HW_2_2_CHIP_ID_REV = 5,
	QCA6174_HW_3_0_CHIP_ID_REV = 8,
	QCA6174_HW_3_1_CHIP_ID_REV = 9,
	QCA6174_HW_3_2_CHIP_ID_REV = 10,
};

#define QCA6174_HW_2_1_FW_DIR		"ath10k/QCA6174/hw2.1"
#define QCA6174_HW_2_1_FW_FILE		"firmware.bin"
#define QCA6174_HW_2_1_OTP_FILE		"otp.bin"
#define QCA6174_HW_2_1_BOARD_DATA_FILE	"board.bin"
#define QCA6174_HW_2_1_PATCH_LOAD_ADDR	0x1234

#define QCA6174_HW_3_0_FW_DIR		"ath10k/QCA6174/hw3.0"
#define QCA6174_HW_3_0_FW_FILE		"firmware.bin"
#define QCA6174_HW_3_0_OTP_FILE		"otp.bin"
#define QCA6174_HW_3_0_BOARD_DATA_FILE	"board.bin"
#define QCA6174_HW_3_0_PATCH_LOAD_ADDR	0x1234

#define ATH10K_FW_API2_FILE		"firmware-2.bin"
#define ATH10K_FW_API3_FILE		"firmware-3.bin"

/* added support for ATH10K_FW_IE_WMI_OP_VERSION */
#define ATH10K_FW_API4_FILE		"firmware-4.bin"

/* HTT id conflict fix for management frames over HTT */
#define ATH10K_FW_API5_FILE		"firmware-5.bin"

#define ATH10K_FW_UTF_FILE		"utf.bin"

/* includes also the null byte */
#define ATH10K_FIRMWARE_MAGIC               "QCA-ATH10K"

#define REG_DUMP_COUNT_QCA988X 60

#define QCA988X_CAL_DATA_LEN		2116

struct ath10k_fw_ie {
	__le32 id;
	__le32 len;
	u8 data[0];
};

enum ath10k_fw_ie_type {
	ATH10K_FW_IE_FW_VERSION = 0,
	ATH10K_FW_IE_TIMESTAMP = 1,
	ATH10K_FW_IE_FEATURES = 2,
	ATH10K_FW_IE_FW_IMAGE = 3,
	ATH10K_FW_IE_OTP_IMAGE = 4,

	/* WMI "operations" interface version, 32 bit value. Supported from
	 * FW API 4 and above.
	 */
	ATH10K_FW_IE_WMI_OP_VERSION = 5,

	/* HTT "operations" interface version, 32 bit value. Supported from
	 * FW API 5 and above.
	 */
	ATH10K_FW_IE_HTT_OP_VERSION = 6,
};

enum ath10k_fw_wmi_op_version {
	ATH10K_FW_WMI_OP_VERSION_UNSET = 0,

	ATH10K_FW_WMI_OP_VERSION_MAIN = 1,
	ATH10K_FW_WMI_OP_VERSION_10_1 = 2,
	ATH10K_FW_WMI_OP_VERSION_10_2 = 3,
	ATH10K_FW_WMI_OP_VERSION_TLV = 4,
	ATH10K_FW_WMI_OP_VERSION_10_2_4 = 5,

	/* keep last */
	ATH10K_FW_WMI_OP_VERSION_MAX,
};

enum ath10k_fw_htt_op_version {
	ATH10K_FW_HTT_OP_VERSION_UNSET = 0,

	ATH10K_FW_HTT_OP_VERSION_MAIN = 1,

	/* also used in 10.2 and 10.2.4 branches */
	ATH10K_FW_HTT_OP_VERSION_10_1 = 2,

	ATH10K_FW_HTT_OP_VERSION_TLV = 3,

	/* keep last */
	ATH10K_FW_HTT_OP_VERSION_MAX,
};

enum ath10k_hw_rev {
	ATH10K_HW_QCA988X,
	ATH10K_HW_QCA6174,
};

struct ath10k_hw_regs {
	u32 rtc_state_cold_reset_mask;
	u32 rtc_soc_base_address;
	u32 rtc_wmac_base_address;
	u32 soc_core_base_address;
	u32 ce_wrapper_base_address;
	u32 ce0_base_address;
	u32 ce1_base_address;
	u32 ce2_base_address;
	u32 ce3_base_address;
	u32 ce4_base_address;
	u32 ce5_base_address;
	u32 ce6_base_address;
	u32 ce7_base_address;
	u32 soc_reset_control_si0_rst_mask;
	u32 soc_reset_control_ce_rst_mask;
	u32 soc_chip_id_address;
	u32 scratch_3_address;
};

extern const struct ath10k_hw_regs qca988x_regs;
extern const struct ath10k_hw_regs qca6174_regs;

#define QCA_REV_988X(ar) ((ar)->hw_rev == ATH10K_HW_QCA988X)
#define QCA_REV_6174(ar) ((ar)->hw_rev == ATH10K_HW_QCA6174)

/* Known pecularities:
 *  - current FW doesn't support raw rx mode (last tested v599)
 *  - current FW dumps upon raw tx mode (last tested v599)
 *  - raw appears in nwifi decap, raw and nwifi appear in ethernet decap
 *  - raw have FCS, nwifi doesn't
 *  - ethernet frames have 802.11 header decapped and parts (base hdr, cipher
 *    param, llc/snap) are aligned to 4byte boundaries each */
enum ath10k_hw_txrx_mode {
	ATH10K_HW_TXRX_RAW = 0,
	ATH10K_HW_TXRX_NATIVE_WIFI = 1,
	ATH10K_HW_TXRX_ETHERNET = 2,

	/* Valid for HTT >= 3.0. Used for management frames in TX_FRM. */
	ATH10K_HW_TXRX_MGMT = 3,
};

enum ath10k_mcast2ucast_mode {
	ATH10K_MCAST2UCAST_DISABLED = 0,
	ATH10K_MCAST2UCAST_ENABLED = 1,
};

struct ath10k_pktlog_hdr {
	__le16 flags;
	__le16 missed_cnt;
	__le16 log_type;
	__le16 size;
	__le32 timestamp;
	u8 payload[0];
} __packed;

/* Target specific defines for MAIN firmware */
#define TARGET_NUM_VDEVS			8
#define TARGET_NUM_PEER_AST			2
#define TARGET_NUM_WDS_ENTRIES			32
#define TARGET_DMA_BURST_SIZE			0
#define TARGET_MAC_AGGR_DELIM			0
#define TARGET_AST_SKID_LIMIT			16
#define TARGET_NUM_STATIONS			16
#define TARGET_NUM_PEERS			((TARGET_NUM_STATIONS) + \
						 (TARGET_NUM_VDEVS))
#define TARGET_NUM_OFFLOAD_PEERS		0
#define TARGET_NUM_OFFLOAD_REORDER_BUFS         0
#define TARGET_NUM_PEER_KEYS			2
#define TARGET_NUM_TIDS				((TARGET_NUM_PEERS) * 2)
#define TARGET_TX_CHAIN_MASK			(BIT(0) | BIT(1) | BIT(2))
#define TARGET_RX_CHAIN_MASK			(BIT(0) | BIT(1) | BIT(2))
#define TARGET_RX_TIMEOUT_LO_PRI		100
#define TARGET_RX_TIMEOUT_HI_PRI		40

/* Native Wifi decap mode is used to align IP frames to 4-byte boundaries and
 * avoid a very expensive re-alignment in mac80211. */
#define TARGET_RX_DECAP_MODE			ATH10K_HW_TXRX_NATIVE_WIFI

#define TARGET_SCAN_MAX_PENDING_REQS		4
#define TARGET_BMISS_OFFLOAD_MAX_VDEV		3
#define TARGET_ROAM_OFFLOAD_MAX_VDEV		3
#define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES	8
#define TARGET_GTK_OFFLOAD_MAX_VDEV		3
#define TARGET_NUM_MCAST_GROUPS			0
#define TARGET_NUM_MCAST_TABLE_ELEMS		0
#define TARGET_MCAST2UCAST_MODE			ATH10K_MCAST2UCAST_DISABLED
#define TARGET_TX_DBG_LOG_SIZE			1024
#define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0
#define TARGET_VOW_CONFIG			0
#define TARGET_NUM_MSDU_DESC			(1024 + 400)
#define TARGET_MAX_FRAG_ENTRIES			0

/* Target specific defines for 10.X firmware */
#define TARGET_10X_NUM_VDEVS			16
#define TARGET_10X_NUM_PEER_AST			2
#define TARGET_10X_NUM_WDS_ENTRIES		32
#define TARGET_10X_DMA_BURST_SIZE		0
#define TARGET_10X_MAC_AGGR_DELIM		0
#define TARGET_10X_AST_SKID_LIMIT		128
#define TARGET_10X_NUM_STATIONS			128
#define TARGET_10X_NUM_PEERS			((TARGET_10X_NUM_STATIONS) + \
						 (TARGET_10X_NUM_VDEVS))
#define TARGET_10X_NUM_OFFLOAD_PEERS		0
#define TARGET_10X_NUM_OFFLOAD_REORDER_BUFS	0
#define TARGET_10X_NUM_PEER_KEYS		2
#define TARGET_10X_NUM_TIDS_MAX			256
#define TARGET_10X_NUM_TIDS			min((TARGET_10X_NUM_TIDS_MAX), \
						    (TARGET_10X_NUM_PEERS) * 2)
#define TARGET_10X_TX_CHAIN_MASK		(BIT(0) | BIT(1) | BIT(2))
#define TARGET_10X_RX_CHAIN_MASK		(BIT(0) | BIT(1) | BIT(2))
#define TARGET_10X_RX_TIMEOUT_LO_PRI		100
#define TARGET_10X_RX_TIMEOUT_HI_PRI		40
#define TARGET_10X_RX_DECAP_MODE		ATH10K_HW_TXRX_NATIVE_WIFI
#define TARGET_10X_SCAN_MAX_PENDING_REQS	4
#define TARGET_10X_BMISS_OFFLOAD_MAX_VDEV	2
#define TARGET_10X_ROAM_OFFLOAD_MAX_VDEV	2
#define TARGET_10X_ROAM_OFFLOAD_MAX_AP_PROFILES	8
#define TARGET_10X_GTK_OFFLOAD_MAX_VDEV		3
#define TARGET_10X_NUM_MCAST_GROUPS		0
#define TARGET_10X_NUM_MCAST_TABLE_ELEMS	0
#define TARGET_10X_MCAST2UCAST_MODE		ATH10K_MCAST2UCAST_DISABLED
#define TARGET_10X_TX_DBG_LOG_SIZE		1024
#define TARGET_10X_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1
#define TARGET_10X_VOW_CONFIG			0
#define TARGET_10X_NUM_MSDU_DESC		(1024 + 400)
#define TARGET_10X_MAX_FRAG_ENTRIES		0

/* 10.2 parameters */
#define TARGET_10_2_DMA_BURST_SIZE		1

/* Target specific defines for WMI-TLV firmware */
#define TARGET_TLV_NUM_VDEVS			3
#define TARGET_TLV_NUM_STATIONS			32
#define TARGET_TLV_NUM_PEERS			((TARGET_TLV_NUM_STATIONS) + \
						 (TARGET_TLV_NUM_VDEVS) + \
						 2)
#define TARGET_TLV_NUM_TDLS_VDEVS		1
#define TARGET_TLV_NUM_TIDS			((TARGET_TLV_NUM_PEERS) * 2)
#define TARGET_TLV_NUM_MSDU_DESC		(1024 + 32)
#define TARGET_TLV_NUM_WOW_PATTERNS		22

/* Number of Copy Engines supported */
#define CE_COUNT 8

/*
 * Total number of PCIe MSI interrupts requested for all interrupt sources.
 * PCIe standard forces this to be a power of 2.
 * Some Host OS's limit MSI requests that can be granted to 8
 * so for now we abide by this limit and avoid requesting more
 * than that.
 */
#define MSI_NUM_REQUEST_LOG2	3
#define MSI_NUM_REQUEST		(1<<MSI_NUM_REQUEST_LOG2)

/*
 * Granted MSIs are assigned as follows:
 * Firmware uses the first
 * Remaining MSIs, if any, are used by Copy Engines
 * This mapping is known to both Target firmware and Host software.
 * It may be changed as long as Host and Target are kept in sync.
 */
/* MSI for firmware (errors, etc.) */
#define MSI_ASSIGN_FW		0

/* MSIs for Copy Engines */
#define MSI_ASSIGN_CE_INITIAL	1
#define MSI_ASSIGN_CE_MAX	7

/* as of IP3.7.1 */
#define RTC_STATE_V_ON				3

#define RTC_STATE_COLD_RESET_MASK		ar->regs->rtc_state_cold_reset_mask
#define RTC_STATE_V_LSB				0
#define RTC_STATE_V_MASK			0x00000007
#define RTC_STATE_ADDRESS			0x0000
#define PCIE_SOC_WAKE_V_MASK			0x00000001
#define PCIE_SOC_WAKE_ADDRESS			0x0004
#define PCIE_SOC_WAKE_RESET			0x00000000
#define SOC_GLOBAL_RESET_ADDRESS		0x0008

#define RTC_SOC_BASE_ADDRESS			ar->regs->rtc_soc_base_address
#define RTC_WMAC_BASE_ADDRESS			ar->regs->rtc_wmac_base_address
#define MAC_COEX_BASE_ADDRESS			0x00006000
#define BT_COEX_BASE_ADDRESS			0x00007000
#define SOC_PCIE_BASE_ADDRESS			0x00008000
#define SOC_CORE_BASE_ADDRESS			ar->regs->soc_core_base_address
#define WLAN_UART_BASE_ADDRESS			0x0000c000
#define WLAN_SI_BASE_ADDRESS			0x00010000
#define WLAN_GPIO_BASE_ADDRESS			0x00014000
#define WLAN_ANALOG_INTF_BASE_ADDRESS		0x0001c000
#define WLAN_MAC_BASE_ADDRESS			0x00020000
#define EFUSE_BASE_ADDRESS			0x00030000
#define FPGA_REG_BASE_ADDRESS			0x00039000
#define WLAN_UART2_BASE_ADDRESS			0x00054c00
#define CE_WRAPPER_BASE_ADDRESS			ar->regs->ce_wrapper_base_address
#define CE0_BASE_ADDRESS			ar->regs->ce0_base_address
#define CE1_BASE_ADDRESS			ar->regs->ce1_base_address
#define CE2_BASE_ADDRESS			ar->regs->ce2_base_address
#define CE3_BASE_ADDRESS			ar->regs->ce3_base_address
#define CE4_BASE_ADDRESS			ar->regs->ce4_base_address
#define CE5_BASE_ADDRESS			ar->regs->ce5_base_address
#define CE6_BASE_ADDRESS			ar->regs->ce6_base_address
#define CE7_BASE_ADDRESS			ar->regs->ce7_base_address
#define DBI_BASE_ADDRESS			0x00060000
#define WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS	0x0006c000
#define PCIE_LOCAL_BASE_ADDRESS			0x00080000

#define SOC_RESET_CONTROL_ADDRESS		0x00000000
#define SOC_RESET_CONTROL_OFFSET		0x00000000
#define SOC_RESET_CONTROL_SI0_RST_MASK		ar->regs->soc_reset_control_si0_rst_mask
#define SOC_RESET_CONTROL_CE_RST_MASK		ar->regs->soc_reset_control_ce_rst_mask
#define SOC_RESET_CONTROL_CPU_WARM_RST_MASK	0x00000040
#define SOC_CPU_CLOCK_OFFSET			0x00000020
#define SOC_CPU_CLOCK_STANDARD_LSB		0
#define SOC_CPU_CLOCK_STANDARD_MASK		0x00000003
#define SOC_CLOCK_CONTROL_OFFSET		0x00000028
#define SOC_CLOCK_CONTROL_SI0_CLK_MASK		0x00000001
#define SOC_SYSTEM_SLEEP_OFFSET			0x000000c4
#define SOC_LPO_CAL_OFFSET			0x000000e0
#define SOC_LPO_CAL_ENABLE_LSB			20
#define SOC_LPO_CAL_ENABLE_MASK			0x00100000
#define SOC_LF_TIMER_CONTROL0_ADDRESS		0x00000050
#define SOC_LF_TIMER_CONTROL0_ENABLE_MASK	0x00000004

#define SOC_CHIP_ID_ADDRESS			ar->regs->soc_chip_id_address
#define SOC_CHIP_ID_REV_LSB			8
#define SOC_CHIP_ID_REV_MASK			0x00000f00

#define WLAN_RESET_CONTROL_COLD_RST_MASK	0x00000008
#define WLAN_RESET_CONTROL_WARM_RST_MASK	0x00000004
#define WLAN_SYSTEM_SLEEP_DISABLE_LSB		0
#define WLAN_SYSTEM_SLEEP_DISABLE_MASK		0x00000001

#define WLAN_GPIO_PIN0_ADDRESS			0x00000028
#define WLAN_GPIO_PIN0_CONFIG_MASK		0x00007800
#define WLAN_GPIO_PIN1_ADDRESS			0x0000002c
#define WLAN_GPIO_PIN1_CONFIG_MASK		0x00007800
#define WLAN_GPIO_PIN10_ADDRESS			0x00000050
#define WLAN_GPIO_PIN11_ADDRESS			0x00000054
#define WLAN_GPIO_PIN12_ADDRESS			0x00000058
#define WLAN_GPIO_PIN13_ADDRESS			0x0000005c

#define CLOCK_GPIO_OFFSET			0xffffffff
#define CLOCK_GPIO_BT_CLK_OUT_EN_LSB		0
#define CLOCK_GPIO_BT_CLK_OUT_EN_MASK		0

#define SI_CONFIG_OFFSET			0x00000000
#define SI_CONFIG_BIDIR_OD_DATA_LSB		18
#define SI_CONFIG_BIDIR_OD_DATA_MASK		0x00040000
#define SI_CONFIG_I2C_LSB			16
#define SI_CONFIG_I2C_MASK			0x00010000
#define SI_CONFIG_POS_SAMPLE_LSB		7
#define SI_CONFIG_POS_SAMPLE_MASK		0x00000080
#define SI_CONFIG_INACTIVE_DATA_LSB		5
#define SI_CONFIG_INACTIVE_DATA_MASK		0x00000020
#define SI_CONFIG_INACTIVE_CLK_LSB		4
#define SI_CONFIG_INACTIVE_CLK_MASK		0x00000010
#define SI_CONFIG_DIVIDER_LSB			0
#define SI_CONFIG_DIVIDER_MASK			0x0000000f
#define SI_CS_OFFSET				0x00000004
#define SI_CS_DONE_ERR_MASK			0x00000400
#define SI_CS_DONE_INT_MASK			0x00000200
#define SI_CS_START_LSB				8
#define SI_CS_START_MASK			0x00000100
#define SI_CS_RX_CNT_LSB			4
#define SI_CS_RX_CNT_MASK			0x000000f0
#define SI_CS_TX_CNT_LSB			0
#define SI_CS_TX_CNT_MASK			0x0000000f

#define SI_TX_DATA0_OFFSET			0x00000008
#define SI_TX_DATA1_OFFSET			0x0000000c
#define SI_RX_DATA0_OFFSET			0x00000010
#define SI_RX_DATA1_OFFSET			0x00000014

#define CORE_CTRL_CPU_INTR_MASK			0x00002000
#define CORE_CTRL_PCIE_REG_31_MASK		0x00000800
#define CORE_CTRL_ADDRESS			0x0000
#define PCIE_INTR_ENABLE_ADDRESS		0x0008
#define PCIE_INTR_CAUSE_ADDRESS			0x000c
#define PCIE_INTR_CLR_ADDRESS			0x0014
#define SCRATCH_3_ADDRESS			ar->regs->scratch_3_address
#define CPU_INTR_ADDRESS			0x0010

/* Firmware indications to the Host via SCRATCH_3 register. */
#define FW_INDICATOR_ADDRESS	(SOC_CORE_BASE_ADDRESS + SCRATCH_3_ADDRESS)
#define FW_IND_EVENT_PENDING			1
#define FW_IND_INITIALIZED			2

/* HOST_REG interrupt from firmware */
#define PCIE_INTR_FIRMWARE_MASK			0x00000400
#define PCIE_INTR_CE_MASK_ALL			0x0007f800

#define DRAM_BASE_ADDRESS			0x00400000

#define MISSING 0

#define SYSTEM_SLEEP_OFFSET			SOC_SYSTEM_SLEEP_OFFSET
#define WLAN_SYSTEM_SLEEP_OFFSET		SOC_SYSTEM_SLEEP_OFFSET
#define WLAN_RESET_CONTROL_OFFSET		SOC_RESET_CONTROL_OFFSET
#define CLOCK_CONTROL_OFFSET			SOC_CLOCK_CONTROL_OFFSET
#define CLOCK_CONTROL_SI0_CLK_MASK		SOC_CLOCK_CONTROL_SI0_CLK_MASK
#define RESET_CONTROL_MBOX_RST_MASK		MISSING
#define RESET_CONTROL_SI0_RST_MASK		SOC_RESET_CONTROL_SI0_RST_MASK
#define GPIO_BASE_ADDRESS			WLAN_GPIO_BASE_ADDRESS
#define GPIO_PIN0_OFFSET			WLAN_GPIO_PIN0_ADDRESS
#define GPIO_PIN1_OFFSET			WLAN_GPIO_PIN1_ADDRESS
#define GPIO_PIN0_CONFIG_MASK			WLAN_GPIO_PIN0_CONFIG_MASK
#define GPIO_PIN1_CONFIG_MASK			WLAN_GPIO_PIN1_CONFIG_MASK
#define SI_BASE_ADDRESS				WLAN_SI_BASE_ADDRESS
#define SCRATCH_BASE_ADDRESS			SOC_CORE_BASE_ADDRESS
#define LOCAL_SCRATCH_OFFSET			0x18
#define CPU_CLOCK_OFFSET			SOC_CPU_CLOCK_OFFSET
#define LPO_CAL_OFFSET				SOC_LPO_CAL_OFFSET
#define GPIO_PIN10_OFFSET			WLAN_GPIO_PIN10_ADDRESS
#define GPIO_PIN11_OFFSET			WLAN_GPIO_PIN11_ADDRESS
#define GPIO_PIN12_OFFSET			WLAN_GPIO_PIN12_ADDRESS
#define GPIO_PIN13_OFFSET			WLAN_GPIO_PIN13_ADDRESS
#define CPU_CLOCK_STANDARD_LSB			SOC_CPU_CLOCK_STANDARD_LSB
#define CPU_CLOCK_STANDARD_MASK			SOC_CPU_CLOCK_STANDARD_MASK
#define LPO_CAL_ENABLE_LSB			SOC_LPO_CAL_ENABLE_LSB
#define LPO_CAL_ENABLE_MASK			SOC_LPO_CAL_ENABLE_MASK
#define ANALOG_INTF_BASE_ADDRESS		WLAN_ANALOG_INTF_BASE_ADDRESS
#define MBOX_BASE_ADDRESS			MISSING
#define INT_STATUS_ENABLE_ERROR_LSB		MISSING
#define INT_STATUS_ENABLE_ERROR_MASK		MISSING
#define INT_STATUS_ENABLE_CPU_LSB		MISSING
#define INT_STATUS_ENABLE_CPU_MASK		MISSING
#define INT_STATUS_ENABLE_COUNTER_LSB		MISSING
#define INT_STATUS_ENABLE_COUNTER_MASK		MISSING
#define INT_STATUS_ENABLE_MBOX_DATA_LSB		MISSING
#define INT_STATUS_ENABLE_MBOX_DATA_MASK	MISSING
#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB	MISSING
#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK	MISSING
#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB	MISSING
#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK	MISSING
#define COUNTER_INT_STATUS_ENABLE_BIT_LSB	MISSING
#define COUNTER_INT_STATUS_ENABLE_BIT_MASK	MISSING
#define INT_STATUS_ENABLE_ADDRESS		MISSING
#define CPU_INT_STATUS_ENABLE_BIT_LSB		MISSING
#define CPU_INT_STATUS_ENABLE_BIT_MASK		MISSING
#define HOST_INT_STATUS_ADDRESS			MISSING
#define CPU_INT_STATUS_ADDRESS			MISSING
#define ERROR_INT_STATUS_ADDRESS		MISSING
#define ERROR_INT_STATUS_WAKEUP_MASK		MISSING
#define ERROR_INT_STATUS_WAKEUP_LSB		MISSING
#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK	MISSING
#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB	MISSING
#define ERROR_INT_STATUS_TX_OVERFLOW_MASK	MISSING
#define ERROR_INT_STATUS_TX_OVERFLOW_LSB	MISSING
#define COUNT_DEC_ADDRESS			MISSING
#define HOST_INT_STATUS_CPU_MASK		MISSING
#define HOST_INT_STATUS_CPU_LSB			MISSING
#define HOST_INT_STATUS_ERROR_MASK		MISSING
#define HOST_INT_STATUS_ERROR_LSB		MISSING
#define HOST_INT_STATUS_COUNTER_MASK		MISSING
#define HOST_INT_STATUS_COUNTER_LSB		MISSING
#define RX_LOOKAHEAD_VALID_ADDRESS		MISSING
#define WINDOW_DATA_ADDRESS			MISSING
#define WINDOW_READ_ADDR_ADDRESS		MISSING
#define WINDOW_WRITE_ADDR_ADDRESS		MISSING

#define RTC_STATE_V_GET(x) (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB)

#endif /* _HW_H_ */
Commit	Line	Data
5e3dd157 KV	1	/*
	2	* Copyright (c) 2005-2011 Atheros Communications Inc.
	3	* Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
	4	*
	5	* Permission to use, copy, modify, and/or distribute this software for any
	6	* purpose with or without fee is hereby granted, provided that the above
	7	* copyright notice and this permission notice appear in all copies.
	8	*
	9	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	10	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	11	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
	12	* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	13	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
	14	* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
	15	* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	16	*/
	17
	18	#ifndef _HW_H_
	19	#define _HW_H_
	20
	21	#include "targaddrs.h"
	22
a58227ef KV	23	#define ATH10K_FW_DIR "ath10k"
a58227ef KV	24
e01ae68c KV	25	/* QCA988X 1.0 definitions (unsupported) */
	26	#define QCA988X_HW_1_0_CHIP_ID_REV 0x0
	27
5e3dd157 KV	28	/* QCA988X 2.0 definitions */
5e3dd157 KV	29	#define QCA988X_HW_2_0_VERSION 0x4100016c
e01ae68c	30	#define QCA988X_HW_2_0_CHIP_ID_REV 0x2
a58227ef	31	#define QCA988X_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA988X/hw2.0"
5e3dd157 KV	32	#define QCA988X_HW_2_0_FW_FILE "firmware.bin"
	33	#define QCA988X_HW_2_0_OTP_FILE "otp.bin"
	34	#define QCA988X_HW_2_0_BOARD_DATA_FILE "board.bin"
	35	#define QCA988X_HW_2_0_PATCH_LOAD_ADDR 0x1234
	36
d63955b3 MK	37	/* QCA6174 target BMI version signatures */
	38	#define QCA6174_HW_1_0_VERSION 0x05000000
	39	#define QCA6174_HW_1_1_VERSION 0x05000001
	40	#define QCA6174_HW_1_3_VERSION 0x05000003
	41	#define QCA6174_HW_2_1_VERSION 0x05010000
	42	#define QCA6174_HW_3_0_VERSION 0x05020000
608b8f73	43	#define QCA6174_HW_3_2_VERSION 0x05030000
d63955b3 MK	44
	45	enum qca6174_pci_rev {
	46	QCA6174_PCI_REV_1_1 = 0x11,
	47	QCA6174_PCI_REV_1_3 = 0x13,
	48	QCA6174_PCI_REV_2_0 = 0x20,
	49	QCA6174_PCI_REV_3_0 = 0x30,
	50	};
	51
	52	enum qca6174_chip_id_rev {
	53	QCA6174_HW_1_0_CHIP_ID_REV = 0,
	54	QCA6174_HW_1_1_CHIP_ID_REV = 1,
	55	QCA6174_HW_1_3_CHIP_ID_REV = 2,
	56	QCA6174_HW_2_1_CHIP_ID_REV = 4,
	57	QCA6174_HW_2_2_CHIP_ID_REV = 5,
	58	QCA6174_HW_3_0_CHIP_ID_REV = 8,
	59	QCA6174_HW_3_1_CHIP_ID_REV = 9,
	60	QCA6174_HW_3_2_CHIP_ID_REV = 10,
	61	};
	62
	63	#define QCA6174_HW_2_1_FW_DIR "ath10k/QCA6174/hw2.1"
	64	#define QCA6174_HW_2_1_FW_FILE "firmware.bin"
	65	#define QCA6174_HW_2_1_OTP_FILE "otp.bin"
	66	#define QCA6174_HW_2_1_BOARD_DATA_FILE "board.bin"
	67	#define QCA6174_HW_2_1_PATCH_LOAD_ADDR 0x1234
	68
	69	#define QCA6174_HW_3_0_FW_DIR "ath10k/QCA6174/hw3.0"
	70	#define QCA6174_HW_3_0_FW_FILE "firmware.bin"
	71	#define QCA6174_HW_3_0_OTP_FILE "otp.bin"
	72	#define QCA6174_HW_3_0_BOARD_DATA_FILE "board.bin"
	73	#define QCA6174_HW_3_0_PATCH_LOAD_ADDR 0x1234
	74
1a222435	75	#define ATH10K_FW_API2_FILE "firmware-2.bin"
24c88f78	76	#define ATH10K_FW_API3_FILE "firmware-3.bin"
1a222435	77
4a16fbec RM	78	/* added support for ATH10K_FW_IE_WMI_OP_VERSION */
	79	#define ATH10K_FW_API4_FILE "firmware-4.bin"
	80
53513c30 KV	81	/* HTT id conflict fix for management frames over HTT */
	82	#define ATH10K_FW_API5_FILE "firmware-5.bin"
	83
43d2a30f KV	84	#define ATH10K_FW_UTF_FILE "utf.bin"
43d2a30f KV	85
1a222435 KV	86	/* includes also the null byte */
	87	#define ATH10K_FIRMWARE_MAGIC "QCA-ATH10K"
	88
384914b2 BG	89	#define REG_DUMP_COUNT_QCA988X 60
384914b2 BG	90
7869b4fa KV	91	#define QCA988X_CAL_DATA_LEN 2116
7869b4fa KV	92
1a222435 KV	93	struct ath10k_fw_ie {
	94	__le32 id;
	95	__le32 len;
	96	u8 data[0];
	97	};
	98
	99	enum ath10k_fw_ie_type {
	100	ATH10K_FW_IE_FW_VERSION = 0,
	101	ATH10K_FW_IE_TIMESTAMP = 1,
	102	ATH10K_FW_IE_FEATURES = 2,
	103	ATH10K_FW_IE_FW_IMAGE = 3,
	104	ATH10K_FW_IE_OTP_IMAGE = 4,
202e86e6 KV	105
	106	/* WMI "operations" interface version, 32 bit value. Supported from
	107	* FW API 4 and above.
	108	*/
	109	ATH10K_FW_IE_WMI_OP_VERSION = 5,
8348db29 RM	110
	111	/* HTT "operations" interface version, 32 bit value. Supported from
	112	* FW API 5 and above.
	113	*/
	114	ATH10K_FW_IE_HTT_OP_VERSION = 6,
202e86e6 KV	115	};
	116
	117	enum ath10k_fw_wmi_op_version {
	118	ATH10K_FW_WMI_OP_VERSION_UNSET = 0,
	119
	120	ATH10K_FW_WMI_OP_VERSION_MAIN = 1,
	121	ATH10K_FW_WMI_OP_VERSION_10_1 = 2,
	122	ATH10K_FW_WMI_OP_VERSION_10_2 = 3,
ca996ec5	123	ATH10K_FW_WMI_OP_VERSION_TLV = 4,
4a16fbec	124	ATH10K_FW_WMI_OP_VERSION_10_2_4 = 5,
202e86e6 KV	125
	126	/* keep last */
	127	ATH10K_FW_WMI_OP_VERSION_MAX,
1a222435 KV	128	};
1a222435 KV	129
8348db29 RM	130	enum ath10k_fw_htt_op_version {
	131	ATH10K_FW_HTT_OP_VERSION_UNSET = 0,
	132
	133	ATH10K_FW_HTT_OP_VERSION_MAIN = 1,
	134
	135	/* also used in 10.2 and 10.2.4 branches */
	136	ATH10K_FW_HTT_OP_VERSION_10_1 = 2,
	137
	138	ATH10K_FW_HTT_OP_VERSION_TLV = 3,
	139
	140	/* keep last */
	141	ATH10K_FW_HTT_OP_VERSION_MAX,
	142	};
	143
d63955b3 MK	144	enum ath10k_hw_rev {
	145	ATH10K_HW_QCA988X,
	146	ATH10K_HW_QCA6174,
	147	};
	148
	149	struct ath10k_hw_regs {
	150	u32 rtc_state_cold_reset_mask;
	151	u32 rtc_soc_base_address;
	152	u32 rtc_wmac_base_address;
	153	u32 soc_core_base_address;
	154	u32 ce_wrapper_base_address;
	155	u32 ce0_base_address;
	156	u32 ce1_base_address;
	157	u32 ce2_base_address;
	158	u32 ce3_base_address;
	159	u32 ce4_base_address;
	160	u32 ce5_base_address;
	161	u32 ce6_base_address;
	162	u32 ce7_base_address;
	163	u32 soc_reset_control_si0_rst_mask;
	164	u32 soc_reset_control_ce_rst_mask;
	165	u32 soc_chip_id_address;
	166	u32 scratch_3_address;
	167	};
	168
	169	extern const struct ath10k_hw_regs qca988x_regs;
	170	extern const struct ath10k_hw_regs qca6174_regs;
	171
	172	#define QCA_REV_988X(ar) ((ar)->hw_rev == ATH10K_HW_QCA988X)
	173	#define QCA_REV_6174(ar) ((ar)->hw_rev == ATH10K_HW_QCA6174)
	174
5e3dd157 KV	175	/* Known pecularities:
	176	* - current FW doesn't support raw rx mode (last tested v599)
	177	* - current FW dumps upon raw tx mode (last tested v599)
	178	* - raw appears in nwifi decap, raw and nwifi appear in ethernet decap
	179	* - raw have FCS, nwifi doesn't
	180	* - ethernet frames have 802.11 header decapped and parts (base hdr, cipher
	181	* param, llc/snap) are aligned to 4byte boundaries each */
	182	enum ath10k_hw_txrx_mode {
	183	ATH10K_HW_TXRX_RAW = 0,
	184	ATH10K_HW_TXRX_NATIVE_WIFI = 1,
	185	ATH10K_HW_TXRX_ETHERNET = 2,
961d4c38 MK	186
	187	/* Valid for HTT >= 3.0. Used for management frames in TX_FRM. */
	188	ATH10K_HW_TXRX_MGMT = 3,
5e3dd157 KV	189	};
	190
	191	enum ath10k_mcast2ucast_mode {
	192	ATH10K_MCAST2UCAST_DISABLED = 0,
	193	ATH10K_MCAST2UCAST_ENABLED = 1,
	194	};
	195
bfdd7937 RM	196	struct ath10k_pktlog_hdr {
	197	__le16 flags;
	198	__le16 missed_cnt;
	199	__le16 log_type;
	200	__le16 size;
	201	__le32 timestamp;
	202	u8 payload[0];
	203	} __packed;
	204
ec6a73f0	205	/* Target specific defines for MAIN firmware */
5e3dd157 KV	206	#define TARGET_NUM_VDEVS 8
	207	#define TARGET_NUM_PEER_AST 2
	208	#define TARGET_NUM_WDS_ENTRIES 32
	209	#define TARGET_DMA_BURST_SIZE 0
	210	#define TARGET_MAC_AGGR_DELIM 0
	211	#define TARGET_AST_SKID_LIMIT 16
cfd1061e MK	212	#define TARGET_NUM_STATIONS 16
	213	#define TARGET_NUM_PEERS ((TARGET_NUM_STATIONS) + \
	214	(TARGET_NUM_VDEVS))
5e3dd157 KV	215	#define TARGET_NUM_OFFLOAD_PEERS 0
	216	#define TARGET_NUM_OFFLOAD_REORDER_BUFS 0
	217	#define TARGET_NUM_PEER_KEYS 2
cfd1061e	218	#define TARGET_NUM_TIDS ((TARGET_NUM_PEERS) * 2)
5e3dd157 KV	219	#define TARGET_TX_CHAIN_MASK (BIT(0) \| BIT(1) \| BIT(2))
	220	#define TARGET_RX_CHAIN_MASK (BIT(0) \| BIT(1) \| BIT(2))
	221	#define TARGET_RX_TIMEOUT_LO_PRI 100
	222	#define TARGET_RX_TIMEOUT_HI_PRI 40
4d316c79 MK	223
	224	/* Native Wifi decap mode is used to align IP frames to 4-byte boundaries and
	225	* avoid a very expensive re-alignment in mac80211. */
	226	#define TARGET_RX_DECAP_MODE ATH10K_HW_TXRX_NATIVE_WIFI
	227
5e3dd157 KV	228	#define TARGET_SCAN_MAX_PENDING_REQS 4
	229	#define TARGET_BMISS_OFFLOAD_MAX_VDEV 3
	230	#define TARGET_ROAM_OFFLOAD_MAX_VDEV 3
	231	#define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 8
	232	#define TARGET_GTK_OFFLOAD_MAX_VDEV 3
	233	#define TARGET_NUM_MCAST_GROUPS 0
	234	#define TARGET_NUM_MCAST_TABLE_ELEMS 0
	235	#define TARGET_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED
	236	#define TARGET_TX_DBG_LOG_SIZE 1024
	237	#define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0
	238	#define TARGET_VOW_CONFIG 0
	239	#define TARGET_NUM_MSDU_DESC (1024 + 400)
	240	#define TARGET_MAX_FRAG_ENTRIES 0
	241
ec6a73f0 BM	242	/* Target specific defines for 10.X firmware */
	243	#define TARGET_10X_NUM_VDEVS 16
	244	#define TARGET_10X_NUM_PEER_AST 2
	245	#define TARGET_10X_NUM_WDS_ENTRIES 32
	246	#define TARGET_10X_DMA_BURST_SIZE 0
	247	#define TARGET_10X_MAC_AGGR_DELIM 0
b24af141	248	#define TARGET_10X_AST_SKID_LIMIT 128
cfd1061e MK	249	#define TARGET_10X_NUM_STATIONS 128
	250	#define TARGET_10X_NUM_PEERS ((TARGET_10X_NUM_STATIONS) + \
	251	(TARGET_10X_NUM_VDEVS))
ec6a73f0 BM	252	#define TARGET_10X_NUM_OFFLOAD_PEERS 0
	253	#define TARGET_10X_NUM_OFFLOAD_REORDER_BUFS 0
	254	#define TARGET_10X_NUM_PEER_KEYS 2
cfd1061e MK	255	#define TARGET_10X_NUM_TIDS_MAX 256
	256	#define TARGET_10X_NUM_TIDS min((TARGET_10X_NUM_TIDS_MAX), \
	257	(TARGET_10X_NUM_PEERS) * 2)
ec6a73f0 BM	258	#define TARGET_10X_TX_CHAIN_MASK (BIT(0) \| BIT(1) \| BIT(2))
	259	#define TARGET_10X_RX_CHAIN_MASK (BIT(0) \| BIT(1) \| BIT(2))
	260	#define TARGET_10X_RX_TIMEOUT_LO_PRI 100
	261	#define TARGET_10X_RX_TIMEOUT_HI_PRI 40
0d1a28f2	262	#define TARGET_10X_RX_DECAP_MODE ATH10K_HW_TXRX_NATIVE_WIFI
ec6a73f0 BM	263	#define TARGET_10X_SCAN_MAX_PENDING_REQS 4
	264	#define TARGET_10X_BMISS_OFFLOAD_MAX_VDEV 2
	265	#define TARGET_10X_ROAM_OFFLOAD_MAX_VDEV 2
	266	#define TARGET_10X_ROAM_OFFLOAD_MAX_AP_PROFILES 8
	267	#define TARGET_10X_GTK_OFFLOAD_MAX_VDEV 3
	268	#define TARGET_10X_NUM_MCAST_GROUPS 0
	269	#define TARGET_10X_NUM_MCAST_TABLE_ELEMS 0
	270	#define TARGET_10X_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED
	271	#define TARGET_10X_TX_DBG_LOG_SIZE 1024
	272	#define TARGET_10X_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1
	273	#define TARGET_10X_VOW_CONFIG 0
	274	#define TARGET_10X_NUM_MSDU_DESC (1024 + 400)
	275	#define TARGET_10X_MAX_FRAG_ENTRIES 0
5e3dd157	276
f6603ff2 SM	277	/* 10.2 parameters */
	278	#define TARGET_10_2_DMA_BURST_SIZE 1
	279
ca996ec5 MK	280	/* Target specific defines for WMI-TLV firmware */
	281	#define TARGET_TLV_NUM_VDEVS 3
	282	#define TARGET_TLV_NUM_STATIONS 32
	283	#define TARGET_TLV_NUM_PEERS ((TARGET_TLV_NUM_STATIONS) + \
	284	(TARGET_TLV_NUM_VDEVS) + \
	285	2)
8cca3d60	286	#define TARGET_TLV_NUM_TDLS_VDEVS 1
ca996ec5 MK	287	#define TARGET_TLV_NUM_TIDS ((TARGET_TLV_NUM_PEERS) * 2)
ca996ec5 MK	288	#define TARGET_TLV_NUM_MSDU_DESC (1024 + 32)
25c86619	289	#define TARGET_TLV_NUM_WOW_PATTERNS 22
ca996ec5	290
5e3dd157 KV	291	/* Number of Copy Engines supported */
	292	#define CE_COUNT 8
	293
	294	/*
	295	* Total number of PCIe MSI interrupts requested for all interrupt sources.
	296	* PCIe standard forces this to be a power of 2.
	297	* Some Host OS's limit MSI requests that can be granted to 8
	298	* so for now we abide by this limit and avoid requesting more
	299	* than that.
	300	*/
	301	#define MSI_NUM_REQUEST_LOG2 3
	302	#define MSI_NUM_REQUEST (1<<MSI_NUM_REQUEST_LOG2)
	303
	304	/*
	305	* Granted MSIs are assigned as follows:
	306	* Firmware uses the first
	307	* Remaining MSIs, if any, are used by Copy Engines
	308	* This mapping is known to both Target firmware and Host software.
	309	* It may be changed as long as Host and Target are kept in sync.
	310	*/
	311	/* MSI for firmware (errors, etc.) */
	312	#define MSI_ASSIGN_FW 0
	313
	314	/* MSIs for Copy Engines */
	315	#define MSI_ASSIGN_CE_INITIAL 1
	316	#define MSI_ASSIGN_CE_MAX 7
	317
	318	/* as of IP3.7.1 */
	319	#define RTC_STATE_V_ON 3
	320
d63955b3	321	#define RTC_STATE_COLD_RESET_MASK ar->regs->rtc_state_cold_reset_mask
5e3dd157 KV	322	#define RTC_STATE_V_LSB 0
	323	#define RTC_STATE_V_MASK 0x00000007
	324	#define RTC_STATE_ADDRESS 0x0000
	325	#define PCIE_SOC_WAKE_V_MASK 0x00000001
	326	#define PCIE_SOC_WAKE_ADDRESS 0x0004
	327	#define PCIE_SOC_WAKE_RESET 0x00000000
	328	#define SOC_GLOBAL_RESET_ADDRESS 0x0008
	329
d63955b3 MK	330	#define RTC_SOC_BASE_ADDRESS ar->regs->rtc_soc_base_address
d63955b3 MK	331	#define RTC_WMAC_BASE_ADDRESS ar->regs->rtc_wmac_base_address
5e3dd157 KV	332	#define MAC_COEX_BASE_ADDRESS 0x00006000
	333	#define BT_COEX_BASE_ADDRESS 0x00007000
	334	#define SOC_PCIE_BASE_ADDRESS 0x00008000
d63955b3	335	#define SOC_CORE_BASE_ADDRESS ar->regs->soc_core_base_address
5e3dd157 KV	336	#define WLAN_UART_BASE_ADDRESS 0x0000c000
	337	#define WLAN_SI_BASE_ADDRESS 0x00010000
	338	#define WLAN_GPIO_BASE_ADDRESS 0x00014000
	339	#define WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000
	340	#define WLAN_MAC_BASE_ADDRESS 0x00020000
	341	#define EFUSE_BASE_ADDRESS 0x00030000
	342	#define FPGA_REG_BASE_ADDRESS 0x00039000
	343	#define WLAN_UART2_BASE_ADDRESS 0x00054c00
d63955b3 MK	344	#define CE_WRAPPER_BASE_ADDRESS ar->regs->ce_wrapper_base_address
	345	#define CE0_BASE_ADDRESS ar->regs->ce0_base_address
	346	#define CE1_BASE_ADDRESS ar->regs->ce1_base_address
	347	#define CE2_BASE_ADDRESS ar->regs->ce2_base_address
	348	#define CE3_BASE_ADDRESS ar->regs->ce3_base_address
	349	#define CE4_BASE_ADDRESS ar->regs->ce4_base_address
	350	#define CE5_BASE_ADDRESS ar->regs->ce5_base_address
	351	#define CE6_BASE_ADDRESS ar->regs->ce6_base_address
	352	#define CE7_BASE_ADDRESS ar->regs->ce7_base_address
5e3dd157 KV	353	#define DBI_BASE_ADDRESS 0x00060000
	354	#define WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS 0x0006c000
	355	#define PCIE_LOCAL_BASE_ADDRESS 0x00080000
	356
fc36e3ff	357	#define SOC_RESET_CONTROL_ADDRESS 0x00000000
5e3dd157	358	#define SOC_RESET_CONTROL_OFFSET 0x00000000
d63955b3 MK	359	#define SOC_RESET_CONTROL_SI0_RST_MASK ar->regs->soc_reset_control_si0_rst_mask
d63955b3 MK	360	#define SOC_RESET_CONTROL_CE_RST_MASK ar->regs->soc_reset_control_ce_rst_mask
fc36e3ff	361	#define SOC_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040
5e3dd157 KV	362	#define SOC_CPU_CLOCK_OFFSET 0x00000020
	363	#define SOC_CPU_CLOCK_STANDARD_LSB 0
	364	#define SOC_CPU_CLOCK_STANDARD_MASK 0x00000003
	365	#define SOC_CLOCK_CONTROL_OFFSET 0x00000028
	366	#define SOC_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001
	367	#define SOC_SYSTEM_SLEEP_OFFSET 0x000000c4
	368	#define SOC_LPO_CAL_OFFSET 0x000000e0
	369	#define SOC_LPO_CAL_ENABLE_LSB 20
	370	#define SOC_LPO_CAL_ENABLE_MASK 0x00100000
fc36e3ff MK	371	#define SOC_LF_TIMER_CONTROL0_ADDRESS 0x00000050
fc36e3ff MK	372	#define SOC_LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004
5e3dd157	373
d63955b3	374	#define SOC_CHIP_ID_ADDRESS ar->regs->soc_chip_id_address
e01ae68c KV	375	#define SOC_CHIP_ID_REV_LSB 8
	376	#define SOC_CHIP_ID_REV_MASK 0x00000f00
	377
5e3dd157 KV	378	#define WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000008
	379	#define WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000004
	380	#define WLAN_SYSTEM_SLEEP_DISABLE_LSB 0
	381	#define WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001
	382
	383	#define WLAN_GPIO_PIN0_ADDRESS 0x00000028
	384	#define WLAN_GPIO_PIN0_CONFIG_MASK 0x00007800
	385	#define WLAN_GPIO_PIN1_ADDRESS 0x0000002c
	386	#define WLAN_GPIO_PIN1_CONFIG_MASK 0x00007800
	387	#define WLAN_GPIO_PIN10_ADDRESS 0x00000050
	388	#define WLAN_GPIO_PIN11_ADDRESS 0x00000054
	389	#define WLAN_GPIO_PIN12_ADDRESS 0x00000058
	390	#define WLAN_GPIO_PIN13_ADDRESS 0x0000005c
	391
	392	#define CLOCK_GPIO_OFFSET 0xffffffff
	393	#define CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0
	394	#define CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0
	395
	396	#define SI_CONFIG_OFFSET 0x00000000
	397	#define SI_CONFIG_BIDIR_OD_DATA_LSB 18
	398	#define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000
	399	#define SI_CONFIG_I2C_LSB 16
	400	#define SI_CONFIG_I2C_MASK 0x00010000
	401	#define SI_CONFIG_POS_SAMPLE_LSB 7
	402	#define SI_CONFIG_POS_SAMPLE_MASK 0x00000080
	403	#define SI_CONFIG_INACTIVE_DATA_LSB 5
	404	#define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020
	405	#define SI_CONFIG_INACTIVE_CLK_LSB 4
	406	#define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010
	407	#define SI_CONFIG_DIVIDER_LSB 0
	408	#define SI_CONFIG_DIVIDER_MASK 0x0000000f
	409	#define SI_CS_OFFSET 0x00000004
	410	#define SI_CS_DONE_ERR_MASK 0x00000400
	411	#define SI_CS_DONE_INT_MASK 0x00000200
	412	#define SI_CS_START_LSB 8
	413	#define SI_CS_START_MASK 0x00000100
	414	#define SI_CS_RX_CNT_LSB 4
	415	#define SI_CS_RX_CNT_MASK 0x000000f0
	416	#define SI_CS_TX_CNT_LSB 0
	417	#define SI_CS_TX_CNT_MASK 0x0000000f
	418
	419	#define SI_TX_DATA0_OFFSET 0x00000008
	420	#define SI_TX_DATA1_OFFSET 0x0000000c
	421	#define SI_RX_DATA0_OFFSET 0x00000010
	422	#define SI_RX_DATA1_OFFSET 0x00000014
	423
	424	#define CORE_CTRL_CPU_INTR_MASK 0x00002000
7c0f0e3c	425	#define CORE_CTRL_PCIE_REG_31_MASK 0x00000800
5e3dd157 KV	426	#define CORE_CTRL_ADDRESS 0x0000
5e3dd157 KV	427	#define PCIE_INTR_ENABLE_ADDRESS 0x0008
e539887b	428	#define PCIE_INTR_CAUSE_ADDRESS 0x000c
5e3dd157	429	#define PCIE_INTR_CLR_ADDRESS 0x0014
d63955b3	430	#define SCRATCH_3_ADDRESS ar->regs->scratch_3_address
fc36e3ff	431	#define CPU_INTR_ADDRESS 0x0010
5e3dd157 KV	432
	433	/* Firmware indications to the Host via SCRATCH_3 register. */
	434	#define FW_INDICATOR_ADDRESS (SOC_CORE_BASE_ADDRESS + SCRATCH_3_ADDRESS)
	435	#define FW_IND_EVENT_PENDING 1
	436	#define FW_IND_INITIALIZED 2
	437
	438	/* HOST_REG interrupt from firmware */
	439	#define PCIE_INTR_FIRMWARE_MASK 0x00000400
	440	#define PCIE_INTR_CE_MASK_ALL 0x0007f800
	441
	442	#define DRAM_BASE_ADDRESS 0x00400000
	443
	444	#define MISSING 0
	445
	446	#define SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET
	447	#define WLAN_SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET
	448	#define WLAN_RESET_CONTROL_OFFSET SOC_RESET_CONTROL_OFFSET
	449	#define CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_OFFSET
	450	#define CLOCK_CONTROL_SI0_CLK_MASK SOC_CLOCK_CONTROL_SI0_CLK_MASK
	451	#define RESET_CONTROL_MBOX_RST_MASK MISSING
	452	#define RESET_CONTROL_SI0_RST_MASK SOC_RESET_CONTROL_SI0_RST_MASK
	453	#define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS
	454	#define GPIO_PIN0_OFFSET WLAN_GPIO_PIN0_ADDRESS
	455	#define GPIO_PIN1_OFFSET WLAN_GPIO_PIN1_ADDRESS
	456	#define GPIO_PIN0_CONFIG_MASK WLAN_GPIO_PIN0_CONFIG_MASK
	457	#define GPIO_PIN1_CONFIG_MASK WLAN_GPIO_PIN1_CONFIG_MASK
	458	#define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS
	459	#define SCRATCH_BASE_ADDRESS SOC_CORE_BASE_ADDRESS
	460	#define LOCAL_SCRATCH_OFFSET 0x18
	461	#define CPU_CLOCK_OFFSET SOC_CPU_CLOCK_OFFSET
	462	#define LPO_CAL_OFFSET SOC_LPO_CAL_OFFSET
	463	#define GPIO_PIN10_OFFSET WLAN_GPIO_PIN10_ADDRESS
	464	#define GPIO_PIN11_OFFSET WLAN_GPIO_PIN11_ADDRESS
	465	#define GPIO_PIN12_OFFSET WLAN_GPIO_PIN12_ADDRESS
	466	#define GPIO_PIN13_OFFSET WLAN_GPIO_PIN13_ADDRESS
	467	#define CPU_CLOCK_STANDARD_LSB SOC_CPU_CLOCK_STANDARD_LSB
	468	#define CPU_CLOCK_STANDARD_MASK SOC_CPU_CLOCK_STANDARD_MASK
	469	#define LPO_CAL_ENABLE_LSB SOC_LPO_CAL_ENABLE_LSB
	470	#define LPO_CAL_ENABLE_MASK SOC_LPO_CAL_ENABLE_MASK
	471	#define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS
	472	#define MBOX_BASE_ADDRESS MISSING
	473	#define INT_STATUS_ENABLE_ERROR_LSB MISSING
	474	#define INT_STATUS_ENABLE_ERROR_MASK MISSING
	475	#define INT_STATUS_ENABLE_CPU_LSB MISSING
	476	#define INT_STATUS_ENABLE_CPU_MASK MISSING
	477	#define INT_STATUS_ENABLE_COUNTER_LSB MISSING
	478	#define INT_STATUS_ENABLE_COUNTER_MASK MISSING
	479	#define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING
	480	#define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING
	481	#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING
	482	#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING
	483	#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING
	484	#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING
	485	#define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING
	486	#define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING
	487	#define INT_STATUS_ENABLE_ADDRESS MISSING
	488	#define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING
	489	#define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING
	490	#define HOST_INT_STATUS_ADDRESS MISSING
	491	#define CPU_INT_STATUS_ADDRESS MISSING
	492	#define ERROR_INT_STATUS_ADDRESS MISSING
	493	#define ERROR_INT_STATUS_WAKEUP_MASK MISSING
	494	#define ERROR_INT_STATUS_WAKEUP_LSB MISSING
	495	#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING
496	#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING
497	#define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING
498	#define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING
499	#define COUNT_DEC_ADDRESS MISSING
500	#define HOST_INT_STATUS_CPU_MASK MISSING
501	#define HOST_INT_STATUS_CPU_LSB MISSING
502	#define HOST_INT_STATUS_ERROR_MASK MISSING
503	#define HOST_INT_STATUS_ERROR_LSB MISSING
504	#define HOST_INT_STATUS_COUNTER_MASK MISSING
505	#define HOST_INT_STATUS_COUNTER_LSB MISSING
506	#define RX_LOOKAHEAD_VALID_ADDRESS MISSING
507	#define WINDOW_DATA_ADDRESS MISSING
508	#define WINDOW_READ_ADDR_ADDRESS MISSING
509	#define WINDOW_WRITE_ADDR_ADDRESS MISSING
510
511	#define RTC_STATE_V_GET(x) (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB)
512
513	#endif /* _HW_H_ */