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5e3dd157 KV |
1 | /* |
2 | * Copyright (c) 2005-2011 Atheros Communications Inc. | |
3 | * Copyright (c) 2011-2013 Qualcomm Atheros, Inc. | |
4 | * | |
5 | * Permission to use, copy, modify, and/or distribute this software for any | |
6 | * purpose with or without fee is hereby granted, provided that the above | |
7 | * copyright notice and this permission notice appear in all copies. | |
8 | * | |
9 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
10 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
11 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
12 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
13 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
14 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
15 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
16 | */ | |
17 | ||
18 | #ifndef _HW_H_ | |
19 | #define _HW_H_ | |
20 | ||
21 | #include "targaddrs.h" | |
22 | ||
a58227ef KV |
23 | #define ATH10K_FW_DIR "ath10k" |
24 | ||
e01ae68c KV |
25 | /* QCA988X 1.0 definitions (unsupported) */ |
26 | #define QCA988X_HW_1_0_CHIP_ID_REV 0x0 | |
27 | ||
5e3dd157 KV |
28 | /* QCA988X 2.0 definitions */ |
29 | #define QCA988X_HW_2_0_VERSION 0x4100016c | |
e01ae68c | 30 | #define QCA988X_HW_2_0_CHIP_ID_REV 0x2 |
a58227ef | 31 | #define QCA988X_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA988X/hw2.0" |
5e3dd157 KV |
32 | #define QCA988X_HW_2_0_FW_FILE "firmware.bin" |
33 | #define QCA988X_HW_2_0_OTP_FILE "otp.bin" | |
34 | #define QCA988X_HW_2_0_BOARD_DATA_FILE "board.bin" | |
35 | #define QCA988X_HW_2_0_PATCH_LOAD_ADDR 0x1234 | |
36 | ||
d63955b3 MK |
37 | /* QCA6174 target BMI version signatures */ |
38 | #define QCA6174_HW_1_0_VERSION 0x05000000 | |
39 | #define QCA6174_HW_1_1_VERSION 0x05000001 | |
40 | #define QCA6174_HW_1_3_VERSION 0x05000003 | |
41 | #define QCA6174_HW_2_1_VERSION 0x05010000 | |
42 | #define QCA6174_HW_3_0_VERSION 0x05020000 | |
608b8f73 | 43 | #define QCA6174_HW_3_2_VERSION 0x05030000 |
d63955b3 MK |
44 | |
45 | enum qca6174_pci_rev { | |
46 | QCA6174_PCI_REV_1_1 = 0x11, | |
47 | QCA6174_PCI_REV_1_3 = 0x13, | |
48 | QCA6174_PCI_REV_2_0 = 0x20, | |
49 | QCA6174_PCI_REV_3_0 = 0x30, | |
50 | }; | |
51 | ||
52 | enum qca6174_chip_id_rev { | |
53 | QCA6174_HW_1_0_CHIP_ID_REV = 0, | |
54 | QCA6174_HW_1_1_CHIP_ID_REV = 1, | |
55 | QCA6174_HW_1_3_CHIP_ID_REV = 2, | |
56 | QCA6174_HW_2_1_CHIP_ID_REV = 4, | |
57 | QCA6174_HW_2_2_CHIP_ID_REV = 5, | |
58 | QCA6174_HW_3_0_CHIP_ID_REV = 8, | |
59 | QCA6174_HW_3_1_CHIP_ID_REV = 9, | |
60 | QCA6174_HW_3_2_CHIP_ID_REV = 10, | |
61 | }; | |
62 | ||
63 | #define QCA6174_HW_2_1_FW_DIR "ath10k/QCA6174/hw2.1" | |
64 | #define QCA6174_HW_2_1_FW_FILE "firmware.bin" | |
65 | #define QCA6174_HW_2_1_OTP_FILE "otp.bin" | |
66 | #define QCA6174_HW_2_1_BOARD_DATA_FILE "board.bin" | |
67 | #define QCA6174_HW_2_1_PATCH_LOAD_ADDR 0x1234 | |
68 | ||
69 | #define QCA6174_HW_3_0_FW_DIR "ath10k/QCA6174/hw3.0" | |
70 | #define QCA6174_HW_3_0_FW_FILE "firmware.bin" | |
71 | #define QCA6174_HW_3_0_OTP_FILE "otp.bin" | |
72 | #define QCA6174_HW_3_0_BOARD_DATA_FILE "board.bin" | |
73 | #define QCA6174_HW_3_0_PATCH_LOAD_ADDR 0x1234 | |
74 | ||
8bd47021 VT |
75 | /* QCA99X0 1.0 definitions (unsupported) */ |
76 | #define QCA99X0_HW_1_0_CHIP_ID_REV 0x0 | |
77 | ||
78 | /* QCA99X0 2.0 definitions */ | |
79 | #define QCA99X0_HW_2_0_DEV_VERSION 0x01000000 | |
80 | #define QCA99X0_HW_2_0_CHIP_ID_REV 0x1 | |
81 | #define QCA99X0_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA99X0/hw2.0" | |
82 | #define QCA99X0_HW_2_0_FW_FILE "firmware.bin" | |
83 | #define QCA99X0_HW_2_0_OTP_FILE "otp.bin" | |
84 | #define QCA99X0_HW_2_0_BOARD_DATA_FILE "board.bin" | |
85 | #define QCA99X0_HW_2_0_PATCH_LOAD_ADDR 0x1234 | |
86 | ||
1a222435 | 87 | #define ATH10K_FW_API2_FILE "firmware-2.bin" |
24c88f78 | 88 | #define ATH10K_FW_API3_FILE "firmware-3.bin" |
1a222435 | 89 | |
4a16fbec RM |
90 | /* added support for ATH10K_FW_IE_WMI_OP_VERSION */ |
91 | #define ATH10K_FW_API4_FILE "firmware-4.bin" | |
92 | ||
53513c30 KV |
93 | /* HTT id conflict fix for management frames over HTT */ |
94 | #define ATH10K_FW_API5_FILE "firmware-5.bin" | |
95 | ||
43d2a30f KV |
96 | #define ATH10K_FW_UTF_FILE "utf.bin" |
97 | ||
1a222435 KV |
98 | /* includes also the null byte */ |
99 | #define ATH10K_FIRMWARE_MAGIC "QCA-ATH10K" | |
100 | ||
384914b2 BG |
101 | #define REG_DUMP_COUNT_QCA988X 60 |
102 | ||
7869b4fa KV |
103 | #define QCA988X_CAL_DATA_LEN 2116 |
104 | ||
1a222435 KV |
105 | struct ath10k_fw_ie { |
106 | __le32 id; | |
107 | __le32 len; | |
108 | u8 data[0]; | |
109 | }; | |
110 | ||
111 | enum ath10k_fw_ie_type { | |
112 | ATH10K_FW_IE_FW_VERSION = 0, | |
113 | ATH10K_FW_IE_TIMESTAMP = 1, | |
114 | ATH10K_FW_IE_FEATURES = 2, | |
115 | ATH10K_FW_IE_FW_IMAGE = 3, | |
116 | ATH10K_FW_IE_OTP_IMAGE = 4, | |
202e86e6 KV |
117 | |
118 | /* WMI "operations" interface version, 32 bit value. Supported from | |
119 | * FW API 4 and above. | |
120 | */ | |
121 | ATH10K_FW_IE_WMI_OP_VERSION = 5, | |
8348db29 RM |
122 | |
123 | /* HTT "operations" interface version, 32 bit value. Supported from | |
124 | * FW API 5 and above. | |
125 | */ | |
126 | ATH10K_FW_IE_HTT_OP_VERSION = 6, | |
202e86e6 KV |
127 | }; |
128 | ||
129 | enum ath10k_fw_wmi_op_version { | |
130 | ATH10K_FW_WMI_OP_VERSION_UNSET = 0, | |
131 | ||
132 | ATH10K_FW_WMI_OP_VERSION_MAIN = 1, | |
133 | ATH10K_FW_WMI_OP_VERSION_10_1 = 2, | |
134 | ATH10K_FW_WMI_OP_VERSION_10_2 = 3, | |
ca996ec5 | 135 | ATH10K_FW_WMI_OP_VERSION_TLV = 4, |
4a16fbec | 136 | ATH10K_FW_WMI_OP_VERSION_10_2_4 = 5, |
202e86e6 KV |
137 | |
138 | /* keep last */ | |
139 | ATH10K_FW_WMI_OP_VERSION_MAX, | |
1a222435 KV |
140 | }; |
141 | ||
8348db29 RM |
142 | enum ath10k_fw_htt_op_version { |
143 | ATH10K_FW_HTT_OP_VERSION_UNSET = 0, | |
144 | ||
145 | ATH10K_FW_HTT_OP_VERSION_MAIN = 1, | |
146 | ||
147 | /* also used in 10.2 and 10.2.4 branches */ | |
148 | ATH10K_FW_HTT_OP_VERSION_10_1 = 2, | |
149 | ||
150 | ATH10K_FW_HTT_OP_VERSION_TLV = 3, | |
151 | ||
152 | /* keep last */ | |
153 | ATH10K_FW_HTT_OP_VERSION_MAX, | |
154 | }; | |
155 | ||
d63955b3 MK |
156 | enum ath10k_hw_rev { |
157 | ATH10K_HW_QCA988X, | |
158 | ATH10K_HW_QCA6174, | |
8bd47021 | 159 | ATH10K_HW_QCA99X0, |
d63955b3 MK |
160 | }; |
161 | ||
162 | struct ath10k_hw_regs { | |
163 | u32 rtc_state_cold_reset_mask; | |
164 | u32 rtc_soc_base_address; | |
165 | u32 rtc_wmac_base_address; | |
166 | u32 soc_core_base_address; | |
167 | u32 ce_wrapper_base_address; | |
168 | u32 ce0_base_address; | |
169 | u32 ce1_base_address; | |
170 | u32 ce2_base_address; | |
171 | u32 ce3_base_address; | |
172 | u32 ce4_base_address; | |
173 | u32 ce5_base_address; | |
174 | u32 ce6_base_address; | |
175 | u32 ce7_base_address; | |
176 | u32 soc_reset_control_si0_rst_mask; | |
177 | u32 soc_reset_control_ce_rst_mask; | |
178 | u32 soc_chip_id_address; | |
179 | u32 scratch_3_address; | |
a521ee98 VT |
180 | u32 fw_indicator_address; |
181 | u32 pcie_local_base_address; | |
182 | u32 ce_wrap_intr_sum_host_msi_lsb; | |
183 | u32 ce_wrap_intr_sum_host_msi_mask; | |
184 | u32 pcie_intr_fw_mask; | |
185 | u32 pcie_intr_ce_mask_all; | |
186 | u32 pcie_intr_clr_address; | |
d63955b3 MK |
187 | }; |
188 | ||
189 | extern const struct ath10k_hw_regs qca988x_regs; | |
190 | extern const struct ath10k_hw_regs qca6174_regs; | |
8bd47021 | 191 | extern const struct ath10k_hw_regs qca99x0_regs; |
d63955b3 | 192 | |
2f2cfc4a VT |
193 | struct ath10k_hw_values { |
194 | u32 rtc_state_val_on; | |
195 | u8 ce_count; | |
196 | u8 msi_assign_ce_max; | |
197 | u8 num_target_ce_config_wlan; | |
198 | }; | |
199 | ||
200 | extern const struct ath10k_hw_values qca988x_values; | |
201 | extern const struct ath10k_hw_values qca6174_values; | |
8bd47021 | 202 | extern const struct ath10k_hw_values qca99x0_values; |
2f2cfc4a | 203 | |
587f7031 MK |
204 | void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey, |
205 | u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev); | |
206 | ||
d63955b3 MK |
207 | #define QCA_REV_988X(ar) ((ar)->hw_rev == ATH10K_HW_QCA988X) |
208 | #define QCA_REV_6174(ar) ((ar)->hw_rev == ATH10K_HW_QCA6174) | |
8bd47021 | 209 | #define QCA_REV_99X0(ar) ((ar)->hw_rev == ATH10K_HW_QCA99X0) |
d63955b3 | 210 | |
5e3dd157 KV |
211 | /* Known pecularities: |
212 | * - current FW doesn't support raw rx mode (last tested v599) | |
213 | * - current FW dumps upon raw tx mode (last tested v599) | |
214 | * - raw appears in nwifi decap, raw and nwifi appear in ethernet decap | |
215 | * - raw have FCS, nwifi doesn't | |
216 | * - ethernet frames have 802.11 header decapped and parts (base hdr, cipher | |
217 | * param, llc/snap) are aligned to 4byte boundaries each */ | |
218 | enum ath10k_hw_txrx_mode { | |
219 | ATH10K_HW_TXRX_RAW = 0, | |
220 | ATH10K_HW_TXRX_NATIVE_WIFI = 1, | |
221 | ATH10K_HW_TXRX_ETHERNET = 2, | |
961d4c38 MK |
222 | |
223 | /* Valid for HTT >= 3.0. Used for management frames in TX_FRM. */ | |
224 | ATH10K_HW_TXRX_MGMT = 3, | |
5e3dd157 KV |
225 | }; |
226 | ||
227 | enum ath10k_mcast2ucast_mode { | |
228 | ATH10K_MCAST2UCAST_DISABLED = 0, | |
229 | ATH10K_MCAST2UCAST_ENABLED = 1, | |
230 | }; | |
231 | ||
bfdd7937 RM |
232 | struct ath10k_pktlog_hdr { |
233 | __le16 flags; | |
234 | __le16 missed_cnt; | |
235 | __le16 log_type; | |
236 | __le16 size; | |
237 | __le32 timestamp; | |
238 | u8 payload[0]; | |
239 | } __packed; | |
240 | ||
6aa4cf1c MK |
241 | enum ath10k_hw_rate_ofdm { |
242 | ATH10K_HW_RATE_OFDM_48M = 0, | |
243 | ATH10K_HW_RATE_OFDM_24M, | |
244 | ATH10K_HW_RATE_OFDM_12M, | |
245 | ATH10K_HW_RATE_OFDM_6M, | |
246 | ATH10K_HW_RATE_OFDM_54M, | |
247 | ATH10K_HW_RATE_OFDM_36M, | |
248 | ATH10K_HW_RATE_OFDM_18M, | |
249 | ATH10K_HW_RATE_OFDM_9M, | |
250 | }; | |
251 | ||
252 | enum ath10k_hw_rate_cck { | |
253 | ATH10K_HW_RATE_CCK_LP_11M = 0, | |
254 | ATH10K_HW_RATE_CCK_LP_5_5M, | |
255 | ATH10K_HW_RATE_CCK_LP_2M, | |
256 | ATH10K_HW_RATE_CCK_LP_1M, | |
257 | ATH10K_HW_RATE_CCK_SP_11M, | |
258 | ATH10K_HW_RATE_CCK_SP_5_5M, | |
259 | ATH10K_HW_RATE_CCK_SP_2M, | |
260 | }; | |
261 | ||
ec6a73f0 | 262 | /* Target specific defines for MAIN firmware */ |
5e3dd157 KV |
263 | #define TARGET_NUM_VDEVS 8 |
264 | #define TARGET_NUM_PEER_AST 2 | |
265 | #define TARGET_NUM_WDS_ENTRIES 32 | |
266 | #define TARGET_DMA_BURST_SIZE 0 | |
267 | #define TARGET_MAC_AGGR_DELIM 0 | |
268 | #define TARGET_AST_SKID_LIMIT 16 | |
cfd1061e MK |
269 | #define TARGET_NUM_STATIONS 16 |
270 | #define TARGET_NUM_PEERS ((TARGET_NUM_STATIONS) + \ | |
271 | (TARGET_NUM_VDEVS)) | |
5e3dd157 KV |
272 | #define TARGET_NUM_OFFLOAD_PEERS 0 |
273 | #define TARGET_NUM_OFFLOAD_REORDER_BUFS 0 | |
274 | #define TARGET_NUM_PEER_KEYS 2 | |
cfd1061e | 275 | #define TARGET_NUM_TIDS ((TARGET_NUM_PEERS) * 2) |
5e3dd157 KV |
276 | #define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) |
277 | #define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) | |
278 | #define TARGET_RX_TIMEOUT_LO_PRI 100 | |
279 | #define TARGET_RX_TIMEOUT_HI_PRI 40 | |
4d316c79 MK |
280 | |
281 | /* Native Wifi decap mode is used to align IP frames to 4-byte boundaries and | |
282 | * avoid a very expensive re-alignment in mac80211. */ | |
283 | #define TARGET_RX_DECAP_MODE ATH10K_HW_TXRX_NATIVE_WIFI | |
284 | ||
5e3dd157 KV |
285 | #define TARGET_SCAN_MAX_PENDING_REQS 4 |
286 | #define TARGET_BMISS_OFFLOAD_MAX_VDEV 3 | |
287 | #define TARGET_ROAM_OFFLOAD_MAX_VDEV 3 | |
288 | #define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 8 | |
289 | #define TARGET_GTK_OFFLOAD_MAX_VDEV 3 | |
290 | #define TARGET_NUM_MCAST_GROUPS 0 | |
291 | #define TARGET_NUM_MCAST_TABLE_ELEMS 0 | |
292 | #define TARGET_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED | |
293 | #define TARGET_TX_DBG_LOG_SIZE 1024 | |
294 | #define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0 | |
295 | #define TARGET_VOW_CONFIG 0 | |
296 | #define TARGET_NUM_MSDU_DESC (1024 + 400) | |
297 | #define TARGET_MAX_FRAG_ENTRIES 0 | |
298 | ||
ec6a73f0 BM |
299 | /* Target specific defines for 10.X firmware */ |
300 | #define TARGET_10X_NUM_VDEVS 16 | |
301 | #define TARGET_10X_NUM_PEER_AST 2 | |
302 | #define TARGET_10X_NUM_WDS_ENTRIES 32 | |
303 | #define TARGET_10X_DMA_BURST_SIZE 0 | |
304 | #define TARGET_10X_MAC_AGGR_DELIM 0 | |
b24af141 | 305 | #define TARGET_10X_AST_SKID_LIMIT 128 |
cfd1061e MK |
306 | #define TARGET_10X_NUM_STATIONS 128 |
307 | #define TARGET_10X_NUM_PEERS ((TARGET_10X_NUM_STATIONS) + \ | |
308 | (TARGET_10X_NUM_VDEVS)) | |
ec6a73f0 BM |
309 | #define TARGET_10X_NUM_OFFLOAD_PEERS 0 |
310 | #define TARGET_10X_NUM_OFFLOAD_REORDER_BUFS 0 | |
311 | #define TARGET_10X_NUM_PEER_KEYS 2 | |
cfd1061e MK |
312 | #define TARGET_10X_NUM_TIDS_MAX 256 |
313 | #define TARGET_10X_NUM_TIDS min((TARGET_10X_NUM_TIDS_MAX), \ | |
314 | (TARGET_10X_NUM_PEERS) * 2) | |
ec6a73f0 BM |
315 | #define TARGET_10X_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) |
316 | #define TARGET_10X_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2)) | |
317 | #define TARGET_10X_RX_TIMEOUT_LO_PRI 100 | |
318 | #define TARGET_10X_RX_TIMEOUT_HI_PRI 40 | |
0d1a28f2 | 319 | #define TARGET_10X_RX_DECAP_MODE ATH10K_HW_TXRX_NATIVE_WIFI |
ec6a73f0 BM |
320 | #define TARGET_10X_SCAN_MAX_PENDING_REQS 4 |
321 | #define TARGET_10X_BMISS_OFFLOAD_MAX_VDEV 2 | |
322 | #define TARGET_10X_ROAM_OFFLOAD_MAX_VDEV 2 | |
323 | #define TARGET_10X_ROAM_OFFLOAD_MAX_AP_PROFILES 8 | |
324 | #define TARGET_10X_GTK_OFFLOAD_MAX_VDEV 3 | |
325 | #define TARGET_10X_NUM_MCAST_GROUPS 0 | |
326 | #define TARGET_10X_NUM_MCAST_TABLE_ELEMS 0 | |
327 | #define TARGET_10X_MCAST2UCAST_MODE ATH10K_MCAST2UCAST_DISABLED | |
328 | #define TARGET_10X_TX_DBG_LOG_SIZE 1024 | |
329 | #define TARGET_10X_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1 | |
330 | #define TARGET_10X_VOW_CONFIG 0 | |
331 | #define TARGET_10X_NUM_MSDU_DESC (1024 + 400) | |
332 | #define TARGET_10X_MAX_FRAG_ENTRIES 0 | |
5e3dd157 | 333 | |
f6603ff2 SM |
334 | /* 10.2 parameters */ |
335 | #define TARGET_10_2_DMA_BURST_SIZE 1 | |
336 | ||
ca996ec5 | 337 | /* Target specific defines for WMI-TLV firmware */ |
039a0051 | 338 | #define TARGET_TLV_NUM_VDEVS 4 |
ca996ec5 | 339 | #define TARGET_TLV_NUM_STATIONS 32 |
039a0051 | 340 | #define TARGET_TLV_NUM_PEERS 35 |
8cca3d60 | 341 | #define TARGET_TLV_NUM_TDLS_VDEVS 1 |
ca996ec5 MK |
342 | #define TARGET_TLV_NUM_TIDS ((TARGET_TLV_NUM_PEERS) * 2) |
343 | #define TARGET_TLV_NUM_MSDU_DESC (1024 + 32) | |
25c86619 | 344 | #define TARGET_TLV_NUM_WOW_PATTERNS 22 |
ca996ec5 | 345 | |
050af069 VT |
346 | /* Diagnostic Window */ |
347 | #define CE_DIAG_PIPE 7 | |
348 | ||
2f2cfc4a VT |
349 | #define NUM_TARGET_CE_CONFIG_WLAN ar->hw_values->num_target_ce_config_wlan |
350 | ||
5e3dd157 | 351 | /* Number of Copy Engines supported */ |
2f2cfc4a | 352 | #define CE_COUNT ar->hw_values->ce_count |
5e3dd157 KV |
353 | |
354 | /* | |
355 | * Total number of PCIe MSI interrupts requested for all interrupt sources. | |
356 | * PCIe standard forces this to be a power of 2. | |
357 | * Some Host OS's limit MSI requests that can be granted to 8 | |
358 | * so for now we abide by this limit and avoid requesting more | |
359 | * than that. | |
360 | */ | |
361 | #define MSI_NUM_REQUEST_LOG2 3 | |
362 | #define MSI_NUM_REQUEST (1<<MSI_NUM_REQUEST_LOG2) | |
363 | ||
364 | /* | |
365 | * Granted MSIs are assigned as follows: | |
366 | * Firmware uses the first | |
367 | * Remaining MSIs, if any, are used by Copy Engines | |
368 | * This mapping is known to both Target firmware and Host software. | |
369 | * It may be changed as long as Host and Target are kept in sync. | |
370 | */ | |
371 | /* MSI for firmware (errors, etc.) */ | |
372 | #define MSI_ASSIGN_FW 0 | |
373 | ||
374 | /* MSIs for Copy Engines */ | |
375 | #define MSI_ASSIGN_CE_INITIAL 1 | |
2f2cfc4a | 376 | #define MSI_ASSIGN_CE_MAX ar->hw_values->msi_assign_ce_max |
5e3dd157 KV |
377 | |
378 | /* as of IP3.7.1 */ | |
2f2cfc4a | 379 | #define RTC_STATE_V_ON ar->hw_values->rtc_state_val_on |
5e3dd157 | 380 | |
d63955b3 | 381 | #define RTC_STATE_COLD_RESET_MASK ar->regs->rtc_state_cold_reset_mask |
5e3dd157 KV |
382 | #define RTC_STATE_V_LSB 0 |
383 | #define RTC_STATE_V_MASK 0x00000007 | |
384 | #define RTC_STATE_ADDRESS 0x0000 | |
385 | #define PCIE_SOC_WAKE_V_MASK 0x00000001 | |
386 | #define PCIE_SOC_WAKE_ADDRESS 0x0004 | |
387 | #define PCIE_SOC_WAKE_RESET 0x00000000 | |
388 | #define SOC_GLOBAL_RESET_ADDRESS 0x0008 | |
389 | ||
d63955b3 MK |
390 | #define RTC_SOC_BASE_ADDRESS ar->regs->rtc_soc_base_address |
391 | #define RTC_WMAC_BASE_ADDRESS ar->regs->rtc_wmac_base_address | |
5e3dd157 KV |
392 | #define MAC_COEX_BASE_ADDRESS 0x00006000 |
393 | #define BT_COEX_BASE_ADDRESS 0x00007000 | |
394 | #define SOC_PCIE_BASE_ADDRESS 0x00008000 | |
d63955b3 | 395 | #define SOC_CORE_BASE_ADDRESS ar->regs->soc_core_base_address |
5e3dd157 KV |
396 | #define WLAN_UART_BASE_ADDRESS 0x0000c000 |
397 | #define WLAN_SI_BASE_ADDRESS 0x00010000 | |
398 | #define WLAN_GPIO_BASE_ADDRESS 0x00014000 | |
399 | #define WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000 | |
400 | #define WLAN_MAC_BASE_ADDRESS 0x00020000 | |
401 | #define EFUSE_BASE_ADDRESS 0x00030000 | |
402 | #define FPGA_REG_BASE_ADDRESS 0x00039000 | |
403 | #define WLAN_UART2_BASE_ADDRESS 0x00054c00 | |
d63955b3 MK |
404 | #define CE_WRAPPER_BASE_ADDRESS ar->regs->ce_wrapper_base_address |
405 | #define CE0_BASE_ADDRESS ar->regs->ce0_base_address | |
406 | #define CE1_BASE_ADDRESS ar->regs->ce1_base_address | |
407 | #define CE2_BASE_ADDRESS ar->regs->ce2_base_address | |
408 | #define CE3_BASE_ADDRESS ar->regs->ce3_base_address | |
409 | #define CE4_BASE_ADDRESS ar->regs->ce4_base_address | |
410 | #define CE5_BASE_ADDRESS ar->regs->ce5_base_address | |
411 | #define CE6_BASE_ADDRESS ar->regs->ce6_base_address | |
412 | #define CE7_BASE_ADDRESS ar->regs->ce7_base_address | |
5e3dd157 KV |
413 | #define DBI_BASE_ADDRESS 0x00060000 |
414 | #define WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS 0x0006c000 | |
a521ee98 | 415 | #define PCIE_LOCAL_BASE_ADDRESS ar->regs->pcie_local_base_address |
5e3dd157 | 416 | |
fc36e3ff | 417 | #define SOC_RESET_CONTROL_ADDRESS 0x00000000 |
5e3dd157 | 418 | #define SOC_RESET_CONTROL_OFFSET 0x00000000 |
d63955b3 MK |
419 | #define SOC_RESET_CONTROL_SI0_RST_MASK ar->regs->soc_reset_control_si0_rst_mask |
420 | #define SOC_RESET_CONTROL_CE_RST_MASK ar->regs->soc_reset_control_ce_rst_mask | |
fc36e3ff | 421 | #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040 |
5e3dd157 KV |
422 | #define SOC_CPU_CLOCK_OFFSET 0x00000020 |
423 | #define SOC_CPU_CLOCK_STANDARD_LSB 0 | |
424 | #define SOC_CPU_CLOCK_STANDARD_MASK 0x00000003 | |
425 | #define SOC_CLOCK_CONTROL_OFFSET 0x00000028 | |
426 | #define SOC_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001 | |
427 | #define SOC_SYSTEM_SLEEP_OFFSET 0x000000c4 | |
428 | #define SOC_LPO_CAL_OFFSET 0x000000e0 | |
429 | #define SOC_LPO_CAL_ENABLE_LSB 20 | |
430 | #define SOC_LPO_CAL_ENABLE_MASK 0x00100000 | |
fc36e3ff MK |
431 | #define SOC_LF_TIMER_CONTROL0_ADDRESS 0x00000050 |
432 | #define SOC_LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004 | |
5e3dd157 | 433 | |
d63955b3 | 434 | #define SOC_CHIP_ID_ADDRESS ar->regs->soc_chip_id_address |
e01ae68c KV |
435 | #define SOC_CHIP_ID_REV_LSB 8 |
436 | #define SOC_CHIP_ID_REV_MASK 0x00000f00 | |
437 | ||
5e3dd157 KV |
438 | #define WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000008 |
439 | #define WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000004 | |
440 | #define WLAN_SYSTEM_SLEEP_DISABLE_LSB 0 | |
441 | #define WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001 | |
442 | ||
443 | #define WLAN_GPIO_PIN0_ADDRESS 0x00000028 | |
444 | #define WLAN_GPIO_PIN0_CONFIG_MASK 0x00007800 | |
445 | #define WLAN_GPIO_PIN1_ADDRESS 0x0000002c | |
446 | #define WLAN_GPIO_PIN1_CONFIG_MASK 0x00007800 | |
447 | #define WLAN_GPIO_PIN10_ADDRESS 0x00000050 | |
448 | #define WLAN_GPIO_PIN11_ADDRESS 0x00000054 | |
449 | #define WLAN_GPIO_PIN12_ADDRESS 0x00000058 | |
450 | #define WLAN_GPIO_PIN13_ADDRESS 0x0000005c | |
451 | ||
452 | #define CLOCK_GPIO_OFFSET 0xffffffff | |
453 | #define CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0 | |
454 | #define CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0 | |
455 | ||
456 | #define SI_CONFIG_OFFSET 0x00000000 | |
457 | #define SI_CONFIG_BIDIR_OD_DATA_LSB 18 | |
458 | #define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000 | |
459 | #define SI_CONFIG_I2C_LSB 16 | |
460 | #define SI_CONFIG_I2C_MASK 0x00010000 | |
461 | #define SI_CONFIG_POS_SAMPLE_LSB 7 | |
462 | #define SI_CONFIG_POS_SAMPLE_MASK 0x00000080 | |
463 | #define SI_CONFIG_INACTIVE_DATA_LSB 5 | |
464 | #define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020 | |
465 | #define SI_CONFIG_INACTIVE_CLK_LSB 4 | |
466 | #define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010 | |
467 | #define SI_CONFIG_DIVIDER_LSB 0 | |
468 | #define SI_CONFIG_DIVIDER_MASK 0x0000000f | |
469 | #define SI_CS_OFFSET 0x00000004 | |
470 | #define SI_CS_DONE_ERR_MASK 0x00000400 | |
471 | #define SI_CS_DONE_INT_MASK 0x00000200 | |
472 | #define SI_CS_START_LSB 8 | |
473 | #define SI_CS_START_MASK 0x00000100 | |
474 | #define SI_CS_RX_CNT_LSB 4 | |
475 | #define SI_CS_RX_CNT_MASK 0x000000f0 | |
476 | #define SI_CS_TX_CNT_LSB 0 | |
477 | #define SI_CS_TX_CNT_MASK 0x0000000f | |
478 | ||
479 | #define SI_TX_DATA0_OFFSET 0x00000008 | |
480 | #define SI_TX_DATA1_OFFSET 0x0000000c | |
481 | #define SI_RX_DATA0_OFFSET 0x00000010 | |
482 | #define SI_RX_DATA1_OFFSET 0x00000014 | |
483 | ||
484 | #define CORE_CTRL_CPU_INTR_MASK 0x00002000 | |
7c0f0e3c | 485 | #define CORE_CTRL_PCIE_REG_31_MASK 0x00000800 |
5e3dd157 KV |
486 | #define CORE_CTRL_ADDRESS 0x0000 |
487 | #define PCIE_INTR_ENABLE_ADDRESS 0x0008 | |
e539887b | 488 | #define PCIE_INTR_CAUSE_ADDRESS 0x000c |
a521ee98 | 489 | #define PCIE_INTR_CLR_ADDRESS ar->regs->pcie_intr_clr_address |
d63955b3 | 490 | #define SCRATCH_3_ADDRESS ar->regs->scratch_3_address |
fc36e3ff | 491 | #define CPU_INTR_ADDRESS 0x0010 |
5e3dd157 | 492 | |
0936ea3f MK |
493 | /* Cycle counters are running at 88MHz */ |
494 | #define CCNT_TO_MSEC(x) ((x) / 88000) | |
495 | ||
5e3dd157 | 496 | /* Firmware indications to the Host via SCRATCH_3 register. */ |
a521ee98 | 497 | #define FW_INDICATOR_ADDRESS ar->regs->fw_indicator_address |
5e3dd157 KV |
498 | #define FW_IND_EVENT_PENDING 1 |
499 | #define FW_IND_INITIALIZED 2 | |
500 | ||
501 | /* HOST_REG interrupt from firmware */ | |
a521ee98 VT |
502 | #define PCIE_INTR_FIRMWARE_MASK ar->regs->pcie_intr_fw_mask |
503 | #define PCIE_INTR_CE_MASK_ALL ar->regs->pcie_intr_ce_mask_all | |
5e3dd157 KV |
504 | |
505 | #define DRAM_BASE_ADDRESS 0x00400000 | |
506 | ||
8bd47021 VT |
507 | #define PCIE_BAR_REG_ADDRESS 0x40030 |
508 | ||
5e3dd157 KV |
509 | #define MISSING 0 |
510 | ||
511 | #define SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET | |
512 | #define WLAN_SYSTEM_SLEEP_OFFSET SOC_SYSTEM_SLEEP_OFFSET | |
513 | #define WLAN_RESET_CONTROL_OFFSET SOC_RESET_CONTROL_OFFSET | |
514 | #define CLOCK_CONTROL_OFFSET SOC_CLOCK_CONTROL_OFFSET | |
515 | #define CLOCK_CONTROL_SI0_CLK_MASK SOC_CLOCK_CONTROL_SI0_CLK_MASK | |
516 | #define RESET_CONTROL_MBOX_RST_MASK MISSING | |
517 | #define RESET_CONTROL_SI0_RST_MASK SOC_RESET_CONTROL_SI0_RST_MASK | |
518 | #define GPIO_BASE_ADDRESS WLAN_GPIO_BASE_ADDRESS | |
519 | #define GPIO_PIN0_OFFSET WLAN_GPIO_PIN0_ADDRESS | |
520 | #define GPIO_PIN1_OFFSET WLAN_GPIO_PIN1_ADDRESS | |
521 | #define GPIO_PIN0_CONFIG_MASK WLAN_GPIO_PIN0_CONFIG_MASK | |
522 | #define GPIO_PIN1_CONFIG_MASK WLAN_GPIO_PIN1_CONFIG_MASK | |
523 | #define SI_BASE_ADDRESS WLAN_SI_BASE_ADDRESS | |
524 | #define SCRATCH_BASE_ADDRESS SOC_CORE_BASE_ADDRESS | |
525 | #define LOCAL_SCRATCH_OFFSET 0x18 | |
526 | #define CPU_CLOCK_OFFSET SOC_CPU_CLOCK_OFFSET | |
527 | #define LPO_CAL_OFFSET SOC_LPO_CAL_OFFSET | |
528 | #define GPIO_PIN10_OFFSET WLAN_GPIO_PIN10_ADDRESS | |
529 | #define GPIO_PIN11_OFFSET WLAN_GPIO_PIN11_ADDRESS | |
530 | #define GPIO_PIN12_OFFSET WLAN_GPIO_PIN12_ADDRESS | |
531 | #define GPIO_PIN13_OFFSET WLAN_GPIO_PIN13_ADDRESS | |
532 | #define CPU_CLOCK_STANDARD_LSB SOC_CPU_CLOCK_STANDARD_LSB | |
533 | #define CPU_CLOCK_STANDARD_MASK SOC_CPU_CLOCK_STANDARD_MASK | |
534 | #define LPO_CAL_ENABLE_LSB SOC_LPO_CAL_ENABLE_LSB | |
535 | #define LPO_CAL_ENABLE_MASK SOC_LPO_CAL_ENABLE_MASK | |
536 | #define ANALOG_INTF_BASE_ADDRESS WLAN_ANALOG_INTF_BASE_ADDRESS | |
537 | #define MBOX_BASE_ADDRESS MISSING | |
538 | #define INT_STATUS_ENABLE_ERROR_LSB MISSING | |
539 | #define INT_STATUS_ENABLE_ERROR_MASK MISSING | |
540 | #define INT_STATUS_ENABLE_CPU_LSB MISSING | |
541 | #define INT_STATUS_ENABLE_CPU_MASK MISSING | |
542 | #define INT_STATUS_ENABLE_COUNTER_LSB MISSING | |
543 | #define INT_STATUS_ENABLE_COUNTER_MASK MISSING | |
544 | #define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING | |
545 | #define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING | |
546 | #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING | |
547 | #define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING | |
548 | #define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING | |
549 | #define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING | |
550 | #define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING | |
551 | #define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING | |
552 | #define INT_STATUS_ENABLE_ADDRESS MISSING | |
553 | #define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING | |
554 | #define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING | |
555 | #define HOST_INT_STATUS_ADDRESS MISSING | |
556 | #define CPU_INT_STATUS_ADDRESS MISSING | |
557 | #define ERROR_INT_STATUS_ADDRESS MISSING | |
558 | #define ERROR_INT_STATUS_WAKEUP_MASK MISSING | |
559 | #define ERROR_INT_STATUS_WAKEUP_LSB MISSING | |
560 | #define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING | |
561 | #define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING | |
562 | #define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING | |
563 | #define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING | |
564 | #define COUNT_DEC_ADDRESS MISSING | |
565 | #define HOST_INT_STATUS_CPU_MASK MISSING | |
566 | #define HOST_INT_STATUS_CPU_LSB MISSING | |
567 | #define HOST_INT_STATUS_ERROR_MASK MISSING | |
568 | #define HOST_INT_STATUS_ERROR_LSB MISSING | |
569 | #define HOST_INT_STATUS_COUNTER_MASK MISSING | |
570 | #define HOST_INT_STATUS_COUNTER_LSB MISSING | |
571 | #define RX_LOOKAHEAD_VALID_ADDRESS MISSING | |
572 | #define WINDOW_DATA_ADDRESS MISSING | |
573 | #define WINDOW_READ_ADDR_ADDRESS MISSING | |
574 | #define WINDOW_WRITE_ADDR_ADDRESS MISSING | |
575 | ||
576 | #define RTC_STATE_V_GET(x) (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB) | |
577 | ||
578 | #endif /* _HW_H_ */ |