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mac80211: implement support for cfg80211_ops->{get,set}_ringparam
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / wireless / ath / ath5k / base.c
CommitLineData
fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
fa1c114f
JS		 43#include <linux/module.h>
44#include <linux/delay.h>
274c7c36 45#include <linux/hardirq.h>
fa1c114f 46#include <linux/if.h>
274c7c36 47#include <linux/io.h>
fa1c114f
JS		 48#include <linux/netdevice.h>
49#include <linux/cache.h>
fa1c114f
JS		 50#include <linux/ethtool.h>
51#include <linux/uaccess.h>
5a0e3ad6 52#include <linux/slab.h>
b1ae1edf 53#include <linux/etherdevice.h>
fa1c114f
JS		 54
55#include <net/ieee80211_radiotap.h>
56
57#include <asm/unaligned.h>
58
59#include "base.h"
60#include "reg.h"
61#include "debug.h"
2111ac0d 62#include "ani.h"
fa1c114f 63
0e472252
BC		 64#define CREATE_TRACE_POINTS
65#include "trace.h"
66
18cb6e32
JL		 67int ath5k_modparam_nohwcrypt;
68module_param_named(nohwcrypt, ath5k_modparam_nohwcrypt, bool, S_IRUGO);
9ad9a26e 69MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
fa1c114f 70
42639fcd 71static int modparam_all_channels;
46802a4f 72module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
42639fcd
BC		 73MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
74
fa1c114f
JS		 75/* Module info */
76MODULE_AUTHOR("Jiri Slaby");
77MODULE_AUTHOR("Nick Kossifidis");
78MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
79MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
80MODULE_LICENSE("Dual BSD/GPL");
fa1c114f 81
132b1c3e 82static int ath5k_init(struct ieee80211_hw *hw);
8aec7af9
NK		 83static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan,
84 bool skip_pcu);
cd2c5486
BR		 85int ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
86void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
fa1c114f 87
fa1c114f 88/* Known SREVs */
2c91108c 89static const struct ath5k_srev_name srev_names[] = {
a0b907ee
FF		 90#ifdef CONFIG_ATHEROS_AR231X
91 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R2 },
92 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R7 },
93 { "2313", AR5K_VERSION_MAC, AR5K_SREV_AR2313_R8 },
94 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R6 },
95 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R7 },
96 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R1 },
97 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R2 },
98#else
1bef016a
NK		 99 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
100 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
101 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
102 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
103 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
104 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
105 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
106 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
107 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
108 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
109 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
110 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
111 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
112 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
113 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
114 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
115 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
116 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
a0b907ee 117#endif
1bef016a 118 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
fa1c114f
JS		 119 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
120 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
1bef016a 121 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
fa1c114f
JS		 122 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
123 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
124 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
1bef016a 125 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
fa1c114f
JS		 126 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
127 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
1bef016a
NK		 128 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
129 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
130 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
1bef016a 131 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
fa1c114f 132 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
a0b907ee
FF		 133#ifdef CONFIG_ATHEROS_AR231X
134 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
135 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
136#endif
fa1c114f
JS		 137 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
138};
139
2c91108c 140static const struct ieee80211_rate ath5k_rates[] = {
63266a65
BR		 141 { .bitrate = 10,
142 .hw_value = ATH5K_RATE_CODE_1M, },
143 { .bitrate = 20,
144 .hw_value = ATH5K_RATE_CODE_2M,
145 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
146 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
147 { .bitrate = 55,
148 .hw_value = ATH5K_RATE_CODE_5_5M,
149 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
150 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
151 { .bitrate = 110,
152 .hw_value = ATH5K_RATE_CODE_11M,
153 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
154 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
155 { .bitrate = 60,
156 .hw_value = ATH5K_RATE_CODE_6M,
157 .flags = 0 },
158 { .bitrate = 90,
159 .hw_value = ATH5K_RATE_CODE_9M,
160 .flags = 0 },
161 { .bitrate = 120,
162 .hw_value = ATH5K_RATE_CODE_12M,
163 .flags = 0 },
164 { .bitrate = 180,
165 .hw_value = ATH5K_RATE_CODE_18M,
166 .flags = 0 },
167 { .bitrate = 240,
168 .hw_value = ATH5K_RATE_CODE_24M,
169 .flags = 0 },
170 { .bitrate = 360,
171 .hw_value = ATH5K_RATE_CODE_36M,
172 .flags = 0 },
173 { .bitrate = 480,
174 .hw_value = ATH5K_RATE_CODE_48M,
175 .flags = 0 },
176 { .bitrate = 540,
177 .hw_value = ATH5K_RATE_CODE_54M,
178 .flags = 0 },
179 /* XR missing */
180};
181
fa1c114f
JS		 182static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
183{
184 u64 tsf = ath5k_hw_get_tsf64(ah);
185
186 if ((tsf & 0x7fff) < rstamp)
187 tsf -= 0x8000;
188
189 return (tsf & ~0x7fff) | rstamp;
190}
191
e5b046d8 192const char *
fa1c114f
JS		 193ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
194{
195 const char *name = "xxxxx";
196 unsigned int i;
197
198 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
199 if (srev_names[i].sr_type != type)
200 continue;
75d0edb8
NK		 201
202 if ((val & 0xf0) == srev_names[i].sr_val)
203 name = srev_names[i].sr_name;
204
205 if ((val & 0xff) == srev_names[i].sr_val) {
fa1c114f
JS		 206 name = srev_names[i].sr_name;
207 break;
208 }
209 }
210
211 return name;
212}
e5aa8474
LR		 213static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
214{
215 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
216 return ath5k_hw_reg_read(ah, reg_offset);
217}
218
219static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
220{
221 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
222 ath5k_hw_reg_write(ah, val, reg_offset);
223}
224
225static const struct ath_ops ath5k_common_ops = {
226 .read = ath5k_ioread32,
227 .write = ath5k_iowrite32,
228};
fa1c114f 229
8a63facc
BC		 230/***********************\
231* Driver Initialization *
232\***********************/
233
234static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
fa1c114f 235{
8a63facc
BC		 236 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
237 struct ath5k_softc *sc = hw->priv;
238 struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah);
fa1c114f 239
8a63facc
BC		 240 return ath_reg_notifier_apply(wiphy, request, regulatory);
241}
6ccf15a1 242
8a63facc
BC		 243/********************\
244* Channel/mode setup *
245\********************/
fa1c114f 246
8a63facc
BC		 247/*
248 * Returns true for the channel numbers used without all_channels modparam.
249 */
410e6120 250static bool ath5k_is_standard_channel(short chan, enum ieee80211_band band)
8a63facc 251{
410e6120
BR		 252 if (band == IEEE80211_BAND_2GHZ && chan <= 14)
253 return true;
254
255 return /* UNII 1,2 */
256 (((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
8a63facc
BC		 257 /* midband */
258 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
259 /* UNII-3 */
410e6120
BR		 260 ((chan & 3) == 1 && chan >= 149 && chan <= 165) ||
261 /* 802.11j 5.030-5.080 GHz (20MHz) */
262 (chan == 8 || chan == 12 || chan == 16) ||
263 /* 802.11j 4.9GHz (20MHz) */
264 (chan == 184 || chan == 188 || chan == 192 || chan == 196));
8a63facc 265}
fa1c114f 266
8a63facc 267static unsigned int
97d9c3a3
BR		 268ath5k_setup_channels(struct ath5k_hw *ah, struct ieee80211_channel *channels,
269 unsigned int mode, unsigned int max)
8a63facc 270{
2b1351a3 271 unsigned int count, size, chfreq, freq, ch;
90c02d72 272 enum ieee80211_band band;
fa1c114f 273
8a63facc
BC		 274 switch (mode) {
275 case AR5K_MODE_11A:
8a63facc 276 /* 1..220, but 2GHz frequencies are filtered by check_channel */
97d9c3a3 277 size = 220;
8a63facc 278 chfreq = CHANNEL_5GHZ;
90c02d72 279 band = IEEE80211_BAND_5GHZ;
8a63facc
BC		 280 break;
281 case AR5K_MODE_11B:
282 case AR5K_MODE_11G:
8a63facc
BC		 283 size = 26;
284 chfreq = CHANNEL_2GHZ;
90c02d72 285 band = IEEE80211_BAND_2GHZ;
8a63facc
BC		 286 break;
287 default:
288 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
289 return 0;
fa1c114f
JS		 290 }
291
2b1351a3
BR		 292 count = 0;
293 for (ch = 1; ch <= size && count < max; ch++) {
90c02d72
BR		 294 freq = ieee80211_channel_to_frequency(ch, band);
295
296 if (freq == 0) /* mapping failed - not a standard channel */
297 continue;
fa1c114f 298
8a63facc
BC		 299 /* Check if channel is supported by the chipset */
300 if (!ath5k_channel_ok(ah, freq, chfreq))
301 continue;
f59ac048 302
410e6120
BR		 303 if (!modparam_all_channels &&
304 !ath5k_is_standard_channel(ch, band))
8a63facc 305 continue;
f59ac048 306
8a63facc
BC		 307 /* Write channel info and increment counter */
308 channels[count].center_freq = freq;
90c02d72 309 channels[count].band = band;
8a63facc
BC		 310 switch (mode) {
311 case AR5K_MODE_11A:
312 case AR5K_MODE_11G:
313 channels[count].hw_value = chfreq | CHANNEL_OFDM;
314 break;
8a63facc
BC		 315 case AR5K_MODE_11B:
316 channels[count].hw_value = CHANNEL_B;
317 }
fa1c114f 318
8a63facc 319 count++;
8a63facc 320 }
fa1c114f 321
8a63facc
BC		 322 return count;
323}
fa1c114f 324
8a63facc
BC		 325static void
326ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
327{
328 u8 i;
fa1c114f 329
8a63facc
BC		 330 for (i = 0; i < AR5K_MAX_RATES; i++)
331 sc->rate_idx[b->band][i] = -1;
fa1c114f 332
8a63facc
BC		 333 for (i = 0; i < b->n_bitrates; i++) {
334 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
335 if (b->bitrates[i].hw_value_short)
336 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
fa1c114f 337 }
8a63facc 338}
fa1c114f 339
8a63facc
BC		 340static int
341ath5k_setup_bands(struct ieee80211_hw *hw)
342{
343 struct ath5k_softc *sc = hw->priv;
344 struct ath5k_hw *ah = sc->ah;
345 struct ieee80211_supported_band *sband;
346 int max_c, count_c = 0;
347 int i;
fa1c114f 348
8a63facc
BC		 349 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
350 max_c = ARRAY_SIZE(sc->channels);
db719718 351
8a63facc
BC		 352 /* 2GHz band */
353 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
354 sband->band = IEEE80211_BAND_2GHZ;
355 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
9adca126 356
8a63facc
BC		 357 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
358 /* G mode */
359 memcpy(sband->bitrates, &ath5k_rates[0],
360 sizeof(struct ieee80211_rate) * 12);
361 sband->n_bitrates = 12;
2f7fe870 362
8a63facc 363 sband->channels = sc->channels;
08105690 364 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
8a63facc 365 AR5K_MODE_11G, max_c);
fa1c114f 366
8a63facc
BC		 367 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
368 count_c = sband->n_channels;
369 max_c -= count_c;
370 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
371 /* B mode */
372 memcpy(sband->bitrates, &ath5k_rates[0],
373 sizeof(struct ieee80211_rate) * 4);
374 sband->n_bitrates = 4;
fa1c114f 375
8a63facc
BC		 376 /* 5211 only supports B rates and uses 4bit rate codes
377 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
378 * fix them up here:
379 */
380 if (ah->ah_version == AR5K_AR5211) {
381 for (i = 0; i < 4; i++) {
382 sband->bitrates[i].hw_value =
383 sband->bitrates[i].hw_value & 0xF;
384 sband->bitrates[i].hw_value_short =
385 sband->bitrates[i].hw_value_short & 0xF;
fa1c114f
JS		 386 }
387 }
fa1c114f 388
8a63facc 389 sband->channels = sc->channels;
08105690 390 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
8a63facc 391 AR5K_MODE_11B, max_c);
fa1c114f 392
8a63facc
BC		 393 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
394 count_c = sband->n_channels;
395 max_c -= count_c;
396 }
397 ath5k_setup_rate_idx(sc, sband);
fa1c114f 398
8a63facc
BC		 399 /* 5GHz band, A mode */
400 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
401 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
402 sband->band = IEEE80211_BAND_5GHZ;
403 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
fa1c114f 404
8a63facc
BC		 405 memcpy(sband->bitrates, &ath5k_rates[4],
406 sizeof(struct ieee80211_rate) * 8);
407 sband->n_bitrates = 8;
fa1c114f 408
8a63facc 409 sband->channels = &sc->channels[count_c];
08105690 410 sband->n_channels = ath5k_setup_channels(ah, sband->channels,
8a63facc 411 AR5K_MODE_11A, max_c);
fa1c114f 412
8a63facc
BC		 413 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
414 }
415 ath5k_setup_rate_idx(sc, sband);
416
417 ath5k_debug_dump_bands(sc);
fa1c114f 418
fa1c114f
JS		 419 return 0;
420}
421
8a63facc
BC		 422/*
423 * Set/change channels. We always reset the chip.
424 * To accomplish this we must first cleanup any pending DMA,
425 * then restart stuff after a la ath5k_init.
426 *
427 * Called with sc->lock.
428 */
cd2c5486 429int
8a63facc
BC		 430ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
431{
432 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
433 "channel set, resetting (%u -> %u MHz)\n",
434 sc->curchan->center_freq, chan->center_freq);
435
8451d22d 436 /*
8a63facc
BC		 437 * To switch channels clear any pending DMA operations;
438 * wait long enough for the RX fifo to drain, reset the
439 * hardware at the new frequency, and then re-enable
440 * the relevant bits of the h/w.
8451d22d 441 */
8aec7af9 442 return ath5k_reset(sc, chan, true);
fa1c114f 443}
fa1c114f 444
e4b0b32a 445void ath5k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
b1ae1edf 446{
e4b0b32a 447 struct ath5k_vif_iter_data *iter_data = data;
b1ae1edf 448 int i;
62c58fb4 449 struct ath5k_vif *avf = (void *)vif->drv_priv;
b1ae1edf
BG		 450
451 if (iter_data->hw_macaddr)
452 for (i = 0; i < ETH_ALEN; i++)
453 iter_data->mask[i] &=
454 ~(iter_data->hw_macaddr[i] ^ mac[i]);
455
456 if (!iter_data->found_active) {
457 iter_data->found_active = true;
458 memcpy(iter_data->active_mac, mac, ETH_ALEN);
459 }
460
461 if (iter_data->need_set_hw_addr && iter_data->hw_macaddr)
462 if (compare_ether_addr(iter_data->hw_macaddr, mac) == 0)
463 iter_data->need_set_hw_addr = false;
464
465 if (!iter_data->any_assoc) {
b1ae1edf
BG		 466 if (avf->assoc)
467 iter_data->any_assoc = true;
468 }
62c58fb4
BG		 469
470 /* Calculate combined mode - when APs are active, operate in AP mode.
471 * Otherwise use the mode of the new interface. This can currently
472 * only deal with combinations of APs and STAs. Only one ad-hoc
7afbb2f0 473 * interfaces is allowed.
62c58fb4
BG		 474 */
475 if (avf->opmode == NL80211_IFTYPE_AP)
476 iter_data->opmode = NL80211_IFTYPE_AP;
e4b0b32a
BG		 477 else {
478 if (avf->opmode == NL80211_IFTYPE_STATION)
479 iter_data->n_stas++;
62c58fb4
BG		 480 if (iter_data->opmode == NL80211_IFTYPE_UNSPECIFIED)
481 iter_data->opmode = avf->opmode;
e4b0b32a 482 }
b1ae1edf
BG		 483}
484
cd2c5486
BR		 485void
486ath5k_update_bssid_mask_and_opmode(struct ath5k_softc *sc,
487 struct ieee80211_vif *vif)
b1ae1edf
BG		 488{
489 struct ath_common *common = ath5k_hw_common(sc->ah);
e4b0b32a
BG		 490 struct ath5k_vif_iter_data iter_data;
491 u32 rfilt;
b1ae1edf
BG		 492
493 /*
494 * Use the hardware MAC address as reference, the hardware uses it
495 * together with the BSSID mask when matching addresses.
496 */
497 iter_data.hw_macaddr = common->macaddr;
498 memset(&iter_data.mask, 0xff, ETH_ALEN);
499 iter_data.found_active = false;
500 iter_data.need_set_hw_addr = true;
62c58fb4 501 iter_data.opmode = NL80211_IFTYPE_UNSPECIFIED;
e4b0b32a 502 iter_data.n_stas = 0;
b1ae1edf
BG		 503
504 if (vif)
e4b0b32a 505 ath5k_vif_iter(&iter_data, vif->addr, vif);
b1ae1edf
BG		 506
507 /* Get list of all active MAC addresses */
e4b0b32a 508 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath5k_vif_iter,
b1ae1edf
BG		 509 &iter_data);
510 memcpy(sc->bssidmask, iter_data.mask, ETH_ALEN);
511
62c58fb4
BG		 512 sc->opmode = iter_data.opmode;
513 if (sc->opmode == NL80211_IFTYPE_UNSPECIFIED)
514 /* Nothing active, default to station mode */
515 sc->opmode = NL80211_IFTYPE_STATION;
516
7afbb2f0
BG		 517 ath5k_hw_set_opmode(sc->ah, sc->opmode);
518 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n",
519 sc->opmode, ath_opmode_to_string(sc->opmode));
62c58fb4 520
b1ae1edf
BG		 521 if (iter_data.need_set_hw_addr && iter_data.found_active)
522 ath5k_hw_set_lladdr(sc->ah, iter_data.active_mac);
523
62c58fb4
BG		 524 if (ath5k_hw_hasbssidmask(sc->ah))
525 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
b1ae1edf 526
e4b0b32a
BG		 527 /* Set up RX Filter */
528 if (iter_data.n_stas > 1) {
529 /* If you have multiple STA interfaces connected to
530 * different APs, ARPs are not received (most of the time?)
531 * Enabling PROMISC appears to fix that probem.
532 */
533 sc->filter_flags |= AR5K_RX_FILTER_PROM;
534 }
fa1c114f 535
8a63facc 536 rfilt = sc->filter_flags;
e4b0b32a 537 ath5k_hw_set_rx_filter(sc->ah, rfilt);
8a63facc
BC		 538 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
539}
fa1c114f 540
8a63facc
BC		 541static inline int
542ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
543{
544 int rix;
fa1c114f 545
8a63facc
BC		 546 /* return base rate on errors */
547 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
548 "hw_rix out of bounds: %x\n", hw_rix))
549 return 0;
550
930a7622 551 rix = sc->rate_idx[sc->curchan->band][hw_rix];
8a63facc
BC		 552 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
553 rix = 0;
554
555 return rix;
556}
557
558/***************\
559* Buffers setup *
560\***************/
561
562static
563struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
564{
565 struct ath_common *common = ath5k_hw_common(sc->ah);
566 struct sk_buff *skb;
fa1c114f
JS		 567
568 /*
8a63facc
BC		 569 * Allocate buffer with headroom_needed space for the
570 * fake physical layer header at the start.
fa1c114f 571 */
8a63facc
BC		 572 skb = ath_rxbuf_alloc(common,
573 common->rx_bufsize,
574 GFP_ATOMIC);
fa1c114f 575
8a63facc
BC		 576 if (!skb) {
577 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
578 common->rx_bufsize);
579 return NULL;
fa1c114f
JS		 580 }
581
aeae4ac9 582 *skb_addr = dma_map_single(sc->dev,
8a63facc 583 skb->data, common->rx_bufsize,
aeae4ac9
FF		 584 DMA_FROM_DEVICE);
585
586 if (unlikely(dma_mapping_error(sc->dev, *skb_addr))) {
8a63facc
BC		 587 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
588 dev_kfree_skb(skb);
589 return NULL;
0e149cf5 590 }
8a63facc
BC		 591 return skb;
592}
0e149cf5 593
8a63facc
BC		 594static int
595ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
596{
597 struct ath5k_hw *ah = sc->ah;
598 struct sk_buff *skb = bf->skb;
599 struct ath5k_desc *ds;
600 int ret;
fa1c114f 601
8a63facc
BC		 602 if (!skb) {
603 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
604 if (!skb)
605 return -ENOMEM;
606 bf->skb = skb;
f769c36b
BC		 607 }
608
8a63facc
BC		 609 /*
610 * Setup descriptors. For receive we always terminate
611 * the descriptor list with a self-linked entry so we'll
612 * not get overrun under high load (as can happen with a
613 * 5212 when ANI processing enables PHY error frames).
614 *
615 * To ensure the last descriptor is self-linked we create
616 * each descriptor as self-linked and add it to the end. As
617 * each additional descriptor is added the previous self-linked
618 * entry is "fixed" naturally. This should be safe even
619 * if DMA is happening. When processing RX interrupts we
620 * never remove/process the last, self-linked, entry on the
621 * descriptor list. This ensures the hardware always has
622 * someplace to write a new frame.
623 */
624 ds = bf->desc;
625 ds->ds_link = bf->daddr; /* link to self */
626 ds->ds_data = bf->skbaddr;
627 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0);
fa1c114f 628 if (ret) {
8a63facc
BC		 629 ATH5K_ERR(sc, "%s: could not setup RX desc\n", __func__);
630 return ret;
fa1c114f
JS		 631 }
632
8a63facc
BC		 633 if (sc->rxlink != NULL)
634 *sc->rxlink = bf->daddr;
635 sc->rxlink = &ds->ds_link;
fa1c114f 636 return 0;
fa1c114f
JS		 637}
638
8a63facc 639static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb)
fa1c114f 640{
8a63facc
BC		 641 struct ieee80211_hdr *hdr;
642 enum ath5k_pkt_type htype;
643 __le16 fc;
fa1c114f 644
8a63facc
BC		 645 hdr = (struct ieee80211_hdr *)skb->data;
646 fc = hdr->frame_control;
fa1c114f 647
8a63facc
BC		 648 if (ieee80211_is_beacon(fc))
649 htype = AR5K_PKT_TYPE_BEACON;
650 else if (ieee80211_is_probe_resp(fc))
651 htype = AR5K_PKT_TYPE_PROBE_RESP;
652 else if (ieee80211_is_atim(fc))
653 htype = AR5K_PKT_TYPE_ATIM;
654 else if (ieee80211_is_pspoll(fc))
655 htype = AR5K_PKT_TYPE_PSPOLL;
fa1c114f 656 else
8a63facc 657 htype = AR5K_PKT_TYPE_NORMAL;
fa1c114f 658
8a63facc 659 return htype;
42639fcd
BC		 660}
661
8a63facc
BC		 662static int
663ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
664 struct ath5k_txq *txq, int padsize)
fa1c114f 665{
8a63facc
BC		 666 struct ath5k_hw *ah = sc->ah;
667 struct ath5k_desc *ds = bf->desc;
668 struct sk_buff *skb = bf->skb;
669 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
670 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
671 struct ieee80211_rate *rate;
672 unsigned int mrr_rate[3], mrr_tries[3];
673 int i, ret;
674 u16 hw_rate;
675 u16 cts_rate = 0;
676 u16 duration = 0;
677 u8 rc_flags;
fa1c114f 678
8a63facc 679 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
fa1c114f 680
8a63facc 681 /* XXX endianness */
aeae4ac9
FF		 682 bf->skbaddr = dma_map_single(sc->dev, skb->data, skb->len,
683 DMA_TO_DEVICE);
fa1c114f 684
8a63facc 685 rate = ieee80211_get_tx_rate(sc->hw, info);
29ad2fac
JL		 686 if (!rate) {
687 ret = -EINVAL;
688 goto err_unmap;
689 }
fa1c114f 690
8a63facc
BC		 691 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
692 flags |= AR5K_TXDESC_NOACK;
fa1c114f 693
8a63facc
BC		 694 rc_flags = info->control.rates[0].flags;
695 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
696 rate->hw_value_short : rate->hw_value;
42639fcd 697
8a63facc
BC		 698 pktlen = skb->len;
699
700 /* FIXME: If we are in g mode and rate is a CCK rate
701 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
702 * from tx power (value is in dB units already) */
703 if (info->control.hw_key) {
704 keyidx = info->control.hw_key->hw_key_idx;
705 pktlen += info->control.hw_key->icv_len;
706 }
707 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
708 flags |= AR5K_TXDESC_RTSENA;
709 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
710 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
b1ae1edf 711 info->control.vif, pktlen, info));
8a63facc
BC		 712 }
713 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
714 flags |= AR5K_TXDESC_CTSENA;
715 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
716 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
b1ae1edf 717 info->control.vif, pktlen, info));
8a63facc
BC		 718 }
719 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
720 ieee80211_get_hdrlen_from_skb(skb), padsize,
721 get_hw_packet_type(skb),
722 (sc->power_level * 2),
723 hw_rate,
724 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
725 cts_rate, duration);
726 if (ret)
727 goto err_unmap;
728
729 memset(mrr_rate, 0, sizeof(mrr_rate));
730 memset(mrr_tries, 0, sizeof(mrr_tries));
731 for (i = 0; i < 3; i++) {
732 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
733 if (!rate)
400ec45a 734 break;
fa1c114f 735
8a63facc
BC		 736 mrr_rate[i] = rate->hw_value;
737 mrr_tries[i] = info->control.rates[i + 1].count;
fa1c114f
JS		 738 }
739
8a63facc
BC		 740 ath5k_hw_setup_mrr_tx_desc(ah, ds,
741 mrr_rate[0], mrr_tries[0],
742 mrr_rate[1], mrr_tries[1],
743 mrr_rate[2], mrr_tries[2]);
fa1c114f 744
8a63facc
BC		 745 ds->ds_link = 0;
746 ds->ds_data = bf->skbaddr;
63266a65 747
8a63facc
BC		 748 spin_lock_bh(&txq->lock);
749 list_add_tail(&bf->list, &txq->q);
925e0b06 750 txq->txq_len++;
8a63facc
BC		 751 if (txq->link == NULL) /* is this first packet? */
752 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
753 else /* no, so only link it */
754 *txq->link = bf->daddr;
63266a65 755
8a63facc
BC		 756 txq->link = &ds->ds_link;
757 ath5k_hw_start_tx_dma(ah, txq->qnum);
758 mmiowb();
759 spin_unlock_bh(&txq->lock);
760
761 return 0;
762err_unmap:
aeae4ac9 763 dma_unmap_single(sc->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
8a63facc 764 return ret;
63266a65
BR		 765}
766
8a63facc
BC		 767/*******************\
768* Descriptors setup *
769\*******************/
770
d8ee398d 771static int
aeae4ac9 772ath5k_desc_alloc(struct ath5k_softc *sc)
fa1c114f 773{
8a63facc
BC		 774 struct ath5k_desc *ds;
775 struct ath5k_buf *bf;
776 dma_addr_t da;
777 unsigned int i;
778 int ret;
d8ee398d 779
8a63facc
BC		 780 /* allocate descriptors */
781 sc->desc_len = sizeof(struct ath5k_desc) *
782 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
aeae4ac9
FF		 783
784 sc->desc = dma_alloc_coherent(sc->dev, sc->desc_len,
785 &sc->desc_daddr, GFP_KERNEL);
8a63facc
BC		 786 if (sc->desc == NULL) {
787 ATH5K_ERR(sc, "can't allocate descriptors\n");
788 ret = -ENOMEM;
789 goto err;
790 }
791 ds = sc->desc;
792 da = sc->desc_daddr;
793 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
794 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
fa1c114f 795
8a63facc
BC		 796 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
797 sizeof(struct ath5k_buf), GFP_KERNEL);
798 if (bf == NULL) {
799 ATH5K_ERR(sc, "can't allocate bufptr\n");
800 ret = -ENOMEM;
801 goto err_free;
802 }
803 sc->bufptr = bf;
fa1c114f 804
8a63facc
BC		 805 INIT_LIST_HEAD(&sc->rxbuf);
806 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
807 bf->desc = ds;
808 bf->daddr = da;
809 list_add_tail(&bf->list, &sc->rxbuf);
810 }
d8ee398d 811
8a63facc
BC		 812 INIT_LIST_HEAD(&sc->txbuf);
813 sc->txbuf_len = ATH_TXBUF;
814 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
815 da += sizeof(*ds)) {
816 bf->desc = ds;
817 bf->daddr = da;
818 list_add_tail(&bf->list, &sc->txbuf);
fa1c114f
JS		 819 }
820
b1ae1edf
BG		 821 /* beacon buffers */
822 INIT_LIST_HEAD(&sc->bcbuf);
823 for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) {
824 bf->desc = ds;
825 bf->daddr = da;
826 list_add_tail(&bf->list, &sc->bcbuf);
827 }
fa1c114f 828
8a63facc
BC		 829 return 0;
830err_free:
aeae4ac9 831 dma_free_coherent(sc->dev, sc->desc_len, sc->desc, sc->desc_daddr);
8a63facc
BC		 832err:
833 sc->desc = NULL;
834 return ret;
835}
fa1c114f 836
cd2c5486
BR		 837void
838ath5k_txbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf)
839{
840 BUG_ON(!bf);
841 if (!bf->skb)
842 return;
843 dma_unmap_single(sc->dev, bf->skbaddr, bf->skb->len,
844 DMA_TO_DEVICE);
845 dev_kfree_skb_any(bf->skb);
846 bf->skb = NULL;
847 bf->skbaddr = 0;
848 bf->desc->ds_data = 0;
849}
850
851void
852ath5k_rxbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf)
853{
854 struct ath5k_hw *ah = sc->ah;
855 struct ath_common *common = ath5k_hw_common(ah);
856
857 BUG_ON(!bf);
858 if (!bf->skb)
859 return;
860 dma_unmap_single(sc->dev, bf->skbaddr, common->rx_bufsize,
861 DMA_FROM_DEVICE);
862 dev_kfree_skb_any(bf->skb);
863 bf->skb = NULL;
864 bf->skbaddr = 0;
865 bf->desc->ds_data = 0;
866}
867
8a63facc 868static void
aeae4ac9 869ath5k_desc_free(struct ath5k_softc *sc)
8a63facc
BC		 870{
871 struct ath5k_buf *bf;
d8ee398d 872
8a63facc
BC		 873 list_for_each_entry(bf, &sc->txbuf, list)
874 ath5k_txbuf_free_skb(sc, bf);
875 list_for_each_entry(bf, &sc->rxbuf, list)
876 ath5k_rxbuf_free_skb(sc, bf);
b1ae1edf
BG		 877 list_for_each_entry(bf, &sc->bcbuf, list)
878 ath5k_txbuf_free_skb(sc, bf);
d8ee398d 879
8a63facc 880 /* Free memory associated with all descriptors */
aeae4ac9 881 dma_free_coherent(sc->dev, sc->desc_len, sc->desc, sc->desc_daddr);
8a63facc
BC		 882 sc->desc = NULL;
883 sc->desc_daddr = 0;
d8ee398d 884
8a63facc
BC		 885 kfree(sc->bufptr);
886 sc->bufptr = NULL;
fa1c114f
JS		 887}
888
8a63facc
BC		 889
890/**************\
891* Queues setup *
892\**************/
893
894static struct ath5k_txq *
895ath5k_txq_setup(struct ath5k_softc *sc,
896 int qtype, int subtype)
fa1c114f 897{
8a63facc
BC		 898 struct ath5k_hw *ah = sc->ah;
899 struct ath5k_txq *txq;
900 struct ath5k_txq_info qi = {
901 .tqi_subtype = subtype,
de8af455
BR		 902 /* XXX: default values not correct for B and XR channels,
903 * but who cares? */
904 .tqi_aifs = AR5K_TUNE_AIFS,
905 .tqi_cw_min = AR5K_TUNE_CWMIN,
906 .tqi_cw_max = AR5K_TUNE_CWMAX
8a63facc
BC		 907 };
908 int qnum;
d8ee398d 909
e30eb4ab 910 /*
8a63facc
BC		 911 * Enable interrupts only for EOL and DESC conditions.
912 * We mark tx descriptors to receive a DESC interrupt
913 * when a tx queue gets deep; otherwise we wait for the
914 * EOL to reap descriptors. Note that this is done to
915 * reduce interrupt load and this only defers reaping
916 * descriptors, never transmitting frames. Aside from
917 * reducing interrupts this also permits more concurrency.
918 * The only potential downside is if the tx queue backs
919 * up in which case the top half of the kernel may backup
920 * due to a lack of tx descriptors.
e30eb4ab 921 */
8a63facc
BC		 922 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
923 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
924 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
925 if (qnum < 0) {
926 /*
927 * NB: don't print a message, this happens
928 * normally on parts with too few tx queues
929 */
930 return ERR_PTR(qnum);
931 }
932 if (qnum >= ARRAY_SIZE(sc->txqs)) {
933 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
934 qnum, ARRAY_SIZE(sc->txqs));
935 ath5k_hw_release_tx_queue(ah, qnum);
936 return ERR_PTR(-EINVAL);
937 }
938 txq = &sc->txqs[qnum];
939 if (!txq->setup) {
940 txq->qnum = qnum;
941 txq->link = NULL;
942 INIT_LIST_HEAD(&txq->q);
943 spin_lock_init(&txq->lock);
944 txq->setup = true;
925e0b06 945 txq->txq_len = 0;
4edd761f 946 txq->txq_poll_mark = false;
923e5b3d 947 txq->txq_stuck = 0;
8a63facc
BC		 948 }
949 return &sc->txqs[qnum];
fa1c114f
JS		 950}
951
8a63facc
BC		 952static int
953ath5k_beaconq_setup(struct ath5k_hw *ah)
fa1c114f 954{
8a63facc 955 struct ath5k_txq_info qi = {
de8af455
BR		 956 /* XXX: default values not correct for B and XR channels,
957 * but who cares? */
958 .tqi_aifs = AR5K_TUNE_AIFS,
959 .tqi_cw_min = AR5K_TUNE_CWMIN,
960 .tqi_cw_max = AR5K_TUNE_CWMAX,
8a63facc
BC		 961 /* NB: for dynamic turbo, don't enable any other interrupts */
962 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
963 };
d8ee398d 964
8a63facc 965 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
fa1c114f
JS		 966}
967
8a63facc
BC		 968static int
969ath5k_beaconq_config(struct ath5k_softc *sc)
fa1c114f
JS		 970{
971 struct ath5k_hw *ah = sc->ah;
8a63facc
BC		 972 struct ath5k_txq_info qi;
973 int ret;
fa1c114f 974
8a63facc
BC		 975 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
976 if (ret)
977 goto err;
fa1c114f 978
8a63facc
BC		 979 if (sc->opmode == NL80211_IFTYPE_AP ||
980 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
981 /*
982 * Always burst out beacon and CAB traffic
983 * (aifs = cwmin = cwmax = 0)
984 */
985 qi.tqi_aifs = 0;
986 qi.tqi_cw_min = 0;
987 qi.tqi_cw_max = 0;
988 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
989 /*
990 * Adhoc mode; backoff between 0 and (2 * cw_min).
991 */
992 qi.tqi_aifs = 0;
993 qi.tqi_cw_min = 0;
de8af455 994 qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN;
8a63facc 995 }
fa1c114f 996
8a63facc
BC		 997 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
998 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
999 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
fa1c114f 1000
8a63facc
BC		 1001 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
1002 if (ret) {
1003 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1004 "hardware queue!\n", __func__);
1005 goto err;
1006 }
1007 ret = ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */
1008 if (ret)
1009 goto err;
b7266047 1010
8a63facc
BC		 1011 /* reconfigure cabq with ready time to 80% of beacon_interval */
1012 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1013 if (ret)
1014 goto err;
b7266047 1015
8a63facc
BC		 1016 qi.tqi_ready_time = (sc->bintval * 80) / 100;
1017 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi);
1018 if (ret)
1019 goto err;
b7266047 1020
8a63facc
BC		 1021 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB);
1022err:
1023 return ret;
d8ee398d
LR		 1024}
1025
80dac9ee
NK		 1026/**
1027 * ath5k_drain_tx_buffs - Empty tx buffers
1028 *
1029 * @sc The &struct ath5k_softc
1030 *
1031 * Empty tx buffers from all queues in preparation
1032 * of a reset or during shutdown.
1033 *
1034 * NB: this assumes output has been stopped and
1035 * we do not need to block ath5k_tx_tasklet
1036 */
8a63facc 1037static void
80dac9ee 1038ath5k_drain_tx_buffs(struct ath5k_softc *sc)
8a63facc 1039{
80dac9ee 1040 struct ath5k_txq *txq;
8a63facc 1041 struct ath5k_buf *bf, *bf0;
80dac9ee 1042 int i;
b6ea0356 1043
80dac9ee
NK		 1044 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) {
1045 if (sc->txqs[i].setup) {
1046 txq = &sc->txqs[i];
1047 spin_lock_bh(&txq->lock);
1048 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1049 ath5k_debug_printtxbuf(sc, bf);
b6ea0356 1050
80dac9ee 1051 ath5k_txbuf_free_skb(sc, bf);
fa1c114f 1052
80dac9ee
NK		 1053 spin_lock_bh(&sc->txbuflock);
1054 list_move_tail(&bf->list, &sc->txbuf);
1055 sc->txbuf_len++;
1056 txq->txq_len--;
1057 spin_unlock_bh(&sc->txbuflock);
8a63facc 1058 }
80dac9ee
NK		 1059 txq->link = NULL;
1060 txq->txq_poll_mark = false;
1061 spin_unlock_bh(&txq->lock);
1062 }
0452d4a5 1063 }
fa1c114f
JS		 1064}
1065
8a63facc
BC		 1066static void
1067ath5k_txq_release(struct ath5k_softc *sc)
2ac2927a 1068{
8a63facc
BC		 1069 struct ath5k_txq *txq = sc->txqs;
1070 unsigned int i;
2ac2927a 1071
8a63facc
BC		 1072 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1073 if (txq->setup) {
1074 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1075 txq->setup = false;
1076 }
1077}
2ac2927a 1078
2ac2927a 1079
8a63facc
BC		 1080/*************\
1081* RX Handling *
1082\*************/
2ac2927a 1083
8a63facc
BC		 1084/*
1085 * Enable the receive h/w following a reset.
1086 */
fa1c114f 1087static int
8a63facc 1088ath5k_rx_start(struct ath5k_softc *sc)
fa1c114f
JS		 1089{
1090 struct ath5k_hw *ah = sc->ah;
8a63facc
BC		 1091 struct ath_common *common = ath5k_hw_common(ah);
1092 struct ath5k_buf *bf;
1093 int ret;
fa1c114f 1094
8a63facc 1095 common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz);
fa1c114f 1096
8a63facc
BC		 1097 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n",
1098 common->cachelsz, common->rx_bufsize);
2f7fe870 1099
8a63facc
BC		 1100 spin_lock_bh(&sc->rxbuflock);
1101 sc->rxlink = NULL;
1102 list_for_each_entry(bf, &sc->rxbuf, list) {
1103 ret = ath5k_rxbuf_setup(sc, bf);
1104 if (ret != 0) {
1105 spin_unlock_bh(&sc->rxbuflock);
1106 goto err;
1107 }
2f7fe870 1108 }
8a63facc
BC		 1109 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1110 ath5k_hw_set_rxdp(ah, bf->daddr);
1111 spin_unlock_bh(&sc->rxbuflock);
2f7fe870 1112
8a63facc 1113 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
e4b0b32a 1114 ath5k_update_bssid_mask_and_opmode(sc, NULL); /* set filters, etc. */
8a63facc 1115 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
fa1c114f
JS		 1116
1117 return 0;
8a63facc 1118err:
fa1c114f
JS		 1119 return ret;
1120}
1121
8a63facc 1122/*
80dac9ee
NK		 1123 * Disable the receive logic on PCU (DRU)
1124 * In preparation for a shutdown.
1125 *
1126 * Note: Doesn't stop rx DMA, ath5k_hw_dma_stop
1127 * does.
8a63facc
BC		 1128 */
1129static void
1130ath5k_rx_stop(struct ath5k_softc *sc)
fa1c114f 1131{
8a63facc 1132 struct ath5k_hw *ah = sc->ah;
fa1c114f 1133
8a63facc 1134 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
80dac9ee 1135 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
fa1c114f 1136
8a63facc
BC		 1137 ath5k_debug_printrxbuffs(sc, ah);
1138}
fa1c114f 1139
8a63facc
BC		 1140static unsigned int
1141ath5k_rx_decrypted(struct ath5k_softc *sc, struct sk_buff *skb,
1142 struct ath5k_rx_status *rs)
1143{
1144 struct ath5k_hw *ah = sc->ah;
1145 struct ath_common *common = ath5k_hw_common(ah);
1146 struct ieee80211_hdr *hdr = (void *)skb->data;
1147 unsigned int keyix, hlen;
fa1c114f 1148
8a63facc
BC		 1149 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1150 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1151 return RX_FLAG_DECRYPTED;
fa1c114f 1152
8a63facc
BC		 1153 /* Apparently when a default key is used to decrypt the packet
1154 the hw does not set the index used to decrypt. In such cases
1155 get the index from the packet. */
1156 hlen = ieee80211_hdrlen(hdr->frame_control);
1157 if (ieee80211_has_protected(hdr->frame_control) &&
1158 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1159 skb->len >= hlen + 4) {
1160 keyix = skb->data[hlen + 3] >> 6;
1161
1162 if (test_bit(keyix, common->keymap))
1163 return RX_FLAG_DECRYPTED;
1164 }
fa1c114f
JS		 1165
1166 return 0;
fa1c114f
JS		 1167}
1168
8a63facc 1169
fa1c114f 1170static void
8a63facc
BC		 1171ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1172 struct ieee80211_rx_status *rxs)
fa1c114f 1173{
8a63facc
BC		 1174 struct ath_common *common = ath5k_hw_common(sc->ah);
1175 u64 tsf, bc_tstamp;
1176 u32 hw_tu;
1177 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
fa1c114f 1178
8a63facc
BC		 1179 if (ieee80211_is_beacon(mgmt->frame_control) &&
1180 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1181 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) {
1182 /*
1183 * Received an IBSS beacon with the same BSSID. Hardware *must*
1184 * have updated the local TSF. We have to work around various
1185 * hardware bugs, though...
1186 */
1187 tsf = ath5k_hw_get_tsf64(sc->ah);
1188 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1189 hw_tu = TSF_TO_TU(tsf);
fa1c114f 1190
8a63facc
BC		 1191 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1192 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1193 (unsigned long long)bc_tstamp,
1194 (unsigned long long)rxs->mactime,
1195 (unsigned long long)(rxs->mactime - bc_tstamp),
1196 (unsigned long long)tsf);
fa1c114f 1197
8a63facc
BC		 1198 /*
1199 * Sometimes the HW will give us a wrong tstamp in the rx
1200 * status, causing the timestamp extension to go wrong.
1201 * (This seems to happen especially with beacon frames bigger
1202 * than 78 byte (incl. FCS))
1203 * But we know that the receive timestamp must be later than the
1204 * timestamp of the beacon since HW must have synced to that.
1205 *
1206 * NOTE: here we assume mactime to be after the frame was
1207 * received, not like mac80211 which defines it at the start.
1208 */
1209 if (bc_tstamp > rxs->mactime) {
1210 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1211 "fixing mactime from %llx to %llx\n",
1212 (unsigned long long)rxs->mactime,
1213 (unsigned long long)tsf);
1214 rxs->mactime = tsf;
1215 }
fa1c114f 1216
8a63facc
BC		 1217 /*
1218 * Local TSF might have moved higher than our beacon timers,
1219 * in that case we have to update them to continue sending
1220 * beacons. This also takes care of synchronizing beacon sending
1221 * times with other stations.
1222 */
1223 if (hw_tu >= sc->nexttbtt)
1224 ath5k_beacon_update_timers(sc, bc_tstamp);
7f896126
BR		 1225
1226 /* Check if the beacon timers are still correct, because a TSF
1227 * update might have created a window between them - for a
1228 * longer description see the comment of this function: */
1229 if (!ath5k_hw_check_beacon_timers(sc->ah, sc->bintval)) {
1230 ath5k_beacon_update_timers(sc, bc_tstamp);
1231 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1232 "fixed beacon timers after beacon receive\n");
1233 }
8a63facc
BC		 1234 }
1235}
fa1c114f 1236
8a63facc
BC		 1237static void
1238ath5k_update_beacon_rssi(struct ath5k_softc *sc, struct sk_buff *skb, int rssi)
1239{
1240 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1241 struct ath5k_hw *ah = sc->ah;
1242 struct ath_common *common = ath5k_hw_common(ah);
fa1c114f 1243
8a63facc
BC		 1244 /* only beacons from our BSSID */
1245 if (!ieee80211_is_beacon(mgmt->frame_control) ||
1246 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) != 0)
1247 return;
fa1c114f 1248
eef39bef 1249 ewma_add(&ah->ah_beacon_rssi_avg, rssi);
fa1c114f 1250
8a63facc
BC		 1251 /* in IBSS mode we should keep RSSI statistics per neighbour */
1252 /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */
1253}
fa1c114f 1254
8a63facc
BC		 1255/*
1256 * Compute padding position. skb must contain an IEEE 802.11 frame
1257 */
1258static int ath5k_common_padpos(struct sk_buff *skb)
fa1c114f 1259{
8a63facc
BC		 1260 struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
1261 __le16 frame_control = hdr->frame_control;
1262 int padpos = 24;
fa1c114f 1263
8a63facc
BC		 1264 if (ieee80211_has_a4(frame_control)) {
1265 padpos += ETH_ALEN;
fa1c114f 1266 }
8a63facc
BC		 1267 if (ieee80211_is_data_qos(frame_control)) {
1268 padpos += IEEE80211_QOS_CTL_LEN;
fa1c114f 1269 }
8a63facc
BC		 1270
1271 return padpos;
fa1c114f
JS		 1272}
1273
8a63facc
BC		 1274/*
1275 * This function expects an 802.11 frame and returns the number of
1276 * bytes added, or -1 if we don't have enough header room.
1277 */
1278static int ath5k_add_padding(struct sk_buff *skb)
fa1c114f 1279{
8a63facc
BC		 1280 int padpos = ath5k_common_padpos(skb);
1281 int padsize = padpos & 3;
fa1c114f 1282
8a63facc 1283 if (padsize && skb->len>padpos) {
fa1c114f 1284
8a63facc
BC		 1285 if (skb_headroom(skb) < padsize)
1286 return -1;
fa1c114f 1287
8a63facc
BC		 1288 skb_push(skb, padsize);
1289 memmove(skb->data, skb->data+padsize, padpos);
1290 return padsize;
1291 }
a951ae21 1292
8a63facc
BC		 1293 return 0;
1294}
fa1c114f 1295
8a63facc
BC		 1296/*
1297 * The MAC header is padded to have 32-bit boundary if the
1298 * packet payload is non-zero. The general calculation for
1299 * padsize would take into account odd header lengths:
1300 * padsize = 4 - (hdrlen & 3); however, since only
1301 * even-length headers are used, padding can only be 0 or 2
1302 * bytes and we can optimize this a bit. We must not try to
1303 * remove padding from short control frames that do not have a
1304 * payload.
1305 *
1306 * This function expects an 802.11 frame and returns the number of
1307 * bytes removed.
1308 */
1309static int ath5k_remove_padding(struct sk_buff *skb)
1310{
1311 int padpos = ath5k_common_padpos(skb);
1312 int padsize = padpos & 3;
6d91e1d8 1313
8a63facc
BC		 1314 if (padsize && skb->len>=padpos+padsize) {
1315 memmove(skb->data + padsize, skb->data, padpos);
1316 skb_pull(skb, padsize);
1317 return padsize;
fa1c114f 1318 }
a951ae21 1319
8a63facc 1320 return 0;
fa1c114f
JS		 1321}
1322
1323static void
8a63facc
BC		 1324ath5k_receive_frame(struct ath5k_softc *sc, struct sk_buff *skb,
1325 struct ath5k_rx_status *rs)
fa1c114f 1326{
8a63facc
BC		 1327 struct ieee80211_rx_status *rxs;
1328
1329 ath5k_remove_padding(skb);
1330
1331 rxs = IEEE80211_SKB_RXCB(skb);
1332
1333 rxs->flag = 0;
1334 if (unlikely(rs->rs_status & AR5K_RXERR_MIC))
1335 rxs->flag |= RX_FLAG_MMIC_ERROR;
fa1c114f
JS		 1336
1337 /*
8a63facc
BC		 1338 * always extend the mac timestamp, since this information is
1339 * also needed for proper IBSS merging.
1340 *
1341 * XXX: it might be too late to do it here, since rs_tstamp is
1342 * 15bit only. that means TSF extension has to be done within
1343 * 32768usec (about 32ms). it might be necessary to move this to
1344 * the interrupt handler, like it is done in madwifi.
1345 *
1346 * Unfortunately we don't know when the hardware takes the rx
1347 * timestamp (beginning of phy frame, data frame, end of rx?).
1348 * The only thing we know is that it is hardware specific...
1349 * On AR5213 it seems the rx timestamp is at the end of the
1350 * frame, but i'm not sure.
1351 *
1352 * NOTE: mac80211 defines mactime at the beginning of the first
1353 * data symbol. Since we don't have any time references it's
1354 * impossible to comply to that. This affects IBSS merge only
1355 * right now, so it's not too bad...
fa1c114f 1356 */
8a63facc 1357 rxs->mactime = ath5k_extend_tsf(sc->ah, rs->rs_tstamp);
6ebacbb7 1358 rxs->flag |= RX_FLAG_MACTIME_MPDU;
fa1c114f 1359
8a63facc 1360 rxs->freq = sc->curchan->center_freq;
930a7622 1361 rxs->band = sc->curchan->band;
fa1c114f 1362
8a63facc 1363 rxs->signal = sc->ah->ah_noise_floor + rs->rs_rssi;
fa1c114f 1364
8a63facc 1365 rxs->antenna = rs->rs_antenna;
fa1c114f 1366
8a63facc
BC		 1367 if (rs->rs_antenna > 0 && rs->rs_antenna < 5)
1368 sc->stats.antenna_rx[rs->rs_antenna]++;
1369 else
1370 sc->stats.antenna_rx[0]++; /* invalid */
fa1c114f 1371
8a63facc
BC		 1372 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs->rs_rate);
1373 rxs->flag |= ath5k_rx_decrypted(sc, skb, rs);
fa1c114f 1374
8a63facc 1375 if (rxs->rate_idx >= 0 && rs->rs_rate ==
930a7622 1376 sc->sbands[sc->curchan->band].bitrates[rxs->rate_idx].hw_value_short)
8a63facc 1377 rxs->flag |= RX_FLAG_SHORTPRE;
fa1c114f 1378
0e472252 1379 trace_ath5k_rx(sc, skb);
fa1c114f 1380
8a63facc 1381 ath5k_update_beacon_rssi(sc, skb, rs->rs_rssi);
fa1c114f 1382
8a63facc
BC		 1383 /* check beacons in IBSS mode */
1384 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1385 ath5k_check_ibss_tsf(sc, skb, rxs);
fa1c114f 1386
8a63facc
BC		 1387 ieee80211_rx(sc->hw, skb);
1388}
fa1c114f 1389
8a63facc
BC		 1390/** ath5k_frame_receive_ok() - Do we want to receive this frame or not?
1391 *
1392 * Check if we want to further process this frame or not. Also update
1393 * statistics. Return true if we want this frame, false if not.
fa1c114f 1394 */
8a63facc
BC		 1395static bool
1396ath5k_receive_frame_ok(struct ath5k_softc *sc, struct ath5k_rx_status *rs)
fa1c114f 1397{
8a63facc 1398 sc->stats.rx_all_count++;
b72acddb 1399 sc->stats.rx_bytes_count += rs->rs_datalen;
fa1c114f 1400
8a63facc
BC		 1401 if (unlikely(rs->rs_status)) {
1402 if (rs->rs_status & AR5K_RXERR_CRC)
1403 sc->stats.rxerr_crc++;
1404 if (rs->rs_status & AR5K_RXERR_FIFO)
1405 sc->stats.rxerr_fifo++;
1406 if (rs->rs_status & AR5K_RXERR_PHY) {
1407 sc->stats.rxerr_phy++;
1408 if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32)
1409 sc->stats.rxerr_phy_code[rs->rs_phyerr]++;
1410 return false;
1411 }
1412 if (rs->rs_status & AR5K_RXERR_DECRYPT) {
1413 /*
1414 * Decrypt error. If the error occurred
1415 * because there was no hardware key, then
1416 * let the frame through so the upper layers
1417 * can process it. This is necessary for 5210
1418 * parts which have no way to setup a ``clear''
1419 * key cache entry.
1420 *
1421 * XXX do key cache faulting
1422 */
1423 sc->stats.rxerr_decrypt++;
1424 if (rs->rs_keyix == AR5K_RXKEYIX_INVALID &&
1425 !(rs->rs_status & AR5K_RXERR_CRC))
1426 return true;
1427 }
1428 if (rs->rs_status & AR5K_RXERR_MIC) {
1429 sc->stats.rxerr_mic++;
1430 return true;
fa1c114f 1431 }
fa1c114f 1432
8a63facc
BC		 1433 /* reject any frames with non-crypto errors */
1434 if (rs->rs_status & ~(AR5K_RXERR_DECRYPT))
1435 return false;
1436 }
fa1c114f 1437
8a63facc
BC		 1438 if (unlikely(rs->rs_more)) {
1439 sc->stats.rxerr_jumbo++;
1440 return false;
1441 }
1442 return true;
fa1c114f
JS		 1443}
1444
fa1c114f 1445static void
8a63facc 1446ath5k_tasklet_rx(unsigned long data)
fa1c114f 1447{
8a63facc
BC		 1448 struct ath5k_rx_status rs = {};
1449 struct sk_buff *skb, *next_skb;
1450 dma_addr_t next_skb_addr;
1451 struct ath5k_softc *sc = (void *)data;
dc1e001b
LR		 1452 struct ath5k_hw *ah = sc->ah;
1453 struct ath_common *common = ath5k_hw_common(ah);
8a63facc
BC		 1454 struct ath5k_buf *bf;
1455 struct ath5k_desc *ds;
1456 int ret;
fa1c114f 1457
8a63facc
BC		 1458 spin_lock(&sc->rxbuflock);
1459 if (list_empty(&sc->rxbuf)) {
1460 ATH5K_WARN(sc, "empty rx buf pool\n");
1461 goto unlock;
1462 }
1463 do {
1464 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1465 BUG_ON(bf->skb == NULL);
1466 skb = bf->skb;
1467 ds = bf->desc;
fa1c114f 1468
8a63facc
BC		 1469 /* bail if HW is still using self-linked descriptor */
1470 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
1471 break;
fa1c114f 1472
8a63facc
BC		 1473 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1474 if (unlikely(ret == -EINPROGRESS))
1475 break;
1476 else if (unlikely(ret)) {
1477 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1478 sc->stats.rxerr_proc++;
1479 break;
1480 }
fa1c114f 1481
8a63facc
BC		 1482 if (ath5k_receive_frame_ok(sc, &rs)) {
1483 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
fa1c114f 1484
8a63facc
BC		 1485 /*
1486 * If we can't replace bf->skb with a new skb under
1487 * memory pressure, just skip this packet
1488 */
1489 if (!next_skb)
1490 goto next;
036cd1ec 1491
aeae4ac9 1492 dma_unmap_single(sc->dev, bf->skbaddr,
8a63facc 1493 common->rx_bufsize,
aeae4ac9 1494 DMA_FROM_DEVICE);
036cd1ec 1495
8a63facc 1496 skb_put(skb, rs.rs_datalen);
6ba81c2c 1497
8a63facc 1498 ath5k_receive_frame(sc, skb, &rs);
6ba81c2c 1499
8a63facc
BC		 1500 bf->skb = next_skb;
1501 bf->skbaddr = next_skb_addr;
036cd1ec 1502 }
8a63facc
BC		 1503next:
1504 list_move_tail(&bf->list, &sc->rxbuf);
1505 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1506unlock:
1507 spin_unlock(&sc->rxbuflock);
036cd1ec
BR		 1508}
1509
b4ea449d 1510
8a63facc
BC		 1511/*************\
1512* TX Handling *
1513\*************/
b4ea449d 1514
7bb45683 1515void
cd2c5486
BR		 1516ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
1517 struct ath5k_txq *txq)
8a63facc
BC		 1518{
1519 struct ath5k_softc *sc = hw->priv;
1520 struct ath5k_buf *bf;
1521 unsigned long flags;
1522 int padsize;
b4ea449d 1523
0e472252 1524 trace_ath5k_tx(sc, skb, txq);
b4ea449d 1525
8a63facc
BC		 1526 /*
1527 * The hardware expects the header padded to 4 byte boundaries.
1528 * If this is not the case, we add the padding after the header.
1529 */
1530 padsize = ath5k_add_padding(skb);
1531 if (padsize < 0) {
1532 ATH5K_ERR(sc, "tx hdrlen not %%4: not enough"
1533 " headroom to pad");
1534 goto drop_packet;
1535 }
8127fbdc 1536
925e0b06
BR		 1537 if (txq->txq_len >= ATH5K_TXQ_LEN_MAX)
1538 ieee80211_stop_queue(hw, txq->qnum);
1539
8a63facc
BC		 1540 spin_lock_irqsave(&sc->txbuflock, flags);
1541 if (list_empty(&sc->txbuf)) {
1542 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
1543 spin_unlock_irqrestore(&sc->txbuflock, flags);
651d9375 1544 ieee80211_stop_queues(hw);
8a63facc 1545 goto drop_packet;
8127fbdc 1546 }
8a63facc
BC		 1547 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
1548 list_del(&bf->list);
1549 sc->txbuf_len--;
1550 if (list_empty(&sc->txbuf))
1551 ieee80211_stop_queues(hw);
1552 spin_unlock_irqrestore(&sc->txbuflock, flags);
1553
1554 bf->skb = skb;
1555
1556 if (ath5k_txbuf_setup(sc, bf, txq, padsize)) {
1557 bf->skb = NULL;
1558 spin_lock_irqsave(&sc->txbuflock, flags);
1559 list_add_tail(&bf->list, &sc->txbuf);
1560 sc->txbuf_len++;
1561 spin_unlock_irqrestore(&sc->txbuflock, flags);
1562 goto drop_packet;
8127fbdc 1563 }
7bb45683 1564 return;
8127fbdc 1565
8a63facc
BC		 1566drop_packet:
1567 dev_kfree_skb_any(skb);
8127fbdc
BP		 1568}
1569
1440401e
BR		 1570static void
1571ath5k_tx_frame_completed(struct ath5k_softc *sc, struct sk_buff *skb,
0e472252 1572 struct ath5k_txq *txq, struct ath5k_tx_status *ts)
1440401e
BR		 1573{
1574 struct ieee80211_tx_info *info;
1575 int i;
1576
1577 sc->stats.tx_all_count++;
b72acddb 1578 sc->stats.tx_bytes_count += skb->len;
1440401e
BR		 1579 info = IEEE80211_SKB_CB(skb);
1580
1581 ieee80211_tx_info_clear_status(info);
1582 for (i = 0; i < 4; i++) {
1583 struct ieee80211_tx_rate *r =
1584 &info->status.rates[i];
1585
1586 if (ts->ts_rate[i]) {
1587 r->idx = ath5k_hw_to_driver_rix(sc, ts->ts_rate[i]);
1588 r->count = ts->ts_retry[i];
1589 } else {
1590 r->idx = -1;
1591 r->count = 0;
1592 }
1593 }
1594
1595 /* count the successful attempt as well */
1596 info->status.rates[ts->ts_final_idx].count++;
1597
1598 if (unlikely(ts->ts_status)) {
1599 sc->stats.ack_fail++;
1600 if (ts->ts_status & AR5K_TXERR_FILT) {
1601 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1602 sc->stats.txerr_filt++;
1603 }
1604 if (ts->ts_status & AR5K_TXERR_XRETRY)
1605 sc->stats.txerr_retry++;
1606 if (ts->ts_status & AR5K_TXERR_FIFO)
1607 sc->stats.txerr_fifo++;
1608 } else {
1609 info->flags |= IEEE80211_TX_STAT_ACK;
1610 info->status.ack_signal = ts->ts_rssi;
1611 }
1612
1613 /*
1614 * Remove MAC header padding before giving the frame
1615 * back to mac80211.
1616 */
1617 ath5k_remove_padding(skb);
1618
1619 if (ts->ts_antenna > 0 && ts->ts_antenna < 5)
1620 sc->stats.antenna_tx[ts->ts_antenna]++;
1621 else
1622 sc->stats.antenna_tx[0]++; /* invalid */
1623
0e472252 1624 trace_ath5k_tx_complete(sc, skb, txq, ts);
1440401e
BR		 1625 ieee80211_tx_status(sc->hw, skb);
1626}
8a63facc
BC		 1627
1628static void
1629ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
8127fbdc 1630{
8a63facc
BC		 1631 struct ath5k_tx_status ts = {};
1632 struct ath5k_buf *bf, *bf0;
1633 struct ath5k_desc *ds;
1634 struct sk_buff *skb;
1440401e 1635 int ret;
8127fbdc 1636
8a63facc
BC		 1637 spin_lock(&txq->lock);
1638 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
23413296
BR		 1639
1640 txq->txq_poll_mark = false;
1641
1642 /* skb might already have been processed last time. */
1643 if (bf->skb != NULL) {
1644 ds = bf->desc;
1645
1646 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1647 if (unlikely(ret == -EINPROGRESS))
1648 break;
1649 else if (unlikely(ret)) {
1650 ATH5K_ERR(sc,
1651 "error %d while processing "
1652 "queue %u\n", ret, txq->qnum);
1653 break;
1654 }
1655
1656 skb = bf->skb;
1657 bf->skb = NULL;
aeae4ac9
FF		 1658
1659 dma_unmap_single(sc->dev, bf->skbaddr, skb->len,
1660 DMA_TO_DEVICE);
0e472252 1661 ath5k_tx_frame_completed(sc, skb, txq, &ts);
23413296 1662 }
8127fbdc 1663
8a63facc
BC		 1664 /*
1665 * It's possible that the hardware can say the buffer is
1666 * completed when it hasn't yet loaded the ds_link from
23413296
BR		 1667 * host memory and moved on.
1668 * Always keep the last descriptor to avoid HW races...
8a63facc 1669 */
23413296
BR		 1670 if (ath5k_hw_get_txdp(sc->ah, txq->qnum) != bf->daddr) {
1671 spin_lock(&sc->txbuflock);
1672 list_move_tail(&bf->list, &sc->txbuf);
1673 sc->txbuf_len++;
1674 txq->txq_len--;
1675 spin_unlock(&sc->txbuflock);
8a63facc 1676 }
fa1c114f 1677 }
fa1c114f 1678 spin_unlock(&txq->lock);
4198a8d0 1679 if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4)
925e0b06 1680 ieee80211_wake_queue(sc->hw, txq->qnum);
fa1c114f
JS		 1681}
1682
1683static void
1684ath5k_tasklet_tx(unsigned long data)
1685{
8784d2ee 1686 int i;
fa1c114f
JS		 1687 struct ath5k_softc *sc = (void *)data;
1688
8784d2ee
BC		 1689 for (i=0; i < AR5K_NUM_TX_QUEUES; i++)
1690 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i)))
1691 ath5k_tx_processq(sc, &sc->txqs[i]);
fa1c114f
JS		 1692}
1693
1694
fa1c114f
JS		 1695/*****************\
1696* Beacon handling *
1697\*****************/
1698
1699/*
1700 * Setup the beacon frame for transmit.
1701 */
1702static int
e039fa4a 1703ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 1704{
1705 struct sk_buff *skb = bf->skb;
a888d52d 1706 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 1707 struct ath5k_hw *ah = sc->ah;
1708 struct ath5k_desc *ds;
2bed03eb
NK		 1709 int ret = 0;
1710 u8 antenna;
fa1c114f 1711 u32 flags;
8127fbdc 1712 const int padsize = 0;
fa1c114f 1713
aeae4ac9
FF		 1714 bf->skbaddr = dma_map_single(sc->dev, skb->data, skb->len,
1715 DMA_TO_DEVICE);
fa1c114f
JS		 1716 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1717 "skbaddr %llx\n", skb, skb->data, skb->len,
1718 (unsigned long long)bf->skbaddr);
aeae4ac9
FF		 1719
1720 if (dma_mapping_error(sc->dev, bf->skbaddr)) {
fa1c114f
JS		 1721 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1722 return -EIO;
1723 }
1724
1725 ds = bf->desc;
2bed03eb 1726 antenna = ah->ah_tx_ant;
fa1c114f
JS		 1727
1728 flags = AR5K_TXDESC_NOACK;
05c914fe 1729 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
fa1c114f
JS		 1730 ds->ds_link = bf->daddr; /* self-linked */
1731 flags |= AR5K_TXDESC_VEOL;
2bed03eb 1732 } else
fa1c114f 1733 ds->ds_link = 0;
2bed03eb
NK		 1734
1735 /*
1736 * If we use multiple antennas on AP and use
1737 * the Sectored AP scenario, switch antenna every
1738 * 4 beacons to make sure everybody hears our AP.
1739 * When a client tries to associate, hw will keep
1740 * track of the tx antenna to be used for this client
1741 * automaticaly, based on ACKed packets.
1742 *
1743 * Note: AP still listens and transmits RTS on the
1744 * default antenna which is supposed to be an omni.
1745 *
1746 * Note2: On sectored scenarios it's possible to have
a180a130
BC		 1747 * multiple antennas (1 omni -- the default -- and 14
1748 * sectors), so if we choose to actually support this
1749 * mode, we need to allow the user to set how many antennas
1750 * we have and tweak the code below to send beacons
1751 * on all of them.
2bed03eb
NK		 1752 */
1753 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
1754 antenna = sc->bsent & 4 ? 2 : 1;
1755
fa1c114f 1756
8f655dde
NK		 1757 /* FIXME: If we are in g mode and rate is a CCK rate
1758 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1759 * from tx power (value is in dB units already) */
fa1c114f 1760 ds->ds_data = bf->skbaddr;
281c56dd 1761 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
8127fbdc 1762 ieee80211_get_hdrlen_from_skb(skb), padsize,
400ec45a 1763 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
e039fa4a 1764 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2e92e6f2 1765 1, AR5K_TXKEYIX_INVALID,
400ec45a 1766 antenna, flags, 0, 0);
fa1c114f
JS		 1767 if (ret)
1768 goto err_unmap;
1769
1770 return 0;
1771err_unmap:
aeae4ac9 1772 dma_unmap_single(sc->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE);
fa1c114f
JS		 1773 return ret;
1774}
1775
8a63facc
BC		 1776/*
1777 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
1778 * this is called only once at config_bss time, for AP we do it every
1779 * SWBA interrupt so that the TIM will reflect buffered frames.
1780 *
1781 * Called with the beacon lock.
1782 */
cd2c5486 1783int
8a63facc
BC		 1784ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1785{
1786 int ret;
1787 struct ath5k_softc *sc = hw->priv;
b1ae1edf 1788 struct ath5k_vif *avf = (void *)vif->drv_priv;
8a63facc
BC		 1789 struct sk_buff *skb;
1790
1791 if (WARN_ON(!vif)) {
1792 ret = -EINVAL;
1793 goto out;
1794 }
1795
1796 skb = ieee80211_beacon_get(hw, vif);
1797
1798 if (!skb) {
1799 ret = -ENOMEM;
1800 goto out;
1801 }
1802
b1ae1edf
BG		 1803 ath5k_txbuf_free_skb(sc, avf->bbuf);
1804 avf->bbuf->skb = skb;
1805 ret = ath5k_beacon_setup(sc, avf->bbuf);
8a63facc 1806 if (ret)
b1ae1edf 1807 avf->bbuf->skb = NULL;
8a63facc
BC		 1808out:
1809 return ret;
1810}
1811
fa1c114f
JS		 1812/*
1813 * Transmit a beacon frame at SWBA. Dynamic updates to the
1814 * frame contents are done as needed and the slot time is
1815 * also adjusted based on current state.
1816 *
5faaff74
BC		 1817 * This is called from software irq context (beacontq tasklets)
1818 * or user context from ath5k_beacon_config.
fa1c114f
JS		 1819 */
1820static void
1821ath5k_beacon_send(struct ath5k_softc *sc)
1822{
fa1c114f 1823 struct ath5k_hw *ah = sc->ah;
b1ae1edf
BG		 1824 struct ieee80211_vif *vif;
1825 struct ath5k_vif *avf;
1826 struct ath5k_buf *bf;
cec8db23 1827 struct sk_buff *skb;
fa1c114f 1828
be9b7259 1829 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f 1830
fa1c114f
JS		 1831 /*
1832 * Check if the previous beacon has gone out. If
a180a130 1833 * not, don't don't try to post another: skip this
fa1c114f
JS		 1834 * period and wait for the next. Missed beacons
1835 * indicate a problem and should not occur. If we
1836 * miss too many consecutive beacons reset the device.
1837 */
1838 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
1839 sc->bmisscount++;
be9b7259 1840 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f 1841 "missed %u consecutive beacons\n", sc->bmisscount);
428cbd4f 1842 if (sc->bmisscount > 10) { /* NB: 10 is a guess */
be9b7259 1843 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 1844 "stuck beacon time (%u missed)\n",
1845 sc->bmisscount);
8d67a031
BR		 1846 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
1847 "stuck beacon, resetting\n");
5faaff74 1848 ieee80211_queue_work(sc->hw, &sc->reset_work);
fa1c114f
JS		 1849 }
1850 return;
1851 }
1852 if (unlikely(sc->bmisscount != 0)) {
be9b7259 1853 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 1854 "resume beacon xmit after %u misses\n",
1855 sc->bmisscount);
1856 sc->bmisscount = 0;
1857 }
1858
b93996cf
JC		 1859 if ((sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) ||
1860 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
b1ae1edf
BG		 1861 u64 tsf = ath5k_hw_get_tsf64(ah);
1862 u32 tsftu = TSF_TO_TU(tsf);
1863 int slot = ((tsftu % sc->bintval) * ATH_BCBUF) / sc->bintval;
1864 vif = sc->bslot[(slot + 1) % ATH_BCBUF];
1865 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1866 "tsf %llx tsftu %x intval %u slot %u vif %p\n",
1867 (unsigned long long)tsf, tsftu, sc->bintval, slot, vif);
1868 } else /* only one interface */
1869 vif = sc->bslot[0];
1870
1871 if (!vif)
1872 return;
1873
1874 avf = (void *)vif->drv_priv;
1875 bf = avf->bbuf;
1876 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
1877 sc->opmode == NL80211_IFTYPE_MONITOR)) {
1878 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
1879 return;
1880 }
1881
fa1c114f
JS		 1882 /*
1883 * Stop any current dma and put the new frame on the queue.
1884 * This should never fail since we check above that no frames
1885 * are still pending on the queue.
1886 */
14fae2d4 1887 if (unlikely(ath5k_hw_stop_beacon_queue(ah, sc->bhalq))) {
428cbd4f 1888 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
fa1c114f
JS		 1889 /* NB: hw still stops DMA, so proceed */
1890 }
fa1c114f 1891
d82b577b
JC		 1892 /* refresh the beacon for AP or MESH mode */
1893 if (sc->opmode == NL80211_IFTYPE_AP ||
1894 sc->opmode == NL80211_IFTYPE_MESH_POINT)
b1ae1edf 1895 ath5k_beacon_update(sc->hw, vif);
1071db86 1896
0e472252
BC		 1897 trace_ath5k_tx(sc, bf->skb, &sc->txqs[sc->bhalq]);
1898
c6e387a2
NK		 1899 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
1900 ath5k_hw_start_tx_dma(ah, sc->bhalq);
be9b7259 1901 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
fa1c114f
JS		 1902 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
1903
b1ae1edf 1904 skb = ieee80211_get_buffered_bc(sc->hw, vif);
cec8db23
BC		 1905 while (skb) {
1906 ath5k_tx_queue(sc->hw, skb, sc->cabq);
b1ae1edf 1907 skb = ieee80211_get_buffered_bc(sc->hw, vif);
cec8db23
BC		 1908 }
1909
fa1c114f
JS		 1910 sc->bsent++;
1911}
1912
9804b98d
BR		 1913/**
1914 * ath5k_beacon_update_timers - update beacon timers
1915 *
1916 * @sc: struct ath5k_softc pointer we are operating on
1917 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
1918 * beacon timer update based on the current HW TSF.
1919 *
1920 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
1921 * of a received beacon or the current local hardware TSF and write it to the
1922 * beacon timer registers.
1923 *
1924 * This is called in a variety of situations, e.g. when a beacon is received,
6ba81c2c 1925 * when a TSF update has been detected, but also when an new IBSS is created or
9804b98d
BR		 1926 * when we otherwise know we have to update the timers, but we keep it in this
1927 * function to have it all together in one place.
1928 */
cd2c5486 1929void
9804b98d 1930ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
fa1c114f
JS		 1931{
1932 struct ath5k_hw *ah = sc->ah;
9804b98d
BR		 1933 u32 nexttbtt, intval, hw_tu, bc_tu;
1934 u64 hw_tsf;
fa1c114f
JS		 1935
1936 intval = sc->bintval & AR5K_BEACON_PERIOD;
b1ae1edf
BG		 1937 if (sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) {
1938 intval /= ATH_BCBUF; /* staggered multi-bss beacons */
1939 if (intval < 15)
1940 ATH5K_WARN(sc, "intval %u is too low, min 15\n",
1941 intval);
1942 }
fa1c114f
JS		 1943 if (WARN_ON(!intval))
1944 return;
1945
9804b98d
BR		 1946 /* beacon TSF converted to TU */
1947 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 1948
9804b98d
BR		 1949 /* current TSF converted to TU */
1950 hw_tsf = ath5k_hw_get_tsf64(ah);
1951 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 1952
11f21df3
BR		 1953#define FUDGE AR5K_TUNE_SW_BEACON_RESP + 3
1954 /* We use FUDGE to make sure the next TBTT is ahead of the current TU.
1955 * Since we later substract AR5K_TUNE_SW_BEACON_RESP (10) in the timer
1956 * configuration we need to make sure it is bigger than that. */
1957
9804b98d
BR		 1958 if (bc_tsf == -1) {
1959 /*
1960 * no beacons received, called internally.
1961 * just need to refresh timers based on HW TSF.
1962 */
1963 nexttbtt = roundup(hw_tu + FUDGE, intval);
1964 } else if (bc_tsf == 0) {
1965 /*
1966 * no beacon received, probably called by ath5k_reset_tsf().
1967 * reset TSF to start with 0.
1968 */
1969 nexttbtt = intval;
1970 intval |= AR5K_BEACON_RESET_TSF;
1971 } else if (bc_tsf > hw_tsf) {
1972 /*
1973 * beacon received, SW merge happend but HW TSF not yet updated.
1974 * not possible to reconfigure timers yet, but next time we
1975 * receive a beacon with the same BSSID, the hardware will
1976 * automatically update the TSF and then we need to reconfigure
1977 * the timers.
1978 */
1979 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1980 "need to wait for HW TSF sync\n");
1981 return;
1982 } else {
1983 /*
1984 * most important case for beacon synchronization between STA.
1985 *
1986 * beacon received and HW TSF has been already updated by HW.
1987 * update next TBTT based on the TSF of the beacon, but make
1988 * sure it is ahead of our local TSF timer.
1989 */
1990 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
1991 }
1992#undef FUDGE
fa1c114f 1993
036cd1ec
BR		 1994 sc->nexttbtt = nexttbtt;
1995
fa1c114f 1996 intval |= AR5K_BEACON_ENA;
fa1c114f 1997 ath5k_hw_init_beacon(ah, nexttbtt, intval);
9804b98d
BR		 1998
1999 /*
2000 * debugging output last in order to preserve the time critical aspect
2001 * of this function
2002 */
2003 if (bc_tsf == -1)
2004 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2005 "reconfigured timers based on HW TSF\n");
2006 else if (bc_tsf == 0)
2007 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2008 "reset HW TSF and timers\n");
2009 else
2010 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2011 "updated timers based on beacon TSF\n");
2012
2013 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2014 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2015 (unsigned long long) bc_tsf,
2016 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
9804b98d
BR		 2017 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2018 intval & AR5K_BEACON_PERIOD,
2019 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2020 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 2021}
2022
036cd1ec
BR		 2023/**
2024 * ath5k_beacon_config - Configure the beacon queues and interrupts
2025 *
2026 * @sc: struct ath5k_softc pointer we are operating on
fa1c114f 2027 *
036cd1ec 2028 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
6ba81c2c 2029 * interrupts to detect TSF updates only.
fa1c114f 2030 */
cd2c5486 2031void
fa1c114f
JS		 2032ath5k_beacon_config(struct ath5k_softc *sc)
2033{
2034 struct ath5k_hw *ah = sc->ah;
b5f03956 2035 unsigned long flags;
fa1c114f 2036
21800491 2037 spin_lock_irqsave(&sc->block, flags);
fa1c114f 2038 sc->bmisscount = 0;
dc1968e7 2039 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
fa1c114f 2040
21800491 2041 if (sc->enable_beacon) {
fa1c114f 2042 /*
036cd1ec
BR		 2043 * In IBSS mode we use a self-linked tx descriptor and let the
2044 * hardware send the beacons automatically. We have to load it
fa1c114f 2045 * only once here.
036cd1ec 2046 * We use the SWBA interrupt only to keep track of the beacon
6ba81c2c 2047 * timers in order to detect automatic TSF updates.
fa1c114f
JS		 2048 */
2049 ath5k_beaconq_config(sc);
fa1c114f 2050
036cd1ec
BR		 2051 sc->imask |= AR5K_INT_SWBA;
2052
da966bca 2053 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
21800491 2054 if (ath5k_hw_hasveol(ah))
da966bca 2055 ath5k_beacon_send(sc);
da966bca
JS		 2056 } else
2057 ath5k_beacon_update_timers(sc, -1);
21800491 2058 } else {
14fae2d4 2059 ath5k_hw_stop_beacon_queue(sc->ah, sc->bhalq);
fa1c114f 2060 }
fa1c114f 2061
c6e387a2 2062 ath5k_hw_set_imr(ah, sc->imask);
21800491
BC		 2063 mmiowb();
2064 spin_unlock_irqrestore(&sc->block, flags);
fa1c114f
JS		 2065}
2066
428cbd4f
NK		 2067static void ath5k_tasklet_beacon(unsigned long data)
2068{
2069 struct ath5k_softc *sc = (struct ath5k_softc *) data;
2070
2071 /*
2072 * Software beacon alert--time to send a beacon.
2073 *
2074 * In IBSS mode we use this interrupt just to
2075 * keep track of the next TBTT (target beacon
2076 * transmission time) in order to detect wether
2077 * automatic TSF updates happened.
2078 */
2079 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2080 /* XXX: only if VEOL suppported */
2081 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
2082 sc->nexttbtt += sc->bintval;
2083 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2084 "SWBA nexttbtt: %x hw_tu: %x "
2085 "TSF: %llx\n",
2086 sc->nexttbtt,
2087 TSF_TO_TU(tsf),
2088 (unsigned long long) tsf);
2089 } else {
2090 spin_lock(&sc->block);
2091 ath5k_beacon_send(sc);
2092 spin_unlock(&sc->block);
2093 }
2094}
2095
fa1c114f
JS		 2096
2097/********************\
2098* Interrupt handling *
2099\********************/
2100
6a8a3f6b
BR		 2101static void
2102ath5k_intr_calibration_poll(struct ath5k_hw *ah)
2103{
2111ac0d
BR		 2104 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) &&
2105 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL)) {
2106 /* run ANI only when full calibration is not active */
2107 ah->ah_cal_next_ani = jiffies +
2108 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI);
2109 tasklet_schedule(&ah->ah_sc->ani_tasklet);
2110
2111 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) {
6a8a3f6b
BR		 2112 ah->ah_cal_next_full = jiffies +
2113 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL);
2114 tasklet_schedule(&ah->ah_sc->calib);
2115 }
2116 /* we could use SWI to generate enough interrupts to meet our
2117 * calibration interval requirements, if necessary:
2118 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */
2119}
2120
132b1c3e 2121irqreturn_t
fa1c114f
JS		 2122ath5k_intr(int irq, void *dev_id)
2123{
2124 struct ath5k_softc *sc = dev_id;
2125 struct ath5k_hw *ah = sc->ah;
2126 enum ath5k_int status;
2127 unsigned int counter = 1000;
2128
2129 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
4cebb34c
FF		 2130 ((ath5k_get_bus_type(ah) != ATH_AHB) &&
2131 !ath5k_hw_is_intr_pending(ah))))
fa1c114f
JS		 2132 return IRQ_NONE;
2133
2134 do {
fa1c114f
JS		 2135 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2136 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2137 status, sc->imask);
fa1c114f
JS		 2138 if (unlikely(status & AR5K_INT_FATAL)) {
2139 /*
2140 * Fatal errors are unrecoverable.
2141 * Typically these are caused by DMA errors.
2142 */
8d67a031
BR		 2143 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2144 "fatal int, resetting\n");
5faaff74 2145 ieee80211_queue_work(sc->hw, &sc->reset_work);
fa1c114f 2146 } else if (unlikely(status & AR5K_INT_RXORN)) {
87d77c4e
BR		 2147 /*
2148 * Receive buffers are full. Either the bus is busy or
2149 * the CPU is not fast enough to process all received
2150 * frames.
2151 * Older chipsets need a reset to come out of this
2152 * condition, but we treat it as RX for newer chips.
2153 * We don't know exactly which versions need a reset -
2154 * this guess is copied from the HAL.
2155 */
2156 sc->stats.rxorn_intr++;
8d67a031
BR		 2157 if (ah->ah_mac_srev < AR5K_SREV_AR5212) {
2158 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2159 "rx overrun, resetting\n");
5faaff74 2160 ieee80211_queue_work(sc->hw, &sc->reset_work);
8d67a031 2161 }
87d77c4e
BR		 2162 else
2163 tasklet_schedule(&sc->rxtq);
fa1c114f
JS		 2164 } else {
2165 if (status & AR5K_INT_SWBA) {
56d2ac76 2166 tasklet_hi_schedule(&sc->beacontq);
fa1c114f
JS		 2167 }
2168 if (status & AR5K_INT_RXEOL) {
2169 /*
2170 * NB: the hardware should re-read the link when
2171 * RXE bit is written, but it doesn't work at
2172 * least on older hardware revs.
2173 */
b3f194e5 2174 sc->stats.rxeol_intr++;
fa1c114f
JS		 2175 }
2176 if (status & AR5K_INT_TXURN) {
2177 /* bump tx trigger level */
2178 ath5k_hw_update_tx_triglevel(ah, true);
2179 }
4c674c60 2180 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
fa1c114f 2181 tasklet_schedule(&sc->rxtq);
4c674c60
NK		 2182 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2183 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
fa1c114f
JS		 2184 tasklet_schedule(&sc->txtq);
2185 if (status & AR5K_INT_BMISS) {
1e3e6e8f 2186 /* TODO */
fa1c114f
JS		 2187 }
2188 if (status & AR5K_INT_MIB) {
2111ac0d 2189 sc->stats.mib_intr++;
495391d7 2190 ath5k_hw_update_mib_counters(ah);
2111ac0d 2191 ath5k_ani_mib_intr(ah);
fa1c114f 2192 }
e6a3b616 2193 if (status & AR5K_INT_GPIO)
e6a3b616 2194 tasklet_schedule(&sc->rf_kill.toggleq);
a6ae0716 2195
fa1c114f 2196 }
4cebb34c
FF		 2197
2198 if (ath5k_get_bus_type(ah) == ATH_AHB)
2199 break;
2200
2516baa6 2201 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
fa1c114f
JS		 2202
2203 if (unlikely(!counter))
2204 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2205
6a8a3f6b 2206 ath5k_intr_calibration_poll(ah);
6e220662 2207
fa1c114f
JS		 2208 return IRQ_HANDLED;
2209}
2210
fa1c114f
JS		 2211/*
2212 * Periodically recalibrate the PHY to account
2213 * for temperature/environment changes.
2214 */
2215static void
6e220662 2216ath5k_tasklet_calibrate(unsigned long data)
fa1c114f
JS		 2217{
2218 struct ath5k_softc *sc = (void *)data;
2219 struct ath5k_hw *ah = sc->ah;
2220
6e220662 2221 /* Only full calibration for now */
e65e1d77 2222 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL;
6e220662 2223
fa1c114f 2224 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
400ec45a
LR		 2225 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2226 sc->curchan->hw_value);
fa1c114f 2227
6f3b414a 2228 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
fa1c114f
JS		 2229 /*
2230 * Rfgain is out of bounds, reset the chip
2231 * to load new gain values.
2232 */
2233 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
5faaff74 2234 ieee80211_queue_work(sc->hw, &sc->reset_work);
fa1c114f
JS		 2235 }
2236 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2237 ATH5K_ERR(sc, "calibration of channel %u failed\n",
400ec45a
LR		 2238 ieee80211_frequency_to_channel(
2239 sc->curchan->center_freq));
fa1c114f 2240
0e8e02dd 2241 /* Noise floor calibration interrupts rx/tx path while I/Q calibration
651d9375
BR		 2242 * doesn't.
2243 * TODO: We should stop TX here, so that it doesn't interfere.
2244 * Note that stopping the queues is not enough to stop TX! */
afe86286
BR		 2245 if (time_is_before_eq_jiffies(ah->ah_cal_next_nf)) {
2246 ah->ah_cal_next_nf = jiffies +
2247 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_NF);
afe86286 2248 ath5k_hw_update_noise_floor(ah);
afe86286 2249 }
6e220662 2250
e65e1d77 2251 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL;
fa1c114f
JS		 2252}
2253
2254
2111ac0d
BR		 2255static void
2256ath5k_tasklet_ani(unsigned long data)
2257{
2258 struct ath5k_softc *sc = (void *)data;
2259 struct ath5k_hw *ah = sc->ah;
2260
2261 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI;
2262 ath5k_ani_calibration(ah);
2263 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI;
fa1c114f
JS		 2264}
2265
2266
4edd761f
BR		 2267static void
2268ath5k_tx_complete_poll_work(struct work_struct *work)
2269{
2270 struct ath5k_softc *sc = container_of(work, struct ath5k_softc,
2271 tx_complete_work.work);
2272 struct ath5k_txq *txq;
2273 int i;
2274 bool needreset = false;
2275
599b13ad
BC		 2276 mutex_lock(&sc->lock);
2277
4edd761f
BR		 2278 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) {
2279 if (sc->txqs[i].setup) {
2280 txq = &sc->txqs[i];
2281 spin_lock_bh(&txq->lock);
23413296 2282 if (txq->txq_len > 1) {
4edd761f
BR		 2283 if (txq->txq_poll_mark) {
2284 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT,
2285 "TX queue stuck %d\n",
2286 txq->qnum);
2287 needreset = true;
923e5b3d 2288 txq->txq_stuck++;
4edd761f
BR		 2289 spin_unlock_bh(&txq->lock);
2290 break;
2291 } else {
2292 txq->txq_poll_mark = true;
2293 }
2294 }
2295 spin_unlock_bh(&txq->lock);
2296 }
2297 }
2298
2299 if (needreset) {
2300 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2301 "TX queues stuck, resetting\n");
8aec7af9 2302 ath5k_reset(sc, NULL, true);
4edd761f
BR		 2303 }
2304
599b13ad
BC		 2305 mutex_unlock(&sc->lock);
2306
4edd761f
BR		 2307 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2308 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2309}
2310
2311
8a63facc
BC		 2312/*************************\
2313* Initialization routines *
2314\*************************/
fa1c114f 2315
132b1c3e
FF		 2316int
2317ath5k_init_softc(struct ath5k_softc *sc, const struct ath_bus_ops *bus_ops)
2318{
2319 struct ieee80211_hw *hw = sc->hw;
2320 struct ath_common *common;
2321 int ret;
2322 int csz;
2323
2324 /* Initialize driver private data */
2325 SET_IEEE80211_DEV(hw, sc->dev);
2326 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
b9e61f11
NK		 2327 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2328 IEEE80211_HW_SIGNAL_DBM |
2329 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
132b1c3e
FF		 2330
2331 hw->wiphy->interface_modes =
2332 BIT(NL80211_IFTYPE_AP) |
2333 BIT(NL80211_IFTYPE_STATION) |
2334 BIT(NL80211_IFTYPE_ADHOC) |
2335 BIT(NL80211_IFTYPE_MESH_POINT);
2336
3de135db
BR		 2337 /* both antennas can be configured as RX or TX */
2338 hw->wiphy->available_antennas_tx = 0x3;
2339 hw->wiphy->available_antennas_rx = 0x3;
2340
132b1c3e
FF		 2341 hw->extra_tx_headroom = 2;
2342 hw->channel_change_time = 5000;
2343
2344 /*
2345 * Mark the device as detached to avoid processing
2346 * interrupts until setup is complete.
2347 */
2348 __set_bit(ATH_STAT_INVALID, sc->status);
2349
2350 sc->opmode = NL80211_IFTYPE_STATION;
2351 sc->bintval = 1000;
2352 mutex_init(&sc->lock);
2353 spin_lock_init(&sc->rxbuflock);
2354 spin_lock_init(&sc->txbuflock);
2355 spin_lock_init(&sc->block);
2356
2357
2358 /* Setup interrupt handler */
2359 ret = request_irq(sc->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
2360 if (ret) {
2361 ATH5K_ERR(sc, "request_irq failed\n");
2362 goto err;
2363 }
2364
2365 /* If we passed the test, malloc an ath5k_hw struct */
2366 sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
2367 if (!sc->ah) {
2368 ret = -ENOMEM;
2369 ATH5K_ERR(sc, "out of memory\n");
2370 goto err_irq;
2371 }
2372
2373 sc->ah->ah_sc = sc;
2374 sc->ah->ah_iobase = sc->iobase;
2375 common = ath5k_hw_common(sc->ah);
2376 common->ops = &ath5k_common_ops;
2377 common->bus_ops = bus_ops;
2378 common->ah = sc->ah;
2379 common->hw = hw;
2380 common->priv = sc;
2381
2382 /*
2383 * Cache line size is used to size and align various
2384 * structures used to communicate with the hardware.
2385 */
2386 ath5k_read_cachesize(common, &csz);
2387 common->cachelsz = csz << 2; /* convert to bytes */
2388
2389 spin_lock_init(&common->cc_lock);
2390
2391 /* Initialize device */
2392 ret = ath5k_hw_init(sc);
2393 if (ret)
2394 goto err_free_ah;
2395
2396 /* set up multi-rate retry capabilities */
2397 if (sc->ah->ah_version == AR5K_AR5212) {
2398 hw->max_rates = 4;
76a9f6fd
BR		 2399 hw->max_rate_tries = max(AR5K_INIT_RETRY_SHORT,
2400 AR5K_INIT_RETRY_LONG);
132b1c3e
FF		 2401 }
2402
2403 hw->vif_data_size = sizeof(struct ath5k_vif);
2404
2405 /* Finish private driver data initialization */
2406 ret = ath5k_init(hw);
2407 if (ret)
2408 goto err_ah;
2409
2410 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
2411 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
2412 sc->ah->ah_mac_srev,
2413 sc->ah->ah_phy_revision);
2414
2415 if (!sc->ah->ah_single_chip) {
2416 /* Single chip radio (!RF5111) */
2417 if (sc->ah->ah_radio_5ghz_revision &&
2418 !sc->ah->ah_radio_2ghz_revision) {
2419 /* No 5GHz support -> report 2GHz radio */
2420 if (!test_bit(AR5K_MODE_11A,
2421 sc->ah->ah_capabilities.cap_mode)) {
2422 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
2423 ath5k_chip_name(AR5K_VERSION_RAD,
2424 sc->ah->ah_radio_5ghz_revision),
2425 sc->ah->ah_radio_5ghz_revision);
2426 /* No 2GHz support (5110 and some
2427 * 5Ghz only cards) -> report 5Ghz radio */
2428 } else if (!test_bit(AR5K_MODE_11B,
2429 sc->ah->ah_capabilities.cap_mode)) {
2430 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
2431 ath5k_chip_name(AR5K_VERSION_RAD,
2432 sc->ah->ah_radio_5ghz_revision),
2433 sc->ah->ah_radio_5ghz_revision);
2434 /* Multiband radio */
2435 } else {
2436 ATH5K_INFO(sc, "RF%s multiband radio found"
2437 " (0x%x)\n",
2438 ath5k_chip_name(AR5K_VERSION_RAD,
2439 sc->ah->ah_radio_5ghz_revision),
2440 sc->ah->ah_radio_5ghz_revision);
2441 }
2442 }
2443 /* Multi chip radio (RF5111 - RF2111) ->
2444 * report both 2GHz/5GHz radios */
2445 else if (sc->ah->ah_radio_5ghz_revision &&
2446 sc->ah->ah_radio_2ghz_revision){
2447 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
2448 ath5k_chip_name(AR5K_VERSION_RAD,
2449 sc->ah->ah_radio_5ghz_revision),
2450 sc->ah->ah_radio_5ghz_revision);
2451 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
2452 ath5k_chip_name(AR5K_VERSION_RAD,
2453 sc->ah->ah_radio_2ghz_revision),
2454 sc->ah->ah_radio_2ghz_revision);
2455 }
2456 }
2457
2458 ath5k_debug_init_device(sc);
2459
2460 /* ready to process interrupts */
2461 __clear_bit(ATH_STAT_INVALID, sc->status);
2462
2463 return 0;
2464err_ah:
2465 ath5k_hw_deinit(sc->ah);
2466err_free_ah:
2467 kfree(sc->ah);
2468err_irq:
2469 free_irq(sc->irq, sc);
2470err:
2471 return ret;
2472}
2473
fa1c114f 2474static int
8a63facc 2475ath5k_stop_locked(struct ath5k_softc *sc)
cec8db23 2476{
8a63facc 2477 struct ath5k_hw *ah = sc->ah;
cec8db23 2478
8a63facc
BC		 2479 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2480 test_bit(ATH_STAT_INVALID, sc->status));
2481
2482 /*
2483 * Shutdown the hardware and driver:
2484 * stop output from above
2485 * disable interrupts
2486 * turn off timers
2487 * turn off the radio
2488 * clear transmit machinery
2489 * clear receive machinery
2490 * drain and release tx queues
2491 * reclaim beacon resources
2492 * power down hardware
2493 *
2494 * Note that some of this work is not possible if the
2495 * hardware is gone (invalid).
2496 */
2497 ieee80211_stop_queues(sc->hw);
2498
2499 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2500 ath5k_led_off(sc);
2501 ath5k_hw_set_imr(ah, 0);
aeae4ac9 2502 synchronize_irq(sc->irq);
8a63facc 2503 ath5k_rx_stop(sc);
80dac9ee
NK		 2504 ath5k_hw_dma_stop(ah);
2505 ath5k_drain_tx_buffs(sc);
8a63facc
BC		 2506 ath5k_hw_phy_disable(ah);
2507 }
2508
2509 return 0;
cec8db23
BC		 2510}
2511
cd2c5486 2512int
132b1c3e 2513ath5k_init_hw(struct ath5k_softc *sc)
fa1c114f 2514{
8a63facc
BC		 2515 struct ath5k_hw *ah = sc->ah;
2516 struct ath_common *common = ath5k_hw_common(ah);
2517 int ret, i;
fa1c114f 2518
8a63facc
BC		 2519 mutex_lock(&sc->lock);
2520
2521 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
fa1c114f 2522
fa1c114f 2523 /*
8a63facc
BC		 2524 * Stop anything previously setup. This is safe
2525 * no matter this is the first time through or not.
fa1c114f 2526 */
8a63facc 2527 ath5k_stop_locked(sc);
fa1c114f 2528
8a63facc
BC		 2529 /*
2530 * The basic interface to setting the hardware in a good
2531 * state is ``reset''. On return the hardware is known to
2532 * be powered up and with interrupts disabled. This must
2533 * be followed by initialization of the appropriate bits
2534 * and then setup of the interrupt mask.
2535 */
2536 sc->curchan = sc->hw->conf.channel;
8a63facc
BC		 2537 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2538 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2539 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
fa1c114f 2540
8aec7af9 2541 ret = ath5k_reset(sc, NULL, false);
8a63facc
BC		 2542 if (ret)
2543 goto done;
fa1c114f 2544
8a63facc
BC		 2545 ath5k_rfkill_hw_start(ah);
2546
2547 /*
2548 * Reset the key cache since some parts do not reset the
2549 * contents on initial power up or resume from suspend.
2550 */
2551 for (i = 0; i < common->keymax; i++)
2552 ath_hw_keyreset(common, (u16) i);
2553
61cde037
NK		 2554 /* Use higher rates for acks instead of base
2555 * rate */
2556 ah->ah_ack_bitrate_high = true;
b1ae1edf
BG		 2557
2558 for (i = 0; i < ARRAY_SIZE(sc->bslot); i++)
2559 sc->bslot[i] = NULL;
2560
8a63facc
BC		 2561 ret = 0;
2562done:
2563 mmiowb();
2564 mutex_unlock(&sc->lock);
4edd761f
BR		 2565
2566 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work,
2567 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT));
2568
8a63facc
BC		 2569 return ret;
2570}
2571
2572static void stop_tasklets(struct ath5k_softc *sc)
2573{
2574 tasklet_kill(&sc->rxtq);
2575 tasklet_kill(&sc->txtq);
2576 tasklet_kill(&sc->calib);
2577 tasklet_kill(&sc->beacontq);
2578 tasklet_kill(&sc->ani_tasklet);
2579}
2580
2581/*
2582 * Stop the device, grabbing the top-level lock to protect
2583 * against concurrent entry through ath5k_init (which can happen
2584 * if another thread does a system call and the thread doing the
2585 * stop is preempted).
2586 */
cd2c5486 2587int
8a63facc
BC		 2588ath5k_stop_hw(struct ath5k_softc *sc)
2589{
2590 int ret;
2591
2592 mutex_lock(&sc->lock);
2593 ret = ath5k_stop_locked(sc);
2594 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2595 /*
2596 * Don't set the card in full sleep mode!
2597 *
2598 * a) When the device is in this state it must be carefully
2599 * woken up or references to registers in the PCI clock
2600 * domain may freeze the bus (and system). This varies
2601 * by chip and is mostly an issue with newer parts
2602 * (madwifi sources mentioned srev >= 0x78) that go to
2603 * sleep more quickly.
2604 *
2605 * b) On older chips full sleep results a weird behaviour
2606 * during wakeup. I tested various cards with srev < 0x78
2607 * and they don't wake up after module reload, a second
2608 * module reload is needed to bring the card up again.
2609 *
2610 * Until we figure out what's going on don't enable
2611 * full chip reset on any chip (this is what Legacy HAL
2612 * and Sam's HAL do anyway). Instead Perform a full reset
2613 * on the device (same as initial state after attach) and
2614 * leave it idle (keep MAC/BB on warm reset) */
2615 ret = ath5k_hw_on_hold(sc->ah);
2616
2617 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2618 "putting device to sleep\n");
fa1c114f
JS		 2619 }
2620
8a63facc
BC		 2621 mmiowb();
2622 mutex_unlock(&sc->lock);
2623
2624 stop_tasklets(sc);
2625
4edd761f
BR		 2626 cancel_delayed_work_sync(&sc->tx_complete_work);
2627
8a63facc
BC		 2628 ath5k_rfkill_hw_stop(sc->ah);
2629
2630 return ret;
fa1c114f
JS		 2631}
2632
209d889b
BC		 2633/*
2634 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2635 * and change to the given channel.
5faaff74
BC		 2636 *
2637 * This should be called with sc->lock.
209d889b 2638 */
fa1c114f 2639static int
8aec7af9
NK		 2640ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan,
2641 bool skip_pcu)
fa1c114f 2642{
fa1c114f 2643 struct ath5k_hw *ah = sc->ah;
f15a4bb2 2644 struct ath_common *common = ath5k_hw_common(ah);
344b54b9 2645 int ret, ani_mode;
fa1c114f
JS		 2646
2647 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
fa1c114f 2648
450464de 2649 ath5k_hw_set_imr(ah, 0);
aeae4ac9 2650 synchronize_irq(sc->irq);
450464de
BC		 2651 stop_tasklets(sc);
2652
344b54b9
NK		 2653 /* Save ani mode and disable ANI durring
2654 * reset. If we don't we might get false
2655 * PHY error interrupts. */
2656 ani_mode = ah->ah_sc->ani_state.ani_mode;
2657 ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF);
2658
19252ecb
NK		 2659 /* We are going to empty hw queues
2660 * so we should also free any remaining
2661 * tx buffers */
2662 ath5k_drain_tx_buffs(sc);
930a7622 2663 if (chan)
209d889b 2664 sc->curchan = chan;
8aec7af9
NK		 2665 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL,
2666 skip_pcu);
d7dc1003 2667 if (ret) {
fa1c114f
JS		 2668 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2669 goto err;
2670 }
d7dc1003 2671
fa1c114f 2672 ret = ath5k_rx_start(sc);
d7dc1003 2673 if (ret) {
fa1c114f
JS		 2674 ATH5K_ERR(sc, "can't start recv logic\n");
2675 goto err;
2676 }
d7dc1003 2677
344b54b9 2678 ath5k_ani_init(ah, ani_mode);
2111ac0d 2679
ac559526
BR		 2680 ah->ah_cal_next_full = jiffies;
2681 ah->ah_cal_next_ani = jiffies;
afe86286 2682 ah->ah_cal_next_nf = jiffies;
5dcc03fe 2683 ewma_init(&ah->ah_beacon_rssi_avg, 1024, 8);
afe86286 2684
f15a4bb2
BR		 2685 /* clear survey data and cycle counters */
2686 memset(&sc->survey, 0, sizeof(sc->survey));
bb007554 2687 spin_lock_bh(&common->cc_lock);
f15a4bb2
BR		 2688 ath_hw_cycle_counters_update(common);
2689 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
2690 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
bb007554 2691 spin_unlock_bh(&common->cc_lock);
f15a4bb2 2692
fa1c114f 2693 /*
d7dc1003
JS		 2694 * Change channels and update the h/w rate map if we're switching;
2695 * e.g. 11a to 11b/g.
2696 *
2697 * We may be doing a reset in response to an ioctl that changes the
2698 * channel so update any state that might change as a result.
fa1c114f
JS		 2699 *
2700 * XXX needed?
2701 */
2702/* ath5k_chan_change(sc, c); */
fa1c114f 2703
d7dc1003
JS		 2704 ath5k_beacon_config(sc);
2705 /* intrs are enabled by ath5k_beacon_config */
fa1c114f 2706
397f385b
BR		 2707 ieee80211_wake_queues(sc->hw);
2708
fa1c114f
JS		 2709 return 0;
2710err:
2711 return ret;
2712}
2713
5faaff74
BC		 2714static void ath5k_reset_work(struct work_struct *work)
2715{
2716 struct ath5k_softc *sc = container_of(work, struct ath5k_softc,
2717 reset_work);
2718
2719 mutex_lock(&sc->lock);
8aec7af9 2720 ath5k_reset(sc, NULL, true);
5faaff74
BC		 2721 mutex_unlock(&sc->lock);
2722}
2723
8a63facc 2724static int
132b1c3e 2725ath5k_init(struct ieee80211_hw *hw)
fa1c114f 2726{
132b1c3e 2727
fa1c114f 2728 struct ath5k_softc *sc = hw->priv;
8a63facc
BC		 2729 struct ath5k_hw *ah = sc->ah;
2730 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
925e0b06 2731 struct ath5k_txq *txq;
8a63facc 2732 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 2733 int ret;
2734
fa1c114f 2735
8a63facc
BC		 2736 /*
2737 * Check if the MAC has multi-rate retry support.
2738 * We do this by trying to setup a fake extended
2739 * descriptor. MACs that don't have support will
2740 * return false w/o doing anything. MACs that do
2741 * support it will return true w/o doing anything.
2742 */
2743 ret = ath5k_hw_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
67d2e2df 2744
8a63facc
BC		 2745 if (ret < 0)
2746 goto err;
2747 if (ret > 0)
2748 __set_bit(ATH_STAT_MRRETRY, sc->status);
ccfe5552 2749
8a63facc
BC		 2750 /*
2751 * Collect the channel list. The 802.11 layer
2752 * is resposible for filtering this list based
2753 * on settings like the phy mode and regulatory
2754 * domain restrictions.
2755 */
2756 ret = ath5k_setup_bands(hw);
2757 if (ret) {
2758 ATH5K_ERR(sc, "can't get channels\n");
2759 goto err;
2760 }
67d2e2df 2761
8a63facc
BC		 2762 /*
2763 * Allocate tx+rx descriptors and populate the lists.
2764 */
aeae4ac9 2765 ret = ath5k_desc_alloc(sc);
8a63facc
BC		 2766 if (ret) {
2767 ATH5K_ERR(sc, "can't allocate descriptors\n");
2768 goto err;
2769 }
fa1c114f 2770
8a63facc
BC		 2771 /*
2772 * Allocate hardware transmit queues: one queue for
2773 * beacon frames and one data queue for each QoS
2774 * priority. Note that hw functions handle resetting
2775 * these queues at the needed time.
2776 */
2777 ret = ath5k_beaconq_setup(ah);
2778 if (ret < 0) {
2779 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
2780 goto err_desc;
2781 }
2782 sc->bhalq = ret;
2783 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
2784 if (IS_ERR(sc->cabq)) {
2785 ATH5K_ERR(sc, "can't setup cab queue\n");
2786 ret = PTR_ERR(sc->cabq);
2787 goto err_bhal;
2788 }
fa1c114f 2789
22d8d9f8
BR		 2790 /* 5211 and 5212 usually support 10 queues but we better rely on the
2791 * capability information */
2792 if (ah->ah_capabilities.cap_queues.q_tx_num >= 6) {
2793 /* This order matches mac80211's queue priority, so we can
2794 * directly use the mac80211 queue number without any mapping */
2795 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO);
2796 if (IS_ERR(txq)) {
2797 ATH5K_ERR(sc, "can't setup xmit queue\n");
2798 ret = PTR_ERR(txq);
2799 goto err_queues;
2800 }
2801 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI);
2802 if (IS_ERR(txq)) {
2803 ATH5K_ERR(sc, "can't setup xmit queue\n");
2804 ret = PTR_ERR(txq);
2805 goto err_queues;
2806 }
2807 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
2808 if (IS_ERR(txq)) {
2809 ATH5K_ERR(sc, "can't setup xmit queue\n");
2810 ret = PTR_ERR(txq);
2811 goto err_queues;
2812 }
2813 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
2814 if (IS_ERR(txq)) {
2815 ATH5K_ERR(sc, "can't setup xmit queue\n");
2816 ret = PTR_ERR(txq);
2817 goto err_queues;
2818 }
2819 hw->queues = 4;
2820 } else {
2821 /* older hardware (5210) can only support one data queue */
2822 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE);
2823 if (IS_ERR(txq)) {
2824 ATH5K_ERR(sc, "can't setup xmit queue\n");
2825 ret = PTR_ERR(txq);
2826 goto err_queues;
2827 }
2828 hw->queues = 1;
2829 }
fa1c114f 2830
8a63facc
BC		 2831 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
2832 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
2833 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc);
2834 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
2835 tasklet_init(&sc->ani_tasklet, ath5k_tasklet_ani, (unsigned long)sc);
be009370 2836
8a63facc 2837 INIT_WORK(&sc->reset_work, ath5k_reset_work);
4edd761f 2838 INIT_DELAYED_WORK(&sc->tx_complete_work, ath5k_tx_complete_poll_work);
fa1c114f 2839
8a63facc
BC		 2840 ret = ath5k_eeprom_read_mac(ah, mac);
2841 if (ret) {
aeae4ac9 2842 ATH5K_ERR(sc, "unable to read address from EEPROM\n");
8a63facc 2843 goto err_queues;
e30eb4ab 2844 }
2bed03eb 2845
8a63facc 2846 SET_IEEE80211_PERM_ADDR(hw, mac);
b1ae1edf 2847 memcpy(&sc->lladdr, mac, ETH_ALEN);
8a63facc 2848 /* All MAC address bits matter for ACKs */
62c58fb4 2849 ath5k_update_bssid_mask_and_opmode(sc, NULL);
8a63facc
BC		 2850
2851 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
2852 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
2853 if (ret) {
2854 ATH5K_ERR(sc, "can't initialize regulatory system\n");
2855 goto err_queues;
2856 }
2857
2858 ret = ieee80211_register_hw(hw);
2859 if (ret) {
2860 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
2861 goto err_queues;
2862 }
2863
2864 if (!ath_is_world_regd(regulatory))
2865 regulatory_hint(hw->wiphy, regulatory->alpha2);
2866
2867 ath5k_init_leds(sc);
2868
2869 ath5k_sysfs_register(sc);
2870
2871 return 0;
2872err_queues:
2873 ath5k_txq_release(sc);
2874err_bhal:
2875 ath5k_hw_release_tx_queue(ah, sc->bhalq);
2876err_desc:
aeae4ac9 2877 ath5k_desc_free(sc);
8a63facc
BC		 2878err:
2879 return ret;
2880}
2881
132b1c3e
FF		 2882void
2883ath5k_deinit_softc(struct ath5k_softc *sc)
8a63facc 2884{
132b1c3e 2885 struct ieee80211_hw *hw = sc->hw;
8a63facc
BC		 2886
2887 /*
2888 * NB: the order of these is important:
2889 * o call the 802.11 layer before detaching ath5k_hw to
2890 * ensure callbacks into the driver to delete global
2891 * key cache entries can be handled
2892 * o reclaim the tx queue data structures after calling
2893 * the 802.11 layer as we'll get called back to reclaim
2894 * node state and potentially want to use them
2895 * o to cleanup the tx queues the hal is called, so detach
2896 * it last
2897 * XXX: ??? detach ath5k_hw ???
2898 * Other than that, it's straightforward...
2899 */
132b1c3e 2900 ath5k_debug_finish_device(sc);
8a63facc 2901 ieee80211_unregister_hw(hw);
aeae4ac9 2902 ath5k_desc_free(sc);
8a63facc
BC		 2903 ath5k_txq_release(sc);
2904 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
2905 ath5k_unregister_leds(sc);
2906
2907 ath5k_sysfs_unregister(sc);
2908 /*
2909 * NB: can't reclaim these until after ieee80211_ifdetach
2910 * returns because we'll get called back to reclaim node
2911 * state and potentially want to use them.
2912 */
132b1c3e
FF		 2913 ath5k_hw_deinit(sc->ah);
2914 free_irq(sc->irq, sc);
8a63facc
BC		 2915}
2916
cd2c5486
BR		 2917bool
2918ath_any_vif_assoc(struct ath5k_softc *sc)
b1ae1edf 2919{
e4b0b32a 2920 struct ath5k_vif_iter_data iter_data;
b1ae1edf
BG		 2921 iter_data.hw_macaddr = NULL;
2922 iter_data.any_assoc = false;
2923 iter_data.need_set_hw_addr = false;
2924 iter_data.found_active = true;
2925
e4b0b32a 2926 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath5k_vif_iter,
b1ae1edf
BG		 2927 &iter_data);
2928 return iter_data.any_assoc;
2929}
2930
cd2c5486 2931void
8a63facc
BC		 2932set_beacon_filter(struct ieee80211_hw *hw, bool enable)
2933{
2934 struct ath5k_softc *sc = hw->priv;
2935 struct ath5k_hw *ah = sc->ah;
2936 u32 rfilt;
2937 rfilt = ath5k_hw_get_rx_filter(ah);
2938 if (enable)
2939 rfilt |= AR5K_RX_FILTER_BEACON;
2940 else
2941 rfilt &= ~AR5K_RX_FILTER_BEACON;
2942 ath5k_hw_set_rx_filter(ah, rfilt);
2943 sc->filter_flags = rfilt;
2944}
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