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fa1c114f JS |
1 | /*- |
2 | * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting | |
3 | * Copyright (c) 2004-2005 Atheros Communications, Inc. | |
4 | * Copyright (c) 2006 Devicescape Software, Inc. | |
5 | * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com> | |
6 | * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu> | |
7 | * | |
8 | * All rights reserved. | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or without | |
11 | * modification, are permitted provided that the following conditions | |
12 | * are met: | |
13 | * 1. Redistributions of source code must retain the above copyright | |
14 | * notice, this list of conditions and the following disclaimer, | |
15 | * without modification. | |
16 | * 2. Redistributions in binary form must reproduce at minimum a disclaimer | |
17 | * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any | |
18 | * redistribution must be conditioned upon including a substantially | |
19 | * similar Disclaimer requirement for further binary redistribution. | |
20 | * 3. Neither the names of the above-listed copyright holders nor the names | |
21 | * of any contributors may be used to endorse or promote products derived | |
22 | * from this software without specific prior written permission. | |
23 | * | |
24 | * Alternatively, this software may be distributed under the terms of the | |
25 | * GNU General Public License ("GPL") version 2 as published by the Free | |
26 | * Software Foundation. | |
27 | * | |
28 | * NO WARRANTY | |
29 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
30 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
31 | * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY | |
32 | * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL | |
33 | * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, | |
34 | * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | |
35 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | |
36 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER | |
37 | * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | |
38 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF | |
39 | * THE POSSIBILITY OF SUCH DAMAGES. | |
40 | * | |
41 | */ | |
42 | ||
516304b0 JP |
43 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
44 | ||
fa1c114f JS |
45 | #include <linux/module.h> |
46 | #include <linux/delay.h> | |
b7f080cf | 47 | #include <linux/dma-mapping.h> |
274c7c36 | 48 | #include <linux/hardirq.h> |
fa1c114f | 49 | #include <linux/if.h> |
274c7c36 | 50 | #include <linux/io.h> |
fa1c114f JS |
51 | #include <linux/netdevice.h> |
52 | #include <linux/cache.h> | |
fa1c114f JS |
53 | #include <linux/ethtool.h> |
54 | #include <linux/uaccess.h> | |
5a0e3ad6 | 55 | #include <linux/slab.h> |
b1ae1edf | 56 | #include <linux/etherdevice.h> |
931be260 | 57 | #include <linux/nl80211.h> |
fa1c114f | 58 | |
4d70f2fb | 59 | #include <net/cfg80211.h> |
fa1c114f JS |
60 | #include <net/ieee80211_radiotap.h> |
61 | ||
62 | #include <asm/unaligned.h> | |
63 | ||
0967e01e | 64 | #include <net/mac80211.h> |
fa1c114f JS |
65 | #include "base.h" |
66 | #include "reg.h" | |
67 | #include "debug.h" | |
2111ac0d | 68 | #include "ani.h" |
931be260 PR |
69 | #include "ath5k.h" |
70 | #include "../regd.h" | |
fa1c114f | 71 | |
0e472252 BC |
72 | #define CREATE_TRACE_POINTS |
73 | #include "trace.h" | |
74 | ||
eb939922 | 75 | bool ath5k_modparam_nohwcrypt; |
18cb6e32 | 76 | module_param_named(nohwcrypt, ath5k_modparam_nohwcrypt, bool, S_IRUGO); |
9ad9a26e | 77 | MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); |
fa1c114f | 78 | |
eb939922 | 79 | static bool modparam_fastchanswitch; |
a99168ee NK |
80 | module_param_named(fastchanswitch, modparam_fastchanswitch, bool, S_IRUGO); |
81 | MODULE_PARM_DESC(fastchanswitch, "Enable fast channel switching for AR2413/AR5413 radios."); | |
82 | ||
11deb533 | 83 | static bool ath5k_modparam_no_hw_rfkill_switch; |
84e1e737 NK |
84 | module_param_named(no_hw_rfkill_switch, ath5k_modparam_no_hw_rfkill_switch, |
85 | bool, S_IRUGO); | |
86 | MODULE_PARM_DESC(no_hw_rfkill_switch, "Ignore the GPIO RFKill switch state"); | |
87 | ||
a99168ee | 88 | |
fa1c114f JS |
89 | /* Module info */ |
90 | MODULE_AUTHOR("Jiri Slaby"); | |
91 | MODULE_AUTHOR("Nick Kossifidis"); | |
92 | MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards."); | |
93 | MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards"); | |
94 | MODULE_LICENSE("Dual BSD/GPL"); | |
fa1c114f | 95 | |
132b1c3e | 96 | static int ath5k_init(struct ieee80211_hw *hw); |
e0d687bd | 97 | static int ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan, |
8aec7af9 | 98 | bool skip_pcu); |
fa1c114f | 99 | |
fa1c114f | 100 | /* Known SREVs */ |
2c91108c | 101 | static const struct ath5k_srev_name srev_names[] = { |
164a9748 | 102 | #ifdef CONFIG_ATH5K_AHB |
0e5d3ab5 SR |
103 | { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R2 }, |
104 | { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R7 }, | |
105 | { "2313", AR5K_VERSION_MAC, AR5K_SREV_AR2313_R8 }, | |
106 | { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R6 }, | |
107 | { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R7 }, | |
108 | { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R1 }, | |
109 | { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R2 }, | |
110 | #else | |
1bef016a NK |
111 | { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 }, |
112 | { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 }, | |
113 | { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A }, | |
114 | { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B }, | |
115 | { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 }, | |
116 | { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 }, | |
117 | { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 }, | |
118 | { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A }, | |
119 | { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 }, | |
120 | { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 }, | |
121 | { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 }, | |
122 | { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 }, | |
123 | { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 }, | |
124 | { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 }, | |
125 | { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 }, | |
126 | { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 }, | |
127 | { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 }, | |
128 | { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 }, | |
0e5d3ab5 | 129 | #endif |
1bef016a | 130 | { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN }, |
fa1c114f JS |
131 | { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 }, |
132 | { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 }, | |
1bef016a | 133 | { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A }, |
fa1c114f JS |
134 | { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 }, |
135 | { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 }, | |
136 | { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A }, | |
1bef016a | 137 | { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B }, |
fa1c114f JS |
138 | { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 }, |
139 | { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A }, | |
1bef016a NK |
140 | { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B }, |
141 | { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 }, | |
142 | { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 }, | |
1bef016a | 143 | { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 }, |
fa1c114f | 144 | { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 }, |
164a9748 | 145 | #ifdef CONFIG_ATH5K_AHB |
0e5d3ab5 SR |
146 | { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 }, |
147 | { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 }, | |
148 | #endif | |
fa1c114f JS |
149 | { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN }, |
150 | }; | |
151 | ||
2c91108c | 152 | static const struct ieee80211_rate ath5k_rates[] = { |
63266a65 BR |
153 | { .bitrate = 10, |
154 | .hw_value = ATH5K_RATE_CODE_1M, }, | |
155 | { .bitrate = 20, | |
156 | .hw_value = ATH5K_RATE_CODE_2M, | |
157 | .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE, | |
158 | .flags = IEEE80211_RATE_SHORT_PREAMBLE }, | |
159 | { .bitrate = 55, | |
160 | .hw_value = ATH5K_RATE_CODE_5_5M, | |
161 | .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE, | |
162 | .flags = IEEE80211_RATE_SHORT_PREAMBLE }, | |
163 | { .bitrate = 110, | |
164 | .hw_value = ATH5K_RATE_CODE_11M, | |
165 | .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE, | |
166 | .flags = IEEE80211_RATE_SHORT_PREAMBLE }, | |
167 | { .bitrate = 60, | |
168 | .hw_value = ATH5K_RATE_CODE_6M, | |
6a09ae95 SW |
169 | .flags = IEEE80211_RATE_SUPPORTS_5MHZ | |
170 | IEEE80211_RATE_SUPPORTS_10MHZ }, | |
63266a65 BR |
171 | { .bitrate = 90, |
172 | .hw_value = ATH5K_RATE_CODE_9M, | |
6a09ae95 SW |
173 | .flags = IEEE80211_RATE_SUPPORTS_5MHZ | |
174 | IEEE80211_RATE_SUPPORTS_10MHZ }, | |
63266a65 BR |
175 | { .bitrate = 120, |
176 | .hw_value = ATH5K_RATE_CODE_12M, | |
6a09ae95 SW |
177 | .flags = IEEE80211_RATE_SUPPORTS_5MHZ | |
178 | IEEE80211_RATE_SUPPORTS_10MHZ }, | |
63266a65 BR |
179 | { .bitrate = 180, |
180 | .hw_value = ATH5K_RATE_CODE_18M, | |
6a09ae95 SW |
181 | .flags = IEEE80211_RATE_SUPPORTS_5MHZ | |
182 | IEEE80211_RATE_SUPPORTS_10MHZ }, | |
63266a65 BR |
183 | { .bitrate = 240, |
184 | .hw_value = ATH5K_RATE_CODE_24M, | |
6a09ae95 SW |
185 | .flags = IEEE80211_RATE_SUPPORTS_5MHZ | |
186 | IEEE80211_RATE_SUPPORTS_10MHZ }, | |
63266a65 BR |
187 | { .bitrate = 360, |
188 | .hw_value = ATH5K_RATE_CODE_36M, | |
6a09ae95 SW |
189 | .flags = IEEE80211_RATE_SUPPORTS_5MHZ | |
190 | IEEE80211_RATE_SUPPORTS_10MHZ }, | |
63266a65 BR |
191 | { .bitrate = 480, |
192 | .hw_value = ATH5K_RATE_CODE_48M, | |
6a09ae95 SW |
193 | .flags = IEEE80211_RATE_SUPPORTS_5MHZ | |
194 | IEEE80211_RATE_SUPPORTS_10MHZ }, | |
63266a65 BR |
195 | { .bitrate = 540, |
196 | .hw_value = ATH5K_RATE_CODE_54M, | |
6a09ae95 SW |
197 | .flags = IEEE80211_RATE_SUPPORTS_5MHZ | |
198 | IEEE80211_RATE_SUPPORTS_10MHZ }, | |
63266a65 BR |
199 | }; |
200 | ||
fa1c114f JS |
201 | static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp) |
202 | { | |
203 | u64 tsf = ath5k_hw_get_tsf64(ah); | |
204 | ||
205 | if ((tsf & 0x7fff) < rstamp) | |
206 | tsf -= 0x8000; | |
207 | ||
208 | return (tsf & ~0x7fff) | rstamp; | |
209 | } | |
210 | ||
e5b046d8 | 211 | const char * |
fa1c114f JS |
212 | ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val) |
213 | { | |
214 | const char *name = "xxxxx"; | |
215 | unsigned int i; | |
216 | ||
217 | for (i = 0; i < ARRAY_SIZE(srev_names); i++) { | |
218 | if (srev_names[i].sr_type != type) | |
219 | continue; | |
75d0edb8 NK |
220 | |
221 | if ((val & 0xf0) == srev_names[i].sr_val) | |
222 | name = srev_names[i].sr_name; | |
223 | ||
224 | if ((val & 0xff) == srev_names[i].sr_val) { | |
fa1c114f JS |
225 | name = srev_names[i].sr_name; |
226 | break; | |
227 | } | |
228 | } | |
229 | ||
230 | return name; | |
231 | } | |
e5aa8474 LR |
232 | static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset) |
233 | { | |
234 | struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv; | |
235 | return ath5k_hw_reg_read(ah, reg_offset); | |
236 | } | |
237 | ||
238 | static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset) | |
239 | { | |
240 | struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv; | |
241 | ath5k_hw_reg_write(ah, val, reg_offset); | |
242 | } | |
243 | ||
244 | static const struct ath_ops ath5k_common_ops = { | |
245 | .read = ath5k_ioread32, | |
246 | .write = ath5k_iowrite32, | |
247 | }; | |
fa1c114f | 248 | |
8a63facc BC |
249 | /***********************\ |
250 | * Driver Initialization * | |
251 | \***********************/ | |
252 | ||
0c0280bd LR |
253 | static void ath5k_reg_notifier(struct wiphy *wiphy, |
254 | struct regulatory_request *request) | |
fa1c114f | 255 | { |
8a63facc | 256 | struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); |
e0d687bd PR |
257 | struct ath5k_hw *ah = hw->priv; |
258 | struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah); | |
fa1c114f | 259 | |
0c0280bd | 260 | ath_reg_notifier_apply(wiphy, request, regulatory); |
8a63facc | 261 | } |
6ccf15a1 | 262 | |
8a63facc BC |
263 | /********************\ |
264 | * Channel/mode setup * | |
265 | \********************/ | |
fa1c114f | 266 | |
8a63facc | 267 | /* |
2f8684ce | 268 | * Returns true for the channel numbers used. |
8a63facc | 269 | */ |
2f8684ce | 270 | #ifdef CONFIG_ATH5K_TEST_CHANNELS |
57fbcce3 | 271 | static bool ath5k_is_standard_channel(short chan, enum nl80211_band band) |
2f8684ce LR |
272 | { |
273 | return true; | |
274 | } | |
275 | ||
276 | #else | |
57fbcce3 | 277 | static bool ath5k_is_standard_channel(short chan, enum nl80211_band band) |
8a63facc | 278 | { |
57fbcce3 | 279 | if (band == NL80211_BAND_2GHZ && chan <= 14) |
410e6120 BR |
280 | return true; |
281 | ||
282 | return /* UNII 1,2 */ | |
283 | (((chan & 3) == 0 && chan >= 36 && chan <= 64) || | |
8a63facc BC |
284 | /* midband */ |
285 | ((chan & 3) == 0 && chan >= 100 && chan <= 140) || | |
286 | /* UNII-3 */ | |
410e6120 BR |
287 | ((chan & 3) == 1 && chan >= 149 && chan <= 165) || |
288 | /* 802.11j 5.030-5.080 GHz (20MHz) */ | |
289 | (chan == 8 || chan == 12 || chan == 16) || | |
290 | /* 802.11j 4.9GHz (20MHz) */ | |
291 | (chan == 184 || chan == 188 || chan == 192 || chan == 196)); | |
8a63facc | 292 | } |
2f8684ce | 293 | #endif |
fa1c114f | 294 | |
8a63facc | 295 | static unsigned int |
97d9c3a3 BR |
296 | ath5k_setup_channels(struct ath5k_hw *ah, struct ieee80211_channel *channels, |
297 | unsigned int mode, unsigned int max) | |
8a63facc | 298 | { |
32c25464 | 299 | unsigned int count, size, freq, ch; |
57fbcce3 | 300 | enum nl80211_band band; |
fa1c114f | 301 | |
8a63facc BC |
302 | switch (mode) { |
303 | case AR5K_MODE_11A: | |
8a63facc | 304 | /* 1..220, but 2GHz frequencies are filtered by check_channel */ |
97d9c3a3 | 305 | size = 220; |
57fbcce3 | 306 | band = NL80211_BAND_5GHZ; |
8a63facc BC |
307 | break; |
308 | case AR5K_MODE_11B: | |
309 | case AR5K_MODE_11G: | |
8a63facc | 310 | size = 26; |
57fbcce3 | 311 | band = NL80211_BAND_2GHZ; |
8a63facc BC |
312 | break; |
313 | default: | |
e0d687bd | 314 | ATH5K_WARN(ah, "bad mode, not copying channels\n"); |
8a63facc | 315 | return 0; |
fa1c114f JS |
316 | } |
317 | ||
2b1351a3 BR |
318 | count = 0; |
319 | for (ch = 1; ch <= size && count < max; ch++) { | |
90c02d72 BR |
320 | freq = ieee80211_channel_to_frequency(ch, band); |
321 | ||
322 | if (freq == 0) /* mapping failed - not a standard channel */ | |
323 | continue; | |
fa1c114f | 324 | |
32c25464 PR |
325 | /* Write channel info, needed for ath5k_channel_ok() */ |
326 | channels[count].center_freq = freq; | |
327 | channels[count].band = band; | |
328 | channels[count].hw_value = mode; | |
329 | ||
8a63facc | 330 | /* Check if channel is supported by the chipset */ |
32c25464 | 331 | if (!ath5k_channel_ok(ah, &channels[count])) |
8a63facc | 332 | continue; |
f59ac048 | 333 | |
2f8684ce | 334 | if (!ath5k_is_standard_channel(ch, band)) |
8a63facc | 335 | continue; |
f59ac048 | 336 | |
8a63facc | 337 | count++; |
8a63facc | 338 | } |
fa1c114f | 339 | |
8a63facc BC |
340 | return count; |
341 | } | |
fa1c114f | 342 | |
8a63facc | 343 | static void |
e0d687bd | 344 | ath5k_setup_rate_idx(struct ath5k_hw *ah, struct ieee80211_supported_band *b) |
8a63facc BC |
345 | { |
346 | u8 i; | |
fa1c114f | 347 | |
8a63facc | 348 | for (i = 0; i < AR5K_MAX_RATES; i++) |
e0d687bd | 349 | ah->rate_idx[b->band][i] = -1; |
fa1c114f | 350 | |
8a63facc | 351 | for (i = 0; i < b->n_bitrates; i++) { |
e0d687bd | 352 | ah->rate_idx[b->band][b->bitrates[i].hw_value] = i; |
8a63facc | 353 | if (b->bitrates[i].hw_value_short) |
e0d687bd | 354 | ah->rate_idx[b->band][b->bitrates[i].hw_value_short] = i; |
fa1c114f | 355 | } |
8a63facc | 356 | } |
fa1c114f | 357 | |
8a63facc BC |
358 | static int |
359 | ath5k_setup_bands(struct ieee80211_hw *hw) | |
360 | { | |
e0d687bd | 361 | struct ath5k_hw *ah = hw->priv; |
8a63facc BC |
362 | struct ieee80211_supported_band *sband; |
363 | int max_c, count_c = 0; | |
364 | int i; | |
fa1c114f | 365 | |
57fbcce3 | 366 | BUILD_BUG_ON(ARRAY_SIZE(ah->sbands) < NUM_NL80211_BANDS); |
e0d687bd | 367 | max_c = ARRAY_SIZE(ah->channels); |
db719718 | 368 | |
8a63facc | 369 | /* 2GHz band */ |
57fbcce3 JB |
370 | sband = &ah->sbands[NL80211_BAND_2GHZ]; |
371 | sband->band = NL80211_BAND_2GHZ; | |
372 | sband->bitrates = &ah->rates[NL80211_BAND_2GHZ][0]; | |
9adca126 | 373 | |
e0d687bd | 374 | if (test_bit(AR5K_MODE_11G, ah->ah_capabilities.cap_mode)) { |
8a63facc BC |
375 | /* G mode */ |
376 | memcpy(sband->bitrates, &ath5k_rates[0], | |
377 | sizeof(struct ieee80211_rate) * 12); | |
378 | sband->n_bitrates = 12; | |
2f7fe870 | 379 | |
e0d687bd | 380 | sband->channels = ah->channels; |
08105690 | 381 | sband->n_channels = ath5k_setup_channels(ah, sband->channels, |
8a63facc | 382 | AR5K_MODE_11G, max_c); |
fa1c114f | 383 | |
57fbcce3 | 384 | hw->wiphy->bands[NL80211_BAND_2GHZ] = sband; |
8a63facc BC |
385 | count_c = sband->n_channels; |
386 | max_c -= count_c; | |
e0d687bd | 387 | } else if (test_bit(AR5K_MODE_11B, ah->ah_capabilities.cap_mode)) { |
8a63facc BC |
388 | /* B mode */ |
389 | memcpy(sband->bitrates, &ath5k_rates[0], | |
390 | sizeof(struct ieee80211_rate) * 4); | |
391 | sband->n_bitrates = 4; | |
fa1c114f | 392 | |
8a63facc BC |
393 | /* 5211 only supports B rates and uses 4bit rate codes |
394 | * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B) | |
395 | * fix them up here: | |
396 | */ | |
397 | if (ah->ah_version == AR5K_AR5211) { | |
398 | for (i = 0; i < 4; i++) { | |
399 | sband->bitrates[i].hw_value = | |
400 | sband->bitrates[i].hw_value & 0xF; | |
401 | sband->bitrates[i].hw_value_short = | |
402 | sband->bitrates[i].hw_value_short & 0xF; | |
fa1c114f JS |
403 | } |
404 | } | |
fa1c114f | 405 | |
e0d687bd | 406 | sband->channels = ah->channels; |
08105690 | 407 | sband->n_channels = ath5k_setup_channels(ah, sband->channels, |
8a63facc | 408 | AR5K_MODE_11B, max_c); |
fa1c114f | 409 | |
57fbcce3 | 410 | hw->wiphy->bands[NL80211_BAND_2GHZ] = sband; |
8a63facc BC |
411 | count_c = sband->n_channels; |
412 | max_c -= count_c; | |
413 | } | |
e0d687bd | 414 | ath5k_setup_rate_idx(ah, sband); |
fa1c114f | 415 | |
8a63facc | 416 | /* 5GHz band, A mode */ |
e0d687bd | 417 | if (test_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode)) { |
57fbcce3 JB |
418 | sband = &ah->sbands[NL80211_BAND_5GHZ]; |
419 | sband->band = NL80211_BAND_5GHZ; | |
420 | sband->bitrates = &ah->rates[NL80211_BAND_5GHZ][0]; | |
fa1c114f | 421 | |
8a63facc BC |
422 | memcpy(sband->bitrates, &ath5k_rates[4], |
423 | sizeof(struct ieee80211_rate) * 8); | |
424 | sband->n_bitrates = 8; | |
fa1c114f | 425 | |
e0d687bd | 426 | sband->channels = &ah->channels[count_c]; |
08105690 | 427 | sband->n_channels = ath5k_setup_channels(ah, sband->channels, |
8a63facc | 428 | AR5K_MODE_11A, max_c); |
fa1c114f | 429 | |
57fbcce3 | 430 | hw->wiphy->bands[NL80211_BAND_5GHZ] = sband; |
8a63facc | 431 | } |
e0d687bd | 432 | ath5k_setup_rate_idx(ah, sband); |
8a63facc | 433 | |
e0d687bd | 434 | ath5k_debug_dump_bands(ah); |
fa1c114f | 435 | |
fa1c114f JS |
436 | return 0; |
437 | } | |
438 | ||
8a63facc BC |
439 | /* |
440 | * Set/change channels. We always reset the chip. | |
441 | * To accomplish this we must first cleanup any pending DMA, | |
442 | * then restart stuff after a la ath5k_init. | |
443 | * | |
e0d687bd | 444 | * Called with ah->lock. |
8a63facc | 445 | */ |
cd2c5486 | 446 | int |
4d70f2fb | 447 | ath5k_chan_set(struct ath5k_hw *ah, struct cfg80211_chan_def *chandef) |
8a63facc | 448 | { |
e0d687bd | 449 | ATH5K_DBG(ah, ATH5K_DEBUG_RESET, |
8a63facc | 450 | "channel set, resetting (%u -> %u MHz)\n", |
4d70f2fb SW |
451 | ah->curchan->center_freq, chandef->chan->center_freq); |
452 | ||
453 | switch (chandef->width) { | |
454 | case NL80211_CHAN_WIDTH_20: | |
455 | case NL80211_CHAN_WIDTH_20_NOHT: | |
456 | ah->ah_bwmode = AR5K_BWMODE_DEFAULT; | |
457 | break; | |
458 | case NL80211_CHAN_WIDTH_5: | |
459 | ah->ah_bwmode = AR5K_BWMODE_5MHZ; | |
460 | break; | |
461 | case NL80211_CHAN_WIDTH_10: | |
462 | ah->ah_bwmode = AR5K_BWMODE_10MHZ; | |
463 | break; | |
464 | default: | |
465 | WARN_ON(1); | |
466 | return -EINVAL; | |
467 | } | |
8a63facc | 468 | |
8451d22d | 469 | /* |
8a63facc BC |
470 | * To switch channels clear any pending DMA operations; |
471 | * wait long enough for the RX fifo to drain, reset the | |
472 | * hardware at the new frequency, and then re-enable | |
473 | * the relevant bits of the h/w. | |
8451d22d | 474 | */ |
4d70f2fb | 475 | return ath5k_reset(ah, chandef->chan, true); |
fa1c114f | 476 | } |
fa1c114f | 477 | |
e4b0b32a | 478 | void ath5k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) |
b1ae1edf | 479 | { |
e4b0b32a | 480 | struct ath5k_vif_iter_data *iter_data = data; |
b1ae1edf | 481 | int i; |
62c58fb4 | 482 | struct ath5k_vif *avf = (void *)vif->drv_priv; |
b1ae1edf BG |
483 | |
484 | if (iter_data->hw_macaddr) | |
485 | for (i = 0; i < ETH_ALEN; i++) | |
486 | iter_data->mask[i] &= | |
487 | ~(iter_data->hw_macaddr[i] ^ mac[i]); | |
488 | ||
489 | if (!iter_data->found_active) { | |
490 | iter_data->found_active = true; | |
491 | memcpy(iter_data->active_mac, mac, ETH_ALEN); | |
492 | } | |
493 | ||
494 | if (iter_data->need_set_hw_addr && iter_data->hw_macaddr) | |
2e42e474 | 495 | if (ether_addr_equal(iter_data->hw_macaddr, mac)) |
b1ae1edf BG |
496 | iter_data->need_set_hw_addr = false; |
497 | ||
498 | if (!iter_data->any_assoc) { | |
b1ae1edf BG |
499 | if (avf->assoc) |
500 | iter_data->any_assoc = true; | |
501 | } | |
62c58fb4 BG |
502 | |
503 | /* Calculate combined mode - when APs are active, operate in AP mode. | |
504 | * Otherwise use the mode of the new interface. This can currently | |
505 | * only deal with combinations of APs and STAs. Only one ad-hoc | |
7afbb2f0 | 506 | * interfaces is allowed. |
62c58fb4 BG |
507 | */ |
508 | if (avf->opmode == NL80211_IFTYPE_AP) | |
509 | iter_data->opmode = NL80211_IFTYPE_AP; | |
e4b0b32a BG |
510 | else { |
511 | if (avf->opmode == NL80211_IFTYPE_STATION) | |
512 | iter_data->n_stas++; | |
62c58fb4 BG |
513 | if (iter_data->opmode == NL80211_IFTYPE_UNSPECIFIED) |
514 | iter_data->opmode = avf->opmode; | |
e4b0b32a | 515 | } |
b1ae1edf BG |
516 | } |
517 | ||
cd2c5486 | 518 | void |
e0d687bd | 519 | ath5k_update_bssid_mask_and_opmode(struct ath5k_hw *ah, |
cd2c5486 | 520 | struct ieee80211_vif *vif) |
b1ae1edf | 521 | { |
e0d687bd | 522 | struct ath_common *common = ath5k_hw_common(ah); |
e4b0b32a BG |
523 | struct ath5k_vif_iter_data iter_data; |
524 | u32 rfilt; | |
b1ae1edf BG |
525 | |
526 | /* | |
527 | * Use the hardware MAC address as reference, the hardware uses it | |
528 | * together with the BSSID mask when matching addresses. | |
529 | */ | |
530 | iter_data.hw_macaddr = common->macaddr; | |
93803b33 | 531 | eth_broadcast_addr(iter_data.mask); |
b1ae1edf BG |
532 | iter_data.found_active = false; |
533 | iter_data.need_set_hw_addr = true; | |
62c58fb4 | 534 | iter_data.opmode = NL80211_IFTYPE_UNSPECIFIED; |
e4b0b32a | 535 | iter_data.n_stas = 0; |
b1ae1edf BG |
536 | |
537 | if (vif) | |
e4b0b32a | 538 | ath5k_vif_iter(&iter_data, vif->addr, vif); |
b1ae1edf BG |
539 | |
540 | /* Get list of all active MAC addresses */ | |
8b2c9824 JB |
541 | ieee80211_iterate_active_interfaces_atomic( |
542 | ah->hw, IEEE80211_IFACE_ITER_RESUME_ALL, | |
543 | ath5k_vif_iter, &iter_data); | |
e0d687bd | 544 | memcpy(ah->bssidmask, iter_data.mask, ETH_ALEN); |
b1ae1edf | 545 | |
e0d687bd PR |
546 | ah->opmode = iter_data.opmode; |
547 | if (ah->opmode == NL80211_IFTYPE_UNSPECIFIED) | |
62c58fb4 | 548 | /* Nothing active, default to station mode */ |
e0d687bd | 549 | ah->opmode = NL80211_IFTYPE_STATION; |
62c58fb4 | 550 | |
e0d687bd PR |
551 | ath5k_hw_set_opmode(ah, ah->opmode); |
552 | ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n", | |
553 | ah->opmode, ath_opmode_to_string(ah->opmode)); | |
62c58fb4 | 554 | |
b1ae1edf | 555 | if (iter_data.need_set_hw_addr && iter_data.found_active) |
e0d687bd | 556 | ath5k_hw_set_lladdr(ah, iter_data.active_mac); |
b1ae1edf | 557 | |
e0d687bd PR |
558 | if (ath5k_hw_hasbssidmask(ah)) |
559 | ath5k_hw_set_bssid_mask(ah, ah->bssidmask); | |
b1ae1edf | 560 | |
e4b0b32a BG |
561 | /* Set up RX Filter */ |
562 | if (iter_data.n_stas > 1) { | |
563 | /* If you have multiple STA interfaces connected to | |
564 | * different APs, ARPs are not received (most of the time?) | |
6a2a0e73 | 565 | * Enabling PROMISC appears to fix that problem. |
e4b0b32a | 566 | */ |
e0d687bd | 567 | ah->filter_flags |= AR5K_RX_FILTER_PROM; |
e4b0b32a | 568 | } |
fa1c114f | 569 | |
e0d687bd PR |
570 | rfilt = ah->filter_flags; |
571 | ath5k_hw_set_rx_filter(ah, rfilt); | |
572 | ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt); | |
8a63facc | 573 | } |
fa1c114f | 574 | |
8a63facc | 575 | static inline int |
e0d687bd | 576 | ath5k_hw_to_driver_rix(struct ath5k_hw *ah, int hw_rix) |
8a63facc BC |
577 | { |
578 | int rix; | |
fa1c114f | 579 | |
8a63facc BC |
580 | /* return base rate on errors */ |
581 | if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES, | |
582 | "hw_rix out of bounds: %x\n", hw_rix)) | |
583 | return 0; | |
584 | ||
e0d687bd | 585 | rix = ah->rate_idx[ah->curchan->band][hw_rix]; |
8a63facc BC |
586 | if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix)) |
587 | rix = 0; | |
588 | ||
589 | return rix; | |
590 | } | |
591 | ||
592 | /***************\ | |
593 | * Buffers setup * | |
594 | \***************/ | |
595 | ||
596 | static | |
e0d687bd | 597 | struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_hw *ah, dma_addr_t *skb_addr) |
8a63facc | 598 | { |
e0d687bd | 599 | struct ath_common *common = ath5k_hw_common(ah); |
8a63facc | 600 | struct sk_buff *skb; |
fa1c114f JS |
601 | |
602 | /* | |
8a63facc BC |
603 | * Allocate buffer with headroom_needed space for the |
604 | * fake physical layer header at the start. | |
fa1c114f | 605 | */ |
8a63facc BC |
606 | skb = ath_rxbuf_alloc(common, |
607 | common->rx_bufsize, | |
608 | GFP_ATOMIC); | |
fa1c114f | 609 | |
8a63facc | 610 | if (!skb) { |
e0d687bd | 611 | ATH5K_ERR(ah, "can't alloc skbuff of size %u\n", |
8a63facc BC |
612 | common->rx_bufsize); |
613 | return NULL; | |
fa1c114f JS |
614 | } |
615 | ||
e0d687bd | 616 | *skb_addr = dma_map_single(ah->dev, |
8a63facc | 617 | skb->data, common->rx_bufsize, |
aeae4ac9 FF |
618 | DMA_FROM_DEVICE); |
619 | ||
e0d687bd PR |
620 | if (unlikely(dma_mapping_error(ah->dev, *skb_addr))) { |
621 | ATH5K_ERR(ah, "%s: DMA mapping failed\n", __func__); | |
8a63facc BC |
622 | dev_kfree_skb(skb); |
623 | return NULL; | |
0e149cf5 | 624 | } |
8a63facc BC |
625 | return skb; |
626 | } | |
0e149cf5 | 627 | |
8a63facc | 628 | static int |
e0d687bd | 629 | ath5k_rxbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf) |
8a63facc | 630 | { |
8a63facc BC |
631 | struct sk_buff *skb = bf->skb; |
632 | struct ath5k_desc *ds; | |
633 | int ret; | |
fa1c114f | 634 | |
8a63facc | 635 | if (!skb) { |
e0d687bd | 636 | skb = ath5k_rx_skb_alloc(ah, &bf->skbaddr); |
8a63facc BC |
637 | if (!skb) |
638 | return -ENOMEM; | |
639 | bf->skb = skb; | |
f769c36b BC |
640 | } |
641 | ||
8a63facc BC |
642 | /* |
643 | * Setup descriptors. For receive we always terminate | |
644 | * the descriptor list with a self-linked entry so we'll | |
645 | * not get overrun under high load (as can happen with a | |
646 | * 5212 when ANI processing enables PHY error frames). | |
647 | * | |
648 | * To ensure the last descriptor is self-linked we create | |
649 | * each descriptor as self-linked and add it to the end. As | |
650 | * each additional descriptor is added the previous self-linked | |
651 | * entry is "fixed" naturally. This should be safe even | |
652 | * if DMA is happening. When processing RX interrupts we | |
653 | * never remove/process the last, self-linked, entry on the | |
654 | * descriptor list. This ensures the hardware always has | |
655 | * someplace to write a new frame. | |
656 | */ | |
657 | ds = bf->desc; | |
658 | ds->ds_link = bf->daddr; /* link to self */ | |
659 | ds->ds_data = bf->skbaddr; | |
660 | ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0); | |
fa1c114f | 661 | if (ret) { |
e0d687bd | 662 | ATH5K_ERR(ah, "%s: could not setup RX desc\n", __func__); |
8a63facc | 663 | return ret; |
fa1c114f JS |
664 | } |
665 | ||
e0d687bd PR |
666 | if (ah->rxlink != NULL) |
667 | *ah->rxlink = bf->daddr; | |
668 | ah->rxlink = &ds->ds_link; | |
fa1c114f | 669 | return 0; |
fa1c114f JS |
670 | } |
671 | ||
8a63facc | 672 | static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb) |
fa1c114f | 673 | { |
8a63facc BC |
674 | struct ieee80211_hdr *hdr; |
675 | enum ath5k_pkt_type htype; | |
676 | __le16 fc; | |
fa1c114f | 677 | |
8a63facc BC |
678 | hdr = (struct ieee80211_hdr *)skb->data; |
679 | fc = hdr->frame_control; | |
fa1c114f | 680 | |
8a63facc BC |
681 | if (ieee80211_is_beacon(fc)) |
682 | htype = AR5K_PKT_TYPE_BEACON; | |
683 | else if (ieee80211_is_probe_resp(fc)) | |
684 | htype = AR5K_PKT_TYPE_PROBE_RESP; | |
685 | else if (ieee80211_is_atim(fc)) | |
686 | htype = AR5K_PKT_TYPE_ATIM; | |
687 | else if (ieee80211_is_pspoll(fc)) | |
688 | htype = AR5K_PKT_TYPE_PSPOLL; | |
fa1c114f | 689 | else |
8a63facc | 690 | htype = AR5K_PKT_TYPE_NORMAL; |
fa1c114f | 691 | |
8a63facc | 692 | return htype; |
42639fcd BC |
693 | } |
694 | ||
0967e01e TH |
695 | static struct ieee80211_rate * |
696 | ath5k_get_rate(const struct ieee80211_hw *hw, | |
697 | const struct ieee80211_tx_info *info, | |
698 | struct ath5k_buf *bf, int idx) | |
699 | { | |
700 | /* | |
701 | * convert a ieee80211_tx_rate RC-table entry to | |
702 | * the respective ieee80211_rate struct | |
703 | */ | |
704 | if (bf->rates[idx].idx < 0) { | |
705 | return NULL; | |
706 | } | |
707 | ||
708 | return &hw->wiphy->bands[info->band]->bitrates[ bf->rates[idx].idx ]; | |
709 | } | |
710 | ||
711 | static u16 | |
712 | ath5k_get_rate_hw_value(const struct ieee80211_hw *hw, | |
713 | const struct ieee80211_tx_info *info, | |
714 | struct ath5k_buf *bf, int idx) | |
715 | { | |
716 | struct ieee80211_rate *rate; | |
717 | u16 hw_rate; | |
718 | u8 rc_flags; | |
719 | ||
720 | rate = ath5k_get_rate(hw, info, bf, idx); | |
721 | if (!rate) | |
722 | return 0; | |
723 | ||
724 | rc_flags = bf->rates[idx].flags; | |
725 | hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ? | |
726 | rate->hw_value_short : rate->hw_value; | |
727 | ||
728 | return hw_rate; | |
729 | } | |
730 | ||
8a63facc | 731 | static int |
e0d687bd | 732 | ath5k_txbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf, |
0967e01e TH |
733 | struct ath5k_txq *txq, int padsize, |
734 | struct ieee80211_tx_control *control) | |
fa1c114f | 735 | { |
8a63facc BC |
736 | struct ath5k_desc *ds = bf->desc; |
737 | struct sk_buff *skb = bf->skb; | |
738 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); | |
739 | unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID; | |
740 | struct ieee80211_rate *rate; | |
741 | unsigned int mrr_rate[3], mrr_tries[3]; | |
742 | int i, ret; | |
743 | u16 hw_rate; | |
744 | u16 cts_rate = 0; | |
745 | u16 duration = 0; | |
746 | u8 rc_flags; | |
fa1c114f | 747 | |
8a63facc | 748 | flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK; |
fa1c114f | 749 | |
8a63facc | 750 | /* XXX endianness */ |
e0d687bd | 751 | bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len, |
aeae4ac9 | 752 | DMA_TO_DEVICE); |
fa1c114f | 753 | |
b499abdc JG |
754 | if (dma_mapping_error(ah->dev, bf->skbaddr)) |
755 | return -ENOSPC; | |
756 | ||
0967e01e TH |
757 | ieee80211_get_tx_rates(info->control.vif, (control) ? control->sta : NULL, skb, bf->rates, |
758 | ARRAY_SIZE(bf->rates)); | |
759 | ||
760 | rate = ath5k_get_rate(ah->hw, info, bf, 0); | |
761 | ||
29ad2fac JL |
762 | if (!rate) { |
763 | ret = -EINVAL; | |
764 | goto err_unmap; | |
765 | } | |
fa1c114f | 766 | |
8a63facc BC |
767 | if (info->flags & IEEE80211_TX_CTL_NO_ACK) |
768 | flags |= AR5K_TXDESC_NOACK; | |
fa1c114f | 769 | |
410d13a6 | 770 | rc_flags = bf->rates[0].flags; |
0967e01e TH |
771 | |
772 | hw_rate = ath5k_get_rate_hw_value(ah->hw, info, bf, 0); | |
42639fcd | 773 | |
8a63facc BC |
774 | pktlen = skb->len; |
775 | ||
776 | /* FIXME: If we are in g mode and rate is a CCK rate | |
777 | * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta | |
778 | * from tx power (value is in dB units already) */ | |
779 | if (info->control.hw_key) { | |
780 | keyidx = info->control.hw_key->hw_key_idx; | |
781 | pktlen += info->control.hw_key->icv_len; | |
782 | } | |
783 | if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) { | |
784 | flags |= AR5K_TXDESC_RTSENA; | |
e0d687bd PR |
785 | cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value; |
786 | duration = le16_to_cpu(ieee80211_rts_duration(ah->hw, | |
b1ae1edf | 787 | info->control.vif, pktlen, info)); |
8a63facc BC |
788 | } |
789 | if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { | |
790 | flags |= AR5K_TXDESC_CTSENA; | |
e0d687bd PR |
791 | cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value; |
792 | duration = le16_to_cpu(ieee80211_ctstoself_duration(ah->hw, | |
b1ae1edf | 793 | info->control.vif, pktlen, info)); |
8a63facc | 794 | } |
0967e01e | 795 | |
8a63facc BC |
796 | ret = ah->ah_setup_tx_desc(ah, ds, pktlen, |
797 | ieee80211_get_hdrlen_from_skb(skb), padsize, | |
798 | get_hw_packet_type(skb), | |
987af54f | 799 | (ah->ah_txpower.txp_requested * 2), |
8a63facc | 800 | hw_rate, |
0967e01e | 801 | bf->rates[0].count, keyidx, ah->ah_tx_ant, flags, |
8a63facc BC |
802 | cts_rate, duration); |
803 | if (ret) | |
804 | goto err_unmap; | |
805 | ||
86f62d9b NK |
806 | /* Set up MRR descriptor */ |
807 | if (ah->ah_capabilities.cap_has_mrr_support) { | |
808 | memset(mrr_rate, 0, sizeof(mrr_rate)); | |
809 | memset(mrr_tries, 0, sizeof(mrr_tries)); | |
0967e01e | 810 | |
86f62d9b | 811 | for (i = 0; i < 3; i++) { |
0967e01e TH |
812 | |
813 | rate = ath5k_get_rate(ah->hw, info, bf, i); | |
86f62d9b NK |
814 | if (!rate) |
815 | break; | |
fa1c114f | 816 | |
0967e01e TH |
817 | mrr_rate[i] = ath5k_get_rate_hw_value(ah->hw, info, bf, i); |
818 | mrr_tries[i] = bf->rates[i].count; | |
86f62d9b | 819 | } |
fa1c114f | 820 | |
86f62d9b NK |
821 | ath5k_hw_setup_mrr_tx_desc(ah, ds, |
822 | mrr_rate[0], mrr_tries[0], | |
823 | mrr_rate[1], mrr_tries[1], | |
824 | mrr_rate[2], mrr_tries[2]); | |
825 | } | |
fa1c114f | 826 | |
8a63facc BC |
827 | ds->ds_link = 0; |
828 | ds->ds_data = bf->skbaddr; | |
63266a65 | 829 | |
8a63facc BC |
830 | spin_lock_bh(&txq->lock); |
831 | list_add_tail(&bf->list, &txq->q); | |
925e0b06 | 832 | txq->txq_len++; |
8a63facc BC |
833 | if (txq->link == NULL) /* is this first packet? */ |
834 | ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr); | |
835 | else /* no, so only link it */ | |
836 | *txq->link = bf->daddr; | |
63266a65 | 837 | |
8a63facc BC |
838 | txq->link = &ds->ds_link; |
839 | ath5k_hw_start_tx_dma(ah, txq->qnum); | |
840 | mmiowb(); | |
841 | spin_unlock_bh(&txq->lock); | |
842 | ||
843 | return 0; | |
844 | err_unmap: | |
e0d687bd | 845 | dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE); |
8a63facc | 846 | return ret; |
63266a65 BR |
847 | } |
848 | ||
8a63facc BC |
849 | /*******************\ |
850 | * Descriptors setup * | |
851 | \*******************/ | |
852 | ||
d8ee398d | 853 | static int |
e0d687bd | 854 | ath5k_desc_alloc(struct ath5k_hw *ah) |
fa1c114f | 855 | { |
8a63facc BC |
856 | struct ath5k_desc *ds; |
857 | struct ath5k_buf *bf; | |
858 | dma_addr_t da; | |
859 | unsigned int i; | |
860 | int ret; | |
d8ee398d | 861 | |
8a63facc | 862 | /* allocate descriptors */ |
e0d687bd | 863 | ah->desc_len = sizeof(struct ath5k_desc) * |
8a63facc | 864 | (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1); |
aeae4ac9 | 865 | |
e0d687bd PR |
866 | ah->desc = dma_alloc_coherent(ah->dev, ah->desc_len, |
867 | &ah->desc_daddr, GFP_KERNEL); | |
868 | if (ah->desc == NULL) { | |
869 | ATH5K_ERR(ah, "can't allocate descriptors\n"); | |
8a63facc BC |
870 | ret = -ENOMEM; |
871 | goto err; | |
872 | } | |
e0d687bd PR |
873 | ds = ah->desc; |
874 | da = ah->desc_daddr; | |
875 | ATH5K_DBG(ah, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n", | |
876 | ds, ah->desc_len, (unsigned long long)ah->desc_daddr); | |
fa1c114f | 877 | |
8a63facc BC |
878 | bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF, |
879 | sizeof(struct ath5k_buf), GFP_KERNEL); | |
880 | if (bf == NULL) { | |
e0d687bd | 881 | ATH5K_ERR(ah, "can't allocate bufptr\n"); |
8a63facc BC |
882 | ret = -ENOMEM; |
883 | goto err_free; | |
884 | } | |
e0d687bd | 885 | ah->bufptr = bf; |
fa1c114f | 886 | |
e0d687bd | 887 | INIT_LIST_HEAD(&ah->rxbuf); |
8a63facc BC |
888 | for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) { |
889 | bf->desc = ds; | |
890 | bf->daddr = da; | |
e0d687bd | 891 | list_add_tail(&bf->list, &ah->rxbuf); |
8a63facc | 892 | } |
d8ee398d | 893 | |
e0d687bd PR |
894 | INIT_LIST_HEAD(&ah->txbuf); |
895 | ah->txbuf_len = ATH_TXBUF; | |
e4bbf2f5 | 896 | for (i = 0; i < ATH_TXBUF; i++, bf++, ds++, da += sizeof(*ds)) { |
8a63facc BC |
897 | bf->desc = ds; |
898 | bf->daddr = da; | |
e0d687bd | 899 | list_add_tail(&bf->list, &ah->txbuf); |
fa1c114f JS |
900 | } |
901 | ||
b1ae1edf | 902 | /* beacon buffers */ |
e0d687bd | 903 | INIT_LIST_HEAD(&ah->bcbuf); |
b1ae1edf BG |
904 | for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) { |
905 | bf->desc = ds; | |
906 | bf->daddr = da; | |
e0d687bd | 907 | list_add_tail(&bf->list, &ah->bcbuf); |
b1ae1edf | 908 | } |
fa1c114f | 909 | |
8a63facc BC |
910 | return 0; |
911 | err_free: | |
e0d687bd | 912 | dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr); |
8a63facc | 913 | err: |
e0d687bd | 914 | ah->desc = NULL; |
8a63facc BC |
915 | return ret; |
916 | } | |
fa1c114f | 917 | |
cd2c5486 | 918 | void |
e0d687bd | 919 | ath5k_txbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf) |
cd2c5486 BR |
920 | { |
921 | BUG_ON(!bf); | |
922 | if (!bf->skb) | |
923 | return; | |
e0d687bd | 924 | dma_unmap_single(ah->dev, bf->skbaddr, bf->skb->len, |
cd2c5486 | 925 | DMA_TO_DEVICE); |
596ab5ec | 926 | ieee80211_free_txskb(ah->hw, bf->skb); |
cd2c5486 BR |
927 | bf->skb = NULL; |
928 | bf->skbaddr = 0; | |
929 | bf->desc->ds_data = 0; | |
930 | } | |
931 | ||
932 | void | |
e0d687bd | 933 | ath5k_rxbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf) |
cd2c5486 | 934 | { |
cd2c5486 BR |
935 | struct ath_common *common = ath5k_hw_common(ah); |
936 | ||
937 | BUG_ON(!bf); | |
938 | if (!bf->skb) | |
939 | return; | |
e0d687bd | 940 | dma_unmap_single(ah->dev, bf->skbaddr, common->rx_bufsize, |
cd2c5486 BR |
941 | DMA_FROM_DEVICE); |
942 | dev_kfree_skb_any(bf->skb); | |
943 | bf->skb = NULL; | |
944 | bf->skbaddr = 0; | |
945 | bf->desc->ds_data = 0; | |
946 | } | |
947 | ||
8a63facc | 948 | static void |
e0d687bd | 949 | ath5k_desc_free(struct ath5k_hw *ah) |
8a63facc BC |
950 | { |
951 | struct ath5k_buf *bf; | |
d8ee398d | 952 | |
e0d687bd PR |
953 | list_for_each_entry(bf, &ah->txbuf, list) |
954 | ath5k_txbuf_free_skb(ah, bf); | |
955 | list_for_each_entry(bf, &ah->rxbuf, list) | |
956 | ath5k_rxbuf_free_skb(ah, bf); | |
957 | list_for_each_entry(bf, &ah->bcbuf, list) | |
958 | ath5k_txbuf_free_skb(ah, bf); | |
d8ee398d | 959 | |
8a63facc | 960 | /* Free memory associated with all descriptors */ |
e0d687bd PR |
961 | dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr); |
962 | ah->desc = NULL; | |
963 | ah->desc_daddr = 0; | |
d8ee398d | 964 | |
e0d687bd PR |
965 | kfree(ah->bufptr); |
966 | ah->bufptr = NULL; | |
fa1c114f JS |
967 | } |
968 | ||
8a63facc BC |
969 | |
970 | /**************\ | |
971 | * Queues setup * | |
972 | \**************/ | |
973 | ||
974 | static struct ath5k_txq * | |
e0d687bd | 975 | ath5k_txq_setup(struct ath5k_hw *ah, |
8a63facc | 976 | int qtype, int subtype) |
fa1c114f | 977 | { |
8a63facc BC |
978 | struct ath5k_txq *txq; |
979 | struct ath5k_txq_info qi = { | |
980 | .tqi_subtype = subtype, | |
de8af455 BR |
981 | /* XXX: default values not correct for B and XR channels, |
982 | * but who cares? */ | |
983 | .tqi_aifs = AR5K_TUNE_AIFS, | |
984 | .tqi_cw_min = AR5K_TUNE_CWMIN, | |
985 | .tqi_cw_max = AR5K_TUNE_CWMAX | |
8a63facc BC |
986 | }; |
987 | int qnum; | |
d8ee398d | 988 | |
e30eb4ab | 989 | /* |
8a63facc BC |
990 | * Enable interrupts only for EOL and DESC conditions. |
991 | * We mark tx descriptors to receive a DESC interrupt | |
992 | * when a tx queue gets deep; otherwise we wait for the | |
993 | * EOL to reap descriptors. Note that this is done to | |
994 | * reduce interrupt load and this only defers reaping | |
995 | * descriptors, never transmitting frames. Aside from | |
996 | * reducing interrupts this also permits more concurrency. | |
997 | * The only potential downside is if the tx queue backs | |
998 | * up in which case the top half of the kernel may backup | |
999 | * due to a lack of tx descriptors. | |
e30eb4ab | 1000 | */ |
8a63facc BC |
1001 | qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE | |
1002 | AR5K_TXQ_FLAG_TXDESCINT_ENABLE; | |
1003 | qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi); | |
1004 | if (qnum < 0) { | |
1005 | /* | |
1006 | * NB: don't print a message, this happens | |
1007 | * normally on parts with too few tx queues | |
1008 | */ | |
1009 | return ERR_PTR(qnum); | |
1010 | } | |
e0d687bd | 1011 | txq = &ah->txqs[qnum]; |
8a63facc BC |
1012 | if (!txq->setup) { |
1013 | txq->qnum = qnum; | |
1014 | txq->link = NULL; | |
1015 | INIT_LIST_HEAD(&txq->q); | |
1016 | spin_lock_init(&txq->lock); | |
1017 | txq->setup = true; | |
925e0b06 | 1018 | txq->txq_len = 0; |
81266baf | 1019 | txq->txq_max = ATH5K_TXQ_LEN_MAX; |
4edd761f | 1020 | txq->txq_poll_mark = false; |
923e5b3d | 1021 | txq->txq_stuck = 0; |
8a63facc | 1022 | } |
e0d687bd | 1023 | return &ah->txqs[qnum]; |
fa1c114f JS |
1024 | } |
1025 | ||
8a63facc BC |
1026 | static int |
1027 | ath5k_beaconq_setup(struct ath5k_hw *ah) | |
fa1c114f | 1028 | { |
8a63facc | 1029 | struct ath5k_txq_info qi = { |
de8af455 BR |
1030 | /* XXX: default values not correct for B and XR channels, |
1031 | * but who cares? */ | |
1032 | .tqi_aifs = AR5K_TUNE_AIFS, | |
1033 | .tqi_cw_min = AR5K_TUNE_CWMIN, | |
1034 | .tqi_cw_max = AR5K_TUNE_CWMAX, | |
8a63facc BC |
1035 | /* NB: for dynamic turbo, don't enable any other interrupts */ |
1036 | .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE | |
1037 | }; | |
d8ee398d | 1038 | |
8a63facc | 1039 | return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi); |
fa1c114f JS |
1040 | } |
1041 | ||
8a63facc | 1042 | static int |
e0d687bd | 1043 | ath5k_beaconq_config(struct ath5k_hw *ah) |
fa1c114f | 1044 | { |
8a63facc BC |
1045 | struct ath5k_txq_info qi; |
1046 | int ret; | |
fa1c114f | 1047 | |
e0d687bd | 1048 | ret = ath5k_hw_get_tx_queueprops(ah, ah->bhalq, &qi); |
8a63facc BC |
1049 | if (ret) |
1050 | goto err; | |
fa1c114f | 1051 | |
e0d687bd PR |
1052 | if (ah->opmode == NL80211_IFTYPE_AP || |
1053 | ah->opmode == NL80211_IFTYPE_MESH_POINT) { | |
8a63facc BC |
1054 | /* |
1055 | * Always burst out beacon and CAB traffic | |
1056 | * (aifs = cwmin = cwmax = 0) | |
1057 | */ | |
1058 | qi.tqi_aifs = 0; | |
1059 | qi.tqi_cw_min = 0; | |
1060 | qi.tqi_cw_max = 0; | |
e0d687bd | 1061 | } else if (ah->opmode == NL80211_IFTYPE_ADHOC) { |
8a63facc BC |
1062 | /* |
1063 | * Adhoc mode; backoff between 0 and (2 * cw_min). | |
1064 | */ | |
1065 | qi.tqi_aifs = 0; | |
1066 | qi.tqi_cw_min = 0; | |
de8af455 | 1067 | qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN; |
8a63facc | 1068 | } |
fa1c114f | 1069 | |
e0d687bd | 1070 | ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, |
8a63facc BC |
1071 | "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n", |
1072 | qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max); | |
fa1c114f | 1073 | |
e0d687bd | 1074 | ret = ath5k_hw_set_tx_queueprops(ah, ah->bhalq, &qi); |
8a63facc | 1075 | if (ret) { |
e0d687bd | 1076 | ATH5K_ERR(ah, "%s: unable to update parameters for beacon " |
8a63facc BC |
1077 | "hardware queue!\n", __func__); |
1078 | goto err; | |
1079 | } | |
e0d687bd | 1080 | ret = ath5k_hw_reset_tx_queue(ah, ah->bhalq); /* push to h/w */ |
8a63facc BC |
1081 | if (ret) |
1082 | goto err; | |
b7266047 | 1083 | |
8a63facc BC |
1084 | /* reconfigure cabq with ready time to 80% of beacon_interval */ |
1085 | ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi); | |
1086 | if (ret) | |
1087 | goto err; | |
b7266047 | 1088 | |
e0d687bd | 1089 | qi.tqi_ready_time = (ah->bintval * 80) / 100; |
8a63facc BC |
1090 | ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi); |
1091 | if (ret) | |
1092 | goto err; | |
b7266047 | 1093 | |
8a63facc BC |
1094 | ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB); |
1095 | err: | |
1096 | return ret; | |
d8ee398d LR |
1097 | } |
1098 | ||
80dac9ee NK |
1099 | /** |
1100 | * ath5k_drain_tx_buffs - Empty tx buffers | |
1101 | * | |
e0d687bd | 1102 | * @ah The &struct ath5k_hw |
80dac9ee NK |
1103 | * |
1104 | * Empty tx buffers from all queues in preparation | |
1105 | * of a reset or during shutdown. | |
1106 | * | |
1107 | * NB: this assumes output has been stopped and | |
1108 | * we do not need to block ath5k_tx_tasklet | |
1109 | */ | |
8a63facc | 1110 | static void |
e0d687bd | 1111 | ath5k_drain_tx_buffs(struct ath5k_hw *ah) |
8a63facc | 1112 | { |
80dac9ee | 1113 | struct ath5k_txq *txq; |
8a63facc | 1114 | struct ath5k_buf *bf, *bf0; |
80dac9ee | 1115 | int i; |
b6ea0356 | 1116 | |
e0d687bd PR |
1117 | for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) { |
1118 | if (ah->txqs[i].setup) { | |
1119 | txq = &ah->txqs[i]; | |
80dac9ee NK |
1120 | spin_lock_bh(&txq->lock); |
1121 | list_for_each_entry_safe(bf, bf0, &txq->q, list) { | |
e0d687bd | 1122 | ath5k_debug_printtxbuf(ah, bf); |
b6ea0356 | 1123 | |
e0d687bd | 1124 | ath5k_txbuf_free_skb(ah, bf); |
fa1c114f | 1125 | |
6617942e | 1126 | spin_lock(&ah->txbuflock); |
e0d687bd PR |
1127 | list_move_tail(&bf->list, &ah->txbuf); |
1128 | ah->txbuf_len++; | |
80dac9ee | 1129 | txq->txq_len--; |
6617942e | 1130 | spin_unlock(&ah->txbuflock); |
8a63facc | 1131 | } |
80dac9ee NK |
1132 | txq->link = NULL; |
1133 | txq->txq_poll_mark = false; | |
1134 | spin_unlock_bh(&txq->lock); | |
1135 | } | |
0452d4a5 | 1136 | } |
fa1c114f JS |
1137 | } |
1138 | ||
8a63facc | 1139 | static void |
e0d687bd | 1140 | ath5k_txq_release(struct ath5k_hw *ah) |
2ac2927a | 1141 | { |
e0d687bd | 1142 | struct ath5k_txq *txq = ah->txqs; |
8a63facc | 1143 | unsigned int i; |
2ac2927a | 1144 | |
e0d687bd | 1145 | for (i = 0; i < ARRAY_SIZE(ah->txqs); i++, txq++) |
8a63facc | 1146 | if (txq->setup) { |
e0d687bd | 1147 | ath5k_hw_release_tx_queue(ah, txq->qnum); |
8a63facc BC |
1148 | txq->setup = false; |
1149 | } | |
1150 | } | |
2ac2927a | 1151 | |
2ac2927a | 1152 | |
8a63facc BC |
1153 | /*************\ |
1154 | * RX Handling * | |
1155 | \*************/ | |
2ac2927a | 1156 | |
8a63facc BC |
1157 | /* |
1158 | * Enable the receive h/w following a reset. | |
1159 | */ | |
fa1c114f | 1160 | static int |
e0d687bd | 1161 | ath5k_rx_start(struct ath5k_hw *ah) |
fa1c114f | 1162 | { |
8a63facc BC |
1163 | struct ath_common *common = ath5k_hw_common(ah); |
1164 | struct ath5k_buf *bf; | |
1165 | int ret; | |
fa1c114f | 1166 | |
8a63facc | 1167 | common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz); |
fa1c114f | 1168 | |
e0d687bd | 1169 | ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n", |
8a63facc | 1170 | common->cachelsz, common->rx_bufsize); |
2f7fe870 | 1171 | |
e0d687bd PR |
1172 | spin_lock_bh(&ah->rxbuflock); |
1173 | ah->rxlink = NULL; | |
1174 | list_for_each_entry(bf, &ah->rxbuf, list) { | |
1175 | ret = ath5k_rxbuf_setup(ah, bf); | |
8a63facc | 1176 | if (ret != 0) { |
e0d687bd | 1177 | spin_unlock_bh(&ah->rxbuflock); |
8a63facc BC |
1178 | goto err; |
1179 | } | |
2f7fe870 | 1180 | } |
e0d687bd | 1181 | bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list); |
8a63facc | 1182 | ath5k_hw_set_rxdp(ah, bf->daddr); |
e0d687bd | 1183 | spin_unlock_bh(&ah->rxbuflock); |
2f7fe870 | 1184 | |
8a63facc | 1185 | ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */ |
e0d687bd | 1186 | ath5k_update_bssid_mask_and_opmode(ah, NULL); /* set filters, etc. */ |
8a63facc | 1187 | ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */ |
fa1c114f JS |
1188 | |
1189 | return 0; | |
8a63facc | 1190 | err: |
fa1c114f JS |
1191 | return ret; |
1192 | } | |
1193 | ||
8a63facc | 1194 | /* |
80dac9ee NK |
1195 | * Disable the receive logic on PCU (DRU) |
1196 | * In preparation for a shutdown. | |
1197 | * | |
1198 | * Note: Doesn't stop rx DMA, ath5k_hw_dma_stop | |
1199 | * does. | |
8a63facc BC |
1200 | */ |
1201 | static void | |
e0d687bd | 1202 | ath5k_rx_stop(struct ath5k_hw *ah) |
fa1c114f | 1203 | { |
fa1c114f | 1204 | |
8a63facc | 1205 | ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */ |
80dac9ee | 1206 | ath5k_hw_stop_rx_pcu(ah); /* disable PCU */ |
fa1c114f | 1207 | |
e0d687bd | 1208 | ath5k_debug_printrxbuffs(ah); |
8a63facc | 1209 | } |
fa1c114f | 1210 | |
8a63facc | 1211 | static unsigned int |
e0d687bd | 1212 | ath5k_rx_decrypted(struct ath5k_hw *ah, struct sk_buff *skb, |
8a63facc BC |
1213 | struct ath5k_rx_status *rs) |
1214 | { | |
8a63facc BC |
1215 | struct ath_common *common = ath5k_hw_common(ah); |
1216 | struct ieee80211_hdr *hdr = (void *)skb->data; | |
1217 | unsigned int keyix, hlen; | |
fa1c114f | 1218 | |
8a63facc BC |
1219 | if (!(rs->rs_status & AR5K_RXERR_DECRYPT) && |
1220 | rs->rs_keyix != AR5K_RXKEYIX_INVALID) | |
1221 | return RX_FLAG_DECRYPTED; | |
fa1c114f | 1222 | |
8a63facc BC |
1223 | /* Apparently when a default key is used to decrypt the packet |
1224 | the hw does not set the index used to decrypt. In such cases | |
1225 | get the index from the packet. */ | |
1226 | hlen = ieee80211_hdrlen(hdr->frame_control); | |
1227 | if (ieee80211_has_protected(hdr->frame_control) && | |
1228 | !(rs->rs_status & AR5K_RXERR_DECRYPT) && | |
1229 | skb->len >= hlen + 4) { | |
1230 | keyix = skb->data[hlen + 3] >> 6; | |
1231 | ||
1232 | if (test_bit(keyix, common->keymap)) | |
1233 | return RX_FLAG_DECRYPTED; | |
1234 | } | |
fa1c114f JS |
1235 | |
1236 | return 0; | |
fa1c114f JS |
1237 | } |
1238 | ||
8a63facc | 1239 | |
fa1c114f | 1240 | static void |
e0d687bd | 1241 | ath5k_check_ibss_tsf(struct ath5k_hw *ah, struct sk_buff *skb, |
8a63facc | 1242 | struct ieee80211_rx_status *rxs) |
fa1c114f | 1243 | { |
8a63facc BC |
1244 | u64 tsf, bc_tstamp; |
1245 | u32 hw_tu; | |
1246 | struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; | |
fa1c114f | 1247 | |
d44efe21 | 1248 | if (le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS) { |
8a63facc BC |
1249 | /* |
1250 | * Received an IBSS beacon with the same BSSID. Hardware *must* | |
1251 | * have updated the local TSF. We have to work around various | |
1252 | * hardware bugs, though... | |
1253 | */ | |
e0d687bd | 1254 | tsf = ath5k_hw_get_tsf64(ah); |
8a63facc BC |
1255 | bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp); |
1256 | hw_tu = TSF_TO_TU(tsf); | |
fa1c114f | 1257 | |
e0d687bd | 1258 | ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, |
8a63facc BC |
1259 | "beacon %llx mactime %llx (diff %lld) tsf now %llx\n", |
1260 | (unsigned long long)bc_tstamp, | |
1261 | (unsigned long long)rxs->mactime, | |
1262 | (unsigned long long)(rxs->mactime - bc_tstamp), | |
1263 | (unsigned long long)tsf); | |
fa1c114f | 1264 | |
8a63facc BC |
1265 | /* |
1266 | * Sometimes the HW will give us a wrong tstamp in the rx | |
1267 | * status, causing the timestamp extension to go wrong. | |
1268 | * (This seems to happen especially with beacon frames bigger | |
1269 | * than 78 byte (incl. FCS)) | |
1270 | * But we know that the receive timestamp must be later than the | |
1271 | * timestamp of the beacon since HW must have synced to that. | |
1272 | * | |
1273 | * NOTE: here we assume mactime to be after the frame was | |
1274 | * received, not like mac80211 which defines it at the start. | |
1275 | */ | |
1276 | if (bc_tstamp > rxs->mactime) { | |
e0d687bd | 1277 | ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, |
8a63facc BC |
1278 | "fixing mactime from %llx to %llx\n", |
1279 | (unsigned long long)rxs->mactime, | |
1280 | (unsigned long long)tsf); | |
1281 | rxs->mactime = tsf; | |
1282 | } | |
fa1c114f | 1283 | |
8a63facc BC |
1284 | /* |
1285 | * Local TSF might have moved higher than our beacon timers, | |
1286 | * in that case we have to update them to continue sending | |
1287 | * beacons. This also takes care of synchronizing beacon sending | |
1288 | * times with other stations. | |
1289 | */ | |
e0d687bd PR |
1290 | if (hw_tu >= ah->nexttbtt) |
1291 | ath5k_beacon_update_timers(ah, bc_tstamp); | |
7f896126 BR |
1292 | |
1293 | /* Check if the beacon timers are still correct, because a TSF | |
1294 | * update might have created a window between them - for a | |
1295 | * longer description see the comment of this function: */ | |
e0d687bd PR |
1296 | if (!ath5k_hw_check_beacon_timers(ah, ah->bintval)) { |
1297 | ath5k_beacon_update_timers(ah, bc_tstamp); | |
1298 | ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, | |
7f896126 BR |
1299 | "fixed beacon timers after beacon receive\n"); |
1300 | } | |
8a63facc BC |
1301 | } |
1302 | } | |
fa1c114f | 1303 | |
8a63facc BC |
1304 | /* |
1305 | * Compute padding position. skb must contain an IEEE 802.11 frame | |
1306 | */ | |
1307 | static int ath5k_common_padpos(struct sk_buff *skb) | |
fa1c114f | 1308 | { |
e4bbf2f5 | 1309 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
8a63facc BC |
1310 | __le16 frame_control = hdr->frame_control; |
1311 | int padpos = 24; | |
fa1c114f | 1312 | |
d2c7f773 | 1313 | if (ieee80211_has_a4(frame_control)) |
8a63facc | 1314 | padpos += ETH_ALEN; |
d2c7f773 PR |
1315 | |
1316 | if (ieee80211_is_data_qos(frame_control)) | |
8a63facc | 1317 | padpos += IEEE80211_QOS_CTL_LEN; |
8a63facc BC |
1318 | |
1319 | return padpos; | |
fa1c114f JS |
1320 | } |
1321 | ||
8a63facc BC |
1322 | /* |
1323 | * This function expects an 802.11 frame and returns the number of | |
1324 | * bytes added, or -1 if we don't have enough header room. | |
1325 | */ | |
1326 | static int ath5k_add_padding(struct sk_buff *skb) | |
fa1c114f | 1327 | { |
8a63facc BC |
1328 | int padpos = ath5k_common_padpos(skb); |
1329 | int padsize = padpos & 3; | |
fa1c114f | 1330 | |
e4bbf2f5 | 1331 | if (padsize && skb->len > padpos) { |
fa1c114f | 1332 | |
8a63facc BC |
1333 | if (skb_headroom(skb) < padsize) |
1334 | return -1; | |
fa1c114f | 1335 | |
8a63facc | 1336 | skb_push(skb, padsize); |
e4bbf2f5 | 1337 | memmove(skb->data, skb->data + padsize, padpos); |
8a63facc BC |
1338 | return padsize; |
1339 | } | |
a951ae21 | 1340 | |
8a63facc BC |
1341 | return 0; |
1342 | } | |
fa1c114f | 1343 | |
8a63facc BC |
1344 | /* |
1345 | * The MAC header is padded to have 32-bit boundary if the | |
1346 | * packet payload is non-zero. The general calculation for | |
1347 | * padsize would take into account odd header lengths: | |
1348 | * padsize = 4 - (hdrlen & 3); however, since only | |
1349 | * even-length headers are used, padding can only be 0 or 2 | |
1350 | * bytes and we can optimize this a bit. We must not try to | |
1351 | * remove padding from short control frames that do not have a | |
1352 | * payload. | |
1353 | * | |
1354 | * This function expects an 802.11 frame and returns the number of | |
1355 | * bytes removed. | |
1356 | */ | |
1357 | static int ath5k_remove_padding(struct sk_buff *skb) | |
1358 | { | |
1359 | int padpos = ath5k_common_padpos(skb); | |
1360 | int padsize = padpos & 3; | |
6d91e1d8 | 1361 | |
e4bbf2f5 | 1362 | if (padsize && skb->len >= padpos + padsize) { |
8a63facc BC |
1363 | memmove(skb->data + padsize, skb->data, padpos); |
1364 | skb_pull(skb, padsize); | |
1365 | return padsize; | |
fa1c114f | 1366 | } |
a951ae21 | 1367 | |
8a63facc | 1368 | return 0; |
fa1c114f JS |
1369 | } |
1370 | ||
1371 | static void | |
e0d687bd | 1372 | ath5k_receive_frame(struct ath5k_hw *ah, struct sk_buff *skb, |
8a63facc | 1373 | struct ath5k_rx_status *rs) |
fa1c114f | 1374 | { |
8a63facc | 1375 | struct ieee80211_rx_status *rxs; |
d44efe21 | 1376 | struct ath_common *common = ath5k_hw_common(ah); |
8a63facc BC |
1377 | |
1378 | ath5k_remove_padding(skb); | |
1379 | ||
1380 | rxs = IEEE80211_SKB_RXCB(skb); | |
1381 | ||
1382 | rxs->flag = 0; | |
1383 | if (unlikely(rs->rs_status & AR5K_RXERR_MIC)) | |
1384 | rxs->flag |= RX_FLAG_MMIC_ERROR; | |
41881354 MV |
1385 | if (unlikely(rs->rs_status & AR5K_RXERR_CRC)) |
1386 | rxs->flag |= RX_FLAG_FAILED_FCS_CRC; | |
1387 | ||
fa1c114f JS |
1388 | |
1389 | /* | |
8a63facc BC |
1390 | * always extend the mac timestamp, since this information is |
1391 | * also needed for proper IBSS merging. | |
1392 | * | |
1393 | * XXX: it might be too late to do it here, since rs_tstamp is | |
1394 | * 15bit only. that means TSF extension has to be done within | |
1395 | * 32768usec (about 32ms). it might be necessary to move this to | |
1396 | * the interrupt handler, like it is done in madwifi. | |
fa1c114f | 1397 | */ |
e0d687bd | 1398 | rxs->mactime = ath5k_extend_tsf(ah, rs->rs_tstamp); |
e576defd | 1399 | rxs->flag |= RX_FLAG_MACTIME_END; |
fa1c114f | 1400 | |
e0d687bd PR |
1401 | rxs->freq = ah->curchan->center_freq; |
1402 | rxs->band = ah->curchan->band; | |
fa1c114f | 1403 | |
e0d687bd | 1404 | rxs->signal = ah->ah_noise_floor + rs->rs_rssi; |
fa1c114f | 1405 | |
8a63facc | 1406 | rxs->antenna = rs->rs_antenna; |
fa1c114f | 1407 | |
8a63facc | 1408 | if (rs->rs_antenna > 0 && rs->rs_antenna < 5) |
e0d687bd | 1409 | ah->stats.antenna_rx[rs->rs_antenna]++; |
8a63facc | 1410 | else |
e0d687bd | 1411 | ah->stats.antenna_rx[0]++; /* invalid */ |
fa1c114f | 1412 | |
e0d687bd PR |
1413 | rxs->rate_idx = ath5k_hw_to_driver_rix(ah, rs->rs_rate); |
1414 | rxs->flag |= ath5k_rx_decrypted(ah, skb, rs); | |
312a6443 SW |
1415 | switch (ah->ah_bwmode) { |
1416 | case AR5K_BWMODE_5MHZ: | |
1417 | rxs->flag |= RX_FLAG_5MHZ; | |
1418 | break; | |
1419 | case AR5K_BWMODE_10MHZ: | |
1420 | rxs->flag |= RX_FLAG_10MHZ; | |
1421 | break; | |
1422 | default: | |
1423 | break; | |
1424 | } | |
fa1c114f | 1425 | |
e6938ea4 | 1426 | if (rs->rs_rate == |
e0d687bd | 1427 | ah->sbands[ah->curchan->band].bitrates[rxs->rate_idx].hw_value_short) |
8a63facc | 1428 | rxs->flag |= RX_FLAG_SHORTPRE; |
fa1c114f | 1429 | |
e0d687bd | 1430 | trace_ath5k_rx(ah, skb); |
fa1c114f | 1431 | |
d44efe21 | 1432 | if (ath_is_mybeacon(common, (struct ieee80211_hdr *)skb->data)) { |
46f26ddf | 1433 | ewma_beacon_rssi_add(&ah->ah_beacon_rssi_avg, rs->rs_rssi); |
fa1c114f | 1434 | |
d44efe21 OR |
1435 | /* check beacons in IBSS mode */ |
1436 | if (ah->opmode == NL80211_IFTYPE_ADHOC) | |
1437 | ath5k_check_ibss_tsf(ah, skb, rxs); | |
1438 | } | |
fa1c114f | 1439 | |
e0d687bd | 1440 | ieee80211_rx(ah->hw, skb); |
8a63facc | 1441 | } |
fa1c114f | 1442 | |
8a63facc BC |
1443 | /** ath5k_frame_receive_ok() - Do we want to receive this frame or not? |
1444 | * | |
1445 | * Check if we want to further process this frame or not. Also update | |
1446 | * statistics. Return true if we want this frame, false if not. | |
fa1c114f | 1447 | */ |
8a63facc | 1448 | static bool |
e0d687bd | 1449 | ath5k_receive_frame_ok(struct ath5k_hw *ah, struct ath5k_rx_status *rs) |
fa1c114f | 1450 | { |
e0d687bd PR |
1451 | ah->stats.rx_all_count++; |
1452 | ah->stats.rx_bytes_count += rs->rs_datalen; | |
fa1c114f | 1453 | |
8a63facc | 1454 | if (unlikely(rs->rs_status)) { |
41881354 MV |
1455 | unsigned int filters; |
1456 | ||
8a63facc | 1457 | if (rs->rs_status & AR5K_RXERR_CRC) |
e0d687bd | 1458 | ah->stats.rxerr_crc++; |
8a63facc | 1459 | if (rs->rs_status & AR5K_RXERR_FIFO) |
e0d687bd | 1460 | ah->stats.rxerr_fifo++; |
8a63facc | 1461 | if (rs->rs_status & AR5K_RXERR_PHY) { |
e0d687bd | 1462 | ah->stats.rxerr_phy++; |
8a63facc | 1463 | if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32) |
e0d687bd | 1464 | ah->stats.rxerr_phy_code[rs->rs_phyerr]++; |
b76ff0d2 MV |
1465 | |
1466 | /* | |
1467 | * Treat packets that underwent a CCK or OFDM reset as having a bad CRC. | |
1468 | * These restarts happen when the radio resynchronizes to a stronger frame | |
1469 | * while receiving a weaker frame. Here we receive the prefix of the weak | |
1470 | * frame. Since these are incomplete packets, mark their CRC as invalid. | |
1471 | */ | |
1472 | if (rs->rs_phyerr == AR5K_RX_PHY_ERROR_OFDM_RESTART || | |
1473 | rs->rs_phyerr == AR5K_RX_PHY_ERROR_CCK_RESTART) { | |
1474 | rs->rs_status |= AR5K_RXERR_CRC; | |
1475 | rs->rs_status &= ~AR5K_RXERR_PHY; | |
1476 | } else { | |
1477 | return false; | |
1478 | } | |
8a63facc BC |
1479 | } |
1480 | if (rs->rs_status & AR5K_RXERR_DECRYPT) { | |
1481 | /* | |
1482 | * Decrypt error. If the error occurred | |
1483 | * because there was no hardware key, then | |
1484 | * let the frame through so the upper layers | |
1485 | * can process it. This is necessary for 5210 | |
1486 | * parts which have no way to setup a ``clear'' | |
1487 | * key cache entry. | |
1488 | * | |
1489 | * XXX do key cache faulting | |
1490 | */ | |
e0d687bd | 1491 | ah->stats.rxerr_decrypt++; |
8a63facc BC |
1492 | if (rs->rs_keyix == AR5K_RXKEYIX_INVALID && |
1493 | !(rs->rs_status & AR5K_RXERR_CRC)) | |
1494 | return true; | |
1495 | } | |
1496 | if (rs->rs_status & AR5K_RXERR_MIC) { | |
e0d687bd | 1497 | ah->stats.rxerr_mic++; |
8a63facc | 1498 | return true; |
fa1c114f | 1499 | } |
fa1c114f | 1500 | |
41881354 MV |
1501 | /* |
1502 | * Reject any frames with non-crypto errors, and take into account the | |
1503 | * current FIF_* filters. | |
1504 | */ | |
1505 | filters = AR5K_RXERR_DECRYPT; | |
1506 | if (ah->fif_filter_flags & FIF_FCSFAIL) | |
1507 | filters |= AR5K_RXERR_CRC; | |
1508 | ||
1509 | if (rs->rs_status & ~filters) | |
8a63facc BC |
1510 | return false; |
1511 | } | |
fa1c114f | 1512 | |
8a63facc | 1513 | if (unlikely(rs->rs_more)) { |
e0d687bd | 1514 | ah->stats.rxerr_jumbo++; |
8a63facc BC |
1515 | return false; |
1516 | } | |
1517 | return true; | |
fa1c114f JS |
1518 | } |
1519 | ||
c266c71a | 1520 | static void |
e0d687bd | 1521 | ath5k_set_current_imask(struct ath5k_hw *ah) |
c266c71a | 1522 | { |
4fc5401c | 1523 | enum ath5k_int imask; |
c266c71a FF |
1524 | unsigned long flags; |
1525 | ||
ab5e290a SR |
1526 | if (test_bit(ATH_STAT_RESET, ah->status)) |
1527 | return; | |
1528 | ||
e0d687bd PR |
1529 | spin_lock_irqsave(&ah->irqlock, flags); |
1530 | imask = ah->imask; | |
1531 | if (ah->rx_pending) | |
c266c71a | 1532 | imask &= ~AR5K_INT_RX_ALL; |
e0d687bd | 1533 | if (ah->tx_pending) |
c266c71a | 1534 | imask &= ~AR5K_INT_TX_ALL; |
e0d687bd PR |
1535 | ath5k_hw_set_imr(ah, imask); |
1536 | spin_unlock_irqrestore(&ah->irqlock, flags); | |
c266c71a FF |
1537 | } |
1538 | ||
fa1c114f | 1539 | static void |
8a63facc | 1540 | ath5k_tasklet_rx(unsigned long data) |
fa1c114f | 1541 | { |
8a63facc BC |
1542 | struct ath5k_rx_status rs = {}; |
1543 | struct sk_buff *skb, *next_skb; | |
1544 | dma_addr_t next_skb_addr; | |
e0d687bd | 1545 | struct ath5k_hw *ah = (void *)data; |
dc1e001b | 1546 | struct ath_common *common = ath5k_hw_common(ah); |
8a63facc BC |
1547 | struct ath5k_buf *bf; |
1548 | struct ath5k_desc *ds; | |
1549 | int ret; | |
fa1c114f | 1550 | |
e0d687bd PR |
1551 | spin_lock(&ah->rxbuflock); |
1552 | if (list_empty(&ah->rxbuf)) { | |
1553 | ATH5K_WARN(ah, "empty rx buf pool\n"); | |
8a63facc BC |
1554 | goto unlock; |
1555 | } | |
1556 | do { | |
e0d687bd | 1557 | bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list); |
8a63facc BC |
1558 | BUG_ON(bf->skb == NULL); |
1559 | skb = bf->skb; | |
1560 | ds = bf->desc; | |
fa1c114f | 1561 | |
8a63facc | 1562 | /* bail if HW is still using self-linked descriptor */ |
e0d687bd | 1563 | if (ath5k_hw_get_rxdp(ah) == bf->daddr) |
8a63facc | 1564 | break; |
fa1c114f | 1565 | |
e0d687bd | 1566 | ret = ah->ah_proc_rx_desc(ah, ds, &rs); |
8a63facc BC |
1567 | if (unlikely(ret == -EINPROGRESS)) |
1568 | break; | |
1569 | else if (unlikely(ret)) { | |
e0d687bd PR |
1570 | ATH5K_ERR(ah, "error in processing rx descriptor\n"); |
1571 | ah->stats.rxerr_proc++; | |
8a63facc BC |
1572 | break; |
1573 | } | |
fa1c114f | 1574 | |
e0d687bd PR |
1575 | if (ath5k_receive_frame_ok(ah, &rs)) { |
1576 | next_skb = ath5k_rx_skb_alloc(ah, &next_skb_addr); | |
fa1c114f | 1577 | |
8a63facc BC |
1578 | /* |
1579 | * If we can't replace bf->skb with a new skb under | |
1580 | * memory pressure, just skip this packet | |
1581 | */ | |
1582 | if (!next_skb) | |
1583 | goto next; | |
036cd1ec | 1584 | |
e0d687bd | 1585 | dma_unmap_single(ah->dev, bf->skbaddr, |
8a63facc | 1586 | common->rx_bufsize, |
aeae4ac9 | 1587 | DMA_FROM_DEVICE); |
036cd1ec | 1588 | |
8a63facc | 1589 | skb_put(skb, rs.rs_datalen); |
6ba81c2c | 1590 | |
e0d687bd | 1591 | ath5k_receive_frame(ah, skb, &rs); |
6ba81c2c | 1592 | |
8a63facc BC |
1593 | bf->skb = next_skb; |
1594 | bf->skbaddr = next_skb_addr; | |
036cd1ec | 1595 | } |
8a63facc | 1596 | next: |
e0d687bd PR |
1597 | list_move_tail(&bf->list, &ah->rxbuf); |
1598 | } while (ath5k_rxbuf_setup(ah, bf) == 0); | |
8a63facc | 1599 | unlock: |
e0d687bd PR |
1600 | spin_unlock(&ah->rxbuflock); |
1601 | ah->rx_pending = false; | |
1602 | ath5k_set_current_imask(ah); | |
036cd1ec BR |
1603 | } |
1604 | ||
b4ea449d | 1605 | |
8a63facc BC |
1606 | /*************\ |
1607 | * TX Handling * | |
1608 | \*************/ | |
b4ea449d | 1609 | |
7bb45683 | 1610 | void |
cd2c5486 | 1611 | ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb, |
0967e01e | 1612 | struct ath5k_txq *txq, struct ieee80211_tx_control *control) |
8a63facc | 1613 | { |
e0d687bd | 1614 | struct ath5k_hw *ah = hw->priv; |
8a63facc BC |
1615 | struct ath5k_buf *bf; |
1616 | unsigned long flags; | |
1617 | int padsize; | |
b4ea449d | 1618 | |
e0d687bd | 1619 | trace_ath5k_tx(ah, skb, txq); |
b4ea449d | 1620 | |
8a63facc BC |
1621 | /* |
1622 | * The hardware expects the header padded to 4 byte boundaries. | |
1623 | * If this is not the case, we add the padding after the header. | |
1624 | */ | |
1625 | padsize = ath5k_add_padding(skb); | |
1626 | if (padsize < 0) { | |
e0d687bd | 1627 | ATH5K_ERR(ah, "tx hdrlen not %%4: not enough" |
8a63facc BC |
1628 | " headroom to pad"); |
1629 | goto drop_packet; | |
1630 | } | |
8127fbdc | 1631 | |
4e868796 FF |
1632 | if (txq->txq_len >= txq->txq_max && |
1633 | txq->qnum <= AR5K_TX_QUEUE_ID_DATA_MAX) | |
925e0b06 BR |
1634 | ieee80211_stop_queue(hw, txq->qnum); |
1635 | ||
e0d687bd PR |
1636 | spin_lock_irqsave(&ah->txbuflock, flags); |
1637 | if (list_empty(&ah->txbuf)) { | |
1638 | ATH5K_ERR(ah, "no further txbuf available, dropping packet\n"); | |
1639 | spin_unlock_irqrestore(&ah->txbuflock, flags); | |
651d9375 | 1640 | ieee80211_stop_queues(hw); |
8a63facc | 1641 | goto drop_packet; |
8127fbdc | 1642 | } |
e0d687bd | 1643 | bf = list_first_entry(&ah->txbuf, struct ath5k_buf, list); |
8a63facc | 1644 | list_del(&bf->list); |
e0d687bd PR |
1645 | ah->txbuf_len--; |
1646 | if (list_empty(&ah->txbuf)) | |
8a63facc | 1647 | ieee80211_stop_queues(hw); |
e0d687bd | 1648 | spin_unlock_irqrestore(&ah->txbuflock, flags); |
8a63facc BC |
1649 | |
1650 | bf->skb = skb; | |
1651 | ||
0967e01e | 1652 | if (ath5k_txbuf_setup(ah, bf, txq, padsize, control)) { |
8a63facc | 1653 | bf->skb = NULL; |
e0d687bd PR |
1654 | spin_lock_irqsave(&ah->txbuflock, flags); |
1655 | list_add_tail(&bf->list, &ah->txbuf); | |
1656 | ah->txbuf_len++; | |
1657 | spin_unlock_irqrestore(&ah->txbuflock, flags); | |
8a63facc | 1658 | goto drop_packet; |
8127fbdc | 1659 | } |
7bb45683 | 1660 | return; |
8127fbdc | 1661 | |
8a63facc | 1662 | drop_packet: |
596ab5ec | 1663 | ieee80211_free_txskb(hw, skb); |
8127fbdc BP |
1664 | } |
1665 | ||
1440401e | 1666 | static void |
e0d687bd | 1667 | ath5k_tx_frame_completed(struct ath5k_hw *ah, struct sk_buff *skb, |
0967e01e TH |
1668 | struct ath5k_txq *txq, struct ath5k_tx_status *ts, |
1669 | struct ath5k_buf *bf) | |
1440401e BR |
1670 | { |
1671 | struct ieee80211_tx_info *info; | |
ed895085 | 1672 | u8 tries[3]; |
1440401e | 1673 | int i; |
0967e01e | 1674 | int size = 0; |
1440401e | 1675 | |
e0d687bd PR |
1676 | ah->stats.tx_all_count++; |
1677 | ah->stats.tx_bytes_count += skb->len; | |
1440401e BR |
1678 | info = IEEE80211_SKB_CB(skb); |
1679 | ||
7ede612f FF |
1680 | size = min_t(int, sizeof(info->status.rates), sizeof(bf->rates)); |
1681 | memcpy(info->status.rates, bf->rates, size); | |
1682 | ||
ed895085 FF |
1683 | tries[0] = info->status.rates[0].count; |
1684 | tries[1] = info->status.rates[1].count; | |
1685 | tries[2] = info->status.rates[2].count; | |
1686 | ||
1440401e | 1687 | ieee80211_tx_info_clear_status(info); |
ed895085 FF |
1688 | |
1689 | for (i = 0; i < ts->ts_final_idx; i++) { | |
1440401e BR |
1690 | struct ieee80211_tx_rate *r = |
1691 | &info->status.rates[i]; | |
1692 | ||
ed895085 | 1693 | r->count = tries[i]; |
1440401e BR |
1694 | } |
1695 | ||
ed895085 | 1696 | info->status.rates[ts->ts_final_idx].count = ts->ts_final_retry; |
6d7b97b2 | 1697 | info->status.rates[ts->ts_final_idx + 1].idx = -1; |
1440401e BR |
1698 | |
1699 | if (unlikely(ts->ts_status)) { | |
e0d687bd | 1700 | ah->stats.ack_fail++; |
1440401e BR |
1701 | if (ts->ts_status & AR5K_TXERR_FILT) { |
1702 | info->flags |= IEEE80211_TX_STAT_TX_FILTERED; | |
e0d687bd | 1703 | ah->stats.txerr_filt++; |
1440401e BR |
1704 | } |
1705 | if (ts->ts_status & AR5K_TXERR_XRETRY) | |
e0d687bd | 1706 | ah->stats.txerr_retry++; |
1440401e | 1707 | if (ts->ts_status & AR5K_TXERR_FIFO) |
e0d687bd | 1708 | ah->stats.txerr_fifo++; |
1440401e BR |
1709 | } else { |
1710 | info->flags |= IEEE80211_TX_STAT_ACK; | |
1711 | info->status.ack_signal = ts->ts_rssi; | |
6d7b97b2 FF |
1712 | |
1713 | /* count the successful attempt as well */ | |
1714 | info->status.rates[ts->ts_final_idx].count++; | |
1440401e BR |
1715 | } |
1716 | ||
1717 | /* | |
1718 | * Remove MAC header padding before giving the frame | |
1719 | * back to mac80211. | |
1720 | */ | |
1721 | ath5k_remove_padding(skb); | |
1722 | ||
1723 | if (ts->ts_antenna > 0 && ts->ts_antenna < 5) | |
e0d687bd | 1724 | ah->stats.antenna_tx[ts->ts_antenna]++; |
1440401e | 1725 | else |
e0d687bd | 1726 | ah->stats.antenna_tx[0]++; /* invalid */ |
1440401e | 1727 | |
e0d687bd PR |
1728 | trace_ath5k_tx_complete(ah, skb, txq, ts); |
1729 | ieee80211_tx_status(ah->hw, skb); | |
1440401e | 1730 | } |
8a63facc BC |
1731 | |
1732 | static void | |
e0d687bd | 1733 | ath5k_tx_processq(struct ath5k_hw *ah, struct ath5k_txq *txq) |
8127fbdc | 1734 | { |
8a63facc BC |
1735 | struct ath5k_tx_status ts = {}; |
1736 | struct ath5k_buf *bf, *bf0; | |
1737 | struct ath5k_desc *ds; | |
1738 | struct sk_buff *skb; | |
1440401e | 1739 | int ret; |
8127fbdc | 1740 | |
8a63facc BC |
1741 | spin_lock(&txq->lock); |
1742 | list_for_each_entry_safe(bf, bf0, &txq->q, list) { | |
23413296 BR |
1743 | |
1744 | txq->txq_poll_mark = false; | |
1745 | ||
1746 | /* skb might already have been processed last time. */ | |
1747 | if (bf->skb != NULL) { | |
1748 | ds = bf->desc; | |
1749 | ||
e0d687bd | 1750 | ret = ah->ah_proc_tx_desc(ah, ds, &ts); |
23413296 BR |
1751 | if (unlikely(ret == -EINPROGRESS)) |
1752 | break; | |
1753 | else if (unlikely(ret)) { | |
e0d687bd | 1754 | ATH5K_ERR(ah, |
23413296 BR |
1755 | "error %d while processing " |
1756 | "queue %u\n", ret, txq->qnum); | |
1757 | break; | |
1758 | } | |
1759 | ||
1760 | skb = bf->skb; | |
1761 | bf->skb = NULL; | |
aeae4ac9 | 1762 | |
e0d687bd | 1763 | dma_unmap_single(ah->dev, bf->skbaddr, skb->len, |
aeae4ac9 | 1764 | DMA_TO_DEVICE); |
0967e01e | 1765 | ath5k_tx_frame_completed(ah, skb, txq, &ts, bf); |
23413296 | 1766 | } |
8127fbdc | 1767 | |
8a63facc BC |
1768 | /* |
1769 | * It's possible that the hardware can say the buffer is | |
1770 | * completed when it hasn't yet loaded the ds_link from | |
23413296 BR |
1771 | * host memory and moved on. |
1772 | * Always keep the last descriptor to avoid HW races... | |
8a63facc | 1773 | */ |
e0d687bd PR |
1774 | if (ath5k_hw_get_txdp(ah, txq->qnum) != bf->daddr) { |
1775 | spin_lock(&ah->txbuflock); | |
1776 | list_move_tail(&bf->list, &ah->txbuf); | |
1777 | ah->txbuf_len++; | |
23413296 | 1778 | txq->txq_len--; |
e0d687bd | 1779 | spin_unlock(&ah->txbuflock); |
8a63facc | 1780 | } |
fa1c114f | 1781 | } |
fa1c114f | 1782 | spin_unlock(&txq->lock); |
4198a8d0 | 1783 | if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4) |
e0d687bd | 1784 | ieee80211_wake_queue(ah->hw, txq->qnum); |
fa1c114f JS |
1785 | } |
1786 | ||
1787 | static void | |
1788 | ath5k_tasklet_tx(unsigned long data) | |
1789 | { | |
8784d2ee | 1790 | int i; |
e0d687bd | 1791 | struct ath5k_hw *ah = (void *)data; |
fa1c114f | 1792 | |
e4bbf2f5 | 1793 | for (i = 0; i < AR5K_NUM_TX_QUEUES; i++) |
7ff7c82e | 1794 | if (ah->txqs[i].setup && (ah->ah_txq_isr_txok_all & BIT(i))) |
e0d687bd | 1795 | ath5k_tx_processq(ah, &ah->txqs[i]); |
c266c71a | 1796 | |
e0d687bd PR |
1797 | ah->tx_pending = false; |
1798 | ath5k_set_current_imask(ah); | |
fa1c114f JS |
1799 | } |
1800 | ||
1801 | ||
fa1c114f JS |
1802 | /*****************\ |
1803 | * Beacon handling * | |
1804 | \*****************/ | |
1805 | ||
1806 | /* | |
1807 | * Setup the beacon frame for transmit. | |
1808 | */ | |
1809 | static int | |
e0d687bd | 1810 | ath5k_beacon_setup(struct ath5k_hw *ah, struct ath5k_buf *bf) |
fa1c114f JS |
1811 | { |
1812 | struct sk_buff *skb = bf->skb; | |
a888d52d | 1813 | struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); |
fa1c114f | 1814 | struct ath5k_desc *ds; |
2bed03eb NK |
1815 | int ret = 0; |
1816 | u8 antenna; | |
fa1c114f | 1817 | u32 flags; |
8127fbdc | 1818 | const int padsize = 0; |
fa1c114f | 1819 | |
e0d687bd | 1820 | bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len, |
aeae4ac9 | 1821 | DMA_TO_DEVICE); |
e0d687bd | 1822 | ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] " |
fa1c114f JS |
1823 | "skbaddr %llx\n", skb, skb->data, skb->len, |
1824 | (unsigned long long)bf->skbaddr); | |
aeae4ac9 | 1825 | |
e0d687bd PR |
1826 | if (dma_mapping_error(ah->dev, bf->skbaddr)) { |
1827 | ATH5K_ERR(ah, "beacon DMA mapping failed\n"); | |
bdc71bc5 BC |
1828 | dev_kfree_skb_any(skb); |
1829 | bf->skb = NULL; | |
fa1c114f JS |
1830 | return -EIO; |
1831 | } | |
1832 | ||
1833 | ds = bf->desc; | |
2bed03eb | 1834 | antenna = ah->ah_tx_ant; |
fa1c114f JS |
1835 | |
1836 | flags = AR5K_TXDESC_NOACK; | |
e0d687bd | 1837 | if (ah->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) { |
fa1c114f JS |
1838 | ds->ds_link = bf->daddr; /* self-linked */ |
1839 | flags |= AR5K_TXDESC_VEOL; | |
2bed03eb | 1840 | } else |
fa1c114f | 1841 | ds->ds_link = 0; |
2bed03eb NK |
1842 | |
1843 | /* | |
1844 | * If we use multiple antennas on AP and use | |
1845 | * the Sectored AP scenario, switch antenna every | |
1846 | * 4 beacons to make sure everybody hears our AP. | |
1847 | * When a client tries to associate, hw will keep | |
1848 | * track of the tx antenna to be used for this client | |
6a2a0e73 | 1849 | * automatically, based on ACKed packets. |
2bed03eb NK |
1850 | * |
1851 | * Note: AP still listens and transmits RTS on the | |
1852 | * default antenna which is supposed to be an omni. | |
1853 | * | |
1854 | * Note2: On sectored scenarios it's possible to have | |
a180a130 BC |
1855 | * multiple antennas (1 omni -- the default -- and 14 |
1856 | * sectors), so if we choose to actually support this | |
1857 | * mode, we need to allow the user to set how many antennas | |
1858 | * we have and tweak the code below to send beacons | |
1859 | * on all of them. | |
2bed03eb NK |
1860 | */ |
1861 | if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP) | |
e0d687bd | 1862 | antenna = ah->bsent & 4 ? 2 : 1; |
2bed03eb | 1863 | |
fa1c114f | 1864 | |
8f655dde NK |
1865 | /* FIXME: If we are in g mode and rate is a CCK rate |
1866 | * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta | |
1867 | * from tx power (value is in dB units already) */ | |
fa1c114f | 1868 | ds->ds_data = bf->skbaddr; |
281c56dd | 1869 | ret = ah->ah_setup_tx_desc(ah, ds, skb->len, |
8127fbdc | 1870 | ieee80211_get_hdrlen_from_skb(skb), padsize, |
987af54f NK |
1871 | AR5K_PKT_TYPE_BEACON, |
1872 | (ah->ah_txpower.txp_requested * 2), | |
e0d687bd | 1873 | ieee80211_get_tx_rate(ah->hw, info)->hw_value, |
2e92e6f2 | 1874 | 1, AR5K_TXKEYIX_INVALID, |
400ec45a | 1875 | antenna, flags, 0, 0); |
fa1c114f JS |
1876 | if (ret) |
1877 | goto err_unmap; | |
1878 | ||
1879 | return 0; | |
1880 | err_unmap: | |
e0d687bd | 1881 | dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE); |
fa1c114f JS |
1882 | return ret; |
1883 | } | |
1884 | ||
8a63facc BC |
1885 | /* |
1886 | * Updates the beacon that is sent by ath5k_beacon_send. For adhoc, | |
1887 | * this is called only once at config_bss time, for AP we do it every | |
1888 | * SWBA interrupt so that the TIM will reflect buffered frames. | |
1889 | * | |
1890 | * Called with the beacon lock. | |
1891 | */ | |
cd2c5486 | 1892 | int |
8a63facc BC |
1893 | ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif) |
1894 | { | |
1895 | int ret; | |
e0d687bd | 1896 | struct ath5k_hw *ah = hw->priv; |
9c371f99 | 1897 | struct ath5k_vif *avf; |
8a63facc BC |
1898 | struct sk_buff *skb; |
1899 | ||
1900 | if (WARN_ON(!vif)) { | |
1901 | ret = -EINVAL; | |
1902 | goto out; | |
1903 | } | |
1904 | ||
1905 | skb = ieee80211_beacon_get(hw, vif); | |
1906 | ||
1907 | if (!skb) { | |
1908 | ret = -ENOMEM; | |
1909 | goto out; | |
1910 | } | |
1911 | ||
9c371f99 | 1912 | avf = (void *)vif->drv_priv; |
e0d687bd | 1913 | ath5k_txbuf_free_skb(ah, avf->bbuf); |
b1ae1edf | 1914 | avf->bbuf->skb = skb; |
e0d687bd | 1915 | ret = ath5k_beacon_setup(ah, avf->bbuf); |
8a63facc BC |
1916 | out: |
1917 | return ret; | |
1918 | } | |
1919 | ||
fa1c114f JS |
1920 | /* |
1921 | * Transmit a beacon frame at SWBA. Dynamic updates to the | |
1922 | * frame contents are done as needed and the slot time is | |
1923 | * also adjusted based on current state. | |
1924 | * | |
5faaff74 BC |
1925 | * This is called from software irq context (beacontq tasklets) |
1926 | * or user context from ath5k_beacon_config. | |
fa1c114f JS |
1927 | */ |
1928 | static void | |
e0d687bd | 1929 | ath5k_beacon_send(struct ath5k_hw *ah) |
fa1c114f | 1930 | { |
b1ae1edf BG |
1931 | struct ieee80211_vif *vif; |
1932 | struct ath5k_vif *avf; | |
1933 | struct ath5k_buf *bf; | |
cec8db23 | 1934 | struct sk_buff *skb; |
bdc71bc5 | 1935 | int err; |
fa1c114f | 1936 | |
e0d687bd | 1937 | ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "in beacon_send\n"); |
fa1c114f | 1938 | |
fa1c114f JS |
1939 | /* |
1940 | * Check if the previous beacon has gone out. If | |
a180a130 | 1941 | * not, don't don't try to post another: skip this |
fa1c114f JS |
1942 | * period and wait for the next. Missed beacons |
1943 | * indicate a problem and should not occur. If we | |
1944 | * miss too many consecutive beacons reset the device. | |
1945 | */ | |
e0d687bd PR |
1946 | if (unlikely(ath5k_hw_num_tx_pending(ah, ah->bhalq) != 0)) { |
1947 | ah->bmisscount++; | |
1948 | ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, | |
1949 | "missed %u consecutive beacons\n", ah->bmisscount); | |
1950 | if (ah->bmisscount > 10) { /* NB: 10 is a guess */ | |
1951 | ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, | |
fa1c114f | 1952 | "stuck beacon time (%u missed)\n", |
e0d687bd PR |
1953 | ah->bmisscount); |
1954 | ATH5K_DBG(ah, ATH5K_DEBUG_RESET, | |
8d67a031 | 1955 | "stuck beacon, resetting\n"); |
e0d687bd | 1956 | ieee80211_queue_work(ah->hw, &ah->reset_work); |
fa1c114f JS |
1957 | } |
1958 | return; | |
1959 | } | |
e0d687bd PR |
1960 | if (unlikely(ah->bmisscount != 0)) { |
1961 | ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, | |
fa1c114f | 1962 | "resume beacon xmit after %u misses\n", |
e0d687bd PR |
1963 | ah->bmisscount); |
1964 | ah->bmisscount = 0; | |
fa1c114f JS |
1965 | } |
1966 | ||
da473b61 CYY |
1967 | if ((ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs + |
1968 | ah->num_mesh_vifs > 1) || | |
e0d687bd | 1969 | ah->opmode == NL80211_IFTYPE_MESH_POINT) { |
b1ae1edf BG |
1970 | u64 tsf = ath5k_hw_get_tsf64(ah); |
1971 | u32 tsftu = TSF_TO_TU(tsf); | |
e0d687bd PR |
1972 | int slot = ((tsftu % ah->bintval) * ATH_BCBUF) / ah->bintval; |
1973 | vif = ah->bslot[(slot + 1) % ATH_BCBUF]; | |
1974 | ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, | |
b1ae1edf | 1975 | "tsf %llx tsftu %x intval %u slot %u vif %p\n", |
e0d687bd | 1976 | (unsigned long long)tsf, tsftu, ah->bintval, slot, vif); |
b1ae1edf | 1977 | } else /* only one interface */ |
e0d687bd | 1978 | vif = ah->bslot[0]; |
b1ae1edf BG |
1979 | |
1980 | if (!vif) | |
1981 | return; | |
1982 | ||
1983 | avf = (void *)vif->drv_priv; | |
1984 | bf = avf->bbuf; | |
b1ae1edf | 1985 | |
fa1c114f JS |
1986 | /* |
1987 | * Stop any current dma and put the new frame on the queue. | |
1988 | * This should never fail since we check above that no frames | |
1989 | * are still pending on the queue. | |
1990 | */ | |
e0d687bd PR |
1991 | if (unlikely(ath5k_hw_stop_beacon_queue(ah, ah->bhalq))) { |
1992 | ATH5K_WARN(ah, "beacon queue %u didn't start/stop ?\n", ah->bhalq); | |
fa1c114f JS |
1993 | /* NB: hw still stops DMA, so proceed */ |
1994 | } | |
fa1c114f | 1995 | |
d82b577b | 1996 | /* refresh the beacon for AP or MESH mode */ |
e0d687bd | 1997 | if (ah->opmode == NL80211_IFTYPE_AP || |
bdc71bc5 BC |
1998 | ah->opmode == NL80211_IFTYPE_MESH_POINT) { |
1999 | err = ath5k_beacon_update(ah->hw, vif); | |
2000 | if (err) | |
2001 | return; | |
2002 | } | |
2003 | ||
2004 | if (unlikely(bf->skb == NULL || ah->opmode == NL80211_IFTYPE_STATION || | |
2005 | ah->opmode == NL80211_IFTYPE_MONITOR)) { | |
2006 | ATH5K_WARN(ah, "bf=%p bf_skb=%p\n", bf, bf->skb); | |
2007 | return; | |
2008 | } | |
1071db86 | 2009 | |
e0d687bd | 2010 | trace_ath5k_tx(ah, bf->skb, &ah->txqs[ah->bhalq]); |
0e472252 | 2011 | |
e0d687bd PR |
2012 | ath5k_hw_set_txdp(ah, ah->bhalq, bf->daddr); |
2013 | ath5k_hw_start_tx_dma(ah, ah->bhalq); | |
2014 | ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n", | |
2015 | ah->bhalq, (unsigned long long)bf->daddr, bf->desc); | |
fa1c114f | 2016 | |
e0d687bd | 2017 | skb = ieee80211_get_buffered_bc(ah->hw, vif); |
cec8db23 | 2018 | while (skb) { |
0967e01e | 2019 | ath5k_tx_queue(ah->hw, skb, ah->cabq, NULL); |
4e868796 | 2020 | |
e0d687bd | 2021 | if (ah->cabq->txq_len >= ah->cabq->txq_max) |
4e868796 FF |
2022 | break; |
2023 | ||
e0d687bd | 2024 | skb = ieee80211_get_buffered_bc(ah->hw, vif); |
cec8db23 BC |
2025 | } |
2026 | ||
e0d687bd | 2027 | ah->bsent++; |
fa1c114f JS |
2028 | } |
2029 | ||
9804b98d BR |
2030 | /** |
2031 | * ath5k_beacon_update_timers - update beacon timers | |
2032 | * | |
e0d687bd | 2033 | * @ah: struct ath5k_hw pointer we are operating on |
9804b98d BR |
2034 | * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a |
2035 | * beacon timer update based on the current HW TSF. | |
2036 | * | |
2037 | * Calculate the next target beacon transmit time (TBTT) based on the timestamp | |
2038 | * of a received beacon or the current local hardware TSF and write it to the | |
2039 | * beacon timer registers. | |
2040 | * | |
2041 | * This is called in a variety of situations, e.g. when a beacon is received, | |
6ba81c2c | 2042 | * when a TSF update has been detected, but also when an new IBSS is created or |
9804b98d BR |
2043 | * when we otherwise know we have to update the timers, but we keep it in this |
2044 | * function to have it all together in one place. | |
2045 | */ | |
cd2c5486 | 2046 | void |
e0d687bd | 2047 | ath5k_beacon_update_timers(struct ath5k_hw *ah, u64 bc_tsf) |
fa1c114f | 2048 | { |
9804b98d BR |
2049 | u32 nexttbtt, intval, hw_tu, bc_tu; |
2050 | u64 hw_tsf; | |
fa1c114f | 2051 | |
e0d687bd | 2052 | intval = ah->bintval & AR5K_BEACON_PERIOD; |
da473b61 CYY |
2053 | if (ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs |
2054 | + ah->num_mesh_vifs > 1) { | |
b1ae1edf BG |
2055 | intval /= ATH_BCBUF; /* staggered multi-bss beacons */ |
2056 | if (intval < 15) | |
e0d687bd | 2057 | ATH5K_WARN(ah, "intval %u is too low, min 15\n", |
b1ae1edf BG |
2058 | intval); |
2059 | } | |
fa1c114f JS |
2060 | if (WARN_ON(!intval)) |
2061 | return; | |
2062 | ||
9804b98d BR |
2063 | /* beacon TSF converted to TU */ |
2064 | bc_tu = TSF_TO_TU(bc_tsf); | |
fa1c114f | 2065 | |
9804b98d BR |
2066 | /* current TSF converted to TU */ |
2067 | hw_tsf = ath5k_hw_get_tsf64(ah); | |
2068 | hw_tu = TSF_TO_TU(hw_tsf); | |
fa1c114f | 2069 | |
633d006e | 2070 | #define FUDGE (AR5K_TUNE_SW_BEACON_RESP + 3) |
11f21df3 | 2071 | /* We use FUDGE to make sure the next TBTT is ahead of the current TU. |
25985edc | 2072 | * Since we later subtract AR5K_TUNE_SW_BEACON_RESP (10) in the timer |
11f21df3 BR |
2073 | * configuration we need to make sure it is bigger than that. */ |
2074 | ||
9804b98d BR |
2075 | if (bc_tsf == -1) { |
2076 | /* | |
2077 | * no beacons received, called internally. | |
2078 | * just need to refresh timers based on HW TSF. | |
2079 | */ | |
2080 | nexttbtt = roundup(hw_tu + FUDGE, intval); | |
2081 | } else if (bc_tsf == 0) { | |
2082 | /* | |
2083 | * no beacon received, probably called by ath5k_reset_tsf(). | |
2084 | * reset TSF to start with 0. | |
2085 | */ | |
2086 | nexttbtt = intval; | |
2087 | intval |= AR5K_BEACON_RESET_TSF; | |
2088 | } else if (bc_tsf > hw_tsf) { | |
2089 | /* | |
25985edc | 2090 | * beacon received, SW merge happened but HW TSF not yet updated. |
9804b98d BR |
2091 | * not possible to reconfigure timers yet, but next time we |
2092 | * receive a beacon with the same BSSID, the hardware will | |
2093 | * automatically update the TSF and then we need to reconfigure | |
2094 | * the timers. | |
2095 | */ | |
e0d687bd | 2096 | ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, |
9804b98d BR |
2097 | "need to wait for HW TSF sync\n"); |
2098 | return; | |
2099 | } else { | |
2100 | /* | |
2101 | * most important case for beacon synchronization between STA. | |
2102 | * | |
2103 | * beacon received and HW TSF has been already updated by HW. | |
2104 | * update next TBTT based on the TSF of the beacon, but make | |
2105 | * sure it is ahead of our local TSF timer. | |
2106 | */ | |
2107 | nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval); | |
2108 | } | |
2109 | #undef FUDGE | |
fa1c114f | 2110 | |
e0d687bd | 2111 | ah->nexttbtt = nexttbtt; |
036cd1ec | 2112 | |
fa1c114f | 2113 | intval |= AR5K_BEACON_ENA; |
c47faa36 | 2114 | ath5k_hw_init_beacon_timers(ah, nexttbtt, intval); |
9804b98d BR |
2115 | |
2116 | /* | |
2117 | * debugging output last in order to preserve the time critical aspect | |
2118 | * of this function | |
2119 | */ | |
2120 | if (bc_tsf == -1) | |
e0d687bd | 2121 | ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, |
9804b98d BR |
2122 | "reconfigured timers based on HW TSF\n"); |
2123 | else if (bc_tsf == 0) | |
e0d687bd | 2124 | ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, |
9804b98d BR |
2125 | "reset HW TSF and timers\n"); |
2126 | else | |
e0d687bd | 2127 | ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, |
9804b98d BR |
2128 | "updated timers based on beacon TSF\n"); |
2129 | ||
e0d687bd | 2130 | ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, |
04f93a87 DM |
2131 | "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n", |
2132 | (unsigned long long) bc_tsf, | |
2133 | (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt); | |
e0d687bd | 2134 | ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "intval %u %s %s\n", |
9804b98d BR |
2135 | intval & AR5K_BEACON_PERIOD, |
2136 | intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "", | |
2137 | intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : ""); | |
fa1c114f JS |
2138 | } |
2139 | ||
036cd1ec BR |
2140 | /** |
2141 | * ath5k_beacon_config - Configure the beacon queues and interrupts | |
2142 | * | |
e0d687bd | 2143 | * @ah: struct ath5k_hw pointer we are operating on |
fa1c114f | 2144 | * |
036cd1ec | 2145 | * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA |
6ba81c2c | 2146 | * interrupts to detect TSF updates only. |
fa1c114f | 2147 | */ |
cd2c5486 | 2148 | void |
e0d687bd | 2149 | ath5k_beacon_config(struct ath5k_hw *ah) |
fa1c114f | 2150 | { |
7dd6753f | 2151 | spin_lock_bh(&ah->block); |
e0d687bd PR |
2152 | ah->bmisscount = 0; |
2153 | ah->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA); | |
fa1c114f | 2154 | |
e0d687bd | 2155 | if (ah->enable_beacon) { |
fa1c114f | 2156 | /* |
036cd1ec BR |
2157 | * In IBSS mode we use a self-linked tx descriptor and let the |
2158 | * hardware send the beacons automatically. We have to load it | |
fa1c114f | 2159 | * only once here. |
036cd1ec | 2160 | * We use the SWBA interrupt only to keep track of the beacon |
6ba81c2c | 2161 | * timers in order to detect automatic TSF updates. |
fa1c114f | 2162 | */ |
e0d687bd | 2163 | ath5k_beaconq_config(ah); |
fa1c114f | 2164 | |
e0d687bd | 2165 | ah->imask |= AR5K_INT_SWBA; |
036cd1ec | 2166 | |
e0d687bd | 2167 | if (ah->opmode == NL80211_IFTYPE_ADHOC) { |
21800491 | 2168 | if (ath5k_hw_hasveol(ah)) |
e0d687bd | 2169 | ath5k_beacon_send(ah); |
da966bca | 2170 | } else |
e0d687bd | 2171 | ath5k_beacon_update_timers(ah, -1); |
21800491 | 2172 | } else { |
e0d687bd | 2173 | ath5k_hw_stop_beacon_queue(ah, ah->bhalq); |
fa1c114f | 2174 | } |
fa1c114f | 2175 | |
e0d687bd | 2176 | ath5k_hw_set_imr(ah, ah->imask); |
21800491 | 2177 | mmiowb(); |
7dd6753f | 2178 | spin_unlock_bh(&ah->block); |
fa1c114f JS |
2179 | } |
2180 | ||
428cbd4f NK |
2181 | static void ath5k_tasklet_beacon(unsigned long data) |
2182 | { | |
e0d687bd | 2183 | struct ath5k_hw *ah = (struct ath5k_hw *) data; |
428cbd4f NK |
2184 | |
2185 | /* | |
2186 | * Software beacon alert--time to send a beacon. | |
2187 | * | |
2188 | * In IBSS mode we use this interrupt just to | |
2189 | * keep track of the next TBTT (target beacon | |
6a2a0e73 | 2190 | * transmission time) in order to detect whether |
428cbd4f NK |
2191 | * automatic TSF updates happened. |
2192 | */ | |
e0d687bd | 2193 | if (ah->opmode == NL80211_IFTYPE_ADHOC) { |
6a2a0e73 | 2194 | /* XXX: only if VEOL supported */ |
e0d687bd PR |
2195 | u64 tsf = ath5k_hw_get_tsf64(ah); |
2196 | ah->nexttbtt += ah->bintval; | |
2197 | ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, | |
428cbd4f NK |
2198 | "SWBA nexttbtt: %x hw_tu: %x " |
2199 | "TSF: %llx\n", | |
e0d687bd | 2200 | ah->nexttbtt, |
428cbd4f NK |
2201 | TSF_TO_TU(tsf), |
2202 | (unsigned long long) tsf); | |
2203 | } else { | |
e0d687bd PR |
2204 | spin_lock(&ah->block); |
2205 | ath5k_beacon_send(ah); | |
2206 | spin_unlock(&ah->block); | |
428cbd4f NK |
2207 | } |
2208 | } | |
2209 | ||
fa1c114f JS |
2210 | |
2211 | /********************\ | |
2212 | * Interrupt handling * | |
2213 | \********************/ | |
2214 | ||
6a8a3f6b BR |
2215 | static void |
2216 | ath5k_intr_calibration_poll(struct ath5k_hw *ah) | |
2217 | { | |
2111ac0d | 2218 | if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) && |
ce169aca NK |
2219 | !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL) && |
2220 | !(ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)) { | |
2221 | ||
2222 | /* Run ANI only when calibration is not active */ | |
2223 | ||
2111ac0d BR |
2224 | ah->ah_cal_next_ani = jiffies + |
2225 | msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI); | |
e0d687bd | 2226 | tasklet_schedule(&ah->ani_tasklet); |
2111ac0d | 2227 | |
ce169aca NK |
2228 | } else if (time_is_before_eq_jiffies(ah->ah_cal_next_short) && |
2229 | !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL) && | |
2230 | !(ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)) { | |
2231 | ||
2232 | /* Run calibration only when another calibration | |
2233 | * is not running. | |
2234 | * | |
2235 | * Note: This is for both full/short calibration, | |
2236 | * if it's time for a full one, ath5k_calibrate_work will deal | |
2237 | * with it. */ | |
2238 | ||
2239 | ah->ah_cal_next_short = jiffies + | |
2240 | msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT); | |
2241 | ieee80211_queue_work(ah->hw, &ah->calib_work); | |
6a8a3f6b BR |
2242 | } |
2243 | /* we could use SWI to generate enough interrupts to meet our | |
2244 | * calibration interval requirements, if necessary: | |
2245 | * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */ | |
2246 | } | |
2247 | ||
c266c71a | 2248 | static void |
e0d687bd | 2249 | ath5k_schedule_rx(struct ath5k_hw *ah) |
c266c71a | 2250 | { |
e0d687bd PR |
2251 | ah->rx_pending = true; |
2252 | tasklet_schedule(&ah->rxtq); | |
c266c71a FF |
2253 | } |
2254 | ||
2255 | static void | |
e0d687bd | 2256 | ath5k_schedule_tx(struct ath5k_hw *ah) |
c266c71a | 2257 | { |
e0d687bd PR |
2258 | ah->tx_pending = true; |
2259 | tasklet_schedule(&ah->txtq); | |
c266c71a FF |
2260 | } |
2261 | ||
f5cbc8ba | 2262 | static irqreturn_t |
fa1c114f JS |
2263 | ath5k_intr(int irq, void *dev_id) |
2264 | { | |
e0d687bd | 2265 | struct ath5k_hw *ah = dev_id; |
fa1c114f JS |
2266 | enum ath5k_int status; |
2267 | unsigned int counter = 1000; | |
2268 | ||
34ce644a NK |
2269 | |
2270 | /* | |
2271 | * If hw is not ready (or detached) and we get an | |
2272 | * interrupt, or if we have no interrupts pending | |
2273 | * (that means it's not for us) skip it. | |
2274 | * | |
2275 | * NOTE: Group 0/1 PCI interface registers are not | |
2276 | * supported on WiSOCs, so we can't check for pending | |
2277 | * interrupts (ISR belongs to another register group | |
2278 | * so we are ok). | |
2279 | */ | |
e0d687bd | 2280 | if (unlikely(test_bit(ATH_STAT_INVALID, ah->status) || |
34ce644a NK |
2281 | ((ath5k_get_bus_type(ah) != ATH_AHB) && |
2282 | !ath5k_hw_is_intr_pending(ah)))) | |
fa1c114f JS |
2283 | return IRQ_NONE; |
2284 | ||
34ce644a | 2285 | /** Main loop **/ |
fa1c114f | 2286 | do { |
34ce644a NK |
2287 | ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */ |
2288 | ||
e0d687bd PR |
2289 | ATH5K_DBG(ah, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n", |
2290 | status, ah->imask); | |
34ce644a NK |
2291 | |
2292 | /* | |
2293 | * Fatal hw error -> Log and reset | |
2294 | * | |
2295 | * Fatal errors are unrecoverable so we have to | |
2296 | * reset the card. These errors include bus and | |
2297 | * dma errors. | |
2298 | */ | |
fa1c114f | 2299 | if (unlikely(status & AR5K_INT_FATAL)) { |
34ce644a | 2300 | |
e0d687bd | 2301 | ATH5K_DBG(ah, ATH5K_DEBUG_RESET, |
8d67a031 | 2302 | "fatal int, resetting\n"); |
e0d687bd | 2303 | ieee80211_queue_work(ah->hw, &ah->reset_work); |
34ce644a NK |
2304 | |
2305 | /* | |
2306 | * RX Overrun -> Count and reset if needed | |
2307 | * | |
2308 | * Receive buffers are full. Either the bus is busy or | |
2309 | * the CPU is not fast enough to process all received | |
2310 | * frames. | |
2311 | */ | |
fa1c114f | 2312 | } else if (unlikely(status & AR5K_INT_RXORN)) { |
34ce644a | 2313 | |
87d77c4e | 2314 | /* |
87d77c4e BR |
2315 | * Older chipsets need a reset to come out of this |
2316 | * condition, but we treat it as RX for newer chips. | |
34ce644a | 2317 | * We don't know exactly which versions need a reset |
87d77c4e BR |
2318 | * this guess is copied from the HAL. |
2319 | */ | |
e0d687bd | 2320 | ah->stats.rxorn_intr++; |
34ce644a | 2321 | |
8d67a031 | 2322 | if (ah->ah_mac_srev < AR5K_SREV_AR5212) { |
e0d687bd | 2323 | ATH5K_DBG(ah, ATH5K_DEBUG_RESET, |
8d67a031 | 2324 | "rx overrun, resetting\n"); |
e0d687bd | 2325 | ieee80211_queue_work(ah->hw, &ah->reset_work); |
d2c7f773 | 2326 | } else |
e0d687bd | 2327 | ath5k_schedule_rx(ah); |
34ce644a | 2328 | |
fa1c114f | 2329 | } else { |
34ce644a NK |
2330 | |
2331 | /* Software Beacon Alert -> Schedule beacon tasklet */ | |
d2c7f773 | 2332 | if (status & AR5K_INT_SWBA) |
e0d687bd | 2333 | tasklet_hi_schedule(&ah->beacontq); |
d2c7f773 | 2334 | |
34ce644a NK |
2335 | /* |
2336 | * No more RX descriptors -> Just count | |
2337 | * | |
2338 | * NB: the hardware should re-read the link when | |
2339 | * RXE bit is written, but it doesn't work at | |
2340 | * least on older hardware revs. | |
2341 | */ | |
2342 | if (status & AR5K_INT_RXEOL) | |
e0d687bd | 2343 | ah->stats.rxeol_intr++; |
34ce644a NK |
2344 | |
2345 | ||
2346 | /* TX Underrun -> Bump tx trigger level */ | |
2347 | if (status & AR5K_INT_TXURN) | |
fa1c114f | 2348 | ath5k_hw_update_tx_triglevel(ah, true); |
34ce644a NK |
2349 | |
2350 | /* RX -> Schedule rx tasklet */ | |
4c674c60 | 2351 | if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR)) |
e0d687bd | 2352 | ath5k_schedule_rx(ah); |
34ce644a NK |
2353 | |
2354 | /* TX -> Schedule tx tasklet */ | |
2355 | if (status & (AR5K_INT_TXOK | |
2356 | | AR5K_INT_TXDESC | |
2357 | | AR5K_INT_TXERR | |
2358 | | AR5K_INT_TXEOL)) | |
e0d687bd | 2359 | ath5k_schedule_tx(ah); |
34ce644a NK |
2360 | |
2361 | /* Missed beacon -> TODO | |
2362 | if (status & AR5K_INT_BMISS) | |
2363 | */ | |
2364 | ||
2365 | /* MIB event -> Update counters and notify ANI */ | |
fa1c114f | 2366 | if (status & AR5K_INT_MIB) { |
e0d687bd | 2367 | ah->stats.mib_intr++; |
495391d7 | 2368 | ath5k_hw_update_mib_counters(ah); |
2111ac0d | 2369 | ath5k_ani_mib_intr(ah); |
fa1c114f | 2370 | } |
34ce644a NK |
2371 | |
2372 | /* GPIO -> Notify RFKill layer */ | |
e6a3b616 | 2373 | if (status & AR5K_INT_GPIO) |
e0d687bd | 2374 | tasklet_schedule(&ah->rf_kill.toggleq); |
a6ae0716 | 2375 | |
fa1c114f | 2376 | } |
4cebb34c FF |
2377 | |
2378 | if (ath5k_get_bus_type(ah) == ATH_AHB) | |
2379 | break; | |
2380 | ||
2516baa6 | 2381 | } while (ath5k_hw_is_intr_pending(ah) && --counter > 0); |
fa1c114f | 2382 | |
34ce644a NK |
2383 | /* |
2384 | * Until we handle rx/tx interrupts mask them on IMR | |
2385 | * | |
2386 | * NOTE: ah->(rx/tx)_pending are set when scheduling the tasklets | |
2387 | * and unset after we 've handled the interrupts. | |
2388 | */ | |
e0d687bd PR |
2389 | if (ah->rx_pending || ah->tx_pending) |
2390 | ath5k_set_current_imask(ah); | |
c266c71a | 2391 | |
fa1c114f | 2392 | if (unlikely(!counter)) |
e0d687bd | 2393 | ATH5K_WARN(ah, "too many interrupts, giving up for now\n"); |
fa1c114f | 2394 | |
34ce644a | 2395 | /* Fire up calibration poll */ |
6a8a3f6b | 2396 | ath5k_intr_calibration_poll(ah); |
6e220662 | 2397 | |
fa1c114f JS |
2398 | return IRQ_HANDLED; |
2399 | } | |
2400 | ||
fa1c114f JS |
2401 | /* |
2402 | * Periodically recalibrate the PHY to account | |
2403 | * for temperature/environment changes. | |
2404 | */ | |
2405 | static void | |
ce169aca | 2406 | ath5k_calibrate_work(struct work_struct *work) |
fa1c114f | 2407 | { |
ce169aca NK |
2408 | struct ath5k_hw *ah = container_of(work, struct ath5k_hw, |
2409 | calib_work); | |
2410 | ||
2411 | /* Should we run a full calibration ? */ | |
2412 | if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) { | |
2413 | ||
2414 | ah->ah_cal_next_full = jiffies + | |
2415 | msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL); | |
2416 | ah->ah_cal_mask |= AR5K_CALIBRATION_FULL; | |
2417 | ||
2418 | ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, | |
2419 | "running full calibration\n"); | |
2420 | ||
2421 | if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) { | |
2422 | /* | |
2423 | * Rfgain is out of bounds, reset the chip | |
2424 | * to load new gain values. | |
2425 | */ | |
2426 | ATH5K_DBG(ah, ATH5K_DEBUG_RESET, | |
2427 | "got new rfgain, resetting\n"); | |
2428 | ieee80211_queue_work(ah->hw, &ah->reset_work); | |
2429 | } | |
ce169aca NK |
2430 | } else |
2431 | ah->ah_cal_mask |= AR5K_CALIBRATION_SHORT; | |
fa1c114f | 2432 | |
6e220662 | 2433 | |
e0d687bd PR |
2434 | ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n", |
2435 | ieee80211_frequency_to_channel(ah->curchan->center_freq), | |
2436 | ah->curchan->hw_value); | |
fa1c114f | 2437 | |
e0d687bd PR |
2438 | if (ath5k_hw_phy_calibrate(ah, ah->curchan)) |
2439 | ATH5K_ERR(ah, "calibration of channel %u failed\n", | |
400ec45a | 2440 | ieee80211_frequency_to_channel( |
e0d687bd | 2441 | ah->curchan->center_freq)); |
fa1c114f | 2442 | |
ce169aca | 2443 | /* Clear calibration flags */ |
62e2c102 | 2444 | if (ah->ah_cal_mask & AR5K_CALIBRATION_FULL) |
ce169aca | 2445 | ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL; |
62e2c102 | 2446 | else if (ah->ah_cal_mask & AR5K_CALIBRATION_SHORT) |
ce169aca | 2447 | ah->ah_cal_mask &= ~AR5K_CALIBRATION_SHORT; |
fa1c114f JS |
2448 | } |
2449 | ||
2450 | ||
2111ac0d BR |
2451 | static void |
2452 | ath5k_tasklet_ani(unsigned long data) | |
2453 | { | |
e0d687bd | 2454 | struct ath5k_hw *ah = (void *)data; |
2111ac0d BR |
2455 | |
2456 | ah->ah_cal_mask |= AR5K_CALIBRATION_ANI; | |
2457 | ath5k_ani_calibration(ah); | |
2458 | ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI; | |
fa1c114f JS |
2459 | } |
2460 | ||
2461 | ||
4edd761f BR |
2462 | static void |
2463 | ath5k_tx_complete_poll_work(struct work_struct *work) | |
2464 | { | |
e0d687bd | 2465 | struct ath5k_hw *ah = container_of(work, struct ath5k_hw, |
4edd761f BR |
2466 | tx_complete_work.work); |
2467 | struct ath5k_txq *txq; | |
2468 | int i; | |
2469 | bool needreset = false; | |
2470 | ||
db178340 SG |
2471 | if (!test_bit(ATH_STAT_STARTED, ah->status)) |
2472 | return; | |
2473 | ||
e0d687bd | 2474 | mutex_lock(&ah->lock); |
599b13ad | 2475 | |
e0d687bd PR |
2476 | for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) { |
2477 | if (ah->txqs[i].setup) { | |
2478 | txq = &ah->txqs[i]; | |
4edd761f | 2479 | spin_lock_bh(&txq->lock); |
23413296 | 2480 | if (txq->txq_len > 1) { |
4edd761f | 2481 | if (txq->txq_poll_mark) { |
e0d687bd | 2482 | ATH5K_DBG(ah, ATH5K_DEBUG_XMIT, |
4edd761f BR |
2483 | "TX queue stuck %d\n", |
2484 | txq->qnum); | |
2485 | needreset = true; | |
923e5b3d | 2486 | txq->txq_stuck++; |
4edd761f BR |
2487 | spin_unlock_bh(&txq->lock); |
2488 | break; | |
2489 | } else { | |
2490 | txq->txq_poll_mark = true; | |
2491 | } | |
2492 | } | |
2493 | spin_unlock_bh(&txq->lock); | |
2494 | } | |
2495 | } | |
2496 | ||
2497 | if (needreset) { | |
e0d687bd | 2498 | ATH5K_DBG(ah, ATH5K_DEBUG_RESET, |
4edd761f | 2499 | "TX queues stuck, resetting\n"); |
e0d687bd | 2500 | ath5k_reset(ah, NULL, true); |
4edd761f BR |
2501 | } |
2502 | ||
e0d687bd | 2503 | mutex_unlock(&ah->lock); |
599b13ad | 2504 | |
e0d687bd | 2505 | ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work, |
4edd761f BR |
2506 | msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT)); |
2507 | } | |
2508 | ||
2509 | ||
8a63facc BC |
2510 | /*************************\ |
2511 | * Initialization routines * | |
2512 | \*************************/ | |
fa1c114f | 2513 | |
9b4760e3 FF |
2514 | static const struct ieee80211_iface_limit if_limits[] = { |
2515 | { .max = 2048, .types = BIT(NL80211_IFTYPE_STATION) }, | |
2516 | { .max = 4, .types = | |
2517 | #ifdef CONFIG_MAC80211_MESH | |
2518 | BIT(NL80211_IFTYPE_MESH_POINT) | | |
2519 | #endif | |
2520 | BIT(NL80211_IFTYPE_AP) }, | |
2521 | }; | |
2522 | ||
2523 | static const struct ieee80211_iface_combination if_comb = { | |
2524 | .limits = if_limits, | |
2525 | .n_limits = ARRAY_SIZE(if_limits), | |
2526 | .max_interfaces = 2048, | |
2527 | .num_different_channels = 1, | |
2528 | }; | |
2529 | ||
e829cf96 | 2530 | int |
bb1f3ad9 | 2531 | ath5k_init_ah(struct ath5k_hw *ah, const struct ath_bus_ops *bus_ops) |
132b1c3e | 2532 | { |
e0d687bd | 2533 | struct ieee80211_hw *hw = ah->hw; |
132b1c3e FF |
2534 | struct ath_common *common; |
2535 | int ret; | |
2536 | int csz; | |
2537 | ||
2538 | /* Initialize driver private data */ | |
e0d687bd | 2539 | SET_IEEE80211_DEV(hw, ah->dev); |
30686bf7 JB |
2540 | ieee80211_hw_set(hw, SUPPORTS_RC_TABLE); |
2541 | ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS); | |
2542 | ieee80211_hw_set(hw, MFP_CAPABLE); | |
2543 | ieee80211_hw_set(hw, SIGNAL_DBM); | |
2544 | ieee80211_hw_set(hw, RX_INCLUDES_FCS); | |
2545 | ieee80211_hw_set(hw, HOST_BROADCAST_PS_BUFFERING); | |
132b1c3e FF |
2546 | |
2547 | hw->wiphy->interface_modes = | |
2548 | BIT(NL80211_IFTYPE_AP) | | |
2549 | BIT(NL80211_IFTYPE_STATION) | | |
2550 | BIT(NL80211_IFTYPE_ADHOC) | | |
2551 | BIT(NL80211_IFTYPE_MESH_POINT); | |
2552 | ||
9b4760e3 FF |
2553 | hw->wiphy->iface_combinations = &if_comb; |
2554 | hw->wiphy->n_iface_combinations = 1; | |
2555 | ||
f9972577 AQ |
2556 | /* SW support for IBSS_RSN is provided by mac80211 */ |
2557 | hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN; | |
2558 | ||
4d70f2fb SW |
2559 | hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_5_10_MHZ; |
2560 | ||
3de135db BR |
2561 | /* both antennas can be configured as RX or TX */ |
2562 | hw->wiphy->available_antennas_tx = 0x3; | |
2563 | hw->wiphy->available_antennas_rx = 0x3; | |
2564 | ||
132b1c3e | 2565 | hw->extra_tx_headroom = 2; |
132b1c3e FF |
2566 | |
2567 | /* | |
2568 | * Mark the device as detached to avoid processing | |
2569 | * interrupts until setup is complete. | |
2570 | */ | |
e0d687bd | 2571 | __set_bit(ATH_STAT_INVALID, ah->status); |
132b1c3e | 2572 | |
e0d687bd PR |
2573 | ah->opmode = NL80211_IFTYPE_STATION; |
2574 | ah->bintval = 1000; | |
2575 | mutex_init(&ah->lock); | |
2576 | spin_lock_init(&ah->rxbuflock); | |
2577 | spin_lock_init(&ah->txbuflock); | |
2578 | spin_lock_init(&ah->block); | |
2579 | spin_lock_init(&ah->irqlock); | |
132b1c3e FF |
2580 | |
2581 | /* Setup interrupt handler */ | |
e0d687bd | 2582 | ret = request_irq(ah->irq, ath5k_intr, IRQF_SHARED, "ath", ah); |
132b1c3e | 2583 | if (ret) { |
e0d687bd | 2584 | ATH5K_ERR(ah, "request_irq failed\n"); |
132b1c3e FF |
2585 | goto err; |
2586 | } | |
2587 | ||
e0d687bd | 2588 | common = ath5k_hw_common(ah); |
132b1c3e FF |
2589 | common->ops = &ath5k_common_ops; |
2590 | common->bus_ops = bus_ops; | |
e0d687bd | 2591 | common->ah = ah; |
132b1c3e | 2592 | common->hw = hw; |
e0d687bd | 2593 | common->priv = ah; |
26d16d23 | 2594 | common->clockrate = 40; |
132b1c3e FF |
2595 | |
2596 | /* | |
2597 | * Cache line size is used to size and align various | |
2598 | * structures used to communicate with the hardware. | |
2599 | */ | |
2600 | ath5k_read_cachesize(common, &csz); | |
2601 | common->cachelsz = csz << 2; /* convert to bytes */ | |
2602 | ||
2603 | spin_lock_init(&common->cc_lock); | |
2604 | ||
2605 | /* Initialize device */ | |
e0d687bd | 2606 | ret = ath5k_hw_init(ah); |
132b1c3e | 2607 | if (ret) |
e0d687bd | 2608 | goto err_irq; |
132b1c3e | 2609 | |
86f62d9b NK |
2610 | /* Set up multi-rate retry capabilities */ |
2611 | if (ah->ah_capabilities.cap_has_mrr_support) { | |
132b1c3e | 2612 | hw->max_rates = 4; |
76a9f6fd BR |
2613 | hw->max_rate_tries = max(AR5K_INIT_RETRY_SHORT, |
2614 | AR5K_INIT_RETRY_LONG); | |
132b1c3e FF |
2615 | } |
2616 | ||
2617 | hw->vif_data_size = sizeof(struct ath5k_vif); | |
2618 | ||
2619 | /* Finish private driver data initialization */ | |
2620 | ret = ath5k_init(hw); | |
2621 | if (ret) | |
2622 | goto err_ah; | |
2623 | ||
e0d687bd PR |
2624 | ATH5K_INFO(ah, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n", |
2625 | ath5k_chip_name(AR5K_VERSION_MAC, ah->ah_mac_srev), | |
2626 | ah->ah_mac_srev, | |
2627 | ah->ah_phy_revision); | |
132b1c3e | 2628 | |
e0d687bd | 2629 | if (!ah->ah_single_chip) { |
132b1c3e | 2630 | /* Single chip radio (!RF5111) */ |
e0d687bd PR |
2631 | if (ah->ah_radio_5ghz_revision && |
2632 | !ah->ah_radio_2ghz_revision) { | |
132b1c3e FF |
2633 | /* No 5GHz support -> report 2GHz radio */ |
2634 | if (!test_bit(AR5K_MODE_11A, | |
e0d687bd PR |
2635 | ah->ah_capabilities.cap_mode)) { |
2636 | ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n", | |
132b1c3e | 2637 | ath5k_chip_name(AR5K_VERSION_RAD, |
e0d687bd PR |
2638 | ah->ah_radio_5ghz_revision), |
2639 | ah->ah_radio_5ghz_revision); | |
132b1c3e | 2640 | /* No 2GHz support (5110 and some |
6a2a0e73 | 2641 | * 5GHz only cards) -> report 5GHz radio */ |
132b1c3e | 2642 | } else if (!test_bit(AR5K_MODE_11B, |
e0d687bd PR |
2643 | ah->ah_capabilities.cap_mode)) { |
2644 | ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n", | |
132b1c3e | 2645 | ath5k_chip_name(AR5K_VERSION_RAD, |
e0d687bd PR |
2646 | ah->ah_radio_5ghz_revision), |
2647 | ah->ah_radio_5ghz_revision); | |
132b1c3e FF |
2648 | /* Multiband radio */ |
2649 | } else { | |
e0d687bd | 2650 | ATH5K_INFO(ah, "RF%s multiband radio found" |
132b1c3e FF |
2651 | " (0x%x)\n", |
2652 | ath5k_chip_name(AR5K_VERSION_RAD, | |
e0d687bd PR |
2653 | ah->ah_radio_5ghz_revision), |
2654 | ah->ah_radio_5ghz_revision); | |
132b1c3e FF |
2655 | } |
2656 | } | |
2657 | /* Multi chip radio (RF5111 - RF2111) -> | |
2658 | * report both 2GHz/5GHz radios */ | |
e0d687bd PR |
2659 | else if (ah->ah_radio_5ghz_revision && |
2660 | ah->ah_radio_2ghz_revision) { | |
2661 | ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n", | |
132b1c3e | 2662 | ath5k_chip_name(AR5K_VERSION_RAD, |
e0d687bd PR |
2663 | ah->ah_radio_5ghz_revision), |
2664 | ah->ah_radio_5ghz_revision); | |
2665 | ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n", | |
132b1c3e | 2666 | ath5k_chip_name(AR5K_VERSION_RAD, |
e0d687bd PR |
2667 | ah->ah_radio_2ghz_revision), |
2668 | ah->ah_radio_2ghz_revision); | |
132b1c3e FF |
2669 | } |
2670 | } | |
2671 | ||
e0d687bd | 2672 | ath5k_debug_init_device(ah); |
132b1c3e FF |
2673 | |
2674 | /* ready to process interrupts */ | |
e0d687bd | 2675 | __clear_bit(ATH_STAT_INVALID, ah->status); |
132b1c3e FF |
2676 | |
2677 | return 0; | |
2678 | err_ah: | |
e0d687bd | 2679 | ath5k_hw_deinit(ah); |
132b1c3e | 2680 | err_irq: |
e0d687bd | 2681 | free_irq(ah->irq, ah); |
132b1c3e FF |
2682 | err: |
2683 | return ret; | |
2684 | } | |
2685 | ||
fa1c114f | 2686 | static int |
e0d687bd | 2687 | ath5k_stop_locked(struct ath5k_hw *ah) |
cec8db23 | 2688 | { |
cec8db23 | 2689 | |
e0d687bd PR |
2690 | ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "invalid %u\n", |
2691 | test_bit(ATH_STAT_INVALID, ah->status)); | |
8a63facc BC |
2692 | |
2693 | /* | |
2694 | * Shutdown the hardware and driver: | |
2695 | * stop output from above | |
2696 | * disable interrupts | |
2697 | * turn off timers | |
2698 | * turn off the radio | |
2699 | * clear transmit machinery | |
2700 | * clear receive machinery | |
2701 | * drain and release tx queues | |
2702 | * reclaim beacon resources | |
2703 | * power down hardware | |
2704 | * | |
2705 | * Note that some of this work is not possible if the | |
2706 | * hardware is gone (invalid). | |
2707 | */ | |
e0d687bd | 2708 | ieee80211_stop_queues(ah->hw); |
8a63facc | 2709 | |
e0d687bd PR |
2710 | if (!test_bit(ATH_STAT_INVALID, ah->status)) { |
2711 | ath5k_led_off(ah); | |
8a63facc | 2712 | ath5k_hw_set_imr(ah, 0); |
e0d687bd PR |
2713 | synchronize_irq(ah->irq); |
2714 | ath5k_rx_stop(ah); | |
80dac9ee | 2715 | ath5k_hw_dma_stop(ah); |
e0d687bd | 2716 | ath5k_drain_tx_buffs(ah); |
8a63facc BC |
2717 | ath5k_hw_phy_disable(ah); |
2718 | } | |
2719 | ||
2720 | return 0; | |
cec8db23 BC |
2721 | } |
2722 | ||
fabba048 | 2723 | int ath5k_start(struct ieee80211_hw *hw) |
fa1c114f | 2724 | { |
fabba048 | 2725 | struct ath5k_hw *ah = hw->priv; |
8a63facc BC |
2726 | struct ath_common *common = ath5k_hw_common(ah); |
2727 | int ret, i; | |
fa1c114f | 2728 | |
e0d687bd | 2729 | mutex_lock(&ah->lock); |
8a63facc | 2730 | |
e0d687bd | 2731 | ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "mode %d\n", ah->opmode); |
fa1c114f | 2732 | |
fa1c114f | 2733 | /* |
8a63facc BC |
2734 | * Stop anything previously setup. This is safe |
2735 | * no matter this is the first time through or not. | |
fa1c114f | 2736 | */ |
e0d687bd | 2737 | ath5k_stop_locked(ah); |
fa1c114f | 2738 | |
8a63facc BC |
2739 | /* |
2740 | * The basic interface to setting the hardware in a good | |
2741 | * state is ``reset''. On return the hardware is known to | |
2742 | * be powered up and with interrupts disabled. This must | |
2743 | * be followed by initialization of the appropriate bits | |
2744 | * and then setup of the interrupt mask. | |
2745 | */ | |
675a0b04 | 2746 | ah->curchan = ah->hw->conf.chandef.chan; |
34ce644a NK |
2747 | ah->imask = AR5K_INT_RXOK |
2748 | | AR5K_INT_RXERR | |
2749 | | AR5K_INT_RXEOL | |
2750 | | AR5K_INT_RXORN | |
2751 | | AR5K_INT_TXDESC | |
2752 | | AR5K_INT_TXEOL | |
2753 | | AR5K_INT_FATAL | |
2754 | | AR5K_INT_GLOBAL | |
2755 | | AR5K_INT_MIB; | |
fa1c114f | 2756 | |
e0d687bd | 2757 | ret = ath5k_reset(ah, NULL, false); |
8a63facc BC |
2758 | if (ret) |
2759 | goto done; | |
fa1c114f | 2760 | |
84e1e737 NK |
2761 | if (!ath5k_modparam_no_hw_rfkill_switch) |
2762 | ath5k_rfkill_hw_start(ah); | |
8a63facc BC |
2763 | |
2764 | /* | |
2765 | * Reset the key cache since some parts do not reset the | |
2766 | * contents on initial power up or resume from suspend. | |
2767 | */ | |
2768 | for (i = 0; i < common->keymax; i++) | |
2769 | ath_hw_keyreset(common, (u16) i); | |
2770 | ||
61cde037 NK |
2771 | /* Use higher rates for acks instead of base |
2772 | * rate */ | |
2773 | ah->ah_ack_bitrate_high = true; | |
b1ae1edf | 2774 | |
e0d687bd PR |
2775 | for (i = 0; i < ARRAY_SIZE(ah->bslot); i++) |
2776 | ah->bslot[i] = NULL; | |
b1ae1edf | 2777 | |
8a63facc BC |
2778 | ret = 0; |
2779 | done: | |
2780 | mmiowb(); | |
e0d687bd | 2781 | mutex_unlock(&ah->lock); |
4edd761f | 2782 | |
db178340 | 2783 | set_bit(ATH_STAT_STARTED, ah->status); |
e0d687bd | 2784 | ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work, |
4edd761f BR |
2785 | msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT)); |
2786 | ||
8a63facc BC |
2787 | return ret; |
2788 | } | |
2789 | ||
e0d687bd | 2790 | static void ath5k_stop_tasklets(struct ath5k_hw *ah) |
8a63facc | 2791 | { |
e0d687bd PR |
2792 | ah->rx_pending = false; |
2793 | ah->tx_pending = false; | |
2794 | tasklet_kill(&ah->rxtq); | |
2795 | tasklet_kill(&ah->txtq); | |
e0d687bd PR |
2796 | tasklet_kill(&ah->beacontq); |
2797 | tasklet_kill(&ah->ani_tasklet); | |
8a63facc BC |
2798 | } |
2799 | ||
2800 | /* | |
2801 | * Stop the device, grabbing the top-level lock to protect | |
2802 | * against concurrent entry through ath5k_init (which can happen | |
2803 | * if another thread does a system call and the thread doing the | |
2804 | * stop is preempted). | |
2805 | */ | |
fabba048 | 2806 | void ath5k_stop(struct ieee80211_hw *hw) |
8a63facc | 2807 | { |
fabba048 | 2808 | struct ath5k_hw *ah = hw->priv; |
8a63facc BC |
2809 | int ret; |
2810 | ||
e0d687bd PR |
2811 | mutex_lock(&ah->lock); |
2812 | ret = ath5k_stop_locked(ah); | |
2813 | if (ret == 0 && !test_bit(ATH_STAT_INVALID, ah->status)) { | |
8a63facc BC |
2814 | /* |
2815 | * Don't set the card in full sleep mode! | |
2816 | * | |
2817 | * a) When the device is in this state it must be carefully | |
2818 | * woken up or references to registers in the PCI clock | |
2819 | * domain may freeze the bus (and system). This varies | |
2820 | * by chip and is mostly an issue with newer parts | |
2821 | * (madwifi sources mentioned srev >= 0x78) that go to | |
2822 | * sleep more quickly. | |
2823 | * | |
2824 | * b) On older chips full sleep results a weird behaviour | |
2825 | * during wakeup. I tested various cards with srev < 0x78 | |
2826 | * and they don't wake up after module reload, a second | |
2827 | * module reload is needed to bring the card up again. | |
2828 | * | |
2829 | * Until we figure out what's going on don't enable | |
2830 | * full chip reset on any chip (this is what Legacy HAL | |
2831 | * and Sam's HAL do anyway). Instead Perform a full reset | |
2832 | * on the device (same as initial state after attach) and | |
2833 | * leave it idle (keep MAC/BB on warm reset) */ | |
e0d687bd | 2834 | ret = ath5k_hw_on_hold(ah); |
8a63facc | 2835 | |
e0d687bd | 2836 | ATH5K_DBG(ah, ATH5K_DEBUG_RESET, |
8a63facc | 2837 | "putting device to sleep\n"); |
fa1c114f JS |
2838 | } |
2839 | ||
8a63facc | 2840 | mmiowb(); |
e0d687bd | 2841 | mutex_unlock(&ah->lock); |
8a63facc | 2842 | |
e0d687bd | 2843 | ath5k_stop_tasklets(ah); |
4edd761f | 2844 | |
db178340 | 2845 | clear_bit(ATH_STAT_STARTED, ah->status); |
e0d687bd | 2846 | cancel_delayed_work_sync(&ah->tx_complete_work); |
8a63facc | 2847 | |
84e1e737 NK |
2848 | if (!ath5k_modparam_no_hw_rfkill_switch) |
2849 | ath5k_rfkill_hw_stop(ah); | |
fa1c114f JS |
2850 | } |
2851 | ||
209d889b BC |
2852 | /* |
2853 | * Reset the hardware. If chan is not NULL, then also pause rx/tx | |
2854 | * and change to the given channel. | |
5faaff74 | 2855 | * |
e0d687bd | 2856 | * This should be called with ah->lock. |
209d889b | 2857 | */ |
fa1c114f | 2858 | static int |
e0d687bd | 2859 | ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan, |
8aec7af9 | 2860 | bool skip_pcu) |
fa1c114f | 2861 | { |
f15a4bb2 | 2862 | struct ath_common *common = ath5k_hw_common(ah); |
344b54b9 | 2863 | int ret, ani_mode; |
4a2f248f | 2864 | bool fast = chan && modparam_fastchanswitch ? 1 : 0; |
fa1c114f | 2865 | |
e0d687bd | 2866 | ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "resetting\n"); |
fa1c114f | 2867 | |
ab5e290a SR |
2868 | __set_bit(ATH_STAT_RESET, ah->status); |
2869 | ||
450464de | 2870 | ath5k_hw_set_imr(ah, 0); |
e0d687bd PR |
2871 | synchronize_irq(ah->irq); |
2872 | ath5k_stop_tasklets(ah); | |
450464de | 2873 | |
25985edc | 2874 | /* Save ani mode and disable ANI during |
344b54b9 NK |
2875 | * reset. If we don't we might get false |
2876 | * PHY error interrupts. */ | |
e0d687bd | 2877 | ani_mode = ah->ani_state.ani_mode; |
344b54b9 NK |
2878 | ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF); |
2879 | ||
19252ecb NK |
2880 | /* We are going to empty hw queues |
2881 | * so we should also free any remaining | |
2882 | * tx buffers */ | |
e0d687bd | 2883 | ath5k_drain_tx_buffs(ah); |
4a2f248f SR |
2884 | |
2885 | /* Stop PCU */ | |
2886 | ath5k_hw_stop_rx_pcu(ah); | |
2887 | ||
2888 | /* Stop DMA | |
2889 | * | |
2890 | * Note: If DMA didn't stop continue | |
2891 | * since only a reset will fix it. | |
2892 | */ | |
2893 | ret = ath5k_hw_dma_stop(ah); | |
2894 | ||
2895 | /* RF Bus grant won't work if we have pending | |
2896 | * frames | |
2897 | */ | |
2898 | if (ret && fast) { | |
2899 | ATH5K_DBG(ah, ATH5K_DEBUG_RESET, | |
2900 | "DMA didn't stop, falling back to normal reset\n"); | |
2901 | fast = false; | |
2902 | } | |
2903 | ||
930a7622 | 2904 | if (chan) |
e0d687bd | 2905 | ah->curchan = chan; |
a99168ee | 2906 | |
e0d687bd | 2907 | ret = ath5k_hw_reset(ah, ah->opmode, ah->curchan, fast, skip_pcu); |
d7dc1003 | 2908 | if (ret) { |
e0d687bd | 2909 | ATH5K_ERR(ah, "can't reset hardware (%d)\n", ret); |
fa1c114f JS |
2910 | goto err; |
2911 | } | |
d7dc1003 | 2912 | |
e0d687bd | 2913 | ret = ath5k_rx_start(ah); |
d7dc1003 | 2914 | if (ret) { |
e0d687bd | 2915 | ATH5K_ERR(ah, "can't start recv logic\n"); |
fa1c114f JS |
2916 | goto err; |
2917 | } | |
d7dc1003 | 2918 | |
344b54b9 | 2919 | ath5k_ani_init(ah, ani_mode); |
2111ac0d | 2920 | |
ce169aca NK |
2921 | /* |
2922 | * Set calibration intervals | |
2923 | * | |
2924 | * Note: We don't need to run calibration imediately | |
2925 | * since some initial calibration is done on reset | |
2926 | * even for fast channel switching. Also on scanning | |
2927 | * this will get set again and again and it won't get | |
2928 | * executed unless we connect somewhere and spend some | |
2929 | * time on the channel (that's what calibration needs | |
2930 | * anyway to be accurate). | |
2931 | */ | |
2932 | ah->ah_cal_next_full = jiffies + | |
2933 | msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL); | |
2934 | ah->ah_cal_next_ani = jiffies + | |
2935 | msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI); | |
2936 | ah->ah_cal_next_short = jiffies + | |
2937 | msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT); | |
2938 | ||
46f26ddf | 2939 | ewma_beacon_rssi_init(&ah->ah_beacon_rssi_avg); |
afe86286 | 2940 | |
f15a4bb2 | 2941 | /* clear survey data and cycle counters */ |
e0d687bd | 2942 | memset(&ah->survey, 0, sizeof(ah->survey)); |
bb007554 | 2943 | spin_lock_bh(&common->cc_lock); |
f15a4bb2 BR |
2944 | ath_hw_cycle_counters_update(common); |
2945 | memset(&common->cc_survey, 0, sizeof(common->cc_survey)); | |
2946 | memset(&common->cc_ani, 0, sizeof(common->cc_ani)); | |
bb007554 | 2947 | spin_unlock_bh(&common->cc_lock); |
f15a4bb2 | 2948 | |
fa1c114f | 2949 | /* |
d7dc1003 JS |
2950 | * Change channels and update the h/w rate map if we're switching; |
2951 | * e.g. 11a to 11b/g. | |
2952 | * | |
2953 | * We may be doing a reset in response to an ioctl that changes the | |
2954 | * channel so update any state that might change as a result. | |
fa1c114f JS |
2955 | * |
2956 | * XXX needed? | |
2957 | */ | |
e0d687bd | 2958 | /* ath5k_chan_change(ah, c); */ |
fa1c114f | 2959 | |
ab5e290a SR |
2960 | __clear_bit(ATH_STAT_RESET, ah->status); |
2961 | ||
e0d687bd | 2962 | ath5k_beacon_config(ah); |
d7dc1003 | 2963 | /* intrs are enabled by ath5k_beacon_config */ |
fa1c114f | 2964 | |
e0d687bd | 2965 | ieee80211_wake_queues(ah->hw); |
397f385b | 2966 | |
fa1c114f JS |
2967 | return 0; |
2968 | err: | |
2969 | return ret; | |
2970 | } | |
2971 | ||
5faaff74 BC |
2972 | static void ath5k_reset_work(struct work_struct *work) |
2973 | { | |
e0d687bd | 2974 | struct ath5k_hw *ah = container_of(work, struct ath5k_hw, |
5faaff74 BC |
2975 | reset_work); |
2976 | ||
e0d687bd PR |
2977 | mutex_lock(&ah->lock); |
2978 | ath5k_reset(ah, NULL, true); | |
2979 | mutex_unlock(&ah->lock); | |
5faaff74 BC |
2980 | } |
2981 | ||
e829cf96 | 2982 | static int |
132b1c3e | 2983 | ath5k_init(struct ieee80211_hw *hw) |
fa1c114f | 2984 | { |
132b1c3e | 2985 | |
e0d687bd | 2986 | struct ath5k_hw *ah = hw->priv; |
8a63facc | 2987 | struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah); |
925e0b06 | 2988 | struct ath5k_txq *txq; |
8a63facc | 2989 | u8 mac[ETH_ALEN] = {}; |
fa1c114f JS |
2990 | int ret; |
2991 | ||
fa1c114f | 2992 | |
8a63facc BC |
2993 | /* |
2994 | * Collect the channel list. The 802.11 layer | |
6a2a0e73 | 2995 | * is responsible for filtering this list based |
8a63facc BC |
2996 | * on settings like the phy mode and regulatory |
2997 | * domain restrictions. | |
2998 | */ | |
2999 | ret = ath5k_setup_bands(hw); | |
3000 | if (ret) { | |
e0d687bd | 3001 | ATH5K_ERR(ah, "can't get channels\n"); |
8a63facc BC |
3002 | goto err; |
3003 | } | |
67d2e2df | 3004 | |
8a63facc BC |
3005 | /* |
3006 | * Allocate tx+rx descriptors and populate the lists. | |
3007 | */ | |
e0d687bd | 3008 | ret = ath5k_desc_alloc(ah); |
8a63facc | 3009 | if (ret) { |
e0d687bd | 3010 | ATH5K_ERR(ah, "can't allocate descriptors\n"); |
8a63facc BC |
3011 | goto err; |
3012 | } | |
fa1c114f | 3013 | |
8a63facc BC |
3014 | /* |
3015 | * Allocate hardware transmit queues: one queue for | |
3016 | * beacon frames and one data queue for each QoS | |
3017 | * priority. Note that hw functions handle resetting | |
3018 | * these queues at the needed time. | |
3019 | */ | |
3020 | ret = ath5k_beaconq_setup(ah); | |
3021 | if (ret < 0) { | |
e0d687bd | 3022 | ATH5K_ERR(ah, "can't setup a beacon xmit queue\n"); |
8a63facc BC |
3023 | goto err_desc; |
3024 | } | |
e0d687bd PR |
3025 | ah->bhalq = ret; |
3026 | ah->cabq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_CAB, 0); | |
3027 | if (IS_ERR(ah->cabq)) { | |
3028 | ATH5K_ERR(ah, "can't setup cab queue\n"); | |
3029 | ret = PTR_ERR(ah->cabq); | |
8a63facc BC |
3030 | goto err_bhal; |
3031 | } | |
fa1c114f | 3032 | |
22d8d9f8 BR |
3033 | /* 5211 and 5212 usually support 10 queues but we better rely on the |
3034 | * capability information */ | |
3035 | if (ah->ah_capabilities.cap_queues.q_tx_num >= 6) { | |
3036 | /* This order matches mac80211's queue priority, so we can | |
3037 | * directly use the mac80211 queue number without any mapping */ | |
e0d687bd | 3038 | txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO); |
22d8d9f8 | 3039 | if (IS_ERR(txq)) { |
e0d687bd | 3040 | ATH5K_ERR(ah, "can't setup xmit queue\n"); |
22d8d9f8 BR |
3041 | ret = PTR_ERR(txq); |
3042 | goto err_queues; | |
3043 | } | |
e0d687bd | 3044 | txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI); |
22d8d9f8 | 3045 | if (IS_ERR(txq)) { |
e0d687bd | 3046 | ATH5K_ERR(ah, "can't setup xmit queue\n"); |
22d8d9f8 BR |
3047 | ret = PTR_ERR(txq); |
3048 | goto err_queues; | |
3049 | } | |
e0d687bd | 3050 | txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE); |
22d8d9f8 | 3051 | if (IS_ERR(txq)) { |
e0d687bd | 3052 | ATH5K_ERR(ah, "can't setup xmit queue\n"); |
22d8d9f8 BR |
3053 | ret = PTR_ERR(txq); |
3054 | goto err_queues; | |
3055 | } | |
e0d687bd | 3056 | txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK); |
22d8d9f8 | 3057 | if (IS_ERR(txq)) { |
e0d687bd | 3058 | ATH5K_ERR(ah, "can't setup xmit queue\n"); |
22d8d9f8 BR |
3059 | ret = PTR_ERR(txq); |
3060 | goto err_queues; | |
3061 | } | |
3062 | hw->queues = 4; | |
3063 | } else { | |
3064 | /* older hardware (5210) can only support one data queue */ | |
e0d687bd | 3065 | txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE); |
22d8d9f8 | 3066 | if (IS_ERR(txq)) { |
e0d687bd | 3067 | ATH5K_ERR(ah, "can't setup xmit queue\n"); |
22d8d9f8 BR |
3068 | ret = PTR_ERR(txq); |
3069 | goto err_queues; | |
3070 | } | |
3071 | hw->queues = 1; | |
3072 | } | |
fa1c114f | 3073 | |
e0d687bd PR |
3074 | tasklet_init(&ah->rxtq, ath5k_tasklet_rx, (unsigned long)ah); |
3075 | tasklet_init(&ah->txtq, ath5k_tasklet_tx, (unsigned long)ah); | |
e0d687bd PR |
3076 | tasklet_init(&ah->beacontq, ath5k_tasklet_beacon, (unsigned long)ah); |
3077 | tasklet_init(&ah->ani_tasklet, ath5k_tasklet_ani, (unsigned long)ah); | |
be009370 | 3078 | |
e0d687bd | 3079 | INIT_WORK(&ah->reset_work, ath5k_reset_work); |
ce169aca | 3080 | INIT_WORK(&ah->calib_work, ath5k_calibrate_work); |
e0d687bd | 3081 | INIT_DELAYED_WORK(&ah->tx_complete_work, ath5k_tx_complete_poll_work); |
fa1c114f | 3082 | |
fa9bfd61 | 3083 | ret = ath5k_hw_common(ah)->bus_ops->eeprom_read_mac(ah, mac); |
8a63facc | 3084 | if (ret) { |
e0d687bd | 3085 | ATH5K_ERR(ah, "unable to read address from EEPROM\n"); |
8a63facc | 3086 | goto err_queues; |
e30eb4ab | 3087 | } |
2bed03eb | 3088 | |
8a63facc BC |
3089 | SET_IEEE80211_PERM_ADDR(hw, mac); |
3090 | /* All MAC address bits matter for ACKs */ | |
e0d687bd | 3091 | ath5k_update_bssid_mask_and_opmode(ah, NULL); |
8a63facc BC |
3092 | |
3093 | regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain; | |
3094 | ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier); | |
3095 | if (ret) { | |
e0d687bd | 3096 | ATH5K_ERR(ah, "can't initialize regulatory system\n"); |
8a63facc BC |
3097 | goto err_queues; |
3098 | } | |
3099 | ||
3100 | ret = ieee80211_register_hw(hw); | |
3101 | if (ret) { | |
e0d687bd | 3102 | ATH5K_ERR(ah, "can't register ieee80211 hw\n"); |
8a63facc BC |
3103 | goto err_queues; |
3104 | } | |
3105 | ||
3106 | if (!ath_is_world_regd(regulatory)) | |
3107 | regulatory_hint(hw->wiphy, regulatory->alpha2); | |
3108 | ||
e0d687bd | 3109 | ath5k_init_leds(ah); |
8a63facc | 3110 | |
e0d687bd | 3111 | ath5k_sysfs_register(ah); |
8a63facc BC |
3112 | |
3113 | return 0; | |
3114 | err_queues: | |
e0d687bd | 3115 | ath5k_txq_release(ah); |
8a63facc | 3116 | err_bhal: |
e0d687bd | 3117 | ath5k_hw_release_tx_queue(ah, ah->bhalq); |
8a63facc | 3118 | err_desc: |
e0d687bd | 3119 | ath5k_desc_free(ah); |
8a63facc BC |
3120 | err: |
3121 | return ret; | |
3122 | } | |
3123 | ||
132b1c3e | 3124 | void |
bb1f3ad9 | 3125 | ath5k_deinit_ah(struct ath5k_hw *ah) |
8a63facc | 3126 | { |
e0d687bd | 3127 | struct ieee80211_hw *hw = ah->hw; |
8a63facc BC |
3128 | |
3129 | /* | |
3130 | * NB: the order of these is important: | |
3131 | * o call the 802.11 layer before detaching ath5k_hw to | |
3132 | * ensure callbacks into the driver to delete global | |
3133 | * key cache entries can be handled | |
3134 | * o reclaim the tx queue data structures after calling | |
3135 | * the 802.11 layer as we'll get called back to reclaim | |
3136 | * node state and potentially want to use them | |
3137 | * o to cleanup the tx queues the hal is called, so detach | |
3138 | * it last | |
3139 | * XXX: ??? detach ath5k_hw ??? | |
3140 | * Other than that, it's straightforward... | |
3141 | */ | |
3142 | ieee80211_unregister_hw(hw); | |
e0d687bd PR |
3143 | ath5k_desc_free(ah); |
3144 | ath5k_txq_release(ah); | |
3145 | ath5k_hw_release_tx_queue(ah, ah->bhalq); | |
3146 | ath5k_unregister_leds(ah); | |
8a63facc | 3147 | |
e0d687bd | 3148 | ath5k_sysfs_unregister(ah); |
8a63facc BC |
3149 | /* |
3150 | * NB: can't reclaim these until after ieee80211_ifdetach | |
3151 | * returns because we'll get called back to reclaim node | |
3152 | * state and potentially want to use them. | |
3153 | */ | |
e0d687bd PR |
3154 | ath5k_hw_deinit(ah); |
3155 | free_irq(ah->irq, ah); | |
8a63facc BC |
3156 | } |
3157 | ||
cd2c5486 | 3158 | bool |
e0d687bd | 3159 | ath5k_any_vif_assoc(struct ath5k_hw *ah) |
b1ae1edf | 3160 | { |
e4b0b32a | 3161 | struct ath5k_vif_iter_data iter_data; |
b1ae1edf BG |
3162 | iter_data.hw_macaddr = NULL; |
3163 | iter_data.any_assoc = false; | |
3164 | iter_data.need_set_hw_addr = false; | |
3165 | iter_data.found_active = true; | |
3166 | ||
8b2c9824 JB |
3167 | ieee80211_iterate_active_interfaces_atomic( |
3168 | ah->hw, IEEE80211_IFACE_ITER_RESUME_ALL, | |
3169 | ath5k_vif_iter, &iter_data); | |
b1ae1edf BG |
3170 | return iter_data.any_assoc; |
3171 | } | |
3172 | ||
cd2c5486 | 3173 | void |
f5cbc8ba | 3174 | ath5k_set_beacon_filter(struct ieee80211_hw *hw, bool enable) |
8a63facc | 3175 | { |
e0d687bd | 3176 | struct ath5k_hw *ah = hw->priv; |
8a63facc BC |
3177 | u32 rfilt; |
3178 | rfilt = ath5k_hw_get_rx_filter(ah); | |
3179 | if (enable) | |
3180 | rfilt |= AR5K_RX_FILTER_BEACON; | |
3181 | else | |
3182 | rfilt &= ~AR5K_RX_FILTER_BEACON; | |
3183 | ath5k_hw_set_rx_filter(ah, rfilt); | |
e0d687bd | 3184 | ah->filter_flags = rfilt; |
8a63facc | 3185 | } |
227842d1 JP |
3186 | |
3187 | void _ath5k_printk(const struct ath5k_hw *ah, const char *level, | |
3188 | const char *fmt, ...) | |
3189 | { | |
3190 | struct va_format vaf; | |
3191 | va_list args; | |
3192 | ||
3193 | va_start(args, fmt); | |
3194 | ||
3195 | vaf.fmt = fmt; | |
3196 | vaf.va = &args; | |
3197 | ||
3198 | if (ah && ah->hw) | |
3199 | printk("%s" pr_fmt("%s: %pV"), | |
3200 | level, wiphy_name(ah->hw->wiphy), &vaf); | |
3201 | else | |
3202 | printk("%s" pr_fmt("%pV"), level, &vaf); | |
3203 | ||
3204 | va_end(args); | |
3205 | } |