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ath5k: Enable AP mode
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / wireless / ath / ath5k / base.c
CommitLineData
fa1c114f
JS		 1/*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
fa1c114f
JS		 43#include <linux/module.h>
44#include <linux/delay.h>
274c7c36 45#include <linux/hardirq.h>
fa1c114f 46#include <linux/if.h>
274c7c36 47#include <linux/io.h>
fa1c114f
JS		 48#include <linux/netdevice.h>
49#include <linux/cache.h>
50#include <linux/pci.h>
51#include <linux/ethtool.h>
52#include <linux/uaccess.h>
53
54#include <net/ieee80211_radiotap.h>
55
56#include <asm/unaligned.h>
57
58#include "base.h"
59#include "reg.h"
60#include "debug.h"
61
fa1c114f 62static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
9ad9a26e 63static int modparam_nohwcrypt;
46802a4f 64module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
9ad9a26e 65MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
fa1c114f 66
42639fcd 67static int modparam_all_channels;
46802a4f 68module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
42639fcd
BC		 69MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
70
fa1c114f
JS		 71
72/******************\
73* Internal defines *
74\******************/
75
76/* Module info */
77MODULE_AUTHOR("Jiri Slaby");
78MODULE_AUTHOR("Nick Kossifidis");
79MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
80MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
81MODULE_LICENSE("Dual BSD/GPL");
0d5f0316 82MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
fa1c114f
JS		 83
84
85/* Known PCI ids */
2c91108c 86static const struct pci_device_id ath5k_pci_id_table[] = {
fa1c114f
JS		 87 { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
88 { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
89 { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
90 { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
91 { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
92 { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
93 { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
94 { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
95 { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
96 { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
102 { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
0d5f0316
NK		 103 { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* PCI-E cards */
104 { PCI_VDEVICE(ATHEROS, 0x001d), .driver_data = AR5K_AR5212 }, /* 2417 Nala */
fa1c114f
JS		 105 { 0 }
106};
107MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
108
109/* Known SREVs */
2c91108c 110static const struct ath5k_srev_name srev_names[] = {
1bef016a
NK		 111 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
112 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
113 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
114 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
115 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
116 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
117 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
118 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
119 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
120 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
121 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
122 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
123 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
124 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
125 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
126 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
127 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
128 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
129 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
fa1c114f
JS		 130 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
131 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
1bef016a 132 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
fa1c114f
JS		 133 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
134 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
135 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
1bef016a 136 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
fa1c114f
JS		 137 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
138 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
1bef016a
NK		 139 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
140 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
141 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
142 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
143 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
144 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
fa1c114f
JS		 145 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
146 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
147};
148
2c91108c 149static const struct ieee80211_rate ath5k_rates[] = {
63266a65
BR		 150 { .bitrate = 10,
151 .hw_value = ATH5K_RATE_CODE_1M, },
152 { .bitrate = 20,
153 .hw_value = ATH5K_RATE_CODE_2M,
154 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
155 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
156 { .bitrate = 55,
157 .hw_value = ATH5K_RATE_CODE_5_5M,
158 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
159 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
160 { .bitrate = 110,
161 .hw_value = ATH5K_RATE_CODE_11M,
162 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
163 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
164 { .bitrate = 60,
165 .hw_value = ATH5K_RATE_CODE_6M,
166 .flags = 0 },
167 { .bitrate = 90,
168 .hw_value = ATH5K_RATE_CODE_9M,
169 .flags = 0 },
170 { .bitrate = 120,
171 .hw_value = ATH5K_RATE_CODE_12M,
172 .flags = 0 },
173 { .bitrate = 180,
174 .hw_value = ATH5K_RATE_CODE_18M,
175 .flags = 0 },
176 { .bitrate = 240,
177 .hw_value = ATH5K_RATE_CODE_24M,
178 .flags = 0 },
179 { .bitrate = 360,
180 .hw_value = ATH5K_RATE_CODE_36M,
181 .flags = 0 },
182 { .bitrate = 480,
183 .hw_value = ATH5K_RATE_CODE_48M,
184 .flags = 0 },
185 { .bitrate = 540,
186 .hw_value = ATH5K_RATE_CODE_54M,
187 .flags = 0 },
188 /* XR missing */
189};
190
fa1c114f
JS		 191/*
192 * Prototypes - PCI stack related functions
193 */
194static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
195 const struct pci_device_id *id);
196static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
197#ifdef CONFIG_PM
198static int ath5k_pci_suspend(struct pci_dev *pdev,
199 pm_message_t state);
200static int ath5k_pci_resume(struct pci_dev *pdev);
201#else
202#define ath5k_pci_suspend NULL
203#define ath5k_pci_resume NULL
204#endif /* CONFIG_PM */
205
04a9e451 206static struct pci_driver ath5k_pci_driver = {
9764f3f9 207 .name = KBUILD_MODNAME,
fa1c114f
JS		 208 .id_table = ath5k_pci_id_table,
209 .probe = ath5k_pci_probe,
210 .remove = __devexit_p(ath5k_pci_remove),
211 .suspend = ath5k_pci_suspend,
212 .resume = ath5k_pci_resume,
213};
214
215
216
217/*
218 * Prototypes - MAC 802.11 stack related functions
219 */
e039fa4a 220static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
d7dc1003
JS		 221static int ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel);
222static int ath5k_reset_wake(struct ath5k_softc *sc);
fa1c114f
JS		 223static int ath5k_start(struct ieee80211_hw *hw);
224static void ath5k_stop(struct ieee80211_hw *hw);
225static int ath5k_add_interface(struct ieee80211_hw *hw,
226 struct ieee80211_if_init_conf *conf);
227static void ath5k_remove_interface(struct ieee80211_hw *hw,
228 struct ieee80211_if_init_conf *conf);
e8975581 229static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
fa1c114f
JS		 230static void ath5k_configure_filter(struct ieee80211_hw *hw,
231 unsigned int changed_flags,
232 unsigned int *new_flags,
233 int mc_count, struct dev_mc_list *mclist);
234static int ath5k_set_key(struct ieee80211_hw *hw,
235 enum set_key_cmd cmd,
dc822b5d 236 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
fa1c114f
JS		 237 struct ieee80211_key_conf *key);
238static int ath5k_get_stats(struct ieee80211_hw *hw,
239 struct ieee80211_low_level_stats *stats);
240static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
241 struct ieee80211_tx_queue_stats *stats);
242static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
3b5d665b 243static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf);
fa1c114f 244static void ath5k_reset_tsf(struct ieee80211_hw *hw);
5b9ab2ec 245static int ath5k_beacon_update(struct ath5k_softc *sc,
e039fa4a 246 struct sk_buff *skb);
02969b38
MX		 247static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
248 struct ieee80211_vif *vif,
249 struct ieee80211_bss_conf *bss_conf,
250 u32 changes);
fa1c114f 251
2c91108c 252static const struct ieee80211_ops ath5k_hw_ops = {
fa1c114f
JS		 253 .tx = ath5k_tx,
254 .start = ath5k_start,
255 .stop = ath5k_stop,
256 .add_interface = ath5k_add_interface,
257 .remove_interface = ath5k_remove_interface,
258 .config = ath5k_config,
fa1c114f
JS		 259 .configure_filter = ath5k_configure_filter,
260 .set_key = ath5k_set_key,
261 .get_stats = ath5k_get_stats,
262 .conf_tx = NULL,
263 .get_tx_stats = ath5k_get_tx_stats,
264 .get_tsf = ath5k_get_tsf,
3b5d665b 265 .set_tsf = ath5k_set_tsf,
fa1c114f 266 .reset_tsf = ath5k_reset_tsf,
02969b38 267 .bss_info_changed = ath5k_bss_info_changed,
fa1c114f
JS		 268};
269
270/*
271 * Prototypes - Internal functions
272 */
273/* Attach detach */
274static int ath5k_attach(struct pci_dev *pdev,
275 struct ieee80211_hw *hw);
276static void ath5k_detach(struct pci_dev *pdev,
277 struct ieee80211_hw *hw);
278/* Channel/mode setup */
279static inline short ath5k_ieee2mhz(short chan);
fa1c114f
JS		 280static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
281 struct ieee80211_channel *channels,
282 unsigned int mode,
283 unsigned int max);
63266a65 284static int ath5k_setup_bands(struct ieee80211_hw *hw);
fa1c114f
JS		 285static int ath5k_chan_set(struct ath5k_softc *sc,
286 struct ieee80211_channel *chan);
287static void ath5k_setcurmode(struct ath5k_softc *sc,
288 unsigned int mode);
289static void ath5k_mode_setup(struct ath5k_softc *sc);
d8ee398d 290
fa1c114f
JS		 291/* Descriptor setup */
292static int ath5k_desc_alloc(struct ath5k_softc *sc,
293 struct pci_dev *pdev);
294static void ath5k_desc_free(struct ath5k_softc *sc,
295 struct pci_dev *pdev);
296/* Buffers setup */
297static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
298 struct ath5k_buf *bf);
299static int ath5k_txbuf_setup(struct ath5k_softc *sc,
e039fa4a 300 struct ath5k_buf *bf);
fa1c114f
JS		 301static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
302 struct ath5k_buf *bf)
303{
304 BUG_ON(!bf);
305 if (!bf->skb)
306 return;
307 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
308 PCI_DMA_TODEVICE);
00482973 309 dev_kfree_skb_any(bf->skb);
fa1c114f
JS		 310 bf->skb = NULL;
311}
312
a6c8d375
FF		 313static inline void ath5k_rxbuf_free(struct ath5k_softc *sc,
314 struct ath5k_buf *bf)
315{
316 BUG_ON(!bf);
317 if (!bf->skb)
318 return;
319 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
320 PCI_DMA_FROMDEVICE);
321 dev_kfree_skb_any(bf->skb);
322 bf->skb = NULL;
323}
324
325
fa1c114f
JS		 326/* Queues setup */
327static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
328 int qtype, int subtype);
329static int ath5k_beaconq_setup(struct ath5k_hw *ah);
330static int ath5k_beaconq_config(struct ath5k_softc *sc);
331static void ath5k_txq_drainq(struct ath5k_softc *sc,
332 struct ath5k_txq *txq);
333static void ath5k_txq_cleanup(struct ath5k_softc *sc);
334static void ath5k_txq_release(struct ath5k_softc *sc);
335/* Rx handling */
336static int ath5k_rx_start(struct ath5k_softc *sc);
337static void ath5k_rx_stop(struct ath5k_softc *sc);
338static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
339 struct ath5k_desc *ds,
b47f407b
BR		 340 struct sk_buff *skb,
341 struct ath5k_rx_status *rs);
fa1c114f
JS		 342static void ath5k_tasklet_rx(unsigned long data);
343/* Tx handling */
344static void ath5k_tx_processq(struct ath5k_softc *sc,
345 struct ath5k_txq *txq);
346static void ath5k_tasklet_tx(unsigned long data);
347/* Beacon handling */
348static int ath5k_beacon_setup(struct ath5k_softc *sc,
e039fa4a 349 struct ath5k_buf *bf);
fa1c114f
JS		 350static void ath5k_beacon_send(struct ath5k_softc *sc);
351static void ath5k_beacon_config(struct ath5k_softc *sc);
9804b98d 352static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
acf3c1a5 353static void ath5k_tasklet_beacon(unsigned long data);
fa1c114f
JS		 354
355static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
356{
357 u64 tsf = ath5k_hw_get_tsf64(ah);
358
359 if ((tsf & 0x7fff) < rstamp)
360 tsf -= 0x8000;
361
362 return (tsf & ~0x7fff) | rstamp;
363}
364
365/* Interrupt handling */
bb2becac 366static int ath5k_init(struct ath5k_softc *sc);
fa1c114f 367static int ath5k_stop_locked(struct ath5k_softc *sc);
bb2becac 368static int ath5k_stop_hw(struct ath5k_softc *sc);
fa1c114f
JS		 369static irqreturn_t ath5k_intr(int irq, void *dev_id);
370static void ath5k_tasklet_reset(unsigned long data);
371
372static void ath5k_calibrate(unsigned long data);
fa1c114f
JS		 373
374/*
375 * Module init/exit functions
376 */
377static int __init
378init_ath5k_pci(void)
379{
380 int ret;
381
382 ath5k_debug_init();
383
04a9e451 384 ret = pci_register_driver(&ath5k_pci_driver);
fa1c114f
JS		 385 if (ret) {
386 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
387 return ret;
388 }
389
390 return 0;
391}
392
393static void __exit
394exit_ath5k_pci(void)
395{
04a9e451 396 pci_unregister_driver(&ath5k_pci_driver);
fa1c114f
JS		 397
398 ath5k_debug_finish();
399}
400
401module_init(init_ath5k_pci);
402module_exit(exit_ath5k_pci);
403
404
405/********************\
406* PCI Initialization *
407\********************/
408
409static const char *
410ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
411{
412 const char *name = "xxxxx";
413 unsigned int i;
414
415 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
416 if (srev_names[i].sr_type != type)
417 continue;
75d0edb8
NK		 418
419 if ((val & 0xf0) == srev_names[i].sr_val)
420 name = srev_names[i].sr_name;
421
422 if ((val & 0xff) == srev_names[i].sr_val) {
fa1c114f
JS		 423 name = srev_names[i].sr_name;
424 break;
425 }
426 }
427
428 return name;
429}
430
431static int __devinit
432ath5k_pci_probe(struct pci_dev *pdev,
433 const struct pci_device_id *id)
434{
435 void __iomem *mem;
436 struct ath5k_softc *sc;
437 struct ieee80211_hw *hw;
438 int ret;
439 u8 csz;
440
441 ret = pci_enable_device(pdev);
442 if (ret) {
443 dev_err(&pdev->dev, "can't enable device\n");
444 goto err;
445 }
446
447 /* XXX 32-bit addressing only */
284901a9 448 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
fa1c114f
JS		 449 if (ret) {
450 dev_err(&pdev->dev, "32-bit DMA not available\n");
451 goto err_dis;
452 }
453
454 /*
455 * Cache line size is used to size and align various
456 * structures used to communicate with the hardware.
457 */
458 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
459 if (csz == 0) {
460 /*
461 * Linux 2.4.18 (at least) writes the cache line size
462 * register as a 16-bit wide register which is wrong.
463 * We must have this setup properly for rx buffer
464 * DMA to work so force a reasonable value here if it
465 * comes up zero.
466 */
467 csz = L1_CACHE_BYTES / sizeof(u32);
468 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
469 }
470 /*
471 * The default setting of latency timer yields poor results,
472 * set it to the value used by other systems. It may be worth
473 * tweaking this setting more.
474 */
475 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
476
477 /* Enable bus mastering */
478 pci_set_master(pdev);
479
480 /*
481 * Disable the RETRY_TIMEOUT register (0x41) to keep
482 * PCI Tx retries from interfering with C3 CPU state.
483 */
484 pci_write_config_byte(pdev, 0x41, 0);
485
486 ret = pci_request_region(pdev, 0, "ath5k");
487 if (ret) {
488 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
489 goto err_dis;
490 }
491
492 mem = pci_iomap(pdev, 0, 0);
493 if (!mem) {
494 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
495 ret = -EIO;
496 goto err_reg;
497 }
498
499 /*
500 * Allocate hw (mac80211 main struct)
501 * and hw->priv (driver private data)
502 */
503 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
504 if (hw == NULL) {
505 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
506 ret = -ENOMEM;
507 goto err_map;
508 }
509
510 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
511
512 /* Initialize driver private data */
513 SET_IEEE80211_DEV(hw, &pdev->dev);
566bfe5a
BR		 514 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
515 IEEE80211_HW_SIGNAL_DBM |
516 IEEE80211_HW_NOISE_DBM;
f59ac048
LR		 517
518 hw->wiphy->interface_modes =
6f5f39c9 519 BIT(NL80211_IFTYPE_AP) |
f59ac048
LR		 520 BIT(NL80211_IFTYPE_STATION) |
521 BIT(NL80211_IFTYPE_ADHOC) |
522 BIT(NL80211_IFTYPE_MESH_POINT);
523
fa1c114f
JS		 524 hw->extra_tx_headroom = 2;
525 hw->channel_change_time = 5000;
fa1c114f
JS		 526 sc = hw->priv;
527 sc->hw = hw;
528 sc->pdev = pdev;
529
530 ath5k_debug_init_device(sc);
531
532 /*
533 * Mark the device as detached to avoid processing
534 * interrupts until setup is complete.
535 */
536 __set_bit(ATH_STAT_INVALID, sc->status);
537
538 sc->iobase = mem; /* So we can unmap it on detach */
539 sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
05c914fe 540 sc->opmode = NL80211_IFTYPE_STATION;
fa1c114f
JS		 541 mutex_init(&sc->lock);
542 spin_lock_init(&sc->rxbuflock);
543 spin_lock_init(&sc->txbuflock);
00482973 544 spin_lock_init(&sc->block);
fa1c114f
JS		 545
546 /* Set private data */
547 pci_set_drvdata(pdev, hw);
548
fa1c114f
JS		 549 /* Setup interrupt handler */
550 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
551 if (ret) {
552 ATH5K_ERR(sc, "request_irq failed\n");
553 goto err_free;
554 }
555
556 /* Initialize device */
557 sc->ah = ath5k_hw_attach(sc, id->driver_data);
558 if (IS_ERR(sc->ah)) {
559 ret = PTR_ERR(sc->ah);
560 goto err_irq;
561 }
562
2f7fe870
FF		 563 /* set up multi-rate retry capabilities */
564 if (sc->ah->ah_version == AR5K_AR5212) {
e6a9854b
JB		 565 hw->max_rates = 4;
566 hw->max_rate_tries = 11;
2f7fe870
FF		 567 }
568
fa1c114f
JS		 569 /* Finish private driver data initialization */
570 ret = ath5k_attach(pdev, hw);
571 if (ret)
572 goto err_ah;
573
574 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
1bef016a 575 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
fa1c114f
JS		 576 sc->ah->ah_mac_srev,
577 sc->ah->ah_phy_revision);
578
400ec45a 579 if (!sc->ah->ah_single_chip) {
fa1c114f 580 /* Single chip radio (!RF5111) */
400ec45a
LR		 581 if (sc->ah->ah_radio_5ghz_revision &&
582 !sc->ah->ah_radio_2ghz_revision) {
fa1c114f 583 /* No 5GHz support -> report 2GHz radio */
400ec45a
LR		 584 if (!test_bit(AR5K_MODE_11A,
585 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 586 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 587 ath5k_chip_name(AR5K_VERSION_RAD,
588 sc->ah->ah_radio_5ghz_revision),
589 sc->ah->ah_radio_5ghz_revision);
590 /* No 2GHz support (5110 and some
591 * 5Ghz only cards) -> report 5Ghz radio */
592 } else if (!test_bit(AR5K_MODE_11B,
593 sc->ah->ah_capabilities.cap_mode)) {
fa1c114f 594 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 595 ath5k_chip_name(AR5K_VERSION_RAD,
596 sc->ah->ah_radio_5ghz_revision),
597 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 598 /* Multiband radio */
599 } else {
600 ATH5K_INFO(sc, "RF%s multiband radio found"
601 " (0x%x)\n",
400ec45a
LR		 602 ath5k_chip_name(AR5K_VERSION_RAD,
603 sc->ah->ah_radio_5ghz_revision),
604 sc->ah->ah_radio_5ghz_revision);
fa1c114f
JS		 605 }
606 }
400ec45a
LR		 607 /* Multi chip radio (RF5111 - RF2111) ->
608 * report both 2GHz/5GHz radios */
609 else if (sc->ah->ah_radio_5ghz_revision &&
610 sc->ah->ah_radio_2ghz_revision){
fa1c114f 611 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
400ec45a
LR		 612 ath5k_chip_name(AR5K_VERSION_RAD,
613 sc->ah->ah_radio_5ghz_revision),
614 sc->ah->ah_radio_5ghz_revision);
fa1c114f 615 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
400ec45a
LR		 616 ath5k_chip_name(AR5K_VERSION_RAD,
617 sc->ah->ah_radio_2ghz_revision),
618 sc->ah->ah_radio_2ghz_revision);
fa1c114f
JS		 619 }
620 }
621
622
623 /* ready to process interrupts */
624 __clear_bit(ATH_STAT_INVALID, sc->status);
625
626 return 0;
627err_ah:
628 ath5k_hw_detach(sc->ah);
629err_irq:
630 free_irq(pdev->irq, sc);
631err_free:
fa1c114f
JS		 632 ieee80211_free_hw(hw);
633err_map:
634 pci_iounmap(pdev, mem);
635err_reg:
636 pci_release_region(pdev, 0);
637err_dis:
638 pci_disable_device(pdev);
639err:
640 return ret;
641}
642
643static void __devexit
644ath5k_pci_remove(struct pci_dev *pdev)
645{
646 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
647 struct ath5k_softc *sc = hw->priv;
648
649 ath5k_debug_finish_device(sc);
650 ath5k_detach(pdev, hw);
651 ath5k_hw_detach(sc->ah);
652 free_irq(pdev->irq, sc);
fa1c114f
JS		 653 pci_iounmap(pdev, sc->iobase);
654 pci_release_region(pdev, 0);
655 pci_disable_device(pdev);
656 ieee80211_free_hw(hw);
657}
658
659#ifdef CONFIG_PM
660static int
661ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
662{
663 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
664 struct ath5k_softc *sc = hw->priv;
665
3a078876 666 ath5k_led_off(sc);
fa1c114f 667
3e4242b9 668 free_irq(pdev->irq, sc);
fa1c114f
JS		 669 pci_save_state(pdev);
670 pci_disable_device(pdev);
671 pci_set_power_state(pdev, PCI_D3hot);
672
673 return 0;
674}
675
676static int
677ath5k_pci_resume(struct pci_dev *pdev)
678{
679 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
680 struct ath5k_softc *sc = hw->priv;
bc1b32d6 681 int err;
fa1c114f 682
3e4242b9 683 pci_restore_state(pdev);
fa1c114f
JS		 684
685 err = pci_enable_device(pdev);
686 if (err)
687 return err;
688
3e4242b9
JS		 689 err = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
690 if (err) {
691 ATH5K_ERR(sc, "request_irq failed\n");
37465c8a 692 goto err_no_irq;
3e4242b9
JS		 693 }
694
3a078876 695 ath5k_led_enable(sc);
fa1c114f 696 return 0;
bb2becac 697
37465c8a 698err_no_irq:
3e4242b9
JS		 699 pci_disable_device(pdev);
700 return err;
fa1c114f
JS		 701}
702#endif /* CONFIG_PM */
703
704
fa1c114f
JS		 705/***********************\
706* Driver Initialization *
707\***********************/
708
f769c36b
BC		 709static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
710{
711 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
712 struct ath5k_softc *sc = hw->priv;
713 struct ath_regulatory *reg = &sc->ah->ah_regulatory;
714
715 return ath_reg_notifier_apply(wiphy, request, reg);
716}
717
fa1c114f
JS		 718static int
719ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
720{
721 struct ath5k_softc *sc = hw->priv;
722 struct ath5k_hw *ah = sc->ah;
0e149cf5 723 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 724 int ret;
725
726 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
727
728 /*
729 * Check if the MAC has multi-rate retry support.
730 * We do this by trying to setup a fake extended
731 * descriptor. MAC's that don't have support will
732 * return false w/o doing anything. MAC's that do
733 * support it will return true w/o doing anything.
734 */
c6e387a2 735 ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
b9887638
JS		 736 if (ret < 0)
737 goto err;
738 if (ret > 0)
fa1c114f
JS		 739 __set_bit(ATH_STAT_MRRETRY, sc->status);
740
fa1c114f
JS		 741 /*
742 * Collect the channel list. The 802.11 layer
743 * is resposible for filtering this list based
744 * on settings like the phy mode and regulatory
745 * domain restrictions.
746 */
63266a65 747 ret = ath5k_setup_bands(hw);
fa1c114f
JS		 748 if (ret) {
749 ATH5K_ERR(sc, "can't get channels\n");
750 goto err;
751 }
752
753 /* NB: setup here so ath5k_rate_update is happy */
d8ee398d
LR		 754 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
755 ath5k_setcurmode(sc, AR5K_MODE_11A);
fa1c114f 756 else
d8ee398d 757 ath5k_setcurmode(sc, AR5K_MODE_11B);
fa1c114f
JS		 758
759 /*
760 * Allocate tx+rx descriptors and populate the lists.
761 */
762 ret = ath5k_desc_alloc(sc, pdev);
763 if (ret) {
764 ATH5K_ERR(sc, "can't allocate descriptors\n");
765 goto err;
766 }
767
768 /*
769 * Allocate hardware transmit queues: one queue for
770 * beacon frames and one data queue for each QoS
771 * priority. Note that hw functions handle reseting
772 * these queues at the needed time.
773 */
774 ret = ath5k_beaconq_setup(ah);
775 if (ret < 0) {
776 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
777 goto err_desc;
778 }
779 sc->bhalq = ret;
780
781 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
782 if (IS_ERR(sc->txq)) {
783 ATH5K_ERR(sc, "can't setup xmit queue\n");
784 ret = PTR_ERR(sc->txq);
785 goto err_bhal;
786 }
787
788 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
789 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
790 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
acf3c1a5 791 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
fa1c114f 792 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
fa1c114f 793
0e149cf5
BC		 794 ret = ath5k_eeprom_read_mac(ah, mac);
795 if (ret) {
796 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
797 sc->pdev->device);
798 goto err_queues;
799 }
800
fa1c114f
JS		 801 SET_IEEE80211_PERM_ADDR(hw, mac);
802 /* All MAC address bits matter for ACKs */
803 memset(sc->bssidmask, 0xff, ETH_ALEN);
804 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
805
f769c36b
BC		 806 ah->ah_regulatory.current_rd =
807 ah->ah_capabilities.cap_eeprom.ee_regdomain;
808 ret = ath_regd_init(&ah->ah_regulatory, hw->wiphy, ath5k_reg_notifier);
809 if (ret) {
810 ATH5K_ERR(sc, "can't initialize regulatory system\n");
811 goto err_queues;
812 }
813
fa1c114f
JS		 814 ret = ieee80211_register_hw(hw);
815 if (ret) {
816 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
817 goto err_queues;
818 }
819
f769c36b
BC		 820 if (!ath_is_world_regd(&sc->ah->ah_regulatory))
821 regulatory_hint(hw->wiphy, sc->ah->ah_regulatory.alpha2);
822
3a078876
BC		 823 ath5k_init_leds(sc);
824
fa1c114f
JS		 825 return 0;
826err_queues:
827 ath5k_txq_release(sc);
828err_bhal:
829 ath5k_hw_release_tx_queue(ah, sc->bhalq);
830err_desc:
831 ath5k_desc_free(sc, pdev);
832err:
833 return ret;
834}
835
836static void
837ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
838{
839 struct ath5k_softc *sc = hw->priv;
840
841 /*
842 * NB: the order of these is important:
843 * o call the 802.11 layer before detaching ath5k_hw to
844 * insure callbacks into the driver to delete global
845 * key cache entries can be handled
846 * o reclaim the tx queue data structures after calling
847 * the 802.11 layer as we'll get called back to reclaim
848 * node state and potentially want to use them
849 * o to cleanup the tx queues the hal is called, so detach
850 * it last
851 * XXX: ??? detach ath5k_hw ???
852 * Other than that, it's straightforward...
853 */
854 ieee80211_unregister_hw(hw);
855 ath5k_desc_free(sc, pdev);
856 ath5k_txq_release(sc);
857 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
3a078876 858 ath5k_unregister_leds(sc);
fa1c114f
JS		 859
860 /*
861 * NB: can't reclaim these until after ieee80211_ifdetach
862 * returns because we'll get called back to reclaim node
863 * state and potentially want to use them.
864 */
865}
866
867
868
869
870/********************\
871* Channel/mode setup *
872\********************/
873
874/*
875 * Convert IEEE channel number to MHz frequency.
876 */
877static inline short
878ath5k_ieee2mhz(short chan)
879{
880 if (chan <= 14 || chan >= 27)
881 return ieee80211chan2mhz(chan);
882 else
883 return 2212 + chan * 20;
884}
885
42639fcd
BC		 886/*
887 * Returns true for the channel numbers used without all_channels modparam.
888 */
889static bool ath5k_is_standard_channel(short chan)
890{
891 return ((chan <= 14) ||
892 /* UNII 1,2 */
893 ((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
894 /* midband */
895 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
896 /* UNII-3 */
897 ((chan & 3) == 1 && chan >= 149 && chan <= 165));
898}
899
fa1c114f
JS		 900static unsigned int
901ath5k_copy_channels(struct ath5k_hw *ah,
902 struct ieee80211_channel *channels,
903 unsigned int mode,
904 unsigned int max)
905{
d8ee398d 906 unsigned int i, count, size, chfreq, freq, ch;
fa1c114f
JS		 907
908 if (!test_bit(mode, ah->ah_modes))
909 return 0;
910
fa1c114f 911 switch (mode) {
d8ee398d
LR		 912 case AR5K_MODE_11A:
913 case AR5K_MODE_11A_TURBO:
fa1c114f 914 /* 1..220, but 2GHz frequencies are filtered by check_channel */
d8ee398d 915 size = 220 ;
fa1c114f
JS		 916 chfreq = CHANNEL_5GHZ;
917 break;
d8ee398d
LR		 918 case AR5K_MODE_11B:
919 case AR5K_MODE_11G:
920 case AR5K_MODE_11G_TURBO:
921 size = 26;
fa1c114f
JS		 922 chfreq = CHANNEL_2GHZ;
923 break;
924 default:
925 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
926 return 0;
927 }
928
929 for (i = 0, count = 0; i < size && max > 0; i++) {
d8ee398d
LR		 930 ch = i + 1 ;
931 freq = ath5k_ieee2mhz(ch);
fa1c114f 932
d8ee398d
LR		 933 /* Check if channel is supported by the chipset */
934 if (!ath5k_channel_ok(ah, freq, chfreq))
fa1c114f
JS		 935 continue;
936
42639fcd
BC		 937 if (!modparam_all_channels && !ath5k_is_standard_channel(ch))
938 continue;
939
d8ee398d
LR		 940 /* Write channel info and increment counter */
941 channels[count].center_freq = freq;
a3f4b914
LR		 942 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
943 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
400ec45a
LR		 944 switch (mode) {
945 case AR5K_MODE_11A:
946 case AR5K_MODE_11G:
947 channels[count].hw_value = chfreq | CHANNEL_OFDM;
948 break;
949 case AR5K_MODE_11A_TURBO:
950 case AR5K_MODE_11G_TURBO:
951 channels[count].hw_value = chfreq |
952 CHANNEL_OFDM | CHANNEL_TURBO;
953 break;
954 case AR5K_MODE_11B:
d8ee398d
LR		 955 channels[count].hw_value = CHANNEL_B;
956 }
fa1c114f 957
fa1c114f
JS		 958 count++;
959 max--;
960 }
961
962 return count;
963}
964
63266a65
BR		 965static void
966ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
967{
968 u8 i;
969
970 for (i = 0; i < AR5K_MAX_RATES; i++)
971 sc->rate_idx[b->band][i] = -1;
972
973 for (i = 0; i < b->n_bitrates; i++) {
974 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
975 if (b->bitrates[i].hw_value_short)
976 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
977 }
978}
979
d8ee398d 980static int
63266a65 981ath5k_setup_bands(struct ieee80211_hw *hw)
fa1c114f
JS		 982{
983 struct ath5k_softc *sc = hw->priv;
d8ee398d 984 struct ath5k_hw *ah = sc->ah;
63266a65
BR		 985 struct ieee80211_supported_band *sband;
986 int max_c, count_c = 0;
987 int i;
fa1c114f 988
d8ee398d 989 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
d8ee398d 990 max_c = ARRAY_SIZE(sc->channels);
d8ee398d
LR		 991
992 /* 2GHz band */
63266a65
BR		 993 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
994 sband->band = IEEE80211_BAND_2GHZ;
995 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
fa1c114f 996
63266a65
BR		 997 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
998 /* G mode */
999 memcpy(sband->bitrates, &ath5k_rates[0],
1000 sizeof(struct ieee80211_rate) * 12);
1001 sband->n_bitrates = 12;
fa1c114f 1002
d8ee398d 1003 sband->channels = sc->channels;
d8ee398d 1004 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
63266a65 1005 AR5K_MODE_11G, max_c);
fa1c114f 1006
63266a65 1007 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
d8ee398d 1008 count_c = sband->n_channels;
63266a65
BR		 1009 max_c -= count_c;
1010 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
1011 /* B mode */
1012 memcpy(sband->bitrates, &ath5k_rates[0],
1013 sizeof(struct ieee80211_rate) * 4);
1014 sband->n_bitrates = 4;
1015
1016 /* 5211 only supports B rates and uses 4bit rate codes
1017 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
1018 * fix them up here:
1019 */
1020 if (ah->ah_version == AR5K_AR5211) {
1021 for (i = 0; i < 4; i++) {
1022 sband->bitrates[i].hw_value =
1023 sband->bitrates[i].hw_value & 0xF;
1024 sband->bitrates[i].hw_value_short =
1025 sband->bitrates[i].hw_value_short & 0xF;
1026 }
1027 }
fa1c114f 1028
63266a65
BR		 1029 sband->channels = sc->channels;
1030 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1031 AR5K_MODE_11B, max_c);
d8ee398d 1032
63266a65
BR		 1033 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1034 count_c = sband->n_channels;
d8ee398d 1035 max_c -= count_c;
fa1c114f 1036 }
63266a65 1037 ath5k_setup_rate_idx(sc, sband);
fa1c114f 1038
63266a65 1039 /* 5GHz band, A mode */
400ec45a 1040 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
63266a65
BR		 1041 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
1042 sband->band = IEEE80211_BAND_5GHZ;
1043 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
fa1c114f 1044
63266a65
BR		 1045 memcpy(sband->bitrates, &ath5k_rates[4],
1046 sizeof(struct ieee80211_rate) * 8);
1047 sband->n_bitrates = 8;
fa1c114f 1048
63266a65 1049 sband->channels = &sc->channels[count_c];
d8ee398d
LR		 1050 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1051 AR5K_MODE_11A, max_c);
1052
d8ee398d
LR		 1053 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1054 }
63266a65 1055 ath5k_setup_rate_idx(sc, sband);
d8ee398d 1056
b446197c 1057 ath5k_debug_dump_bands(sc);
d8ee398d
LR		 1058
1059 return 0;
fa1c114f
JS		 1060}
1061
1062/*
1063 * Set/change channels. If the channel is really being changed,
1064 * it's done by reseting the chip. To accomplish this we must
1065 * first cleanup any pending DMA, then restart stuff after a la
1066 * ath5k_init.
be009370
BC		 1067 *
1068 * Called with sc->lock.
fa1c114f
JS		 1069 */
1070static int
1071ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1072{
d8ee398d
LR		 1073 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1074 sc->curchan->center_freq, chan->center_freq);
1075
1076 if (chan->center_freq != sc->curchan->center_freq ||
1077 chan->hw_value != sc->curchan->hw_value) {
1078
1079 sc->curchan = chan;
1080 sc->curband = &sc->sbands[chan->band];
fa1c114f 1081
fa1c114f
JS		 1082 /*
1083 * To switch channels clear any pending DMA operations;
1084 * wait long enough for the RX fifo to drain, reset the
1085 * hardware at the new frequency, and then re-enable
1086 * the relevant bits of the h/w.
1087 */
d7dc1003 1088 return ath5k_reset(sc, true, true);
fa1c114f
JS		 1089 }
1090
1091 return 0;
1092}
1093
1094static void
1095ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1096{
fa1c114f 1097 sc->curmode = mode;
d8ee398d 1098
400ec45a 1099 if (mode == AR5K_MODE_11A) {
d8ee398d
LR		 1100 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1101 } else {
1102 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1103 }
fa1c114f
JS		 1104}
1105
1106static void
1107ath5k_mode_setup(struct ath5k_softc *sc)
1108{
1109 struct ath5k_hw *ah = sc->ah;
1110 u32 rfilt;
1111
1112 /* configure rx filter */
1113 rfilt = sc->filter_flags;
1114 ath5k_hw_set_rx_filter(ah, rfilt);
1115
1116 if (ath5k_hw_hasbssidmask(ah))
1117 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1118
1119 /* configure operational mode */
1120 ath5k_hw_set_opmode(ah);
1121
1122 ath5k_hw_set_mcast_filter(ah, 0, 0);
1123 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1124}
1125
d8ee398d 1126static inline int
63266a65
BR		 1127ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1128{
b7266047
BC		 1129 int rix;
1130
1131 /* return base rate on errors */
1132 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
1133 "hw_rix out of bounds: %x\n", hw_rix))
1134 return 0;
1135
1136 rix = sc->rate_idx[sc->curband->band][hw_rix];
1137 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
1138 rix = 0;
1139
1140 return rix;
d8ee398d
LR		 1141}
1142
fa1c114f
JS		 1143/***************\
1144* Buffers setup *
1145\***************/
1146
b6ea0356
BC		 1147static
1148struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
1149{
1150 struct sk_buff *skb;
1151 unsigned int off;
1152
1153 /*
1154 * Allocate buffer with headroom_needed space for the
1155 * fake physical layer header at the start.
1156 */
1157 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1158
1159 if (!skb) {
1160 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1161 sc->rxbufsize + sc->cachelsz - 1);
1162 return NULL;
1163 }
1164 /*
1165 * Cache-line-align. This is important (for the
1166 * 5210 at least) as not doing so causes bogus data
1167 * in rx'd frames.
1168 */
1169 off = ((unsigned long)skb->data) % sc->cachelsz;
1170 if (off != 0)
1171 skb_reserve(skb, sc->cachelsz - off);
1172
1173 *skb_addr = pci_map_single(sc->pdev,
1174 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
1175 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
1176 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1177 dev_kfree_skb(skb);
1178 return NULL;
1179 }
1180 return skb;
1181}
1182
fa1c114f
JS		 1183static int
1184ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1185{
1186 struct ath5k_hw *ah = sc->ah;
1187 struct sk_buff *skb = bf->skb;
1188 struct ath5k_desc *ds;
1189
b6ea0356
BC		 1190 if (!skb) {
1191 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
1192 if (!skb)
fa1c114f 1193 return -ENOMEM;
fa1c114f 1194 bf->skb = skb;
fa1c114f
JS		 1195 }
1196
1197 /*
1198 * Setup descriptors. For receive we always terminate
1199 * the descriptor list with a self-linked entry so we'll
1200 * not get overrun under high load (as can happen with a
1201 * 5212 when ANI processing enables PHY error frames).
1202 *
1203 * To insure the last descriptor is self-linked we create
1204 * each descriptor as self-linked and add it to the end. As
1205 * each additional descriptor is added the previous self-linked
1206 * entry is ``fixed'' naturally. This should be safe even
1207 * if DMA is happening. When processing RX interrupts we
1208 * never remove/process the last, self-linked, entry on the
1209 * descriptor list. This insures the hardware always has
1210 * someplace to write a new frame.
1211 */
1212 ds = bf->desc;
1213 ds->ds_link = bf->daddr; /* link to self */
1214 ds->ds_data = bf->skbaddr;
c6e387a2 1215 ah->ah_setup_rx_desc(ah, ds,
fa1c114f
JS		 1216 skb_tailroom(skb), /* buffer size */
1217 0);
1218
1219 if (sc->rxlink != NULL)
1220 *sc->rxlink = bf->daddr;
1221 sc->rxlink = &ds->ds_link;
1222 return 0;
1223}
1224
1225static int
e039fa4a 1226ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 1227{
1228 struct ath5k_hw *ah = sc->ah;
1229 struct ath5k_txq *txq = sc->txq;
1230 struct ath5k_desc *ds = bf->desc;
1231 struct sk_buff *skb = bf->skb;
a888d52d 1232 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f 1233 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
2f7fe870
FF		 1234 struct ieee80211_rate *rate;
1235 unsigned int mrr_rate[3], mrr_tries[3];
1236 int i, ret;
8902ff4e 1237 u16 hw_rate;
07c1e852
BC		 1238 u16 cts_rate = 0;
1239 u16 duration = 0;
8902ff4e 1240 u8 rc_flags;
fa1c114f
JS		 1241
1242 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
e039fa4a 1243
fa1c114f
JS		 1244 /* XXX endianness */
1245 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1246 PCI_DMA_TODEVICE);
1247
8902ff4e
BC		 1248 rate = ieee80211_get_tx_rate(sc->hw, info);
1249
e039fa4a 1250 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
fa1c114f
JS		 1251 flags |= AR5K_TXDESC_NOACK;
1252
8902ff4e
BC		 1253 rc_flags = info->control.rates[0].flags;
1254 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
1255 rate->hw_value_short : rate->hw_value;
1256
281c56dd 1257 pktlen = skb->len;
fa1c114f 1258
8f655dde
NK		 1259 /* FIXME: If we are in g mode and rate is a CCK rate
1260 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1261 * from tx power (value is in dB units already) */
362695e1
BC		 1262 if (info->control.hw_key) {
1263 keyidx = info->control.hw_key->hw_key_idx;
1264 pktlen += info->control.hw_key->icv_len;
1265 }
07c1e852
BC		 1266 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1267 flags |= AR5K_TXDESC_RTSENA;
1268 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1269 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
1270 sc->vif, pktlen, info));
1271 }
1272 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1273 flags |= AR5K_TXDESC_CTSENA;
1274 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1275 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
1276 sc->vif, pktlen, info));
1277 }
fa1c114f
JS		 1278 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1279 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
2e92e6f2 1280 (sc->power_level * 2),
8902ff4e 1281 hw_rate,
07c1e852
BC		 1282 info->control.rates[0].count, keyidx, 0, flags,
1283 cts_rate, duration);
fa1c114f
JS		 1284 if (ret)
1285 goto err_unmap;
1286
2f7fe870
FF		 1287 memset(mrr_rate, 0, sizeof(mrr_rate));
1288 memset(mrr_tries, 0, sizeof(mrr_tries));
1289 for (i = 0; i < 3; i++) {
1290 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1291 if (!rate)
1292 break;
1293
1294 mrr_rate[i] = rate->hw_value;
e6a9854b 1295 mrr_tries[i] = info->control.rates[i + 1].count;
2f7fe870
FF		 1296 }
1297
1298 ah->ah_setup_mrr_tx_desc(ah, ds,
1299 mrr_rate[0], mrr_tries[0],
1300 mrr_rate[1], mrr_tries[1],
1301 mrr_rate[2], mrr_tries[2]);
1302
fa1c114f
JS		 1303 ds->ds_link = 0;
1304 ds->ds_data = bf->skbaddr;
1305
1306 spin_lock_bh(&txq->lock);
1307 list_add_tail(&bf->list, &txq->q);
57ffc589 1308 sc->tx_stats[txq->qnum].len++;
fa1c114f 1309 if (txq->link == NULL) /* is this first packet? */
c6e387a2 1310 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
fa1c114f
JS		 1311 else /* no, so only link it */
1312 *txq->link = bf->daddr;
1313
1314 txq->link = &ds->ds_link;
c6e387a2 1315 ath5k_hw_start_tx_dma(ah, txq->qnum);
274c7c36 1316 mmiowb();
fa1c114f
JS		 1317 spin_unlock_bh(&txq->lock);
1318
1319 return 0;
1320err_unmap:
1321 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1322 return ret;
1323}
1324
1325/*******************\
1326* Descriptors setup *
1327\*******************/
1328
1329static int
1330ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1331{
1332 struct ath5k_desc *ds;
1333 struct ath5k_buf *bf;
1334 dma_addr_t da;
1335 unsigned int i;
1336 int ret;
1337
1338 /* allocate descriptors */
1339 sc->desc_len = sizeof(struct ath5k_desc) *
1340 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1341 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1342 if (sc->desc == NULL) {
1343 ATH5K_ERR(sc, "can't allocate descriptors\n");
1344 ret = -ENOMEM;
1345 goto err;
1346 }
1347 ds = sc->desc;
1348 da = sc->desc_daddr;
1349 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1350 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1351
1352 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1353 sizeof(struct ath5k_buf), GFP_KERNEL);
1354 if (bf == NULL) {
1355 ATH5K_ERR(sc, "can't allocate bufptr\n");
1356 ret = -ENOMEM;
1357 goto err_free;
1358 }
1359 sc->bufptr = bf;
1360
1361 INIT_LIST_HEAD(&sc->rxbuf);
1362 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1363 bf->desc = ds;
1364 bf->daddr = da;
1365 list_add_tail(&bf->list, &sc->rxbuf);
1366 }
1367
1368 INIT_LIST_HEAD(&sc->txbuf);
1369 sc->txbuf_len = ATH_TXBUF;
1370 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1371 da += sizeof(*ds)) {
1372 bf->desc = ds;
1373 bf->daddr = da;
1374 list_add_tail(&bf->list, &sc->txbuf);
1375 }
1376
1377 /* beacon buffer */
1378 bf->desc = ds;
1379 bf->daddr = da;
1380 sc->bbuf = bf;
1381
1382 return 0;
1383err_free:
1384 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1385err:
1386 sc->desc = NULL;
1387 return ret;
1388}
1389
1390static void
1391ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1392{
1393 struct ath5k_buf *bf;
1394
1395 ath5k_txbuf_free(sc, sc->bbuf);
1396 list_for_each_entry(bf, &sc->txbuf, list)
1397 ath5k_txbuf_free(sc, bf);
1398 list_for_each_entry(bf, &sc->rxbuf, list)
a6c8d375 1399 ath5k_rxbuf_free(sc, bf);
fa1c114f
JS		 1400
1401 /* Free memory associated with all descriptors */
1402 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1403
1404 kfree(sc->bufptr);
1405 sc->bufptr = NULL;
1406}
1407
1408
1409
1410
1411
1412/**************\
1413* Queues setup *
1414\**************/
1415
1416static struct ath5k_txq *
1417ath5k_txq_setup(struct ath5k_softc *sc,
1418 int qtype, int subtype)
1419{
1420 struct ath5k_hw *ah = sc->ah;
1421 struct ath5k_txq *txq;
1422 struct ath5k_txq_info qi = {
1423 .tqi_subtype = subtype,
1424 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1425 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1426 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1427 };
1428 int qnum;
1429
1430 /*
1431 * Enable interrupts only for EOL and DESC conditions.
1432 * We mark tx descriptors to receive a DESC interrupt
1433 * when a tx queue gets deep; otherwise waiting for the
1434 * EOL to reap descriptors. Note that this is done to
1435 * reduce interrupt load and this only defers reaping
1436 * descriptors, never transmitting frames. Aside from
1437 * reducing interrupts this also permits more concurrency.
1438 * The only potential downside is if the tx queue backs
1439 * up in which case the top half of the kernel may backup
1440 * due to a lack of tx descriptors.
1441 */
1442 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1443 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1444 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1445 if (qnum < 0) {
1446 /*
1447 * NB: don't print a message, this happens
1448 * normally on parts with too few tx queues
1449 */
1450 return ERR_PTR(qnum);
1451 }
1452 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1453 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1454 qnum, ARRAY_SIZE(sc->txqs));
1455 ath5k_hw_release_tx_queue(ah, qnum);
1456 return ERR_PTR(-EINVAL);
1457 }
1458 txq = &sc->txqs[qnum];
1459 if (!txq->setup) {
1460 txq->qnum = qnum;
1461 txq->link = NULL;
1462 INIT_LIST_HEAD(&txq->q);
1463 spin_lock_init(&txq->lock);
1464 txq->setup = true;
1465 }
1466 return &sc->txqs[qnum];
1467}
1468
1469static int
1470ath5k_beaconq_setup(struct ath5k_hw *ah)
1471{
1472 struct ath5k_txq_info qi = {
1473 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1474 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1475 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1476 /* NB: for dynamic turbo, don't enable any other interrupts */
1477 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1478 };
1479
1480 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1481}
1482
1483static int
1484ath5k_beaconq_config(struct ath5k_softc *sc)
1485{
1486 struct ath5k_hw *ah = sc->ah;
1487 struct ath5k_txq_info qi;
1488 int ret;
1489
1490 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1491 if (ret)
1492 return ret;
05c914fe
JB		 1493 if (sc->opmode == NL80211_IFTYPE_AP ||
1494 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
fa1c114f
JS		 1495 /*
1496 * Always burst out beacon and CAB traffic
1497 * (aifs = cwmin = cwmax = 0)
1498 */
1499 qi.tqi_aifs = 0;
1500 qi.tqi_cw_min = 0;
1501 qi.tqi_cw_max = 0;
05c914fe 1502 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
6d91e1d8
BR		 1503 /*
1504 * Adhoc mode; backoff between 0 and (2 * cw_min).
1505 */
1506 qi.tqi_aifs = 0;
1507 qi.tqi_cw_min = 0;
1508 qi.tqi_cw_max = 2 * ah->ah_cw_min;
fa1c114f
JS		 1509 }
1510
6d91e1d8
BR		 1511 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1512 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1513 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1514
c6e387a2 1515 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
fa1c114f
JS		 1516 if (ret) {
1517 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1518 "hardware queue!\n", __func__);
1519 return ret;
1520 }
1521
1522 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1523}
1524
1525static void
1526ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1527{
1528 struct ath5k_buf *bf, *bf0;
1529
1530 /*
1531 * NB: this assumes output has been stopped and
1532 * we do not need to block ath5k_tx_tasklet
1533 */
1534 spin_lock_bh(&txq->lock);
1535 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
b47f407b 1536 ath5k_debug_printtxbuf(sc, bf);
fa1c114f
JS		 1537
1538 ath5k_txbuf_free(sc, bf);
1539
1540 spin_lock_bh(&sc->txbuflock);
57ffc589 1541 sc->tx_stats[txq->qnum].len--;
fa1c114f
JS		 1542 list_move_tail(&bf->list, &sc->txbuf);
1543 sc->txbuf_len++;
1544 spin_unlock_bh(&sc->txbuflock);
1545 }
1546 txq->link = NULL;
1547 spin_unlock_bh(&txq->lock);
1548}
1549
1550/*
1551 * Drain the transmit queues and reclaim resources.
1552 */
1553static void
1554ath5k_txq_cleanup(struct ath5k_softc *sc)
1555{
1556 struct ath5k_hw *ah = sc->ah;
1557 unsigned int i;
1558
1559 /* XXX return value */
1560 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1561 /* don't touch the hardware if marked invalid */
1562 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1563 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
c6e387a2 1564 ath5k_hw_get_txdp(ah, sc->bhalq));
fa1c114f
JS		 1565 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1566 if (sc->txqs[i].setup) {
1567 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1568 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1569 "link %p\n",
1570 sc->txqs[i].qnum,
c6e387a2 1571 ath5k_hw_get_txdp(ah,
fa1c114f
JS		 1572 sc->txqs[i].qnum),
1573 sc->txqs[i].link);
1574 }
1575 }
36d6825b 1576 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
fa1c114f
JS		 1577
1578 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1579 if (sc->txqs[i].setup)
1580 ath5k_txq_drainq(sc, &sc->txqs[i]);
1581}
1582
1583static void
1584ath5k_txq_release(struct ath5k_softc *sc)
1585{
1586 struct ath5k_txq *txq = sc->txqs;
1587 unsigned int i;
1588
1589 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1590 if (txq->setup) {
1591 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1592 txq->setup = false;
1593 }
1594}
1595
1596
1597
1598
1599/*************\
1600* RX Handling *
1601\*************/
1602
1603/*
1604 * Enable the receive h/w following a reset.
1605 */
1606static int
1607ath5k_rx_start(struct ath5k_softc *sc)
1608{
1609 struct ath5k_hw *ah = sc->ah;
1610 struct ath5k_buf *bf;
1611 int ret;
1612
1613 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1614
1615 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1616 sc->cachelsz, sc->rxbufsize);
1617
fa1c114f 1618 spin_lock_bh(&sc->rxbuflock);
26925042 1619 sc->rxlink = NULL;
fa1c114f
JS		 1620 list_for_each_entry(bf, &sc->rxbuf, list) {
1621 ret = ath5k_rxbuf_setup(sc, bf);
1622 if (ret != 0) {
1623 spin_unlock_bh(&sc->rxbuflock);
1624 goto err;
1625 }
1626 }
1627 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
26925042 1628 ath5k_hw_set_rxdp(ah, bf->daddr);
fa1c114f
JS		 1629 spin_unlock_bh(&sc->rxbuflock);
1630
c6e387a2 1631 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
fa1c114f
JS		 1632 ath5k_mode_setup(sc); /* set filters, etc. */
1633 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1634
1635 return 0;
1636err:
1637 return ret;
1638}
1639
1640/*
1641 * Disable the receive h/w in preparation for a reset.
1642 */
1643static void
1644ath5k_rx_stop(struct ath5k_softc *sc)
1645{
1646 struct ath5k_hw *ah = sc->ah;
1647
c6e387a2 1648 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
fa1c114f
JS		 1649 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1650 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
fa1c114f
JS		 1651
1652 ath5k_debug_printrxbuffs(sc, ah);
1653
1654 sc->rxlink = NULL; /* just in case */
1655}
1656
1657static unsigned int
1658ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
b47f407b 1659 struct sk_buff *skb, struct ath5k_rx_status *rs)
fa1c114f
JS		 1660{
1661 struct ieee80211_hdr *hdr = (void *)skb->data;
798ee985 1662 unsigned int keyix, hlen;
fa1c114f 1663
b47f407b
BR		 1664 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1665 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
fa1c114f
JS		 1666 return RX_FLAG_DECRYPTED;
1667
1668 /* Apparently when a default key is used to decrypt the packet
1669 the hw does not set the index used to decrypt. In such cases
1670 get the index from the packet. */
798ee985 1671 hlen = ieee80211_hdrlen(hdr->frame_control);
24b56e70
HH		 1672 if (ieee80211_has_protected(hdr->frame_control) &&
1673 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1674 skb->len >= hlen + 4) {
fa1c114f
JS		 1675 keyix = skb->data[hlen + 3] >> 6;
1676
1677 if (test_bit(keyix, sc->keymap))
1678 return RX_FLAG_DECRYPTED;
1679 }
1680
1681 return 0;
1682}
1683
036cd1ec
BR		 1684
1685static void
6ba81c2c
BR		 1686ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1687 struct ieee80211_rx_status *rxs)
036cd1ec 1688{
6ba81c2c 1689 u64 tsf, bc_tstamp;
036cd1ec
BR		 1690 u32 hw_tu;
1691 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1692
24b56e70 1693 if (ieee80211_is_beacon(mgmt->frame_control) &&
38c07b43 1694 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
036cd1ec
BR		 1695 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1696 /*
6ba81c2c
BR		 1697 * Received an IBSS beacon with the same BSSID. Hardware *must*
1698 * have updated the local TSF. We have to work around various
1699 * hardware bugs, though...
036cd1ec 1700 */
6ba81c2c
BR		 1701 tsf = ath5k_hw_get_tsf64(sc->ah);
1702 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1703 hw_tu = TSF_TO_TU(tsf);
1704
1705 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1706 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
06501d29
JL		 1707 (unsigned long long)bc_tstamp,
1708 (unsigned long long)rxs->mactime,
1709 (unsigned long long)(rxs->mactime - bc_tstamp),
1710 (unsigned long long)tsf);
6ba81c2c
BR		 1711
1712 /*
1713 * Sometimes the HW will give us a wrong tstamp in the rx
1714 * status, causing the timestamp extension to go wrong.
1715 * (This seems to happen especially with beacon frames bigger
1716 * than 78 byte (incl. FCS))
1717 * But we know that the receive timestamp must be later than the
1718 * timestamp of the beacon since HW must have synced to that.
1719 *
1720 * NOTE: here we assume mactime to be after the frame was
1721 * received, not like mac80211 which defines it at the start.
1722 */
1723 if (bc_tstamp > rxs->mactime) {
036cd1ec 1724 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
6ba81c2c 1725 "fixing mactime from %llx to %llx\n",
06501d29
JL		 1726 (unsigned long long)rxs->mactime,
1727 (unsigned long long)tsf);
6ba81c2c 1728 rxs->mactime = tsf;
036cd1ec 1729 }
6ba81c2c
BR		 1730
1731 /*
1732 * Local TSF might have moved higher than our beacon timers,
1733 * in that case we have to update them to continue sending
1734 * beacons. This also takes care of synchronizing beacon sending
1735 * times with other stations.
1736 */
1737 if (hw_tu >= sc->nexttbtt)
1738 ath5k_beacon_update_timers(sc, bc_tstamp);
036cd1ec
BR		 1739 }
1740}
1741
fa1c114f
JS		 1742static void
1743ath5k_tasklet_rx(unsigned long data)
1744{
1745 struct ieee80211_rx_status rxs = {};
b47f407b 1746 struct ath5k_rx_status rs = {};
b6ea0356
BC		 1747 struct sk_buff *skb, *next_skb;
1748 dma_addr_t next_skb_addr;
fa1c114f 1749 struct ath5k_softc *sc = (void *)data;
c57ca815 1750 struct ath5k_buf *bf;
fa1c114f 1751 struct ath5k_desc *ds;
fa1c114f
JS		 1752 int ret;
1753 int hdrlen;
0fe45b1d 1754 int padsize;
fa1c114f
JS		 1755
1756 spin_lock(&sc->rxbuflock);
3a0f2c87
JS		 1757 if (list_empty(&sc->rxbuf)) {
1758 ATH5K_WARN(sc, "empty rx buf pool\n");
1759 goto unlock;
1760 }
fa1c114f 1761 do {
d6894b5b
BC		 1762 rxs.flag = 0;
1763
fa1c114f
JS		 1764 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1765 BUG_ON(bf->skb == NULL);
1766 skb = bf->skb;
1767 ds = bf->desc;
1768
c57ca815
BC		 1769 /* bail if HW is still using self-linked descriptor */
1770 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
1771 break;
fa1c114f 1772
b47f407b 1773 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
fa1c114f
JS		 1774 if (unlikely(ret == -EINPROGRESS))
1775 break;
1776 else if (unlikely(ret)) {
1777 ATH5K_ERR(sc, "error in processing rx descriptor\n");
65872e6b 1778 spin_unlock(&sc->rxbuflock);
fa1c114f
JS		 1779 return;
1780 }
1781
b47f407b 1782 if (unlikely(rs.rs_more)) {
fa1c114f
JS		 1783 ATH5K_WARN(sc, "unsupported jumbo\n");
1784 goto next;
1785 }
1786
b47f407b
BR		 1787 if (unlikely(rs.rs_status)) {
1788 if (rs.rs_status & AR5K_RXERR_PHY)
fa1c114f 1789 goto next;
b47f407b 1790 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
fa1c114f
JS		 1791 /*
1792 * Decrypt error. If the error occurred
1793 * because there was no hardware key, then
1794 * let the frame through so the upper layers
1795 * can process it. This is necessary for 5210
1796 * parts which have no way to setup a ``clear''
1797 * key cache entry.
1798 *
1799 * XXX do key cache faulting
1800 */
b47f407b
BR		 1801 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1802 !(rs.rs_status & AR5K_RXERR_CRC))
fa1c114f
JS		 1803 goto accept;
1804 }
b47f407b 1805 if (rs.rs_status & AR5K_RXERR_MIC) {
fa1c114f
JS		 1806 rxs.flag |= RX_FLAG_MMIC_ERROR;
1807 goto accept;
1808 }
1809
1810 /* let crypto-error packets fall through in MNTR */
b47f407b
BR		 1811 if ((rs.rs_status &
1812 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
05c914fe 1813 sc->opmode != NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 1814 goto next;
1815 }
1816accept:
b6ea0356
BC		 1817 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
1818
1819 /*
1820 * If we can't replace bf->skb with a new skb under memory
1821 * pressure, just skip this packet
1822 */
1823 if (!next_skb)
1824 goto next;
1825
fa1c114f
JS		 1826 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1827 PCI_DMA_FROMDEVICE);
b47f407b 1828 skb_put(skb, rs.rs_datalen);
fa1c114f 1829
0fe45b1d
BP		 1830 /* The MAC header is padded to have 32-bit boundary if the
1831 * packet payload is non-zero. The general calculation for
1832 * padsize would take into account odd header lengths:
1833 * padsize = (4 - hdrlen % 4) % 4; However, since only
1834 * even-length headers are used, padding can only be 0 or 2
1835 * bytes and we can optimize this a bit. In addition, we must
1836 * not try to remove padding from short control frames that do
1837 * not have payload. */
fa1c114f 1838 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
fd6effca
BC		 1839 padsize = ath5k_pad_size(hdrlen);
1840 if (padsize) {
0fe45b1d
BP		 1841 memmove(skb->data + padsize, skb->data, hdrlen);
1842 skb_pull(skb, padsize);
fa1c114f
JS		 1843 }
1844
c0e1899b
BR		 1845 /*
1846 * always extend the mac timestamp, since this information is
1847 * also needed for proper IBSS merging.
1848 *
1849 * XXX: it might be too late to do it here, since rs_tstamp is
1850 * 15bit only. that means TSF extension has to be done within
1851 * 32768usec (about 32ms). it might be necessary to move this to
1852 * the interrupt handler, like it is done in madwifi.
e14296ca
BR		 1853 *
1854 * Unfortunately we don't know when the hardware takes the rx
1855 * timestamp (beginning of phy frame, data frame, end of rx?).
1856 * The only thing we know is that it is hardware specific...
1857 * On AR5213 it seems the rx timestamp is at the end of the
1858 * frame, but i'm not sure.
1859 *
1860 * NOTE: mac80211 defines mactime at the beginning of the first
1861 * data symbol. Since we don't have any time references it's
1862 * impossible to comply to that. This affects IBSS merge only
1863 * right now, so it's not too bad...
c0e1899b 1864 */
b47f407b 1865 rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
c0e1899b
BR		 1866 rxs.flag |= RX_FLAG_TSFT;
1867
d8ee398d
LR		 1868 rxs.freq = sc->curchan->center_freq;
1869 rxs.band = sc->curband->band;
fa1c114f 1870
fa1c114f 1871 rxs.noise = sc->ah->ah_noise_floor;
566bfe5a 1872 rxs.signal = rxs.noise + rs.rs_rssi;
6e0e0bf8
LR		 1873
1874 /* An rssi of 35 indicates you should be able use
1875 * 54 Mbps reliably. A more elaborate scheme can be used
1876 * here but it requires a map of SNR/throughput for each
1877 * possible mode used */
1878 rxs.qual = rs.rs_rssi * 100 / 35;
1879
1880 /* rssi can be more than 35 though, anything above that
1881 * should be considered at 100% */
1882 if (rxs.qual > 100)
1883 rxs.qual = 100;
fa1c114f 1884
b47f407b
BR		 1885 rxs.antenna = rs.rs_antenna;
1886 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1887 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
fa1c114f 1888
06303352
BR		 1889 if (rxs.rate_idx >= 0 && rs.rs_rate ==
1890 sc->curband->bitrates[rxs.rate_idx].hw_value_short)
63266a65 1891 rxs.flag |= RX_FLAG_SHORTPRE;
06303352 1892
fa1c114f
JS		 1893 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1894
036cd1ec 1895 /* check beacons in IBSS mode */
05c914fe 1896 if (sc->opmode == NL80211_IFTYPE_ADHOC)
6ba81c2c 1897 ath5k_check_ibss_tsf(sc, skb, &rxs);
036cd1ec 1898
fa1c114f 1899 __ieee80211_rx(sc->hw, skb, &rxs);
b6ea0356
BC		 1900
1901 bf->skb = next_skb;
1902 bf->skbaddr = next_skb_addr;
fa1c114f
JS		 1903next:
1904 list_move_tail(&bf->list, &sc->rxbuf);
1905 } while (ath5k_rxbuf_setup(sc, bf) == 0);
3a0f2c87 1906unlock:
fa1c114f
JS		 1907 spin_unlock(&sc->rxbuflock);
1908}
1909
1910
1911
1912
1913/*************\
1914* TX Handling *
1915\*************/
1916
1917static void
1918ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1919{
b47f407b 1920 struct ath5k_tx_status ts = {};
fa1c114f
JS		 1921 struct ath5k_buf *bf, *bf0;
1922 struct ath5k_desc *ds;
1923 struct sk_buff *skb;
e039fa4a 1924 struct ieee80211_tx_info *info;
2f7fe870 1925 int i, ret;
fa1c114f
JS		 1926
1927 spin_lock(&txq->lock);
1928 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1929 ds = bf->desc;
1930
b47f407b 1931 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
fa1c114f
JS		 1932 if (unlikely(ret == -EINPROGRESS))
1933 break;
1934 else if (unlikely(ret)) {
1935 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1936 ret, txq->qnum);
1937 break;
1938 }
1939
1940 skb = bf->skb;
a888d52d 1941 info = IEEE80211_SKB_CB(skb);
fa1c114f 1942 bf->skb = NULL;
e039fa4a 1943
fa1c114f
JS		 1944 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1945 PCI_DMA_TODEVICE);
1946
e6a9854b 1947 ieee80211_tx_info_clear_status(info);
2f7fe870 1948 for (i = 0; i < 4; i++) {
e6a9854b
JB		 1949 struct ieee80211_tx_rate *r =
1950 &info->status.rates[i];
2f7fe870
FF		 1951
1952 if (ts.ts_rate[i]) {
e6a9854b
JB		 1953 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
1954 r->count = ts.ts_retry[i];
2f7fe870 1955 } else {
e6a9854b
JB		 1956 r->idx = -1;
1957 r->count = 0;
2f7fe870
FF		 1958 }
1959 }
1960
e6a9854b
JB		 1961 /* count the successful attempt as well */
1962 info->status.rates[ts.ts_final_idx].count++;
1963
b47f407b 1964 if (unlikely(ts.ts_status)) {
fa1c114f 1965 sc->ll_stats.dot11ACKFailureCount++;
e6a9854b 1966 if (ts.ts_status & AR5K_TXERR_FILT)
e039fa4a 1967 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
fa1c114f 1968 } else {
e039fa4a
JB		 1969 info->flags |= IEEE80211_TX_STAT_ACK;
1970 info->status.ack_signal = ts.ts_rssi;
fa1c114f
JS		 1971 }
1972
e039fa4a 1973 ieee80211_tx_status(sc->hw, skb);
57ffc589 1974 sc->tx_stats[txq->qnum].count++;
fa1c114f
JS		 1975
1976 spin_lock(&sc->txbuflock);
57ffc589 1977 sc->tx_stats[txq->qnum].len--;
fa1c114f
JS		 1978 list_move_tail(&bf->list, &sc->txbuf);
1979 sc->txbuf_len++;
1980 spin_unlock(&sc->txbuflock);
1981 }
1982 if (likely(list_empty(&txq->q)))
1983 txq->link = NULL;
1984 spin_unlock(&txq->lock);
1985 if (sc->txbuf_len > ATH_TXBUF / 5)
1986 ieee80211_wake_queues(sc->hw);
1987}
1988
1989static void
1990ath5k_tasklet_tx(unsigned long data)
1991{
1992 struct ath5k_softc *sc = (void *)data;
1993
1994 ath5k_tx_processq(sc, sc->txq);
fa1c114f
JS		 1995}
1996
1997
fa1c114f
JS		 1998/*****************\
1999* Beacon handling *
2000\*****************/
2001
2002/*
2003 * Setup the beacon frame for transmit.
2004 */
2005static int
e039fa4a 2006ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
fa1c114f
JS		 2007{
2008 struct sk_buff *skb = bf->skb;
a888d52d 2009 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
fa1c114f
JS		 2010 struct ath5k_hw *ah = sc->ah;
2011 struct ath5k_desc *ds;
2012 int ret, antenna = 0;
2013 u32 flags;
2014
2015 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
2016 PCI_DMA_TODEVICE);
2017 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
2018 "skbaddr %llx\n", skb, skb->data, skb->len,
2019 (unsigned long long)bf->skbaddr);
8d8bb39b 2020 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
fa1c114f
JS		 2021 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
2022 return -EIO;
2023 }
2024
2025 ds = bf->desc;
2026
2027 flags = AR5K_TXDESC_NOACK;
05c914fe 2028 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
fa1c114f
JS		 2029 ds->ds_link = bf->daddr; /* self-linked */
2030 flags |= AR5K_TXDESC_VEOL;
2031 /*
2032 * Let hardware handle antenna switching if txantenna is not set
2033 */
2034 } else {
2035 ds->ds_link = 0;
2036 /*
2037 * Switch antenna every 4 beacons if txantenna is not set
2038 * XXX assumes two antennas
2039 */
2040 if (antenna == 0)
2041 antenna = sc->bsent & 4 ? 2 : 1;
2042 }
2043
8f655dde
NK		 2044 /* FIXME: If we are in g mode and rate is a CCK rate
2045 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
2046 * from tx power (value is in dB units already) */
fa1c114f 2047 ds->ds_data = bf->skbaddr;
281c56dd 2048 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
fa1c114f 2049 ieee80211_get_hdrlen_from_skb(skb),
400ec45a 2050 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
e039fa4a 2051 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2e92e6f2 2052 1, AR5K_TXKEYIX_INVALID,
400ec45a 2053 antenna, flags, 0, 0);
fa1c114f
JS		 2054 if (ret)
2055 goto err_unmap;
2056
2057 return 0;
2058err_unmap:
2059 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
2060 return ret;
2061}
2062
2063/*
2064 * Transmit a beacon frame at SWBA. Dynamic updates to the
2065 * frame contents are done as needed and the slot time is
2066 * also adjusted based on current state.
2067 *
acf3c1a5
BC		 2068 * This is called from software irq context (beacontq or restq
2069 * tasklets) or user context from ath5k_beacon_config.
fa1c114f
JS		 2070 */
2071static void
2072ath5k_beacon_send(struct ath5k_softc *sc)
2073{
2074 struct ath5k_buf *bf = sc->bbuf;
2075 struct ath5k_hw *ah = sc->ah;
2076
be9b7259 2077 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
fa1c114f 2078
05c914fe
JB		 2079 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
2080 sc->opmode == NL80211_IFTYPE_MONITOR)) {
fa1c114f
JS		 2081 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2082 return;
2083 }
2084 /*
2085 * Check if the previous beacon has gone out. If
2086 * not don't don't try to post another, skip this
2087 * period and wait for the next. Missed beacons
2088 * indicate a problem and should not occur. If we
2089 * miss too many consecutive beacons reset the device.
2090 */
2091 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2092 sc->bmisscount++;
be9b7259 2093 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f 2094 "missed %u consecutive beacons\n", sc->bmisscount);
428cbd4f 2095 if (sc->bmisscount > 10) { /* NB: 10 is a guess */
be9b7259 2096 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2097 "stuck beacon time (%u missed)\n",
2098 sc->bmisscount);
2099 tasklet_schedule(&sc->restq);
2100 }
2101 return;
2102 }
2103 if (unlikely(sc->bmisscount != 0)) {
be9b7259 2104 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
fa1c114f
JS		 2105 "resume beacon xmit after %u misses\n",
2106 sc->bmisscount);
2107 sc->bmisscount = 0;
2108 }
2109
2110 /*
2111 * Stop any current dma and put the new frame on the queue.
2112 * This should never fail since we check above that no frames
2113 * are still pending on the queue.
2114 */
2115 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
428cbd4f 2116 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
fa1c114f
JS		 2117 /* NB: hw still stops DMA, so proceed */
2118 }
fa1c114f 2119
428cbd4f
NK		 2120 /* Note: Beacon buffer is updated on beacon_update when mac80211
2121 * calls config_interface */
c6e387a2
NK		 2122 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2123 ath5k_hw_start_tx_dma(ah, sc->bhalq);
be9b7259 2124 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
fa1c114f
JS		 2125 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2126
2127 sc->bsent++;
2128}
2129
2130
9804b98d
BR		 2131/**
2132 * ath5k_beacon_update_timers - update beacon timers
2133 *
2134 * @sc: struct ath5k_softc pointer we are operating on
2135 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2136 * beacon timer update based on the current HW TSF.
2137 *
2138 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2139 * of a received beacon or the current local hardware TSF and write it to the
2140 * beacon timer registers.
2141 *
2142 * This is called in a variety of situations, e.g. when a beacon is received,
6ba81c2c 2143 * when a TSF update has been detected, but also when an new IBSS is created or
9804b98d
BR		 2144 * when we otherwise know we have to update the timers, but we keep it in this
2145 * function to have it all together in one place.
2146 */
fa1c114f 2147static void
9804b98d 2148ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
fa1c114f
JS		 2149{
2150 struct ath5k_hw *ah = sc->ah;
9804b98d
BR		 2151 u32 nexttbtt, intval, hw_tu, bc_tu;
2152 u64 hw_tsf;
fa1c114f
JS		 2153
2154 intval = sc->bintval & AR5K_BEACON_PERIOD;
2155 if (WARN_ON(!intval))
2156 return;
2157
9804b98d
BR		 2158 /* beacon TSF converted to TU */
2159 bc_tu = TSF_TO_TU(bc_tsf);
fa1c114f 2160
9804b98d
BR		 2161 /* current TSF converted to TU */
2162 hw_tsf = ath5k_hw_get_tsf64(ah);
2163 hw_tu = TSF_TO_TU(hw_tsf);
fa1c114f 2164
9804b98d
BR		 2165#define FUDGE 3
2166 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2167 if (bc_tsf == -1) {
2168 /*
2169 * no beacons received, called internally.
2170 * just need to refresh timers based on HW TSF.
2171 */
2172 nexttbtt = roundup(hw_tu + FUDGE, intval);
2173 } else if (bc_tsf == 0) {
2174 /*
2175 * no beacon received, probably called by ath5k_reset_tsf().
2176 * reset TSF to start with 0.
2177 */
2178 nexttbtt = intval;
2179 intval |= AR5K_BEACON_RESET_TSF;
2180 } else if (bc_tsf > hw_tsf) {
2181 /*
2182 * beacon received, SW merge happend but HW TSF not yet updated.
2183 * not possible to reconfigure timers yet, but next time we
2184 * receive a beacon with the same BSSID, the hardware will
2185 * automatically update the TSF and then we need to reconfigure
2186 * the timers.
2187 */
2188 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2189 "need to wait for HW TSF sync\n");
2190 return;
2191 } else {
2192 /*
2193 * most important case for beacon synchronization between STA.
2194 *
2195 * beacon received and HW TSF has been already updated by HW.
2196 * update next TBTT based on the TSF of the beacon, but make
2197 * sure it is ahead of our local TSF timer.
2198 */
2199 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2200 }
2201#undef FUDGE
fa1c114f 2202
036cd1ec
BR		 2203 sc->nexttbtt = nexttbtt;
2204
fa1c114f 2205 intval |= AR5K_BEACON_ENA;
fa1c114f 2206 ath5k_hw_init_beacon(ah, nexttbtt, intval);
9804b98d
BR		 2207
2208 /*
2209 * debugging output last in order to preserve the time critical aspect
2210 * of this function
2211 */
2212 if (bc_tsf == -1)
2213 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2214 "reconfigured timers based on HW TSF\n");
2215 else if (bc_tsf == 0)
2216 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2217 "reset HW TSF and timers\n");
2218 else
2219 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2220 "updated timers based on beacon TSF\n");
2221
2222 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
04f93a87
DM		 2223 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2224 (unsigned long long) bc_tsf,
2225 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
9804b98d
BR		 2226 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2227 intval & AR5K_BEACON_PERIOD,
2228 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2229 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
fa1c114f
JS		 2230}
2231
2232
036cd1ec
BR		 2233/**
2234 * ath5k_beacon_config - Configure the beacon queues and interrupts
2235 *
2236 * @sc: struct ath5k_softc pointer we are operating on
fa1c114f 2237 *
036cd1ec 2238 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
6ba81c2c 2239 * interrupts to detect TSF updates only.
fa1c114f
JS		 2240 */
2241static void
2242ath5k_beacon_config(struct ath5k_softc *sc)
2243{
2244 struct ath5k_hw *ah = sc->ah;
b5f03956 2245 unsigned long flags;
fa1c114f 2246
c6e387a2 2247 ath5k_hw_set_imr(ah, 0);
fa1c114f 2248 sc->bmisscount = 0;
dc1968e7 2249 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
fa1c114f 2250
1e3e6e8f 2251 if (sc->opmode == NL80211_IFTYPE_ADHOC ||
b706e65b 2252 sc->opmode == NL80211_IFTYPE_MESH_POINT ||
da966bca 2253 sc->opmode == NL80211_IFTYPE_AP) {
fa1c114f 2254 /*
036cd1ec
BR		 2255 * In IBSS mode we use a self-linked tx descriptor and let the
2256 * hardware send the beacons automatically. We have to load it
fa1c114f 2257 * only once here.
036cd1ec 2258 * We use the SWBA interrupt only to keep track of the beacon
6ba81c2c 2259 * timers in order to detect automatic TSF updates.
fa1c114f
JS		 2260 */
2261 ath5k_beaconq_config(sc);
fa1c114f 2262
036cd1ec
BR		 2263 sc->imask |= AR5K_INT_SWBA;
2264
da966bca
JS		 2265 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2266 if (ath5k_hw_hasveol(ah)) {
b5f03956 2267 spin_lock_irqsave(&sc->block, flags);
da966bca 2268 ath5k_beacon_send(sc);
b5f03956 2269 spin_unlock_irqrestore(&sc->block, flags);
da966bca
JS		 2270 }
2271 } else
2272 ath5k_beacon_update_timers(sc, -1);
fa1c114f 2273 }
fa1c114f 2274
c6e387a2 2275 ath5k_hw_set_imr(ah, sc->imask);
fa1c114f
JS		 2276}
2277
428cbd4f
NK		 2278static void ath5k_tasklet_beacon(unsigned long data)
2279{
2280 struct ath5k_softc *sc = (struct ath5k_softc *) data;
2281
2282 /*
2283 * Software beacon alert--time to send a beacon.
2284 *
2285 * In IBSS mode we use this interrupt just to
2286 * keep track of the next TBTT (target beacon
2287 * transmission time) in order to detect wether
2288 * automatic TSF updates happened.
2289 */
2290 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2291 /* XXX: only if VEOL suppported */
2292 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
2293 sc->nexttbtt += sc->bintval;
2294 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2295 "SWBA nexttbtt: %x hw_tu: %x "
2296 "TSF: %llx\n",
2297 sc->nexttbtt,
2298 TSF_TO_TU(tsf),
2299 (unsigned long long) tsf);
2300 } else {
2301 spin_lock(&sc->block);
2302 ath5k_beacon_send(sc);
2303 spin_unlock(&sc->block);
2304 }
2305}
2306
fa1c114f
JS		 2307
2308/********************\
2309* Interrupt handling *
2310\********************/
2311
2312static int
bb2becac 2313ath5k_init(struct ath5k_softc *sc)
fa1c114f 2314{
bc1b32d6
EO		 2315 struct ath5k_hw *ah = sc->ah;
2316 int ret, i;
fa1c114f
JS		 2317
2318 mutex_lock(&sc->lock);
2319
2320 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2321
2322 /*
2323 * Stop anything previously setup. This is safe
2324 * no matter this is the first time through or not.
2325 */
2326 ath5k_stop_locked(sc);
2327
2328 /*
2329 * The basic interface to setting the hardware in a good
2330 * state is ``reset''. On return the hardware is known to
2331 * be powered up and with interrupts disabled. This must
2332 * be followed by initialization of the appropriate bits
2333 * and then setup of the interrupt mask.
2334 */
d8ee398d
LR		 2335 sc->curchan = sc->hw->conf.channel;
2336 sc->curband = &sc->sbands[sc->curchan->band];
6a53a8a9
NK		 2337 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2338 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
9ca9fb8a 2339 AR5K_INT_FATAL | AR5K_INT_GLOBAL;
d7dc1003
JS		 2340 ret = ath5k_reset(sc, false, false);
2341 if (ret)
2342 goto done;
fa1c114f 2343
bc1b32d6
EO		 2344 /*
2345 * Reset the key cache since some parts do not reset the
2346 * contents on initial power up or resume from suspend.
2347 */
2348 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
2349 ath5k_hw_reset_key(ah, i);
2350
fa1c114f 2351 /* Set ack to be sent at low bit-rates */
bc1b32d6 2352 ath5k_hw_set_ack_bitrate_high(ah, false);
fa1c114f
JS		 2353
2354 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2355 msecs_to_jiffies(ath5k_calinterval * 1000)));
2356
2357 ret = 0;
2358done:
274c7c36 2359 mmiowb();
fa1c114f
JS		 2360 mutex_unlock(&sc->lock);
2361 return ret;
2362}
2363
2364static int
2365ath5k_stop_locked(struct ath5k_softc *sc)
2366{
2367 struct ath5k_hw *ah = sc->ah;
2368
2369 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2370 test_bit(ATH_STAT_INVALID, sc->status));
2371
2372 /*
2373 * Shutdown the hardware and driver:
2374 * stop output from above
2375 * disable interrupts
2376 * turn off timers
2377 * turn off the radio
2378 * clear transmit machinery
2379 * clear receive machinery
2380 * drain and release tx queues
2381 * reclaim beacon resources
2382 * power down hardware
2383 *
2384 * Note that some of this work is not possible if the
2385 * hardware is gone (invalid).
2386 */
2387 ieee80211_stop_queues(sc->hw);
2388
2389 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
3a078876 2390 ath5k_led_off(sc);
c6e387a2 2391 ath5k_hw_set_imr(ah, 0);
274c7c36 2392 synchronize_irq(sc->pdev->irq);
fa1c114f
JS		 2393 }
2394 ath5k_txq_cleanup(sc);
2395 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2396 ath5k_rx_stop(sc);
2397 ath5k_hw_phy_disable(ah);
2398 } else
2399 sc->rxlink = NULL;
2400
2401 return 0;
2402}
2403
2404/*
2405 * Stop the device, grabbing the top-level lock to protect
2406 * against concurrent entry through ath5k_init (which can happen
2407 * if another thread does a system call and the thread doing the
2408 * stop is preempted).
2409 */
2410static int
bb2becac 2411ath5k_stop_hw(struct ath5k_softc *sc)
fa1c114f
JS		 2412{
2413 int ret;
2414
2415 mutex_lock(&sc->lock);
2416 ret = ath5k_stop_locked(sc);
2417 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2418 /*
2419 * Set the chip in full sleep mode. Note that we are
2420 * careful to do this only when bringing the interface
2421 * completely to a stop. When the chip is in this state
2422 * it must be carefully woken up or references to
2423 * registers in the PCI clock domain may freeze the bus
2424 * (and system). This varies by chip and is mostly an
2425 * issue with newer parts that go to sleep more quickly.
2426 */
2427 if (sc->ah->ah_mac_srev >= 0x78) {
2428 /*
2429 * XXX
2430 * don't put newer MAC revisions > 7.8 to sleep because
2431 * of the above mentioned problems
2432 */
2433 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2434 "not putting device to sleep\n");
2435 } else {
2436 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2437 "putting device to full sleep\n");
2438 ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2439 }
2440 }
2441 ath5k_txbuf_free(sc, sc->bbuf);
8bdd5b9c 2442
274c7c36 2443 mmiowb();
fa1c114f
JS		 2444 mutex_unlock(&sc->lock);
2445
2446 del_timer_sync(&sc->calib_tim);
10488f8a
JS		 2447 tasklet_kill(&sc->rxtq);
2448 tasklet_kill(&sc->txtq);
2449 tasklet_kill(&sc->restq);
acf3c1a5 2450 tasklet_kill(&sc->beacontq);
fa1c114f
JS		 2451
2452 return ret;
2453}
2454
2455static irqreturn_t
2456ath5k_intr(int irq, void *dev_id)
2457{
2458 struct ath5k_softc *sc = dev_id;
2459 struct ath5k_hw *ah = sc->ah;
2460 enum ath5k_int status;
2461 unsigned int counter = 1000;
2462
2463 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2464 !ath5k_hw_is_intr_pending(ah)))
2465 return IRQ_NONE;
2466
2467 do {
fa1c114f
JS		 2468 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2469 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2470 status, sc->imask);
fa1c114f
JS		 2471 if (unlikely(status & AR5K_INT_FATAL)) {
2472 /*
2473 * Fatal errors are unrecoverable.
2474 * Typically these are caused by DMA errors.
2475 */
2476 tasklet_schedule(&sc->restq);
2477 } else if (unlikely(status & AR5K_INT_RXORN)) {
2478 tasklet_schedule(&sc->restq);
2479 } else {
2480 if (status & AR5K_INT_SWBA) {
56d2ac76 2481 tasklet_hi_schedule(&sc->beacontq);
fa1c114f
JS		 2482 }
2483 if (status & AR5K_INT_RXEOL) {
2484 /*
2485 * NB: the hardware should re-read the link when
2486 * RXE bit is written, but it doesn't work at
2487 * least on older hardware revs.
2488 */
2489 sc->rxlink = NULL;
2490 }
2491 if (status & AR5K_INT_TXURN) {
2492 /* bump tx trigger level */
2493 ath5k_hw_update_tx_triglevel(ah, true);
2494 }
4c674c60 2495 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
fa1c114f 2496 tasklet_schedule(&sc->rxtq);
4c674c60
NK		 2497 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2498 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
fa1c114f
JS		 2499 tasklet_schedule(&sc->txtq);
2500 if (status & AR5K_INT_BMISS) {
1e3e6e8f 2501 /* TODO */
fa1c114f
JS		 2502 }
2503 if (status & AR5K_INT_MIB) {
194828a2
NK		 2504 /*
2505 * These stats are also used for ANI i think
2506 * so how about updating them more often ?
2507 */
2508 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f
JS		 2509 }
2510 }
2516baa6 2511 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
fa1c114f
JS		 2512
2513 if (unlikely(!counter))
2514 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2515
2516 return IRQ_HANDLED;
2517}
2518
2519static void
2520ath5k_tasklet_reset(unsigned long data)
2521{
2522 struct ath5k_softc *sc = (void *)data;
2523
d7dc1003 2524 ath5k_reset_wake(sc);
fa1c114f
JS		 2525}
2526
2527/*
2528 * Periodically recalibrate the PHY to account
2529 * for temperature/environment changes.
2530 */
2531static void
2532ath5k_calibrate(unsigned long data)
2533{
2534 struct ath5k_softc *sc = (void *)data;
2535 struct ath5k_hw *ah = sc->ah;
2536
2537 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
400ec45a
LR		 2538 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2539 sc->curchan->hw_value);
fa1c114f 2540
6f3b414a 2541 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
fa1c114f
JS		 2542 /*
2543 * Rfgain is out of bounds, reset the chip
2544 * to load new gain values.
2545 */
2546 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
d7dc1003 2547 ath5k_reset_wake(sc);
fa1c114f
JS		 2548 }
2549 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2550 ATH5K_ERR(sc, "calibration of channel %u failed\n",
400ec45a
LR		 2551 ieee80211_frequency_to_channel(
2552 sc->curchan->center_freq));
fa1c114f
JS		 2553
2554 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2555 msecs_to_jiffies(ath5k_calinterval * 1000)));
2556}
2557
2558
fa1c114f
JS		 2559/********************\
2560* Mac80211 functions *
2561\********************/
2562
2563static int
e039fa4a 2564ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
fa1c114f
JS		 2565{
2566 struct ath5k_softc *sc = hw->priv;
2567 struct ath5k_buf *bf;
2568 unsigned long flags;
2569 int hdrlen;
0fe45b1d 2570 int padsize;
fa1c114f
JS		 2571
2572 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2573
05c914fe 2574 if (sc->opmode == NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 2575 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2576
2577 /*
2578 * the hardware expects the header padded to 4 byte boundaries
2579 * if this is not the case we add the padding after the header
2580 */
2581 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
fd6effca
BC		 2582 padsize = ath5k_pad_size(hdrlen);
2583 if (padsize) {
0fe45b1d
BP		 2584
2585 if (skb_headroom(skb) < padsize) {
fa1c114f 2586 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
0fe45b1d 2587 " headroom to pad %d\n", hdrlen, padsize);
5a0fe8ac 2588 goto drop_packet;
fa1c114f 2589 }
0fe45b1d
BP		 2590 skb_push(skb, padsize);
2591 memmove(skb->data, skb->data+padsize, hdrlen);
fa1c114f
JS		 2592 }
2593
fa1c114f
JS		 2594 spin_lock_irqsave(&sc->txbuflock, flags);
2595 if (list_empty(&sc->txbuf)) {
2596 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2597 spin_unlock_irqrestore(&sc->txbuflock, flags);
e2530083 2598 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
5a0fe8ac 2599 goto drop_packet;
fa1c114f
JS		 2600 }
2601 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2602 list_del(&bf->list);
2603 sc->txbuf_len--;
2604 if (list_empty(&sc->txbuf))
2605 ieee80211_stop_queues(hw);
2606 spin_unlock_irqrestore(&sc->txbuflock, flags);
2607
2608 bf->skb = skb;
2609
e039fa4a 2610 if (ath5k_txbuf_setup(sc, bf)) {
fa1c114f
JS		 2611 bf->skb = NULL;
2612 spin_lock_irqsave(&sc->txbuflock, flags);
2613 list_add_tail(&bf->list, &sc->txbuf);
2614 sc->txbuf_len++;
2615 spin_unlock_irqrestore(&sc->txbuflock, flags);
5a0fe8ac 2616 goto drop_packet;
fa1c114f 2617 }
5a0fe8ac 2618 return NETDEV_TX_OK;
fa1c114f 2619
5a0fe8ac
BC		 2620drop_packet:
2621 dev_kfree_skb_any(skb);
71ef99c8 2622 return NETDEV_TX_OK;
fa1c114f
JS		 2623}
2624
2625static int
d7dc1003 2626ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel)
fa1c114f 2627{
fa1c114f
JS		 2628 struct ath5k_hw *ah = sc->ah;
2629 int ret;
2630
2631 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
fa1c114f 2632
d7dc1003 2633 if (stop) {
c6e387a2 2634 ath5k_hw_set_imr(ah, 0);
d7dc1003
JS		 2635 ath5k_txq_cleanup(sc);
2636 ath5k_rx_stop(sc);
2637 }
fa1c114f 2638 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
d7dc1003 2639 if (ret) {
fa1c114f
JS		 2640 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2641 goto err;
2642 }
d7dc1003 2643
fa1c114f 2644 ret = ath5k_rx_start(sc);
d7dc1003 2645 if (ret) {
fa1c114f
JS		 2646 ATH5K_ERR(sc, "can't start recv logic\n");
2647 goto err;
2648 }
d7dc1003 2649
fa1c114f 2650 /*
d7dc1003
JS		 2651 * Change channels and update the h/w rate map if we're switching;
2652 * e.g. 11a to 11b/g.
2653 *
2654 * We may be doing a reset in response to an ioctl that changes the
2655 * channel so update any state that might change as a result.
fa1c114f
JS		 2656 *
2657 * XXX needed?
2658 */
2659/* ath5k_chan_change(sc, c); */
fa1c114f 2660
d7dc1003
JS		 2661 ath5k_beacon_config(sc);
2662 /* intrs are enabled by ath5k_beacon_config */
fa1c114f
JS		 2663
2664 return 0;
2665err:
2666 return ret;
2667}
2668
d7dc1003
JS		 2669static int
2670ath5k_reset_wake(struct ath5k_softc *sc)
2671{
2672 int ret;
2673
2674 ret = ath5k_reset(sc, true, true);
2675 if (!ret)
2676 ieee80211_wake_queues(sc->hw);
2677
2678 return ret;
2679}
2680
fa1c114f
JS		 2681static int ath5k_start(struct ieee80211_hw *hw)
2682{
bb2becac 2683 return ath5k_init(hw->priv);
fa1c114f
JS		 2684}
2685
2686static void ath5k_stop(struct ieee80211_hw *hw)
2687{
bb2becac 2688 ath5k_stop_hw(hw->priv);
fa1c114f
JS		 2689}
2690
2691static int ath5k_add_interface(struct ieee80211_hw *hw,
2692 struct ieee80211_if_init_conf *conf)
2693{
2694 struct ath5k_softc *sc = hw->priv;
2695 int ret;
2696
2697 mutex_lock(&sc->lock);
32bfd35d 2698 if (sc->vif) {
fa1c114f
JS		 2699 ret = 0;
2700 goto end;
2701 }
2702
32bfd35d 2703 sc->vif = conf->vif;
fa1c114f
JS		 2704
2705 switch (conf->type) {
da966bca 2706 case NL80211_IFTYPE_AP:
05c914fe
JB		 2707 case NL80211_IFTYPE_STATION:
2708 case NL80211_IFTYPE_ADHOC:
b706e65b 2709 case NL80211_IFTYPE_MESH_POINT:
05c914fe 2710 case NL80211_IFTYPE_MONITOR:
fa1c114f
JS		 2711 sc->opmode = conf->type;
2712 break;
2713 default:
2714 ret = -EOPNOTSUPP;
2715 goto end;
2716 }
67d2e2df
JS		 2717
2718 /* Set to a reasonable value. Note that this will
2719 * be set to mac80211's value at ath5k_config(). */
2720 sc->bintval = 1000;
0e149cf5 2721 ath5k_hw_set_lladdr(sc->ah, conf->mac_addr);
67d2e2df 2722
fa1c114f
JS		 2723 ret = 0;
2724end:
2725 mutex_unlock(&sc->lock);
2726 return ret;
2727}
2728
2729static void
2730ath5k_remove_interface(struct ieee80211_hw *hw,
2731 struct ieee80211_if_init_conf *conf)
2732{
2733 struct ath5k_softc *sc = hw->priv;
0e149cf5 2734 u8 mac[ETH_ALEN] = {};
fa1c114f
JS		 2735
2736 mutex_lock(&sc->lock);
32bfd35d 2737 if (sc->vif != conf->vif)
fa1c114f
JS		 2738 goto end;
2739
0e149cf5 2740 ath5k_hw_set_lladdr(sc->ah, mac);
32bfd35d 2741 sc->vif = NULL;
fa1c114f
JS		 2742end:
2743 mutex_unlock(&sc->lock);
2744}
2745
d8ee398d
LR		 2746/*
2747 * TODO: Phy disable/diversity etc
2748 */
fa1c114f 2749static int
e8975581 2750ath5k_config(struct ieee80211_hw *hw, u32 changed)
fa1c114f
JS		 2751{
2752 struct ath5k_softc *sc = hw->priv;
a0823810 2753 struct ath5k_hw *ah = sc->ah;
e8975581 2754 struct ieee80211_conf *conf = &hw->conf;
be009370
BC		 2755 int ret;
2756
2757 mutex_lock(&sc->lock);
fa1c114f 2758
a0823810
NK		 2759 sc->bintval = conf->beacon_int;
2760
2761 if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
2762 (sc->power_level != conf->power_level)) {
2763 sc->power_level = conf->power_level;
2764
2765 /* Half dB steps */
2766 ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
2767 }
fa1c114f 2768
be009370
BC		 2769 ret = ath5k_chan_set(sc, conf->channel);
2770
2771 mutex_unlock(&sc->lock);
2772 return ret;
fa1c114f
JS		 2773}
2774
fa1c114f
JS		 2775#define SUPPORTED_FIF_FLAGS \
2776 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2777 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2778 FIF_BCN_PRBRESP_PROMISC
2779/*
2780 * o always accept unicast, broadcast, and multicast traffic
2781 * o multicast traffic for all BSSIDs will be enabled if mac80211
2782 * says it should be
2783 * o maintain current state of phy ofdm or phy cck error reception.
2784 * If the hardware detects any of these type of errors then
2785 * ath5k_hw_get_rx_filter() will pass to us the respective
2786 * hardware filters to be able to receive these type of frames.
2787 * o probe request frames are accepted only when operating in
2788 * hostap, adhoc, or monitor modes
2789 * o enable promiscuous mode according to the interface state
2790 * o accept beacons:
2791 * - when operating in adhoc mode so the 802.11 layer creates
2792 * node table entries for peers,
2793 * - when operating in station mode for collecting rssi data when
2794 * the station is otherwise quiet, or
2795 * - when scanning
2796 */
2797static void ath5k_configure_filter(struct ieee80211_hw *hw,
2798 unsigned int changed_flags,
2799 unsigned int *new_flags,
2800 int mc_count, struct dev_mc_list *mclist)
2801{
2802 struct ath5k_softc *sc = hw->priv;
2803 struct ath5k_hw *ah = sc->ah;
2804 u32 mfilt[2], val, rfilt;
2805 u8 pos;
2806 int i;
2807
2808 mfilt[0] = 0;
2809 mfilt[1] = 0;
2810
2811 /* Only deal with supported flags */
2812 changed_flags &= SUPPORTED_FIF_FLAGS;
2813 *new_flags &= SUPPORTED_FIF_FLAGS;
2814
2815 /* If HW detects any phy or radar errors, leave those filters on.
2816 * Also, always enable Unicast, Broadcasts and Multicast
2817 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2818 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2819 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2820 AR5K_RX_FILTER_MCAST);
2821
2822 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2823 if (*new_flags & FIF_PROMISC_IN_BSS) {
2824 rfilt |= AR5K_RX_FILTER_PROM;
2825 __set_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 2826 } else {
fa1c114f 2827 __clear_bit(ATH_STAT_PROMISC, sc->status);
0bbac08f 2828 }
fa1c114f
JS		 2829 }
2830
2831 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2832 if (*new_flags & FIF_ALLMULTI) {
2833 mfilt[0] = ~0;
2834 mfilt[1] = ~0;
2835 } else {
2836 for (i = 0; i < mc_count; i++) {
2837 if (!mclist)
2838 break;
2839 /* calculate XOR of eight 6-bit values */
533dd1b0 2840 val = get_unaligned_le32(mclist->dmi_addr + 0);
fa1c114f 2841 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
533dd1b0 2842 val = get_unaligned_le32(mclist->dmi_addr + 3);
fa1c114f
JS		 2843 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2844 pos &= 0x3f;
2845 mfilt[pos / 32] |= (1 << (pos % 32));
2846 /* XXX: we might be able to just do this instead,
2847 * but not sure, needs testing, if we do use this we'd
2848 * neet to inform below to not reset the mcast */
2849 /* ath5k_hw_set_mcast_filterindex(ah,
2850 * mclist->dmi_addr[5]); */
2851 mclist = mclist->next;
2852 }
2853 }
2854
2855 /* This is the best we can do */
2856 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2857 rfilt |= AR5K_RX_FILTER_PHYERR;
2858
2859 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2860 * and probes for any BSSID, this needs testing */
2861 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2862 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2863
2864 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2865 * set we should only pass on control frames for this
2866 * station. This needs testing. I believe right now this
2867 * enables *all* control frames, which is OK.. but
2868 * but we should see if we can improve on granularity */
2869 if (*new_flags & FIF_CONTROL)
2870 rfilt |= AR5K_RX_FILTER_CONTROL;
2871
2872 /* Additional settings per mode -- this is per ath5k */
2873
2874 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2875
05c914fe 2876 if (sc->opmode == NL80211_IFTYPE_MONITOR)
fa1c114f
JS		 2877 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2878 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
05c914fe 2879 if (sc->opmode != NL80211_IFTYPE_STATION)
fa1c114f 2880 rfilt |= AR5K_RX_FILTER_PROBEREQ;
05c914fe
JB		 2881 if (sc->opmode != NL80211_IFTYPE_AP &&
2882 sc->opmode != NL80211_IFTYPE_MESH_POINT &&
fa1c114f
JS		 2883 test_bit(ATH_STAT_PROMISC, sc->status))
2884 rfilt |= AR5K_RX_FILTER_PROM;
02969b38 2885 if ((sc->opmode == NL80211_IFTYPE_STATION && sc->assoc) ||
296bf2ae
LR		 2886 sc->opmode == NL80211_IFTYPE_ADHOC ||
2887 sc->opmode == NL80211_IFTYPE_AP)
fa1c114f 2888 rfilt |= AR5K_RX_FILTER_BEACON;
b706e65b
AY		 2889 if (sc->opmode == NL80211_IFTYPE_MESH_POINT)
2890 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2891 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
fa1c114f
JS		 2892
2893 /* Set filters */
0bbac08f 2894 ath5k_hw_set_rx_filter(ah, rfilt);
fa1c114f
JS		 2895
2896 /* Set multicast bits */
2897 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2898 /* Set the cached hw filter flags, this will alter actually
2899 * be set in HW */
2900 sc->filter_flags = rfilt;
2901}
2902
2903static int
2904ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
dc822b5d
JB		 2905 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
2906 struct ieee80211_key_conf *key)
fa1c114f
JS		 2907{
2908 struct ath5k_softc *sc = hw->priv;
2909 int ret = 0;
2910
9ad9a26e
BC		 2911 if (modparam_nohwcrypt)
2912 return -EOPNOTSUPP;
2913
0bbac08f 2914 switch (key->alg) {
fa1c114f 2915 case ALG_WEP:
fa1c114f 2916 case ALG_TKIP:
3f64b435 2917 break;
fa1c114f
JS		 2918 case ALG_CCMP:
2919 return -EOPNOTSUPP;
2920 default:
2921 WARN_ON(1);
2922 return -EINVAL;
2923 }
2924
2925 mutex_lock(&sc->lock);
2926
2927 switch (cmd) {
2928 case SET_KEY:
dc822b5d
JB		 2929 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key,
2930 sta ? sta->addr : NULL);
fa1c114f
JS		 2931 if (ret) {
2932 ATH5K_ERR(sc, "can't set the key\n");
2933 goto unlock;
2934 }
2935 __set_bit(key->keyidx, sc->keymap);
2936 key->hw_key_idx = key->keyidx;
3f64b435
BC		 2937 key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV |
2938 IEEE80211_KEY_FLAG_GENERATE_MMIC);
fa1c114f
JS		 2939 break;
2940 case DISABLE_KEY:
2941 ath5k_hw_reset_key(sc->ah, key->keyidx);
2942 __clear_bit(key->keyidx, sc->keymap);
2943 break;
2944 default:
2945 ret = -EINVAL;
2946 goto unlock;
2947 }
2948
2949unlock:
274c7c36 2950 mmiowb();
fa1c114f
JS		 2951 mutex_unlock(&sc->lock);
2952 return ret;
2953}
2954
2955static int
2956ath5k_get_stats(struct ieee80211_hw *hw,
2957 struct ieee80211_low_level_stats *stats)
2958{
2959 struct ath5k_softc *sc = hw->priv;
194828a2
NK		 2960 struct ath5k_hw *ah = sc->ah;
2961
2962 /* Force update */
2963 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
fa1c114f
JS		 2964
2965 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
2966
2967 return 0;
2968}
2969
2970static int
2971ath5k_get_tx_stats(struct ieee80211_hw *hw,
2972 struct ieee80211_tx_queue_stats *stats)
2973{
2974 struct ath5k_softc *sc = hw->priv;
2975
2976 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
2977
2978 return 0;
2979}
2980
2981static u64
2982ath5k_get_tsf(struct ieee80211_hw *hw)
2983{
2984 struct ath5k_softc *sc = hw->priv;
2985
2986 return ath5k_hw_get_tsf64(sc->ah);
2987}
2988
3b5d665b
AF		 2989static void
2990ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2991{
2992 struct ath5k_softc *sc = hw->priv;
2993
2994 ath5k_hw_set_tsf64(sc->ah, tsf);
2995}
2996
fa1c114f
JS		 2997static void
2998ath5k_reset_tsf(struct ieee80211_hw *hw)
2999{
3000 struct ath5k_softc *sc = hw->priv;
3001
9804b98d
BR		 3002 /*
3003 * in IBSS mode we need to update the beacon timers too.
3004 * this will also reset the TSF if we call it with 0
3005 */
05c914fe 3006 if (sc->opmode == NL80211_IFTYPE_ADHOC)
9804b98d
BR		 3007 ath5k_beacon_update_timers(sc, 0);
3008 else
3009 ath5k_hw_reset_tsf(sc->ah);
fa1c114f
JS		 3010}
3011
3012static int
da966bca 3013ath5k_beacon_update(struct ath5k_softc *sc, struct sk_buff *skb)
fa1c114f 3014{
00482973 3015 unsigned long flags;
fa1c114f
JS		 3016 int ret;
3017
3018 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3019
00482973 3020 spin_lock_irqsave(&sc->block, flags);
fa1c114f
JS		 3021 ath5k_txbuf_free(sc, sc->bbuf);
3022 sc->bbuf->skb = skb;
e039fa4a 3023 ret = ath5k_beacon_setup(sc, sc->bbuf);
fa1c114f
JS		 3024 if (ret)
3025 sc->bbuf->skb = NULL;
00482973
JS		 3026 spin_unlock_irqrestore(&sc->block, flags);
3027 if (!ret) {
fa1c114f 3028 ath5k_beacon_config(sc);
274c7c36
JS		 3029 mmiowb();
3030 }
fa1c114f 3031
fa1c114f
JS		 3032 return ret;
3033}
02969b38
MX		 3034static void
3035set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3036{
3037 struct ath5k_softc *sc = hw->priv;
3038 struct ath5k_hw *ah = sc->ah;
3039 u32 rfilt;
3040 rfilt = ath5k_hw_get_rx_filter(ah);
3041 if (enable)
3042 rfilt |= AR5K_RX_FILTER_BEACON;
3043 else
3044 rfilt &= ~AR5K_RX_FILTER_BEACON;
3045 ath5k_hw_set_rx_filter(ah, rfilt);
3046 sc->filter_flags = rfilt;
3047}
fa1c114f 3048
02969b38
MX		 3049static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3050 struct ieee80211_vif *vif,
3051 struct ieee80211_bss_conf *bss_conf,
3052 u32 changes)
3053{
3054 struct ath5k_softc *sc = hw->priv;
2d0ddec5
JB		 3055 struct ath5k_hw *ah = sc->ah;
3056
3057 mutex_lock(&sc->lock);
3058 if (WARN_ON(sc->vif != vif))
3059 goto unlock;
3060
3061 if (changes & BSS_CHANGED_BSSID) {
3062 /* Cache for later use during resets */
3063 memcpy(ah->ah_bssid, bss_conf->bssid, ETH_ALEN);
3064 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
3065 * a clean way of letting us retrieve this yet. */
3066 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
3067 mmiowb();
3068 }
57c4d7b4
JB		 3069
3070 if (changes & BSS_CHANGED_BEACON_INT)
3071 sc->bintval = bss_conf->beacon_int;
3072
02969b38 3073 if (changes & BSS_CHANGED_ASSOC) {
02969b38
MX		 3074 sc->assoc = bss_conf->assoc;
3075 if (sc->opmode == NL80211_IFTYPE_STATION)
3076 set_beacon_filter(hw, sc->assoc);
02969b38 3077 }
2d0ddec5
JB		 3078
3079 if (changes & BSS_CHANGED_BEACON &&
3080 (vif->type == NL80211_IFTYPE_ADHOC ||
3081 vif->type == NL80211_IFTYPE_MESH_POINT ||
3082 vif->type == NL80211_IFTYPE_AP)) {
3083 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
3084
3085 if (beacon)
3086 ath5k_beacon_update(sc, beacon);
3087 }
3088
3089 unlock:
3090 mutex_unlock(&sc->lock);
02969b38 3091}
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