[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / ath / ath5k / base.h

/*-
 * Copyright (c) 2002-2007 Sam Leffler, Errno Consulting
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer,
 *    without modification.
 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
 *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
 *    redistribution must be conditioned upon including a substantially
 *    similar Disclaimer requirement for further binary redistribution.
 * 3. Neither the names of the above-listed copyright holders nor the names
 *    of any contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 * Alternatively, this software may be distributed under the terms of the
 * GNU General Public License ("GPL") version 2 as published by the Free
 * Software Foundation.
 *
 * NO WARRANTY
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
 * THE POSSIBILITY OF SUCH DAMAGES.
 *
 */

/*
 * Definitions for the Atheros Wireless LAN controller driver.
 */
#ifndef _DEV_ATH_ATHVAR_H
#define _DEV_ATH_ATHVAR_H

#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/wireless.h>
#include <linux/if_ether.h>
#include <linux/leds.h>
#include <linux/rfkill.h>

#include "ath5k.h"
#include "debug.h"

#include "../regd.h"
#include "../ath.h"

#define	ATH_RXBUF	40		/* number of RX buffers */
#define	ATH_TXBUF	200		/* number of TX buffers */
#define ATH_BCBUF	1		/* number of beacon buffers */

struct ath5k_buf {
	struct list_head	list;
	struct ath5k_desc	*desc;	/* virtual addr of desc */
	dma_addr_t		daddr;	/* physical addr of desc */
	struct sk_buff		*skb;	/* skbuff for buf */
	dma_addr_t		skbaddr;/* physical addr of skb data */
};

/*
 * Data transmit queue state.  One of these exists for each
 * hardware transmit queue.  Packets sent to us from above
 * are assigned to queues based on their priority.  Not all
 * devices support a complete set of hardware transmit queues.
 * For those devices the array sc_ac2q will map multiple
 * priorities to fewer hardware queues (typically all to one
 * hardware queue).
 */
struct ath5k_txq {
	unsigned int		qnum;	/* hardware q number */
	u32			*link;	/* link ptr in last TX desc */
	struct list_head	q;	/* transmit queue */
	spinlock_t		lock;	/* lock on q and link */
	bool			setup;
};

#define ATH5K_LED_MAX_NAME_LEN 31

/*
 * State for LED triggers
 */
struct ath5k_led
{
	char name[ATH5K_LED_MAX_NAME_LEN + 1];	/* name of the LED in sysfs */
	struct ath5k_softc *sc;			/* driver state */
	struct led_classdev led_dev;		/* led classdev */
};

/* Rfkill */
struct ath5k_rfkill {
	/* GPIO PIN for rfkill */
	u16 gpio;
	/* polarity of rfkill GPIO PIN */
	bool polarity;
	/* RFKILL toggle tasklet */
	struct tasklet_struct toggleq;
};

#if CHAN_DEBUG
#define ATH_CHAN_MAX	(26+26+26+200+200)
#else
#define ATH_CHAN_MAX	(14+14+14+252+20)
#endif

/* Software Carrier, keeps track of the driver state
 * associated with an instance of a device */
struct ath5k_softc {
	struct pci_dev		*pdev;		/* for dma mapping */
	void __iomem		*iobase;	/* address of the device */
	struct mutex		lock;		/* dev-level lock */
	struct ieee80211_low_level_stats ll_stats;
	struct ieee80211_hw	*hw;		/* IEEE 802.11 common */
	struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
	struct ieee80211_channel channels[ATH_CHAN_MAX];
	struct ieee80211_rate	rates[IEEE80211_NUM_BANDS][AR5K_MAX_RATES];
	s8			rate_idx[IEEE80211_NUM_BANDS][AR5K_MAX_RATES];
	enum nl80211_iftype	opmode;
	struct ath5k_hw		*ah;		/* Atheros HW */

	struct ieee80211_supported_band		*curband;

#ifdef CONFIG_ATH5K_DEBUG
	struct ath5k_dbg_info	debug;		/* debug info */
#endif /* CONFIG_ATH5K_DEBUG */

	struct ath5k_buf	*bufptr;	/* allocated buffer ptr */
	struct ath5k_desc	*desc;		/* TX/RX descriptors */
	dma_addr_t		desc_daddr;	/* DMA (physical) address */
	size_t			desc_len;	/* size of TX/RX descriptors */

	DECLARE_BITMAP(status, 5);
#define ATH_STAT_INVALID	0		/* disable hardware accesses */
#define ATH_STAT_MRRETRY	1		/* multi-rate retry support */
#define ATH_STAT_PROMISC	2
#define ATH_STAT_LEDSOFT	3		/* enable LED gpio status */
#define ATH_STAT_STARTED	4		/* opened & irqs enabled */

	unsigned int		filter_flags;	/* HW flags, AR5K_RX_FILTER_* */
	unsigned int		curmode;	/* current phy mode */
	struct ieee80211_channel *curchan;	/* current h/w channel */

	struct ieee80211_vif *vif;

	enum ath5k_int		imask;		/* interrupt mask copy */

	u8			bssidmask[ETH_ALEN];

	unsigned int		led_pin,	/* GPIO pin for driving LED */
				led_on;		/* pin setting for LED on */

	struct tasklet_struct	restq;		/* reset tasklet */

	unsigned int		rxbufsize;	/* rx size based on mtu */
	struct list_head	rxbuf;		/* receive buffer */
	spinlock_t		rxbuflock;
	u32			*rxlink;	/* link ptr in last RX desc */
	struct tasklet_struct	rxtq;		/* rx intr tasklet */
	struct ath5k_led	rx_led;		/* rx led */

	struct list_head	txbuf;		/* transmit buffer */
	spinlock_t		txbuflock;
	unsigned int		txbuf_len;	/* buf count in txbuf list */
	struct ath5k_txq	txqs[AR5K_NUM_TX_QUEUES];	/* tx queues */
	struct ath5k_txq	*txq;		/* main tx queue */
	struct tasklet_struct	txtq;		/* tx intr tasklet */
	struct ath5k_led	tx_led;		/* tx led */

	struct ath5k_rfkill	rf_kill;

	struct tasklet_struct	calib;		/* calibration tasklet */

	spinlock_t		block;		/* protects beacon */
	struct tasklet_struct	beacontq;	/* beacon intr tasklet */
	struct ath5k_buf	*bbuf;		/* beacon buffer */
	unsigned int		bhalq,		/* SW q for outgoing beacons */
				bmisscount,	/* missed beacon transmits */
				bintval,	/* beacon interval in TU */
				bsent;
	unsigned int		nexttbtt;	/* next beacon time in TU */
	struct ath5k_txq	*cabq;		/* content after beacon */

	int 			power_level;	/* Requested tx power in dbm */
	bool			assoc;		/* associate state */
	bool			enable_beacon;	/* true if beacons are on */
};

#define ath5k_hw_hasbssidmask(_ah) \
	(ath5k_hw_get_capability(_ah, AR5K_CAP_BSSIDMASK, 0, NULL) == 0)
#define ath5k_hw_hasveol(_ah) \
	(ath5k_hw_get_capability(_ah, AR5K_CAP_VEOL, 0, NULL) == 0)

#endif
Commit	Line	Data
fa1c114f JS	1	/*-
	2	* Copyright (c) 2002-2007 Sam Leffler, Errno Consulting
	3	* All rights reserved.
	4	*
	5	* Redistribution and use in source and binary forms, with or without
	6	* modification, are permitted provided that the following conditions
	7	* are met:
	8	* 1. Redistributions of source code must retain the above copyright
	9	* notice, this list of conditions and the following disclaimer,
	10	* without modification.
	11	* 2. Redistributions in binary form must reproduce at minimum a disclaimer
	12	* similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
	13	* redistribution must be conditioned upon including a substantially
	14	* similar Disclaimer requirement for further binary redistribution.
	15	* 3. Neither the names of the above-listed copyright holders nor the names
	16	* of any contributors may be used to endorse or promote products derived
	17	* from this software without specific prior written permission.
	18	*
	19	* Alternatively, this software may be distributed under the terms of the
	20	* GNU General Public License ("GPL") version 2 as published by the Free
	21	* Software Foundation.
	22	*
	23	* NO WARRANTY
	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
	25	* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
	26	* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
	27	* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
	28	* THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
	29	* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
	30	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
	31	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
	32	* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
	33	* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
	34	* THE POSSIBILITY OF SUCH DAMAGES.
	35	*
	36	*/
	37
	38	/*
6070d81e	39	* Definitions for the Atheros Wireless LAN controller driver.
fa1c114f JS	40	*/
	41	#ifndef _DEV_ATH_ATHVAR_H
	42	#define _DEV_ATH_ATHVAR_H
	43
	44	#include <linux/interrupt.h>
	45	#include <linux/list.h>
	46	#include <linux/wireless.h>
	47	#include <linux/if_ether.h>
3a078876	48	#include <linux/leds.h>
e6a3b616	49	#include <linux/rfkill.h>
fa1c114f JS	50
	51	#include "ath5k.h"
	52	#include "debug.h"
608b88cb LR	53
608b88cb LR	54	#include "../regd.h"
aeb63cfd	55	#include "../ath.h"
fa1c114f JS	56
	57	#define ATH_RXBUF 40 /* number of RX buffers */
	58	#define ATH_TXBUF 200 /* number of TX buffers */
	59	#define ATH_BCBUF 1 /* number of beacon buffers */
	60
	61	struct ath5k_buf {
	62	struct list_head list;
fa1c114f JS	63	struct ath5k_desc desc; / virtual addr of desc */
	64	dma_addr_t daddr; /* physical addr of desc */
	65	struct sk_buff skb; / skbuff for buf */
	66	dma_addr_t skbaddr;/* physical addr of skb data */
fa1c114f JS	67	};
	68
	69	/*
	70	* Data transmit queue state. One of these exists for each
	71	* hardware transmit queue. Packets sent to us from above
	72	* are assigned to queues based on their priority. Not all
	73	* devices support a complete set of hardware transmit queues.
	74	* For those devices the array sc_ac2q will map multiple
	75	* priorities to fewer hardware queues (typically all to one
	76	* hardware queue).
	77	*/
	78	struct ath5k_txq {
	79	unsigned int qnum; /* hardware q number */
	80	u32 link; / link ptr in last TX desc */
	81	struct list_head q; /* transmit queue */
	82	spinlock_t lock; /* lock on q and link */
	83	bool setup;
	84	};
	85
3a078876 BC	86	#define ATH5K_LED_MAX_NAME_LEN 31
	87
	88	/*
	89	* State for LED triggers
	90	*/
	91	struct ath5k_led
	92	{
	93	char name[ATH5K_LED_MAX_NAME_LEN + 1]; /* name of the LED in sysfs */
	94	struct ath5k_softc sc; / driver state */
	95	struct led_classdev led_dev; /* led classdev */
	96	};
	97
e6a3b616 TD	98	/* Rfkill */
	99	struct ath5k_rfkill {
	100	/* GPIO PIN for rfkill */
	101	u16 gpio;
	102	/* polarity of rfkill GPIO PIN */
	103	bool polarity;
	104	/* RFKILL toggle tasklet */
	105	struct tasklet_struct toggleq;
	106	};
3a078876	107
fa1c114f JS	108	#if CHAN_DEBUG
	109	#define ATH_CHAN_MAX (26+26+26+200+200)
	110	#else
d8ee398d	111	#define ATH_CHAN_MAX (14+14+14+252+20)
fa1c114f JS	112	#endif
	113
	114	/* Software Carrier, keeps track of the driver state
	115	* associated with an instance of a device */
	116	struct ath5k_softc {
	117	struct pci_dev pdev; / for dma mapping */
	118	void __iomem iobase; / address of the device */
	119	struct mutex lock; /* dev-level lock */
fa1c114f JS	120	struct ieee80211_low_level_stats ll_stats;
fa1c114f JS	121	struct ieee80211_hw hw; / IEEE 802.11 common */
d8ee398d	122	struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
fa1c114f	123	struct ieee80211_channel channels[ATH_CHAN_MAX];
63266a65	124	struct ieee80211_rate rates[IEEE80211_NUM_BANDS][AR5K_MAX_RATES];
b7266047	125	s8 rate_idx[IEEE80211_NUM_BANDS][AR5K_MAX_RATES];
05c914fe	126	enum nl80211_iftype opmode;
fa1c114f JS	127	struct ath5k_hw ah; / Atheros HW */
fa1c114f JS	128
d8ee398d LR	129	struct ieee80211_supported_band *curband;
d8ee398d LR	130
b446197c	131	#ifdef CONFIG_ATH5K_DEBUG
fa1c114f	132	struct ath5k_dbg_info debug; /* debug info */
b446197c	133	#endif /* CONFIG_ATH5K_DEBUG */
fa1c114f JS	134
	135	struct ath5k_buf bufptr; / allocated buffer ptr */
	136	struct ath5k_desc desc; / TX/RX descriptors */
	137	dma_addr_t desc_daddr; /* DMA (physical) address */
	138	size_t desc_len; /* size of TX/RX descriptors */
fa1c114f	139
8bdd5b9c	140	DECLARE_BITMAP(status, 5);
fa1c114f JS	141	#define ATH_STAT_INVALID 0 /* disable hardware accesses */
	142	#define ATH_STAT_MRRETRY 1 /* multi-rate retry support */
	143	#define ATH_STAT_PROMISC 2
3a078876	144	#define ATH_STAT_LEDSOFT 3 /* enable LED gpio status */
8bdd5b9c	145	#define ATH_STAT_STARTED 4 /* opened & irqs enabled */
fa1c114f JS	146
	147	unsigned int filter_flags; /* HW flags, AR5K_RX_FILTER_* */
	148	unsigned int curmode; /* current phy mode */
	149	struct ieee80211_channel curchan; / current h/w channel */
	150
32bfd35d	151	struct ieee80211_vif *vif;
fa1c114f	152
fa1c114f JS	153	enum ath5k_int imask; /* interrupt mask copy */
fa1c114f JS	154
fa1c114f JS	155	u8 bssidmask[ETH_ALEN];
	156
	157	unsigned int led_pin, /* GPIO pin for driving LED */
5ef4017a	158	led_on; /* pin setting for LED on */
fa1c114f JS	159
	160	struct tasklet_struct restq; /* reset tasklet */
	161
	162	unsigned int rxbufsize; /* rx size based on mtu */
	163	struct list_head rxbuf; /* receive buffer */
	164	spinlock_t rxbuflock;
	165	u32 rxlink; / link ptr in last RX desc */
	166	struct tasklet_struct rxtq; /* rx intr tasklet */
3a078876	167	struct ath5k_led rx_led; /* rx led */
fa1c114f JS	168
	169	struct list_head txbuf; /* transmit buffer */
	170	spinlock_t txbuflock;
	171	unsigned int txbuf_len; /* buf count in txbuf list */
cec8db23 BC	172	struct ath5k_txq txqs[AR5K_NUM_TX_QUEUES]; /* tx queues */
cec8db23 BC	173	struct ath5k_txq txq; / main tx queue */
fa1c114f	174	struct tasklet_struct txtq; /* tx intr tasklet */
3a078876	175	struct ath5k_led tx_led; /* tx led */
fa1c114f	176
e6a3b616	177	struct ath5k_rfkill rf_kill;
e6a3b616	178
6e220662 NK	179	struct tasklet_struct calib; /* calibration tasklet */
6e220662 NK	180
00482973	181	spinlock_t block; /* protects beacon */
acf3c1a5	182	struct tasklet_struct beacontq; /* beacon intr tasklet */
fa1c114f JS	183	struct ath5k_buf bbuf; / beacon buffer */
	184	unsigned int bhalq, /* SW q for outgoing beacons */
	185	bmisscount, /* missed beacon transmits */
e535c1ac	186	bintval, /* beacon interval in TU */
fa1c114f	187	bsent;
036cd1ec	188	unsigned int nexttbtt; /* next beacon time in TU */
cec8db23	189	struct ath5k_txq cabq; / content after beacon */
fa1c114f	190
d8ee398d	191	int power_level; /* Requested tx power in dbm */
94e2bd68	192	bool assoc; /* associate state */
21800491	193	bool enable_beacon; /* true if beacons are on */
fa1c114f JS	194	};
	195
	196	#define ath5k_hw_hasbssidmask(_ah) \
	197	(ath5k_hw_get_capability(_ah, AR5K_CAP_BSSIDMASK, 0, NULL) == 0)
	198	#define ath5k_hw_hasveol(_ah) \
	199	(ath5k_hw_get_capability(_ah, AR5K_CAP_VEOL, 0, NULL) == 0)
	200
	201	#endif