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c6e387a2 NK |
1 | /* |
2 | * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org> | |
3 | * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com> | |
4 | * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org> | |
5 | * | |
6 | * Permission to use, copy, modify, and distribute this software for any | |
7 | * purpose with or without fee is hereby granted, provided that the above | |
8 | * copyright notice and this permission notice appear in all copies. | |
9 | * | |
10 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
11 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
12 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
13 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
14 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
15 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
16 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
17 | * | |
18 | */ | |
19 | ||
20 | /******************************\ | |
21 | Hardware Descriptor Functions | |
22 | \******************************/ | |
23 | ||
24 | #include "ath5k.h" | |
25 | #include "reg.h" | |
26 | #include "debug.h" | |
c6e387a2 | 27 | |
9320b5c4 | 28 | |
c47faa36 NK |
29 | /** |
30 | * DOC: Hardware descriptor functions | |
31 | * | |
32 | * Here we handle the processing of the low-level hw descriptors | |
33 | * that hw reads and writes via DMA for each TX and RX attempt (that means | |
34 | * we can also have descriptors for failed TX/RX tries). We have two kind of | |
35 | * descriptors for RX and TX, control descriptors tell the hw how to send or | |
36 | * receive a packet where to read/write it from/to etc and status descriptors | |
37 | * that contain information about how the packet was sent or received (errors | |
38 | * included). | |
39 | * | |
40 | * Descriptor format is not exactly the same for each MAC chip version so we | |
41 | * have function pointers on &struct ath5k_hw we initialize at runtime based on | |
42 | * the chip used. | |
43 | */ | |
44 | ||
45 | ||
9320b5c4 NK |
46 | /************************\ |
47 | * TX Control descriptors * | |
48 | \************************/ | |
c6e387a2 | 49 | |
c47faa36 NK |
50 | /** |
51 | * ath5k_hw_setup_2word_tx_desc() - Initialize a 2-word tx control descriptor | |
52 | * @ah: The &struct ath5k_hw | |
53 | * @desc: The &struct ath5k_desc | |
54 | * @pkt_len: Frame length in bytes | |
55 | * @hdr_len: Header length in bytes (only used on AR5210) | |
56 | * @padsize: Any padding we've added to the frame length | |
57 | * @type: One of enum ath5k_pkt_type | |
58 | * @tx_power: Tx power in 0.5dB steps | |
59 | * @tx_rate0: HW idx for transmission rate | |
60 | * @tx_tries0: Max number of retransmissions | |
61 | * @key_index: Index on key table to use for encryption | |
62 | * @antenna_mode: Which antenna to use (0 for auto) | |
63 | * @flags: One of AR5K_TXDESC_* flags (desc.h) | |
64 | * @rtscts_rate: HW idx for RTS/CTS transmission rate | |
65 | * @rtscts_duration: What to put on duration field on the header of RTS/CTS | |
66 | * | |
67 | * Internal function to initialize a 2-Word TX control descriptor | |
68 | * found on AR5210 and AR5211 MACs chips. | |
69 | * | |
70 | * Returns 0 on success or -EINVAL on false input | |
c6e387a2 NK |
71 | */ |
72 | static int | |
c47faa36 NK |
73 | ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *ah, |
74 | struct ath5k_desc *desc, | |
75 | unsigned int pkt_len, unsigned int hdr_len, | |
76 | int padsize, | |
77 | enum ath5k_pkt_type type, | |
78 | unsigned int tx_power, | |
79 | unsigned int tx_rate0, unsigned int tx_tries0, | |
80 | unsigned int key_index, | |
81 | unsigned int antenna_mode, | |
82 | unsigned int flags, | |
83 | unsigned int rtscts_rate, unsigned int rtscts_duration) | |
c6e387a2 NK |
84 | { |
85 | u32 frame_type; | |
86 | struct ath5k_hw_2w_tx_ctl *tx_ctl; | |
87 | unsigned int frame_len; | |
88 | ||
89 | tx_ctl = &desc->ud.ds_tx5210.tx_ctl; | |
90 | ||
91 | /* | |
92 | * Validate input | |
93 | * - Zero retries don't make sense. | |
25985edc | 94 | * - A zero rate will put the HW into a mode where it continuously sends |
c6e387a2 NK |
95 | * noise on the channel, so it is important to avoid this. |
96 | */ | |
97 | if (unlikely(tx_tries0 == 0)) { | |
e0d687bd | 98 | ATH5K_ERR(ah, "zero retries\n"); |
c6e387a2 NK |
99 | WARN_ON(1); |
100 | return -EINVAL; | |
101 | } | |
102 | if (unlikely(tx_rate0 == 0)) { | |
e0d687bd | 103 | ATH5K_ERR(ah, "zero rate\n"); |
c6e387a2 NK |
104 | WARN_ON(1); |
105 | return -EINVAL; | |
106 | } | |
107 | ||
108 | /* Clear descriptor */ | |
109 | memset(&desc->ud.ds_tx5210, 0, sizeof(struct ath5k_hw_5210_tx_desc)); | |
110 | ||
111 | /* Setup control descriptor */ | |
112 | ||
113 | /* Verify and set frame length */ | |
114 | ||
115 | /* remove padding we might have added before */ | |
8127fbdc | 116 | frame_len = pkt_len - padsize + FCS_LEN; |
c6e387a2 NK |
117 | |
118 | if (frame_len & ~AR5K_2W_TX_DESC_CTL0_FRAME_LEN) | |
119 | return -EINVAL; | |
120 | ||
121 | tx_ctl->tx_control_0 = frame_len & AR5K_2W_TX_DESC_CTL0_FRAME_LEN; | |
122 | ||
123 | /* Verify and set buffer length */ | |
124 | ||
125 | /* NB: beacon's BufLen must be a multiple of 4 bytes */ | |
126 | if (type == AR5K_PKT_TYPE_BEACON) | |
127 | pkt_len = roundup(pkt_len, 4); | |
128 | ||
129 | if (pkt_len & ~AR5K_2W_TX_DESC_CTL1_BUF_LEN) | |
130 | return -EINVAL; | |
131 | ||
132 | tx_ctl->tx_control_1 = pkt_len & AR5K_2W_TX_DESC_CTL1_BUF_LEN; | |
133 | ||
134 | /* | |
1884a367 | 135 | * Verify and set header length (only 5210) |
c6e387a2 NK |
136 | */ |
137 | if (ah->ah_version == AR5K_AR5210) { | |
03417bc6 | 138 | if (hdr_len & ~AR5K_2W_TX_DESC_CTL0_HEADER_LEN_5210) |
c6e387a2 NK |
139 | return -EINVAL; |
140 | tx_ctl->tx_control_0 |= | |
03417bc6 | 141 | AR5K_REG_SM(hdr_len, AR5K_2W_TX_DESC_CTL0_HEADER_LEN_5210); |
c6e387a2 NK |
142 | } |
143 | ||
8127fbdc | 144 | /*Differences between 5210-5211*/ |
c6e387a2 NK |
145 | if (ah->ah_version == AR5K_AR5210) { |
146 | switch (type) { | |
147 | case AR5K_PKT_TYPE_BEACON: | |
148 | case AR5K_PKT_TYPE_PROBE_RESP: | |
149 | frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY; | |
3ffca4fc | 150 | break; |
c6e387a2 NK |
151 | case AR5K_PKT_TYPE_PIFS: |
152 | frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS; | |
3ffca4fc | 153 | break; |
c6e387a2 | 154 | default: |
2237e928 | 155 | frame_type = type; |
3ffca4fc | 156 | break; |
c6e387a2 NK |
157 | } |
158 | ||
159 | tx_ctl->tx_control_0 |= | |
03417bc6 | 160 | AR5K_REG_SM(frame_type, AR5K_2W_TX_DESC_CTL0_FRAME_TYPE_5210) | |
c6e387a2 NK |
161 | AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE); |
162 | ||
163 | } else { | |
164 | tx_ctl->tx_control_0 |= | |
165 | AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE) | | |
166 | AR5K_REG_SM(antenna_mode, | |
167 | AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT); | |
168 | tx_ctl->tx_control_1 |= | |
03417bc6 | 169 | AR5K_REG_SM(type, AR5K_2W_TX_DESC_CTL1_FRAME_TYPE_5211); |
c6e387a2 | 170 | } |
1884a367 | 171 | |
c6e387a2 NK |
172 | #define _TX_FLAGS(_c, _flag) \ |
173 | if (flags & AR5K_TXDESC_##_flag) { \ | |
174 | tx_ctl->tx_control_##_c |= \ | |
175 | AR5K_2W_TX_DESC_CTL##_c##_##_flag; \ | |
176 | } | |
1884a367 BR |
177 | #define _TX_FLAGS_5211(_c, _flag) \ |
178 | if (flags & AR5K_TXDESC_##_flag) { \ | |
179 | tx_ctl->tx_control_##_c |= \ | |
180 | AR5K_2W_TX_DESC_CTL##_c##_##_flag##_5211; \ | |
181 | } | |
c6e387a2 | 182 | _TX_FLAGS(0, CLRDMASK); |
c6e387a2 NK |
183 | _TX_FLAGS(0, INTREQ); |
184 | _TX_FLAGS(0, RTSENA); | |
1884a367 BR |
185 | |
186 | if (ah->ah_version == AR5K_AR5211) { | |
187 | _TX_FLAGS_5211(0, VEOL); | |
188 | _TX_FLAGS_5211(1, NOACK); | |
189 | } | |
c6e387a2 NK |
190 | |
191 | #undef _TX_FLAGS | |
1884a367 | 192 | #undef _TX_FLAGS_5211 |
c6e387a2 NK |
193 | |
194 | /* | |
195 | * WEP crap | |
196 | */ | |
197 | if (key_index != AR5K_TXKEYIX_INVALID) { | |
198 | tx_ctl->tx_control_0 |= | |
199 | AR5K_2W_TX_DESC_CTL0_ENCRYPT_KEY_VALID; | |
200 | tx_ctl->tx_control_1 |= | |
201 | AR5K_REG_SM(key_index, | |
03417bc6 | 202 | AR5K_2W_TX_DESC_CTL1_ENC_KEY_IDX); |
c6e387a2 NK |
203 | } |
204 | ||
205 | /* | |
206 | * RTS/CTS Duration [5210 ?] | |
207 | */ | |
208 | if ((ah->ah_version == AR5K_AR5210) && | |
209 | (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA))) | |
210 | tx_ctl->tx_control_1 |= rtscts_duration & | |
03417bc6 | 211 | AR5K_2W_TX_DESC_CTL1_RTS_DURATION_5210; |
c6e387a2 NK |
212 | |
213 | return 0; | |
214 | } | |
215 | ||
c47faa36 NK |
216 | /** |
217 | * ath5k_hw_setup_4word_tx_desc() - Initialize a 4-word tx control descriptor | |
218 | * @ah: The &struct ath5k_hw | |
219 | * @desc: The &struct ath5k_desc | |
220 | * @pkt_len: Frame length in bytes | |
221 | * @hdr_len: Header length in bytes (only used on AR5210) | |
222 | * @padsize: Any padding we've added to the frame length | |
223 | * @type: One of enum ath5k_pkt_type | |
224 | * @tx_power: Tx power in 0.5dB steps | |
225 | * @tx_rate0: HW idx for transmission rate | |
226 | * @tx_tries0: Max number of retransmissions | |
227 | * @key_index: Index on key table to use for encryption | |
228 | * @antenna_mode: Which antenna to use (0 for auto) | |
229 | * @flags: One of AR5K_TXDESC_* flags (desc.h) | |
230 | * @rtscts_rate: HW idx for RTS/CTS transmission rate | |
231 | * @rtscts_duration: What to put on duration field on the header of RTS/CTS | |
232 | * | |
233 | * Internal function to initialize a 4-Word TX control descriptor | |
234 | * found on AR5212 and later MACs chips. | |
235 | * | |
236 | * Returns 0 on success or -EINVAL on false input | |
c6e387a2 | 237 | */ |
c47faa36 NK |
238 | static int |
239 | ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *ah, | |
240 | struct ath5k_desc *desc, | |
241 | unsigned int pkt_len, unsigned int hdr_len, | |
242 | int padsize, | |
243 | enum ath5k_pkt_type type, | |
244 | unsigned int tx_power, | |
245 | unsigned int tx_rate0, unsigned int tx_tries0, | |
246 | unsigned int key_index, | |
247 | unsigned int antenna_mode, | |
248 | unsigned int flags, | |
249 | unsigned int rtscts_rate, unsigned int rtscts_duration) | |
c6e387a2 NK |
250 | { |
251 | struct ath5k_hw_4w_tx_ctl *tx_ctl; | |
252 | unsigned int frame_len; | |
253 | ||
8962d871 JL |
254 | /* |
255 | * Use local variables for these to reduce load/store access on | |
256 | * uncached memory | |
257 | */ | |
c5e0a88a | 258 | u32 txctl0 = 0, txctl1 = 0, txctl2 = 0, txctl3 = 0; |
c6e387a2 | 259 | |
c6e387a2 NK |
260 | tx_ctl = &desc->ud.ds_tx5212.tx_ctl; |
261 | ||
262 | /* | |
263 | * Validate input | |
264 | * - Zero retries don't make sense. | |
25985edc | 265 | * - A zero rate will put the HW into a mode where it continuously sends |
c6e387a2 NK |
266 | * noise on the channel, so it is important to avoid this. |
267 | */ | |
268 | if (unlikely(tx_tries0 == 0)) { | |
e0d687bd | 269 | ATH5K_ERR(ah, "zero retries\n"); |
c6e387a2 NK |
270 | WARN_ON(1); |
271 | return -EINVAL; | |
272 | } | |
273 | if (unlikely(tx_rate0 == 0)) { | |
e0d687bd | 274 | ATH5K_ERR(ah, "zero rate\n"); |
c6e387a2 NK |
275 | WARN_ON(1); |
276 | return -EINVAL; | |
277 | } | |
278 | ||
8f655dde NK |
279 | tx_power += ah->ah_txpower.txp_offset; |
280 | if (tx_power > AR5K_TUNE_MAX_TXPOWER) | |
281 | tx_power = AR5K_TUNE_MAX_TXPOWER; | |
282 | ||
8962d871 | 283 | /* Clear descriptor status area */ |
c5e0a88a FF |
284 | memset(&desc->ud.ds_tx5212.tx_stat, 0, |
285 | sizeof(desc->ud.ds_tx5212.tx_stat)); | |
c6e387a2 NK |
286 | |
287 | /* Setup control descriptor */ | |
288 | ||
289 | /* Verify and set frame length */ | |
290 | ||
291 | /* remove padding we might have added before */ | |
8127fbdc | 292 | frame_len = pkt_len - padsize + FCS_LEN; |
c6e387a2 NK |
293 | |
294 | if (frame_len & ~AR5K_4W_TX_DESC_CTL0_FRAME_LEN) | |
295 | return -EINVAL; | |
296 | ||
c5e0a88a | 297 | txctl0 = frame_len & AR5K_4W_TX_DESC_CTL0_FRAME_LEN; |
c6e387a2 NK |
298 | |
299 | /* Verify and set buffer length */ | |
300 | ||
301 | /* NB: beacon's BufLen must be a multiple of 4 bytes */ | |
302 | if (type == AR5K_PKT_TYPE_BEACON) | |
303 | pkt_len = roundup(pkt_len, 4); | |
304 | ||
305 | if (pkt_len & ~AR5K_4W_TX_DESC_CTL1_BUF_LEN) | |
306 | return -EINVAL; | |
307 | ||
c5e0a88a | 308 | txctl1 = pkt_len & AR5K_4W_TX_DESC_CTL1_BUF_LEN; |
c6e387a2 | 309 | |
c5e0a88a FF |
310 | txctl0 |= AR5K_REG_SM(tx_power, AR5K_4W_TX_DESC_CTL0_XMIT_POWER) | |
311 | AR5K_REG_SM(antenna_mode, AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT); | |
312 | txctl1 |= AR5K_REG_SM(type, AR5K_4W_TX_DESC_CTL1_FRAME_TYPE); | |
313 | txctl2 = AR5K_REG_SM(tx_tries0, AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0); | |
314 | txctl3 = tx_rate0 & AR5K_4W_TX_DESC_CTL3_XMIT_RATE0; | |
c6e387a2 NK |
315 | |
316 | #define _TX_FLAGS(_c, _flag) \ | |
317 | if (flags & AR5K_TXDESC_##_flag) { \ | |
c5e0a88a | 318 | txctl##_c |= AR5K_4W_TX_DESC_CTL##_c##_##_flag; \ |
c6e387a2 NK |
319 | } |
320 | ||
321 | _TX_FLAGS(0, CLRDMASK); | |
322 | _TX_FLAGS(0, VEOL); | |
323 | _TX_FLAGS(0, INTREQ); | |
324 | _TX_FLAGS(0, RTSENA); | |
325 | _TX_FLAGS(0, CTSENA); | |
326 | _TX_FLAGS(1, NOACK); | |
327 | ||
328 | #undef _TX_FLAGS | |
329 | ||
330 | /* | |
331 | * WEP crap | |
332 | */ | |
333 | if (key_index != AR5K_TXKEYIX_INVALID) { | |
c5e0a88a FF |
334 | txctl0 |= AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID; |
335 | txctl1 |= AR5K_REG_SM(key_index, | |
03417bc6 | 336 | AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_IDX); |
c6e387a2 NK |
337 | } |
338 | ||
339 | /* | |
340 | * RTS/CTS | |
341 | */ | |
342 | if (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)) { | |
343 | if ((flags & AR5K_TXDESC_RTSENA) && | |
344 | (flags & AR5K_TXDESC_CTSENA)) | |
345 | return -EINVAL; | |
c5e0a88a FF |
346 | txctl2 |= rtscts_duration & AR5K_4W_TX_DESC_CTL2_RTS_DURATION; |
347 | txctl3 |= AR5K_REG_SM(rtscts_rate, | |
c6e387a2 NK |
348 | AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE); |
349 | } | |
350 | ||
c5e0a88a FF |
351 | tx_ctl->tx_control_0 = txctl0; |
352 | tx_ctl->tx_control_1 = txctl1; | |
353 | tx_ctl->tx_control_2 = txctl2; | |
354 | tx_ctl->tx_control_3 = txctl3; | |
355 | ||
c6e387a2 NK |
356 | return 0; |
357 | } | |
358 | ||
c47faa36 NK |
359 | /** |
360 | * ath5k_hw_setup_mrr_tx_desc() - Initialize an MRR tx control descriptor | |
361 | * @ah: The &struct ath5k_hw | |
362 | * @desc: The &struct ath5k_desc | |
363 | * @tx_rate1: HW idx for rate used on transmission series 1 | |
364 | * @tx_tries1: Max number of retransmissions for transmission series 1 | |
365 | * @tx_rate2: HW idx for rate used on transmission series 2 | |
366 | * @tx_tries2: Max number of retransmissions for transmission series 2 | |
367 | * @tx_rate3: HW idx for rate used on transmission series 3 | |
368 | * @tx_tries3: Max number of retransmissions for transmission series 3 | |
369 | * | |
370 | * Multi rate retry (MRR) tx control descriptors are available only on AR5212 | |
371 | * MACs, they are part of the normal 4-word tx control descriptor (see above) | |
372 | * but we handle them through a separate function for better abstraction. | |
373 | * | |
374 | * Returns 0 on success or -EINVAL on invalid input | |
c6e387a2 | 375 | */ |
a6668193 | 376 | int |
c47faa36 NK |
377 | ath5k_hw_setup_mrr_tx_desc(struct ath5k_hw *ah, |
378 | struct ath5k_desc *desc, | |
379 | u_int tx_rate1, u_int tx_tries1, | |
380 | u_int tx_rate2, u_int tx_tries2, | |
381 | u_int tx_rate3, u_int tx_tries3) | |
c6e387a2 NK |
382 | { |
383 | struct ath5k_hw_4w_tx_ctl *tx_ctl; | |
384 | ||
a6668193 BR |
385 | /* no mrr support for cards older than 5212 */ |
386 | if (ah->ah_version < AR5K_AR5212) | |
387 | return 0; | |
388 | ||
c6e387a2 NK |
389 | /* |
390 | * Rates can be 0 as long as the retry count is 0 too. | |
391 | * A zero rate and nonzero retry count will put the HW into a mode where | |
25985edc | 392 | * it continuously sends noise on the channel, so it is important to |
c6e387a2 NK |
393 | * avoid this. |
394 | */ | |
395 | if (unlikely((tx_rate1 == 0 && tx_tries1 != 0) || | |
396 | (tx_rate2 == 0 && tx_tries2 != 0) || | |
397 | (tx_rate3 == 0 && tx_tries3 != 0))) { | |
e0d687bd | 398 | ATH5K_ERR(ah, "zero rate\n"); |
c6e387a2 NK |
399 | WARN_ON(1); |
400 | return -EINVAL; | |
401 | } | |
402 | ||
403 | if (ah->ah_version == AR5K_AR5212) { | |
404 | tx_ctl = &desc->ud.ds_tx5212.tx_ctl; | |
405 | ||
406 | #define _XTX_TRIES(_n) \ | |
407 | if (tx_tries##_n) { \ | |
408 | tx_ctl->tx_control_2 |= \ | |
409 | AR5K_REG_SM(tx_tries##_n, \ | |
410 | AR5K_4W_TX_DESC_CTL2_XMIT_TRIES##_n); \ | |
411 | tx_ctl->tx_control_3 |= \ | |
412 | AR5K_REG_SM(tx_rate##_n, \ | |
413 | AR5K_4W_TX_DESC_CTL3_XMIT_RATE##_n); \ | |
414 | } | |
415 | ||
416 | _XTX_TRIES(1); | |
417 | _XTX_TRIES(2); | |
418 | _XTX_TRIES(3); | |
419 | ||
420 | #undef _XTX_TRIES | |
421 | ||
422 | return 1; | |
423 | } | |
424 | ||
425 | return 0; | |
426 | } | |
427 | ||
9320b5c4 NK |
428 | |
429 | /***********************\ | |
430 | * TX Status descriptors * | |
431 | \***********************/ | |
432 | ||
c47faa36 NK |
433 | /** |
434 | * ath5k_hw_proc_2word_tx_status() - Process a tx status descriptor on 5210/1 | |
435 | * @ah: The &struct ath5k_hw | |
436 | * @desc: The &struct ath5k_desc | |
437 | * @ts: The &struct ath5k_tx_status | |
c6e387a2 | 438 | */ |
c47faa36 NK |
439 | static int |
440 | ath5k_hw_proc_2word_tx_status(struct ath5k_hw *ah, | |
441 | struct ath5k_desc *desc, | |
442 | struct ath5k_tx_status *ts) | |
c6e387a2 NK |
443 | { |
444 | struct ath5k_hw_2w_tx_ctl *tx_ctl; | |
445 | struct ath5k_hw_tx_status *tx_status; | |
446 | ||
c6e387a2 NK |
447 | tx_ctl = &desc->ud.ds_tx5210.tx_ctl; |
448 | tx_status = &desc->ud.ds_tx5210.tx_stat; | |
449 | ||
450 | /* No frame has been send or error */ | |
451 | if (unlikely((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0)) | |
452 | return -EINPROGRESS; | |
453 | ||
454 | /* | |
455 | * Get descriptor status | |
456 | */ | |
457 | ts->ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0, | |
458 | AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP); | |
459 | ts->ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0, | |
460 | AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT); | |
ed895085 | 461 | ts->ts_final_retry = AR5K_REG_MS(tx_status->tx_status_0, |
c6e387a2 NK |
462 | AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT); |
463 | /*TODO: ts->ts_virtcol + test*/ | |
464 | ts->ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1, | |
465 | AR5K_DESC_TX_STATUS1_SEQ_NUM); | |
466 | ts->ts_rssi = AR5K_REG_MS(tx_status->tx_status_1, | |
467 | AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH); | |
468 | ts->ts_antenna = 1; | |
469 | ts->ts_status = 0; | |
2f7fe870 | 470 | ts->ts_final_idx = 0; |
c6e387a2 NK |
471 | |
472 | if (!(tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK)) { | |
473 | if (tx_status->tx_status_0 & | |
474 | AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES) | |
475 | ts->ts_status |= AR5K_TXERR_XRETRY; | |
476 | ||
477 | if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN) | |
478 | ts->ts_status |= AR5K_TXERR_FIFO; | |
479 | ||
480 | if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED) | |
481 | ts->ts_status |= AR5K_TXERR_FILT; | |
482 | } | |
483 | ||
484 | return 0; | |
485 | } | |
486 | ||
c47faa36 NK |
487 | /** |
488 | * ath5k_hw_proc_4word_tx_status() - Process a tx status descriptor on 5212 | |
489 | * @ah: The &struct ath5k_hw | |
490 | * @desc: The &struct ath5k_desc | |
491 | * @ts: The &struct ath5k_tx_status | |
c6e387a2 | 492 | */ |
c47faa36 NK |
493 | static int |
494 | ath5k_hw_proc_4word_tx_status(struct ath5k_hw *ah, | |
495 | struct ath5k_desc *desc, | |
496 | struct ath5k_tx_status *ts) | |
c6e387a2 NK |
497 | { |
498 | struct ath5k_hw_4w_tx_ctl *tx_ctl; | |
499 | struct ath5k_hw_tx_status *tx_status; | |
ed895085 | 500 | u32 txstat0, txstat1; |
c6e387a2 | 501 | |
c6e387a2 NK |
502 | tx_ctl = &desc->ud.ds_tx5212.tx_ctl; |
503 | tx_status = &desc->ud.ds_tx5212.tx_stat; | |
504 | ||
b161b89f FF |
505 | txstat1 = ACCESS_ONCE(tx_status->tx_status_1); |
506 | ||
c6e387a2 | 507 | /* No frame has been send or error */ |
b161b89f | 508 | if (unlikely(!(txstat1 & AR5K_DESC_TX_STATUS1_DONE))) |
c6e387a2 NK |
509 | return -EINPROGRESS; |
510 | ||
b161b89f | 511 | txstat0 = ACCESS_ONCE(tx_status->tx_status_0); |
b161b89f | 512 | |
c6e387a2 NK |
513 | /* |
514 | * Get descriptor status | |
515 | */ | |
b161b89f | 516 | ts->ts_tstamp = AR5K_REG_MS(txstat0, |
c6e387a2 | 517 | AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP); |
b161b89f | 518 | ts->ts_shortretry = AR5K_REG_MS(txstat0, |
c6e387a2 | 519 | AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT); |
ed895085 | 520 | ts->ts_final_retry = AR5K_REG_MS(txstat0, |
c6e387a2 | 521 | AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT); |
b161b89f | 522 | ts->ts_seqnum = AR5K_REG_MS(txstat1, |
c6e387a2 | 523 | AR5K_DESC_TX_STATUS1_SEQ_NUM); |
b161b89f | 524 | ts->ts_rssi = AR5K_REG_MS(txstat1, |
c6e387a2 | 525 | AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH); |
b161b89f | 526 | ts->ts_antenna = (txstat1 & |
03417bc6 | 527 | AR5K_DESC_TX_STATUS1_XMIT_ANTENNA_5212) ? 2 : 1; |
c6e387a2 NK |
528 | ts->ts_status = 0; |
529 | ||
b161b89f | 530 | ts->ts_final_idx = AR5K_REG_MS(txstat1, |
03417bc6 | 531 | AR5K_DESC_TX_STATUS1_FINAL_TS_IX_5212); |
2f7fe870 | 532 | |
c6e387a2 | 533 | /* TX error */ |
b161b89f FF |
534 | if (!(txstat0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK)) { |
535 | if (txstat0 & AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES) | |
c6e387a2 NK |
536 | ts->ts_status |= AR5K_TXERR_XRETRY; |
537 | ||
b161b89f | 538 | if (txstat0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN) |
c6e387a2 NK |
539 | ts->ts_status |= AR5K_TXERR_FIFO; |
540 | ||
b161b89f | 541 | if (txstat0 & AR5K_DESC_TX_STATUS0_FILTERED) |
c6e387a2 NK |
542 | ts->ts_status |= AR5K_TXERR_FILT; |
543 | } | |
544 | ||
545 | return 0; | |
546 | } | |
547 | ||
9320b5c4 NK |
548 | |
549 | /****************\ | |
550 | * RX Descriptors * | |
551 | \****************/ | |
c6e387a2 | 552 | |
c47faa36 NK |
553 | /** |
554 | * ath5k_hw_setup_rx_desc() - Initialize an rx control descriptor | |
555 | * @ah: The &struct ath5k_hw | |
556 | * @desc: The &struct ath5k_desc | |
557 | * @size: RX buffer length in bytes | |
558 | * @flags: One of AR5K_RXDESC_* flags | |
c6e387a2 | 559 | */ |
c47faa36 NK |
560 | int |
561 | ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, | |
562 | struct ath5k_desc *desc, | |
563 | u32 size, unsigned int flags) | |
c6e387a2 NK |
564 | { |
565 | struct ath5k_hw_rx_ctl *rx_ctl; | |
566 | ||
c6e387a2 NK |
567 | rx_ctl = &desc->ud.ds_rx.rx_ctl; |
568 | ||
569 | /* | |
570 | * Clear the descriptor | |
571 | * If we don't clean the status descriptor, | |
572 | * while scanning we get too many results, | |
573 | * most of them virtual, after some secs | |
574 | * of scanning system hangs. M.F. | |
575 | */ | |
576 | memset(&desc->ud.ds_rx, 0, sizeof(struct ath5k_hw_all_rx_desc)); | |
577 | ||
8786123b BR |
578 | if (unlikely(size & ~AR5K_DESC_RX_CTL1_BUF_LEN)) |
579 | return -EINVAL; | |
580 | ||
c6e387a2 NK |
581 | /* Setup descriptor */ |
582 | rx_ctl->rx_control_1 = size & AR5K_DESC_RX_CTL1_BUF_LEN; | |
c6e387a2 NK |
583 | |
584 | if (flags & AR5K_RXDESC_INTREQ) | |
585 | rx_ctl->rx_control_1 |= AR5K_DESC_RX_CTL1_INTREQ; | |
586 | ||
587 | return 0; | |
588 | } | |
589 | ||
c47faa36 NK |
590 | /** |
591 | * ath5k_hw_proc_5210_rx_status() - Process the rx status descriptor on 5210/1 | |
592 | * @ah: The &struct ath5k_hw | |
593 | * @desc: The &struct ath5k_desc | |
594 | * @rs: The &struct ath5k_rx_status | |
595 | * | |
596 | * Internal function used to process an RX status descriptor | |
597 | * on AR5210/5211 MAC. | |
598 | * | |
599 | * Returns 0 on success or -EINPROGRESS in case we haven't received the who;e | |
600 | * frame yet. | |
c6e387a2 | 601 | */ |
c47faa36 NK |
602 | static int |
603 | ath5k_hw_proc_5210_rx_status(struct ath5k_hw *ah, | |
604 | struct ath5k_desc *desc, | |
605 | struct ath5k_rx_status *rs) | |
c6e387a2 NK |
606 | { |
607 | struct ath5k_hw_rx_status *rx_status; | |
608 | ||
62412a8f | 609 | rx_status = &desc->ud.ds_rx.rx_stat; |
c6e387a2 NK |
610 | |
611 | /* No frame received / not ready */ | |
612 | if (unlikely(!(rx_status->rx_status_1 & | |
8786123b | 613 | AR5K_5210_RX_DESC_STATUS1_DONE))) |
c6e387a2 NK |
614 | return -EINPROGRESS; |
615 | ||
8786123b BR |
616 | memset(rs, 0, sizeof(struct ath5k_rx_status)); |
617 | ||
c6e387a2 NK |
618 | /* |
619 | * Frame receive status | |
620 | */ | |
621 | rs->rs_datalen = rx_status->rx_status_0 & | |
622 | AR5K_5210_RX_DESC_STATUS0_DATA_LEN; | |
623 | rs->rs_rssi = AR5K_REG_MS(rx_status->rx_status_0, | |
624 | AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL); | |
625 | rs->rs_rate = AR5K_REG_MS(rx_status->rx_status_0, | |
626 | AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE); | |
c7930339 BC |
627 | rs->rs_more = !!(rx_status->rx_status_0 & |
628 | AR5K_5210_RX_DESC_STATUS0_MORE); | |
8786123b BR |
629 | /* TODO: this timestamp is 13 bit, later on we assume 15 bit! |
630 | * also the HAL code for 5210 says the timestamp is bits [10..22] of the | |
631 | * TSF, and extends the timestamp here to 15 bit. | |
632 | * we need to check on 5210... | |
633 | */ | |
c6e387a2 NK |
634 | rs->rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1, |
635 | AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP); | |
1884a367 BR |
636 | |
637 | if (ah->ah_version == AR5K_AR5211) | |
638 | rs->rs_antenna = AR5K_REG_MS(rx_status->rx_status_0, | |
639 | AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANT_5211); | |
640 | else | |
641 | rs->rs_antenna = (rx_status->rx_status_0 & | |
642 | AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANT_5210) | |
643 | ? 2 : 1; | |
644 | ||
c6e387a2 NK |
645 | /* |
646 | * Key table status | |
647 | */ | |
648 | if (rx_status->rx_status_1 & AR5K_5210_RX_DESC_STATUS1_KEY_INDEX_VALID) | |
649 | rs->rs_keyix = AR5K_REG_MS(rx_status->rx_status_1, | |
650 | AR5K_5210_RX_DESC_STATUS1_KEY_INDEX); | |
651 | else | |
652 | rs->rs_keyix = AR5K_RXKEYIX_INVALID; | |
653 | ||
654 | /* | |
655 | * Receive/descriptor errors | |
656 | */ | |
657 | if (!(rx_status->rx_status_1 & | |
8786123b | 658 | AR5K_5210_RX_DESC_STATUS1_FRAME_RECEIVE_OK)) { |
c6e387a2 NK |
659 | if (rx_status->rx_status_1 & |
660 | AR5K_5210_RX_DESC_STATUS1_CRC_ERROR) | |
661 | rs->rs_status |= AR5K_RXERR_CRC; | |
662 | ||
8786123b BR |
663 | /* only on 5210 */ |
664 | if ((ah->ah_version == AR5K_AR5210) && | |
665 | (rx_status->rx_status_1 & | |
666 | AR5K_5210_RX_DESC_STATUS1_FIFO_OVERRUN_5210)) | |
c6e387a2 NK |
667 | rs->rs_status |= AR5K_RXERR_FIFO; |
668 | ||
669 | if (rx_status->rx_status_1 & | |
670 | AR5K_5210_RX_DESC_STATUS1_PHY_ERROR) { | |
671 | rs->rs_status |= AR5K_RXERR_PHY; | |
8786123b | 672 | rs->rs_phyerr = AR5K_REG_MS(rx_status->rx_status_1, |
c6e387a2 NK |
673 | AR5K_5210_RX_DESC_STATUS1_PHY_ERROR); |
674 | } | |
675 | ||
676 | if (rx_status->rx_status_1 & | |
677 | AR5K_5210_RX_DESC_STATUS1_DECRYPT_CRC_ERROR) | |
678 | rs->rs_status |= AR5K_RXERR_DECRYPT; | |
679 | } | |
680 | ||
681 | return 0; | |
682 | } | |
683 | ||
c47faa36 NK |
684 | /** |
685 | * ath5k_hw_proc_5212_rx_status() - Process the rx status descriptor on 5212 | |
686 | * @ah: The &struct ath5k_hw | |
687 | * @desc: The &struct ath5k_desc | |
688 | * @rs: The &struct ath5k_rx_status | |
689 | * | |
690 | * Internal function used to process an RX status descriptor | |
691 | * on AR5212 and later MAC. | |
692 | * | |
693 | * Returns 0 on success or -EINPROGRESS in case we haven't received the who;e | |
694 | * frame yet. | |
c6e387a2 | 695 | */ |
c47faa36 NK |
696 | static int |
697 | ath5k_hw_proc_5212_rx_status(struct ath5k_hw *ah, | |
698 | struct ath5k_desc *desc, | |
699 | struct ath5k_rx_status *rs) | |
c6e387a2 NK |
700 | { |
701 | struct ath5k_hw_rx_status *rx_status; | |
b2fd97d0 | 702 | u32 rxstat0, rxstat1; |
c6e387a2 | 703 | |
62412a8f | 704 | rx_status = &desc->ud.ds_rx.rx_stat; |
b2fd97d0 | 705 | rxstat1 = ACCESS_ONCE(rx_status->rx_status_1); |
c6e387a2 NK |
706 | |
707 | /* No frame received / not ready */ | |
b2fd97d0 | 708 | if (unlikely(!(rxstat1 & AR5K_5212_RX_DESC_STATUS1_DONE))) |
c6e387a2 NK |
709 | return -EINPROGRESS; |
710 | ||
8786123b | 711 | memset(rs, 0, sizeof(struct ath5k_rx_status)); |
b2fd97d0 | 712 | rxstat0 = ACCESS_ONCE(rx_status->rx_status_0); |
8786123b | 713 | |
c6e387a2 NK |
714 | /* |
715 | * Frame receive status | |
716 | */ | |
b2fd97d0 FF |
717 | rs->rs_datalen = rxstat0 & AR5K_5212_RX_DESC_STATUS0_DATA_LEN; |
718 | rs->rs_rssi = AR5K_REG_MS(rxstat0, | |
c6e387a2 | 719 | AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL); |
b2fd97d0 | 720 | rs->rs_rate = AR5K_REG_MS(rxstat0, |
c6e387a2 | 721 | AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE); |
b2fd97d0 | 722 | rs->rs_antenna = AR5K_REG_MS(rxstat0, |
c7930339 | 723 | AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA); |
b2fd97d0 FF |
724 | rs->rs_more = !!(rxstat0 & AR5K_5212_RX_DESC_STATUS0_MORE); |
725 | rs->rs_tstamp = AR5K_REG_MS(rxstat1, | |
c6e387a2 | 726 | AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP); |
c6e387a2 NK |
727 | |
728 | /* | |
729 | * Key table status | |
730 | */ | |
b2fd97d0 FF |
731 | if (rxstat1 & AR5K_5212_RX_DESC_STATUS1_KEY_INDEX_VALID) |
732 | rs->rs_keyix = AR5K_REG_MS(rxstat1, | |
2847109f | 733 | AR5K_5212_RX_DESC_STATUS1_KEY_INDEX); |
c6e387a2 NK |
734 | else |
735 | rs->rs_keyix = AR5K_RXKEYIX_INVALID; | |
736 | ||
737 | /* | |
738 | * Receive/descriptor errors | |
739 | */ | |
b2fd97d0 FF |
740 | if (!(rxstat1 & AR5K_5212_RX_DESC_STATUS1_FRAME_RECEIVE_OK)) { |
741 | if (rxstat1 & AR5K_5212_RX_DESC_STATUS1_CRC_ERROR) | |
c6e387a2 NK |
742 | rs->rs_status |= AR5K_RXERR_CRC; |
743 | ||
b2fd97d0 | 744 | if (rxstat1 & AR5K_5212_RX_DESC_STATUS1_PHY_ERROR) { |
c6e387a2 | 745 | rs->rs_status |= AR5K_RXERR_PHY; |
b2fd97d0 | 746 | rs->rs_phyerr = AR5K_REG_MS(rxstat1, |
62412a8f | 747 | AR5K_5212_RX_DESC_STATUS1_PHY_ERROR_CODE); |
6a0076e0 BR |
748 | if (!ah->ah_capabilities.cap_has_phyerr_counters) |
749 | ath5k_ani_phy_error_report(ah, rs->rs_phyerr); | |
c6e387a2 NK |
750 | } |
751 | ||
b2fd97d0 | 752 | if (rxstat1 & AR5K_5212_RX_DESC_STATUS1_DECRYPT_CRC_ERROR) |
c6e387a2 NK |
753 | rs->rs_status |= AR5K_RXERR_DECRYPT; |
754 | ||
b2fd97d0 | 755 | if (rxstat1 & AR5K_5212_RX_DESC_STATUS1_MIC_ERROR) |
c6e387a2 NK |
756 | rs->rs_status |= AR5K_RXERR_MIC; |
757 | } | |
c6e387a2 NK |
758 | return 0; |
759 | } | |
760 | ||
9320b5c4 NK |
761 | |
762 | /********\ | |
763 | * Attach * | |
764 | \********/ | |
765 | ||
c47faa36 NK |
766 | /** |
767 | * ath5k_hw_init_desc_functions() - Init function pointers inside ah | |
768 | * @ah: The &struct ath5k_hw | |
769 | * | |
770 | * Maps the internal descriptor functions to the function pointers on ah, used | |
771 | * from above. This is used as an abstraction layer to handle the various chips | |
772 | * the same way. | |
c6e387a2 | 773 | */ |
c47faa36 NK |
774 | int |
775 | ath5k_hw_init_desc_functions(struct ath5k_hw *ah) | |
c6e387a2 | 776 | { |
c6e387a2 | 777 | if (ah->ah_version == AR5K_AR5212) { |
c6e387a2 | 778 | ah->ah_setup_tx_desc = ath5k_hw_setup_4word_tx_desc; |
c6e387a2 | 779 | ah->ah_proc_tx_desc = ath5k_hw_proc_4word_tx_status; |
a6668193 BR |
780 | ah->ah_proc_rx_desc = ath5k_hw_proc_5212_rx_status; |
781 | } else if (ah->ah_version <= AR5K_AR5211) { | |
c6e387a2 | 782 | ah->ah_setup_tx_desc = ath5k_hw_setup_2word_tx_desc; |
c6e387a2 | 783 | ah->ah_proc_tx_desc = ath5k_hw_proc_2word_tx_status; |
c6e387a2 | 784 | ah->ah_proc_rx_desc = ath5k_hw_proc_5210_rx_status; |
a6668193 BR |
785 | } else |
786 | return -ENOTSUPP; | |
c6e387a2 NK |
787 | return 0; |
788 | } |