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1 | /* |
2 | * Copyright (c) 2008-2009 Atheros Communications Inc. | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #include <linux/nl80211.h> | |
18 | #include <linux/pci.h> | |
19 | #include <linux/pci-aspm.h> | |
20 | #include "../ath.h" | |
21 | #include "ath5k.h" | |
22 | #include "debug.h" | |
23 | #include "base.h" | |
24 | #include "reg.h" | |
25 | ||
26 | /* Known PCI ids */ | |
27 | static DEFINE_PCI_DEVICE_TABLE(ath5k_pci_id_table) = { | |
28 | { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */ | |
29 | { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */ | |
30 | { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/ | |
31 | { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */ | |
32 | { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */ | |
33 | { PCI_VDEVICE(3COM_2, 0x0013) }, /* 3com 5212 */ | |
34 | { PCI_VDEVICE(3COM, 0x0013) }, /* 3com 3CRDAG675 5212 */ | |
35 | { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */ | |
36 | { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 combatible */ | |
37 | { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 combatible */ | |
38 | { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 combatible */ | |
39 | { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 combatible */ | |
40 | { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 combatible */ | |
41 | { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 combatible */ | |
42 | { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */ | |
43 | { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */ | |
44 | { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */ | |
45 | { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */ | |
46 | { 0 } | |
47 | }; | |
b7ee1d01 | 48 | MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table); |
e5b046d8 FF |
49 | |
50 | /* return bus cachesize in 4B word units */ | |
51 | static void ath5k_pci_read_cachesize(struct ath_common *common, int *csz) | |
52 | { | |
53 | struct ath5k_softc *sc = (struct ath5k_softc *) common->priv; | |
54 | u8 u8tmp; | |
55 | ||
56 | pci_read_config_byte(sc->pdev, PCI_CACHE_LINE_SIZE, &u8tmp); | |
57 | *csz = (int)u8tmp; | |
58 | ||
59 | /* | |
25985edc | 60 | * This check was put in to avoid "unpleasant" consequences if |
e5b046d8 FF |
61 | * the bootrom has not fully initialized all PCI devices. |
62 | * Sometimes the cache line size register is not set | |
63 | */ | |
64 | ||
65 | if (*csz == 0) | |
66 | *csz = L1_CACHE_BYTES >> 2; /* Use the default size */ | |
67 | } | |
68 | ||
4aa5d783 FF |
69 | /* |
70 | * Read from eeprom | |
71 | */ | |
fda9b7af WD |
72 | static bool |
73 | ath5k_pci_eeprom_read(struct ath_common *common, u32 offset, u16 *data) | |
4aa5d783 FF |
74 | { |
75 | struct ath5k_hw *ah = (struct ath5k_hw *) common->ah; | |
76 | u32 status, timeout; | |
77 | ||
78 | /* | |
79 | * Initialize EEPROM access | |
80 | */ | |
81 | if (ah->ah_version == AR5K_AR5210) { | |
82 | AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE); | |
83 | (void)ath5k_hw_reg_read(ah, AR5K_EEPROM_BASE + (4 * offset)); | |
84 | } else { | |
85 | ath5k_hw_reg_write(ah, offset, AR5K_EEPROM_BASE); | |
86 | AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD, | |
87 | AR5K_EEPROM_CMD_READ); | |
88 | } | |
89 | ||
90 | for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) { | |
91 | status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS); | |
92 | if (status & AR5K_EEPROM_STAT_RDDONE) { | |
93 | if (status & AR5K_EEPROM_STAT_RDERR) | |
fda9b7af | 94 | return false; |
4aa5d783 FF |
95 | *data = (u16)(ath5k_hw_reg_read(ah, AR5K_EEPROM_DATA) & |
96 | 0xffff); | |
fda9b7af | 97 | return true; |
4aa5d783 FF |
98 | } |
99 | udelay(15); | |
100 | } | |
101 | ||
fda9b7af | 102 | return false; |
4aa5d783 FF |
103 | } |
104 | ||
e7aecd32 FF |
105 | int ath5k_hw_read_srev(struct ath5k_hw *ah) |
106 | { | |
107 | ah->ah_mac_srev = ath5k_hw_reg_read(ah, AR5K_SREV); | |
108 | return 0; | |
109 | } | |
110 | ||
e5b046d8 FF |
111 | /* Common ath_bus_opts structure */ |
112 | static const struct ath_bus_ops ath_pci_bus_ops = { | |
113 | .ath_bus_type = ATH_PCI, | |
114 | .read_cachesize = ath5k_pci_read_cachesize, | |
4aa5d783 | 115 | .eeprom_read = ath5k_pci_eeprom_read, |
e5b046d8 FF |
116 | }; |
117 | ||
118 | /********************\ | |
119 | * PCI Initialization * | |
120 | \********************/ | |
121 | ||
122 | static int __devinit | |
123 | ath5k_pci_probe(struct pci_dev *pdev, | |
124 | const struct pci_device_id *id) | |
125 | { | |
126 | void __iomem *mem; | |
127 | struct ath5k_softc *sc; | |
128 | struct ieee80211_hw *hw; | |
129 | int ret; | |
130 | u8 csz; | |
131 | ||
132 | /* | |
133 | * L0s needs to be disabled on all ath5k cards. | |
134 | * | |
135 | * For distributions shipping with CONFIG_PCIEASPM (this will be enabled | |
136 | * by default in the future in 2.6.36) this will also mean both L1 and | |
137 | * L0s will be disabled when a pre 1.1 PCIe device is detected. We do | |
138 | * know L1 works correctly even for all ath5k pre 1.1 PCIe devices | |
139 | * though but cannot currently undue the effect of a blacklist, for | |
140 | * details you can read pcie_aspm_sanity_check() and see how it adjusts | |
141 | * the device link capability. | |
142 | * | |
143 | * It may be possible in the future to implement some PCI API to allow | |
144 | * drivers to override blacklists for pre 1.1 PCIe but for now it is | |
145 | * best to accept that both L0s and L1 will be disabled completely for | |
146 | * distributions shipping with CONFIG_PCIEASPM rather than having this | |
147 | * issue present. Motivation for adding this new API will be to help | |
148 | * with power consumption for some of these devices. | |
149 | */ | |
150 | pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S); | |
151 | ||
152 | ret = pci_enable_device(pdev); | |
153 | if (ret) { | |
154 | dev_err(&pdev->dev, "can't enable device\n"); | |
155 | goto err; | |
156 | } | |
157 | ||
158 | /* XXX 32-bit addressing only */ | |
159 | ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
160 | if (ret) { | |
161 | dev_err(&pdev->dev, "32-bit DMA not available\n"); | |
162 | goto err_dis; | |
163 | } | |
164 | ||
165 | /* | |
166 | * Cache line size is used to size and align various | |
167 | * structures used to communicate with the hardware. | |
168 | */ | |
169 | pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz); | |
170 | if (csz == 0) { | |
171 | /* | |
172 | * Linux 2.4.18 (at least) writes the cache line size | |
173 | * register as a 16-bit wide register which is wrong. | |
174 | * We must have this setup properly for rx buffer | |
175 | * DMA to work so force a reasonable value here if it | |
176 | * comes up zero. | |
177 | */ | |
178 | csz = L1_CACHE_BYTES >> 2; | |
179 | pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz); | |
180 | } | |
181 | /* | |
182 | * The default setting of latency timer yields poor results, | |
183 | * set it to the value used by other systems. It may be worth | |
184 | * tweaking this setting more. | |
185 | */ | |
186 | pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8); | |
187 | ||
188 | /* Enable bus mastering */ | |
189 | pci_set_master(pdev); | |
190 | ||
191 | /* | |
192 | * Disable the RETRY_TIMEOUT register (0x41) to keep | |
193 | * PCI Tx retries from interfering with C3 CPU state. | |
194 | */ | |
195 | pci_write_config_byte(pdev, 0x41, 0); | |
196 | ||
197 | ret = pci_request_region(pdev, 0, "ath5k"); | |
198 | if (ret) { | |
199 | dev_err(&pdev->dev, "cannot reserve PCI memory region\n"); | |
200 | goto err_dis; | |
201 | } | |
202 | ||
203 | mem = pci_iomap(pdev, 0, 0); | |
204 | if (!mem) { | |
205 | dev_err(&pdev->dev, "cannot remap PCI memory region\n") ; | |
206 | ret = -EIO; | |
207 | goto err_reg; | |
208 | } | |
209 | ||
210 | /* | |
211 | * Allocate hw (mac80211 main struct) | |
212 | * and hw->priv (driver private data) | |
213 | */ | |
214 | hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops); | |
215 | if (hw == NULL) { | |
216 | dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n"); | |
217 | ret = -ENOMEM; | |
218 | goto err_map; | |
219 | } | |
220 | ||
221 | dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy)); | |
222 | ||
223 | sc = hw->priv; | |
224 | sc->hw = hw; | |
225 | sc->pdev = pdev; | |
226 | sc->dev = &pdev->dev; | |
227 | sc->irq = pdev->irq; | |
228 | sc->devid = id->device; | |
229 | sc->iobase = mem; /* So we can unmap it on detach */ | |
230 | ||
231 | /* Initialize */ | |
232 | ret = ath5k_init_softc(sc, &ath_pci_bus_ops); | |
233 | if (ret) | |
234 | goto err_free; | |
235 | ||
236 | /* Set private data */ | |
237 | pci_set_drvdata(pdev, hw); | |
238 | ||
239 | return 0; | |
240 | err_free: | |
241 | ieee80211_free_hw(hw); | |
242 | err_map: | |
243 | pci_iounmap(pdev, mem); | |
244 | err_reg: | |
245 | pci_release_region(pdev, 0); | |
246 | err_dis: | |
247 | pci_disable_device(pdev); | |
248 | err: | |
249 | return ret; | |
250 | } | |
251 | ||
252 | static void __devexit | |
253 | ath5k_pci_remove(struct pci_dev *pdev) | |
254 | { | |
255 | struct ieee80211_hw *hw = pci_get_drvdata(pdev); | |
256 | struct ath5k_softc *sc = hw->priv; | |
257 | ||
258 | ath5k_deinit_softc(sc); | |
259 | pci_iounmap(pdev, sc->iobase); | |
260 | pci_release_region(pdev, 0); | |
261 | pci_disable_device(pdev); | |
262 | ieee80211_free_hw(hw); | |
263 | } | |
264 | ||
265 | #ifdef CONFIG_PM_SLEEP | |
266 | static int ath5k_pci_suspend(struct device *dev) | |
267 | { | |
268 | struct ath5k_softc *sc = pci_get_drvdata(to_pci_dev(dev)); | |
269 | ||
270 | ath5k_led_off(sc); | |
271 | return 0; | |
272 | } | |
273 | ||
274 | static int ath5k_pci_resume(struct device *dev) | |
275 | { | |
276 | struct pci_dev *pdev = to_pci_dev(dev); | |
277 | struct ath5k_softc *sc = pci_get_drvdata(pdev); | |
278 | ||
279 | /* | |
280 | * Suspend/Resume resets the PCI configuration space, so we have to | |
281 | * re-disable the RETRY_TIMEOUT register (0x41) to keep | |
282 | * PCI Tx retries from interfering with C3 CPU state | |
283 | */ | |
284 | pci_write_config_byte(pdev, 0x41, 0); | |
285 | ||
286 | ath5k_led_enable(sc); | |
287 | return 0; | |
288 | } | |
289 | ||
290 | static SIMPLE_DEV_PM_OPS(ath5k_pm_ops, ath5k_pci_suspend, ath5k_pci_resume); | |
291 | #define ATH5K_PM_OPS (&ath5k_pm_ops) | |
292 | #else | |
293 | #define ATH5K_PM_OPS NULL | |
294 | #endif /* CONFIG_PM_SLEEP */ | |
295 | ||
296 | static struct pci_driver ath5k_pci_driver = { | |
297 | .name = KBUILD_MODNAME, | |
298 | .id_table = ath5k_pci_id_table, | |
299 | .probe = ath5k_pci_probe, | |
300 | .remove = __devexit_p(ath5k_pci_remove), | |
301 | .driver.pm = ATH5K_PM_OPS, | |
302 | }; | |
303 | ||
304 | /* | |
305 | * Module init/exit functions | |
306 | */ | |
307 | static int __init | |
308 | init_ath5k_pci(void) | |
309 | { | |
310 | int ret; | |
311 | ||
312 | ret = pci_register_driver(&ath5k_pci_driver); | |
313 | if (ret) { | |
314 | printk(KERN_ERR "ath5k_pci: can't register pci driver\n"); | |
315 | return ret; | |
316 | } | |
317 | ||
318 | return 0; | |
319 | } | |
320 | ||
321 | static void __exit | |
322 | exit_ath5k_pci(void) | |
323 | { | |
324 | pci_unregister_driver(&ath5k_pci_driver); | |
325 | } | |
326 | ||
327 | module_init(init_ath5k_pci); | |
328 | module_exit(exit_ath5k_pci); |