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394cf0a1 | 1 | /* |
cee075a2 | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
394cf0a1 S |
3 | * |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #ifndef ANI_H | |
18 | #define ANI_H | |
19 | ||
20 | #define HAL_PROCESS_ANI 0x00000001 | |
21 | #define ATH9K_RSSI_EP_MULTIPLIER (1<<7) | |
22 | ||
2660b81a | 23 | #define DO_ANI(ah) (((ah)->proc_phyerr & HAL_PROCESS_ANI)) |
394cf0a1 S |
24 | |
25 | #define HAL_EP_RND(x, mul) \ | |
26 | ((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul)) | |
27 | #define BEACON_RSSI(ahp) \ | |
2660b81a | 28 | HAL_EP_RND(ahp->stats.ast_nodestats.ns_avgbrssi, \ |
394cf0a1 S |
29 | ATH9K_RSSI_EP_MULTIPLIER) |
30 | ||
31 | #define ATH9K_ANI_OFDM_TRIG_HIGH 500 | |
32 | #define ATH9K_ANI_OFDM_TRIG_LOW 200 | |
33 | #define ATH9K_ANI_CCK_TRIG_HIGH 200 | |
34 | #define ATH9K_ANI_CCK_TRIG_LOW 100 | |
35 | #define ATH9K_ANI_NOISE_IMMUNE_LVL 4 | |
36 | #define ATH9K_ANI_USE_OFDM_WEAK_SIG true | |
37 | #define ATH9K_ANI_CCK_WEAK_SIG_THR false | |
38 | #define ATH9K_ANI_SPUR_IMMUNE_LVL 7 | |
39 | #define ATH9K_ANI_FIRSTEP_LVL 0 | |
40 | #define ATH9K_ANI_RSSI_THR_HIGH 40 | |
41 | #define ATH9K_ANI_RSSI_THR_LOW 7 | |
42 | #define ATH9K_ANI_PERIOD 100 | |
43 | ||
44 | #define HAL_NOISE_IMMUNE_MAX 4 | |
45 | #define HAL_SPUR_IMMUNE_MAX 7 | |
46 | #define HAL_FIRST_STEP_MAX 2 | |
47 | ||
48 | enum ath9k_ani_cmd { | |
49 | ATH9K_ANI_PRESENT = 0x1, | |
50 | ATH9K_ANI_NOISE_IMMUNITY_LEVEL = 0x2, | |
51 | ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION = 0x4, | |
52 | ATH9K_ANI_CCK_WEAK_SIGNAL_THR = 0x8, | |
53 | ATH9K_ANI_FIRSTEP_LEVEL = 0x10, | |
54 | ATH9K_ANI_SPUR_IMMUNITY_LEVEL = 0x20, | |
55 | ATH9K_ANI_MODE = 0x40, | |
56 | ATH9K_ANI_PHYERR_RESET = 0x80, | |
57 | ATH9K_ANI_ALL = 0xff | |
58 | }; | |
59 | ||
60 | struct ath9k_mib_stats { | |
61 | u32 ackrcv_bad; | |
62 | u32 rts_bad; | |
63 | u32 rts_good; | |
64 | u32 fcs_bad; | |
65 | u32 beacons; | |
66 | }; | |
67 | ||
68 | struct ath9k_node_stats { | |
69 | u32 ns_avgbrssi; | |
70 | u32 ns_avgrssi; | |
71 | u32 ns_avgtxrssi; | |
72 | u32 ns_avgtxrate; | |
73 | }; | |
74 | ||
ee6e8d1c S |
75 | struct ar5416AniState { |
76 | struct ath9k_channel *c; | |
77 | u8 noiseImmunityLevel; | |
78 | u8 spurImmunityLevel; | |
79 | u8 firstepLevel; | |
80 | u8 ofdmWeakSigDetectOff; | |
81 | u8 cckWeakSigThreshold; | |
82 | u32 listenTime; | |
83 | u32 ofdmTrigHigh; | |
84 | u32 ofdmTrigLow; | |
85 | int32_t cckTrigHigh; | |
86 | int32_t cckTrigLow; | |
87 | int32_t rssiThrLow; | |
88 | int32_t rssiThrHigh; | |
89 | u32 noiseFloor; | |
90 | u32 txFrameCount; | |
91 | u32 rxFrameCount; | |
92 | u32 cycleCount; | |
93 | u32 ofdmPhyErrCount; | |
94 | u32 cckPhyErrCount; | |
95 | u32 ofdmPhyErrBase; | |
96 | u32 cckPhyErrBase; | |
97 | int16_t pktRssi[2]; | |
98 | int16_t ofdmErrRssi[2]; | |
99 | int16_t cckErrRssi[2]; | |
100 | }; | |
101 | ||
394cf0a1 S |
102 | struct ar5416Stats { |
103 | u32 ast_ani_niup; | |
104 | u32 ast_ani_nidown; | |
105 | u32 ast_ani_spurup; | |
106 | u32 ast_ani_spurdown; | |
107 | u32 ast_ani_ofdmon; | |
108 | u32 ast_ani_ofdmoff; | |
109 | u32 ast_ani_cckhigh; | |
110 | u32 ast_ani_ccklow; | |
111 | u32 ast_ani_stepup; | |
112 | u32 ast_ani_stepdown; | |
113 | u32 ast_ani_ofdmerrs; | |
114 | u32 ast_ani_cckerrs; | |
115 | u32 ast_ani_reset; | |
116 | u32 ast_ani_lzero; | |
117 | u32 ast_ani_lneg; | |
118 | struct ath9k_mib_stats ast_mibstats; | |
119 | struct ath9k_node_stats ast_nodestats; | |
120 | }; | |
2660b81a | 121 | #define ah_mibStats stats.ast_mibstats |
394cf0a1 | 122 | |
cbe61d8a S |
123 | void ath9k_ani_reset(struct ath_hw *ah); |
124 | void ath9k_hw_ani_monitor(struct ath_hw *ah, | |
394cf0a1 S |
125 | const struct ath9k_node_stats *stats, |
126 | struct ath9k_channel *chan); | |
cbe61d8a S |
127 | bool ath9k_hw_phycounters(struct ath_hw *ah); |
128 | void ath9k_enable_mib_counters(struct ath_hw *ah); | |
129 | void ath9k_hw_disable_mib_counters(struct ath_hw *ah); | |
130 | u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hw *ah, u32 *rxc_pcnt, | |
394cf0a1 | 131 | u32 *rxf_pcnt, u32 *txf_pcnt); |
cbe61d8a | 132 | void ath9k_hw_procmibevent(struct ath_hw *ah, |
394cf0a1 | 133 | const struct ath9k_node_stats *stats); |
cbe61d8a S |
134 | void ath9k_hw_ani_setup(struct ath_hw *ah); |
135 | void ath9k_hw_ani_attach(struct ath_hw *ah); | |
136 | void ath9k_hw_ani_detach(struct ath_hw *ah); | |
394cf0a1 S |
137 | |
138 | #endif /* ANI_H */ |