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ath_hw: Fix bssid mask documentation
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / wireless / ath / ath9k / ar9003_calib.c
CommitLineData
795f5e2c
LR		 1/*
2 * Copyright (c) 2010 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "hw.h"
18#include "hw-ops.h"
19#include "ar9003_phy.h"
20
858b7e36 21#define MAX_MEASUREMENT 8
3782c69d
RM		 22#define MAX_MAG_DELTA 11
23#define MAX_PHS_DELTA 10
858b7e36
VT		 24
25struct coeff {
3782c69d
RM		 26 int mag_coeff[AR9300_MAX_CHAINS][MAX_MEASUREMENT];
27 int phs_coeff[AR9300_MAX_CHAINS][MAX_MEASUREMENT];
858b7e36
VT		 28 int iqc_coeff[2];
29};
30
6497827f
FF		 31enum ar9003_cal_types {
32 IQ_MISMATCH_CAL = BIT(0),
33 TEMP_COMP_CAL = BIT(1),
34};
35
795f5e2c
LR		 36static void ar9003_hw_setup_calibration(struct ath_hw *ah,
37 struct ath9k_cal_list *currCal)
38{
4b01931e
LR		 39 struct ath_common *common = ath9k_hw_common(ah);
40
41 /* Select calibration to run */
42 switch (currCal->calData->calType) {
43 case IQ_MISMATCH_CAL:
44 /*
45 * Start calibration with
46 * 2^(INIT_IQCAL_LOG_COUNT_MAX+1) samples
47 */
48 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
49 AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX,
50 currCal->calData->calCountMax);
51 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
52
226afe68
JP		 53 ath_dbg(common, ATH_DBG_CALIBRATE,
54 "starting IQ Mismatch Calibration\n");
4b01931e
LR		 55
56 /* Kick-off cal */
57 REG_SET_BIT(ah, AR_PHY_TIMING4, AR_PHY_TIMING4_DO_CAL);
58 break;
59 case TEMP_COMP_CAL:
60 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_THERM,
61 AR_PHY_65NM_CH0_THERM_LOCAL, 1);
62 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_THERM,
63 AR_PHY_65NM_CH0_THERM_START, 1);
64
226afe68
JP		 65 ath_dbg(common, ATH_DBG_CALIBRATE,
66 "starting Temperature Compensation Calibration\n");
4b01931e 67 break;
4b01931e 68 }
795f5e2c
LR		 69}
70
df23acaa
LR		 71/*
72 * Generic calibration routine.
73 * Recalibrate the lower PHY chips to account for temperature/environment
74 * changes.
75 */
76static bool ar9003_hw_per_calibration(struct ath_hw *ah,
77 struct ath9k_channel *ichan,
78 u8 rxchainmask,
79 struct ath9k_cal_list *currCal)
80{
20bd2a09 81 struct ath9k_hw_cal_data *caldata = ah->caldata;
df23acaa
LR		 82 /* Cal is assumed not done until explicitly set below */
83 bool iscaldone = false;
84
85 /* Calibration in progress. */
86 if (currCal->calState == CAL_RUNNING) {
87 /* Check to see if it has finished. */
88 if (!(REG_READ(ah, AR_PHY_TIMING4) & AR_PHY_TIMING4_DO_CAL)) {
89 /*
90 * Accumulate cal measures for active chains
91 */
92 currCal->calData->calCollect(ah);
93 ah->cal_samples++;
94
95 if (ah->cal_samples >=
96 currCal->calData->calNumSamples) {
97 unsigned int i, numChains = 0;
98 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
99 if (rxchainmask & (1 << i))
100 numChains++;
101 }
102
103 /*
104 * Process accumulated data
105 */
106 currCal->calData->calPostProc(ah, numChains);
107
108 /* Calibration has finished. */
20bd2a09 109 caldata->CalValid |= currCal->calData->calType;
df23acaa
LR		 110 currCal->calState = CAL_DONE;
111 iscaldone = true;
112 } else {
113 /*
114 * Set-up collection of another sub-sample until we
115 * get desired number
116 */
117 ar9003_hw_setup_calibration(ah, currCal);
118 }
119 }
20bd2a09 120 } else if (!(caldata->CalValid & currCal->calData->calType)) {
df23acaa
LR		 121 /* If current cal is marked invalid in channel, kick it off */
122 ath9k_hw_reset_calibration(ah, currCal);
123 }
124
125 return iscaldone;
126}
127
795f5e2c
LR		 128static bool ar9003_hw_calibrate(struct ath_hw *ah,
129 struct ath9k_channel *chan,
130 u8 rxchainmask,
131 bool longcal)
132{
df23acaa
LR		 133 bool iscaldone = true;
134 struct ath9k_cal_list *currCal = ah->cal_list_curr;
135
136 /*
137 * For given calibration:
138 * 1. Call generic cal routine
139 * 2. When this cal is done (isCalDone) if we have more cals waiting
140 * (eg after reset), mask this to upper layers by not propagating
141 * isCalDone if it is set to TRUE.
142 * Instead, change isCalDone to FALSE and setup the waiting cal(s)
143 * to be run.
144 */
145 if (currCal &&
146 (currCal->calState == CAL_RUNNING ||
147 currCal->calState == CAL_WAITING)) {
148 iscaldone = ar9003_hw_per_calibration(ah, chan,
149 rxchainmask, currCal);
150 if (iscaldone) {
151 ah->cal_list_curr = currCal = currCal->calNext;
152
153 if (currCal->calState == CAL_WAITING) {
154 iscaldone = false;
155 ath9k_hw_reset_calibration(ah, currCal);
156 }
157 }
158 }
795f5e2c 159
df23acaa
LR		 160 /* Do NF cal only at longer intervals */
161 if (longcal) {
93697460
FF		 162 /*
163 * Get the value from the previous NF cal and update
164 * history buffer.
165 */
166 ath9k_hw_getnf(ah, chan);
167
df23acaa
LR		 168 /*
169 * Load the NF from history buffer of the current channel.
170 * NF is slow time-variant, so it is OK to use a historical
171 * value.
172 */
173 ath9k_hw_loadnf(ah, ah->curchan);
174
175 /* start NF calibration, without updating BB NF register */
00c86590 176 ath9k_hw_start_nfcal(ah, false);
df23acaa
LR		 177 }
178
179 return iscaldone;
795f5e2c
LR		 180}
181
590b7d2f
LR		 182static void ar9003_hw_iqcal_collect(struct ath_hw *ah)
183{
184 int i;
185
186 /* Accumulate IQ cal measures for active chains */
187 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
5d48ae78
VT		 188 if (ah->txchainmask & BIT(i)) {
189 ah->totalPowerMeasI[i] +=
190 REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
191 ah->totalPowerMeasQ[i] +=
192 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
193 ah->totalIqCorrMeas[i] +=
194 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
195 ath_dbg(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
196 "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
197 ah->cal_samples, i, ah->totalPowerMeasI[i],
198 ah->totalPowerMeasQ[i],
199 ah->totalIqCorrMeas[i]);
200 }
590b7d2f
LR		 201 }
202}
203
204static void ar9003_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
205{
206 struct ath_common *common = ath9k_hw_common(ah);
207 u32 powerMeasQ, powerMeasI, iqCorrMeas;
208 u32 qCoffDenom, iCoffDenom;
209 int32_t qCoff, iCoff;
210 int iqCorrNeg, i;
07b2fa5a 211 static const u_int32_t offset_array[3] = {
590b7d2f
LR		 212 AR_PHY_RX_IQCAL_CORR_B0,
213 AR_PHY_RX_IQCAL_CORR_B1,
214 AR_PHY_RX_IQCAL_CORR_B2,
215 };
216
217 for (i = 0; i < numChains; i++) {
218 powerMeasI = ah->totalPowerMeasI[i];
219 powerMeasQ = ah->totalPowerMeasQ[i];
220 iqCorrMeas = ah->totalIqCorrMeas[i];
221
226afe68
JP		 222 ath_dbg(common, ATH_DBG_CALIBRATE,
223 "Starting IQ Cal and Correction for Chain %d\n",
224 i);
590b7d2f 225
226afe68
JP		 226 ath_dbg(common, ATH_DBG_CALIBRATE,
227 "Orignal: Chn %diq_corr_meas = 0x%08x\n",
228 i, ah->totalIqCorrMeas[i]);
590b7d2f
LR		 229
230 iqCorrNeg = 0;
231
232 if (iqCorrMeas > 0x80000000) {
233 iqCorrMeas = (0xffffffff - iqCorrMeas) + 1;
234 iqCorrNeg = 1;
235 }
236
226afe68
JP		 237 ath_dbg(common, ATH_DBG_CALIBRATE,
238 "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
239 ath_dbg(common, ATH_DBG_CALIBRATE,
240 "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
241 ath_dbg(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
242 iqCorrNeg);
590b7d2f
LR		 243
244 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 256;
245 qCoffDenom = powerMeasQ / 64;
246
247 if ((iCoffDenom != 0) && (qCoffDenom != 0)) {
248 iCoff = iqCorrMeas / iCoffDenom;
249 qCoff = powerMeasI / qCoffDenom - 64;
226afe68
JP		 250 ath_dbg(common, ATH_DBG_CALIBRATE,
251 "Chn %d iCoff = 0x%08x\n", i, iCoff);
252 ath_dbg(common, ATH_DBG_CALIBRATE,
253 "Chn %d qCoff = 0x%08x\n", i, qCoff);
590b7d2f
LR		 254
255 /* Force bounds on iCoff */
256 if (iCoff >= 63)
257 iCoff = 63;
258 else if (iCoff <= -63)
259 iCoff = -63;
260
261 /* Negate iCoff if iqCorrNeg == 0 */
262 if (iqCorrNeg == 0x0)
263 iCoff = -iCoff;
264
265 /* Force bounds on qCoff */
266 if (qCoff >= 63)
267 qCoff = 63;
268 else if (qCoff <= -63)
269 qCoff = -63;
270
271 iCoff = iCoff & 0x7f;
272 qCoff = qCoff & 0x7f;
273
226afe68
JP		 274 ath_dbg(common, ATH_DBG_CALIBRATE,
275 "Chn %d : iCoff = 0x%x qCoff = 0x%x\n",
276 i, iCoff, qCoff);
277 ath_dbg(common, ATH_DBG_CALIBRATE,
278 "Register offset (0x%04x) before update = 0x%x\n",
279 offset_array[i],
280 REG_READ(ah, offset_array[i]));
590b7d2f
LR		 281
282 REG_RMW_FIELD(ah, offset_array[i],
283 AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF,
284 iCoff);
285 REG_RMW_FIELD(ah, offset_array[i],
286 AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF,
287 qCoff);
226afe68
JP		 288 ath_dbg(common, ATH_DBG_CALIBRATE,
289 "Register offset (0x%04x) QI COFF (bitfields 0x%08x) after update = 0x%x\n",
290 offset_array[i],
291 AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF,
292 REG_READ(ah, offset_array[i]));
293 ath_dbg(common, ATH_DBG_CALIBRATE,
294 "Register offset (0x%04x) QQ COFF (bitfields 0x%08x) after update = 0x%x\n",
295 offset_array[i],
296 AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF,
297 REG_READ(ah, offset_array[i]));
298
299 ath_dbg(common, ATH_DBG_CALIBRATE,
300 "IQ Cal and Correction done for Chain %d\n", i);
590b7d2f
LR		 301 }
302 }
303
304 REG_SET_BIT(ah, AR_PHY_RX_IQCAL_CORR_B0,
305 AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE);
226afe68
JP		 306 ath_dbg(common, ATH_DBG_CALIBRATE,
307 "IQ Cal and Correction (offset 0x%04x) enabled (bit position 0x%08x). New Value 0x%08x\n",
308 (unsigned) (AR_PHY_RX_IQCAL_CORR_B0),
309 AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE,
310 REG_READ(ah, AR_PHY_RX_IQCAL_CORR_B0));
590b7d2f
LR		 311}
312
313static const struct ath9k_percal_data iq_cal_single_sample = {
314 IQ_MISMATCH_CAL,
315 MIN_CAL_SAMPLES,
316 PER_MAX_LOG_COUNT,
317 ar9003_hw_iqcal_collect,
318 ar9003_hw_iqcalibrate
319};
320
795f5e2c
LR		 321static void ar9003_hw_init_cal_settings(struct ath_hw *ah)
322{
590b7d2f 323 ah->iq_caldata.calData = &iq_cal_single_sample;
795f5e2c
LR		 324}
325
df23acaa
LR		 326/*
327 * solve 4x4 linear equation used in loopback iq cal.
328 */
329static bool ar9003_hw_solve_iq_cal(struct ath_hw *ah,
330 s32 sin_2phi_1,
331 s32 cos_2phi_1,
332 s32 sin_2phi_2,
333 s32 cos_2phi_2,
334 s32 mag_a0_d0,
335 s32 phs_a0_d0,
336 s32 mag_a1_d0,
337 s32 phs_a1_d0,
338 s32 solved_eq[])
339{
340 s32 f1 = cos_2phi_1 - cos_2phi_2,
341 f3 = sin_2phi_1 - sin_2phi_2,
342 f2;
343 s32 mag_tx, phs_tx, mag_rx, phs_rx;
344 const s32 result_shift = 1 << 15;
345 struct ath_common *common = ath9k_hw_common(ah);
346
347 f2 = (f1 * f1 + f3 * f3) / result_shift;
348
349 if (!f2) {
226afe68 350 ath_dbg(common, ATH_DBG_CALIBRATE, "Divide by 0\n");
df23acaa
LR		 351 return false;
352 }
353
354 /* mag mismatch, tx */
355 mag_tx = f1 * (mag_a0_d0 - mag_a1_d0) + f3 * (phs_a0_d0 - phs_a1_d0);
356 /* phs mismatch, tx */
357 phs_tx = f3 * (-mag_a0_d0 + mag_a1_d0) + f1 * (phs_a0_d0 - phs_a1_d0);
358
359 mag_tx = (mag_tx / f2);
360 phs_tx = (phs_tx / f2);
361
362 /* mag mismatch, rx */
363 mag_rx = mag_a0_d0 - (cos_2phi_1 * mag_tx + sin_2phi_1 * phs_tx) /
364 result_shift;
365 /* phs mismatch, rx */
366 phs_rx = phs_a0_d0 + (sin_2phi_1 * mag_tx - cos_2phi_1 * phs_tx) /
367 result_shift;
368
369 solved_eq[0] = mag_tx;
370 solved_eq[1] = phs_tx;
371 solved_eq[2] = mag_rx;
372 solved_eq[3] = phs_rx;
373
374 return true;
375}
376
377static s32 ar9003_hw_find_mag_approx(struct ath_hw *ah, s32 in_re, s32 in_im)
77d6d39a 378{
df23acaa
LR		 379 s32 abs_i = abs(in_re),
380 abs_q = abs(in_im),
381 max_abs, min_abs;
382
383 if (abs_i > abs_q) {
384 max_abs = abs_i;
385 min_abs = abs_q;
386 } else {
387 max_abs = abs_q;
388 min_abs = abs_i;
389 }
390
391 return max_abs - (max_abs / 32) + (min_abs / 8) + (min_abs / 4);
392}
393
394#define DELPT 32
395
396static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah,
397 s32 chain_idx,
398 const s32 iq_res[],
399 s32 iqc_coeff[])
400{
401 s32 i2_m_q2_a0_d0, i2_p_q2_a0_d0, iq_corr_a0_d0,
402 i2_m_q2_a0_d1, i2_p_q2_a0_d1, iq_corr_a0_d1,
403 i2_m_q2_a1_d0, i2_p_q2_a1_d0, iq_corr_a1_d0,
404 i2_m_q2_a1_d1, i2_p_q2_a1_d1, iq_corr_a1_d1;
405 s32 mag_a0_d0, mag_a1_d0, mag_a0_d1, mag_a1_d1,
406 phs_a0_d0, phs_a1_d0, phs_a0_d1, phs_a1_d1,
407 sin_2phi_1, cos_2phi_1,
408 sin_2phi_2, cos_2phi_2;
409 s32 mag_tx, phs_tx, mag_rx, phs_rx;
410 s32 solved_eq[4], mag_corr_tx, phs_corr_tx, mag_corr_rx, phs_corr_rx,
411 q_q_coff, q_i_coff;
412 const s32 res_scale = 1 << 15;
413 const s32 delpt_shift = 1 << 8;
414 s32 mag1, mag2;
415 struct ath_common *common = ath9k_hw_common(ah);
416
417 i2_m_q2_a0_d0 = iq_res[0] & 0xfff;
418 i2_p_q2_a0_d0 = (iq_res[0] >> 12) & 0xfff;
419 iq_corr_a0_d0 = ((iq_res[0] >> 24) & 0xff) + ((iq_res[1] & 0xf) << 8);
420
421 if (i2_m_q2_a0_d0 > 0x800)
422 i2_m_q2_a0_d0 = -((0xfff - i2_m_q2_a0_d0) + 1);
423
424 if (i2_p_q2_a0_d0 > 0x800)
425 i2_p_q2_a0_d0 = -((0xfff - i2_p_q2_a0_d0) + 1);
426
427 if (iq_corr_a0_d0 > 0x800)
428 iq_corr_a0_d0 = -((0xfff - iq_corr_a0_d0) + 1);
429
430 i2_m_q2_a0_d1 = (iq_res[1] >> 4) & 0xfff;
431 i2_p_q2_a0_d1 = (iq_res[2] & 0xfff);
432 iq_corr_a0_d1 = (iq_res[2] >> 12) & 0xfff;
433
434 if (i2_m_q2_a0_d1 > 0x800)
435 i2_m_q2_a0_d1 = -((0xfff - i2_m_q2_a0_d1) + 1);
436
437 if (i2_p_q2_a0_d1 > 0x800)
438 i2_p_q2_a0_d1 = -((0xfff - i2_p_q2_a0_d1) + 1);
439
440 if (iq_corr_a0_d1 > 0x800)
441 iq_corr_a0_d1 = -((0xfff - iq_corr_a0_d1) + 1);
442
443 i2_m_q2_a1_d0 = ((iq_res[2] >> 24) & 0xff) + ((iq_res[3] & 0xf) << 8);
444 i2_p_q2_a1_d0 = (iq_res[3] >> 4) & 0xfff;
445 iq_corr_a1_d0 = iq_res[4] & 0xfff;
446
447 if (i2_m_q2_a1_d0 > 0x800)
448 i2_m_q2_a1_d0 = -((0xfff - i2_m_q2_a1_d0) + 1);
449
450 if (i2_p_q2_a1_d0 > 0x800)
451 i2_p_q2_a1_d0 = -((0xfff - i2_p_q2_a1_d0) + 1);
452
453 if (iq_corr_a1_d0 > 0x800)
454 iq_corr_a1_d0 = -((0xfff - iq_corr_a1_d0) + 1);
455
456 i2_m_q2_a1_d1 = (iq_res[4] >> 12) & 0xfff;
457 i2_p_q2_a1_d1 = ((iq_res[4] >> 24) & 0xff) + ((iq_res[5] & 0xf) << 8);
458 iq_corr_a1_d1 = (iq_res[5] >> 4) & 0xfff;
459
460 if (i2_m_q2_a1_d1 > 0x800)
461 i2_m_q2_a1_d1 = -((0xfff - i2_m_q2_a1_d1) + 1);
462
463 if (i2_p_q2_a1_d1 > 0x800)
464 i2_p_q2_a1_d1 = -((0xfff - i2_p_q2_a1_d1) + 1);
465
466 if (iq_corr_a1_d1 > 0x800)
467 iq_corr_a1_d1 = -((0xfff - iq_corr_a1_d1) + 1);
468
469 if ((i2_p_q2_a0_d0 == 0) || (i2_p_q2_a0_d1 == 0) ||
470 (i2_p_q2_a1_d0 == 0) || (i2_p_q2_a1_d1 == 0)) {
226afe68
JP		 471 ath_dbg(common, ATH_DBG_CALIBRATE,
472 "Divide by 0:\n"
473 "a0_d0=%d\n"
474 "a0_d1=%d\n"
475 "a2_d0=%d\n"
476 "a1_d1=%d\n",
477 i2_p_q2_a0_d0, i2_p_q2_a0_d1,
478 i2_p_q2_a1_d0, i2_p_q2_a1_d1);
df23acaa
LR		 479 return false;
480 }
481
482 mag_a0_d0 = (i2_m_q2_a0_d0 * res_scale) / i2_p_q2_a0_d0;
483 phs_a0_d0 = (iq_corr_a0_d0 * res_scale) / i2_p_q2_a0_d0;
484
485 mag_a0_d1 = (i2_m_q2_a0_d1 * res_scale) / i2_p_q2_a0_d1;
486 phs_a0_d1 = (iq_corr_a0_d1 * res_scale) / i2_p_q2_a0_d1;
487
488 mag_a1_d0 = (i2_m_q2_a1_d0 * res_scale) / i2_p_q2_a1_d0;
489 phs_a1_d0 = (iq_corr_a1_d0 * res_scale) / i2_p_q2_a1_d0;
490
491 mag_a1_d1 = (i2_m_q2_a1_d1 * res_scale) / i2_p_q2_a1_d1;
492 phs_a1_d1 = (iq_corr_a1_d1 * res_scale) / i2_p_q2_a1_d1;
493
494 /* w/o analog phase shift */
495 sin_2phi_1 = (((mag_a0_d0 - mag_a0_d1) * delpt_shift) / DELPT);
496 /* w/o analog phase shift */
497 cos_2phi_1 = (((phs_a0_d1 - phs_a0_d0) * delpt_shift) / DELPT);
498 /* w/ analog phase shift */
499 sin_2phi_2 = (((mag_a1_d0 - mag_a1_d1) * delpt_shift) / DELPT);
500 /* w/ analog phase shift */
501 cos_2phi_2 = (((phs_a1_d1 - phs_a1_d0) * delpt_shift) / DELPT);
502
503 /*
504 * force sin^2 + cos^2 = 1;
505 * find magnitude by approximation
506 */
507 mag1 = ar9003_hw_find_mag_approx(ah, cos_2phi_1, sin_2phi_1);
508 mag2 = ar9003_hw_find_mag_approx(ah, cos_2phi_2, sin_2phi_2);
509
510 if ((mag1 == 0) || (mag2 == 0)) {
226afe68
JP		 511 ath_dbg(common, ATH_DBG_CALIBRATE,
512 "Divide by 0: mag1=%d, mag2=%d\n",
513 mag1, mag2);
df23acaa
LR		 514 return false;
515 }
516
517 /* normalization sin and cos by mag */
518 sin_2phi_1 = (sin_2phi_1 * res_scale / mag1);
519 cos_2phi_1 = (cos_2phi_1 * res_scale / mag1);
520 sin_2phi_2 = (sin_2phi_2 * res_scale / mag2);
521 cos_2phi_2 = (cos_2phi_2 * res_scale / mag2);
522
523 /* calculate IQ mismatch */
524 if (!ar9003_hw_solve_iq_cal(ah,
525 sin_2phi_1, cos_2phi_1,
526 sin_2phi_2, cos_2phi_2,
527 mag_a0_d0, phs_a0_d0,
528 mag_a1_d0,
529 phs_a1_d0, solved_eq)) {
226afe68
JP		 530 ath_dbg(common, ATH_DBG_CALIBRATE,
531 "Call to ar9003_hw_solve_iq_cal() failed.\n");
df23acaa
LR		 532 return false;
533 }
534
535 mag_tx = solved_eq[0];
536 phs_tx = solved_eq[1];
537 mag_rx = solved_eq[2];
538 phs_rx = solved_eq[3];
539
226afe68
JP		 540 ath_dbg(common, ATH_DBG_CALIBRATE,
541 "chain %d: mag mismatch=%d phase mismatch=%d\n",
542 chain_idx, mag_tx/res_scale, phs_tx/res_scale);
df23acaa
LR		 543
544 if (res_scale == mag_tx) {
226afe68
JP		 545 ath_dbg(common, ATH_DBG_CALIBRATE,
546 "Divide by 0: mag_tx=%d, res_scale=%d\n",
547 mag_tx, res_scale);
df23acaa
LR		 548 return false;
549 }
550
551 /* calculate and quantize Tx IQ correction factor */
552 mag_corr_tx = (mag_tx * res_scale) / (res_scale - mag_tx);
553 phs_corr_tx = -phs_tx;
554
555 q_q_coff = (mag_corr_tx * 128 / res_scale);
556 q_i_coff = (phs_corr_tx * 256 / res_scale);
557
226afe68
JP		 558 ath_dbg(common, ATH_DBG_CALIBRATE,
559 "tx chain %d: mag corr=%d phase corr=%d\n",
560 chain_idx, q_q_coff, q_i_coff);
df23acaa
LR		 561
562 if (q_i_coff < -63)
563 q_i_coff = -63;
564 if (q_i_coff > 63)
565 q_i_coff = 63;
566 if (q_q_coff < -63)
567 q_q_coff = -63;
568 if (q_q_coff > 63)
569 q_q_coff = 63;
570
571 iqc_coeff[0] = (q_q_coff * 128) + q_i_coff;
572
226afe68
JP		 573 ath_dbg(common, ATH_DBG_CALIBRATE,
574 "tx chain %d: iq corr coeff=%x\n",
575 chain_idx, iqc_coeff[0]);
df23acaa
LR		 576
577 if (-mag_rx == res_scale) {
226afe68
JP		 578 ath_dbg(common, ATH_DBG_CALIBRATE,
579 "Divide by 0: mag_rx=%d, res_scale=%d\n",
580 mag_rx, res_scale);
df23acaa
LR		 581 return false;
582 }
583
584 /* calculate and quantize Rx IQ correction factors */
585 mag_corr_rx = (-mag_rx * res_scale) / (res_scale + mag_rx);
586 phs_corr_rx = -phs_rx;
587
588 q_q_coff = (mag_corr_rx * 128 / res_scale);
589 q_i_coff = (phs_corr_rx * 256 / res_scale);
590
226afe68
JP		 591 ath_dbg(common, ATH_DBG_CALIBRATE,
592 "rx chain %d: mag corr=%d phase corr=%d\n",
593 chain_idx, q_q_coff, q_i_coff);
df23acaa
LR		 594
595 if (q_i_coff < -63)
596 q_i_coff = -63;
597 if (q_i_coff > 63)
598 q_i_coff = 63;
599 if (q_q_coff < -63)
600 q_q_coff = -63;
601 if (q_q_coff > 63)
602 q_q_coff = 63;
603
604 iqc_coeff[1] = (q_q_coff * 128) + q_i_coff;
605
226afe68
JP		 606 ath_dbg(common, ATH_DBG_CALIBRATE,
607 "rx chain %d: iq corr coeff=%x\n",
608 chain_idx, iqc_coeff[1]);
df23acaa
LR		 609
610 return true;
611}
612
3782c69d
RM		 613static void ar9003_hw_detect_outlier(int *mp_coeff, int nmeasurement,
614 int max_delta)
858b7e36 615{
3782c69d
RM		 616 int mp_max = -64, max_idx = 0;
617 int mp_min = 63, min_idx = 0;
618 int mp_avg = 0, i, outlier_idx = 0;
619
620 /* find min/max mismatch across all calibrated gains */
621 for (i = 0; i < nmeasurement; i++) {
622 mp_avg += mp_coeff[i];
623 if (mp_coeff[i] > mp_max) {
624 mp_max = mp_coeff[i];
625 max_idx = i;
626 } else if (mp_coeff[i] < mp_min) {
627 mp_min = mp_coeff[i];
628 min_idx = i;
629 }
630 }
858b7e36 631
3782c69d
RM		 632 /* find average (exclude max abs value) */
633 for (i = 0; i < nmeasurement; i++) {
634 if ((abs(mp_coeff[i]) < abs(mp_max)) ||
635 (abs(mp_coeff[i]) < abs(mp_min)))
636 mp_avg += mp_coeff[i];
637 }
638 mp_avg /= (nmeasurement - 1);
858b7e36 639
3782c69d
RM		 640 /* detect outlier */
641 if (abs(mp_max - mp_min) > max_delta) {
642 if (abs(mp_max - mp_avg) > abs(mp_min - mp_avg))
643 outlier_idx = max_idx;
644 else
645 outlier_idx = min_idx;
646 }
647 mp_coeff[outlier_idx] = mp_avg;
858b7e36
VT		 648}
649
650static void ar9003_hw_tx_iqcal_load_avg_2_passes(struct ath_hw *ah,
651 u8 num_chains,
652 struct coeff *coeff)
653{
858b7e36 654 int i, im, nmeasurement;
858b7e36
VT		 655 u32 tx_corr_coeff[MAX_MEASUREMENT][AR9300_MAX_CHAINS];
656
657 memset(tx_corr_coeff, 0, sizeof(tx_corr_coeff));
658 for (i = 0; i < MAX_MEASUREMENT / 2; i++) {
659 tx_corr_coeff[i * 2][0] = tx_corr_coeff[(i * 2) + 1][0] =
660 AR_PHY_TX_IQCAL_CORR_COEFF_B0(i);
661 if (!AR_SREV_9485(ah)) {
662 tx_corr_coeff[i * 2][1] =
663 tx_corr_coeff[(i * 2) + 1][1] =
664 AR_PHY_TX_IQCAL_CORR_COEFF_B1(i);
665
666 tx_corr_coeff[i * 2][2] =
667 tx_corr_coeff[(i * 2) + 1][2] =
668 AR_PHY_TX_IQCAL_CORR_COEFF_B2(i);
669 }
670 }
671
672 /* Load the average of 2 passes */
673 for (i = 0; i < num_chains; i++) {
3782c69d
RM		 674 nmeasurement = REG_READ_FIELD(ah,
675 AR_PHY_TX_IQCAL_STATUS_B0,
676 AR_PHY_CALIBRATED_GAINS_0);
858b7e36
VT		 677
678 if (nmeasurement > MAX_MEASUREMENT)
679 nmeasurement = MAX_MEASUREMENT;
680
3782c69d
RM		 681 /* detect outlier only if nmeasurement > 1 */
682 if (nmeasurement > 1) {
683 /* Detect magnitude outlier */
684 ar9003_hw_detect_outlier(coeff->mag_coeff[i],
685 nmeasurement, MAX_MAG_DELTA);
858b7e36 686
3782c69d
RM		 687 /* Detect phase outlier */
688 ar9003_hw_detect_outlier(coeff->phs_coeff[i],
689 nmeasurement, MAX_PHS_DELTA);
690 }
858b7e36 691
3782c69d
RM		 692 for (im = 0; im < nmeasurement; im++) {
693
694 coeff->iqc_coeff[0] = (coeff->mag_coeff[i][im] & 0x7f) |
695 ((coeff->phs_coeff[i][im] & 0x7f) << 7);
858b7e36
VT		 696
697 if ((im % 2) == 0)
698 REG_RMW_FIELD(ah, tx_corr_coeff[im][i],
699 AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE,
700 coeff->iqc_coeff[0]);
701 else
702 REG_RMW_FIELD(ah, tx_corr_coeff[im][i],
703 AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE,
704 coeff->iqc_coeff[0]);
705 }
706 }
707
708 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_3,
709 AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN, 0x1);
710 REG_RMW_FIELD(ah, AR_PHY_RX_IQCAL_CORR_B0,
711 AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN, 0x1);
712
713 return;
714
858b7e36
VT		 715}
716
3782c69d 717static bool ar9003_hw_tx_iq_cal_run(struct ath_hw *ah)
0b2084bc
VT		 718{
719 struct ath_common *common = ath9k_hw_common(ah);
858b7e36
VT		 720 u8 tx_gain_forced;
721
858b7e36
VT		 722 tx_gain_forced = REG_READ_FIELD(ah, AR_PHY_TX_FORCED_GAIN,
723 AR_PHY_TXGAIN_FORCE);
724 if (tx_gain_forced)
725 REG_RMW_FIELD(ah, AR_PHY_TX_FORCED_GAIN,
726 AR_PHY_TXGAIN_FORCE, 0);
727
3782c69d
RM		 728 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_START,
729 AR_PHY_TX_IQCAL_START_DO_CAL, 1);
730
731 if (!ath9k_hw_wait(ah, AR_PHY_TX_IQCAL_START,
732 AR_PHY_TX_IQCAL_START_DO_CAL, 0,
733 AH_WAIT_TIMEOUT)) {
734 ath_dbg(common, ATH_DBG_CALIBRATE,
735 "Tx IQ Cal is not completed.\n");
736 return false;
737 }
738 return true;
858b7e36
VT		 739}
740
741static void ar9003_hw_tx_iq_cal_post_proc(struct ath_hw *ah)
742{
743 struct ath_common *common = ath9k_hw_common(ah);
744 const u32 txiqcal_status[AR9300_MAX_CHAINS] = {
3782c69d 745 AR_PHY_TX_IQCAL_STATUS_B0,
858b7e36
VT		 746 AR_PHY_TX_IQCAL_STATUS_B1,
747 AR_PHY_TX_IQCAL_STATUS_B2,
748 };
749 const u_int32_t chan_info_tab[] = {
750 AR_PHY_CHAN_INFO_TAB_0,
751 AR_PHY_CHAN_INFO_TAB_1,
752 AR_PHY_CHAN_INFO_TAB_2,
753 };
754 struct coeff coeff;
755 s32 iq_res[6];
756 u8 num_chains = 0;
3782c69d 757 int i, im, j;
858b7e36
VT		 758 int nmeasurement;
759
760 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
761 if (ah->txchainmask & (1 << i))
762 num_chains++;
763 }
764
3782c69d
RM		 765 for (i = 0; i < num_chains; i++) {
766 nmeasurement = REG_READ_FIELD(ah,
767 AR_PHY_TX_IQCAL_STATUS_B0,
768 AR_PHY_CALIBRATED_GAINS_0);
769 if (nmeasurement > MAX_MEASUREMENT)
770 nmeasurement = MAX_MEASUREMENT;
858b7e36 771
3782c69d
RM		 772 for (im = 0; im < nmeasurement; im++) {
773 ath_dbg(common, ATH_DBG_CALIBRATE,
774 "Doing Tx IQ Cal for chain %d.\n", i);
858b7e36 775
3782c69d
RM		 776 if (REG_READ(ah, txiqcal_status[i]) &
777 AR_PHY_TX_IQCAL_STATUS_FAILED) {
778 ath_dbg(common, ATH_DBG_CALIBRATE,
858b7e36 779 "Tx IQ Cal failed for chain %d.\n", i);
3782c69d
RM		 780 goto tx_iqcal_fail;
781 }
858b7e36 782
3782c69d
RM		 783 for (j = 0; j < 3; j++) {
784 u32 idx = 2 * j, offset = 4 * (3 * im + j);
858b7e36 785
3782c69d 786 REG_RMW_FIELD(ah,
858b7e36
VT		 787 AR_PHY_CHAN_INFO_MEMORY,
788 AR_PHY_CHAN_INFO_TAB_S2_READ,
789 0);
790
3782c69d
RM		 791 /* 32 bits */
792 iq_res[idx] = REG_READ(ah,
793 chan_info_tab[i] +
794 offset);
858b7e36 795
3782c69d 796 REG_RMW_FIELD(ah,
858b7e36
VT		 797 AR_PHY_CHAN_INFO_MEMORY,
798 AR_PHY_CHAN_INFO_TAB_S2_READ,
799 1);
800
3782c69d
RM		 801 /* 16 bits */
802 iq_res[idx + 1] = 0xffff & REG_READ(ah,
803 chan_info_tab[i] + offset);
858b7e36 804
3782c69d
RM		 805 ath_dbg(common, ATH_DBG_CALIBRATE,
806 "IQ RES[%d]=0x%x"
807 "IQ_RES[%d]=0x%x\n",
808 idx, iq_res[idx], idx + 1,
809 iq_res[idx + 1]);
810 }
858b7e36 811
3782c69d
RM		 812 if (!ar9003_hw_calc_iq_corr(ah, i, iq_res,
813 coeff.iqc_coeff)) {
814 ath_dbg(common, ATH_DBG_CALIBRATE,
815 "Failed in calculation of \
816 IQ correction.\n");
817 goto tx_iqcal_fail;
818 }
858b7e36 819
3782c69d
RM		 820 coeff.mag_coeff[i][im] = coeff.iqc_coeff[0] & 0x7f;
821 coeff.phs_coeff[i][im] =
822 (coeff.iqc_coeff[0] >> 7) & 0x7f;
858b7e36 823
3782c69d
RM		 824 if (coeff.mag_coeff[i][im] > 63)
825 coeff.mag_coeff[i][im] -= 128;
826 if (coeff.phs_coeff[i][im] > 63)
827 coeff.phs_coeff[i][im] -= 128;
858b7e36
VT		 828 }
829 }
830 ar9003_hw_tx_iqcal_load_avg_2_passes(ah, num_chains, &coeff);
831
832 return;
833
834tx_iqcal_fail:
835 ath_dbg(common, ATH_DBG_CALIBRATE, "Tx IQ Cal failed\n");
836 return;
837}
df23acaa
LR		 838static bool ar9003_hw_init_cal(struct ath_hw *ah,
839 struct ath9k_channel *chan)
840{
841 struct ath_common *common = ath9k_hw_common(ah);
e758ff8f 842 struct ath9k_hw_capabilities *pCap = &ah->caps;
a9d85fbd 843 int val;
3782c69d 844 bool txiqcal_done = false;
df23acaa 845
a9d85fbd 846 val = REG_READ(ah, AR_ENT_OTP);
226afe68 847 ath_dbg(common, ATH_DBG_CALIBRATE, "ath9k: AR_ENT_OTP 0x%x\n", val);
a9d85fbd 848
e758ff8f
VT		 849 /* Configure rx/tx chains before running AGC/TxiQ cals */
850 if (val & AR_ENT_OTP_CHAIN2_DISABLE)
a9d85fbd
SB		 851 ar9003_hw_set_chain_masks(ah, 0x3, 0x3);
852 else
e758ff8f
VT		 853 ar9003_hw_set_chain_masks(ah, pCap->rx_chainmask,
854 pCap->tx_chainmask);
df23acaa 855
c5395b67 856 /* Do Tx IQ Calibration */
3782c69d
RM		 857 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1,
858 AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT,
859 DELPT);
858b7e36 860
3782c69d
RM		 861 /*
862 * For AR9485 or later chips, TxIQ cal runs as part of
863 * AGC calibration
864 */
865 if (AR_SREV_9485_OR_LATER(ah))
866 txiqcal_done = true;
867 else {
868 txiqcal_done = ar9003_hw_tx_iq_cal_run(ah);
869 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
870 udelay(5);
871 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
872 }
c5395b67 873
df23acaa
LR		 874 /* Calibrate the AGC */
875 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
876 REG_READ(ah, AR_PHY_AGC_CONTROL) |
877 AR_PHY_AGC_CONTROL_CAL);
878
879 /* Poll for offset calibration complete */
880 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
881 0, AH_WAIT_TIMEOUT)) {
226afe68
JP		 882 ath_dbg(common, ATH_DBG_CALIBRATE,
883 "offset calibration failed to complete in 1ms; noisy environment?\n");
df23acaa
LR		 884 return false;
885 }
886
3782c69d 887 if (txiqcal_done)
858b7e36
VT		 888 ar9003_hw_tx_iq_cal_post_proc(ah);
889
df23acaa
LR		 890 /* Revert chainmasks to their original values before NF cal */
891 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
892
00c86590
FF		 893 ath9k_hw_start_nfcal(ah, true);
894
df23acaa
LR		 895 /* Initialize list pointers */
896 ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
6497827f 897 ah->supp_cals = IQ_MISMATCH_CAL;
df23acaa 898
6497827f 899 if (ah->supp_cals & IQ_MISMATCH_CAL) {
df23acaa
LR		 900 INIT_CAL(&ah->iq_caldata);
901 INSERT_CAL(ah, &ah->iq_caldata);
226afe68
JP		 902 ath_dbg(common, ATH_DBG_CALIBRATE,
903 "enabling IQ Calibration.\n");
df23acaa
LR		 904 }
905
6497827f 906 if (ah->supp_cals & TEMP_COMP_CAL) {
df23acaa
LR		 907 INIT_CAL(&ah->tempCompCalData);
908 INSERT_CAL(ah, &ah->tempCompCalData);
226afe68
JP		 909 ath_dbg(common, ATH_DBG_CALIBRATE,
910 "enabling Temperature Compensation Calibration.\n");
df23acaa
LR		 911 }
912
913 /* Initialize current pointer to first element in list */
914 ah->cal_list_curr = ah->cal_list;
915
916 if (ah->cal_list_curr)
917 ath9k_hw_reset_calibration(ah, ah->cal_list_curr);
918
20bd2a09
FF		 919 if (ah->caldata)
920 ah->caldata->CalValid = 0;
df23acaa
LR		 921
922 return true;
77d6d39a
LR		 923}
924
795f5e2c
LR		 925void ar9003_hw_attach_calib_ops(struct ath_hw *ah)
926{
927 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
928 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
929
930 priv_ops->init_cal_settings = ar9003_hw_init_cal_settings;
931 priv_ops->init_cal = ar9003_hw_init_cal;
932 priv_ops->setup_calibration = ar9003_hw_setup_calibration;
795f5e2c
LR		 933
934 ops->calibrate = ar9003_hw_calibrate;
935}
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