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8525f280 LR |
1 | /* |
2 | * Copyright (c) 2010 Atheros Communications Inc. | |
3 | * | |
4 | * Permission to use, copy, modify, and/or distribute this software for any | |
5 | * purpose with or without fee is hereby granted, provided that the above | |
6 | * copyright notice and this permission notice appear in all copies. | |
7 | * | |
8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
15 | */ | |
16 | ||
17 | #include "hw.h" | |
da6f1d7f | 18 | #include "ar9003_phy.h" |
8525f280 LR |
19 | |
20 | /** | |
21 | * ar9003_hw_set_channel - set channel on single-chip device | |
22 | * @ah: atheros hardware structure | |
23 | * @chan: | |
24 | * | |
25 | * This is the function to change channel on single-chip devices, that is | |
26 | * all devices after ar9280. | |
27 | * | |
28 | * This function takes the channel value in MHz and sets | |
29 | * hardware channel value. Assumes writes have been enabled to analog bus. | |
30 | * | |
31 | * Actual Expression, | |
32 | * | |
33 | * For 2GHz channel, | |
34 | * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17) | |
35 | * (freq_ref = 40MHz) | |
36 | * | |
37 | * For 5GHz channel, | |
38 | * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10) | |
39 | * (freq_ref = 40MHz/(24>>amodeRefSel)) | |
40 | * | |
41 | * For 5GHz channels which are 5MHz spaced, | |
42 | * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17) | |
43 | * (freq_ref = 40MHz) | |
44 | */ | |
45 | static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) | |
46 | { | |
f7abf0c1 FF |
47 | u16 bMode, fracMode = 0, aModeRefSel = 0; |
48 | u32 freq, channelSel = 0, reg32 = 0; | |
49 | struct chan_centers centers; | |
50 | int loadSynthChannel; | |
51 | ||
52 | ath9k_hw_get_channel_centers(ah, chan, ¢ers); | |
53 | freq = centers.synth_center; | |
54 | ||
55 | if (freq < 4800) { /* 2 GHz, fractional mode */ | |
56 | channelSel = CHANSEL_2G(freq); | |
57 | /* Set to 2G mode */ | |
58 | bMode = 1; | |
59 | } else { | |
60 | channelSel = CHANSEL_5G(freq); | |
61 | /* Doubler is ON, so, divide channelSel by 2. */ | |
62 | channelSel >>= 1; | |
63 | /* Set to 5G mode */ | |
64 | bMode = 0; | |
65 | } | |
66 | ||
67 | /* Enable fractional mode for all channels */ | |
68 | fracMode = 1; | |
69 | aModeRefSel = 0; | |
70 | loadSynthChannel = 0; | |
71 | ||
72 | reg32 = (bMode << 29); | |
73 | REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); | |
74 | ||
75 | /* Enable Long shift Select for Synthesizer */ | |
76 | REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4, | |
77 | AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1); | |
78 | ||
79 | /* Program Synth. setting */ | |
80 | reg32 = (channelSel << 2) | (fracMode << 30) | | |
81 | (aModeRefSel << 28) | (loadSynthChannel << 31); | |
82 | REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); | |
83 | ||
84 | /* Toggle Load Synth channel bit */ | |
85 | loadSynthChannel = 1; | |
86 | reg32 = (channelSel << 2) | (fracMode << 30) | | |
87 | (aModeRefSel << 28) | (loadSynthChannel << 31); | |
88 | REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); | |
89 | ||
90 | ah->curchan = chan; | |
91 | ah->curchan_rad_index = -1; | |
92 | ||
8525f280 LR |
93 | return 0; |
94 | } | |
95 | ||
96 | /** | |
97 | * ar9003_hw_spur_mitigate - convert baseband spur frequency | |
98 | * @ah: atheros hardware structure | |
99 | * @chan: | |
100 | * | |
101 | * For single-chip solutions. Converts to baseband spur frequency given the | |
102 | * input channel frequency and compute register settings below. | |
103 | * | |
104 | * Spur mitigation for MRC CCK | |
105 | */ | |
106 | static void ar9003_hw_spur_mitigate(struct ath_hw *ah, | |
107 | struct ath9k_channel *chan) | |
108 | { | |
ca375554 FF |
109 | u32 spur_freq[4] = { 2420, 2440, 2464, 2480 }; |
110 | int cur_bb_spur, negative = 0, cck_spur_freq; | |
111 | int i; | |
112 | ||
113 | /* | |
114 | * Need to verify range +/- 10 MHz in control channel, otherwise spur | |
115 | * is out-of-band and can be ignored. | |
116 | */ | |
117 | ||
118 | for (i = 0; i < 4; i++) { | |
119 | negative = 0; | |
120 | cur_bb_spur = spur_freq[i] - chan->channel; | |
121 | ||
122 | if (cur_bb_spur < 0) { | |
123 | negative = 1; | |
124 | cur_bb_spur = -cur_bb_spur; | |
125 | } | |
126 | if (cur_bb_spur < 10) { | |
127 | cck_spur_freq = (int)((cur_bb_spur << 19) / 11); | |
128 | ||
129 | if (negative == 1) | |
130 | cck_spur_freq = -cck_spur_freq; | |
131 | ||
132 | cck_spur_freq = cck_spur_freq & 0xfffff; | |
133 | ||
134 | REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL, | |
135 | AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7); | |
136 | REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, | |
137 | AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f); | |
138 | REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, | |
139 | AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE, | |
140 | 0x2); | |
141 | REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, | |
142 | AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, | |
143 | 0x1); | |
144 | REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, | |
145 | AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, | |
146 | cck_spur_freq); | |
147 | ||
148 | return; | |
149 | } | |
150 | } | |
151 | ||
152 | REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL, | |
153 | AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5); | |
154 | REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, | |
155 | AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0); | |
156 | REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT, | |
157 | AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0); | |
8525f280 LR |
158 | } |
159 | ||
160 | static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah, | |
161 | struct ath9k_channel *chan) | |
162 | { | |
317d3328 FF |
163 | u32 pll; |
164 | ||
165 | pll = SM(0x5, AR_RTC_9300_PLL_REFDIV); | |
166 | ||
167 | if (chan && IS_CHAN_HALF_RATE(chan)) | |
168 | pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL); | |
169 | else if (chan && IS_CHAN_QUARTER_RATE(chan)) | |
170 | pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL); | |
171 | ||
172 | if (chan && IS_CHAN_5GHZ(chan)) { | |
173 | pll |= SM(0x28, AR_RTC_9300_PLL_DIV); | |
174 | ||
175 | /* | |
176 | * When doing fast clock, set PLL to 0x142c | |
177 | */ | |
178 | if (IS_CHAN_A_5MHZ_SPACED(chan)) | |
179 | pll = 0x142c; | |
180 | } else | |
181 | pll |= SM(0x2c, AR_RTC_9300_PLL_DIV); | |
182 | ||
183 | return pll; | |
8525f280 LR |
184 | } |
185 | ||
186 | static void ar9003_hw_set_channel_regs(struct ath_hw *ah, | |
187 | struct ath9k_channel *chan) | |
188 | { | |
189 | /* TODO */ | |
190 | } | |
191 | ||
192 | static void ar9003_hw_init_bb(struct ath_hw *ah, | |
193 | struct ath9k_channel *chan) | |
194 | { | |
195 | /* TODO */ | |
196 | } | |
197 | ||
198 | static int ar9003_hw_process_ini(struct ath_hw *ah, | |
199 | struct ath9k_channel *chan) | |
200 | { | |
201 | /* TODO */ | |
202 | return -1; | |
203 | } | |
204 | ||
205 | static void ar9003_hw_set_rfmode(struct ath_hw *ah, | |
206 | struct ath9k_channel *chan) | |
207 | { | |
208 | /* TODO */ | |
209 | } | |
210 | ||
211 | static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah) | |
212 | { | |
213 | /* TODO */ | |
214 | } | |
215 | ||
216 | static void ar9003_hw_set_delta_slope(struct ath_hw *ah, | |
217 | struct ath9k_channel *chan) | |
218 | { | |
219 | /* TODO */ | |
220 | } | |
221 | ||
222 | static bool ar9003_hw_rfbus_req(struct ath_hw *ah) | |
223 | { | |
224 | /* TODO */ | |
225 | return false; | |
226 | } | |
227 | ||
228 | static void ar9003_hw_rfbus_done(struct ath_hw *ah) | |
229 | { | |
230 | /* TODO */ | |
231 | } | |
232 | ||
233 | static void ar9003_hw_enable_rfkill(struct ath_hw *ah) | |
234 | { | |
235 | /* TODO */ | |
236 | } | |
237 | ||
238 | static void ar9003_hw_set_diversity(struct ath_hw *ah, bool value) | |
239 | { | |
240 | /* TODO */ | |
241 | } | |
242 | ||
243 | void ar9003_hw_attach_phy_ops(struct ath_hw *ah) | |
244 | { | |
245 | struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); | |
246 | ||
247 | priv_ops->rf_set_freq = ar9003_hw_set_channel; | |
248 | priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate; | |
249 | priv_ops->compute_pll_control = ar9003_hw_compute_pll_control; | |
250 | priv_ops->set_channel_regs = ar9003_hw_set_channel_regs; | |
251 | priv_ops->init_bb = ar9003_hw_init_bb; | |
252 | priv_ops->process_ini = ar9003_hw_process_ini; | |
253 | priv_ops->set_rfmode = ar9003_hw_set_rfmode; | |
254 | priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive; | |
255 | priv_ops->set_delta_slope = ar9003_hw_set_delta_slope; | |
256 | priv_ops->rfbus_req = ar9003_hw_rfbus_req; | |
257 | priv_ops->rfbus_done = ar9003_hw_rfbus_done; | |
258 | priv_ops->enable_rfkill = ar9003_hw_enable_rfkill; | |
259 | priv_ops->set_diversity = ar9003_hw_set_diversity; | |
260 | } |