]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - drivers/net/wireless/ath/ath9k/ar9003_phy.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge remote-tracking branches 'spi/topic/atmel', 'spi/topic/cadence', 'spi/topic...
[mirror_ubuntu-artful-kernel.git] / drivers / net / wireless / ath / ath9k / ar9003_phy.c
CommitLineData
8525f280 1/*
5b68138e 2 * Copyright (c) 2010-2011 Atheros Communications Inc.
8525f280
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
ee40fa06 17#include <linux/export.h>
8525f280 18#include "hw.h"
da6f1d7f 19#include "ar9003_phy.h"
8525f280 20
e36b27af
LR		 21static const int firstep_table[] =
22/* level: 0 1 2 3 4 5 6 7 8 */
23 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */
24
25static const int cycpwrThr1_table[] =
26/* level: 0 1 2 3 4 5 6 7 8 */
27 { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */
28
29/*
30 * register values to turn OFDM weak signal detection OFF
31 */
32static const int m1ThreshLow_off = 127;
33static const int m2ThreshLow_off = 127;
34static const int m1Thresh_off = 127;
35static const int m2Thresh_off = 127;
36static const int m2CountThr_off = 31;
37static const int m2CountThrLow_off = 63;
38static const int m1ThreshLowExt_off = 127;
39static const int m2ThreshLowExt_off = 127;
40static const int m1ThreshExt_off = 127;
41static const int m2ThreshExt_off = 127;
42
8525f280
LR		 43/**
44 * ar9003_hw_set_channel - set channel on single-chip device
45 * @ah: atheros hardware structure
46 * @chan:
47 *
48 * This is the function to change channel on single-chip devices, that is
e4922f2b 49 * for AR9300 family of chipsets.
8525f280
LR		 50 *
51 * This function takes the channel value in MHz and sets
52 * hardware channel value. Assumes writes have been enabled to analog bus.
53 *
54 * Actual Expression,
55 *
56 * For 2GHz channel,
57 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
58 * (freq_ref = 40MHz)
59 *
60 * For 5GHz channel,
61 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
62 * (freq_ref = 40MHz/(24>>amodeRefSel))
63 *
64 * For 5GHz channels which are 5MHz spaced,
65 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
66 * (freq_ref = 40MHz)
67 */
68static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
69{
f7abf0c1 70 u16 bMode, fracMode = 0, aModeRefSel = 0;
1a26cda8 71 u32 freq, chan_frac, div, channelSel = 0, reg32 = 0;
f7abf0c1
FF		 72 struct chan_centers centers;
73 int loadSynthChannel;
74
75 ath9k_hw_get_channel_centers(ah, chan, &centers);
76 freq = centers.synth_center;
77
78 if (freq < 4800) { /* 2 GHz, fractional mode */
5acb4b93 79 if (AR_SREV_9330(ah)) {
5acb4b93
GJ		 80 if (ah->is_clk_25mhz)
81 div = 75;
82 else
83 div = 120;
84
85 channelSel = (freq * 4) / div;
86 chan_frac = (((freq * 4) % div) * 0x20000) / div;
87 channelSel = (channelSel << 17) | chan_frac;
a4a2954f 88 } else if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
3dfd7f60 89 /*
1a26cda8
SM		 90 * freq_ref = 40 / (refdiva >> amoderefsel);
91 * where refdiva=1 and amoderefsel=0
3dfd7f60
VT		 92 * ndiv = ((chan_mhz * 4) / 3) / freq_ref;
93 * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000
94 */
95 channelSel = (freq * 4) / 120;
96 chan_frac = (((freq * 4) % 120) * 0x20000) / 120;
97 channelSel = (channelSel << 17) | chan_frac;
1a26cda8 98 } else if (AR_SREV_9340(ah)) {
17869f4f 99 if (ah->is_clk_25mhz) {
17869f4f
VT		 100 channelSel = (freq * 2) / 75;
101 chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
102 channelSel = (channelSel << 17) | chan_frac;
1a26cda8 103 } else {
17869f4f 104 channelSel = CHANSEL_2G(freq) >> 1;
1a26cda8 105 }
2c323058 106 } else if (AR_SREV_9550(ah) || AR_SREV_9531(ah)) {
1a26cda8
SM		 107 if (ah->is_clk_25mhz)
108 div = 75;
109 else
110 div = 120;
111
112 channelSel = (freq * 4) / div;
113 chan_frac = (((freq * 4) % div) * 0x20000) / div;
114 channelSel = (channelSel << 17) | chan_frac;
115 } else {
85dd0921 116 channelSel = CHANSEL_2G(freq);
1a26cda8 117 }
f7abf0c1
FF		 118 /* Set to 2G mode */
119 bMode = 1;
120 } else {
2c323058 121 if ((AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah)) &&
db4a3de9 122 ah->is_clk_25mhz) {
530275e5
FF		 123 channelSel = freq / 75;
124 chan_frac = ((freq % 75) * 0x20000) / 75;
17869f4f
VT		 125 channelSel = (channelSel << 17) | chan_frac;
126 } else {
127 channelSel = CHANSEL_5G(freq);
128 /* Doubler is ON, so, divide channelSel by 2. */
129 channelSel >>= 1;
130 }
f7abf0c1
FF		 131 /* Set to 5G mode */
132 bMode = 0;
133 }
134
135 /* Enable fractional mode for all channels */
136 fracMode = 1;
137 aModeRefSel = 0;
138 loadSynthChannel = 0;
139
140 reg32 = (bMode << 29);
141 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
142
143 /* Enable Long shift Select for Synthesizer */
144 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4,
145 AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1);
146
147 /* Program Synth. setting */
148 reg32 = (channelSel << 2) | (fracMode << 30) |
149 (aModeRefSel << 28) | (loadSynthChannel << 31);
150 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
151
152 /* Toggle Load Synth channel bit */
153 loadSynthChannel = 1;
154 reg32 = (channelSel << 2) | (fracMode << 30) |
155 (aModeRefSel << 28) | (loadSynthChannel << 31);
156 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
157
158 ah->curchan = chan;
f7abf0c1 159
8525f280
LR		 160 return 0;
161}
162
163/**
e36b27af 164 * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency
8525f280
LR		 165 * @ah: atheros hardware structure
166 * @chan:
167 *
168 * For single-chip solutions. Converts to baseband spur frequency given the
169 * input channel frequency and compute register settings below.
170 *
171 * Spur mitigation for MRC CCK
172 */
1547da37
LR		 173static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
174 struct ath9k_channel *chan)
8525f280 175{
07b2fa5a 176 static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
ca375554
FF		 177 int cur_bb_spur, negative = 0, cck_spur_freq;
178 int i;
d9a2545a 179 int range, max_spur_cnts, synth_freq;
4b5237cc 180 u8 *spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah, IS_CHAN_2GHZ(chan));
ca375554
FF		 181
182 /*
183 * Need to verify range +/- 10 MHz in control channel, otherwise spur
184 * is out-of-band and can be ignored.
185 */
186
8528f12e
GJ		 187 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
188 AR_SREV_9550(ah)) {
d9a2545a
VT		 189 if (spur_fbin_ptr[0] == 0) /* No spur */
190 return;
191 max_spur_cnts = 5;
192 if (IS_CHAN_HT40(chan)) {
193 range = 19;
194 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
195 AR_PHY_GC_DYN2040_PRI_CH) == 0)
196 synth_freq = chan->channel + 10;
197 else
198 synth_freq = chan->channel - 10;
199 } else {
200 range = 10;
201 synth_freq = chan->channel;
202 }
203 } else {
38df2f07 204 range = AR_SREV_9462(ah) ? 5 : 10;
d9a2545a
VT		 205 max_spur_cnts = 4;
206 synth_freq = chan->channel;
207 }
208
209 for (i = 0; i < max_spur_cnts; i++) {
38df2f07
RM		 210 if (AR_SREV_9462(ah) && (i == 0 || i == 3))
211 continue;
d43d04a9 212
ca375554 213 negative = 0;
8528f12e
GJ		 214 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
215 AR_SREV_9550(ah))
8edb254c
GJ		 216 cur_bb_spur = ath9k_hw_fbin2freq(spur_fbin_ptr[i],
217 IS_CHAN_2GHZ(chan));
d9a2545a 218 else
8edb254c 219 cur_bb_spur = spur_freq[i];
ca375554 220
8edb254c 221 cur_bb_spur -= synth_freq;
ca375554
FF		 222 if (cur_bb_spur < 0) {
223 negative = 1;
224 cur_bb_spur = -cur_bb_spur;
225 }
d9a2545a 226 if (cur_bb_spur < range) {
ca375554
FF		 227 cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
228
229 if (negative == 1)
230 cck_spur_freq = -cck_spur_freq;
231
232 cck_spur_freq = cck_spur_freq & 0xfffff;
233
234 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
235 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
236 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
237 AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
238 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
239 AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE,
240 0x2);
241 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
242 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT,
243 0x1);
244 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
245 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ,
246 cck_spur_freq);
247
248 return;
249 }
250 }
251
252 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
253 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
254 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
255 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0);
256 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
257 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
8525f280
LR		 258}
259
1547da37
LR		 260/* Clean all spur register fields */
261static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah)
262{
263 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
264 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0);
265 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
266 AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
267 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
268 AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
269 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
270 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0);
271 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
272 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0);
273 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
274 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0);
275 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
276 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0);
277 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
278 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0);
279 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
280 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0);
281
282 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
283 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0);
284 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
285 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0);
286 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
287 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0);
288 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
289 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0);
290 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
291 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0);
292 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
293 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0);
294 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
295 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0);
296 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
297 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0);
298 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
299 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0);
300 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
301 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
302}
303
304static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
305 int freq_offset,
306 int spur_freq_sd,
307 int spur_delta_phase,
d43d04a9
SM		 308 int spur_subchannel_sd,
309 int range,
310 int synth_freq)
1547da37
LR		 311{
312 int mask_index = 0;
313
314 /* OFDM Spur mitigation */
315 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
316 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1);
317 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
318 AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
319 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
320 AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
321 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
322 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd);
323 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
324 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1);
d43d04a9
SM		 325
326 if (!(AR_SREV_9565(ah) && range == 10 && synth_freq == 2437))
327 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
328 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1);
329
1547da37
LR		 330 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
331 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1);
332 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
333 AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
334 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
335 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);
336
23dd9b2a
FF		 337 if (!AR_SREV_9340(ah) &&
338 REG_READ_FIELD(ah, AR_PHY_MODE,
1547da37
LR		 339 AR_PHY_MODE_DYNAMIC) == 0x1)
340 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
341 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);
342
343 mask_index = (freq_offset << 4) / 5;
344 if (mask_index < 0)
345 mask_index = mask_index - 1;
346
347 mask_index = mask_index & 0x7f;
348
349 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
350 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1);
351 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
352 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1);
353 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
354 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1);
355 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
356 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index);
357 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
358 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index);
359 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
360 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index);
361 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
362 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc);
363 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
364 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc);
365 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
366 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
367 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
368 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
369}
370
d43d04a9
SM		 371static void ar9003_hw_spur_ofdm_9565(struct ath_hw *ah,
372 int freq_offset)
373{
374 int mask_index = 0;
375
376 mask_index = (freq_offset << 4) / 5;
377 if (mask_index < 0)
378 mask_index = mask_index - 1;
379
380 mask_index = mask_index & 0x7f;
381
382 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
383 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B,
384 mask_index);
385
386 /* A == B */
387 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B,
388 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A,
389 mask_index);
390
391 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
392 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B,
393 mask_index);
394 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
395 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_B, 0xe);
396 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
397 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_B, 0xe);
398
399 /* A == B */
400 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B,
401 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
402}
403
1547da37
LR		 404static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
405 struct ath9k_channel *chan,
d43d04a9
SM		 406 int freq_offset,
407 int range,
408 int synth_freq)
1547da37
LR		 409{
410 int spur_freq_sd = 0;
411 int spur_subchannel_sd = 0;
412 int spur_delta_phase = 0;
413
414 if (IS_CHAN_HT40(chan)) {
415 if (freq_offset < 0) {
416 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
417 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
418 spur_subchannel_sd = 1;
419 else
420 spur_subchannel_sd = 0;
421
9d1ceac5 422 spur_freq_sd = ((freq_offset + 10) << 9) / 11;
1547da37
LR		 423
424 } else {
425 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
426 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
427 spur_subchannel_sd = 0;
428 else
429 spur_subchannel_sd = 1;
430
9d1ceac5 431 spur_freq_sd = ((freq_offset - 10) << 9) / 11;
1547da37
LR		 432
433 }
434
435 spur_delta_phase = (freq_offset << 17) / 5;
436
437 } else {
438 spur_subchannel_sd = 0;
439 spur_freq_sd = (freq_offset << 9) /11;
440 spur_delta_phase = (freq_offset << 18) / 5;
441 }
442
443 spur_freq_sd = spur_freq_sd & 0x3ff;
444 spur_delta_phase = spur_delta_phase & 0xfffff;
445
446 ar9003_hw_spur_ofdm(ah,
447 freq_offset,
448 spur_freq_sd,
449 spur_delta_phase,
d43d04a9
SM		 450 spur_subchannel_sd,
451 range, synth_freq);
1547da37
LR		 452}
453
454/* Spur mitigation for OFDM */
455static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
456 struct ath9k_channel *chan)
457{
458 int synth_freq;
459 int range = 10;
460 int freq_offset = 0;
461 int mode;
462 u8* spurChansPtr;
463 unsigned int i;
464 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
465
466 if (IS_CHAN_5GHZ(chan)) {
467 spurChansPtr = &(eep->modalHeader5G.spurChans[0]);
468 mode = 0;
469 }
470 else {
471 spurChansPtr = &(eep->modalHeader2G.spurChans[0]);
472 mode = 1;
473 }
474
475 if (spurChansPtr[0] == 0)
476 return; /* No spur in the mode */
477
478 if (IS_CHAN_HT40(chan)) {
479 range = 19;
480 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
481 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
482 synth_freq = chan->channel - 10;
483 else
484 synth_freq = chan->channel + 10;
485 } else {
486 range = 10;
487 synth_freq = chan->channel;
488 }
489
490 ar9003_hw_spur_ofdm_clear(ah);
491
0f8e94d2 492 for (i = 0; i < AR_EEPROM_MODAL_SPURS && spurChansPtr[i]; i++) {
8edb254c
GJ		 493 freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i], mode);
494 freq_offset -= synth_freq;
1547da37 495 if (abs(freq_offset) < range) {
d43d04a9
SM		 496 ar9003_hw_spur_ofdm_work(ah, chan, freq_offset,
497 range, synth_freq);
498
499 if (AR_SREV_9565(ah) && (i < 4)) {
500 freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i + 1],
501 mode);
502 freq_offset -= synth_freq;
503 if (abs(freq_offset) < range)
504 ar9003_hw_spur_ofdm_9565(ah, freq_offset);
505 }
506
1547da37
LR		 507 break;
508 }
509 }
510}
511
512static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
513 struct ath9k_channel *chan)
514{
d43d04a9
SM		 515 if (!AR_SREV_9565(ah))
516 ar9003_hw_spur_mitigate_mrc_cck(ah, chan);
1547da37
LR		 517 ar9003_hw_spur_mitigate_ofdm(ah, chan);
518}
519
5fb9b1b9
FF		 520static u32 ar9003_hw_compute_pll_control_soc(struct ath_hw *ah,
521 struct ath9k_channel *chan)
522{
523 u32 pll;
524
525 pll = SM(0x5, AR_RTC_9300_SOC_PLL_REFDIV);
526
527 if (chan && IS_CHAN_HALF_RATE(chan))
528 pll |= SM(0x1, AR_RTC_9300_SOC_PLL_CLKSEL);
529 else if (chan && IS_CHAN_QUARTER_RATE(chan))
530 pll |= SM(0x2, AR_RTC_9300_SOC_PLL_CLKSEL);
531
532 pll |= SM(0x2c, AR_RTC_9300_SOC_PLL_DIV_INT);
533
534 return pll;
535}
536
8525f280
LR		 537static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
538 struct ath9k_channel *chan)
539{
317d3328
FF		 540 u32 pll;
541
542 pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
543
544 if (chan && IS_CHAN_HALF_RATE(chan))
545 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
546 else if (chan && IS_CHAN_QUARTER_RATE(chan))
547 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
548
14bc1104 549 pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
317d3328
FF		 550
551 return pll;
8525f280
LR		 552}
553
554static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
555 struct ath9k_channel *chan)
556{
cffb5e49
LR		 557 u32 phymode;
558 u32 enableDacFifo = 0;
559
560 enableDacFifo =
561 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO);
562
563 /* Enable 11n HT, 20 MHz */
8ad38d22 564 phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 |
cffb5e49
LR		 565 AR_PHY_GC_SHORT_GI_40 | enableDacFifo;
566
567 /* Configure baseband for dynamic 20/40 operation */
568 if (IS_CHAN_HT40(chan)) {
569 phymode |= AR_PHY_GC_DYN2040_EN;
570 /* Configure control (primary) channel at +-10MHz */
8896934c 571 if (IS_CHAN_HT40PLUS(chan))
cffb5e49
LR		 572 phymode |= AR_PHY_GC_DYN2040_PRI_CH;
573
574 }
575
576 /* make sure we preserve INI settings */
577 phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);
578 /* turn off Green Field detection for STA for now */
579 phymode &= ~AR_PHY_GC_GF_DETECT_EN;
580
581 REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
582
583 /* Configure MAC for 20/40 operation */
e4744ec7 584 ath9k_hw_set11nmac2040(ah, chan);
cffb5e49
LR		 585
586 /* global transmit timeout (25 TUs default)*/
587 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
588 /* carrier sense timeout */
589 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
8525f280
LR		 590}
591
592static void ar9003_hw_init_bb(struct ath_hw *ah,
593 struct ath9k_channel *chan)
594{
af914a9f
LR		 595 u32 synthDelay;
596
597 /*
598 * Wait for the frequency synth to settle (synth goes on
599 * via AR_PHY_ACTIVE_EN). Read the phy active delay register.
600 * Value is in 100ns increments.
601 */
602 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
af914a9f
LR		 603
604 /* Activate the PHY (includes baseband activate + synthesizer on) */
605 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
7c5adc8d 606 ath9k_hw_synth_delay(ah, chan, synthDelay);
8525f280
LR		 607}
608
4a8f1995 609void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
cffb5e49 610{
24171dd9 611 if (ah->caps.tx_chainmask == 5 || ah->caps.rx_chainmask == 5)
cffb5e49
LR		 612 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
613 AR_PHY_SWAP_ALT_CHAIN);
24171dd9
FF		 614
615 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
616 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
cffb5e49 617
ea066d5a 618 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7))
24171dd9 619 tx = 3;
ea066d5a 620
24171dd9 621 REG_WRITE(ah, AR_SELFGEN_MASK, tx);
cffb5e49
LR		 622}
623
624/*
625 * Override INI values with chip specific configuration.
626 */
627static void ar9003_hw_override_ini(struct ath_hw *ah)
628{
629 u32 val;
630
631 /*
632 * Set the RX_ABORT and RX_DIS and clear it only after
633 * RXE is set for MAC. This prevents frames with
634 * corrupted descriptor status.
635 */
636 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
637
638 /*
639 * For AR9280 and above, there is a new feature that allows
640 * Multicast search based on both MAC Address and Key ID. By default,
641 * this feature is enabled. But since the driver is not using this
642 * feature, we switch it off; otherwise multicast search based on
643 * MAC addr only will fail.
644 */
645 val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
9ef48932
SM		 646 val |= AR_AGG_WEP_ENABLE_FIX |
647 AR_AGG_WEP_ENABLE |
648 AR_PCU_MISC_MODE2_CFP_IGNORE;
649 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
bf3f204b 650
4b03f16e
SM		 651 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
652 REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE,
653 AR_GLB_SWREG_DISCONT_EN_BT_WLAN);
654
655 if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0,
656 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL))
657 ah->enabled_cals |= TX_IQ_CAL;
658 else
659 ah->enabled_cals &= ~TX_IQ_CAL;
660
4b03f16e 661 }
34d9b689
SM		 662
663 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE)
664 ah->enabled_cals |= TX_CL_CAL;
665 else
666 ah->enabled_cals &= ~TX_CL_CAL;
4e6ce4dc
MP		 667
668 if (AR_SREV_9340(ah) || AR_SREV_9531(ah) || AR_SREV_9550(ah)) {
669 if (ah->is_clk_25mhz) {
670 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
671 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
672 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
673 } else {
674 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
675 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
676 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
677 }
678 udelay(100);
679 }
cffb5e49
LR		 680}
681
682static void ar9003_hw_prog_ini(struct ath_hw *ah,
683 struct ar5416IniArray *iniArr,
684 int column)
685{
686 unsigned int i, regWrites = 0;
687
688 /* New INI format: Array may be undefined (pre, core, post arrays) */
689 if (!iniArr->ia_array)
690 return;
691
692 /*
693 * New INI format: Pre, core, and post arrays for a given subsystem
694 * may be modal (> 2 columns) or non-modal (2 columns). Determine if
695 * the array is non-modal and force the column to 1.
696 */
697 if (column >= iniArr->ia_columns)
698 column = 1;
699
700 for (i = 0; i < iniArr->ia_rows; i++) {
701 u32 reg = INI_RA(iniArr, i, 0);
702 u32 val = INI_RA(iniArr, i, column);
703
7e68b746 704 REG_WRITE(ah, reg, val);
b2ccc507 705
cffb5e49
LR		 706 DO_DELAY(regWrites);
707 }
708}
709
8bc45c6b
GJ		 710static int ar9550_hw_get_modes_txgain_index(struct ath_hw *ah,
711 struct ath9k_channel *chan)
712{
713 int ret;
714
8896934c
FF		 715 if (IS_CHAN_2GHZ(chan)) {
716 if (IS_CHAN_HT40(chan))
717 return 7;
8bc45c6b 718 else
8896934c
FF		 719 return 8;
720 }
8bc45c6b 721
8896934c
FF		 722 if (chan->channel <= 5350)
723 ret = 1;
724 else if ((chan->channel > 5350) && (chan->channel <= 5600))
725 ret = 3;
726 else
727 ret = 5;
8bc45c6b 728
8896934c
FF		 729 if (IS_CHAN_HT40(chan))
730 ret++;
8bc45c6b
GJ		 731
732 return ret;
733}
734
6fcbe538
SM		 735static void ar9003_doubler_fix(struct ath_hw *ah)
736{
737 if (AR_SREV_9300(ah) || AR_SREV_9580(ah) || AR_SREV_9550(ah)) {
738 REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2,
739 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
740 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0);
741 REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2,
742 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
743 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0);
744 REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2,
745 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
746 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0);
747
748 udelay(200);
749
750 REG_CLR_BIT(ah, AR_PHY_65NM_CH0_RXTX2,
751 AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK);
752 REG_CLR_BIT(ah, AR_PHY_65NM_CH1_RXTX2,
753 AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK);
754 REG_CLR_BIT(ah, AR_PHY_65NM_CH2_RXTX2,
755 AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK);
756
757 udelay(1);
758
759 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX2,
760 AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1);
761 REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX2,
762 AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1);
763 REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX2,
764 AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1);
765
766 udelay(200);
767
768 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH12,
769 AR_PHY_65NM_CH0_SYNTH12_VREFMUL3, 0xf);
770
771 REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2, 0,
772 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
773 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S);
774 REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2, 0,
775 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
776 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S);
777 REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2, 0,
778 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
779 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S);
780 }
781}
782
8525f280
LR		 783static int ar9003_hw_process_ini(struct ath_hw *ah,
784 struct ath9k_channel *chan)
785{
cffb5e49 786 unsigned int regWrites = 0, i;
0ff2b5c0 787 u32 modesIndex;
cffb5e49 788
8896934c
FF		 789 if (IS_CHAN_5GHZ(chan))
790 modesIndex = IS_CHAN_HT40(chan) ? 2 : 1;
791 else
792 modesIndex = IS_CHAN_HT40(chan) ? 3 : 4;
cffb5e49 793
51dbd0a8
SM		 794 /*
795 * SOC, MAC, BB, RADIO initvals.
796 */
cffb5e49
LR		 797 for (i = 0; i < ATH_INI_NUM_SPLIT; i++) {
798 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex);
799 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
800 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
801 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
2b5e54e2 802 if (i == ATH_INI_POST && AR_SREV_9462_20_OR_LATER(ah))
2577c6e8
SB		 803 ar9003_hw_prog_ini(ah,
804 &ah->ini_radio_post_sys2ant,
805 modesIndex);
cffb5e49
LR		 806 }
807
6fcbe538
SM		 808 ar9003_doubler_fix(ah);
809
51dbd0a8
SM		 810 /*
811 * RXGAIN initvals.
812 */
cffb5e49 813 REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
51dbd0a8 814
2b5e54e2 815 if (AR_SREV_9462_20_OR_LATER(ah)) {
c177fabe
SM		 816 /*
817 * CUS217 mix LNA mode.
818 */
819 if (ar9003_hw_get_rx_gain_idx(ah) == 2) {
820 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core,
821 1, regWrites);
822 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
823 modesIndex, regWrites);
824 }
825
51dbd0a8
SM		 826 /*
827 * 5G-XLNA
828 */
829 if ((ar9003_hw_get_rx_gain_idx(ah) == 2) ||
830 (ar9003_hw_get_rx_gain_idx(ah) == 3)) {
831 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_5g_xlna,
832 modesIndex, regWrites);
833 }
834 }
835
8bc45c6b
GJ		 836 if (AR_SREV_9550(ah))
837 REG_WRITE_ARRAY(&ah->ini_modes_rx_gain_bounds, modesIndex,
838 regWrites);
839
51dbd0a8
SM		 840 /*
841 * TXGAIN initvals.
842 */
2c323058
SM		 843 if (AR_SREV_9550(ah) || AR_SREV_9531(ah)) {
844 int modes_txgain_index = 1;
845
846 if (AR_SREV_9550(ah))
847 modes_txgain_index = ar9550_hw_get_modes_txgain_index(ah, chan);
8bc45c6b 848
8bc45c6b
GJ		 849 if (modes_txgain_index < 0)
850 return -EINVAL;
851
852 REG_WRITE_ARRAY(&ah->iniModesTxGain, modes_txgain_index,
853 regWrites);
854 } else {
855 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
856 }
cffb5e49
LR		 857
858 /*
859 * For 5GHz channels requiring Fast Clock, apply
860 * different modal values.
861 */
6b42e8d0 862 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
c7d36f9f 863 REG_WRITE_ARRAY(&ah->iniModesFastClock,
cffb5e49
LR		 864 modesIndex, regWrites);
865
51dbd0a8
SM		 866 /*
867 * Clock frequency initvals.
868 */
c7d36f9f 869 REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites);
d89baac8 870
51dbd0a8
SM		 871 /*
872 * JAPAN regulatory.
873 */
9951c4d0 874 if (chan->channel == 2484)
57527f8d 875 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1);
9951c4d0 876
5f0c04ea 877 ah->modes_index = modesIndex;
cffb5e49
LR		 878 ar9003_hw_override_ini(ah);
879 ar9003_hw_set_channel_regs(ah, chan);
880 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
64ea57d0 881 ath9k_hw_apply_txpower(ah, chan, false);
cffb5e49
LR		 882
883 return 0;
8525f280
LR		 884}
885
886static void ar9003_hw_set_rfmode(struct ath_hw *ah,
887 struct ath9k_channel *chan)
888{
af914a9f
LR		 889 u32 rfMode = 0;
890
891 if (chan == NULL)
892 return;
893
1a5e6326
FF		 894 if (IS_CHAN_2GHZ(chan))
895 rfMode |= AR_PHY_MODE_DYNAMIC;
896 else
897 rfMode |= AR_PHY_MODE_OFDM;
af914a9f 898
6b42e8d0 899 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
af914a9f
LR		 900 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
901
3e61d3f9
FF		 902 if (rfMode & (AR_PHY_MODE_QUARTER | AR_PHY_MODE_HALF))
903 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
904 AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW, 3);
905
af914a9f 906 REG_WRITE(ah, AR_PHY_MODE, rfMode);
8525f280
LR		 907}
908
909static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
910{
af914a9f 911 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
8525f280
LR		 912}
913
914static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
915 struct ath9k_channel *chan)
916{
af914a9f
LR		 917 u32 coef_scaled, ds_coef_exp, ds_coef_man;
918 u32 clockMhzScaled = 0x64000000;
919 struct chan_centers centers;
920
921 /*
922 * half and quarter rate can divide the scaled clock by 2 or 4
923 * scale for selected channel bandwidth
924 */
925 if (IS_CHAN_HALF_RATE(chan))
926 clockMhzScaled = clockMhzScaled >> 1;
927 else if (IS_CHAN_QUARTER_RATE(chan))
928 clockMhzScaled = clockMhzScaled >> 2;
929
930 /*
931 * ALGO -> coef = 1e8/fcarrier*fclock/40;
932 * scaled coef to provide precision for this floating calculation
933 */
934 ath9k_hw_get_channel_centers(ah, chan, &centers);
935 coef_scaled = clockMhzScaled / centers.synth_center;
936
937 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
938 &ds_coef_exp);
939
940 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
941 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
942 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
943 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
944
945 /*
946 * For Short GI,
947 * scaled coeff is 9/10 that of normal coeff
948 */
949 coef_scaled = (9 * coef_scaled) / 10;
950
951 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
952 &ds_coef_exp);
953
954 /* for short gi */
955 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
956 AR_PHY_SGI_DSC_MAN, ds_coef_man);
957 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
958 AR_PHY_SGI_DSC_EXP, ds_coef_exp);
8525f280
LR		 959}
960
961static bool ar9003_hw_rfbus_req(struct ath_hw *ah)
962{
af914a9f
LR		 963 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
964 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
965 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
8525f280
LR		 966}
967
af914a9f
LR		 968/*
969 * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN).
970 * Read the phy active delay register. Value is in 100ns increments.
971 */
8525f280
LR		 972static void ar9003_hw_rfbus_done(struct ath_hw *ah)
973{
af914a9f 974 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
af914a9f 975
7c5adc8d 976 ath9k_hw_synth_delay(ah, ah->curchan, synthDelay);
af914a9f
LR		 977
978 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
8525f280
LR		 979}
980
c16fcb49
FF		 981static bool ar9003_hw_ani_control(struct ath_hw *ah,
982 enum ath9k_ani_cmd cmd, int param)
983{
af914a9f 984 struct ath_common *common = ath9k_hw_common(ah);
e36b27af 985 struct ath9k_channel *chan = ah->curchan;
c24bd362 986 struct ar5416AniState *aniState = &ah->ani;
ff23e084
SM		 987 int m1ThreshLow, m2ThreshLow;
988 int m1Thresh, m2Thresh;
989 int m2CountThr, m2CountThrLow;
990 int m1ThreshLowExt, m2ThreshLowExt;
991 int m1ThreshExt, m2ThreshExt;
e36b27af 992 s32 value, value2;
af914a9f
LR		 993
994 switch (cmd & ah->ani_function) {
af914a9f 995 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
e36b27af
LR		 996 /*
997 * on == 1 means ofdm weak signal detection is ON
998 * on == 1 is the default, for less noise immunity
999 *
1000 * on == 0 means ofdm weak signal detection is OFF
1001 * on == 0 means more noise imm
1002 */
af914a9f 1003 u32 on = param ? 1 : 0;
af914a9f 1004
ff23e084
SM		 1005 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
1006 goto skip_ws_det;
1007
1008 m1ThreshLow = on ?
1009 aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
1010 m2ThreshLow = on ?
1011 aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
1012 m1Thresh = on ?
1013 aniState->iniDef.m1Thresh : m1Thresh_off;
1014 m2Thresh = on ?
1015 aniState->iniDef.m2Thresh : m2Thresh_off;
1016 m2CountThr = on ?
1017 aniState->iniDef.m2CountThr : m2CountThr_off;
1018 m2CountThrLow = on ?
1019 aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
1020 m1ThreshLowExt = on ?
1021 aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
1022 m2ThreshLowExt = on ?
1023 aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
1024 m1ThreshExt = on ?
1025 aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
1026 m2ThreshExt = on ?
1027 aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
1028
1029 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1030 AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
1031 m1ThreshLow);
1032 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1033 AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
1034 m2ThreshLow);
1035 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1036 AR_PHY_SFCORR_M1_THRESH,
1037 m1Thresh);
1038 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1039 AR_PHY_SFCORR_M2_THRESH,
1040 m2Thresh);
1041 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1042 AR_PHY_SFCORR_M2COUNT_THR,
1043 m2CountThr);
1044 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1045 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
1046 m2CountThrLow);
1047 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1048 AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
1049 m1ThreshLowExt);
1050 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1051 AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
1052 m2ThreshLowExt);
1053 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1054 AR_PHY_SFCORR_EXT_M1_THRESH,
1055 m1ThreshExt);
1056 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1057 AR_PHY_SFCORR_EXT_M2_THRESH,
1058 m2ThreshExt);
1059skip_ws_det:
af914a9f
LR		 1060 if (on)
1061 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
1062 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1063 else
1064 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
1065 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1066
7067e701 1067 if (on != aniState->ofdmWeakSigDetect) {
d2182b69 1068 ath_dbg(common, ANI,
226afe68
JP		 1069 "** ch %d: ofdm weak signal: %s=>%s\n",
1070 chan->channel,
7067e701 1071 aniState->ofdmWeakSigDetect ?
226afe68
JP		 1072 "on" : "off",
1073 on ? "on" : "off");
af914a9f
LR		 1074 if (on)
1075 ah->stats.ast_ani_ofdmon++;
1076 else
1077 ah->stats.ast_ani_ofdmoff++;
7067e701 1078 aniState->ofdmWeakSigDetect = on;
af914a9f
LR		 1079 }
1080 break;
1081 }
af914a9f 1082 case ATH9K_ANI_FIRSTEP_LEVEL:{
af914a9f
LR		 1083 u32 level = param;
1084
e36b27af 1085 if (level >= ARRAY_SIZE(firstep_table)) {
d2182b69 1086 ath_dbg(common, ANI,
226afe68
JP		 1087 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",
1088 level, ARRAY_SIZE(firstep_table));
af914a9f
LR		 1089 return false;
1090 }
e36b27af
LR		 1091
1092 /*
1093 * make register setting relative to default
1094 * from INI file & cap value
1095 */
1096 value = firstep_table[level] -
465dce62 1097 firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
e36b27af
LR		 1098 aniState->iniDef.firstep;
1099 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1100 value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1101 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1102 value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
af914a9f
LR		 1103 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1104 AR_PHY_FIND_SIG_FIRSTEP,
e36b27af
LR		 1105 value);
1106 /*
1107 * we need to set first step low register too
1108 * make register setting relative to default
1109 * from INI file & cap value
1110 */
1111 value2 = firstep_table[level] -
465dce62 1112 firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
e36b27af
LR		 1113 aniState->iniDef.firstepLow;
1114 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1115 value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1116 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1117 value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1118
1119 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
1120 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2);
1121
1122 if (level != aniState->firstepLevel) {
d2182b69 1123 ath_dbg(common, ANI,
226afe68
JP		 1124 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
1125 chan->channel,
1126 aniState->firstepLevel,
1127 level,
465dce62 1128 ATH9K_ANI_FIRSTEP_LVL,
226afe68
JP		 1129 value,
1130 aniState->iniDef.firstep);
d2182b69 1131 ath_dbg(common, ANI,
226afe68
JP		 1132 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
1133 chan->channel,
1134 aniState->firstepLevel,
1135 level,
465dce62 1136 ATH9K_ANI_FIRSTEP_LVL,
226afe68
JP		 1137 value2,
1138 aniState->iniDef.firstepLow);
e36b27af
LR		 1139 if (level > aniState->firstepLevel)
1140 ah->stats.ast_ani_stepup++;
1141 else if (level < aniState->firstepLevel)
1142 ah->stats.ast_ani_stepdown++;
1143 aniState->firstepLevel = level;
1144 }
af914a9f
LR		 1145 break;
1146 }
1147 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
af914a9f
LR		 1148 u32 level = param;
1149
e36b27af 1150 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
d2182b69 1151 ath_dbg(common, ANI,
226afe68
JP		 1152 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",
1153 level, ARRAY_SIZE(cycpwrThr1_table));
af914a9f
LR		 1154 return false;
1155 }
e36b27af
LR		 1156 /*
1157 * make register setting relative to default
1158 * from INI file & cap value
1159 */
1160 value = cycpwrThr1_table[level] -
465dce62 1161 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
e36b27af
LR		 1162 aniState->iniDef.cycpwrThr1;
1163 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1164 value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1165 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1166 value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
af914a9f
LR		 1167 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
1168 AR_PHY_TIMING5_CYCPWR_THR1,
e36b27af
LR		 1169 value);
1170
1171 /*
1172 * set AR_PHY_EXT_CCA for extension channel
1173 * make register setting relative to default
1174 * from INI file & cap value
1175 */
1176 value2 = cycpwrThr1_table[level] -
465dce62 1177 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
e36b27af
LR		 1178 aniState->iniDef.cycpwrThr1Ext;
1179 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1180 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1181 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1182 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1183 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
1184 AR_PHY_EXT_CYCPWR_THR1, value2);
1185
1186 if (level != aniState->spurImmunityLevel) {
d2182b69 1187 ath_dbg(common, ANI,
226afe68
JP		 1188 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
1189 chan->channel,
1190 aniState->spurImmunityLevel,
1191 level,
465dce62 1192 ATH9K_ANI_SPUR_IMMUNE_LVL,
226afe68
JP		 1193 value,
1194 aniState->iniDef.cycpwrThr1);
d2182b69 1195 ath_dbg(common, ANI,
226afe68
JP		 1196 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
1197 chan->channel,
1198 aniState->spurImmunityLevel,
1199 level,
465dce62 1200 ATH9K_ANI_SPUR_IMMUNE_LVL,
226afe68
JP		 1201 value2,
1202 aniState->iniDef.cycpwrThr1Ext);
e36b27af
LR		 1203 if (level > aniState->spurImmunityLevel)
1204 ah->stats.ast_ani_spurup++;
1205 else if (level < aniState->spurImmunityLevel)
1206 ah->stats.ast_ani_spurdown++;
1207 aniState->spurImmunityLevel = level;
1208 }
af914a9f
LR		 1209 break;
1210 }
e36b27af
LR		 1211 case ATH9K_ANI_MRC_CCK:{
1212 /*
1213 * is_on == 1 means MRC CCK ON (default, less noise imm)
1214 * is_on == 0 means MRC CCK is OFF (more noise imm)
1215 */
1216 bool is_on = param ? 1 : 0;
a1c781bb
FF		 1217
1218 if (ah->caps.rx_chainmask == 1)
1219 break;
1220
e36b27af
LR		 1221 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1222 AR_PHY_MRC_CCK_ENABLE, is_on);
1223 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1224 AR_PHY_MRC_CCK_MUX_REG, is_on);
81b67fd6 1225 if (is_on != aniState->mrcCCK) {
d2182b69 1226 ath_dbg(common, ANI, "** ch %d: MRC CCK: %s=>%s\n",
226afe68 1227 chan->channel,
81b67fd6 1228 aniState->mrcCCK ? "on" : "off",
226afe68 1229 is_on ? "on" : "off");
e36b27af
LR		 1230 if (is_on)
1231 ah->stats.ast_ani_ccklow++;
1232 else
1233 ah->stats.ast_ani_cckhigh++;
81b67fd6 1234 aniState->mrcCCK = is_on;
e36b27af
LR		 1235 }
1236 break;
1237 }
af914a9f 1238 default:
d2182b69 1239 ath_dbg(common, ANI, "invalid cmd %u\n", cmd);
af914a9f
LR		 1240 return false;
1241 }
1242
d2182b69 1243 ath_dbg(common, ANI,
226afe68
JP		 1244 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1245 aniState->spurImmunityLevel,
7067e701 1246 aniState->ofdmWeakSigDetect ? "on" : "off",
226afe68 1247 aniState->firstepLevel,
81b67fd6 1248 aniState->mrcCCK ? "on" : "off",
226afe68
JP		 1249 aniState->listenTime,
1250 aniState->ofdmPhyErrCount,
1251 aniState->cckPhyErrCount);
af914a9f 1252 return true;
c16fcb49
FF		 1253}
1254
641d9921
FF		 1255static void ar9003_hw_do_getnf(struct ath_hw *ah,
1256 int16_t nfarray[NUM_NF_READINGS])
1257{
b06af7a5
VT		 1258#define AR_PHY_CH_MINCCA_PWR 0x1FF00000
1259#define AR_PHY_CH_MINCCA_PWR_S 20
1260#define AR_PHY_CH_EXT_MINCCA_PWR 0x01FF0000
1261#define AR_PHY_CH_EXT_MINCCA_PWR_S 16
641d9921 1262
b06af7a5
VT		 1263 int16_t nf;
1264 int i;
866b7780 1265
b06af7a5
VT		 1266 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1267 if (ah->rxchainmask & BIT(i)) {
1268 nf = MS(REG_READ(ah, ah->nf_regs[i]),
1269 AR_PHY_CH_MINCCA_PWR);
1270 nfarray[i] = sign_extend32(nf, 8);
641d9921 1271
b06af7a5
VT		 1272 if (IS_CHAN_HT40(ah->curchan)) {
1273 u8 ext_idx = AR9300_MAX_CHAINS + i;
641d9921 1274
b06af7a5
VT		 1275 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]),
1276 AR_PHY_CH_EXT_MINCCA_PWR);
1277 nfarray[ext_idx] = sign_extend32(nf, 8);
1278 }
1279 }
1280 }
641d9921
FF		 1281}
1282
f2552e28 1283static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
641d9921 1284{
f2552e28
FF		 1285 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
1286 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
ae245cde 1287 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ;
f2552e28
FF		 1288 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
1289 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
1290 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ;
ae245cde
SM		 1291
1292 if (AR_SREV_9330(ah))
1293 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ;
1294
a4a2954f 1295 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
ae245cde
SM		 1296 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ;
1297 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9462_2GHZ;
1298 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ;
1299 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9462_5GHZ;
1300 }
641d9921
FF		 1301}
1302
e36b27af
LR		 1303/*
1304 * Initialize the ANI register values with default (ini) values.
1305 * This routine is called during a (full) hardware reset after
1306 * all the registers are initialised from the INI.
1307 */
1308static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
1309{
1310 struct ar5416AniState *aniState;
1311 struct ath_common *common = ath9k_hw_common(ah);
1312 struct ath9k_channel *chan = ah->curchan;
1313 struct ath9k_ani_default *iniDef;
e36b27af
LR		 1314 u32 val;
1315
c24bd362 1316 aniState = &ah->ani;
e36b27af
LR		 1317 iniDef = &aniState->iniDef;
1318
8896934c 1319 ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz\n",
226afe68
JP		 1320 ah->hw_version.macVersion,
1321 ah->hw_version.macRev,
1322 ah->opmode,
8896934c 1323 chan->channel);
e36b27af
LR		 1324
1325 val = REG_READ(ah, AR_PHY_SFCORR);
1326 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1327 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1328 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1329
1330 val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1331 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1332 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1333 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1334
1335 val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1336 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1337 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1338 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1339 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1340 iniDef->firstep = REG_READ_FIELD(ah,
1341 AR_PHY_FIND_SIG,
1342 AR_PHY_FIND_SIG_FIRSTEP);
1343 iniDef->firstepLow = REG_READ_FIELD(ah,
1344 AR_PHY_FIND_SIG_LOW,
1345 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW);
1346 iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1347 AR_PHY_TIMING5,
1348 AR_PHY_TIMING5_CYCPWR_THR1);
1349 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1350 AR_PHY_EXT_CCA,
1351 AR_PHY_EXT_CYCPWR_THR1);
1352
1353 /* these levels just got reset to defaults by the INI */
465dce62
FF		 1354 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
1355 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
4f4395c6 1356 aniState->ofdmWeakSigDetect = true;
81b67fd6 1357 aniState->mrcCCK = true;
e36b27af
LR		 1358}
1359
4e8c14e9
FF		 1360static void ar9003_hw_set_radar_params(struct ath_hw *ah,
1361 struct ath_hw_radar_conf *conf)
1362{
4a878b9f 1363 unsigned int regWrites = 0;
4e8c14e9
FF		 1364 u32 radar_0 = 0, radar_1 = 0;
1365
1366 if (!conf) {
1367 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
1368 return;
1369 }
1370
1371 radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
1372 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1373 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
1374 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
1375 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
1376 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
1377
1378 radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
1379 radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
1380 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
1381 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
1382 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
1383
1384 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1385 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1386 if (conf->ext_channel)
1387 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1388 else
1389 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
4a878b9f
SM		 1390
1391 if (AR_SREV_9300(ah) || AR_SREV_9340(ah) || AR_SREV_9580(ah)) {
1392 REG_WRITE_ARRAY(&ah->ini_dfs,
1393 IS_CHAN_HT40(ah->curchan) ? 2 : 1, regWrites);
1394 }
4e8c14e9
FF		 1395}
1396
c5d0855a
FF		 1397static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
1398{
1399 struct ath_hw_radar_conf *conf = &ah->radar_conf;
1400
1401 conf->fir_power = -28;
1402 conf->radar_rssi = 0;
1403 conf->pulse_height = 10;
1404 conf->pulse_rssi = 24;
1405 conf->pulse_inband = 8;
1406 conf->pulse_maxlen = 255;
1407 conf->pulse_inband_step = 12;
1408 conf->radar_inband = 8;
1409}
1410
6bcbc062 1411static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah,
9aa49ea3 1412 struct ath_hw_antcomb_conf *antconf)
6bcbc062
MSS		 1413{
1414 u32 regval;
1415
1416 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
9aa49ea3
SM		 1417 antconf->main_lna_conf = (regval & AR_PHY_ANT_DIV_MAIN_LNACONF) >>
1418 AR_PHY_ANT_DIV_MAIN_LNACONF_S;
1419 antconf->alt_lna_conf = (regval & AR_PHY_ANT_DIV_ALT_LNACONF) >>
1420 AR_PHY_ANT_DIV_ALT_LNACONF_S;
1421 antconf->fast_div_bias = (regval & AR_PHY_ANT_FAST_DIV_BIAS) >>
1422 AR_PHY_ANT_FAST_DIV_BIAS_S;
cd0ed1b5 1423
c4cf2c58 1424 if (AR_SREV_9330_11(ah)) {
f96bd2ad 1425 antconf->lna1_lna2_switch_delta = -1;
c4cf2c58
GJ		 1426 antconf->lna1_lna2_delta = -9;
1427 antconf->div_group = 1;
1428 } else if (AR_SREV_9485(ah)) {
f96bd2ad 1429 antconf->lna1_lna2_switch_delta = -1;
cd0ed1b5
GJ		 1430 antconf->lna1_lna2_delta = -9;
1431 antconf->div_group = 2;
5317c9c3 1432 } else if (AR_SREV_9565(ah)) {
f96bd2ad
SM		 1433 antconf->lna1_lna2_switch_delta = 3;
1434 antconf->lna1_lna2_delta = -9;
5317c9c3 1435 antconf->div_group = 3;
cd0ed1b5 1436 } else {
f96bd2ad 1437 antconf->lna1_lna2_switch_delta = -1;
cd0ed1b5
GJ		 1438 antconf->lna1_lna2_delta = -3;
1439 antconf->div_group = 0;
1440 }
6bcbc062
MSS		 1441}
1442
1443static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah,
1444 struct ath_hw_antcomb_conf *antconf)
1445{
1446 u32 regval;
1447
1448 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
9aa49ea3
SM		 1449 regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1450 AR_PHY_ANT_DIV_ALT_LNACONF |
1451 AR_PHY_ANT_FAST_DIV_BIAS |
1452 AR_PHY_ANT_DIV_MAIN_GAINTB |
1453 AR_PHY_ANT_DIV_ALT_GAINTB);
1454 regval |= ((antconf->main_lna_conf << AR_PHY_ANT_DIV_MAIN_LNACONF_S)
1455 & AR_PHY_ANT_DIV_MAIN_LNACONF);
1456 regval |= ((antconf->alt_lna_conf << AR_PHY_ANT_DIV_ALT_LNACONF_S)
1457 & AR_PHY_ANT_DIV_ALT_LNACONF);
1458 regval |= ((antconf->fast_div_bias << AR_PHY_ANT_FAST_DIV_BIAS_S)
1459 & AR_PHY_ANT_FAST_DIV_BIAS);
1460 regval |= ((antconf->main_gaintb << AR_PHY_ANT_DIV_MAIN_GAINTB_S)
1461 & AR_PHY_ANT_DIV_MAIN_GAINTB);
1462 regval |= ((antconf->alt_gaintb << AR_PHY_ANT_DIV_ALT_GAINTB_S)
1463 & AR_PHY_ANT_DIV_ALT_GAINTB);
6bcbc062
MSS		 1464
1465 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1466}
1467
36e8825e
SM		 1468#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
1469
d8d7744b 1470static void ar9003_hw_set_bt_ant_diversity(struct ath_hw *ah, bool enable)
362cd03f 1471{
84893817 1472 struct ath9k_hw_capabilities *pCap = &ah->caps;
362cd03f
SM		 1473 u8 ant_div_ctl1;
1474 u32 regval;
1475
84893817 1476 if (!AR_SREV_9485(ah) && !AR_SREV_9565(ah))
362cd03f
SM		 1477 return;
1478
84893817
SM		 1479 if (AR_SREV_9485(ah)) {
1480 regval = ar9003_hw_ant_ctrl_common_2_get(ah,
1481 IS_CHAN_2GHZ(ah->curchan));
1482 if (enable) {
1483 regval &= ~AR_SWITCH_TABLE_COM2_ALL;
1484 regval |= ah->config.ant_ctrl_comm2g_switch_enable;
1485 }
1486 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2,
1487 AR_SWITCH_TABLE_COM2_ALL, regval);
1488 }
1489
362cd03f
SM		 1490 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
1491
84893817
SM		 1492 /*
1493 * Set MAIN/ALT LNA conf.
1494 * Set MAIN/ALT gain_tb.
1495 */
362cd03f
SM		 1496 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1497 regval &= (~AR_ANT_DIV_CTRL_ALL);
1498 regval |= (ant_div_ctl1 & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
362cd03f
SM		 1499 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1500
fb5a2dcb 1501 if (AR_SREV_9485_11_OR_LATER(ah)) {
84893817
SM		 1502 /*
1503 * Enable LNA diversity.
1504 */
362cd03f 1505 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
84893817
SM		 1506 regval &= ~AR_PHY_ANT_DIV_LNADIV;
1507 regval |= ((ant_div_ctl1 >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S;
1508 if (enable)
1509 regval |= AR_ANT_DIV_ENABLE;
1510
362cd03f 1511 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
84893817
SM		 1512
1513 /*
1514 * Enable fast antenna diversity.
1515 */
1516 regval = REG_READ(ah, AR_PHY_CCK_DETECT);
1517 regval &= ~AR_FAST_DIV_ENABLE;
1518 regval |= ((ant_div_ctl1 >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S;
1519 if (enable)
1520 regval |= AR_FAST_DIV_ENABLE;
1521
1522 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
1523
1524 if (pCap->hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) {
1525 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1526 regval &= (~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1527 AR_PHY_ANT_DIV_ALT_LNACONF |
1528 AR_PHY_ANT_DIV_ALT_GAINTB |
1529 AR_PHY_ANT_DIV_MAIN_GAINTB));
1530 /*
1531 * Set MAIN to LNA1 and ALT to LNA2 at the
1532 * beginning.
1533 */
1534 regval |= (ATH_ANT_DIV_COMB_LNA1 <<
1535 AR_PHY_ANT_DIV_MAIN_LNACONF_S);
1536 regval |= (ATH_ANT_DIV_COMB_LNA2 <<
1537 AR_PHY_ANT_DIV_ALT_LNACONF_S);
1538 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1539 }
1540 } else if (AR_SREV_9565(ah)) {
1541 if (enable) {
c9468682
SM		 1542 REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1543 AR_ANT_DIV_ENABLE);
84893817
SM		 1544 REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1545 (1 << AR_PHY_ANT_SW_RX_PROT_S));
c9468682
SM		 1546 REG_SET_BIT(ah, AR_PHY_CCK_DETECT,
1547 AR_FAST_DIV_ENABLE);
1548 REG_SET_BIT(ah, AR_PHY_RESTART,
1549 AR_PHY_RESTART_ENABLE_DIV_M2FLAG);
84893817
SM		 1550 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV,
1551 AR_BTCOEX_WL_LNADIV_FORCE_ON);
1552 } else {
c9468682
SM		 1553 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1554 AR_ANT_DIV_ENABLE);
84893817
SM		 1555 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1556 (1 << AR_PHY_ANT_SW_RX_PROT_S));
c9468682
SM		 1557 REG_CLR_BIT(ah, AR_PHY_CCK_DETECT,
1558 AR_FAST_DIV_ENABLE);
1559 REG_CLR_BIT(ah, AR_PHY_RESTART,
1560 AR_PHY_RESTART_ENABLE_DIV_M2FLAG);
84893817
SM		 1561 REG_CLR_BIT(ah, AR_BTCOEX_WL_LNADIV,
1562 AR_BTCOEX_WL_LNADIV_FORCE_ON);
1563
1564 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1565 regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1566 AR_PHY_ANT_DIV_ALT_LNACONF |
1567 AR_PHY_ANT_DIV_MAIN_GAINTB |
1568 AR_PHY_ANT_DIV_ALT_GAINTB);
1569 regval |= (ATH_ANT_DIV_COMB_LNA1 <<
1570 AR_PHY_ANT_DIV_MAIN_LNACONF_S);
1571 regval |= (ATH_ANT_DIV_COMB_LNA2 <<
1572 AR_PHY_ANT_DIV_ALT_LNACONF_S);
1573 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1574 }
362cd03f
SM		 1575 }
1576}
1577
36e8825e
SM		 1578#endif
1579
5f0c04ea
RM		 1580static int ar9003_hw_fast_chan_change(struct ath_hw *ah,
1581 struct ath9k_channel *chan,
1582 u8 *ini_reloaded)
1583{
1584 unsigned int regWrites = 0;
af2db444 1585 u32 modesIndex, txgain_index;
5f0c04ea 1586
8896934c
FF		 1587 if (IS_CHAN_5GHZ(chan))
1588 modesIndex = IS_CHAN_HT40(chan) ? 2 : 1;
1589 else
1590 modesIndex = IS_CHAN_HT40(chan) ? 3 : 4;
5f0c04ea 1591
af2db444
RM		 1592 txgain_index = AR_SREV_9531(ah) ? 1 : modesIndex;
1593
5f0c04ea
RM		 1594 if (modesIndex == ah->modes_index) {
1595 *ini_reloaded = false;
1596 goto set_rfmode;
1597 }
1598
1599 ar9003_hw_prog_ini(ah, &ah->iniSOC[ATH_INI_POST], modesIndex);
1600 ar9003_hw_prog_ini(ah, &ah->iniMac[ATH_INI_POST], modesIndex);
1601 ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex);
1602 ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex);
aaa53ee9 1603
2b5e54e2 1604 if (AR_SREV_9462_20_OR_LATER(ah))
aaa53ee9
SM		 1605 ar9003_hw_prog_ini(ah, &ah->ini_radio_post_sys2ant,
1606 modesIndex);
5f0c04ea 1607
af2db444 1608 REG_WRITE_ARRAY(&ah->iniModesTxGain, txgain_index, regWrites);
5f0c04ea 1609
07a9bd20
SM		 1610 if (AR_SREV_9462_20_OR_LATER(ah)) {
1611 /*
1612 * CUS217 mix LNA mode.
1613 */
1614 if (ar9003_hw_get_rx_gain_idx(ah) == 2) {
1615 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core,
1616 1, regWrites);
1617 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
1618 modesIndex, regWrites);
1619 }
1620 }
1621
5f0c04ea
RM		 1622 /*
1623 * For 5GHz channels requiring Fast Clock, apply
1624 * different modal values.
1625 */
1626 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
c7d36f9f 1627 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, regWrites);
5f0c04ea 1628
aaa53ee9
SM		 1629 if (AR_SREV_9565(ah))
1630 REG_WRITE_ARRAY(&ah->iniModesFastClock, 1, regWrites);
1631
07a9bd20
SM		 1632 /*
1633 * JAPAN regulatory.
1634 */
1635 if (chan->channel == 2484)
1636 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1);
5f0c04ea
RM		 1637
1638 ah->modes_index = modesIndex;
1639 *ini_reloaded = true;
1640
1641set_rfmode:
1642 ar9003_hw_set_rfmode(ah, chan);
1643 return 0;
1644}
1645
e93d083f
SW		 1646static void ar9003_hw_spectral_scan_config(struct ath_hw *ah,
1647 struct ath_spec_scan *param)
1648{
1649 u8 count;
1650
1651 if (!param->enabled) {
1652 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1653 AR_PHY_SPECTRAL_SCAN_ENABLE);
1654 return;
1655 }
1656
1657 REG_SET_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_FFT_ENA);
1658 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE);
1659
1660 /* on AR93xx and newer, count = 0 will make the the chip send
1661 * spectral samples endlessly. Check if this really was intended,
1662 * and fix otherwise.
1663 */
1664 count = param->count;
1665 if (param->endless)
1666 count = 0;
1667 else if (param->count == 0)
1668 count = 1;
1669
1670 if (param->short_repeat)
1671 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1672 AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT);
1673 else
1674 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1675 AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT);
1676
1677 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1678 AR_PHY_SPECTRAL_SCAN_COUNT, count);
1679 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1680 AR_PHY_SPECTRAL_SCAN_PERIOD, param->period);
1681 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1682 AR_PHY_SPECTRAL_SCAN_FFT_PERIOD, param->fft_period);
1683
1684 return;
1685}
1686
1687static void ar9003_hw_spectral_scan_trigger(struct ath_hw *ah)
1688{
1689 /* Activate spectral scan */
1690 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1691 AR_PHY_SPECTRAL_SCAN_ACTIVE);
1692}
1693
1694static void ar9003_hw_spectral_scan_wait(struct ath_hw *ah)
1695{
1696 struct ath_common *common = ath9k_hw_common(ah);
1697
1698 /* Poll for spectral scan complete */
1699 if (!ath9k_hw_wait(ah, AR_PHY_SPECTRAL_SCAN,
1700 AR_PHY_SPECTRAL_SCAN_ACTIVE,
1701 0, AH_WAIT_TIMEOUT)) {
1702 ath_err(common, "spectral scan wait failed\n");
1703 return;
1704 }
1705}
1706
89f927af
LR		 1707static void ar9003_hw_tx99_start(struct ath_hw *ah, u32 qnum)
1708{
1709 REG_SET_BIT(ah, AR_PHY_TEST, PHY_AGC_CLR);
1710 REG_SET_BIT(ah, 0x9864, 0x7f000);
1711 REG_SET_BIT(ah, 0x9924, 0x7f00fe);
1712 REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
1713 REG_WRITE(ah, AR_CR, AR_CR_RXD);
1714 REG_WRITE(ah, AR_DLCL_IFS(qnum), 0);
1715 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20); /* 50 OK */
1716 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20);
1717 REG_WRITE(ah, AR_TIME_OUT, 0x00000400);
1718 REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff);
1719 REG_SET_BIT(ah, AR_QMISC(qnum), AR_Q_MISC_DCU_EARLY_TERM_REQ);
1720}
1721
1722static void ar9003_hw_tx99_stop(struct ath_hw *ah)
1723{
1724 REG_CLR_BIT(ah, AR_PHY_TEST, PHY_AGC_CLR);
1725 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
1726}
1727
1728static void ar9003_hw_tx99_set_txpower(struct ath_hw *ah, u8 txpower)
1729{
1730 static s16 p_pwr_array[ar9300RateSize] = { 0 };
1731 unsigned int i;
1732
1733 if (txpower <= MAX_RATE_POWER) {
1734 for (i = 0; i < ar9300RateSize; i++)
1735 p_pwr_array[i] = txpower;
1736 } else {
1737 for (i = 0; i < ar9300RateSize; i++)
1738 p_pwr_array[i] = MAX_RATE_POWER;
1739 }
1740
1741 REG_WRITE(ah, 0xa458, 0);
1742
1743 REG_WRITE(ah, 0xa3c0,
1744 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 24) |
1745 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 16) |
1746 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 8) |
1747 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0));
1748 REG_WRITE(ah, 0xa3c4,
1749 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_54], 24) |
1750 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_48], 16) |
1751 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_36], 8) |
1752 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0));
1753 REG_WRITE(ah, 0xa3c8,
1754 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 24) |
1755 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 16) |
1756 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 0));
1757 REG_WRITE(ah, 0xa3cc,
1758 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_11S], 24) |
1759 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_11L], 16) |
1760 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_5S], 8) |
1761 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 0));
1762 REG_WRITE(ah, 0xa3d0,
1763 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_5], 24) |
1764 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_4], 16) |
1765 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_1_3_9_11_17_19], 8)|
1766 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_0_8_16], 0));
1767 REG_WRITE(ah, 0xa3d4,
1768 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_13], 24) |
1769 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_12], 16) |
1770 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_7], 8) |
1771 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_6], 0));
1772 REG_WRITE(ah, 0xa3e4,
1773 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_21], 24) |
1774 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_20], 16) |
1775 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_15], 8) |
1776 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_14], 0));
1777 REG_WRITE(ah, 0xa3e8,
1778 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_23], 24) |
1779 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_22], 16) |
1780 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_23], 8) |
1781 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_22], 0));
1782 REG_WRITE(ah, 0xa3d8,
1783 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_5], 24) |
1784 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_4], 16) |
1785 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_1_3_9_11_17_19], 8) |
1786 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_0_8_16], 0));
1787 REG_WRITE(ah, 0xa3dc,
1788 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_13], 24) |
1789 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_12], 16) |
1790 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_7], 8) |
1791 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_6], 0));
1792 REG_WRITE(ah, 0xa3ec,
1793 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_21], 24) |
1794 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_20], 16) |
1795 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_15], 8) |
1796 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_14], 0));
1797}
1798
8525f280
LR		 1799void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
1800{
1801 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
6bcbc062 1802 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
07b2fa5a 1803 static const u32 ar9300_cca_regs[6] = {
bbacee13
FF		 1804 AR_PHY_CCA_0,
1805 AR_PHY_CCA_1,
1806 AR_PHY_CCA_2,
1807 AR_PHY_EXT_CCA,
1808 AR_PHY_EXT_CCA_1,
1809 AR_PHY_EXT_CCA_2,
1810 };
8525f280
LR		 1811
1812 priv_ops->rf_set_freq = ar9003_hw_set_channel;
1813 priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
5fb9b1b9
FF		 1814
1815 if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah))
1816 priv_ops->compute_pll_control = ar9003_hw_compute_pll_control_soc;
1817 else
1818 priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
1819
8525f280
LR		 1820 priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
1821 priv_ops->init_bb = ar9003_hw_init_bb;
1822 priv_ops->process_ini = ar9003_hw_process_ini;
1823 priv_ops->set_rfmode = ar9003_hw_set_rfmode;
1824 priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive;
1825 priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
1826 priv_ops->rfbus_req = ar9003_hw_rfbus_req;
1827 priv_ops->rfbus_done = ar9003_hw_rfbus_done;
c16fcb49 1828 priv_ops->ani_control = ar9003_hw_ani_control;
641d9921 1829 priv_ops->do_getnf = ar9003_hw_do_getnf;
e36b27af 1830 priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
4e8c14e9 1831 priv_ops->set_radar_params = ar9003_hw_set_radar_params;
5f0c04ea 1832 priv_ops->fast_chan_change = ar9003_hw_fast_chan_change;
f2552e28 1833
6bcbc062
MSS		 1834 ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get;
1835 ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set;
e93d083f
SW		 1836 ops->spectral_scan_config = ar9003_hw_spectral_scan_config;
1837 ops->spectral_scan_trigger = ar9003_hw_spectral_scan_trigger;
1838 ops->spectral_scan_wait = ar9003_hw_spectral_scan_wait;
6bcbc062 1839
36e8825e
SM		 1840#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
1841 ops->set_bt_ant_diversity = ar9003_hw_set_bt_ant_diversity;
1842#endif
89f927af
LR		 1843 ops->tx99_start = ar9003_hw_tx99_start;
1844 ops->tx99_stop = ar9003_hw_tx99_stop;
1845 ops->tx99_set_txpower = ar9003_hw_tx99_set_txpower;
36e8825e 1846
f2552e28 1847 ar9003_hw_set_nf_limits(ah);
c5d0855a 1848 ar9003_hw_set_radar_conf(ah);
bbacee13 1849 memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
8525f280 1850}
aea702b7 1851
d88527d3
SM		 1852/*
1853 * Baseband Watchdog signatures:
1854 *
1855 * 0x04000539: BB hang when operating in HT40 DFS Channel.
1856 * Full chip reset is not required, but a recovery
1857 * mechanism is needed.
1858 *
1859 * 0x1300000a: Related to CAC deafness.
1860 * Chip reset is not required.
1861 *
1862 * 0x0400000a: Related to CAC deafness.
1863 * Full chip reset is required.
1864 *
1865 * 0x04000b09: RX state machine gets into an illegal state
1866 * when a packet with unsupported rate is received.
1867 * Full chip reset is required and PHY_RESTART has
1868 * to be disabled.
1869 *
1870 * 0x04000409: Packet stuck on receive.
1871 * Full chip reset is required for all chips except AR9340.
1872 */
1873
1874/*
1875 * ar9003_hw_bb_watchdog_check(): Returns true if a chip reset is required.
1876 */
1877bool ar9003_hw_bb_watchdog_check(struct ath_hw *ah)
1878{
1879 u32 val;
1880
1881 switch(ah->bb_watchdog_last_status) {
1882 case 0x04000539:
1883 val = REG_READ(ah, AR_PHY_RADAR_0);
1884 val &= (~AR_PHY_RADAR_0_FIRPWR);
1885 val |= SM(0x7f, AR_PHY_RADAR_0_FIRPWR);
1886 REG_WRITE(ah, AR_PHY_RADAR_0, val);
1887 udelay(1);
1888 val = REG_READ(ah, AR_PHY_RADAR_0);
1889 val &= ~AR_PHY_RADAR_0_FIRPWR;
1890 val |= SM(AR9300_DFS_FIRPWR, AR_PHY_RADAR_0_FIRPWR);
1891 REG_WRITE(ah, AR_PHY_RADAR_0, val);
1892
1893 return false;
1894 case 0x1300000a:
1895 return false;
1896 case 0x0400000a:
1897 case 0x04000b09:
1898 return true;
1899 case 0x04000409:
2c323058 1900 if (AR_SREV_9340(ah) || AR_SREV_9531(ah))
d88527d3
SM		 1901 return false;
1902 else
1903 return true;
1904 default:
1905 /*
1906 * For any other unknown signatures, do a
1907 * full chip reset.
1908 */
1909 return true;
1910 }
1911}
1912EXPORT_SYMBOL(ar9003_hw_bb_watchdog_check);
1913
aea702b7
LR		 1914void ar9003_hw_bb_watchdog_config(struct ath_hw *ah)
1915{
1916 struct ath_common *common = ath9k_hw_common(ah);
1917 u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms;
1918 u32 val, idle_count;
1919
1920 if (!idle_tmo_ms) {
1921 /* disable IRQ, disable chip-reset for BB panic */
1922 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1923 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) &
1924 ~(AR_PHY_WATCHDOG_RST_ENABLE |
1925 AR_PHY_WATCHDOG_IRQ_ENABLE));
1926
1927 /* disable watchdog in non-IDLE mode, disable in IDLE mode */
1928 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1929 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) &
1930 ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1931 AR_PHY_WATCHDOG_IDLE_ENABLE));
1932
d2182b69 1933 ath_dbg(common, RESET, "Disabled BB Watchdog\n");
aea702b7
LR		 1934 return;
1935 }
1936
1937 /* enable IRQ, disable chip-reset for BB watchdog */
1938 val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK;
1939 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1940 (val | AR_PHY_WATCHDOG_IRQ_ENABLE) &
1941 ~AR_PHY_WATCHDOG_RST_ENABLE);
1942
1943 /* bound limit to 10 secs */
1944 if (idle_tmo_ms > 10000)
1945 idle_tmo_ms = 10000;
1946
1947 /*
1948 * The time unit for watchdog event is 2^15 44/88MHz cycles.
1949 *
1950 * For HT20 we have a time unit of 2^15/44 MHz = .74 ms per tick
1951 * For HT40 we have a time unit of 2^15/88 MHz = .37 ms per tick
1952 *
1953 * Given we use fast clock now in 5 GHz, these time units should
1954 * be common for both 2 GHz and 5 GHz.
1955 */
1956 idle_count = (100 * idle_tmo_ms) / 74;
1957 if (ah->curchan && IS_CHAN_HT40(ah->curchan))
1958 idle_count = (100 * idle_tmo_ms) / 37;
1959
1960 /*
1961 * enable watchdog in non-IDLE mode, disable in IDLE mode,
1962 * set idle time-out.
1963 */
1964 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1965 AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1966 AR_PHY_WATCHDOG_IDLE_MASK |
1967 (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2)));
1968
d2182b69 1969 ath_dbg(common, RESET, "Enabled BB Watchdog timeout (%u ms)\n",
226afe68 1970 idle_tmo_ms);
aea702b7
LR		 1971}
1972
1973void ar9003_hw_bb_watchdog_read(struct ath_hw *ah)
1974{
1975 /*
1976 * we want to avoid printing in ISR context so we save the
1977 * watchdog status to be printed later in bottom half context.
1978 */
1979 ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS);
1980
1981 /*
1982 * the watchdog timer should reset on status read but to be sure
1983 * sure we write 0 to the watchdog status bit.
1984 */
1985 REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS,
1986 ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR);
1987}
1988
1989void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah)
1990{
1991 struct ath_common *common = ath9k_hw_common(ah);
9dbebc7f 1992 u32 status;
aea702b7
LR		 1993
1994 if (likely(!(common->debug_mask & ATH_DBG_RESET)))
1995 return;
1996
1997 status = ah->bb_watchdog_last_status;
d2182b69 1998 ath_dbg(common, RESET,
226afe68 1999 "\n==== BB update: BB status=0x%08x ====\n", status);
d2182b69 2000 ath_dbg(common, RESET,
226afe68
JP		 2001 "** BB state: wd=%u det=%u rdar=%u rOFDM=%d rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
2002 MS(status, AR_PHY_WATCHDOG_INFO),
2003 MS(status, AR_PHY_WATCHDOG_DET_HANG),
2004 MS(status, AR_PHY_WATCHDOG_RADAR_SM),
2005 MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM),
2006 MS(status, AR_PHY_WATCHDOG_RX_CCK_SM),
2007 MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM),
2008 MS(status, AR_PHY_WATCHDOG_TX_CCK_SM),
2009 MS(status, AR_PHY_WATCHDOG_AGC_SM),
2010 MS(status, AR_PHY_WATCHDOG_SRCH_SM));
2011
d2182b69 2012 ath_dbg(common, RESET, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
226afe68
JP		 2013 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1),
2014 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2));
d2182b69 2015 ath_dbg(common, RESET, "** BB mode: BB_gen_controls=0x%08x **\n",
226afe68 2016 REG_READ(ah, AR_PHY_GEN_CTRL));
aea702b7 2017
b5bfc568
FF		 2018#define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles)
2019 if (common->cc_survey.cycles)
d2182b69 2020 ath_dbg(common, RESET,
226afe68
JP		 2021 "** BB busy times: rx_clear=%d%%, rx_frame=%d%%, tx_frame=%d%% **\n",
2022 PCT(rx_busy), PCT(rx_frame), PCT(tx_frame));
aea702b7 2023
d2182b69 2024 ath_dbg(common, RESET, "==== BB update: done ====\n\n");
aea702b7
LR		 2025}
2026EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info);
51ac8cbb
RM		 2027
2028void ar9003_hw_disable_phy_restart(struct ath_hw *ah)
2029{
a7abaf7d 2030 u8 result;
51ac8cbb
RM		 2031 u32 val;
2032
2033 /* While receiving unsupported rate frame rx state machine
2034 * gets into a state 0xb and if phy_restart happens in that
2035 * state, BB would go hang. If RXSM is in 0xb state after
2036 * first bb panic, ensure to disable the phy_restart.
2037 */
a7abaf7d 2038 result = MS(ah->bb_watchdog_last_status, AR_PHY_WATCHDOG_RX_OFDM_SM);
51ac8cbb 2039
a7abaf7d
SM		 2040 if ((result == 0xb) || ah->bb_hang_rx_ofdm) {
2041 ah->bb_hang_rx_ofdm = true;
2042 val = REG_READ(ah, AR_PHY_RESTART);
2043 val &= ~AR_PHY_RESTART_ENA;
2044 REG_WRITE(ah, AR_PHY_RESTART, val);
2045 }
51ac8cbb
RM		 2046}
2047EXPORT_SYMBOL(ar9003_hw_disable_phy_restart);
Ubuntu Artful kernel mirror