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Merge tag 'nfc-next-4.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/sameo...
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / wireless / ath / ath9k / ar9003_phy.c
CommitLineData
8525f280 1/*
5b68138e 2 * Copyright (c) 2010-2011 Atheros Communications Inc.
8525f280
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
ee40fa06 17#include <linux/export.h>
8525f280 18#include "hw.h"
da6f1d7f 19#include "ar9003_phy.h"
8525f280 20
23f53dd3
LB		 21#define AR9300_OFDM_RATES 8
22#define AR9300_HT_SS_RATES 8
23#define AR9300_HT_DS_RATES 8
24#define AR9300_HT_TS_RATES 8
25
26#define AR9300_11NA_OFDM_SHIFT 0
27#define AR9300_11NA_HT_SS_SHIFT 8
28#define AR9300_11NA_HT_DS_SHIFT 16
29#define AR9300_11NA_HT_TS_SHIFT 24
30
31#define AR9300_11NG_OFDM_SHIFT 4
32#define AR9300_11NG_HT_SS_SHIFT 12
33#define AR9300_11NG_HT_DS_SHIFT 20
34#define AR9300_11NG_HT_TS_SHIFT 28
35
e36b27af
LR		 36static const int firstep_table[] =
37/* level: 0 1 2 3 4 5 6 7 8 */
38 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */
39
40static const int cycpwrThr1_table[] =
41/* level: 0 1 2 3 4 5 6 7 8 */
42 { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */
43
44/*
45 * register values to turn OFDM weak signal detection OFF
46 */
47static const int m1ThreshLow_off = 127;
48static const int m2ThreshLow_off = 127;
49static const int m1Thresh_off = 127;
50static const int m2Thresh_off = 127;
51static const int m2CountThr_off = 31;
52static const int m2CountThrLow_off = 63;
53static const int m1ThreshLowExt_off = 127;
54static const int m2ThreshLowExt_off = 127;
55static const int m1ThreshExt_off = 127;
56static const int m2ThreshExt_off = 127;
57
23f53dd3
LB		 58static const u8 ofdm2pwr[] = {
59 ALL_TARGET_LEGACY_6_24,
60 ALL_TARGET_LEGACY_6_24,
61 ALL_TARGET_LEGACY_6_24,
62 ALL_TARGET_LEGACY_6_24,
63 ALL_TARGET_LEGACY_6_24,
64 ALL_TARGET_LEGACY_36,
65 ALL_TARGET_LEGACY_48,
66 ALL_TARGET_LEGACY_54
67};
68
69static const u8 mcs2pwr_ht20[] = {
70 ALL_TARGET_HT20_0_8_16,
71 ALL_TARGET_HT20_1_3_9_11_17_19,
72 ALL_TARGET_HT20_1_3_9_11_17_19,
73 ALL_TARGET_HT20_1_3_9_11_17_19,
74 ALL_TARGET_HT20_4,
75 ALL_TARGET_HT20_5,
76 ALL_TARGET_HT20_6,
77 ALL_TARGET_HT20_7,
78 ALL_TARGET_HT20_0_8_16,
79 ALL_TARGET_HT20_1_3_9_11_17_19,
80 ALL_TARGET_HT20_1_3_9_11_17_19,
81 ALL_TARGET_HT20_1_3_9_11_17_19,
82 ALL_TARGET_HT20_12,
83 ALL_TARGET_HT20_13,
84 ALL_TARGET_HT20_14,
85 ALL_TARGET_HT20_15,
86 ALL_TARGET_HT20_0_8_16,
87 ALL_TARGET_HT20_1_3_9_11_17_19,
88 ALL_TARGET_HT20_1_3_9_11_17_19,
89 ALL_TARGET_HT20_1_3_9_11_17_19,
90 ALL_TARGET_HT20_20,
91 ALL_TARGET_HT20_21,
92 ALL_TARGET_HT20_22,
93 ALL_TARGET_HT20_23
94};
95
96static const u8 mcs2pwr_ht40[] = {
97 ALL_TARGET_HT40_0_8_16,
98 ALL_TARGET_HT40_1_3_9_11_17_19,
99 ALL_TARGET_HT40_1_3_9_11_17_19,
100 ALL_TARGET_HT40_1_3_9_11_17_19,
101 ALL_TARGET_HT40_4,
102 ALL_TARGET_HT40_5,
103 ALL_TARGET_HT40_6,
104 ALL_TARGET_HT40_7,
105 ALL_TARGET_HT40_0_8_16,
106 ALL_TARGET_HT40_1_3_9_11_17_19,
107 ALL_TARGET_HT40_1_3_9_11_17_19,
108 ALL_TARGET_HT40_1_3_9_11_17_19,
109 ALL_TARGET_HT40_12,
110 ALL_TARGET_HT40_13,
111 ALL_TARGET_HT40_14,
112 ALL_TARGET_HT40_15,
113 ALL_TARGET_HT40_0_8_16,
114 ALL_TARGET_HT40_1_3_9_11_17_19,
115 ALL_TARGET_HT40_1_3_9_11_17_19,
116 ALL_TARGET_HT40_1_3_9_11_17_19,
117 ALL_TARGET_HT40_20,
118 ALL_TARGET_HT40_21,
119 ALL_TARGET_HT40_22,
120 ALL_TARGET_HT40_23,
121};
122
8525f280
LR		 123/**
124 * ar9003_hw_set_channel - set channel on single-chip device
125 * @ah: atheros hardware structure
126 * @chan:
127 *
128 * This is the function to change channel on single-chip devices, that is
e4922f2b 129 * for AR9300 family of chipsets.
8525f280
LR		 130 *
131 * This function takes the channel value in MHz and sets
132 * hardware channel value. Assumes writes have been enabled to analog bus.
133 *
134 * Actual Expression,
135 *
136 * For 2GHz channel,
137 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
138 * (freq_ref = 40MHz)
139 *
140 * For 5GHz channel,
141 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
142 * (freq_ref = 40MHz/(24>>amodeRefSel))
143 *
144 * For 5GHz channels which are 5MHz spaced,
145 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
146 * (freq_ref = 40MHz)
147 */
148static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
149{
f7abf0c1 150 u16 bMode, fracMode = 0, aModeRefSel = 0;
1a26cda8 151 u32 freq, chan_frac, div, channelSel = 0, reg32 = 0;
f7abf0c1
FF		 152 struct chan_centers centers;
153 int loadSynthChannel;
154
155 ath9k_hw_get_channel_centers(ah, chan, &centers);
156 freq = centers.synth_center;
157
158 if (freq < 4800) { /* 2 GHz, fractional mode */
5acb4b93 159 if (AR_SREV_9330(ah)) {
5acb4b93
GJ		 160 if (ah->is_clk_25mhz)
161 div = 75;
162 else
163 div = 120;
164
165 channelSel = (freq * 4) / div;
166 chan_frac = (((freq * 4) % div) * 0x20000) / div;
167 channelSel = (channelSel << 17) | chan_frac;
a4a2954f 168 } else if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
3dfd7f60 169 /*
1a26cda8
SM		 170 * freq_ref = 40 / (refdiva >> amoderefsel);
171 * where refdiva=1 and amoderefsel=0
3dfd7f60
VT		 172 * ndiv = ((chan_mhz * 4) / 3) / freq_ref;
173 * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000
174 */
175 channelSel = (freq * 4) / 120;
176 chan_frac = (((freq * 4) % 120) * 0x20000) / 120;
177 channelSel = (channelSel << 17) | chan_frac;
1a26cda8 178 } else if (AR_SREV_9340(ah)) {
17869f4f 179 if (ah->is_clk_25mhz) {
17869f4f
VT		 180 channelSel = (freq * 2) / 75;
181 chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
182 channelSel = (channelSel << 17) | chan_frac;
1a26cda8 183 } else {
17869f4f 184 channelSel = CHANSEL_2G(freq) >> 1;
1a26cda8 185 }
ede6a5e7
MP		 186 } else if (AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
187 AR_SREV_9561(ah)) {
1a26cda8
SM		 188 if (ah->is_clk_25mhz)
189 div = 75;
190 else
191 div = 120;
192
193 channelSel = (freq * 4) / div;
194 chan_frac = (((freq * 4) % div) * 0x20000) / div;
195 channelSel = (channelSel << 17) | chan_frac;
196 } else {
85dd0921 197 channelSel = CHANSEL_2G(freq);
1a26cda8 198 }
f7abf0c1
FF		 199 /* Set to 2G mode */
200 bMode = 1;
201 } else {
ede6a5e7
MP		 202 if ((AR_SREV_9340(ah) || AR_SREV_9550(ah) ||
203 AR_SREV_9531(ah) || AR_SREV_9561(ah)) &&
db4a3de9 204 ah->is_clk_25mhz) {
530275e5
FF		 205 channelSel = freq / 75;
206 chan_frac = ((freq % 75) * 0x20000) / 75;
17869f4f
VT		 207 channelSel = (channelSel << 17) | chan_frac;
208 } else {
209 channelSel = CHANSEL_5G(freq);
210 /* Doubler is ON, so, divide channelSel by 2. */
211 channelSel >>= 1;
212 }
f7abf0c1
FF		 213 /* Set to 5G mode */
214 bMode = 0;
215 }
216
217 /* Enable fractional mode for all channels */
218 fracMode = 1;
219 aModeRefSel = 0;
220 loadSynthChannel = 0;
221
222 reg32 = (bMode << 29);
223 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
224
225 /* Enable Long shift Select for Synthesizer */
226 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4,
227 AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1);
228
229 /* Program Synth. setting */
230 reg32 = (channelSel << 2) | (fracMode << 30) |
231 (aModeRefSel << 28) | (loadSynthChannel << 31);
232 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
233
234 /* Toggle Load Synth channel bit */
235 loadSynthChannel = 1;
236 reg32 = (channelSel << 2) | (fracMode << 30) |
237 (aModeRefSel << 28) | (loadSynthChannel << 31);
238 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
239
240 ah->curchan = chan;
f7abf0c1 241
8525f280
LR		 242 return 0;
243}
244
245/**
e36b27af 246 * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency
8525f280
LR		 247 * @ah: atheros hardware structure
248 * @chan:
249 *
250 * For single-chip solutions. Converts to baseband spur frequency given the
251 * input channel frequency and compute register settings below.
252 *
253 * Spur mitigation for MRC CCK
254 */
1547da37
LR		 255static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
256 struct ath9k_channel *chan)
8525f280 257{
07b2fa5a 258 static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
ca375554
FF		 259 int cur_bb_spur, negative = 0, cck_spur_freq;
260 int i;
d9a2545a 261 int range, max_spur_cnts, synth_freq;
4b5237cc 262 u8 *spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah, IS_CHAN_2GHZ(chan));
ca375554
FF		 263
264 /*
265 * Need to verify range +/- 10 MHz in control channel, otherwise spur
266 * is out-of-band and can be ignored.
267 */
268
8528f12e 269 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
ede6a5e7 270 AR_SREV_9550(ah) || AR_SREV_9561(ah)) {
d9a2545a
VT		 271 if (spur_fbin_ptr[0] == 0) /* No spur */
272 return;
273 max_spur_cnts = 5;
274 if (IS_CHAN_HT40(chan)) {
275 range = 19;
276 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
277 AR_PHY_GC_DYN2040_PRI_CH) == 0)
278 synth_freq = chan->channel + 10;
279 else
280 synth_freq = chan->channel - 10;
281 } else {
282 range = 10;
283 synth_freq = chan->channel;
284 }
285 } else {
38df2f07 286 range = AR_SREV_9462(ah) ? 5 : 10;
d9a2545a
VT		 287 max_spur_cnts = 4;
288 synth_freq = chan->channel;
289 }
290
291 for (i = 0; i < max_spur_cnts; i++) {
38df2f07
RM		 292 if (AR_SREV_9462(ah) && (i == 0 || i == 3))
293 continue;
d43d04a9 294
ca375554 295 negative = 0;
8528f12e 296 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
ede6a5e7 297 AR_SREV_9550(ah) || AR_SREV_9561(ah))
8edb254c
GJ		 298 cur_bb_spur = ath9k_hw_fbin2freq(spur_fbin_ptr[i],
299 IS_CHAN_2GHZ(chan));
d9a2545a 300 else
8edb254c 301 cur_bb_spur = spur_freq[i];
ca375554 302
8edb254c 303 cur_bb_spur -= synth_freq;
ca375554
FF		 304 if (cur_bb_spur < 0) {
305 negative = 1;
306 cur_bb_spur = -cur_bb_spur;
307 }
d9a2545a 308 if (cur_bb_spur < range) {
ca375554
FF		 309 cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
310
311 if (negative == 1)
312 cck_spur_freq = -cck_spur_freq;
313
314 cck_spur_freq = cck_spur_freq & 0xfffff;
315
316 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
317 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
318 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
319 AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
320 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
321 AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE,
322 0x2);
323 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
324 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT,
325 0x1);
326 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
327 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ,
328 cck_spur_freq);
329
330 return;
331 }
332 }
333
334 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
335 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
336 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
337 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0);
338 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
339 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
8525f280
LR		 340}
341
1547da37
LR		 342/* Clean all spur register fields */
343static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah)
344{
345 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
346 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0);
347 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
348 AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
349 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
350 AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
351 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
352 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0);
353 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
354 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0);
355 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
356 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0);
357 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
358 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0);
359 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
360 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0);
361 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
362 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0);
363
364 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
365 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0);
366 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
367 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0);
368 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
369 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0);
370 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
371 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0);
372 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
373 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0);
374 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
375 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0);
376 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
377 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0);
378 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
379 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0);
380 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
381 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0);
382 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
383 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
384}
385
386static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
387 int freq_offset,
388 int spur_freq_sd,
389 int spur_delta_phase,
d43d04a9
SM		 390 int spur_subchannel_sd,
391 int range,
392 int synth_freq)
1547da37
LR		 393{
394 int mask_index = 0;
395
396 /* OFDM Spur mitigation */
397 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
398 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1);
399 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
400 AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
401 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
402 AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
403 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
404 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd);
405 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
406 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1);
d43d04a9
SM		 407
408 if (!(AR_SREV_9565(ah) && range == 10 && synth_freq == 2437))
409 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
410 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1);
411
1547da37
LR		 412 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
413 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1);
414 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
415 AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
416 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
417 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);
418
23dd9b2a
FF		 419 if (!AR_SREV_9340(ah) &&
420 REG_READ_FIELD(ah, AR_PHY_MODE,
1547da37
LR		 421 AR_PHY_MODE_DYNAMIC) == 0x1)
422 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
423 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);
424
425 mask_index = (freq_offset << 4) / 5;
426 if (mask_index < 0)
427 mask_index = mask_index - 1;
428
429 mask_index = mask_index & 0x7f;
430
431 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
432 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1);
433 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
434 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1);
435 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
436 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1);
437 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
438 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index);
439 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
440 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index);
441 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
442 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index);
443 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
444 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc);
445 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
446 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc);
447 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
448 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
449 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
450 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
451}
452
d43d04a9
SM		 453static void ar9003_hw_spur_ofdm_9565(struct ath_hw *ah,
454 int freq_offset)
455{
456 int mask_index = 0;
457
458 mask_index = (freq_offset << 4) / 5;
459 if (mask_index < 0)
460 mask_index = mask_index - 1;
461
462 mask_index = mask_index & 0x7f;
463
464 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
465 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B,
466 mask_index);
467
468 /* A == B */
469 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B,
470 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A,
471 mask_index);
472
473 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
474 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B,
475 mask_index);
476 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
477 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_B, 0xe);
478 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
479 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_B, 0xe);
480
481 /* A == B */
482 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B,
483 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
484}
485
1547da37
LR		 486static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
487 struct ath9k_channel *chan,
d43d04a9
SM		 488 int freq_offset,
489 int range,
490 int synth_freq)
1547da37
LR		 491{
492 int spur_freq_sd = 0;
493 int spur_subchannel_sd = 0;
494 int spur_delta_phase = 0;
495
496 if (IS_CHAN_HT40(chan)) {
497 if (freq_offset < 0) {
498 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
499 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
500 spur_subchannel_sd = 1;
501 else
502 spur_subchannel_sd = 0;
503
9d1ceac5 504 spur_freq_sd = ((freq_offset + 10) << 9) / 11;
1547da37
LR		 505
506 } else {
507 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
508 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
509 spur_subchannel_sd = 0;
510 else
511 spur_subchannel_sd = 1;
512
9d1ceac5 513 spur_freq_sd = ((freq_offset - 10) << 9) / 11;
1547da37
LR		 514
515 }
516
517 spur_delta_phase = (freq_offset << 17) / 5;
518
519 } else {
520 spur_subchannel_sd = 0;
521 spur_freq_sd = (freq_offset << 9) /11;
522 spur_delta_phase = (freq_offset << 18) / 5;
523 }
524
525 spur_freq_sd = spur_freq_sd & 0x3ff;
526 spur_delta_phase = spur_delta_phase & 0xfffff;
527
528 ar9003_hw_spur_ofdm(ah,
529 freq_offset,
530 spur_freq_sd,
531 spur_delta_phase,
d43d04a9
SM		 532 spur_subchannel_sd,
533 range, synth_freq);
1547da37
LR		 534}
535
536/* Spur mitigation for OFDM */
537static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
538 struct ath9k_channel *chan)
539{
540 int synth_freq;
541 int range = 10;
542 int freq_offset = 0;
543 int mode;
544 u8* spurChansPtr;
545 unsigned int i;
546 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
547
548 if (IS_CHAN_5GHZ(chan)) {
549 spurChansPtr = &(eep->modalHeader5G.spurChans[0]);
550 mode = 0;
551 }
552 else {
553 spurChansPtr = &(eep->modalHeader2G.spurChans[0]);
554 mode = 1;
555 }
556
557 if (spurChansPtr[0] == 0)
558 return; /* No spur in the mode */
559
560 if (IS_CHAN_HT40(chan)) {
561 range = 19;
562 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
563 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
564 synth_freq = chan->channel - 10;
565 else
566 synth_freq = chan->channel + 10;
567 } else {
568 range = 10;
569 synth_freq = chan->channel;
570 }
571
572 ar9003_hw_spur_ofdm_clear(ah);
573
0f8e94d2 574 for (i = 0; i < AR_EEPROM_MODAL_SPURS && spurChansPtr[i]; i++) {
8edb254c
GJ		 575 freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i], mode);
576 freq_offset -= synth_freq;
1547da37 577 if (abs(freq_offset) < range) {
d43d04a9
SM		 578 ar9003_hw_spur_ofdm_work(ah, chan, freq_offset,
579 range, synth_freq);
580
581 if (AR_SREV_9565(ah) && (i < 4)) {
582 freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i + 1],
583 mode);
584 freq_offset -= synth_freq;
585 if (abs(freq_offset) < range)
586 ar9003_hw_spur_ofdm_9565(ah, freq_offset);
587 }
588
1547da37
LR		 589 break;
590 }
591 }
592}
593
594static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
595 struct ath9k_channel *chan)
596{
d43d04a9
SM		 597 if (!AR_SREV_9565(ah))
598 ar9003_hw_spur_mitigate_mrc_cck(ah, chan);
1547da37
LR		 599 ar9003_hw_spur_mitigate_ofdm(ah, chan);
600}
601
5fb9b1b9
FF		 602static u32 ar9003_hw_compute_pll_control_soc(struct ath_hw *ah,
603 struct ath9k_channel *chan)
604{
605 u32 pll;
606
607 pll = SM(0x5, AR_RTC_9300_SOC_PLL_REFDIV);
608
609 if (chan && IS_CHAN_HALF_RATE(chan))
610 pll |= SM(0x1, AR_RTC_9300_SOC_PLL_CLKSEL);
611 else if (chan && IS_CHAN_QUARTER_RATE(chan))
612 pll |= SM(0x2, AR_RTC_9300_SOC_PLL_CLKSEL);
613
614 pll |= SM(0x2c, AR_RTC_9300_SOC_PLL_DIV_INT);
615
616 return pll;
617}
618
8525f280
LR		 619static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
620 struct ath9k_channel *chan)
621{
317d3328
FF		 622 u32 pll;
623
624 pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
625
626 if (chan && IS_CHAN_HALF_RATE(chan))
627 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
628 else if (chan && IS_CHAN_QUARTER_RATE(chan))
629 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
630
14bc1104 631 pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
317d3328
FF		 632
633 return pll;
8525f280
LR		 634}
635
636static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
637 struct ath9k_channel *chan)
638{
cffb5e49
LR		 639 u32 phymode;
640 u32 enableDacFifo = 0;
641
642 enableDacFifo =
643 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO);
644
645 /* Enable 11n HT, 20 MHz */
ede6a5e7
MP		 646 phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SHORT_GI_40 | enableDacFifo;
647
648 if (!AR_SREV_9561(ah))
649 phymode |= AR_PHY_GC_SINGLE_HT_LTF1;
cffb5e49
LR		 650
651 /* Configure baseband for dynamic 20/40 operation */
652 if (IS_CHAN_HT40(chan)) {
653 phymode |= AR_PHY_GC_DYN2040_EN;
654 /* Configure control (primary) channel at +-10MHz */
8896934c 655 if (IS_CHAN_HT40PLUS(chan))
cffb5e49
LR		 656 phymode |= AR_PHY_GC_DYN2040_PRI_CH;
657
658 }
659
660 /* make sure we preserve INI settings */
661 phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);
662 /* turn off Green Field detection for STA for now */
663 phymode &= ~AR_PHY_GC_GF_DETECT_EN;
664
665 REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
666
667 /* Configure MAC for 20/40 operation */
e4744ec7 668 ath9k_hw_set11nmac2040(ah, chan);
cffb5e49
LR		 669
670 /* global transmit timeout (25 TUs default)*/
671 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
672 /* carrier sense timeout */
673 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
8525f280
LR		 674}
675
676static void ar9003_hw_init_bb(struct ath_hw *ah,
677 struct ath9k_channel *chan)
678{
af914a9f
LR		 679 u32 synthDelay;
680
681 /*
682 * Wait for the frequency synth to settle (synth goes on
683 * via AR_PHY_ACTIVE_EN). Read the phy active delay register.
684 * Value is in 100ns increments.
685 */
686 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
af914a9f
LR		 687
688 /* Activate the PHY (includes baseband activate + synthesizer on) */
689 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
7c5adc8d 690 ath9k_hw_synth_delay(ah, chan, synthDelay);
8525f280
LR		 691}
692
4a8f1995 693void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
cffb5e49 694{
24171dd9 695 if (ah->caps.tx_chainmask == 5 || ah->caps.rx_chainmask == 5)
cffb5e49
LR		 696 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
697 AR_PHY_SWAP_ALT_CHAIN);
24171dd9
FF		 698
699 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
700 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
cffb5e49 701
ea066d5a 702 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7))
24171dd9 703 tx = 3;
ea066d5a 704
24171dd9 705 REG_WRITE(ah, AR_SELFGEN_MASK, tx);
cffb5e49
LR		 706}
707
708/*
709 * Override INI values with chip specific configuration.
710 */
711static void ar9003_hw_override_ini(struct ath_hw *ah)
712{
713 u32 val;
714
715 /*
716 * Set the RX_ABORT and RX_DIS and clear it only after
717 * RXE is set for MAC. This prevents frames with
718 * corrupted descriptor status.
719 */
720 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
721
722 /*
723 * For AR9280 and above, there is a new feature that allows
724 * Multicast search based on both MAC Address and Key ID. By default,
725 * this feature is enabled. But since the driver is not using this
726 * feature, we switch it off; otherwise multicast search based on
727 * MAC addr only will fail.
728 */
729 val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
9ef48932
SM		 730 val |= AR_AGG_WEP_ENABLE_FIX |
731 AR_AGG_WEP_ENABLE |
732 AR_PCU_MISC_MODE2_CFP_IGNORE;
733 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
bf3f204b 734
4b03f16e
SM		 735 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
736 REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE,
737 AR_GLB_SWREG_DISCONT_EN_BT_WLAN);
738
739 if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0,
740 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL))
741 ah->enabled_cals |= TX_IQ_CAL;
742 else
743 ah->enabled_cals &= ~TX_IQ_CAL;
744
4b03f16e 745 }
34d9b689
SM		 746
747 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE)
748 ah->enabled_cals |= TX_CL_CAL;
749 else
750 ah->enabled_cals &= ~TX_CL_CAL;
4e6ce4dc 751
ede6a5e7
MP		 752 if (AR_SREV_9340(ah) || AR_SREV_9531(ah) || AR_SREV_9550(ah) ||
753 AR_SREV_9561(ah)) {
4e6ce4dc
MP		 754 if (ah->is_clk_25mhz) {
755 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
756 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
757 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
758 } else {
759 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
760 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
761 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
762 }
763 udelay(100);
764 }
cffb5e49
LR		 765}
766
767static void ar9003_hw_prog_ini(struct ath_hw *ah,
768 struct ar5416IniArray *iniArr,
769 int column)
770{
771 unsigned int i, regWrites = 0;
772
773 /* New INI format: Array may be undefined (pre, core, post arrays) */
774 if (!iniArr->ia_array)
775 return;
776
777 /*
778 * New INI format: Pre, core, and post arrays for a given subsystem
779 * may be modal (> 2 columns) or non-modal (2 columns). Determine if
780 * the array is non-modal and force the column to 1.
781 */
782 if (column >= iniArr->ia_columns)
783 column = 1;
784
785 for (i = 0; i < iniArr->ia_rows; i++) {
786 u32 reg = INI_RA(iniArr, i, 0);
787 u32 val = INI_RA(iniArr, i, column);
788
7e68b746 789 REG_WRITE(ah, reg, val);
b2ccc507 790
cffb5e49
LR		 791 DO_DELAY(regWrites);
792 }
793}
794
8bc45c6b
GJ		 795static int ar9550_hw_get_modes_txgain_index(struct ath_hw *ah,
796 struct ath9k_channel *chan)
797{
798 int ret;
799
8896934c
FF		 800 if (IS_CHAN_2GHZ(chan)) {
801 if (IS_CHAN_HT40(chan))
802 return 7;
8bc45c6b 803 else
8896934c
FF		 804 return 8;
805 }
8bc45c6b 806
8896934c
FF		 807 if (chan->channel <= 5350)
808 ret = 1;
809 else if ((chan->channel > 5350) && (chan->channel <= 5600))
810 ret = 3;
811 else
812 ret = 5;
8bc45c6b 813
8896934c
FF		 814 if (IS_CHAN_HT40(chan))
815 ret++;
8bc45c6b
GJ		 816
817 return ret;
818}
819
ede6a5e7
MP		 820static int ar9561_hw_get_modes_txgain_index(struct ath_hw *ah,
821 struct ath9k_channel *chan)
822{
823 if (IS_CHAN_2GHZ(chan)) {
824 if (IS_CHAN_HT40(chan))
825 return 1;
826 else
827 return 2;
828 }
829
830 return 0;
831}
832
6fcbe538
SM		 833static void ar9003_doubler_fix(struct ath_hw *ah)
834{
835 if (AR_SREV_9300(ah) || AR_SREV_9580(ah) || AR_SREV_9550(ah)) {
836 REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2,
837 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
838 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0);
839 REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2,
840 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
841 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0);
842 REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2,
843 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
844 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0);
845
846 udelay(200);
847
848 REG_CLR_BIT(ah, AR_PHY_65NM_CH0_RXTX2,
849 AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK);
850 REG_CLR_BIT(ah, AR_PHY_65NM_CH1_RXTX2,
851 AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK);
852 REG_CLR_BIT(ah, AR_PHY_65NM_CH2_RXTX2,
853 AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK);
854
855 udelay(1);
856
857 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX2,
858 AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1);
859 REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX2,
860 AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1);
861 REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX2,
862 AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1);
863
864 udelay(200);
865
866 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH12,
867 AR_PHY_65NM_CH0_SYNTH12_VREFMUL3, 0xf);
868
869 REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2, 0,
870 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
871 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S);
872 REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2, 0,
873 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
874 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S);
875 REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2, 0,
876 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
877 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S);
878 }
879}
880
8525f280
LR		 881static int ar9003_hw_process_ini(struct ath_hw *ah,
882 struct ath9k_channel *chan)
883{
cffb5e49 884 unsigned int regWrites = 0, i;
0ff2b5c0 885 u32 modesIndex;
cffb5e49 886
8896934c
FF		 887 if (IS_CHAN_5GHZ(chan))
888 modesIndex = IS_CHAN_HT40(chan) ? 2 : 1;
889 else
890 modesIndex = IS_CHAN_HT40(chan) ? 3 : 4;
cffb5e49 891
51dbd0a8
SM		 892 /*
893 * SOC, MAC, BB, RADIO initvals.
894 */
cffb5e49
LR		 895 for (i = 0; i < ATH_INI_NUM_SPLIT; i++) {
896 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex);
897 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
898 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
899 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
2b5e54e2 900 if (i == ATH_INI_POST && AR_SREV_9462_20_OR_LATER(ah))
2577c6e8
SB		 901 ar9003_hw_prog_ini(ah,
902 &ah->ini_radio_post_sys2ant,
903 modesIndex);
cffb5e49
LR		 904 }
905
6fcbe538
SM		 906 ar9003_doubler_fix(ah);
907
51dbd0a8
SM		 908 /*
909 * RXGAIN initvals.
910 */
cffb5e49 911 REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
51dbd0a8 912
2b5e54e2 913 if (AR_SREV_9462_20_OR_LATER(ah)) {
c177fabe
SM		 914 /*
915 * CUS217 mix LNA mode.
916 */
917 if (ar9003_hw_get_rx_gain_idx(ah) == 2) {
918 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core,
919 1, regWrites);
920 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
921 modesIndex, regWrites);
922 }
923
51dbd0a8
SM		 924 /*
925 * 5G-XLNA
926 */
927 if ((ar9003_hw_get_rx_gain_idx(ah) == 2) ||
928 (ar9003_hw_get_rx_gain_idx(ah) == 3)) {
871d0051 929 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_xlna,
51dbd0a8
SM		 930 modesIndex, regWrites);
931 }
932 }
933
ede6a5e7 934 if (AR_SREV_9550(ah) || AR_SREV_9561(ah))
8bc45c6b
GJ		 935 REG_WRITE_ARRAY(&ah->ini_modes_rx_gain_bounds, modesIndex,
936 regWrites);
937
cfa2b42b
MP		 938 if (AR_SREV_9561(ah) && (ar9003_hw_get_rx_gain_idx(ah) == 0))
939 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_xlna,
940 modesIndex, regWrites);
51dbd0a8
SM		 941 /*
942 * TXGAIN initvals.
943 */
ede6a5e7 944 if (AR_SREV_9550(ah) || AR_SREV_9531(ah) || AR_SREV_9561(ah)) {
2c323058
SM		 945 int modes_txgain_index = 1;
946
947 if (AR_SREV_9550(ah))
948 modes_txgain_index = ar9550_hw_get_modes_txgain_index(ah, chan);
8bc45c6b 949
ede6a5e7
MP		 950 if (AR_SREV_9561(ah))
951 modes_txgain_index =
952 ar9561_hw_get_modes_txgain_index(ah, chan);
953
8bc45c6b
GJ		 954 if (modes_txgain_index < 0)
955 return -EINVAL;
956
957 REG_WRITE_ARRAY(&ah->iniModesTxGain, modes_txgain_index,
958 regWrites);
959 } else {
960 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
961 }
cffb5e49
LR		 962
963 /*
964 * For 5GHz channels requiring Fast Clock, apply
965 * different modal values.
966 */
6b42e8d0 967 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
c7d36f9f 968 REG_WRITE_ARRAY(&ah->iniModesFastClock,
cffb5e49
LR		 969 modesIndex, regWrites);
970
51dbd0a8
SM		 971 /*
972 * Clock frequency initvals.
973 */
c7d36f9f 974 REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites);
d89baac8 975
51dbd0a8
SM		 976 /*
977 * JAPAN regulatory.
978 */
25c0f301 979 if (chan->channel == 2484) {
57527f8d 980 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1);
9951c4d0 981
25c0f301
MP		 982 if (AR_SREV_9531(ah))
983 REG_RMW_FIELD(ah, AR_PHY_FCAL_2_0,
984 AR_PHY_FLC_PWR_THRESH, 0);
985 }
986
5f0c04ea 987 ah->modes_index = modesIndex;
cffb5e49
LR		 988 ar9003_hw_override_ini(ah);
989 ar9003_hw_set_channel_regs(ah, chan);
990 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
64ea57d0 991 ath9k_hw_apply_txpower(ah, chan, false);
cffb5e49
LR		 992
993 return 0;
8525f280
LR		 994}
995
996static void ar9003_hw_set_rfmode(struct ath_hw *ah,
997 struct ath9k_channel *chan)
998{
af914a9f
LR		 999 u32 rfMode = 0;
1000
1001 if (chan == NULL)
1002 return;
1003
1a5e6326
FF		 1004 if (IS_CHAN_2GHZ(chan))
1005 rfMode |= AR_PHY_MODE_DYNAMIC;
1006 else
1007 rfMode |= AR_PHY_MODE_OFDM;
af914a9f 1008
6b42e8d0 1009 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
af914a9f
LR		 1010 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1011
3e61d3f9
FF		 1012 if (rfMode & (AR_PHY_MODE_QUARTER | AR_PHY_MODE_HALF))
1013 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
1014 AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW, 3);
1015
af914a9f 1016 REG_WRITE(ah, AR_PHY_MODE, rfMode);
8525f280
LR		 1017}
1018
1019static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
1020{
af914a9f 1021 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
8525f280
LR		 1022}
1023
1024static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
1025 struct ath9k_channel *chan)
1026{
af914a9f
LR		 1027 u32 coef_scaled, ds_coef_exp, ds_coef_man;
1028 u32 clockMhzScaled = 0x64000000;
1029 struct chan_centers centers;
1030
1031 /*
1032 * half and quarter rate can divide the scaled clock by 2 or 4
1033 * scale for selected channel bandwidth
1034 */
1035 if (IS_CHAN_HALF_RATE(chan))
1036 clockMhzScaled = clockMhzScaled >> 1;
1037 else if (IS_CHAN_QUARTER_RATE(chan))
1038 clockMhzScaled = clockMhzScaled >> 2;
1039
1040 /*
1041 * ALGO -> coef = 1e8/fcarrier*fclock/40;
1042 * scaled coef to provide precision for this floating calculation
1043 */
1044 ath9k_hw_get_channel_centers(ah, chan, &centers);
1045 coef_scaled = clockMhzScaled / centers.synth_center;
1046
1047 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1048 &ds_coef_exp);
1049
1050 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1051 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1052 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1053 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1054
1055 /*
1056 * For Short GI,
1057 * scaled coeff is 9/10 that of normal coeff
1058 */
1059 coef_scaled = (9 * coef_scaled) / 10;
1060
1061 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1062 &ds_coef_exp);
1063
1064 /* for short gi */
1065 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
1066 AR_PHY_SGI_DSC_MAN, ds_coef_man);
1067 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
1068 AR_PHY_SGI_DSC_EXP, ds_coef_exp);
8525f280
LR		 1069}
1070
1071static bool ar9003_hw_rfbus_req(struct ath_hw *ah)
1072{
af914a9f
LR		 1073 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1074 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1075 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
8525f280
LR		 1076}
1077
af914a9f
LR		 1078/*
1079 * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN).
1080 * Read the phy active delay register. Value is in 100ns increments.
1081 */
8525f280
LR		 1082static void ar9003_hw_rfbus_done(struct ath_hw *ah)
1083{
af914a9f 1084 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
af914a9f 1085
7c5adc8d 1086 ath9k_hw_synth_delay(ah, ah->curchan, synthDelay);
af914a9f
LR		 1087
1088 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
8525f280
LR		 1089}
1090
c16fcb49
FF		 1091static bool ar9003_hw_ani_control(struct ath_hw *ah,
1092 enum ath9k_ani_cmd cmd, int param)
1093{
af914a9f 1094 struct ath_common *common = ath9k_hw_common(ah);
e36b27af 1095 struct ath9k_channel *chan = ah->curchan;
c24bd362 1096 struct ar5416AniState *aniState = &ah->ani;
ff23e084
SM		 1097 int m1ThreshLow, m2ThreshLow;
1098 int m1Thresh, m2Thresh;
1099 int m2CountThr, m2CountThrLow;
1100 int m1ThreshLowExt, m2ThreshLowExt;
1101 int m1ThreshExt, m2ThreshExt;
e36b27af 1102 s32 value, value2;
af914a9f
LR		 1103
1104 switch (cmd & ah->ani_function) {
af914a9f 1105 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
e36b27af
LR		 1106 /*
1107 * on == 1 means ofdm weak signal detection is ON
1108 * on == 1 is the default, for less noise immunity
1109 *
1110 * on == 0 means ofdm weak signal detection is OFF
1111 * on == 0 means more noise imm
1112 */
af914a9f 1113 u32 on = param ? 1 : 0;
af914a9f 1114
ff23e084
SM		 1115 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
1116 goto skip_ws_det;
1117
1118 m1ThreshLow = on ?
1119 aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
1120 m2ThreshLow = on ?
1121 aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
1122 m1Thresh = on ?
1123 aniState->iniDef.m1Thresh : m1Thresh_off;
1124 m2Thresh = on ?
1125 aniState->iniDef.m2Thresh : m2Thresh_off;
1126 m2CountThr = on ?
1127 aniState->iniDef.m2CountThr : m2CountThr_off;
1128 m2CountThrLow = on ?
1129 aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
1130 m1ThreshLowExt = on ?
1131 aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
1132 m2ThreshLowExt = on ?
1133 aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
1134 m1ThreshExt = on ?
1135 aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
1136 m2ThreshExt = on ?
1137 aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
1138
1139 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1140 AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
1141 m1ThreshLow);
1142 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1143 AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
1144 m2ThreshLow);
1145 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1146 AR_PHY_SFCORR_M1_THRESH,
1147 m1Thresh);
1148 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1149 AR_PHY_SFCORR_M2_THRESH,
1150 m2Thresh);
1151 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1152 AR_PHY_SFCORR_M2COUNT_THR,
1153 m2CountThr);
1154 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1155 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
1156 m2CountThrLow);
1157 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1158 AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
1159 m1ThreshLowExt);
1160 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1161 AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
1162 m2ThreshLowExt);
1163 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1164 AR_PHY_SFCORR_EXT_M1_THRESH,
1165 m1ThreshExt);
1166 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1167 AR_PHY_SFCORR_EXT_M2_THRESH,
1168 m2ThreshExt);
1169skip_ws_det:
af914a9f
LR		 1170 if (on)
1171 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
1172 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1173 else
1174 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
1175 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1176
7067e701 1177 if (on != aniState->ofdmWeakSigDetect) {
d2182b69 1178 ath_dbg(common, ANI,
226afe68
JP		 1179 "** ch %d: ofdm weak signal: %s=>%s\n",
1180 chan->channel,
7067e701 1181 aniState->ofdmWeakSigDetect ?
226afe68
JP		 1182 "on" : "off",
1183 on ? "on" : "off");
af914a9f
LR		 1184 if (on)
1185 ah->stats.ast_ani_ofdmon++;
1186 else
1187 ah->stats.ast_ani_ofdmoff++;
7067e701 1188 aniState->ofdmWeakSigDetect = on;
af914a9f
LR		 1189 }
1190 break;
1191 }
af914a9f 1192 case ATH9K_ANI_FIRSTEP_LEVEL:{
af914a9f
LR		 1193 u32 level = param;
1194
e36b27af 1195 if (level >= ARRAY_SIZE(firstep_table)) {
d2182b69 1196 ath_dbg(common, ANI,
226afe68
JP		 1197 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",
1198 level, ARRAY_SIZE(firstep_table));
af914a9f
LR		 1199 return false;
1200 }
e36b27af
LR		 1201
1202 /*
1203 * make register setting relative to default
1204 * from INI file & cap value
1205 */
1206 value = firstep_table[level] -
465dce62 1207 firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
e36b27af
LR		 1208 aniState->iniDef.firstep;
1209 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1210 value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1211 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1212 value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
af914a9f
LR		 1213 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1214 AR_PHY_FIND_SIG_FIRSTEP,
e36b27af
LR		 1215 value);
1216 /*
1217 * we need to set first step low register too
1218 * make register setting relative to default
1219 * from INI file & cap value
1220 */
1221 value2 = firstep_table[level] -
465dce62 1222 firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
e36b27af
LR		 1223 aniState->iniDef.firstepLow;
1224 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1225 value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1226 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1227 value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1228
1229 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
1230 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2);
1231
1232 if (level != aniState->firstepLevel) {
d2182b69 1233 ath_dbg(common, ANI,
226afe68
JP		 1234 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
1235 chan->channel,
1236 aniState->firstepLevel,
1237 level,
465dce62 1238 ATH9K_ANI_FIRSTEP_LVL,
226afe68
JP		 1239 value,
1240 aniState->iniDef.firstep);
d2182b69 1241 ath_dbg(common, ANI,
226afe68
JP		 1242 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
1243 chan->channel,
1244 aniState->firstepLevel,
1245 level,
465dce62 1246 ATH9K_ANI_FIRSTEP_LVL,
226afe68
JP		 1247 value2,
1248 aniState->iniDef.firstepLow);
e36b27af
LR		 1249 if (level > aniState->firstepLevel)
1250 ah->stats.ast_ani_stepup++;
1251 else if (level < aniState->firstepLevel)
1252 ah->stats.ast_ani_stepdown++;
1253 aniState->firstepLevel = level;
1254 }
af914a9f
LR		 1255 break;
1256 }
1257 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
af914a9f
LR		 1258 u32 level = param;
1259
e36b27af 1260 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
d2182b69 1261 ath_dbg(common, ANI,
226afe68
JP		 1262 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",
1263 level, ARRAY_SIZE(cycpwrThr1_table));
af914a9f
LR		 1264 return false;
1265 }
e36b27af
LR		 1266 /*
1267 * make register setting relative to default
1268 * from INI file & cap value
1269 */
1270 value = cycpwrThr1_table[level] -
465dce62 1271 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
e36b27af
LR		 1272 aniState->iniDef.cycpwrThr1;
1273 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1274 value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1275 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1276 value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
af914a9f
LR		 1277 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
1278 AR_PHY_TIMING5_CYCPWR_THR1,
e36b27af
LR		 1279 value);
1280
1281 /*
1282 * set AR_PHY_EXT_CCA for extension channel
1283 * make register setting relative to default
1284 * from INI file & cap value
1285 */
1286 value2 = cycpwrThr1_table[level] -
465dce62 1287 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
e36b27af
LR		 1288 aniState->iniDef.cycpwrThr1Ext;
1289 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1290 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1291 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1292 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1293 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
1294 AR_PHY_EXT_CYCPWR_THR1, value2);
1295
1296 if (level != aniState->spurImmunityLevel) {
d2182b69 1297 ath_dbg(common, ANI,
226afe68
JP		 1298 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
1299 chan->channel,
1300 aniState->spurImmunityLevel,
1301 level,
465dce62 1302 ATH9K_ANI_SPUR_IMMUNE_LVL,
226afe68
JP		 1303 value,
1304 aniState->iniDef.cycpwrThr1);
d2182b69 1305 ath_dbg(common, ANI,
226afe68
JP		 1306 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
1307 chan->channel,
1308 aniState->spurImmunityLevel,
1309 level,
465dce62 1310 ATH9K_ANI_SPUR_IMMUNE_LVL,
226afe68
JP		 1311 value2,
1312 aniState->iniDef.cycpwrThr1Ext);
e36b27af
LR		 1313 if (level > aniState->spurImmunityLevel)
1314 ah->stats.ast_ani_spurup++;
1315 else if (level < aniState->spurImmunityLevel)
1316 ah->stats.ast_ani_spurdown++;
1317 aniState->spurImmunityLevel = level;
1318 }
af914a9f
LR		 1319 break;
1320 }
e36b27af
LR		 1321 case ATH9K_ANI_MRC_CCK:{
1322 /*
1323 * is_on == 1 means MRC CCK ON (default, less noise imm)
1324 * is_on == 0 means MRC CCK is OFF (more noise imm)
1325 */
1326 bool is_on = param ? 1 : 0;
a1c781bb
FF		 1327
1328 if (ah->caps.rx_chainmask == 1)
1329 break;
1330
e36b27af
LR		 1331 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1332 AR_PHY_MRC_CCK_ENABLE, is_on);
1333 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1334 AR_PHY_MRC_CCK_MUX_REG, is_on);
81b67fd6 1335 if (is_on != aniState->mrcCCK) {
d2182b69 1336 ath_dbg(common, ANI, "** ch %d: MRC CCK: %s=>%s\n",
226afe68 1337 chan->channel,
81b67fd6 1338 aniState->mrcCCK ? "on" : "off",
226afe68 1339 is_on ? "on" : "off");
1451a363
BC		 1340 if (is_on)
1341 ah->stats.ast_ani_ccklow++;
1342 else
1343 ah->stats.ast_ani_cckhigh++;
1344 aniState->mrcCCK = is_on;
e36b27af
LR		 1345 }
1346 break;
1347 }
af914a9f 1348 default:
d2182b69 1349 ath_dbg(common, ANI, "invalid cmd %u\n", cmd);
af914a9f
LR		 1350 return false;
1351 }
1352
d2182b69 1353 ath_dbg(common, ANI,
226afe68
JP		 1354 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1355 aniState->spurImmunityLevel,
7067e701 1356 aniState->ofdmWeakSigDetect ? "on" : "off",
226afe68 1357 aniState->firstepLevel,
81b67fd6 1358 aniState->mrcCCK ? "on" : "off",
226afe68
JP		 1359 aniState->listenTime,
1360 aniState->ofdmPhyErrCount,
1361 aniState->cckPhyErrCount);
af914a9f 1362 return true;
c16fcb49
FF		 1363}
1364
641d9921
FF		 1365static void ar9003_hw_do_getnf(struct ath_hw *ah,
1366 int16_t nfarray[NUM_NF_READINGS])
1367{
b06af7a5
VT		 1368#define AR_PHY_CH_MINCCA_PWR 0x1FF00000
1369#define AR_PHY_CH_MINCCA_PWR_S 20
1370#define AR_PHY_CH_EXT_MINCCA_PWR 0x01FF0000
1371#define AR_PHY_CH_EXT_MINCCA_PWR_S 16
641d9921 1372
b06af7a5
VT		 1373 int16_t nf;
1374 int i;
866b7780 1375
b06af7a5
VT		 1376 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1377 if (ah->rxchainmask & BIT(i)) {
1378 nf = MS(REG_READ(ah, ah->nf_regs[i]),
1379 AR_PHY_CH_MINCCA_PWR);
1380 nfarray[i] = sign_extend32(nf, 8);
641d9921 1381
b06af7a5
VT		 1382 if (IS_CHAN_HT40(ah->curchan)) {
1383 u8 ext_idx = AR9300_MAX_CHAINS + i;
641d9921 1384
b06af7a5
VT		 1385 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]),
1386 AR_PHY_CH_EXT_MINCCA_PWR);
1387 nfarray[ext_idx] = sign_extend32(nf, 8);
1388 }
1389 }
1390 }
641d9921
FF		 1391}
1392
f2552e28 1393static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
641d9921 1394{
f2552e28
FF		 1395 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
1396 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
ae245cde 1397 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ;
f2552e28
FF		 1398 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
1399 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
1400 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ;
ae245cde
SM		 1401
1402 if (AR_SREV_9330(ah))
1403 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ;
1404
a4a2954f 1405 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
ae245cde
SM		 1406 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ;
1407 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9462_2GHZ;
1408 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ;
1409 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9462_5GHZ;
1410 }
641d9921
FF		 1411}
1412
e36b27af
LR		 1413/*
1414 * Initialize the ANI register values with default (ini) values.
1415 * This routine is called during a (full) hardware reset after
1416 * all the registers are initialised from the INI.
1417 */
1418static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
1419{
1420 struct ar5416AniState *aniState;
1421 struct ath_common *common = ath9k_hw_common(ah);
1422 struct ath9k_channel *chan = ah->curchan;
1423 struct ath9k_ani_default *iniDef;
e36b27af
LR		 1424 u32 val;
1425
c24bd362 1426 aniState = &ah->ani;
e36b27af
LR		 1427 iniDef = &aniState->iniDef;
1428
8896934c 1429 ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz\n",
226afe68
JP		 1430 ah->hw_version.macVersion,
1431 ah->hw_version.macRev,
1432 ah->opmode,
8896934c 1433 chan->channel);
e36b27af
LR		 1434
1435 val = REG_READ(ah, AR_PHY_SFCORR);
1436 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1437 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1438 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1439
1440 val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1441 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1442 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1443 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1444
1445 val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1446 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1447 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1448 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1449 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1450 iniDef->firstep = REG_READ_FIELD(ah,
1451 AR_PHY_FIND_SIG,
1452 AR_PHY_FIND_SIG_FIRSTEP);
1453 iniDef->firstepLow = REG_READ_FIELD(ah,
1454 AR_PHY_FIND_SIG_LOW,
1455 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW);
1456 iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1457 AR_PHY_TIMING5,
1458 AR_PHY_TIMING5_CYCPWR_THR1);
1459 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1460 AR_PHY_EXT_CCA,
1461 AR_PHY_EXT_CYCPWR_THR1);
1462
1463 /* these levels just got reset to defaults by the INI */
465dce62
FF		 1464 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
1465 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
4f4395c6 1466 aniState->ofdmWeakSigDetect = true;
81b67fd6 1467 aniState->mrcCCK = true;
e36b27af
LR		 1468}
1469
4e8c14e9
FF		 1470static void ar9003_hw_set_radar_params(struct ath_hw *ah,
1471 struct ath_hw_radar_conf *conf)
1472{
4a878b9f 1473 unsigned int regWrites = 0;
992a36a6 1474 u32 radar_0 = 0, radar_1;
4e8c14e9
FF		 1475
1476 if (!conf) {
1477 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
1478 return;
1479 }
1480
1481 radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
1482 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1483 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
1484 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
1485 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
1486 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
1487
992a36a6
LB		 1488 radar_1 = REG_READ(ah, AR_PHY_RADAR_1);
1489 radar_1 &= ~(AR_PHY_RADAR_1_MAXLEN | AR_PHY_RADAR_1_RELSTEP_THRESH |
1490 AR_PHY_RADAR_1_RELPWR_THRESH);
4e8c14e9
FF		 1491 radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
1492 radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
1493 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
1494 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
1495 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
1496
1497 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1498 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1499 if (conf->ext_channel)
1500 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1501 else
1502 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
4a878b9f
SM		 1503
1504 if (AR_SREV_9300(ah) || AR_SREV_9340(ah) || AR_SREV_9580(ah)) {
1505 REG_WRITE_ARRAY(&ah->ini_dfs,
1506 IS_CHAN_HT40(ah->curchan) ? 2 : 1, regWrites);
1507 }
4e8c14e9
FF		 1508}
1509
c5d0855a
FF		 1510static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
1511{
1512 struct ath_hw_radar_conf *conf = &ah->radar_conf;
1513
1514 conf->fir_power = -28;
1515 conf->radar_rssi = 0;
1516 conf->pulse_height = 10;
edad1873 1517 conf->pulse_rssi = 15;
c5d0855a
FF		 1518 conf->pulse_inband = 8;
1519 conf->pulse_maxlen = 255;
1520 conf->pulse_inband_step = 12;
1521 conf->radar_inband = 8;
1522}
1523
6bcbc062 1524static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah,
9aa49ea3 1525 struct ath_hw_antcomb_conf *antconf)
6bcbc062
MSS		 1526{
1527 u32 regval;
1528
1529 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
9aa49ea3
SM		 1530 antconf->main_lna_conf = (regval & AR_PHY_ANT_DIV_MAIN_LNACONF) >>
1531 AR_PHY_ANT_DIV_MAIN_LNACONF_S;
1532 antconf->alt_lna_conf = (regval & AR_PHY_ANT_DIV_ALT_LNACONF) >>
1533 AR_PHY_ANT_DIV_ALT_LNACONF_S;
1534 antconf->fast_div_bias = (regval & AR_PHY_ANT_FAST_DIV_BIAS) >>
1535 AR_PHY_ANT_FAST_DIV_BIAS_S;
cd0ed1b5 1536
c4cf2c58 1537 if (AR_SREV_9330_11(ah)) {
f96bd2ad 1538 antconf->lna1_lna2_switch_delta = -1;
c4cf2c58
GJ		 1539 antconf->lna1_lna2_delta = -9;
1540 antconf->div_group = 1;
1541 } else if (AR_SREV_9485(ah)) {
f96bd2ad 1542 antconf->lna1_lna2_switch_delta = -1;
cd0ed1b5
GJ		 1543 antconf->lna1_lna2_delta = -9;
1544 antconf->div_group = 2;
5317c9c3 1545 } else if (AR_SREV_9565(ah)) {
f96bd2ad
SM		 1546 antconf->lna1_lna2_switch_delta = 3;
1547 antconf->lna1_lna2_delta = -9;
5317c9c3 1548 antconf->div_group = 3;
cd0ed1b5 1549 } else {
f96bd2ad 1550 antconf->lna1_lna2_switch_delta = -1;
cd0ed1b5
GJ		 1551 antconf->lna1_lna2_delta = -3;
1552 antconf->div_group = 0;
1553 }
6bcbc062
MSS		 1554}
1555
1556static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah,
1557 struct ath_hw_antcomb_conf *antconf)
1558{
1559 u32 regval;
1560
1561 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
9aa49ea3
SM		 1562 regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1563 AR_PHY_ANT_DIV_ALT_LNACONF |
1564 AR_PHY_ANT_FAST_DIV_BIAS |
1565 AR_PHY_ANT_DIV_MAIN_GAINTB |
1566 AR_PHY_ANT_DIV_ALT_GAINTB);
1567 regval |= ((antconf->main_lna_conf << AR_PHY_ANT_DIV_MAIN_LNACONF_S)
1568 & AR_PHY_ANT_DIV_MAIN_LNACONF);
1569 regval |= ((antconf->alt_lna_conf << AR_PHY_ANT_DIV_ALT_LNACONF_S)
1570 & AR_PHY_ANT_DIV_ALT_LNACONF);
1571 regval |= ((antconf->fast_div_bias << AR_PHY_ANT_FAST_DIV_BIAS_S)
1572 & AR_PHY_ANT_FAST_DIV_BIAS);
1573 regval |= ((antconf->main_gaintb << AR_PHY_ANT_DIV_MAIN_GAINTB_S)
1574 & AR_PHY_ANT_DIV_MAIN_GAINTB);
1575 regval |= ((antconf->alt_gaintb << AR_PHY_ANT_DIV_ALT_GAINTB_S)
1576 & AR_PHY_ANT_DIV_ALT_GAINTB);
6bcbc062
MSS		 1577
1578 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1579}
1580
36e8825e
SM		 1581#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
1582
d8d7744b 1583static void ar9003_hw_set_bt_ant_diversity(struct ath_hw *ah, bool enable)
362cd03f 1584{
84893817 1585 struct ath9k_hw_capabilities *pCap = &ah->caps;
362cd03f
SM		 1586 u8 ant_div_ctl1;
1587 u32 regval;
1588
84893817 1589 if (!AR_SREV_9485(ah) && !AR_SREV_9565(ah))
362cd03f
SM		 1590 return;
1591
84893817
SM		 1592 if (AR_SREV_9485(ah)) {
1593 regval = ar9003_hw_ant_ctrl_common_2_get(ah,
1594 IS_CHAN_2GHZ(ah->curchan));
1595 if (enable) {
1596 regval &= ~AR_SWITCH_TABLE_COM2_ALL;
1597 regval |= ah->config.ant_ctrl_comm2g_switch_enable;
1598 }
1599 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2,
1600 AR_SWITCH_TABLE_COM2_ALL, regval);
1601 }
1602
362cd03f
SM		 1603 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
1604
84893817
SM		 1605 /*
1606 * Set MAIN/ALT LNA conf.
1607 * Set MAIN/ALT gain_tb.
1608 */
362cd03f
SM		 1609 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1610 regval &= (~AR_ANT_DIV_CTRL_ALL);
1611 regval |= (ant_div_ctl1 & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
362cd03f
SM		 1612 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1613
fb5a2dcb 1614 if (AR_SREV_9485_11_OR_LATER(ah)) {
84893817
SM		 1615 /*
1616 * Enable LNA diversity.
1617 */
362cd03f 1618 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
84893817
SM		 1619 regval &= ~AR_PHY_ANT_DIV_LNADIV;
1620 regval |= ((ant_div_ctl1 >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S;
1621 if (enable)
1622 regval |= AR_ANT_DIV_ENABLE;
1623
362cd03f 1624 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
84893817
SM		 1625
1626 /*
1627 * Enable fast antenna diversity.
1628 */
1629 regval = REG_READ(ah, AR_PHY_CCK_DETECT);
1630 regval &= ~AR_FAST_DIV_ENABLE;
1631 regval |= ((ant_div_ctl1 >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S;
1632 if (enable)
1633 regval |= AR_FAST_DIV_ENABLE;
1634
1635 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
1636
1637 if (pCap->hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) {
1638 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1639 regval &= (~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1640 AR_PHY_ANT_DIV_ALT_LNACONF |
1641 AR_PHY_ANT_DIV_ALT_GAINTB |
1642 AR_PHY_ANT_DIV_MAIN_GAINTB));
1643 /*
1644 * Set MAIN to LNA1 and ALT to LNA2 at the
1645 * beginning.
1646 */
1647 regval |= (ATH_ANT_DIV_COMB_LNA1 <<
1648 AR_PHY_ANT_DIV_MAIN_LNACONF_S);
1649 regval |= (ATH_ANT_DIV_COMB_LNA2 <<
1650 AR_PHY_ANT_DIV_ALT_LNACONF_S);
1651 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1652 }
1653 } else if (AR_SREV_9565(ah)) {
1654 if (enable) {
c9468682
SM		 1655 REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1656 AR_ANT_DIV_ENABLE);
84893817
SM		 1657 REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1658 (1 << AR_PHY_ANT_SW_RX_PROT_S));
c9468682
SM		 1659 REG_SET_BIT(ah, AR_PHY_CCK_DETECT,
1660 AR_FAST_DIV_ENABLE);
1661 REG_SET_BIT(ah, AR_PHY_RESTART,
1662 AR_PHY_RESTART_ENABLE_DIV_M2FLAG);
84893817
SM		 1663 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV,
1664 AR_BTCOEX_WL_LNADIV_FORCE_ON);
1665 } else {
c9468682
SM		 1666 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1667 AR_ANT_DIV_ENABLE);
84893817
SM		 1668 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1669 (1 << AR_PHY_ANT_SW_RX_PROT_S));
c9468682
SM		 1670 REG_CLR_BIT(ah, AR_PHY_CCK_DETECT,
1671 AR_FAST_DIV_ENABLE);
1672 REG_CLR_BIT(ah, AR_PHY_RESTART,
1673 AR_PHY_RESTART_ENABLE_DIV_M2FLAG);
84893817
SM		 1674 REG_CLR_BIT(ah, AR_BTCOEX_WL_LNADIV,
1675 AR_BTCOEX_WL_LNADIV_FORCE_ON);
1676
1677 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1678 regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1679 AR_PHY_ANT_DIV_ALT_LNACONF |
1680 AR_PHY_ANT_DIV_MAIN_GAINTB |
1681 AR_PHY_ANT_DIV_ALT_GAINTB);
1682 regval |= (ATH_ANT_DIV_COMB_LNA1 <<
1683 AR_PHY_ANT_DIV_MAIN_LNACONF_S);
1684 regval |= (ATH_ANT_DIV_COMB_LNA2 <<
1685 AR_PHY_ANT_DIV_ALT_LNACONF_S);
1686 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1687 }
362cd03f
SM		 1688 }
1689}
1690
36e8825e
SM		 1691#endif
1692
5f0c04ea
RM		 1693static int ar9003_hw_fast_chan_change(struct ath_hw *ah,
1694 struct ath9k_channel *chan,
1695 u8 *ini_reloaded)
1696{
1697 unsigned int regWrites = 0;
af2db444 1698 u32 modesIndex, txgain_index;
5f0c04ea 1699
8896934c
FF		 1700 if (IS_CHAN_5GHZ(chan))
1701 modesIndex = IS_CHAN_HT40(chan) ? 2 : 1;
1702 else
1703 modesIndex = IS_CHAN_HT40(chan) ? 3 : 4;
5f0c04ea 1704
af2db444
RM		 1705 txgain_index = AR_SREV_9531(ah) ? 1 : modesIndex;
1706
5f0c04ea
RM		 1707 if (modesIndex == ah->modes_index) {
1708 *ini_reloaded = false;
1709 goto set_rfmode;
1710 }
1711
1712 ar9003_hw_prog_ini(ah, &ah->iniSOC[ATH_INI_POST], modesIndex);
1713 ar9003_hw_prog_ini(ah, &ah->iniMac[ATH_INI_POST], modesIndex);
1714 ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex);
1715 ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex);
aaa53ee9 1716
2b5e54e2 1717 if (AR_SREV_9462_20_OR_LATER(ah))
aaa53ee9
SM		 1718 ar9003_hw_prog_ini(ah, &ah->ini_radio_post_sys2ant,
1719 modesIndex);
5f0c04ea 1720
af2db444 1721 REG_WRITE_ARRAY(&ah->iniModesTxGain, txgain_index, regWrites);
5f0c04ea 1722
07a9bd20
SM		 1723 if (AR_SREV_9462_20_OR_LATER(ah)) {
1724 /*
1725 * CUS217 mix LNA mode.
1726 */
1727 if (ar9003_hw_get_rx_gain_idx(ah) == 2) {
1728 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core,
1729 1, regWrites);
1730 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
1731 modesIndex, regWrites);
1732 }
1733 }
1734
5f0c04ea
RM		 1735 /*
1736 * For 5GHz channels requiring Fast Clock, apply
1737 * different modal values.
1738 */
1739 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
c7d36f9f 1740 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, regWrites);
5f0c04ea 1741
aaa53ee9
SM		 1742 if (AR_SREV_9565(ah))
1743 REG_WRITE_ARRAY(&ah->iniModesFastClock, 1, regWrites);
1744
07a9bd20
SM		 1745 /*
1746 * JAPAN regulatory.
1747 */
1748 if (chan->channel == 2484)
1749 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1);
5f0c04ea
RM		 1750
1751 ah->modes_index = modesIndex;
1752 *ini_reloaded = true;
1753
1754set_rfmode:
1755 ar9003_hw_set_rfmode(ah, chan);
1756 return 0;
1757}
1758
e93d083f
SW		 1759static void ar9003_hw_spectral_scan_config(struct ath_hw *ah,
1760 struct ath_spec_scan *param)
1761{
1762 u8 count;
1763
1764 if (!param->enabled) {
1765 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1766 AR_PHY_SPECTRAL_SCAN_ENABLE);
1767 return;
1768 }
1769
1770 REG_SET_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_FFT_ENA);
1771 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE);
1772
1773 /* on AR93xx and newer, count = 0 will make the the chip send
1774 * spectral samples endlessly. Check if this really was intended,
1775 * and fix otherwise.
1776 */
1777 count = param->count;
1778 if (param->endless)
1779 count = 0;
1780 else if (param->count == 0)
1781 count = 1;
1782
1783 if (param->short_repeat)
1784 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1785 AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT);
1786 else
1787 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1788 AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT);
1789
1790 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1791 AR_PHY_SPECTRAL_SCAN_COUNT, count);
1792 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1793 AR_PHY_SPECTRAL_SCAN_PERIOD, param->period);
1794 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1795 AR_PHY_SPECTRAL_SCAN_FFT_PERIOD, param->fft_period);
1796
1797 return;
1798}
1799
1800static void ar9003_hw_spectral_scan_trigger(struct ath_hw *ah)
1801{
1802 /* Activate spectral scan */
1803 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1804 AR_PHY_SPECTRAL_SCAN_ACTIVE);
1805}
1806
1807static void ar9003_hw_spectral_scan_wait(struct ath_hw *ah)
1808{
1809 struct ath_common *common = ath9k_hw_common(ah);
1810
1811 /* Poll for spectral scan complete */
1812 if (!ath9k_hw_wait(ah, AR_PHY_SPECTRAL_SCAN,
1813 AR_PHY_SPECTRAL_SCAN_ACTIVE,
1814 0, AH_WAIT_TIMEOUT)) {
1815 ath_err(common, "spectral scan wait failed\n");
1816 return;
1817 }
1818}
1819
89f927af
LR		 1820static void ar9003_hw_tx99_start(struct ath_hw *ah, u32 qnum)
1821{
1822 REG_SET_BIT(ah, AR_PHY_TEST, PHY_AGC_CLR);
1823 REG_SET_BIT(ah, 0x9864, 0x7f000);
1824 REG_SET_BIT(ah, 0x9924, 0x7f00fe);
1825 REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
1826 REG_WRITE(ah, AR_CR, AR_CR_RXD);
1827 REG_WRITE(ah, AR_DLCL_IFS(qnum), 0);
1828 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20); /* 50 OK */
1829 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20);
1830 REG_WRITE(ah, AR_TIME_OUT, 0x00000400);
1831 REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff);
1832 REG_SET_BIT(ah, AR_QMISC(qnum), AR_Q_MISC_DCU_EARLY_TERM_REQ);
1833}
1834
1835static void ar9003_hw_tx99_stop(struct ath_hw *ah)
1836{
1837 REG_CLR_BIT(ah, AR_PHY_TEST, PHY_AGC_CLR);
1838 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
1839}
1840
1841static void ar9003_hw_tx99_set_txpower(struct ath_hw *ah, u8 txpower)
1842{
1843 static s16 p_pwr_array[ar9300RateSize] = { 0 };
1844 unsigned int i;
1845
1846 if (txpower <= MAX_RATE_POWER) {
1847 for (i = 0; i < ar9300RateSize; i++)
1848 p_pwr_array[i] = txpower;
1849 } else {
1850 for (i = 0; i < ar9300RateSize; i++)
1851 p_pwr_array[i] = MAX_RATE_POWER;
1852 }
1853
1854 REG_WRITE(ah, 0xa458, 0);
1855
1856 REG_WRITE(ah, 0xa3c0,
1857 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 24) |
1858 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 16) |
1859 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 8) |
1860 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0));
1861 REG_WRITE(ah, 0xa3c4,
1862 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_54], 24) |
1863 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_48], 16) |
1864 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_36], 8) |
1865 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_6_24], 0));
1866 REG_WRITE(ah, 0xa3c8,
1867 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 24) |
1868 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 16) |
1869 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 0));
1870 REG_WRITE(ah, 0xa3cc,
1871 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_11S], 24) |
1872 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_11L], 16) |
1873 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_5S], 8) |
1874 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_LEGACY_1L_5L], 0));
1875 REG_WRITE(ah, 0xa3d0,
1876 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_5], 24) |
1877 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_4], 16) |
1878 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_1_3_9_11_17_19], 8)|
1879 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_0_8_16], 0));
1880 REG_WRITE(ah, 0xa3d4,
1881 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_13], 24) |
1882 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_12], 16) |
1883 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_7], 8) |
1884 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_6], 0));
1885 REG_WRITE(ah, 0xa3e4,
1886 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_21], 24) |
1887 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_20], 16) |
1888 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_15], 8) |
1889 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_14], 0));
1890 REG_WRITE(ah, 0xa3e8,
1891 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_23], 24) |
1892 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_22], 16) |
1893 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_23], 8) |
1894 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT20_22], 0));
1895 REG_WRITE(ah, 0xa3d8,
1896 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_5], 24) |
1897 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_4], 16) |
1898 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_1_3_9_11_17_19], 8) |
1899 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_0_8_16], 0));
1900 REG_WRITE(ah, 0xa3dc,
1901 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_13], 24) |
1902 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_12], 16) |
1903 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_7], 8) |
1904 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_6], 0));
1905 REG_WRITE(ah, 0xa3ec,
1906 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_21], 24) |
1907 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_20], 16) |
1908 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_15], 8) |
1909 ATH9K_POW_SM(p_pwr_array[ALL_TARGET_HT40_14], 0));
1910}
1911
23f53dd3
LB		 1912static void ar9003_hw_init_txpower_cck(struct ath_hw *ah, u8 *rate_array)
1913{
1914 ah->tx_power[0] = rate_array[ALL_TARGET_LEGACY_1L_5L];
1915 ah->tx_power[1] = rate_array[ALL_TARGET_LEGACY_1L_5L];
1916 ah->tx_power[2] = min(rate_array[ALL_TARGET_LEGACY_1L_5L],
1917 rate_array[ALL_TARGET_LEGACY_5S]);
1918 ah->tx_power[3] = min(rate_array[ALL_TARGET_LEGACY_11L],
1919 rate_array[ALL_TARGET_LEGACY_11S]);
1920}
1921
1922static void ar9003_hw_init_txpower_ofdm(struct ath_hw *ah, u8 *rate_array,
1923 int offset)
1924{
1925 int i, j;
1926
1927 for (i = offset; i < offset + AR9300_OFDM_RATES; i++) {
1928 /* OFDM rate to power table idx */
1929 j = ofdm2pwr[i - offset];
1930 ah->tx_power[i] = rate_array[j];
1931 }
1932}
1933
1934static void ar9003_hw_init_txpower_ht(struct ath_hw *ah, u8 *rate_array,
1935 int ss_offset, int ds_offset,
1936 int ts_offset, bool is_40)
1937{
1938 int i, j, mcs_idx = 0;
1939 const u8 *mcs2pwr = (is_40) ? mcs2pwr_ht40 : mcs2pwr_ht20;
1940
1941 for (i = ss_offset; i < ss_offset + AR9300_HT_SS_RATES; i++) {
1942 j = mcs2pwr[mcs_idx];
1943 ah->tx_power[i] = rate_array[j];
1944 mcs_idx++;
1945 }
1946
1947 for (i = ds_offset; i < ds_offset + AR9300_HT_DS_RATES; i++) {
1948 j = mcs2pwr[mcs_idx];
1949 ah->tx_power[i] = rate_array[j];
1950 mcs_idx++;
1951 }
1952
1953 for (i = ts_offset; i < ts_offset + AR9300_HT_TS_RATES; i++) {
1954 j = mcs2pwr[mcs_idx];
1955 ah->tx_power[i] = rate_array[j];
1956 mcs_idx++;
1957 }
1958}
1959
1960static void ar9003_hw_init_txpower_stbc(struct ath_hw *ah, int ss_offset,
1961 int ds_offset, int ts_offset)
1962{
1963 memcpy(&ah->tx_power_stbc[ss_offset], &ah->tx_power[ss_offset],
1964 AR9300_HT_SS_RATES);
1965 memcpy(&ah->tx_power_stbc[ds_offset], &ah->tx_power[ds_offset],
1966 AR9300_HT_DS_RATES);
1967 memcpy(&ah->tx_power_stbc[ts_offset], &ah->tx_power[ts_offset],
1968 AR9300_HT_TS_RATES);
1969}
1970
1971void ar9003_hw_init_rate_txpower(struct ath_hw *ah, u8 *rate_array,
1972 struct ath9k_channel *chan)
1973{
1974 if (IS_CHAN_5GHZ(chan)) {
1975 ar9003_hw_init_txpower_ofdm(ah, rate_array,
1976 AR9300_11NA_OFDM_SHIFT);
1977 if (IS_CHAN_HT20(chan) || IS_CHAN_HT40(chan)) {
1978 ar9003_hw_init_txpower_ht(ah, rate_array,
1979 AR9300_11NA_HT_SS_SHIFT,
1980 AR9300_11NA_HT_DS_SHIFT,
1981 AR9300_11NA_HT_TS_SHIFT,
1982 IS_CHAN_HT40(chan));
1983 ar9003_hw_init_txpower_stbc(ah,
1984 AR9300_11NA_HT_SS_SHIFT,
1985 AR9300_11NA_HT_DS_SHIFT,
1986 AR9300_11NA_HT_TS_SHIFT);
1987 }
1988 } else {
1989 ar9003_hw_init_txpower_cck(ah, rate_array);
1990 ar9003_hw_init_txpower_ofdm(ah, rate_array,
1991 AR9300_11NG_OFDM_SHIFT);
1992 if (IS_CHAN_HT20(chan) || IS_CHAN_HT40(chan)) {
1993 ar9003_hw_init_txpower_ht(ah, rate_array,
1994 AR9300_11NG_HT_SS_SHIFT,
1995 AR9300_11NG_HT_DS_SHIFT,
1996 AR9300_11NG_HT_TS_SHIFT,
1997 IS_CHAN_HT40(chan));
1998 ar9003_hw_init_txpower_stbc(ah,
1999 AR9300_11NG_HT_SS_SHIFT,
2000 AR9300_11NG_HT_DS_SHIFT,
2001 AR9300_11NG_HT_TS_SHIFT);
2002 }
2003 }
2004}
2005
8525f280
LR		 2006void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
2007{
2008 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
6bcbc062 2009 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
07b2fa5a 2010 static const u32 ar9300_cca_regs[6] = {
bbacee13
FF		 2011 AR_PHY_CCA_0,
2012 AR_PHY_CCA_1,
2013 AR_PHY_CCA_2,
2014 AR_PHY_EXT_CCA,
2015 AR_PHY_EXT_CCA_1,
2016 AR_PHY_EXT_CCA_2,
2017 };
8525f280
LR		 2018
2019 priv_ops->rf_set_freq = ar9003_hw_set_channel;
2020 priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
5fb9b1b9 2021
ede6a5e7
MP		 2022 if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
2023 AR_SREV_9561(ah))
5fb9b1b9
FF		 2024 priv_ops->compute_pll_control = ar9003_hw_compute_pll_control_soc;
2025 else
2026 priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
2027
8525f280
LR		 2028 priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
2029 priv_ops->init_bb = ar9003_hw_init_bb;
2030 priv_ops->process_ini = ar9003_hw_process_ini;
2031 priv_ops->set_rfmode = ar9003_hw_set_rfmode;
2032 priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive;
2033 priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
2034 priv_ops->rfbus_req = ar9003_hw_rfbus_req;
2035 priv_ops->rfbus_done = ar9003_hw_rfbus_done;
c16fcb49 2036 priv_ops->ani_control = ar9003_hw_ani_control;
641d9921 2037 priv_ops->do_getnf = ar9003_hw_do_getnf;
e36b27af 2038 priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
4e8c14e9 2039 priv_ops->set_radar_params = ar9003_hw_set_radar_params;
5f0c04ea 2040 priv_ops->fast_chan_change = ar9003_hw_fast_chan_change;
f2552e28 2041
6bcbc062
MSS		 2042 ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get;
2043 ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set;
e93d083f
SW		 2044 ops->spectral_scan_config = ar9003_hw_spectral_scan_config;
2045 ops->spectral_scan_trigger = ar9003_hw_spectral_scan_trigger;
2046 ops->spectral_scan_wait = ar9003_hw_spectral_scan_wait;
6bcbc062 2047
36e8825e
SM		 2048#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
2049 ops->set_bt_ant_diversity = ar9003_hw_set_bt_ant_diversity;
2050#endif
89f927af
LR		 2051 ops->tx99_start = ar9003_hw_tx99_start;
2052 ops->tx99_stop = ar9003_hw_tx99_stop;
2053 ops->tx99_set_txpower = ar9003_hw_tx99_set_txpower;
36e8825e 2054
f2552e28 2055 ar9003_hw_set_nf_limits(ah);
c5d0855a 2056 ar9003_hw_set_radar_conf(ah);
bbacee13 2057 memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
8525f280 2058}
aea702b7 2059
d88527d3
SM		 2060/*
2061 * Baseband Watchdog signatures:
2062 *
2063 * 0x04000539: BB hang when operating in HT40 DFS Channel.
2064 * Full chip reset is not required, but a recovery
2065 * mechanism is needed.
2066 *
2067 * 0x1300000a: Related to CAC deafness.
2068 * Chip reset is not required.
2069 *
2070 * 0x0400000a: Related to CAC deafness.
2071 * Full chip reset is required.
2072 *
2073 * 0x04000b09: RX state machine gets into an illegal state
2074 * when a packet with unsupported rate is received.
2075 * Full chip reset is required and PHY_RESTART has
2076 * to be disabled.
2077 *
2078 * 0x04000409: Packet stuck on receive.
3f6cc4e5
MP		 2079 * Full chip reset is required for all chips except
2080 * AR9340, AR9531 and AR9561.
d88527d3
SM		 2081 */
2082
2083/*
2084 * ar9003_hw_bb_watchdog_check(): Returns true if a chip reset is required.
2085 */
2086bool ar9003_hw_bb_watchdog_check(struct ath_hw *ah)
2087{
2088 u32 val;
2089
2090 switch(ah->bb_watchdog_last_status) {
2091 case 0x04000539:
2092 val = REG_READ(ah, AR_PHY_RADAR_0);
2093 val &= (~AR_PHY_RADAR_0_FIRPWR);
2094 val |= SM(0x7f, AR_PHY_RADAR_0_FIRPWR);
2095 REG_WRITE(ah, AR_PHY_RADAR_0, val);
2096 udelay(1);
2097 val = REG_READ(ah, AR_PHY_RADAR_0);
2098 val &= ~AR_PHY_RADAR_0_FIRPWR;
2099 val |= SM(AR9300_DFS_FIRPWR, AR_PHY_RADAR_0_FIRPWR);
2100 REG_WRITE(ah, AR_PHY_RADAR_0, val);
2101
2102 return false;
2103 case 0x1300000a:
2104 return false;
2105 case 0x0400000a:
2106 case 0x04000b09:
2107 return true;
2108 case 0x04000409:
3f6cc4e5 2109 if (AR_SREV_9340(ah) || AR_SREV_9531(ah) || AR_SREV_9561(ah))
d88527d3
SM		 2110 return false;
2111 else
2112 return true;
2113 default:
2114 /*
2115 * For any other unknown signatures, do a
2116 * full chip reset.
2117 */
2118 return true;
2119 }
2120}
2121EXPORT_SYMBOL(ar9003_hw_bb_watchdog_check);
2122
aea702b7
LR		 2123void ar9003_hw_bb_watchdog_config(struct ath_hw *ah)
2124{
2125 struct ath_common *common = ath9k_hw_common(ah);
2126 u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms;
2127 u32 val, idle_count;
2128
2129 if (!idle_tmo_ms) {
2130 /* disable IRQ, disable chip-reset for BB panic */
2131 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
2132 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) &
2133 ~(AR_PHY_WATCHDOG_RST_ENABLE |
2134 AR_PHY_WATCHDOG_IRQ_ENABLE));
2135
2136 /* disable watchdog in non-IDLE mode, disable in IDLE mode */
2137 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
2138 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) &
2139 ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
2140 AR_PHY_WATCHDOG_IDLE_ENABLE));
2141
d2182b69 2142 ath_dbg(common, RESET, "Disabled BB Watchdog\n");
aea702b7
LR		 2143 return;
2144 }
2145
2146 /* enable IRQ, disable chip-reset for BB watchdog */
2147 val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK;
2148 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
2149 (val | AR_PHY_WATCHDOG_IRQ_ENABLE) &
2150 ~AR_PHY_WATCHDOG_RST_ENABLE);
2151
2152 /* bound limit to 10 secs */
2153 if (idle_tmo_ms > 10000)
2154 idle_tmo_ms = 10000;
2155
2156 /*
2157 * The time unit for watchdog event is 2^15 44/88MHz cycles.
2158 *
2159 * For HT20 we have a time unit of 2^15/44 MHz = .74 ms per tick
2160 * For HT40 we have a time unit of 2^15/88 MHz = .37 ms per tick
2161 *
2162 * Given we use fast clock now in 5 GHz, these time units should
2163 * be common for both 2 GHz and 5 GHz.
2164 */
2165 idle_count = (100 * idle_tmo_ms) / 74;
2166 if (ah->curchan && IS_CHAN_HT40(ah->curchan))
2167 idle_count = (100 * idle_tmo_ms) / 37;
2168
2169 /*
2170 * enable watchdog in non-IDLE mode, disable in IDLE mode,
2171 * set idle time-out.
2172 */
2173 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
2174 AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
2175 AR_PHY_WATCHDOG_IDLE_MASK |
2176 (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2)));
2177
d2182b69 2178 ath_dbg(common, RESET, "Enabled BB Watchdog timeout (%u ms)\n",
226afe68 2179 idle_tmo_ms);
aea702b7
LR		 2180}
2181
2182void ar9003_hw_bb_watchdog_read(struct ath_hw *ah)
2183{
2184 /*
2185 * we want to avoid printing in ISR context so we save the
2186 * watchdog status to be printed later in bottom half context.
2187 */
2188 ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS);
2189
2190 /*
2191 * the watchdog timer should reset on status read but to be sure
2192 * sure we write 0 to the watchdog status bit.
2193 */
2194 REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS,
2195 ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR);
2196}
2197
2198void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah)
2199{
2200 struct ath_common *common = ath9k_hw_common(ah);
9dbebc7f 2201 u32 status;
aea702b7
LR		 2202
2203 if (likely(!(common->debug_mask & ATH_DBG_RESET)))
2204 return;
2205
2206 status = ah->bb_watchdog_last_status;
d2182b69 2207 ath_dbg(common, RESET,
226afe68 2208 "\n==== BB update: BB status=0x%08x ====\n", status);
d2182b69 2209 ath_dbg(common, RESET,
226afe68
JP		 2210 "** BB state: wd=%u det=%u rdar=%u rOFDM=%d rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
2211 MS(status, AR_PHY_WATCHDOG_INFO),
2212 MS(status, AR_PHY_WATCHDOG_DET_HANG),
2213 MS(status, AR_PHY_WATCHDOG_RADAR_SM),
2214 MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM),
2215 MS(status, AR_PHY_WATCHDOG_RX_CCK_SM),
2216 MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM),
2217 MS(status, AR_PHY_WATCHDOG_TX_CCK_SM),
2218 MS(status, AR_PHY_WATCHDOG_AGC_SM),
2219 MS(status, AR_PHY_WATCHDOG_SRCH_SM));
2220
d2182b69 2221 ath_dbg(common, RESET, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
226afe68
JP		 2222 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1),
2223 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2));
d2182b69 2224 ath_dbg(common, RESET, "** BB mode: BB_gen_controls=0x%08x **\n",
226afe68 2225 REG_READ(ah, AR_PHY_GEN_CTRL));
aea702b7 2226
b5bfc568
FF		 2227#define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles)
2228 if (common->cc_survey.cycles)
d2182b69 2229 ath_dbg(common, RESET,
226afe68
JP		 2230 "** BB busy times: rx_clear=%d%%, rx_frame=%d%%, tx_frame=%d%% **\n",
2231 PCT(rx_busy), PCT(rx_frame), PCT(tx_frame));
aea702b7 2232
d2182b69 2233 ath_dbg(common, RESET, "==== BB update: done ====\n\n");
aea702b7
LR		 2234}
2235EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info);
51ac8cbb
RM		 2236
2237void ar9003_hw_disable_phy_restart(struct ath_hw *ah)
2238{
a7abaf7d 2239 u8 result;
51ac8cbb
RM		 2240 u32 val;
2241
2242 /* While receiving unsupported rate frame rx state machine
2243 * gets into a state 0xb and if phy_restart happens in that
2244 * state, BB would go hang. If RXSM is in 0xb state after
2245 * first bb panic, ensure to disable the phy_restart.
2246 */
a7abaf7d 2247 result = MS(ah->bb_watchdog_last_status, AR_PHY_WATCHDOG_RX_OFDM_SM);
51ac8cbb 2248
a7abaf7d
SM		 2249 if ((result == 0xb) || ah->bb_hang_rx_ofdm) {
2250 ah->bb_hang_rx_ofdm = true;
2251 val = REG_READ(ah, AR_PHY_RESTART);
2252 val &= ~AR_PHY_RESTART_ENA;
2253 REG_WRITE(ah, AR_PHY_RESTART, val);
2254 }
51ac8cbb
RM		 2255}
2256EXPORT_SYMBOL(ar9003_hw_disable_phy_restart);
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