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ath9k: Update AR9462 2.0 initvals
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / wireless / ath / ath9k / ar9003_phy.c
CommitLineData
8525f280 1/*
5b68138e 2 * Copyright (c) 2010-2011 Atheros Communications Inc.
8525f280
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
ee40fa06 17#include <linux/export.h>
8525f280 18#include "hw.h"
da6f1d7f 19#include "ar9003_phy.h"
8525f280 20
e36b27af
LR		 21static const int firstep_table[] =
22/* level: 0 1 2 3 4 5 6 7 8 */
23 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */
24
25static const int cycpwrThr1_table[] =
26/* level: 0 1 2 3 4 5 6 7 8 */
27 { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */
28
29/*
30 * register values to turn OFDM weak signal detection OFF
31 */
32static const int m1ThreshLow_off = 127;
33static const int m2ThreshLow_off = 127;
34static const int m1Thresh_off = 127;
35static const int m2Thresh_off = 127;
36static const int m2CountThr_off = 31;
37static const int m2CountThrLow_off = 63;
38static const int m1ThreshLowExt_off = 127;
39static const int m2ThreshLowExt_off = 127;
40static const int m1ThreshExt_off = 127;
41static const int m2ThreshExt_off = 127;
42
8525f280
LR		 43/**
44 * ar9003_hw_set_channel - set channel on single-chip device
45 * @ah: atheros hardware structure
46 * @chan:
47 *
48 * This is the function to change channel on single-chip devices, that is
e4922f2b 49 * for AR9300 family of chipsets.
8525f280
LR		 50 *
51 * This function takes the channel value in MHz and sets
52 * hardware channel value. Assumes writes have been enabled to analog bus.
53 *
54 * Actual Expression,
55 *
56 * For 2GHz channel,
57 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
58 * (freq_ref = 40MHz)
59 *
60 * For 5GHz channel,
61 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
62 * (freq_ref = 40MHz/(24>>amodeRefSel))
63 *
64 * For 5GHz channels which are 5MHz spaced,
65 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
66 * (freq_ref = 40MHz)
67 */
68static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
69{
f7abf0c1 70 u16 bMode, fracMode = 0, aModeRefSel = 0;
1a26cda8 71 u32 freq, chan_frac, div, channelSel = 0, reg32 = 0;
f7abf0c1
FF		 72 struct chan_centers centers;
73 int loadSynthChannel;
74
75 ath9k_hw_get_channel_centers(ah, chan, &centers);
76 freq = centers.synth_center;
77
78 if (freq < 4800) { /* 2 GHz, fractional mode */
5acb4b93 79 if (AR_SREV_9330(ah)) {
5acb4b93
GJ		 80 if (ah->is_clk_25mhz)
81 div = 75;
82 else
83 div = 120;
84
85 channelSel = (freq * 4) / div;
86 chan_frac = (((freq * 4) % div) * 0x20000) / div;
87 channelSel = (channelSel << 17) | chan_frac;
a4a2954f 88 } else if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
3dfd7f60 89 /*
1a26cda8
SM		 90 * freq_ref = 40 / (refdiva >> amoderefsel);
91 * where refdiva=1 and amoderefsel=0
3dfd7f60
VT		 92 * ndiv = ((chan_mhz * 4) / 3) / freq_ref;
93 * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000
94 */
95 channelSel = (freq * 4) / 120;
96 chan_frac = (((freq * 4) % 120) * 0x20000) / 120;
97 channelSel = (channelSel << 17) | chan_frac;
1a26cda8 98 } else if (AR_SREV_9340(ah)) {
17869f4f 99 if (ah->is_clk_25mhz) {
17869f4f
VT		 100 channelSel = (freq * 2) / 75;
101 chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
102 channelSel = (channelSel << 17) | chan_frac;
1a26cda8 103 } else {
17869f4f 104 channelSel = CHANSEL_2G(freq) >> 1;
1a26cda8
SM		 105 }
106 } else if (AR_SREV_9550(ah)) {
107 if (ah->is_clk_25mhz)
108 div = 75;
109 else
110 div = 120;
111
112 channelSel = (freq * 4) / div;
113 chan_frac = (((freq * 4) % div) * 0x20000) / div;
114 channelSel = (channelSel << 17) | chan_frac;
115 } else {
85dd0921 116 channelSel = CHANSEL_2G(freq);
1a26cda8 117 }
f7abf0c1
FF		 118 /* Set to 2G mode */
119 bMode = 1;
120 } else {
db4a3de9
GJ		 121 if ((AR_SREV_9340(ah) || AR_SREV_9550(ah)) &&
122 ah->is_clk_25mhz) {
530275e5
FF		 123 channelSel = freq / 75;
124 chan_frac = ((freq % 75) * 0x20000) / 75;
17869f4f
VT		 125 channelSel = (channelSel << 17) | chan_frac;
126 } else {
127 channelSel = CHANSEL_5G(freq);
128 /* Doubler is ON, so, divide channelSel by 2. */
129 channelSel >>= 1;
130 }
f7abf0c1
FF		 131 /* Set to 5G mode */
132 bMode = 0;
133 }
134
135 /* Enable fractional mode for all channels */
136 fracMode = 1;
137 aModeRefSel = 0;
138 loadSynthChannel = 0;
139
140 reg32 = (bMode << 29);
141 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
142
143 /* Enable Long shift Select for Synthesizer */
144 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4,
145 AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1);
146
147 /* Program Synth. setting */
148 reg32 = (channelSel << 2) | (fracMode << 30) |
149 (aModeRefSel << 28) | (loadSynthChannel << 31);
150 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
151
152 /* Toggle Load Synth channel bit */
153 loadSynthChannel = 1;
154 reg32 = (channelSel << 2) | (fracMode << 30) |
155 (aModeRefSel << 28) | (loadSynthChannel << 31);
156 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
157
158 ah->curchan = chan;
f7abf0c1 159
8525f280
LR		 160 return 0;
161}
162
163/**
e36b27af 164 * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency
8525f280
LR		 165 * @ah: atheros hardware structure
166 * @chan:
167 *
168 * For single-chip solutions. Converts to baseband spur frequency given the
169 * input channel frequency and compute register settings below.
170 *
171 * Spur mitigation for MRC CCK
172 */
1547da37
LR		 173static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
174 struct ath9k_channel *chan)
8525f280 175{
07b2fa5a 176 static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
ca375554
FF		 177 int cur_bb_spur, negative = 0, cck_spur_freq;
178 int i;
d9a2545a 179 int range, max_spur_cnts, synth_freq;
4b5237cc 180 u8 *spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah, IS_CHAN_2GHZ(chan));
ca375554
FF		 181
182 /*
183 * Need to verify range +/- 10 MHz in control channel, otherwise spur
184 * is out-of-band and can be ignored.
185 */
186
8528f12e
GJ		 187 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
188 AR_SREV_9550(ah)) {
d9a2545a
VT		 189 if (spur_fbin_ptr[0] == 0) /* No spur */
190 return;
191 max_spur_cnts = 5;
192 if (IS_CHAN_HT40(chan)) {
193 range = 19;
194 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
195 AR_PHY_GC_DYN2040_PRI_CH) == 0)
196 synth_freq = chan->channel + 10;
197 else
198 synth_freq = chan->channel - 10;
199 } else {
200 range = 10;
201 synth_freq = chan->channel;
202 }
203 } else {
38df2f07 204 range = AR_SREV_9462(ah) ? 5 : 10;
d9a2545a
VT		 205 max_spur_cnts = 4;
206 synth_freq = chan->channel;
207 }
208
209 for (i = 0; i < max_spur_cnts; i++) {
38df2f07
RM		 210 if (AR_SREV_9462(ah) && (i == 0 || i == 3))
211 continue;
d43d04a9 212
ca375554 213 negative = 0;
8528f12e
GJ		 214 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
215 AR_SREV_9550(ah))
8edb254c
GJ		 216 cur_bb_spur = ath9k_hw_fbin2freq(spur_fbin_ptr[i],
217 IS_CHAN_2GHZ(chan));
d9a2545a 218 else
8edb254c 219 cur_bb_spur = spur_freq[i];
ca375554 220
8edb254c 221 cur_bb_spur -= synth_freq;
ca375554
FF		 222 if (cur_bb_spur < 0) {
223 negative = 1;
224 cur_bb_spur = -cur_bb_spur;
225 }
d9a2545a 226 if (cur_bb_spur < range) {
ca375554
FF		 227 cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
228
229 if (negative == 1)
230 cck_spur_freq = -cck_spur_freq;
231
232 cck_spur_freq = cck_spur_freq & 0xfffff;
233
234 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
235 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
236 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
237 AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
238 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
239 AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE,
240 0x2);
241 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
242 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT,
243 0x1);
244 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
245 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ,
246 cck_spur_freq);
247
248 return;
249 }
250 }
251
252 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
253 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
254 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
255 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0);
256 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
257 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
8525f280
LR		 258}
259
1547da37
LR		 260/* Clean all spur register fields */
261static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah)
262{
263 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
264 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0);
265 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
266 AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
267 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
268 AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
269 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
270 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0);
271 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
272 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0);
273 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
274 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0);
275 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
276 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0);
277 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
278 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0);
279 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
280 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0);
281
282 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
283 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0);
284 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
285 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0);
286 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
287 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0);
288 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
289 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0);
290 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
291 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0);
292 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
293 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0);
294 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
295 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0);
296 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
297 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0);
298 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
299 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0);
300 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
301 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
302}
303
304static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
305 int freq_offset,
306 int spur_freq_sd,
307 int spur_delta_phase,
d43d04a9
SM		 308 int spur_subchannel_sd,
309 int range,
310 int synth_freq)
1547da37
LR		 311{
312 int mask_index = 0;
313
314 /* OFDM Spur mitigation */
315 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
316 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1);
317 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
318 AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
319 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
320 AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
321 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
322 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd);
323 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
324 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1);
d43d04a9
SM		 325
326 if (!(AR_SREV_9565(ah) && range == 10 && synth_freq == 2437))
327 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
328 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1);
329
1547da37
LR		 330 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
331 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1);
332 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
333 AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
334 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
335 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);
336
23dd9b2a
FF		 337 if (!AR_SREV_9340(ah) &&
338 REG_READ_FIELD(ah, AR_PHY_MODE,
1547da37
LR		 339 AR_PHY_MODE_DYNAMIC) == 0x1)
340 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
341 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);
342
343 mask_index = (freq_offset << 4) / 5;
344 if (mask_index < 0)
345 mask_index = mask_index - 1;
346
347 mask_index = mask_index & 0x7f;
348
349 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
350 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1);
351 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
352 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1);
353 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
354 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1);
355 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
356 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index);
357 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
358 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index);
359 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
360 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index);
361 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
362 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc);
363 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
364 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc);
365 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
366 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
367 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
368 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
369}
370
d43d04a9
SM		 371static void ar9003_hw_spur_ofdm_9565(struct ath_hw *ah,
372 int freq_offset)
373{
374 int mask_index = 0;
375
376 mask_index = (freq_offset << 4) / 5;
377 if (mask_index < 0)
378 mask_index = mask_index - 1;
379
380 mask_index = mask_index & 0x7f;
381
382 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
383 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B,
384 mask_index);
385
386 /* A == B */
387 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B,
388 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A,
389 mask_index);
390
391 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
392 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B,
393 mask_index);
394 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
395 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_B, 0xe);
396 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
397 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_B, 0xe);
398
399 /* A == B */
400 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B,
401 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
402}
403
1547da37
LR		 404static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
405 struct ath9k_channel *chan,
d43d04a9
SM		 406 int freq_offset,
407 int range,
408 int synth_freq)
1547da37
LR		 409{
410 int spur_freq_sd = 0;
411 int spur_subchannel_sd = 0;
412 int spur_delta_phase = 0;
413
414 if (IS_CHAN_HT40(chan)) {
415 if (freq_offset < 0) {
416 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
417 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
418 spur_subchannel_sd = 1;
419 else
420 spur_subchannel_sd = 0;
421
9d1ceac5 422 spur_freq_sd = ((freq_offset + 10) << 9) / 11;
1547da37
LR		 423
424 } else {
425 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
426 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
427 spur_subchannel_sd = 0;
428 else
429 spur_subchannel_sd = 1;
430
9d1ceac5 431 spur_freq_sd = ((freq_offset - 10) << 9) / 11;
1547da37
LR		 432
433 }
434
435 spur_delta_phase = (freq_offset << 17) / 5;
436
437 } else {
438 spur_subchannel_sd = 0;
439 spur_freq_sd = (freq_offset << 9) /11;
440 spur_delta_phase = (freq_offset << 18) / 5;
441 }
442
443 spur_freq_sd = spur_freq_sd & 0x3ff;
444 spur_delta_phase = spur_delta_phase & 0xfffff;
445
446 ar9003_hw_spur_ofdm(ah,
447 freq_offset,
448 spur_freq_sd,
449 spur_delta_phase,
d43d04a9
SM		 450 spur_subchannel_sd,
451 range, synth_freq);
1547da37
LR		 452}
453
454/* Spur mitigation for OFDM */
455static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
456 struct ath9k_channel *chan)
457{
458 int synth_freq;
459 int range = 10;
460 int freq_offset = 0;
461 int mode;
462 u8* spurChansPtr;
463 unsigned int i;
464 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
465
466 if (IS_CHAN_5GHZ(chan)) {
467 spurChansPtr = &(eep->modalHeader5G.spurChans[0]);
468 mode = 0;
469 }
470 else {
471 spurChansPtr = &(eep->modalHeader2G.spurChans[0]);
472 mode = 1;
473 }
474
475 if (spurChansPtr[0] == 0)
476 return; /* No spur in the mode */
477
478 if (IS_CHAN_HT40(chan)) {
479 range = 19;
480 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
481 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
482 synth_freq = chan->channel - 10;
483 else
484 synth_freq = chan->channel + 10;
485 } else {
486 range = 10;
487 synth_freq = chan->channel;
488 }
489
490 ar9003_hw_spur_ofdm_clear(ah);
491
0f8e94d2 492 for (i = 0; i < AR_EEPROM_MODAL_SPURS && spurChansPtr[i]; i++) {
8edb254c
GJ		 493 freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i], mode);
494 freq_offset -= synth_freq;
1547da37 495 if (abs(freq_offset) < range) {
d43d04a9
SM		 496 ar9003_hw_spur_ofdm_work(ah, chan, freq_offset,
497 range, synth_freq);
498
499 if (AR_SREV_9565(ah) && (i < 4)) {
500 freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i + 1],
501 mode);
502 freq_offset -= synth_freq;
503 if (abs(freq_offset) < range)
504 ar9003_hw_spur_ofdm_9565(ah, freq_offset);
505 }
506
1547da37
LR		 507 break;
508 }
509 }
510}
511
512static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
513 struct ath9k_channel *chan)
514{
d43d04a9
SM		 515 if (!AR_SREV_9565(ah))
516 ar9003_hw_spur_mitigate_mrc_cck(ah, chan);
1547da37
LR		 517 ar9003_hw_spur_mitigate_ofdm(ah, chan);
518}
519
8525f280
LR		 520static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
521 struct ath9k_channel *chan)
522{
317d3328
FF		 523 u32 pll;
524
525 pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
526
527 if (chan && IS_CHAN_HALF_RATE(chan))
528 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
529 else if (chan && IS_CHAN_QUARTER_RATE(chan))
530 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
531
14bc1104 532 pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
317d3328
FF		 533
534 return pll;
8525f280
LR		 535}
536
537static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
538 struct ath9k_channel *chan)
539{
cffb5e49
LR		 540 u32 phymode;
541 u32 enableDacFifo = 0;
542
543 enableDacFifo =
544 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO);
545
546 /* Enable 11n HT, 20 MHz */
8ad38d22 547 phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 |
cffb5e49
LR		 548 AR_PHY_GC_SHORT_GI_40 | enableDacFifo;
549
550 /* Configure baseband for dynamic 20/40 operation */
551 if (IS_CHAN_HT40(chan)) {
552 phymode |= AR_PHY_GC_DYN2040_EN;
553 /* Configure control (primary) channel at +-10MHz */
554 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
555 (chan->chanmode == CHANNEL_G_HT40PLUS))
556 phymode |= AR_PHY_GC_DYN2040_PRI_CH;
557
558 }
559
560 /* make sure we preserve INI settings */
561 phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);
562 /* turn off Green Field detection for STA for now */
563 phymode &= ~AR_PHY_GC_GF_DETECT_EN;
564
565 REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
566
567 /* Configure MAC for 20/40 operation */
568 ath9k_hw_set11nmac2040(ah);
569
570 /* global transmit timeout (25 TUs default)*/
571 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
572 /* carrier sense timeout */
573 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
8525f280
LR		 574}
575
576static void ar9003_hw_init_bb(struct ath_hw *ah,
577 struct ath9k_channel *chan)
578{
af914a9f
LR		 579 u32 synthDelay;
580
581 /*
582 * Wait for the frequency synth to settle (synth goes on
583 * via AR_PHY_ACTIVE_EN). Read the phy active delay register.
584 * Value is in 100ns increments.
585 */
586 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
af914a9f
LR		 587
588 /* Activate the PHY (includes baseband activate + synthesizer on) */
589 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
7c5adc8d 590 ath9k_hw_synth_delay(ah, chan, synthDelay);
8525f280
LR		 591}
592
4a8f1995 593void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
cffb5e49 594{
24171dd9 595 if (ah->caps.tx_chainmask == 5 || ah->caps.rx_chainmask == 5)
cffb5e49
LR		 596 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
597 AR_PHY_SWAP_ALT_CHAIN);
24171dd9
FF		 598
599 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
600 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
cffb5e49 601
ea066d5a 602 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7))
24171dd9 603 tx = 3;
ea066d5a 604
24171dd9 605 REG_WRITE(ah, AR_SELFGEN_MASK, tx);
cffb5e49
LR		 606}
607
608/*
609 * Override INI values with chip specific configuration.
610 */
611static void ar9003_hw_override_ini(struct ath_hw *ah)
612{
613 u32 val;
614
615 /*
616 * Set the RX_ABORT and RX_DIS and clear it only after
617 * RXE is set for MAC. This prevents frames with
618 * corrupted descriptor status.
619 */
620 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
621
622 /*
623 * For AR9280 and above, there is a new feature that allows
624 * Multicast search based on both MAC Address and Key ID. By default,
625 * this feature is enabled. But since the driver is not using this
626 * feature, we switch it off; otherwise multicast search based on
627 * MAC addr only will fail.
628 */
629 val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
630 REG_WRITE(ah, AR_PCU_MISC_MODE2,
631 val | AR_AGG_WEP_ENABLE_FIX | AR_AGG_WEP_ENABLE);
bf3f204b
FF		 632
633 REG_SET_BIT(ah, AR_PHY_CCK_DETECT,
634 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
cffb5e49
LR		 635}
636
637static void ar9003_hw_prog_ini(struct ath_hw *ah,
638 struct ar5416IniArray *iniArr,
639 int column)
640{
641 unsigned int i, regWrites = 0;
642
643 /* New INI format: Array may be undefined (pre, core, post arrays) */
644 if (!iniArr->ia_array)
645 return;
646
647 /*
648 * New INI format: Pre, core, and post arrays for a given subsystem
649 * may be modal (> 2 columns) or non-modal (2 columns). Determine if
650 * the array is non-modal and force the column to 1.
651 */
652 if (column >= iniArr->ia_columns)
653 column = 1;
654
655 for (i = 0; i < iniArr->ia_rows; i++) {
656 u32 reg = INI_RA(iniArr, i, 0);
657 u32 val = INI_RA(iniArr, i, column);
658
7e68b746 659 REG_WRITE(ah, reg, val);
b2ccc507 660
cffb5e49
LR		 661 DO_DELAY(regWrites);
662 }
663}
664
8bc45c6b
GJ		 665static int ar9550_hw_get_modes_txgain_index(struct ath_hw *ah,
666 struct ath9k_channel *chan)
667{
668 int ret;
669
670 switch (chan->chanmode) {
671 case CHANNEL_A:
672 case CHANNEL_A_HT20:
673 if (chan->channel <= 5350)
674 ret = 1;
675 else if ((chan->channel > 5350) && (chan->channel <= 5600))
676 ret = 3;
677 else
678 ret = 5;
679 break;
680
681 case CHANNEL_A_HT40PLUS:
682 case CHANNEL_A_HT40MINUS:
683 if (chan->channel <= 5350)
684 ret = 2;
685 else if ((chan->channel > 5350) && (chan->channel <= 5600))
686 ret = 4;
687 else
688 ret = 6;
689 break;
690
691 case CHANNEL_G:
692 case CHANNEL_G_HT20:
693 case CHANNEL_B:
694 ret = 8;
695 break;
696
697 case CHANNEL_G_HT40PLUS:
698 case CHANNEL_G_HT40MINUS:
699 ret = 7;
700 break;
701
702 default:
703 ret = -EINVAL;
704 }
705
706 return ret;
707}
708
8525f280
LR		 709static int ar9003_hw_process_ini(struct ath_hw *ah,
710 struct ath9k_channel *chan)
711{
cffb5e49 712 unsigned int regWrites = 0, i;
0ff2b5c0 713 u32 modesIndex;
cffb5e49
LR		 714
715 switch (chan->chanmode) {
716 case CHANNEL_A:
717 case CHANNEL_A_HT20:
718 modesIndex = 1;
cffb5e49
LR		 719 break;
720 case CHANNEL_A_HT40PLUS:
721 case CHANNEL_A_HT40MINUS:
722 modesIndex = 2;
cffb5e49
LR		 723 break;
724 case CHANNEL_G:
725 case CHANNEL_G_HT20:
726 case CHANNEL_B:
727 modesIndex = 4;
cffb5e49
LR		 728 break;
729 case CHANNEL_G_HT40PLUS:
730 case CHANNEL_G_HT40MINUS:
731 modesIndex = 3;
cffb5e49
LR		 732 break;
733
734 default:
735 return -EINVAL;
736 }
737
738 for (i = 0; i < ATH_INI_NUM_SPLIT; i++) {
739 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex);
740 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
741 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
742 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
423e38e8 743 if (i == ATH_INI_POST && AR_SREV_9462_20(ah))
2577c6e8
SB		 744 ar9003_hw_prog_ini(ah,
745 &ah->ini_radio_post_sys2ant,
746 modesIndex);
cffb5e49
LR		 747 }
748
749 REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
8bc45c6b
GJ		 750 if (AR_SREV_9550(ah))
751 REG_WRITE_ARRAY(&ah->ini_modes_rx_gain_bounds, modesIndex,
752 regWrites);
753
754 if (AR_SREV_9550(ah)) {
755 int modes_txgain_index;
756
757 modes_txgain_index = ar9550_hw_get_modes_txgain_index(ah, chan);
758 if (modes_txgain_index < 0)
759 return -EINVAL;
760
761 REG_WRITE_ARRAY(&ah->iniModesTxGain, modes_txgain_index,
762 regWrites);
763 } else {
764 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
765 }
cffb5e49
LR		 766
767 /*
768 * For 5GHz channels requiring Fast Clock, apply
769 * different modal values.
770 */
6b42e8d0 771 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
c7d36f9f 772 REG_WRITE_ARRAY(&ah->iniModesFastClock,
cffb5e49
LR		 773 modesIndex, regWrites);
774
c7d36f9f 775 REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites);
d89baac8 776
9951c4d0 777 if (chan->channel == 2484)
57527f8d 778 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1);
9951c4d0 779
a4a2954f 780 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
c8b6fbe1
RM		 781 REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE,
782 AR_GLB_SWREG_DISCONT_EN_BT_WLAN);
783
5f0c04ea 784 ah->modes_index = modesIndex;
cffb5e49
LR		 785 ar9003_hw_override_ini(ah);
786 ar9003_hw_set_channel_regs(ah, chan);
787 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
64ea57d0 788 ath9k_hw_apply_txpower(ah, chan, false);
cffb5e49 789
a4a2954f 790 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
8ad74c4d 791 if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0,
a4a2954f 792 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL))
8ad74c4d
RM		 793 ah->enabled_cals |= TX_IQ_CAL;
794 else
795 ah->enabled_cals &= ~TX_IQ_CAL;
796
797 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE)
798 ah->enabled_cals |= TX_CL_CAL;
799 else
800 ah->enabled_cals &= ~TX_CL_CAL;
801 }
802
cffb5e49 803 return 0;
8525f280
LR		 804}
805
806static void ar9003_hw_set_rfmode(struct ath_hw *ah,
807 struct ath9k_channel *chan)
808{
af914a9f
LR		 809 u32 rfMode = 0;
810
811 if (chan == NULL)
812 return;
813
814 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
815 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
816
6b42e8d0 817 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
af914a9f 818 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
08685ce3
FF		 819 if (IS_CHAN_QUARTER_RATE(chan))
820 rfMode |= AR_PHY_MODE_QUARTER;
821 if (IS_CHAN_HALF_RATE(chan))
822 rfMode |= AR_PHY_MODE_HALF;
af914a9f 823
3e61d3f9
FF		 824 if (rfMode & (AR_PHY_MODE_QUARTER | AR_PHY_MODE_HALF))
825 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
826 AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW, 3);
827
af914a9f 828 REG_WRITE(ah, AR_PHY_MODE, rfMode);
8525f280
LR		 829}
830
831static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
832{
af914a9f 833 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
8525f280
LR		 834}
835
836static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
837 struct ath9k_channel *chan)
838{
af914a9f
LR		 839 u32 coef_scaled, ds_coef_exp, ds_coef_man;
840 u32 clockMhzScaled = 0x64000000;
841 struct chan_centers centers;
842
843 /*
844 * half and quarter rate can divide the scaled clock by 2 or 4
845 * scale for selected channel bandwidth
846 */
847 if (IS_CHAN_HALF_RATE(chan))
848 clockMhzScaled = clockMhzScaled >> 1;
849 else if (IS_CHAN_QUARTER_RATE(chan))
850 clockMhzScaled = clockMhzScaled >> 2;
851
852 /*
853 * ALGO -> coef = 1e8/fcarrier*fclock/40;
854 * scaled coef to provide precision for this floating calculation
855 */
856 ath9k_hw_get_channel_centers(ah, chan, &centers);
857 coef_scaled = clockMhzScaled / centers.synth_center;
858
859 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
860 &ds_coef_exp);
861
862 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
863 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
864 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
865 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
866
867 /*
868 * For Short GI,
869 * scaled coeff is 9/10 that of normal coeff
870 */
871 coef_scaled = (9 * coef_scaled) / 10;
872
873 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
874 &ds_coef_exp);
875
876 /* for short gi */
877 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
878 AR_PHY_SGI_DSC_MAN, ds_coef_man);
879 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
880 AR_PHY_SGI_DSC_EXP, ds_coef_exp);
8525f280
LR		 881}
882
883static bool ar9003_hw_rfbus_req(struct ath_hw *ah)
884{
af914a9f
LR		 885 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
886 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
887 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
8525f280
LR		 888}
889
af914a9f
LR		 890/*
891 * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN).
892 * Read the phy active delay register. Value is in 100ns increments.
893 */
8525f280
LR		 894static void ar9003_hw_rfbus_done(struct ath_hw *ah)
895{
af914a9f 896 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
af914a9f 897
7c5adc8d 898 ath9k_hw_synth_delay(ah, ah->curchan, synthDelay);
af914a9f
LR		 899
900 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
8525f280
LR		 901}
902
c16fcb49
FF		 903static bool ar9003_hw_ani_control(struct ath_hw *ah,
904 enum ath9k_ani_cmd cmd, int param)
905{
af914a9f 906 struct ath_common *common = ath9k_hw_common(ah);
e36b27af 907 struct ath9k_channel *chan = ah->curchan;
c24bd362 908 struct ar5416AniState *aniState = &ah->ani;
ff23e084
SM		 909 int m1ThreshLow, m2ThreshLow;
910 int m1Thresh, m2Thresh;
911 int m2CountThr, m2CountThrLow;
912 int m1ThreshLowExt, m2ThreshLowExt;
913 int m1ThreshExt, m2ThreshExt;
e36b27af 914 s32 value, value2;
af914a9f
LR		 915
916 switch (cmd & ah->ani_function) {
af914a9f 917 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
e36b27af
LR		 918 /*
919 * on == 1 means ofdm weak signal detection is ON
920 * on == 1 is the default, for less noise immunity
921 *
922 * on == 0 means ofdm weak signal detection is OFF
923 * on == 0 means more noise imm
924 */
af914a9f 925 u32 on = param ? 1 : 0;
af914a9f 926
ff23e084
SM		 927 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
928 goto skip_ws_det;
929
930 m1ThreshLow = on ?
931 aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
932 m2ThreshLow = on ?
933 aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
934 m1Thresh = on ?
935 aniState->iniDef.m1Thresh : m1Thresh_off;
936 m2Thresh = on ?
937 aniState->iniDef.m2Thresh : m2Thresh_off;
938 m2CountThr = on ?
939 aniState->iniDef.m2CountThr : m2CountThr_off;
940 m2CountThrLow = on ?
941 aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
942 m1ThreshLowExt = on ?
943 aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
944 m2ThreshLowExt = on ?
945 aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
946 m1ThreshExt = on ?
947 aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
948 m2ThreshExt = on ?
949 aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
950
951 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
952 AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
953 m1ThreshLow);
954 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
955 AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
956 m2ThreshLow);
957 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
958 AR_PHY_SFCORR_M1_THRESH,
959 m1Thresh);
960 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
961 AR_PHY_SFCORR_M2_THRESH,
962 m2Thresh);
963 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
964 AR_PHY_SFCORR_M2COUNT_THR,
965 m2CountThr);
966 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
967 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
968 m2CountThrLow);
969 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
970 AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
971 m1ThreshLowExt);
972 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
973 AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
974 m2ThreshLowExt);
975 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
976 AR_PHY_SFCORR_EXT_M1_THRESH,
977 m1ThreshExt);
978 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
979 AR_PHY_SFCORR_EXT_M2_THRESH,
980 m2ThreshExt);
981skip_ws_det:
af914a9f
LR		 982 if (on)
983 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
984 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
985 else
986 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
987 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
988
7067e701 989 if (on != aniState->ofdmWeakSigDetect) {
d2182b69 990 ath_dbg(common, ANI,
226afe68
JP		 991 "** ch %d: ofdm weak signal: %s=>%s\n",
992 chan->channel,
7067e701 993 aniState->ofdmWeakSigDetect ?
226afe68
JP		 994 "on" : "off",
995 on ? "on" : "off");
af914a9f
LR		 996 if (on)
997 ah->stats.ast_ani_ofdmon++;
998 else
999 ah->stats.ast_ani_ofdmoff++;
7067e701 1000 aniState->ofdmWeakSigDetect = on;
af914a9f
LR		 1001 }
1002 break;
1003 }
af914a9f 1004 case ATH9K_ANI_FIRSTEP_LEVEL:{
af914a9f
LR		 1005 u32 level = param;
1006
e36b27af 1007 if (level >= ARRAY_SIZE(firstep_table)) {
d2182b69 1008 ath_dbg(common, ANI,
226afe68
JP		 1009 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",
1010 level, ARRAY_SIZE(firstep_table));
af914a9f
LR		 1011 return false;
1012 }
e36b27af
LR		 1013
1014 /*
1015 * make register setting relative to default
1016 * from INI file & cap value
1017 */
1018 value = firstep_table[level] -
465dce62 1019 firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
e36b27af
LR		 1020 aniState->iniDef.firstep;
1021 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1022 value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1023 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1024 value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
af914a9f
LR		 1025 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1026 AR_PHY_FIND_SIG_FIRSTEP,
e36b27af
LR		 1027 value);
1028 /*
1029 * we need to set first step low register too
1030 * make register setting relative to default
1031 * from INI file & cap value
1032 */
1033 value2 = firstep_table[level] -
465dce62 1034 firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
e36b27af
LR		 1035 aniState->iniDef.firstepLow;
1036 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1037 value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1038 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1039 value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1040
1041 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
1042 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2);
1043
1044 if (level != aniState->firstepLevel) {
d2182b69 1045 ath_dbg(common, ANI,
226afe68
JP		 1046 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
1047 chan->channel,
1048 aniState->firstepLevel,
1049 level,
465dce62 1050 ATH9K_ANI_FIRSTEP_LVL,
226afe68
JP		 1051 value,
1052 aniState->iniDef.firstep);
d2182b69 1053 ath_dbg(common, ANI,
226afe68
JP		 1054 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
1055 chan->channel,
1056 aniState->firstepLevel,
1057 level,
465dce62 1058 ATH9K_ANI_FIRSTEP_LVL,
226afe68
JP		 1059 value2,
1060 aniState->iniDef.firstepLow);
e36b27af
LR		 1061 if (level > aniState->firstepLevel)
1062 ah->stats.ast_ani_stepup++;
1063 else if (level < aniState->firstepLevel)
1064 ah->stats.ast_ani_stepdown++;
1065 aniState->firstepLevel = level;
1066 }
af914a9f
LR		 1067 break;
1068 }
1069 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
af914a9f
LR		 1070 u32 level = param;
1071
e36b27af 1072 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
d2182b69 1073 ath_dbg(common, ANI,
226afe68
JP		 1074 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",
1075 level, ARRAY_SIZE(cycpwrThr1_table));
af914a9f
LR		 1076 return false;
1077 }
e36b27af
LR		 1078 /*
1079 * make register setting relative to default
1080 * from INI file & cap value
1081 */
1082 value = cycpwrThr1_table[level] -
465dce62 1083 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
e36b27af
LR		 1084 aniState->iniDef.cycpwrThr1;
1085 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1086 value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1087 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1088 value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
af914a9f
LR		 1089 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
1090 AR_PHY_TIMING5_CYCPWR_THR1,
e36b27af
LR		 1091 value);
1092
1093 /*
1094 * set AR_PHY_EXT_CCA for extension channel
1095 * make register setting relative to default
1096 * from INI file & cap value
1097 */
1098 value2 = cycpwrThr1_table[level] -
465dce62 1099 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
e36b27af
LR		 1100 aniState->iniDef.cycpwrThr1Ext;
1101 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1102 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1103 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1104 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1105 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
1106 AR_PHY_EXT_CYCPWR_THR1, value2);
1107
1108 if (level != aniState->spurImmunityLevel) {
d2182b69 1109 ath_dbg(common, ANI,
226afe68
JP		 1110 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
1111 chan->channel,
1112 aniState->spurImmunityLevel,
1113 level,
465dce62 1114 ATH9K_ANI_SPUR_IMMUNE_LVL,
226afe68
JP		 1115 value,
1116 aniState->iniDef.cycpwrThr1);
d2182b69 1117 ath_dbg(common, ANI,
226afe68
JP		 1118 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
1119 chan->channel,
1120 aniState->spurImmunityLevel,
1121 level,
465dce62 1122 ATH9K_ANI_SPUR_IMMUNE_LVL,
226afe68
JP		 1123 value2,
1124 aniState->iniDef.cycpwrThr1Ext);
e36b27af
LR		 1125 if (level > aniState->spurImmunityLevel)
1126 ah->stats.ast_ani_spurup++;
1127 else if (level < aniState->spurImmunityLevel)
1128 ah->stats.ast_ani_spurdown++;
1129 aniState->spurImmunityLevel = level;
1130 }
af914a9f
LR		 1131 break;
1132 }
e36b27af
LR		 1133 case ATH9K_ANI_MRC_CCK:{
1134 /*
1135 * is_on == 1 means MRC CCK ON (default, less noise imm)
1136 * is_on == 0 means MRC CCK is OFF (more noise imm)
1137 */
1138 bool is_on = param ? 1 : 0;
1139 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1140 AR_PHY_MRC_CCK_ENABLE, is_on);
1141 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1142 AR_PHY_MRC_CCK_MUX_REG, is_on);
81b67fd6 1143 if (is_on != aniState->mrcCCK) {
d2182b69 1144 ath_dbg(common, ANI, "** ch %d: MRC CCK: %s=>%s\n",
226afe68 1145 chan->channel,
81b67fd6 1146 aniState->mrcCCK ? "on" : "off",
226afe68 1147 is_on ? "on" : "off");
e36b27af
LR		 1148 if (is_on)
1149 ah->stats.ast_ani_ccklow++;
1150 else
1151 ah->stats.ast_ani_cckhigh++;
81b67fd6 1152 aniState->mrcCCK = is_on;
e36b27af
LR		 1153 }
1154 break;
1155 }
af914a9f
LR		 1156 case ATH9K_ANI_PRESENT:
1157 break;
1158 default:
d2182b69 1159 ath_dbg(common, ANI, "invalid cmd %u\n", cmd);
af914a9f
LR		 1160 return false;
1161 }
1162
d2182b69 1163 ath_dbg(common, ANI,
226afe68
JP		 1164 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1165 aniState->spurImmunityLevel,
7067e701 1166 aniState->ofdmWeakSigDetect ? "on" : "off",
226afe68 1167 aniState->firstepLevel,
81b67fd6 1168 aniState->mrcCCK ? "on" : "off",
226afe68
JP		 1169 aniState->listenTime,
1170 aniState->ofdmPhyErrCount,
1171 aniState->cckPhyErrCount);
af914a9f 1172 return true;
c16fcb49
FF		 1173}
1174
641d9921
FF		 1175static void ar9003_hw_do_getnf(struct ath_hw *ah,
1176 int16_t nfarray[NUM_NF_READINGS])
1177{
b06af7a5
VT		 1178#define AR_PHY_CH_MINCCA_PWR 0x1FF00000
1179#define AR_PHY_CH_MINCCA_PWR_S 20
1180#define AR_PHY_CH_EXT_MINCCA_PWR 0x01FF0000
1181#define AR_PHY_CH_EXT_MINCCA_PWR_S 16
641d9921 1182
b06af7a5
VT		 1183 int16_t nf;
1184 int i;
866b7780 1185
b06af7a5
VT		 1186 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1187 if (ah->rxchainmask & BIT(i)) {
1188 nf = MS(REG_READ(ah, ah->nf_regs[i]),
1189 AR_PHY_CH_MINCCA_PWR);
1190 nfarray[i] = sign_extend32(nf, 8);
641d9921 1191
b06af7a5
VT		 1192 if (IS_CHAN_HT40(ah->curchan)) {
1193 u8 ext_idx = AR9300_MAX_CHAINS + i;
641d9921 1194
b06af7a5
VT		 1195 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]),
1196 AR_PHY_CH_EXT_MINCCA_PWR);
1197 nfarray[ext_idx] = sign_extend32(nf, 8);
1198 }
1199 }
1200 }
641d9921
FF		 1201}
1202
f2552e28 1203static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
641d9921 1204{
f2552e28
FF		 1205 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
1206 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
ae245cde 1207 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ;
f2552e28
FF		 1208 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
1209 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
1210 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ;
ae245cde
SM		 1211
1212 if (AR_SREV_9330(ah))
1213 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ;
1214
a4a2954f 1215 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
ae245cde
SM		 1216 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ;
1217 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9462_2GHZ;
1218 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ;
1219 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9462_5GHZ;
1220 }
641d9921
FF		 1221}
1222
e36b27af
LR		 1223/*
1224 * Initialize the ANI register values with default (ini) values.
1225 * This routine is called during a (full) hardware reset after
1226 * all the registers are initialised from the INI.
1227 */
1228static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
1229{
1230 struct ar5416AniState *aniState;
1231 struct ath_common *common = ath9k_hw_common(ah);
1232 struct ath9k_channel *chan = ah->curchan;
1233 struct ath9k_ani_default *iniDef;
e36b27af
LR		 1234 u32 val;
1235
c24bd362 1236 aniState = &ah->ani;
e36b27af
LR		 1237 iniDef = &aniState->iniDef;
1238
d2182b69 1239 ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
226afe68
JP		 1240 ah->hw_version.macVersion,
1241 ah->hw_version.macRev,
1242 ah->opmode,
1243 chan->channel,
1244 chan->channelFlags);
e36b27af
LR		 1245
1246 val = REG_READ(ah, AR_PHY_SFCORR);
1247 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1248 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1249 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1250
1251 val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1252 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1253 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1254 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1255
1256 val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1257 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1258 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1259 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1260 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1261 iniDef->firstep = REG_READ_FIELD(ah,
1262 AR_PHY_FIND_SIG,
1263 AR_PHY_FIND_SIG_FIRSTEP);
1264 iniDef->firstepLow = REG_READ_FIELD(ah,
1265 AR_PHY_FIND_SIG_LOW,
1266 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW);
1267 iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1268 AR_PHY_TIMING5,
1269 AR_PHY_TIMING5_CYCPWR_THR1);
1270 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1271 AR_PHY_EXT_CCA,
1272 AR_PHY_EXT_CYCPWR_THR1);
1273
1274 /* these levels just got reset to defaults by the INI */
465dce62
FF		 1275 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
1276 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
4f4395c6 1277 aniState->ofdmWeakSigDetect = true;
81b67fd6 1278 aniState->mrcCCK = true;
e36b27af
LR		 1279}
1280
4e8c14e9
FF		 1281static void ar9003_hw_set_radar_params(struct ath_hw *ah,
1282 struct ath_hw_radar_conf *conf)
1283{
1284 u32 radar_0 = 0, radar_1 = 0;
1285
1286 if (!conf) {
1287 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
1288 return;
1289 }
1290
1291 radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
1292 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1293 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
1294 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
1295 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
1296 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
1297
1298 radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
1299 radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
1300 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
1301 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
1302 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
1303
1304 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1305 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1306 if (conf->ext_channel)
1307 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1308 else
1309 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1310}
1311
c5d0855a
FF		 1312static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
1313{
1314 struct ath_hw_radar_conf *conf = &ah->radar_conf;
1315
1316 conf->fir_power = -28;
1317 conf->radar_rssi = 0;
1318 conf->pulse_height = 10;
1319 conf->pulse_rssi = 24;
1320 conf->pulse_inband = 8;
1321 conf->pulse_maxlen = 255;
1322 conf->pulse_inband_step = 12;
1323 conf->radar_inband = 8;
1324}
1325
6bcbc062 1326static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah,
9aa49ea3 1327 struct ath_hw_antcomb_conf *antconf)
6bcbc062
MSS		 1328{
1329 u32 regval;
1330
1331 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
9aa49ea3
SM		 1332 antconf->main_lna_conf = (regval & AR_PHY_ANT_DIV_MAIN_LNACONF) >>
1333 AR_PHY_ANT_DIV_MAIN_LNACONF_S;
1334 antconf->alt_lna_conf = (regval & AR_PHY_ANT_DIV_ALT_LNACONF) >>
1335 AR_PHY_ANT_DIV_ALT_LNACONF_S;
1336 antconf->fast_div_bias = (regval & AR_PHY_ANT_FAST_DIV_BIAS) >>
1337 AR_PHY_ANT_FAST_DIV_BIAS_S;
cd0ed1b5 1338
c4cf2c58
GJ		 1339 if (AR_SREV_9330_11(ah)) {
1340 antconf->lna1_lna2_delta = -9;
1341 antconf->div_group = 1;
1342 } else if (AR_SREV_9485(ah)) {
cd0ed1b5
GJ		 1343 antconf->lna1_lna2_delta = -9;
1344 antconf->div_group = 2;
5317c9c3
SM		 1345 } else if (AR_SREV_9565(ah)) {
1346 antconf->lna1_lna2_delta = -3;
1347 antconf->div_group = 3;
cd0ed1b5
GJ		 1348 } else {
1349 antconf->lna1_lna2_delta = -3;
1350 antconf->div_group = 0;
1351 }
6bcbc062
MSS		 1352}
1353
1354static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah,
1355 struct ath_hw_antcomb_conf *antconf)
1356{
1357 u32 regval;
1358
1359 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
9aa49ea3
SM		 1360 regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1361 AR_PHY_ANT_DIV_ALT_LNACONF |
1362 AR_PHY_ANT_FAST_DIV_BIAS |
1363 AR_PHY_ANT_DIV_MAIN_GAINTB |
1364 AR_PHY_ANT_DIV_ALT_GAINTB);
1365 regval |= ((antconf->main_lna_conf << AR_PHY_ANT_DIV_MAIN_LNACONF_S)
1366 & AR_PHY_ANT_DIV_MAIN_LNACONF);
1367 regval |= ((antconf->alt_lna_conf << AR_PHY_ANT_DIV_ALT_LNACONF_S)
1368 & AR_PHY_ANT_DIV_ALT_LNACONF);
1369 regval |= ((antconf->fast_div_bias << AR_PHY_ANT_FAST_DIV_BIAS_S)
1370 & AR_PHY_ANT_FAST_DIV_BIAS);
1371 regval |= ((antconf->main_gaintb << AR_PHY_ANT_DIV_MAIN_GAINTB_S)
1372 & AR_PHY_ANT_DIV_MAIN_GAINTB);
1373 regval |= ((antconf->alt_gaintb << AR_PHY_ANT_DIV_ALT_GAINTB_S)
1374 & AR_PHY_ANT_DIV_ALT_GAINTB);
6bcbc062
MSS		 1375
1376 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1377}
1378
362cd03f
SM		 1379static void ar9003_hw_antctrl_shared_chain_lnadiv(struct ath_hw *ah,
1380 bool enable)
1381{
1382 u8 ant_div_ctl1;
1383 u32 regval;
1384
1385 if (!AR_SREV_9565(ah))
1386 return;
1387
1388 ah->shared_chain_lnadiv = enable;
1389 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
1390
1391 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1392 regval &= (~AR_ANT_DIV_CTRL_ALL);
1393 regval |= (ant_div_ctl1 & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
1394 regval &= ~AR_PHY_ANT_DIV_LNADIV;
1395 regval |= ((ant_div_ctl1 >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S;
1396
1397 if (enable)
1398 regval |= AR_ANT_DIV_ENABLE;
1399
1400 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1401
1402 regval = REG_READ(ah, AR_PHY_CCK_DETECT);
1403 regval &= ~AR_FAST_DIV_ENABLE;
1404 regval |= ((ant_div_ctl1 >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S;
1405
1406 if (enable)
1407 regval |= AR_FAST_DIV_ENABLE;
1408
1409 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
1410
1411 if (enable) {
1412 REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1413 (1 << AR_PHY_ANT_SW_RX_PROT_S));
302a3c3a 1414 if (ah->curchan && IS_CHAN_2GHZ(ah->curchan))
362cd03f
SM		 1415 REG_SET_BIT(ah, AR_PHY_RESTART,
1416 AR_PHY_RESTART_ENABLE_DIV_M2FLAG);
1417 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV,
1418 AR_BTCOEX_WL_LNADIV_FORCE_ON);
1419 } else {
1420 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL, AR_ANT_DIV_ENABLE);
1421 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1422 (1 << AR_PHY_ANT_SW_RX_PROT_S));
1423 REG_CLR_BIT(ah, AR_PHY_CCK_DETECT, AR_FAST_DIV_ENABLE);
1424 REG_CLR_BIT(ah, AR_BTCOEX_WL_LNADIV,
1425 AR_BTCOEX_WL_LNADIV_FORCE_ON);
1426
1427 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1428 regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1429 AR_PHY_ANT_DIV_ALT_LNACONF |
1430 AR_PHY_ANT_DIV_MAIN_GAINTB |
1431 AR_PHY_ANT_DIV_ALT_GAINTB);
1432 regval |= (AR_PHY_ANT_DIV_LNA1 << AR_PHY_ANT_DIV_MAIN_LNACONF_S);
1433 regval |= (AR_PHY_ANT_DIV_LNA2 << AR_PHY_ANT_DIV_ALT_LNACONF_S);
1434 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1435 }
1436}
1437
5f0c04ea
RM		 1438static int ar9003_hw_fast_chan_change(struct ath_hw *ah,
1439 struct ath9k_channel *chan,
1440 u8 *ini_reloaded)
1441{
1442 unsigned int regWrites = 0;
1443 u32 modesIndex;
1444
1445 switch (chan->chanmode) {
1446 case CHANNEL_A:
1447 case CHANNEL_A_HT20:
1448 modesIndex = 1;
1449 break;
1450 case CHANNEL_A_HT40PLUS:
1451 case CHANNEL_A_HT40MINUS:
1452 modesIndex = 2;
1453 break;
1454 case CHANNEL_G:
1455 case CHANNEL_G_HT20:
1456 case CHANNEL_B:
1457 modesIndex = 4;
1458 break;
1459 case CHANNEL_G_HT40PLUS:
1460 case CHANNEL_G_HT40MINUS:
1461 modesIndex = 3;
1462 break;
1463
1464 default:
1465 return -EINVAL;
1466 }
1467
1468 if (modesIndex == ah->modes_index) {
1469 *ini_reloaded = false;
1470 goto set_rfmode;
1471 }
1472
1473 ar9003_hw_prog_ini(ah, &ah->iniSOC[ATH_INI_POST], modesIndex);
1474 ar9003_hw_prog_ini(ah, &ah->iniMac[ATH_INI_POST], modesIndex);
1475 ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex);
1476 ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex);
aaa53ee9 1477
423e38e8 1478 if (AR_SREV_9462_20(ah))
aaa53ee9
SM		 1479 ar9003_hw_prog_ini(ah, &ah->ini_radio_post_sys2ant,
1480 modesIndex);
5f0c04ea
RM		 1481
1482 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1483
1484 /*
1485 * For 5GHz channels requiring Fast Clock, apply
1486 * different modal values.
1487 */
1488 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
c7d36f9f 1489 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, regWrites);
5f0c04ea 1490
aaa53ee9
SM		 1491 if (AR_SREV_9565(ah))
1492 REG_WRITE_ARRAY(&ah->iniModesFastClock, 1, regWrites);
1493
c7d36f9f 1494 REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites);
5f0c04ea
RM		 1495
1496 ah->modes_index = modesIndex;
1497 *ini_reloaded = true;
1498
1499set_rfmode:
1500 ar9003_hw_set_rfmode(ah, chan);
1501 return 0;
1502}
1503
e93d083f
SW		 1504static void ar9003_hw_spectral_scan_config(struct ath_hw *ah,
1505 struct ath_spec_scan *param)
1506{
1507 u8 count;
1508
1509 if (!param->enabled) {
1510 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1511 AR_PHY_SPECTRAL_SCAN_ENABLE);
1512 return;
1513 }
1514
1515 REG_SET_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_FFT_ENA);
1516 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE);
1517
1518 /* on AR93xx and newer, count = 0 will make the the chip send
1519 * spectral samples endlessly. Check if this really was intended,
1520 * and fix otherwise.
1521 */
1522 count = param->count;
1523 if (param->endless)
1524 count = 0;
1525 else if (param->count == 0)
1526 count = 1;
1527
1528 if (param->short_repeat)
1529 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1530 AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT);
1531 else
1532 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1533 AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT);
1534
1535 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1536 AR_PHY_SPECTRAL_SCAN_COUNT, count);
1537 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1538 AR_PHY_SPECTRAL_SCAN_PERIOD, param->period);
1539 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1540 AR_PHY_SPECTRAL_SCAN_FFT_PERIOD, param->fft_period);
1541
1542 return;
1543}
1544
1545static void ar9003_hw_spectral_scan_trigger(struct ath_hw *ah)
1546{
1547 /* Activate spectral scan */
1548 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1549 AR_PHY_SPECTRAL_SCAN_ACTIVE);
1550}
1551
1552static void ar9003_hw_spectral_scan_wait(struct ath_hw *ah)
1553{
1554 struct ath_common *common = ath9k_hw_common(ah);
1555
1556 /* Poll for spectral scan complete */
1557 if (!ath9k_hw_wait(ah, AR_PHY_SPECTRAL_SCAN,
1558 AR_PHY_SPECTRAL_SCAN_ACTIVE,
1559 0, AH_WAIT_TIMEOUT)) {
1560 ath_err(common, "spectral scan wait failed\n");
1561 return;
1562 }
1563}
1564
8525f280
LR		 1565void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
1566{
1567 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
6bcbc062 1568 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
07b2fa5a 1569 static const u32 ar9300_cca_regs[6] = {
bbacee13
FF		 1570 AR_PHY_CCA_0,
1571 AR_PHY_CCA_1,
1572 AR_PHY_CCA_2,
1573 AR_PHY_EXT_CCA,
1574 AR_PHY_EXT_CCA_1,
1575 AR_PHY_EXT_CCA_2,
1576 };
8525f280
LR		 1577
1578 priv_ops->rf_set_freq = ar9003_hw_set_channel;
1579 priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
1580 priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
1581 priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
1582 priv_ops->init_bb = ar9003_hw_init_bb;
1583 priv_ops->process_ini = ar9003_hw_process_ini;
1584 priv_ops->set_rfmode = ar9003_hw_set_rfmode;
1585 priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive;
1586 priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
1587 priv_ops->rfbus_req = ar9003_hw_rfbus_req;
1588 priv_ops->rfbus_done = ar9003_hw_rfbus_done;
c16fcb49 1589 priv_ops->ani_control = ar9003_hw_ani_control;
641d9921 1590 priv_ops->do_getnf = ar9003_hw_do_getnf;
e36b27af 1591 priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
4e8c14e9 1592 priv_ops->set_radar_params = ar9003_hw_set_radar_params;
5f0c04ea 1593 priv_ops->fast_chan_change = ar9003_hw_fast_chan_change;
f2552e28 1594
6bcbc062
MSS		 1595 ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get;
1596 ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set;
362cd03f 1597 ops->antctrl_shared_chain_lnadiv = ar9003_hw_antctrl_shared_chain_lnadiv;
e93d083f
SW		 1598 ops->spectral_scan_config = ar9003_hw_spectral_scan_config;
1599 ops->spectral_scan_trigger = ar9003_hw_spectral_scan_trigger;
1600 ops->spectral_scan_wait = ar9003_hw_spectral_scan_wait;
6bcbc062 1601
f2552e28 1602 ar9003_hw_set_nf_limits(ah);
c5d0855a 1603 ar9003_hw_set_radar_conf(ah);
bbacee13 1604 memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
8525f280 1605}
aea702b7
LR		 1606
1607void ar9003_hw_bb_watchdog_config(struct ath_hw *ah)
1608{
1609 struct ath_common *common = ath9k_hw_common(ah);
1610 u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms;
1611 u32 val, idle_count;
1612
1613 if (!idle_tmo_ms) {
1614 /* disable IRQ, disable chip-reset for BB panic */
1615 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1616 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) &
1617 ~(AR_PHY_WATCHDOG_RST_ENABLE |
1618 AR_PHY_WATCHDOG_IRQ_ENABLE));
1619
1620 /* disable watchdog in non-IDLE mode, disable in IDLE mode */
1621 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1622 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) &
1623 ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1624 AR_PHY_WATCHDOG_IDLE_ENABLE));
1625
d2182b69 1626 ath_dbg(common, RESET, "Disabled BB Watchdog\n");
aea702b7
LR		 1627 return;
1628 }
1629
1630 /* enable IRQ, disable chip-reset for BB watchdog */
1631 val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK;
1632 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1633 (val | AR_PHY_WATCHDOG_IRQ_ENABLE) &
1634 ~AR_PHY_WATCHDOG_RST_ENABLE);
1635
1636 /* bound limit to 10 secs */
1637 if (idle_tmo_ms > 10000)
1638 idle_tmo_ms = 10000;
1639
1640 /*
1641 * The time unit for watchdog event is 2^15 44/88MHz cycles.
1642 *
1643 * For HT20 we have a time unit of 2^15/44 MHz = .74 ms per tick
1644 * For HT40 we have a time unit of 2^15/88 MHz = .37 ms per tick
1645 *
1646 * Given we use fast clock now in 5 GHz, these time units should
1647 * be common for both 2 GHz and 5 GHz.
1648 */
1649 idle_count = (100 * idle_tmo_ms) / 74;
1650 if (ah->curchan && IS_CHAN_HT40(ah->curchan))
1651 idle_count = (100 * idle_tmo_ms) / 37;
1652
1653 /*
1654 * enable watchdog in non-IDLE mode, disable in IDLE mode,
1655 * set idle time-out.
1656 */
1657 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1658 AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1659 AR_PHY_WATCHDOG_IDLE_MASK |
1660 (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2)));
1661
d2182b69 1662 ath_dbg(common, RESET, "Enabled BB Watchdog timeout (%u ms)\n",
226afe68 1663 idle_tmo_ms);
aea702b7
LR		 1664}
1665
1666void ar9003_hw_bb_watchdog_read(struct ath_hw *ah)
1667{
1668 /*
1669 * we want to avoid printing in ISR context so we save the
1670 * watchdog status to be printed later in bottom half context.
1671 */
1672 ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS);
1673
1674 /*
1675 * the watchdog timer should reset on status read but to be sure
1676 * sure we write 0 to the watchdog status bit.
1677 */
1678 REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS,
1679 ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR);
1680}
1681
1682void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah)
1683{
1684 struct ath_common *common = ath9k_hw_common(ah);
9dbebc7f 1685 u32 status;
aea702b7
LR		 1686
1687 if (likely(!(common->debug_mask & ATH_DBG_RESET)))
1688 return;
1689
1690 status = ah->bb_watchdog_last_status;
d2182b69 1691 ath_dbg(common, RESET,
226afe68 1692 "\n==== BB update: BB status=0x%08x ====\n", status);
d2182b69 1693 ath_dbg(common, RESET,
226afe68
JP		 1694 "** BB state: wd=%u det=%u rdar=%u rOFDM=%d rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
1695 MS(status, AR_PHY_WATCHDOG_INFO),
1696 MS(status, AR_PHY_WATCHDOG_DET_HANG),
1697 MS(status, AR_PHY_WATCHDOG_RADAR_SM),
1698 MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM),
1699 MS(status, AR_PHY_WATCHDOG_RX_CCK_SM),
1700 MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM),
1701 MS(status, AR_PHY_WATCHDOG_TX_CCK_SM),
1702 MS(status, AR_PHY_WATCHDOG_AGC_SM),
1703 MS(status, AR_PHY_WATCHDOG_SRCH_SM));
1704
d2182b69 1705 ath_dbg(common, RESET, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
226afe68
JP		 1706 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1),
1707 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2));
d2182b69 1708 ath_dbg(common, RESET, "** BB mode: BB_gen_controls=0x%08x **\n",
226afe68 1709 REG_READ(ah, AR_PHY_GEN_CTRL));
aea702b7 1710
b5bfc568
FF		 1711#define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles)
1712 if (common->cc_survey.cycles)
d2182b69 1713 ath_dbg(common, RESET,
226afe68
JP		 1714 "** BB busy times: rx_clear=%d%%, rx_frame=%d%%, tx_frame=%d%% **\n",
1715 PCT(rx_busy), PCT(rx_frame), PCT(tx_frame));
aea702b7 1716
d2182b69 1717 ath_dbg(common, RESET, "==== BB update: done ====\n\n");
aea702b7
LR		 1718}
1719EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info);
51ac8cbb
RM		 1720
1721void ar9003_hw_disable_phy_restart(struct ath_hw *ah)
1722{
1723 u32 val;
1724
1725 /* While receiving unsupported rate frame rx state machine
1726 * gets into a state 0xb and if phy_restart happens in that
1727 * state, BB would go hang. If RXSM is in 0xb state after
1728 * first bb panic, ensure to disable the phy_restart.
1729 */
1730 if (!((MS(ah->bb_watchdog_last_status,
1731 AR_PHY_WATCHDOG_RX_OFDM_SM) == 0xb) ||
1732 ah->bb_hang_rx_ofdm))
1733 return;
1734
1735 ah->bb_hang_rx_ofdm = true;
1736 val = REG_READ(ah, AR_PHY_RESTART);
1737 val &= ~AR_PHY_RESTART_ENA;
1738
1739 REG_WRITE(ah, AR_PHY_RESTART, val);
1740}
1741EXPORT_SYMBOL(ar9003_hw_disable_phy_restart);
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