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ath9k_hw: Add AR9565 initvals
[mirror_ubuntu-jammy-kernel.git] / drivers / net / wireless / ath / ath9k / ar9003_phy.c
CommitLineData
8525f280 1/*
5b68138e 2 * Copyright (c) 2010-2011 Atheros Communications Inc.
8525f280
LR		 3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
ee40fa06 17#include <linux/export.h>
8525f280 18#include "hw.h"
da6f1d7f 19#include "ar9003_phy.h"
8525f280 20
e36b27af
LR		 21static const int firstep_table[] =
22/* level: 0 1 2 3 4 5 6 7 8 */
23 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */
24
25static const int cycpwrThr1_table[] =
26/* level: 0 1 2 3 4 5 6 7 8 */
27 { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */
28
29/*
30 * register values to turn OFDM weak signal detection OFF
31 */
32static const int m1ThreshLow_off = 127;
33static const int m2ThreshLow_off = 127;
34static const int m1Thresh_off = 127;
35static const int m2Thresh_off = 127;
36static const int m2CountThr_off = 31;
37static const int m2CountThrLow_off = 63;
38static const int m1ThreshLowExt_off = 127;
39static const int m2ThreshLowExt_off = 127;
40static const int m1ThreshExt_off = 127;
41static const int m2ThreshExt_off = 127;
42
8525f280
LR		 43/**
44 * ar9003_hw_set_channel - set channel on single-chip device
45 * @ah: atheros hardware structure
46 * @chan:
47 *
48 * This is the function to change channel on single-chip devices, that is
e4922f2b 49 * for AR9300 family of chipsets.
8525f280
LR		 50 *
51 * This function takes the channel value in MHz and sets
52 * hardware channel value. Assumes writes have been enabled to analog bus.
53 *
54 * Actual Expression,
55 *
56 * For 2GHz channel,
57 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
58 * (freq_ref = 40MHz)
59 *
60 * For 5GHz channel,
61 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
62 * (freq_ref = 40MHz/(24>>amodeRefSel))
63 *
64 * For 5GHz channels which are 5MHz spaced,
65 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
66 * (freq_ref = 40MHz)
67 */
68static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
69{
f7abf0c1
FF		 70 u16 bMode, fracMode = 0, aModeRefSel = 0;
71 u32 freq, channelSel = 0, reg32 = 0;
72 struct chan_centers centers;
73 int loadSynthChannel;
74
75 ath9k_hw_get_channel_centers(ah, chan, &centers);
76 freq = centers.synth_center;
77
78 if (freq < 4800) { /* 2 GHz, fractional mode */
5acb4b93
GJ		 79 if (AR_SREV_9330(ah)) {
80 u32 chan_frac;
81 u32 div;
82
83 if (ah->is_clk_25mhz)
84 div = 75;
85 else
86 div = 120;
87
88 channelSel = (freq * 4) / div;
89 chan_frac = (((freq * 4) % div) * 0x20000) / div;
90 channelSel = (channelSel << 17) | chan_frac;
91 } else if (AR_SREV_9485(ah)) {
3dfd7f60
VT		 92 u32 chan_frac;
93
94 /*
95 * freq_ref = 40 / (refdiva >> amoderefsel); where refdiva=1 and amoderefsel=0
96 * ndiv = ((chan_mhz * 4) / 3) / freq_ref;
97 * chansel = int(ndiv), chanfrac = (ndiv - chansel) * 0x20000
98 */
99 channelSel = (freq * 4) / 120;
100 chan_frac = (((freq * 4) % 120) * 0x20000) / 120;
101 channelSel = (channelSel << 17) | chan_frac;
db4a3de9 102 } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah)) {
17869f4f
VT		 103 if (ah->is_clk_25mhz) {
104 u32 chan_frac;
105
106 channelSel = (freq * 2) / 75;
107 chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
108 channelSel = (channelSel << 17) | chan_frac;
109 } else
110 channelSel = CHANSEL_2G(freq) >> 1;
3dfd7f60 111 } else
85dd0921 112 channelSel = CHANSEL_2G(freq);
f7abf0c1
FF		 113 /* Set to 2G mode */
114 bMode = 1;
115 } else {
db4a3de9
GJ		 116 if ((AR_SREV_9340(ah) || AR_SREV_9550(ah)) &&
117 ah->is_clk_25mhz) {
17869f4f
VT		 118 u32 chan_frac;
119
530275e5
FF		 120 channelSel = freq / 75;
121 chan_frac = ((freq % 75) * 0x20000) / 75;
17869f4f
VT		 122 channelSel = (channelSel << 17) | chan_frac;
123 } else {
124 channelSel = CHANSEL_5G(freq);
125 /* Doubler is ON, so, divide channelSel by 2. */
126 channelSel >>= 1;
127 }
f7abf0c1
FF		 128 /* Set to 5G mode */
129 bMode = 0;
130 }
131
132 /* Enable fractional mode for all channels */
133 fracMode = 1;
134 aModeRefSel = 0;
135 loadSynthChannel = 0;
136
137 reg32 = (bMode << 29);
138 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
139
140 /* Enable Long shift Select for Synthesizer */
141 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4,
142 AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1);
143
144 /* Program Synth. setting */
145 reg32 = (channelSel << 2) | (fracMode << 30) |
146 (aModeRefSel << 28) | (loadSynthChannel << 31);
147 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
148
149 /* Toggle Load Synth channel bit */
150 loadSynthChannel = 1;
151 reg32 = (channelSel << 2) | (fracMode << 30) |
152 (aModeRefSel << 28) | (loadSynthChannel << 31);
153 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
154
155 ah->curchan = chan;
f7abf0c1 156
8525f280
LR		 157 return 0;
158}
159
160/**
e36b27af 161 * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency
8525f280
LR		 162 * @ah: atheros hardware structure
163 * @chan:
164 *
165 * For single-chip solutions. Converts to baseband spur frequency given the
166 * input channel frequency and compute register settings below.
167 *
168 * Spur mitigation for MRC CCK
169 */
1547da37
LR		 170static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
171 struct ath9k_channel *chan)
8525f280 172{
07b2fa5a 173 static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
ca375554
FF		 174 int cur_bb_spur, negative = 0, cck_spur_freq;
175 int i;
d9a2545a 176 int range, max_spur_cnts, synth_freq;
4b5237cc 177 u8 *spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah, IS_CHAN_2GHZ(chan));
ca375554
FF		 178
179 /*
180 * Need to verify range +/- 10 MHz in control channel, otherwise spur
181 * is out-of-band and can be ignored.
182 */
183
8528f12e
GJ		 184 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
185 AR_SREV_9550(ah)) {
d9a2545a
VT		 186 if (spur_fbin_ptr[0] == 0) /* No spur */
187 return;
188 max_spur_cnts = 5;
189 if (IS_CHAN_HT40(chan)) {
190 range = 19;
191 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
192 AR_PHY_GC_DYN2040_PRI_CH) == 0)
193 synth_freq = chan->channel + 10;
194 else
195 synth_freq = chan->channel - 10;
196 } else {
197 range = 10;
198 synth_freq = chan->channel;
199 }
200 } else {
38df2f07 201 range = AR_SREV_9462(ah) ? 5 : 10;
d9a2545a
VT		 202 max_spur_cnts = 4;
203 synth_freq = chan->channel;
204 }
205
206 for (i = 0; i < max_spur_cnts; i++) {
38df2f07
RM		 207 if (AR_SREV_9462(ah) && (i == 0 || i == 3))
208 continue;
ca375554 209 negative = 0;
8528f12e
GJ		 210 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
211 AR_SREV_9550(ah))
8edb254c
GJ		 212 cur_bb_spur = ath9k_hw_fbin2freq(spur_fbin_ptr[i],
213 IS_CHAN_2GHZ(chan));
d9a2545a 214 else
8edb254c 215 cur_bb_spur = spur_freq[i];
ca375554 216
8edb254c 217 cur_bb_spur -= synth_freq;
ca375554
FF		 218 if (cur_bb_spur < 0) {
219 negative = 1;
220 cur_bb_spur = -cur_bb_spur;
221 }
d9a2545a 222 if (cur_bb_spur < range) {
ca375554
FF		 223 cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
224
225 if (negative == 1)
226 cck_spur_freq = -cck_spur_freq;
227
228 cck_spur_freq = cck_spur_freq & 0xfffff;
229
230 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
231 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
232 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
233 AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
234 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
235 AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE,
236 0x2);
237 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
238 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT,
239 0x1);
240 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
241 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ,
242 cck_spur_freq);
243
244 return;
245 }
246 }
247
248 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
249 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
250 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
251 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0);
252 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
253 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
8525f280
LR		 254}
255
1547da37
LR		 256/* Clean all spur register fields */
257static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah)
258{
259 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
260 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0);
261 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
262 AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
263 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
264 AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
265 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
266 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0);
267 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
268 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0);
269 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
270 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0);
271 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
272 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0);
273 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
274 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0);
275 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
276 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0);
277
278 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
279 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0);
280 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
281 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0);
282 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
283 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0);
284 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
285 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0);
286 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
287 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0);
288 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
289 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0);
290 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
291 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0);
292 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
293 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0);
294 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
295 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0);
296 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
297 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
298}
299
300static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
301 int freq_offset,
302 int spur_freq_sd,
303 int spur_delta_phase,
304 int spur_subchannel_sd)
305{
306 int mask_index = 0;
307
308 /* OFDM Spur mitigation */
309 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
310 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1);
311 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
312 AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
313 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
314 AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
315 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
316 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd);
317 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
318 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1);
319 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
320 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1);
321 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
322 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1);
323 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
324 AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
325 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
326 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);
327
328 if (REG_READ_FIELD(ah, AR_PHY_MODE,
329 AR_PHY_MODE_DYNAMIC) == 0x1)
330 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
331 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);
332
333 mask_index = (freq_offset << 4) / 5;
334 if (mask_index < 0)
335 mask_index = mask_index - 1;
336
337 mask_index = mask_index & 0x7f;
338
339 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
340 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1);
341 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
342 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1);
343 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
344 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1);
345 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
346 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index);
347 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
348 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index);
349 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
350 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index);
351 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
352 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc);
353 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
354 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc);
355 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
356 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
357 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
358 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
359}
360
361static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
362 struct ath9k_channel *chan,
363 int freq_offset)
364{
365 int spur_freq_sd = 0;
366 int spur_subchannel_sd = 0;
367 int spur_delta_phase = 0;
368
369 if (IS_CHAN_HT40(chan)) {
370 if (freq_offset < 0) {
371 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
372 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
373 spur_subchannel_sd = 1;
374 else
375 spur_subchannel_sd = 0;
376
9d1ceac5 377 spur_freq_sd = ((freq_offset + 10) << 9) / 11;
1547da37
LR		 378
379 } else {
380 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
381 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
382 spur_subchannel_sd = 0;
383 else
384 spur_subchannel_sd = 1;
385
9d1ceac5 386 spur_freq_sd = ((freq_offset - 10) << 9) / 11;
1547da37
LR		 387
388 }
389
390 spur_delta_phase = (freq_offset << 17) / 5;
391
392 } else {
393 spur_subchannel_sd = 0;
394 spur_freq_sd = (freq_offset << 9) /11;
395 spur_delta_phase = (freq_offset << 18) / 5;
396 }
397
398 spur_freq_sd = spur_freq_sd & 0x3ff;
399 spur_delta_phase = spur_delta_phase & 0xfffff;
400
401 ar9003_hw_spur_ofdm(ah,
402 freq_offset,
403 spur_freq_sd,
404 spur_delta_phase,
405 spur_subchannel_sd);
406}
407
408/* Spur mitigation for OFDM */
409static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
410 struct ath9k_channel *chan)
411{
412 int synth_freq;
413 int range = 10;
414 int freq_offset = 0;
415 int mode;
416 u8* spurChansPtr;
417 unsigned int i;
418 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
419
420 if (IS_CHAN_5GHZ(chan)) {
421 spurChansPtr = &(eep->modalHeader5G.spurChans[0]);
422 mode = 0;
423 }
424 else {
425 spurChansPtr = &(eep->modalHeader2G.spurChans[0]);
426 mode = 1;
427 }
428
429 if (spurChansPtr[0] == 0)
430 return; /* No spur in the mode */
431
432 if (IS_CHAN_HT40(chan)) {
433 range = 19;
434 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
435 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
436 synth_freq = chan->channel - 10;
437 else
438 synth_freq = chan->channel + 10;
439 } else {
440 range = 10;
441 synth_freq = chan->channel;
442 }
443
444 ar9003_hw_spur_ofdm_clear(ah);
445
0f8e94d2 446 for (i = 0; i < AR_EEPROM_MODAL_SPURS && spurChansPtr[i]; i++) {
8edb254c
GJ		 447 freq_offset = ath9k_hw_fbin2freq(spurChansPtr[i], mode);
448 freq_offset -= synth_freq;
1547da37
LR		 449 if (abs(freq_offset) < range) {
450 ar9003_hw_spur_ofdm_work(ah, chan, freq_offset);
451 break;
452 }
453 }
454}
455
456static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
457 struct ath9k_channel *chan)
458{
459 ar9003_hw_spur_mitigate_mrc_cck(ah, chan);
460 ar9003_hw_spur_mitigate_ofdm(ah, chan);
461}
462
8525f280
LR		 463static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
464 struct ath9k_channel *chan)
465{
317d3328
FF		 466 u32 pll;
467
468 pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
469
470 if (chan && IS_CHAN_HALF_RATE(chan))
471 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
472 else if (chan && IS_CHAN_QUARTER_RATE(chan))
473 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
474
14bc1104 475 pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
317d3328
FF		 476
477 return pll;
8525f280
LR		 478}
479
480static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
481 struct ath9k_channel *chan)
482{
cffb5e49
LR		 483 u32 phymode;
484 u32 enableDacFifo = 0;
485
486 enableDacFifo =
487 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO);
488
489 /* Enable 11n HT, 20 MHz */
8ad38d22 490 phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 |
cffb5e49
LR		 491 AR_PHY_GC_SHORT_GI_40 | enableDacFifo;
492
493 /* Configure baseband for dynamic 20/40 operation */
494 if (IS_CHAN_HT40(chan)) {
495 phymode |= AR_PHY_GC_DYN2040_EN;
496 /* Configure control (primary) channel at +-10MHz */
497 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
498 (chan->chanmode == CHANNEL_G_HT40PLUS))
499 phymode |= AR_PHY_GC_DYN2040_PRI_CH;
500
501 }
502
503 /* make sure we preserve INI settings */
504 phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);
505 /* turn off Green Field detection for STA for now */
506 phymode &= ~AR_PHY_GC_GF_DETECT_EN;
507
508 REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
509
510 /* Configure MAC for 20/40 operation */
511 ath9k_hw_set11nmac2040(ah);
512
513 /* global transmit timeout (25 TUs default)*/
514 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
515 /* carrier sense timeout */
516 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
8525f280
LR		 517}
518
519static void ar9003_hw_init_bb(struct ath_hw *ah,
520 struct ath9k_channel *chan)
521{
af914a9f
LR		 522 u32 synthDelay;
523
524 /*
525 * Wait for the frequency synth to settle (synth goes on
526 * via AR_PHY_ACTIVE_EN). Read the phy active delay register.
527 * Value is in 100ns increments.
528 */
529 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
af914a9f
LR		 530
531 /* Activate the PHY (includes baseband activate + synthesizer on) */
532 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
7c5adc8d 533 ath9k_hw_synth_delay(ah, chan, synthDelay);
8525f280
LR		 534}
535
56266bff 536static void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
cffb5e49
LR		 537{
538 switch (rx) {
539 case 0x5:
540 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
541 AR_PHY_SWAP_ALT_CHAIN);
542 case 0x3:
543 case 0x1:
544 case 0x2:
545 case 0x7:
546 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
547 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
548 break;
549 default:
550 break;
551 }
552
ea066d5a
MSS		 553 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7))
554 REG_WRITE(ah, AR_SELFGEN_MASK, 0x3);
423e38e8 555 else if (AR_SREV_9462(ah))
2577c6e8
SB		 556 /* xxx only when MCI support is enabled */
557 REG_WRITE(ah, AR_SELFGEN_MASK, 0x3);
ea066d5a
MSS		 558 else
559 REG_WRITE(ah, AR_SELFGEN_MASK, tx);
560
cffb5e49
LR		 561 if (tx == 0x5) {
562 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
563 AR_PHY_SWAP_ALT_CHAIN);
564 }
565}
566
567/*
568 * Override INI values with chip specific configuration.
569 */
570static void ar9003_hw_override_ini(struct ath_hw *ah)
571{
572 u32 val;
573
574 /*
575 * Set the RX_ABORT and RX_DIS and clear it only after
576 * RXE is set for MAC. This prevents frames with
577 * corrupted descriptor status.
578 */
579 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
580
581 /*
582 * For AR9280 and above, there is a new feature that allows
583 * Multicast search based on both MAC Address and Key ID. By default,
584 * this feature is enabled. But since the driver is not using this
585 * feature, we switch it off; otherwise multicast search based on
586 * MAC addr only will fail.
587 */
588 val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
589 REG_WRITE(ah, AR_PCU_MISC_MODE2,
590 val | AR_AGG_WEP_ENABLE_FIX | AR_AGG_WEP_ENABLE);
bf3f204b
FF		 591
592 REG_SET_BIT(ah, AR_PHY_CCK_DETECT,
593 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
cffb5e49
LR		 594}
595
596static void ar9003_hw_prog_ini(struct ath_hw *ah,
597 struct ar5416IniArray *iniArr,
598 int column)
599{
600 unsigned int i, regWrites = 0;
601
602 /* New INI format: Array may be undefined (pre, core, post arrays) */
603 if (!iniArr->ia_array)
604 return;
605
606 /*
607 * New INI format: Pre, core, and post arrays for a given subsystem
608 * may be modal (> 2 columns) or non-modal (2 columns). Determine if
609 * the array is non-modal and force the column to 1.
610 */
611 if (column >= iniArr->ia_columns)
612 column = 1;
613
614 for (i = 0; i < iniArr->ia_rows; i++) {
615 u32 reg = INI_RA(iniArr, i, 0);
616 u32 val = INI_RA(iniArr, i, column);
617
7e68b746 618 REG_WRITE(ah, reg, val);
b2ccc507 619
cffb5e49
LR		 620 DO_DELAY(regWrites);
621 }
622}
623
8bc45c6b
GJ		 624static int ar9550_hw_get_modes_txgain_index(struct ath_hw *ah,
625 struct ath9k_channel *chan)
626{
627 int ret;
628
629 switch (chan->chanmode) {
630 case CHANNEL_A:
631 case CHANNEL_A_HT20:
632 if (chan->channel <= 5350)
633 ret = 1;
634 else if ((chan->channel > 5350) && (chan->channel <= 5600))
635 ret = 3;
636 else
637 ret = 5;
638 break;
639
640 case CHANNEL_A_HT40PLUS:
641 case CHANNEL_A_HT40MINUS:
642 if (chan->channel <= 5350)
643 ret = 2;
644 else if ((chan->channel > 5350) && (chan->channel <= 5600))
645 ret = 4;
646 else
647 ret = 6;
648 break;
649
650 case CHANNEL_G:
651 case CHANNEL_G_HT20:
652 case CHANNEL_B:
653 ret = 8;
654 break;
655
656 case CHANNEL_G_HT40PLUS:
657 case CHANNEL_G_HT40MINUS:
658 ret = 7;
659 break;
660
661 default:
662 ret = -EINVAL;
663 }
664
665 return ret;
666}
667
8525f280
LR		 668static int ar9003_hw_process_ini(struct ath_hw *ah,
669 struct ath9k_channel *chan)
670{
cffb5e49 671 unsigned int regWrites = 0, i;
0ff2b5c0 672 u32 modesIndex;
cffb5e49
LR		 673
674 switch (chan->chanmode) {
675 case CHANNEL_A:
676 case CHANNEL_A_HT20:
677 modesIndex = 1;
cffb5e49
LR		 678 break;
679 case CHANNEL_A_HT40PLUS:
680 case CHANNEL_A_HT40MINUS:
681 modesIndex = 2;
cffb5e49
LR		 682 break;
683 case CHANNEL_G:
684 case CHANNEL_G_HT20:
685 case CHANNEL_B:
686 modesIndex = 4;
cffb5e49
LR		 687 break;
688 case CHANNEL_G_HT40PLUS:
689 case CHANNEL_G_HT40MINUS:
690 modesIndex = 3;
cffb5e49
LR		 691 break;
692
693 default:
694 return -EINVAL;
695 }
696
697 for (i = 0; i < ATH_INI_NUM_SPLIT; i++) {
698 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex);
699 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
700 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
701 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
423e38e8 702 if (i == ATH_INI_POST && AR_SREV_9462_20(ah))
2577c6e8
SB		 703 ar9003_hw_prog_ini(ah,
704 &ah->ini_radio_post_sys2ant,
705 modesIndex);
cffb5e49
LR		 706 }
707
708 REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
8bc45c6b
GJ		 709 if (AR_SREV_9550(ah))
710 REG_WRITE_ARRAY(&ah->ini_modes_rx_gain_bounds, modesIndex,
711 regWrites);
712
713 if (AR_SREV_9550(ah)) {
714 int modes_txgain_index;
715
716 modes_txgain_index = ar9550_hw_get_modes_txgain_index(ah, chan);
717 if (modes_txgain_index < 0)
718 return -EINVAL;
719
720 REG_WRITE_ARRAY(&ah->iniModesTxGain, modes_txgain_index,
721 regWrites);
722 } else {
723 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
724 }
cffb5e49
LR		 725
726 /*
727 * For 5GHz channels requiring Fast Clock, apply
728 * different modal values.
729 */
6b42e8d0 730 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
c7d36f9f 731 REG_WRITE_ARRAY(&ah->iniModesFastClock,
cffb5e49
LR		 732 modesIndex, regWrites);
733
c7d36f9f 734 REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites);
d89baac8 735
9951c4d0
FF		 736 if (chan->channel == 2484)
737 ar9003_hw_prog_ini(ah, &ah->ini_japan2484, 1);
738
c8b6fbe1
RM		 739 if (AR_SREV_9462(ah))
740 REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE,
741 AR_GLB_SWREG_DISCONT_EN_BT_WLAN);
742
5f0c04ea 743 ah->modes_index = modesIndex;
cffb5e49
LR		 744 ar9003_hw_override_ini(ah);
745 ar9003_hw_set_channel_regs(ah, chan);
746 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
64ea57d0 747 ath9k_hw_apply_txpower(ah, chan, false);
cffb5e49 748
423e38e8 749 if (AR_SREV_9462(ah)) {
8ad74c4d
RM		 750 if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0,
751 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL))
752 ah->enabled_cals |= TX_IQ_CAL;
753 else
754 ah->enabled_cals &= ~TX_IQ_CAL;
755
756 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE)
757 ah->enabled_cals |= TX_CL_CAL;
758 else
759 ah->enabled_cals &= ~TX_CL_CAL;
760 }
761
cffb5e49 762 return 0;
8525f280
LR		 763}
764
765static void ar9003_hw_set_rfmode(struct ath_hw *ah,
766 struct ath9k_channel *chan)
767{
af914a9f
LR		 768 u32 rfMode = 0;
769
770 if (chan == NULL)
771 return;
772
773 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
774 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
775
6b42e8d0 776 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
af914a9f 777 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
08685ce3
FF		 778 if (IS_CHAN_QUARTER_RATE(chan))
779 rfMode |= AR_PHY_MODE_QUARTER;
780 if (IS_CHAN_HALF_RATE(chan))
781 rfMode |= AR_PHY_MODE_HALF;
af914a9f 782
3e61d3f9
FF		 783 if (rfMode & (AR_PHY_MODE_QUARTER | AR_PHY_MODE_HALF))
784 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
785 AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW, 3);
786
af914a9f 787 REG_WRITE(ah, AR_PHY_MODE, rfMode);
8525f280
LR		 788}
789
790static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
791{
af914a9f 792 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
8525f280
LR		 793}
794
795static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
796 struct ath9k_channel *chan)
797{
af914a9f
LR		 798 u32 coef_scaled, ds_coef_exp, ds_coef_man;
799 u32 clockMhzScaled = 0x64000000;
800 struct chan_centers centers;
801
802 /*
803 * half and quarter rate can divide the scaled clock by 2 or 4
804 * scale for selected channel bandwidth
805 */
806 if (IS_CHAN_HALF_RATE(chan))
807 clockMhzScaled = clockMhzScaled >> 1;
808 else if (IS_CHAN_QUARTER_RATE(chan))
809 clockMhzScaled = clockMhzScaled >> 2;
810
811 /*
812 * ALGO -> coef = 1e8/fcarrier*fclock/40;
813 * scaled coef to provide precision for this floating calculation
814 */
815 ath9k_hw_get_channel_centers(ah, chan, &centers);
816 coef_scaled = clockMhzScaled / centers.synth_center;
817
818 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
819 &ds_coef_exp);
820
821 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
822 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
823 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
824 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
825
826 /*
827 * For Short GI,
828 * scaled coeff is 9/10 that of normal coeff
829 */
830 coef_scaled = (9 * coef_scaled) / 10;
831
832 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
833 &ds_coef_exp);
834
835 /* for short gi */
836 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
837 AR_PHY_SGI_DSC_MAN, ds_coef_man);
838 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
839 AR_PHY_SGI_DSC_EXP, ds_coef_exp);
8525f280
LR		 840}
841
842static bool ar9003_hw_rfbus_req(struct ath_hw *ah)
843{
af914a9f
LR		 844 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
845 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
846 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
8525f280
LR		 847}
848
af914a9f
LR		 849/*
850 * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN).
851 * Read the phy active delay register. Value is in 100ns increments.
852 */
8525f280
LR		 853static void ar9003_hw_rfbus_done(struct ath_hw *ah)
854{
af914a9f 855 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
af914a9f 856
7c5adc8d 857 ath9k_hw_synth_delay(ah, ah->curchan, synthDelay);
af914a9f
LR		 858
859 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
8525f280
LR		 860}
861
c16fcb49
FF		 862static bool ar9003_hw_ani_control(struct ath_hw *ah,
863 enum ath9k_ani_cmd cmd, int param)
864{
af914a9f 865 struct ath_common *common = ath9k_hw_common(ah);
e36b27af 866 struct ath9k_channel *chan = ah->curchan;
093115b7 867 struct ar5416AniState *aniState = &chan->ani;
e36b27af 868 s32 value, value2;
af914a9f
LR		 869
870 switch (cmd & ah->ani_function) {
af914a9f 871 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
e36b27af
LR		 872 /*
873 * on == 1 means ofdm weak signal detection is ON
874 * on == 1 is the default, for less noise immunity
875 *
876 * on == 0 means ofdm weak signal detection is OFF
877 * on == 0 means more noise imm
878 */
af914a9f 879 u32 on = param ? 1 : 0;
af914a9f
LR		 880
881 if (on)
882 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
883 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
884 else
885 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
886 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
887
7067e701 888 if (on != aniState->ofdmWeakSigDetect) {
d2182b69 889 ath_dbg(common, ANI,
226afe68
JP		 890 "** ch %d: ofdm weak signal: %s=>%s\n",
891 chan->channel,
7067e701 892 aniState->ofdmWeakSigDetect ?
226afe68
JP		 893 "on" : "off",
894 on ? "on" : "off");
af914a9f
LR		 895 if (on)
896 ah->stats.ast_ani_ofdmon++;
897 else
898 ah->stats.ast_ani_ofdmoff++;
7067e701 899 aniState->ofdmWeakSigDetect = on;
af914a9f
LR		 900 }
901 break;
902 }
af914a9f 903 case ATH9K_ANI_FIRSTEP_LEVEL:{
af914a9f
LR		 904 u32 level = param;
905
e36b27af 906 if (level >= ARRAY_SIZE(firstep_table)) {
d2182b69 907 ath_dbg(common, ANI,
226afe68
JP		 908 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",
909 level, ARRAY_SIZE(firstep_table));
af914a9f
LR		 910 return false;
911 }
e36b27af
LR		 912
913 /*
914 * make register setting relative to default
915 * from INI file & cap value
916 */
917 value = firstep_table[level] -
465dce62 918 firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
e36b27af
LR		 919 aniState->iniDef.firstep;
920 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
921 value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
922 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
923 value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
af914a9f
LR		 924 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
925 AR_PHY_FIND_SIG_FIRSTEP,
e36b27af
LR		 926 value);
927 /*
928 * we need to set first step low register too
929 * make register setting relative to default
930 * from INI file & cap value
931 */
932 value2 = firstep_table[level] -
465dce62 933 firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
e36b27af
LR		 934 aniState->iniDef.firstepLow;
935 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
936 value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
937 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
938 value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
939
940 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
941 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2);
942
943 if (level != aniState->firstepLevel) {
d2182b69 944 ath_dbg(common, ANI,
226afe68
JP		 945 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
946 chan->channel,
947 aniState->firstepLevel,
948 level,
465dce62 949 ATH9K_ANI_FIRSTEP_LVL,
226afe68
JP		 950 value,
951 aniState->iniDef.firstep);
d2182b69 952 ath_dbg(common, ANI,
226afe68
JP		 953 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
954 chan->channel,
955 aniState->firstepLevel,
956 level,
465dce62 957 ATH9K_ANI_FIRSTEP_LVL,
226afe68
JP		 958 value2,
959 aniState->iniDef.firstepLow);
e36b27af
LR		 960 if (level > aniState->firstepLevel)
961 ah->stats.ast_ani_stepup++;
962 else if (level < aniState->firstepLevel)
963 ah->stats.ast_ani_stepdown++;
964 aniState->firstepLevel = level;
965 }
af914a9f
LR		 966 break;
967 }
968 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
af914a9f
LR		 969 u32 level = param;
970
e36b27af 971 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
d2182b69 972 ath_dbg(common, ANI,
226afe68
JP		 973 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",
974 level, ARRAY_SIZE(cycpwrThr1_table));
af914a9f
LR		 975 return false;
976 }
e36b27af
LR		 977 /*
978 * make register setting relative to default
979 * from INI file & cap value
980 */
981 value = cycpwrThr1_table[level] -
465dce62 982 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
e36b27af
LR		 983 aniState->iniDef.cycpwrThr1;
984 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
985 value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
986 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
987 value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
af914a9f
LR		 988 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
989 AR_PHY_TIMING5_CYCPWR_THR1,
e36b27af
LR		 990 value);
991
992 /*
993 * set AR_PHY_EXT_CCA for extension channel
994 * make register setting relative to default
995 * from INI file & cap value
996 */
997 value2 = cycpwrThr1_table[level] -
465dce62 998 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
e36b27af
LR		 999 aniState->iniDef.cycpwrThr1Ext;
1000 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1001 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1002 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1003 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1004 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
1005 AR_PHY_EXT_CYCPWR_THR1, value2);
1006
1007 if (level != aniState->spurImmunityLevel) {
d2182b69 1008 ath_dbg(common, ANI,
226afe68
JP		 1009 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
1010 chan->channel,
1011 aniState->spurImmunityLevel,
1012 level,
465dce62 1013 ATH9K_ANI_SPUR_IMMUNE_LVL,
226afe68
JP		 1014 value,
1015 aniState->iniDef.cycpwrThr1);
d2182b69 1016 ath_dbg(common, ANI,
226afe68
JP		 1017 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
1018 chan->channel,
1019 aniState->spurImmunityLevel,
1020 level,
465dce62 1021 ATH9K_ANI_SPUR_IMMUNE_LVL,
226afe68
JP		 1022 value2,
1023 aniState->iniDef.cycpwrThr1Ext);
e36b27af
LR		 1024 if (level > aniState->spurImmunityLevel)
1025 ah->stats.ast_ani_spurup++;
1026 else if (level < aniState->spurImmunityLevel)
1027 ah->stats.ast_ani_spurdown++;
1028 aniState->spurImmunityLevel = level;
1029 }
af914a9f
LR		 1030 break;
1031 }
e36b27af
LR		 1032 case ATH9K_ANI_MRC_CCK:{
1033 /*
1034 * is_on == 1 means MRC CCK ON (default, less noise imm)
1035 * is_on == 0 means MRC CCK is OFF (more noise imm)
1036 */
1037 bool is_on = param ? 1 : 0;
1038 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1039 AR_PHY_MRC_CCK_ENABLE, is_on);
1040 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1041 AR_PHY_MRC_CCK_MUX_REG, is_on);
81b67fd6 1042 if (is_on != aniState->mrcCCK) {
d2182b69 1043 ath_dbg(common, ANI, "** ch %d: MRC CCK: %s=>%s\n",
226afe68 1044 chan->channel,
81b67fd6 1045 aniState->mrcCCK ? "on" : "off",
226afe68 1046 is_on ? "on" : "off");
e36b27af
LR		 1047 if (is_on)
1048 ah->stats.ast_ani_ccklow++;
1049 else
1050 ah->stats.ast_ani_cckhigh++;
81b67fd6 1051 aniState->mrcCCK = is_on;
e36b27af
LR		 1052 }
1053 break;
1054 }
af914a9f
LR		 1055 case ATH9K_ANI_PRESENT:
1056 break;
1057 default:
d2182b69 1058 ath_dbg(common, ANI, "invalid cmd %u\n", cmd);
af914a9f
LR		 1059 return false;
1060 }
1061
d2182b69 1062 ath_dbg(common, ANI,
226afe68
JP		 1063 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1064 aniState->spurImmunityLevel,
7067e701 1065 aniState->ofdmWeakSigDetect ? "on" : "off",
226afe68 1066 aniState->firstepLevel,
81b67fd6 1067 aniState->mrcCCK ? "on" : "off",
226afe68
JP		 1068 aniState->listenTime,
1069 aniState->ofdmPhyErrCount,
1070 aniState->cckPhyErrCount);
af914a9f 1071 return true;
c16fcb49
FF		 1072}
1073
641d9921
FF		 1074static void ar9003_hw_do_getnf(struct ath_hw *ah,
1075 int16_t nfarray[NUM_NF_READINGS])
1076{
b06af7a5
VT		 1077#define AR_PHY_CH_MINCCA_PWR 0x1FF00000
1078#define AR_PHY_CH_MINCCA_PWR_S 20
1079#define AR_PHY_CH_EXT_MINCCA_PWR 0x01FF0000
1080#define AR_PHY_CH_EXT_MINCCA_PWR_S 16
641d9921 1081
b06af7a5
VT		 1082 int16_t nf;
1083 int i;
866b7780 1084
b06af7a5
VT		 1085 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1086 if (ah->rxchainmask & BIT(i)) {
1087 nf = MS(REG_READ(ah, ah->nf_regs[i]),
1088 AR_PHY_CH_MINCCA_PWR);
1089 nfarray[i] = sign_extend32(nf, 8);
641d9921 1090
b06af7a5
VT		 1091 if (IS_CHAN_HT40(ah->curchan)) {
1092 u8 ext_idx = AR9300_MAX_CHAINS + i;
641d9921 1093
b06af7a5
VT		 1094 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]),
1095 AR_PHY_CH_EXT_MINCCA_PWR);
1096 nfarray[ext_idx] = sign_extend32(nf, 8);
1097 }
1098 }
1099 }
641d9921
FF		 1100}
1101
f2552e28 1102static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
641d9921 1103{
f2552e28
FF		 1104 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
1105 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
ae245cde 1106 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ;
f2552e28
FF		 1107 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
1108 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
1109 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ;
ae245cde
SM		 1110
1111 if (AR_SREV_9330(ah))
1112 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ;
1113
1114 if (AR_SREV_9462(ah)) {
1115 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ;
1116 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9462_2GHZ;
1117 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ;
1118 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9462_5GHZ;
1119 }
641d9921
FF		 1120}
1121
e36b27af
LR		 1122/*
1123 * Initialize the ANI register values with default (ini) values.
1124 * This routine is called during a (full) hardware reset after
1125 * all the registers are initialised from the INI.
1126 */
1127static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
1128{
1129 struct ar5416AniState *aniState;
1130 struct ath_common *common = ath9k_hw_common(ah);
1131 struct ath9k_channel *chan = ah->curchan;
1132 struct ath9k_ani_default *iniDef;
e36b27af
LR		 1133 u32 val;
1134
093115b7 1135 aniState = &ah->curchan->ani;
e36b27af
LR		 1136 iniDef = &aniState->iniDef;
1137
d2182b69 1138 ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
226afe68
JP		 1139 ah->hw_version.macVersion,
1140 ah->hw_version.macRev,
1141 ah->opmode,
1142 chan->channel,
1143 chan->channelFlags);
e36b27af
LR		 1144
1145 val = REG_READ(ah, AR_PHY_SFCORR);
1146 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1147 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1148 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1149
1150 val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1151 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1152 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1153 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1154
1155 val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1156 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1157 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1158 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1159 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1160 iniDef->firstep = REG_READ_FIELD(ah,
1161 AR_PHY_FIND_SIG,
1162 AR_PHY_FIND_SIG_FIRSTEP);
1163 iniDef->firstepLow = REG_READ_FIELD(ah,
1164 AR_PHY_FIND_SIG_LOW,
1165 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW);
1166 iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1167 AR_PHY_TIMING5,
1168 AR_PHY_TIMING5_CYCPWR_THR1);
1169 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1170 AR_PHY_EXT_CCA,
1171 AR_PHY_EXT_CYCPWR_THR1);
1172
1173 /* these levels just got reset to defaults by the INI */
465dce62
FF		 1174 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
1175 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
7067e701 1176 aniState->ofdmWeakSigDetect = ATH9K_ANI_USE_OFDM_WEAK_SIG;
81b67fd6 1177 aniState->mrcCCK = true;
e36b27af
LR		 1178}
1179
4e8c14e9
FF		 1180static void ar9003_hw_set_radar_params(struct ath_hw *ah,
1181 struct ath_hw_radar_conf *conf)
1182{
1183 u32 radar_0 = 0, radar_1 = 0;
1184
1185 if (!conf) {
1186 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
1187 return;
1188 }
1189
1190 radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
1191 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1192 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
1193 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
1194 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
1195 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
1196
1197 radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
1198 radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
1199 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
1200 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
1201 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
1202
1203 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1204 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1205 if (conf->ext_channel)
1206 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1207 else
1208 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1209}
1210
c5d0855a
FF		 1211static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
1212{
1213 struct ath_hw_radar_conf *conf = &ah->radar_conf;
1214
1215 conf->fir_power = -28;
1216 conf->radar_rssi = 0;
1217 conf->pulse_height = 10;
1218 conf->pulse_rssi = 24;
1219 conf->pulse_inband = 8;
1220 conf->pulse_maxlen = 255;
1221 conf->pulse_inband_step = 12;
1222 conf->radar_inband = 8;
1223}
1224
6bcbc062
MSS		 1225static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah,
1226 struct ath_hw_antcomb_conf *antconf)
1227{
1228 u32 regval;
1229
1230 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1231 antconf->main_lna_conf = (regval & AR_PHY_9485_ANT_DIV_MAIN_LNACONF) >>
1232 AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S;
1233 antconf->alt_lna_conf = (regval & AR_PHY_9485_ANT_DIV_ALT_LNACONF) >>
1234 AR_PHY_9485_ANT_DIV_ALT_LNACONF_S;
1235 antconf->fast_div_bias = (regval & AR_PHY_9485_ANT_FAST_DIV_BIAS) >>
1236 AR_PHY_9485_ANT_FAST_DIV_BIAS_S;
cd0ed1b5 1237
c4cf2c58
GJ		 1238 if (AR_SREV_9330_11(ah)) {
1239 antconf->lna1_lna2_delta = -9;
1240 antconf->div_group = 1;
1241 } else if (AR_SREV_9485(ah)) {
cd0ed1b5
GJ		 1242 antconf->lna1_lna2_delta = -9;
1243 antconf->div_group = 2;
1244 } else {
1245 antconf->lna1_lna2_delta = -3;
1246 antconf->div_group = 0;
1247 }
6bcbc062
MSS		 1248}
1249
1250static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah,
1251 struct ath_hw_antcomb_conf *antconf)
1252{
1253 u32 regval;
1254
1255 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1256 regval &= ~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF |
1257 AR_PHY_9485_ANT_DIV_ALT_LNACONF |
1258 AR_PHY_9485_ANT_FAST_DIV_BIAS |
1259 AR_PHY_9485_ANT_DIV_MAIN_GAINTB |
1260 AR_PHY_9485_ANT_DIV_ALT_GAINTB);
1261 regval |= ((antconf->main_lna_conf <<
1262 AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S)
1263 & AR_PHY_9485_ANT_DIV_MAIN_LNACONF);
1264 regval |= ((antconf->alt_lna_conf << AR_PHY_9485_ANT_DIV_ALT_LNACONF_S)
1265 & AR_PHY_9485_ANT_DIV_ALT_LNACONF);
1266 regval |= ((antconf->fast_div_bias << AR_PHY_9485_ANT_FAST_DIV_BIAS_S)
1267 & AR_PHY_9485_ANT_FAST_DIV_BIAS);
1268 regval |= ((antconf->main_gaintb << AR_PHY_9485_ANT_DIV_MAIN_GAINTB_S)
1269 & AR_PHY_9485_ANT_DIV_MAIN_GAINTB);
1270 regval |= ((antconf->alt_gaintb << AR_PHY_9485_ANT_DIV_ALT_GAINTB_S)
1271 & AR_PHY_9485_ANT_DIV_ALT_GAINTB);
1272
1273 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1274}
1275
5f0c04ea
RM		 1276static int ar9003_hw_fast_chan_change(struct ath_hw *ah,
1277 struct ath9k_channel *chan,
1278 u8 *ini_reloaded)
1279{
1280 unsigned int regWrites = 0;
1281 u32 modesIndex;
1282
1283 switch (chan->chanmode) {
1284 case CHANNEL_A:
1285 case CHANNEL_A_HT20:
1286 modesIndex = 1;
1287 break;
1288 case CHANNEL_A_HT40PLUS:
1289 case CHANNEL_A_HT40MINUS:
1290 modesIndex = 2;
1291 break;
1292 case CHANNEL_G:
1293 case CHANNEL_G_HT20:
1294 case CHANNEL_B:
1295 modesIndex = 4;
1296 break;
1297 case CHANNEL_G_HT40PLUS:
1298 case CHANNEL_G_HT40MINUS:
1299 modesIndex = 3;
1300 break;
1301
1302 default:
1303 return -EINVAL;
1304 }
1305
1306 if (modesIndex == ah->modes_index) {
1307 *ini_reloaded = false;
1308 goto set_rfmode;
1309 }
1310
1311 ar9003_hw_prog_ini(ah, &ah->iniSOC[ATH_INI_POST], modesIndex);
1312 ar9003_hw_prog_ini(ah, &ah->iniMac[ATH_INI_POST], modesIndex);
1313 ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex);
1314 ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex);
aaa53ee9 1315
423e38e8 1316 if (AR_SREV_9462_20(ah))
aaa53ee9
SM		 1317 ar9003_hw_prog_ini(ah, &ah->ini_radio_post_sys2ant,
1318 modesIndex);
5f0c04ea
RM		 1319
1320 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1321
1322 /*
1323 * For 5GHz channels requiring Fast Clock, apply
1324 * different modal values.
1325 */
1326 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
c7d36f9f 1327 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, regWrites);
5f0c04ea 1328
aaa53ee9
SM		 1329 if (AR_SREV_9565(ah))
1330 REG_WRITE_ARRAY(&ah->iniModesFastClock, 1, regWrites);
1331
c7d36f9f 1332 REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites);
5f0c04ea
RM		 1333
1334 ah->modes_index = modesIndex;
1335 *ini_reloaded = true;
1336
1337set_rfmode:
1338 ar9003_hw_set_rfmode(ah, chan);
1339 return 0;
1340}
1341
8525f280
LR		 1342void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
1343{
1344 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
6bcbc062 1345 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
07b2fa5a 1346 static const u32 ar9300_cca_regs[6] = {
bbacee13
FF		 1347 AR_PHY_CCA_0,
1348 AR_PHY_CCA_1,
1349 AR_PHY_CCA_2,
1350 AR_PHY_EXT_CCA,
1351 AR_PHY_EXT_CCA_1,
1352 AR_PHY_EXT_CCA_2,
1353 };
8525f280
LR		 1354
1355 priv_ops->rf_set_freq = ar9003_hw_set_channel;
1356 priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
1357 priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
1358 priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
1359 priv_ops->init_bb = ar9003_hw_init_bb;
1360 priv_ops->process_ini = ar9003_hw_process_ini;
1361 priv_ops->set_rfmode = ar9003_hw_set_rfmode;
1362 priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive;
1363 priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
1364 priv_ops->rfbus_req = ar9003_hw_rfbus_req;
1365 priv_ops->rfbus_done = ar9003_hw_rfbus_done;
c16fcb49 1366 priv_ops->ani_control = ar9003_hw_ani_control;
641d9921 1367 priv_ops->do_getnf = ar9003_hw_do_getnf;
e36b27af 1368 priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
4e8c14e9 1369 priv_ops->set_radar_params = ar9003_hw_set_radar_params;
5f0c04ea 1370 priv_ops->fast_chan_change = ar9003_hw_fast_chan_change;
f2552e28 1371
6bcbc062
MSS		 1372 ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get;
1373 ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set;
1374
f2552e28 1375 ar9003_hw_set_nf_limits(ah);
c5d0855a 1376 ar9003_hw_set_radar_conf(ah);
bbacee13 1377 memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
8525f280 1378}
aea702b7
LR		 1379
1380void ar9003_hw_bb_watchdog_config(struct ath_hw *ah)
1381{
1382 struct ath_common *common = ath9k_hw_common(ah);
1383 u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms;
1384 u32 val, idle_count;
1385
1386 if (!idle_tmo_ms) {
1387 /* disable IRQ, disable chip-reset for BB panic */
1388 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1389 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) &
1390 ~(AR_PHY_WATCHDOG_RST_ENABLE |
1391 AR_PHY_WATCHDOG_IRQ_ENABLE));
1392
1393 /* disable watchdog in non-IDLE mode, disable in IDLE mode */
1394 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1395 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) &
1396 ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1397 AR_PHY_WATCHDOG_IDLE_ENABLE));
1398
d2182b69 1399 ath_dbg(common, RESET, "Disabled BB Watchdog\n");
aea702b7
LR		 1400 return;
1401 }
1402
1403 /* enable IRQ, disable chip-reset for BB watchdog */
1404 val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK;
1405 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1406 (val | AR_PHY_WATCHDOG_IRQ_ENABLE) &
1407 ~AR_PHY_WATCHDOG_RST_ENABLE);
1408
1409 /* bound limit to 10 secs */
1410 if (idle_tmo_ms > 10000)
1411 idle_tmo_ms = 10000;
1412
1413 /*
1414 * The time unit for watchdog event is 2^15 44/88MHz cycles.
1415 *
1416 * For HT20 we have a time unit of 2^15/44 MHz = .74 ms per tick
1417 * For HT40 we have a time unit of 2^15/88 MHz = .37 ms per tick
1418 *
1419 * Given we use fast clock now in 5 GHz, these time units should
1420 * be common for both 2 GHz and 5 GHz.
1421 */
1422 idle_count = (100 * idle_tmo_ms) / 74;
1423 if (ah->curchan && IS_CHAN_HT40(ah->curchan))
1424 idle_count = (100 * idle_tmo_ms) / 37;
1425
1426 /*
1427 * enable watchdog in non-IDLE mode, disable in IDLE mode,
1428 * set idle time-out.
1429 */
1430 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1431 AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1432 AR_PHY_WATCHDOG_IDLE_MASK |
1433 (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2)));
1434
d2182b69 1435 ath_dbg(common, RESET, "Enabled BB Watchdog timeout (%u ms)\n",
226afe68 1436 idle_tmo_ms);
aea702b7
LR		 1437}
1438
1439void ar9003_hw_bb_watchdog_read(struct ath_hw *ah)
1440{
1441 /*
1442 * we want to avoid printing in ISR context so we save the
1443 * watchdog status to be printed later in bottom half context.
1444 */
1445 ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS);
1446
1447 /*
1448 * the watchdog timer should reset on status read but to be sure
1449 * sure we write 0 to the watchdog status bit.
1450 */
1451 REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS,
1452 ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR);
1453}
1454
1455void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah)
1456{
1457 struct ath_common *common = ath9k_hw_common(ah);
9dbebc7f 1458 u32 status;
aea702b7
LR		 1459
1460 if (likely(!(common->debug_mask & ATH_DBG_RESET)))
1461 return;
1462
1463 status = ah->bb_watchdog_last_status;
d2182b69 1464 ath_dbg(common, RESET,
226afe68 1465 "\n==== BB update: BB status=0x%08x ====\n", status);
d2182b69 1466 ath_dbg(common, RESET,
226afe68
JP		 1467 "** BB state: wd=%u det=%u rdar=%u rOFDM=%d rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
1468 MS(status, AR_PHY_WATCHDOG_INFO),
1469 MS(status, AR_PHY_WATCHDOG_DET_HANG),
1470 MS(status, AR_PHY_WATCHDOG_RADAR_SM),
1471 MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM),
1472 MS(status, AR_PHY_WATCHDOG_RX_CCK_SM),
1473 MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM),
1474 MS(status, AR_PHY_WATCHDOG_TX_CCK_SM),
1475 MS(status, AR_PHY_WATCHDOG_AGC_SM),
1476 MS(status, AR_PHY_WATCHDOG_SRCH_SM));
1477
d2182b69 1478 ath_dbg(common, RESET, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
226afe68
JP		 1479 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1),
1480 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2));
d2182b69 1481 ath_dbg(common, RESET, "** BB mode: BB_gen_controls=0x%08x **\n",
226afe68 1482 REG_READ(ah, AR_PHY_GEN_CTRL));
aea702b7 1483
b5bfc568
FF		 1484#define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles)
1485 if (common->cc_survey.cycles)
d2182b69 1486 ath_dbg(common, RESET,
226afe68
JP		 1487 "** BB busy times: rx_clear=%d%%, rx_frame=%d%%, tx_frame=%d%% **\n",
1488 PCT(rx_busy), PCT(rx_frame), PCT(tx_frame));
aea702b7 1489
d2182b69 1490 ath_dbg(common, RESET, "==== BB update: done ====\n\n");
aea702b7
LR		 1491}
1492EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info);
51ac8cbb
RM		 1493
1494void ar9003_hw_disable_phy_restart(struct ath_hw *ah)
1495{
1496 u32 val;
1497
1498 /* While receiving unsupported rate frame rx state machine
1499 * gets into a state 0xb and if phy_restart happens in that
1500 * state, BB would go hang. If RXSM is in 0xb state after
1501 * first bb panic, ensure to disable the phy_restart.
1502 */
1503 if (!((MS(ah->bb_watchdog_last_status,
1504 AR_PHY_WATCHDOG_RX_OFDM_SM) == 0xb) ||
1505 ah->bb_hang_rx_ofdm))
1506 return;
1507
1508 ah->bb_hang_rx_ofdm = true;
1509 val = REG_READ(ah, AR_PHY_RESTART);
1510 val &= ~AR_PHY_RESTART_ENA;
1511
1512 REG_WRITE(ah, AR_PHY_RESTART, val);
1513}
1514EXPORT_SYMBOL(ar9003_hw_disable_phy_restart);
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