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ath9k_hw: sync initvals for ar9001 and ar9002 with Atheros
[mirror_ubuntu-hirsute-kernel.git] / drivers / net / wireless / ath / ath9k / ar9003_phy.c
CommitLineData
8525f280
LR		 1/*
2 * Copyright (c) 2010 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include "hw.h"
da6f1d7f 18#include "ar9003_phy.h"
8525f280 19
e36b27af
LR		 20static const int firstep_table[] =
21/* level: 0 1 2 3 4 5 6 7 8 */
22 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */
23
24static const int cycpwrThr1_table[] =
25/* level: 0 1 2 3 4 5 6 7 8 */
26 { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */
27
28/*
29 * register values to turn OFDM weak signal detection OFF
30 */
31static const int m1ThreshLow_off = 127;
32static const int m2ThreshLow_off = 127;
33static const int m1Thresh_off = 127;
34static const int m2Thresh_off = 127;
35static const int m2CountThr_off = 31;
36static const int m2CountThrLow_off = 63;
37static const int m1ThreshLowExt_off = 127;
38static const int m2ThreshLowExt_off = 127;
39static const int m1ThreshExt_off = 127;
40static const int m2ThreshExt_off = 127;
41
8525f280
LR		 42/**
43 * ar9003_hw_set_channel - set channel on single-chip device
44 * @ah: atheros hardware structure
45 * @chan:
46 *
47 * This is the function to change channel on single-chip devices, that is
48 * all devices after ar9280.
49 *
50 * This function takes the channel value in MHz and sets
51 * hardware channel value. Assumes writes have been enabled to analog bus.
52 *
53 * Actual Expression,
54 *
55 * For 2GHz channel,
56 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
57 * (freq_ref = 40MHz)
58 *
59 * For 5GHz channel,
60 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
61 * (freq_ref = 40MHz/(24>>amodeRefSel))
62 *
63 * For 5GHz channels which are 5MHz spaced,
64 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
65 * (freq_ref = 40MHz)
66 */
67static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
68{
f7abf0c1
FF		 69 u16 bMode, fracMode = 0, aModeRefSel = 0;
70 u32 freq, channelSel = 0, reg32 = 0;
71 struct chan_centers centers;
72 int loadSynthChannel;
73
74 ath9k_hw_get_channel_centers(ah, chan, &centers);
75 freq = centers.synth_center;
76
77 if (freq < 4800) { /* 2 GHz, fractional mode */
78 channelSel = CHANSEL_2G(freq);
79 /* Set to 2G mode */
80 bMode = 1;
81 } else {
82 channelSel = CHANSEL_5G(freq);
83 /* Doubler is ON, so, divide channelSel by 2. */
84 channelSel >>= 1;
85 /* Set to 5G mode */
86 bMode = 0;
87 }
88
89 /* Enable fractional mode for all channels */
90 fracMode = 1;
91 aModeRefSel = 0;
92 loadSynthChannel = 0;
93
94 reg32 = (bMode << 29);
95 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
96
97 /* Enable Long shift Select for Synthesizer */
98 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4,
99 AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1);
100
101 /* Program Synth. setting */
102 reg32 = (channelSel << 2) | (fracMode << 30) |
103 (aModeRefSel << 28) | (loadSynthChannel << 31);
104 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
105
106 /* Toggle Load Synth channel bit */
107 loadSynthChannel = 1;
108 reg32 = (channelSel << 2) | (fracMode << 30) |
109 (aModeRefSel << 28) | (loadSynthChannel << 31);
110 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
111
112 ah->curchan = chan;
113 ah->curchan_rad_index = -1;
114
8525f280
LR		 115 return 0;
116}
117
118/**
e36b27af 119 * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency
8525f280
LR		 120 * @ah: atheros hardware structure
121 * @chan:
122 *
123 * For single-chip solutions. Converts to baseband spur frequency given the
124 * input channel frequency and compute register settings below.
125 *
126 * Spur mitigation for MRC CCK
127 */
1547da37
LR		 128static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
129 struct ath9k_channel *chan)
8525f280 130{
ca375554
FF		 131 u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
132 int cur_bb_spur, negative = 0, cck_spur_freq;
133 int i;
134
135 /*
136 * Need to verify range +/- 10 MHz in control channel, otherwise spur
137 * is out-of-band and can be ignored.
138 */
139
140 for (i = 0; i < 4; i++) {
141 negative = 0;
142 cur_bb_spur = spur_freq[i] - chan->channel;
143
144 if (cur_bb_spur < 0) {
145 negative = 1;
146 cur_bb_spur = -cur_bb_spur;
147 }
148 if (cur_bb_spur < 10) {
149 cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
150
151 if (negative == 1)
152 cck_spur_freq = -cck_spur_freq;
153
154 cck_spur_freq = cck_spur_freq & 0xfffff;
155
156 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
157 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
158 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
159 AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
160 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
161 AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE,
162 0x2);
163 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
164 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT,
165 0x1);
166 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
167 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ,
168 cck_spur_freq);
169
170 return;
171 }
172 }
173
174 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
175 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
176 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
177 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0);
178 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
179 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
8525f280
LR		 180}
181
1547da37
LR		 182/* Clean all spur register fields */
183static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah)
184{
185 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
186 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0);
187 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
188 AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
189 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
190 AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
191 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
192 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0);
193 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
194 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0);
195 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
196 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0);
197 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
198 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0);
199 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
200 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0);
201 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
202 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0);
203
204 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
205 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0);
206 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
207 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0);
208 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
209 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0);
210 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
211 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0);
212 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
213 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0);
214 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
215 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0);
216 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
217 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0);
218 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
219 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0);
220 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
221 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0);
222 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
223 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
224}
225
226static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
227 int freq_offset,
228 int spur_freq_sd,
229 int spur_delta_phase,
230 int spur_subchannel_sd)
231{
232 int mask_index = 0;
233
234 /* OFDM Spur mitigation */
235 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
236 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1);
237 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
238 AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
239 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
240 AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
241 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
242 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd);
243 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
244 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1);
245 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
246 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1);
247 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
248 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1);
249 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
250 AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
251 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
252 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);
253
254 if (REG_READ_FIELD(ah, AR_PHY_MODE,
255 AR_PHY_MODE_DYNAMIC) == 0x1)
256 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
257 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);
258
259 mask_index = (freq_offset << 4) / 5;
260 if (mask_index < 0)
261 mask_index = mask_index - 1;
262
263 mask_index = mask_index & 0x7f;
264
265 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
266 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1);
267 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
268 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1);
269 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
270 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1);
271 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
272 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index);
273 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
274 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index);
275 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
276 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index);
277 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
278 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc);
279 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
280 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc);
281 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
282 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
283 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
284 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
285}
286
287static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
288 struct ath9k_channel *chan,
289 int freq_offset)
290{
291 int spur_freq_sd = 0;
292 int spur_subchannel_sd = 0;
293 int spur_delta_phase = 0;
294
295 if (IS_CHAN_HT40(chan)) {
296 if (freq_offset < 0) {
297 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
298 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
299 spur_subchannel_sd = 1;
300 else
301 spur_subchannel_sd = 0;
302
303 spur_freq_sd = ((freq_offset + 10) << 9) / 11;
304
305 } else {
306 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
307 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
308 spur_subchannel_sd = 0;
309 else
310 spur_subchannel_sd = 1;
311
312 spur_freq_sd = ((freq_offset - 10) << 9) / 11;
313
314 }
315
316 spur_delta_phase = (freq_offset << 17) / 5;
317
318 } else {
319 spur_subchannel_sd = 0;
320 spur_freq_sd = (freq_offset << 9) /11;
321 spur_delta_phase = (freq_offset << 18) / 5;
322 }
323
324 spur_freq_sd = spur_freq_sd & 0x3ff;
325 spur_delta_phase = spur_delta_phase & 0xfffff;
326
327 ar9003_hw_spur_ofdm(ah,
328 freq_offset,
329 spur_freq_sd,
330 spur_delta_phase,
331 spur_subchannel_sd);
332}
333
334/* Spur mitigation for OFDM */
335static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
336 struct ath9k_channel *chan)
337{
338 int synth_freq;
339 int range = 10;
340 int freq_offset = 0;
341 int mode;
342 u8* spurChansPtr;
343 unsigned int i;
344 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
345
346 if (IS_CHAN_5GHZ(chan)) {
347 spurChansPtr = &(eep->modalHeader5G.spurChans[0]);
348 mode = 0;
349 }
350 else {
351 spurChansPtr = &(eep->modalHeader2G.spurChans[0]);
352 mode = 1;
353 }
354
355 if (spurChansPtr[0] == 0)
356 return; /* No spur in the mode */
357
358 if (IS_CHAN_HT40(chan)) {
359 range = 19;
360 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
361 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
362 synth_freq = chan->channel - 10;
363 else
364 synth_freq = chan->channel + 10;
365 } else {
366 range = 10;
367 synth_freq = chan->channel;
368 }
369
370 ar9003_hw_spur_ofdm_clear(ah);
371
372 for (i = 0; spurChansPtr[i] && i < 5; i++) {
373 freq_offset = FBIN2FREQ(spurChansPtr[i], mode) - synth_freq;
374 if (abs(freq_offset) < range) {
375 ar9003_hw_spur_ofdm_work(ah, chan, freq_offset);
376 break;
377 }
378 }
379}
380
381static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
382 struct ath9k_channel *chan)
383{
384 ar9003_hw_spur_mitigate_mrc_cck(ah, chan);
385 ar9003_hw_spur_mitigate_ofdm(ah, chan);
386}
387
8525f280
LR		 388static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
389 struct ath9k_channel *chan)
390{
317d3328
FF		 391 u32 pll;
392
393 pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
394
395 if (chan && IS_CHAN_HALF_RATE(chan))
396 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
397 else if (chan && IS_CHAN_QUARTER_RATE(chan))
398 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
399
14bc1104 400 pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
317d3328
FF		 401
402 return pll;
8525f280
LR		 403}
404
405static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
406 struct ath9k_channel *chan)
407{
cffb5e49
LR		 408 u32 phymode;
409 u32 enableDacFifo = 0;
410
411 enableDacFifo =
412 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO);
413
414 /* Enable 11n HT, 20 MHz */
415 phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 | AR_PHY_GC_WALSH |
416 AR_PHY_GC_SHORT_GI_40 | enableDacFifo;
417
418 /* Configure baseband for dynamic 20/40 operation */
419 if (IS_CHAN_HT40(chan)) {
420 phymode |= AR_PHY_GC_DYN2040_EN;
421 /* Configure control (primary) channel at +-10MHz */
422 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
423 (chan->chanmode == CHANNEL_G_HT40PLUS))
424 phymode |= AR_PHY_GC_DYN2040_PRI_CH;
425
426 }
427
428 /* make sure we preserve INI settings */
429 phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);
430 /* turn off Green Field detection for STA for now */
431 phymode &= ~AR_PHY_GC_GF_DETECT_EN;
432
433 REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
434
435 /* Configure MAC for 20/40 operation */
436 ath9k_hw_set11nmac2040(ah);
437
438 /* global transmit timeout (25 TUs default)*/
439 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
440 /* carrier sense timeout */
441 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
8525f280
LR		 442}
443
444static void ar9003_hw_init_bb(struct ath_hw *ah,
445 struct ath9k_channel *chan)
446{
af914a9f
LR		 447 u32 synthDelay;
448
449 /*
450 * Wait for the frequency synth to settle (synth goes on
451 * via AR_PHY_ACTIVE_EN). Read the phy active delay register.
452 * Value is in 100ns increments.
453 */
454 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
455 if (IS_CHAN_B(chan))
456 synthDelay = (4 * synthDelay) / 22;
457 else
458 synthDelay /= 10;
459
460 /* Activate the PHY (includes baseband activate + synthesizer on) */
461 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
462
463 /*
464 * There is an issue if the AP starts the calibration before
465 * the base band timeout completes. This could result in the
466 * rx_clear false triggering. As a workaround we add delay an
467 * extra BASE_ACTIVATE_DELAY usecs to ensure this condition
468 * does not happen.
469 */
470 udelay(synthDelay + BASE_ACTIVATE_DELAY);
8525f280
LR		 471}
472
cffb5e49
LR		 473void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
474{
475 switch (rx) {
476 case 0x5:
477 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
478 AR_PHY_SWAP_ALT_CHAIN);
479 case 0x3:
480 case 0x1:
481 case 0x2:
482 case 0x7:
483 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
484 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
485 break;
486 default:
487 break;
488 }
489
490 REG_WRITE(ah, AR_SELFGEN_MASK, tx);
491 if (tx == 0x5) {
492 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
493 AR_PHY_SWAP_ALT_CHAIN);
494 }
495}
496
497/*
498 * Override INI values with chip specific configuration.
499 */
500static void ar9003_hw_override_ini(struct ath_hw *ah)
501{
502 u32 val;
503
504 /*
505 * Set the RX_ABORT and RX_DIS and clear it only after
506 * RXE is set for MAC. This prevents frames with
507 * corrupted descriptor status.
508 */
509 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
510
511 /*
512 * For AR9280 and above, there is a new feature that allows
513 * Multicast search based on both MAC Address and Key ID. By default,
514 * this feature is enabled. But since the driver is not using this
515 * feature, we switch it off; otherwise multicast search based on
516 * MAC addr only will fail.
517 */
518 val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
519 REG_WRITE(ah, AR_PCU_MISC_MODE2,
520 val | AR_AGG_WEP_ENABLE_FIX | AR_AGG_WEP_ENABLE);
521}
522
523static void ar9003_hw_prog_ini(struct ath_hw *ah,
524 struct ar5416IniArray *iniArr,
525 int column)
526{
527 unsigned int i, regWrites = 0;
528
529 /* New INI format: Array may be undefined (pre, core, post arrays) */
530 if (!iniArr->ia_array)
531 return;
532
533 /*
534 * New INI format: Pre, core, and post arrays for a given subsystem
535 * may be modal (> 2 columns) or non-modal (2 columns). Determine if
536 * the array is non-modal and force the column to 1.
537 */
538 if (column >= iniArr->ia_columns)
539 column = 1;
540
541 for (i = 0; i < iniArr->ia_rows; i++) {
542 u32 reg = INI_RA(iniArr, i, 0);
543 u32 val = INI_RA(iniArr, i, column);
544
545 REG_WRITE(ah, reg, val);
cffb5e49
LR		 546 DO_DELAY(regWrites);
547 }
548}
549
8525f280
LR		 550static int ar9003_hw_process_ini(struct ath_hw *ah,
551 struct ath9k_channel *chan)
552{
cffb5e49
LR		 553 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
554 unsigned int regWrites = 0, i;
555 struct ieee80211_channel *channel = chan->chan;
556 u32 modesIndex, freqIndex;
557
558 switch (chan->chanmode) {
559 case CHANNEL_A:
560 case CHANNEL_A_HT20:
561 modesIndex = 1;
562 freqIndex = 1;
563 break;
564 case CHANNEL_A_HT40PLUS:
565 case CHANNEL_A_HT40MINUS:
566 modesIndex = 2;
567 freqIndex = 1;
568 break;
569 case CHANNEL_G:
570 case CHANNEL_G_HT20:
571 case CHANNEL_B:
572 modesIndex = 4;
573 freqIndex = 2;
574 break;
575 case CHANNEL_G_HT40PLUS:
576 case CHANNEL_G_HT40MINUS:
577 modesIndex = 3;
578 freqIndex = 2;
579 break;
580
581 default:
582 return -EINVAL;
583 }
584
585 for (i = 0; i < ATH_INI_NUM_SPLIT; i++) {
586 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex);
587 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
588 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
589 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
590 }
591
592 REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
593 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
594
595 /*
596 * For 5GHz channels requiring Fast Clock, apply
597 * different modal values.
598 */
6b42e8d0 599 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
cffb5e49
LR		 600 REG_WRITE_ARRAY(&ah->iniModesAdditional,
601 modesIndex, regWrites);
602
603 ar9003_hw_override_ini(ah);
604 ar9003_hw_set_channel_regs(ah, chan);
605 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
606
607 /* Set TX power */
608 ah->eep_ops->set_txpower(ah, chan,
609 ath9k_regd_get_ctl(regulatory, chan),
610 channel->max_antenna_gain * 2,
611 channel->max_power * 2,
612 min((u32) MAX_RATE_POWER,
613 (u32) regulatory->power_limit));
614
615 return 0;
8525f280
LR		 616}
617
618static void ar9003_hw_set_rfmode(struct ath_hw *ah,
619 struct ath9k_channel *chan)
620{
af914a9f
LR		 621 u32 rfMode = 0;
622
623 if (chan == NULL)
624 return;
625
626 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
627 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
628
6b42e8d0 629 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
af914a9f
LR		 630 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
631
632 REG_WRITE(ah, AR_PHY_MODE, rfMode);
8525f280
LR		 633}
634
635static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
636{
af914a9f 637 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
8525f280
LR		 638}
639
640static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
641 struct ath9k_channel *chan)
642{
af914a9f
LR		 643 u32 coef_scaled, ds_coef_exp, ds_coef_man;
644 u32 clockMhzScaled = 0x64000000;
645 struct chan_centers centers;
646
647 /*
648 * half and quarter rate can divide the scaled clock by 2 or 4
649 * scale for selected channel bandwidth
650 */
651 if (IS_CHAN_HALF_RATE(chan))
652 clockMhzScaled = clockMhzScaled >> 1;
653 else if (IS_CHAN_QUARTER_RATE(chan))
654 clockMhzScaled = clockMhzScaled >> 2;
655
656 /*
657 * ALGO -> coef = 1e8/fcarrier*fclock/40;
658 * scaled coef to provide precision for this floating calculation
659 */
660 ath9k_hw_get_channel_centers(ah, chan, &centers);
661 coef_scaled = clockMhzScaled / centers.synth_center;
662
663 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
664 &ds_coef_exp);
665
666 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
667 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
668 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
669 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
670
671 /*
672 * For Short GI,
673 * scaled coeff is 9/10 that of normal coeff
674 */
675 coef_scaled = (9 * coef_scaled) / 10;
676
677 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
678 &ds_coef_exp);
679
680 /* for short gi */
681 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
682 AR_PHY_SGI_DSC_MAN, ds_coef_man);
683 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
684 AR_PHY_SGI_DSC_EXP, ds_coef_exp);
8525f280
LR		 685}
686
687static bool ar9003_hw_rfbus_req(struct ath_hw *ah)
688{
af914a9f
LR		 689 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
690 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
691 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
8525f280
LR		 692}
693
af914a9f
LR		 694/*
695 * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN).
696 * Read the phy active delay register. Value is in 100ns increments.
697 */
8525f280
LR		 698static void ar9003_hw_rfbus_done(struct ath_hw *ah)
699{
af914a9f
LR		 700 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
701 if (IS_CHAN_B(ah->curchan))
702 synthDelay = (4 * synthDelay) / 22;
703 else
704 synthDelay /= 10;
705
706 udelay(synthDelay + BASE_ACTIVATE_DELAY);
707
708 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
8525f280
LR		 709}
710
af914a9f
LR		 711/*
712 * Set the interrupt and GPIO values so the ISR can disable RF
713 * on a switch signal. Assumes GPIO port and interrupt polarity
714 * are set prior to call.
715 */
8525f280
LR		 716static void ar9003_hw_enable_rfkill(struct ath_hw *ah)
717{
af914a9f
LR		 718 /* Connect rfsilent_bb_l to baseband */
719 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
720 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
721 /* Set input mux for rfsilent_bb_l to GPIO #0 */
722 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
723 AR_GPIO_INPUT_MUX2_RFSILENT);
724
725 /*
726 * Configure the desired GPIO port for input and
727 * enable baseband rf silence.
728 */
729 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
730 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
8525f280
LR		 731}
732
733static void ar9003_hw_set_diversity(struct ath_hw *ah, bool value)
734{
af914a9f
LR		 735 u32 v = REG_READ(ah, AR_PHY_CCK_DETECT);
736 if (value)
737 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
738 else
739 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
740 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
8525f280
LR		 741}
742
c16fcb49
FF		 743static bool ar9003_hw_ani_control(struct ath_hw *ah,
744 enum ath9k_ani_cmd cmd, int param)
745{
af914a9f
LR		 746 struct ar5416AniState *aniState = ah->curani;
747 struct ath_common *common = ath9k_hw_common(ah);
e36b27af
LR		 748 struct ath9k_channel *chan = ah->curchan;
749 s32 value, value2;
af914a9f
LR		 750
751 switch (cmd & ah->ani_function) {
af914a9f 752 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
e36b27af
LR		 753 /*
754 * on == 1 means ofdm weak signal detection is ON
755 * on == 1 is the default, for less noise immunity
756 *
757 * on == 0 means ofdm weak signal detection is OFF
758 * on == 0 means more noise imm
759 */
af914a9f 760 u32 on = param ? 1 : 0;
e36b27af
LR		 761 /*
762 * make register setting for default
763 * (weak sig detect ON) come from INI file
764 */
765 int m1ThreshLow = on ?
766 aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
767 int m2ThreshLow = on ?
768 aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
769 int m1Thresh = on ?
770 aniState->iniDef.m1Thresh : m1Thresh_off;
771 int m2Thresh = on ?
772 aniState->iniDef.m2Thresh : m2Thresh_off;
773 int m2CountThr = on ?
774 aniState->iniDef.m2CountThr : m2CountThr_off;
775 int m2CountThrLow = on ?
776 aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
777 int m1ThreshLowExt = on ?
778 aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
779 int m2ThreshLowExt = on ?
780 aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
781 int m1ThreshExt = on ?
782 aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
783 int m2ThreshExt = on ?
784 aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
af914a9f
LR		 785
786 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
787 AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
e36b27af 788 m1ThreshLow);
af914a9f
LR		 789 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
790 AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
e36b27af 791 m2ThreshLow);
af914a9f 792 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
e36b27af 793 AR_PHY_SFCORR_M1_THRESH, m1Thresh);
af914a9f 794 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
e36b27af 795 AR_PHY_SFCORR_M2_THRESH, m2Thresh);
af914a9f 796 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
e36b27af 797 AR_PHY_SFCORR_M2COUNT_THR, m2CountThr);
af914a9f
LR		 798 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
799 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
e36b27af 800 m2CountThrLow);
af914a9f
LR		 801
802 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
e36b27af 803 AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLowExt);
af914a9f 804 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
e36b27af 805 AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLowExt);
af914a9f 806 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
e36b27af 807 AR_PHY_SFCORR_EXT_M1_THRESH, m1ThreshExt);
af914a9f 808 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
e36b27af 809 AR_PHY_SFCORR_EXT_M2_THRESH, m2ThreshExt);
af914a9f
LR		 810
811 if (on)
812 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
813 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
814 else
815 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
816 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
817
818 if (!on != aniState->ofdmWeakSigDetectOff) {
e36b27af
LR		 819 ath_print(common, ATH_DBG_ANI,
820 "** ch %d: ofdm weak signal: %s=>%s\n",
821 chan->channel,
822 !aniState->ofdmWeakSigDetectOff ?
823 "on" : "off",
824 on ? "on" : "off");
af914a9f
LR		 825 if (on)
826 ah->stats.ast_ani_ofdmon++;
827 else
828 ah->stats.ast_ani_ofdmoff++;
829 aniState->ofdmWeakSigDetectOff = !on;
830 }
831 break;
832 }
af914a9f 833 case ATH9K_ANI_FIRSTEP_LEVEL:{
af914a9f
LR		 834 u32 level = param;
835
e36b27af 836 if (level >= ARRAY_SIZE(firstep_table)) {
af914a9f 837 ath_print(common, ATH_DBG_ANI,
e36b27af
LR		 838 "ATH9K_ANI_FIRSTEP_LEVEL: level "
839 "out of range (%u > %u)\n",
af914a9f 840 level,
e36b27af 841 (unsigned) ARRAY_SIZE(firstep_table));
af914a9f
LR		 842 return false;
843 }
e36b27af
LR		 844
845 /*
846 * make register setting relative to default
847 * from INI file & cap value
848 */
849 value = firstep_table[level] -
850 firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
851 aniState->iniDef.firstep;
852 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
853 value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
854 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
855 value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
af914a9f
LR		 856 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
857 AR_PHY_FIND_SIG_FIRSTEP,
e36b27af
LR		 858 value);
859 /*
860 * we need to set first step low register too
861 * make register setting relative to default
862 * from INI file & cap value
863 */
864 value2 = firstep_table[level] -
865 firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
866 aniState->iniDef.firstepLow;
867 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
868 value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
869 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
870 value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
871
872 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
873 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2);
874
875 if (level != aniState->firstepLevel) {
876 ath_print(common, ATH_DBG_ANI,
877 "** ch %d: level %d=>%d[def:%d] "
878 "firstep[level]=%d ini=%d\n",
879 chan->channel,
880 aniState->firstepLevel,
881 level,
882 ATH9K_ANI_FIRSTEP_LVL_NEW,
883 value,
884 aniState->iniDef.firstep);
885 ath_print(common, ATH_DBG_ANI,
886 "** ch %d: level %d=>%d[def:%d] "
887 "firstep_low[level]=%d ini=%d\n",
888 chan->channel,
889 aniState->firstepLevel,
890 level,
891 ATH9K_ANI_FIRSTEP_LVL_NEW,
892 value2,
893 aniState->iniDef.firstepLow);
894 if (level > aniState->firstepLevel)
895 ah->stats.ast_ani_stepup++;
896 else if (level < aniState->firstepLevel)
897 ah->stats.ast_ani_stepdown++;
898 aniState->firstepLevel = level;
899 }
af914a9f
LR		 900 break;
901 }
902 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
af914a9f
LR		 903 u32 level = param;
904
e36b27af 905 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
af914a9f 906 ath_print(common, ATH_DBG_ANI,
e36b27af
LR		 907 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level "
908 "out of range (%u > %u)\n",
af914a9f 909 level,
e36b27af 910 (unsigned) ARRAY_SIZE(cycpwrThr1_table));
af914a9f
LR		 911 return false;
912 }
e36b27af
LR		 913 /*
914 * make register setting relative to default
915 * from INI file & cap value
916 */
917 value = cycpwrThr1_table[level] -
918 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
919 aniState->iniDef.cycpwrThr1;
920 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
921 value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
922 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
923 value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
af914a9f
LR		 924 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
925 AR_PHY_TIMING5_CYCPWR_THR1,
e36b27af
LR		 926 value);
927
928 /*
929 * set AR_PHY_EXT_CCA for extension channel
930 * make register setting relative to default
931 * from INI file & cap value
932 */
933 value2 = cycpwrThr1_table[level] -
934 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
935 aniState->iniDef.cycpwrThr1Ext;
936 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
937 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
938 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
939 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
940 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
941 AR_PHY_EXT_CYCPWR_THR1, value2);
942
943 if (level != aniState->spurImmunityLevel) {
944 ath_print(common, ATH_DBG_ANI,
945 "** ch %d: level %d=>%d[def:%d] "
946 "cycpwrThr1[level]=%d ini=%d\n",
947 chan->channel,
948 aniState->spurImmunityLevel,
949 level,
950 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
951 value,
952 aniState->iniDef.cycpwrThr1);
953 ath_print(common, ATH_DBG_ANI,
954 "** ch %d: level %d=>%d[def:%d] "
955 "cycpwrThr1Ext[level]=%d ini=%d\n",
956 chan->channel,
957 aniState->spurImmunityLevel,
958 level,
959 ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
960 value2,
961 aniState->iniDef.cycpwrThr1Ext);
962 if (level > aniState->spurImmunityLevel)
963 ah->stats.ast_ani_spurup++;
964 else if (level < aniState->spurImmunityLevel)
965 ah->stats.ast_ani_spurdown++;
966 aniState->spurImmunityLevel = level;
967 }
af914a9f
LR		 968 break;
969 }
e36b27af
LR		 970 case ATH9K_ANI_MRC_CCK:{
971 /*
972 * is_on == 1 means MRC CCK ON (default, less noise imm)
973 * is_on == 0 means MRC CCK is OFF (more noise imm)
974 */
975 bool is_on = param ? 1 : 0;
976 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
977 AR_PHY_MRC_CCK_ENABLE, is_on);
978 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
979 AR_PHY_MRC_CCK_MUX_REG, is_on);
980 if (!is_on != aniState->mrcCCKOff) {
981 ath_print(common, ATH_DBG_ANI,
982 "** ch %d: MRC CCK: %s=>%s\n",
983 chan->channel,
984 !aniState->mrcCCKOff ? "on" : "off",
985 is_on ? "on" : "off");
986 if (is_on)
987 ah->stats.ast_ani_ccklow++;
988 else
989 ah->stats.ast_ani_cckhigh++;
990 aniState->mrcCCKOff = !is_on;
991 }
992 break;
993 }
af914a9f
LR		 994 case ATH9K_ANI_PRESENT:
995 break;
996 default:
997 ath_print(common, ATH_DBG_ANI,
998 "invalid cmd %u\n", cmd);
999 return false;
1000 }
1001
af914a9f 1002 ath_print(common, ATH_DBG_ANI,
e36b27af
LR		 1003 "ANI parameters: SI=%d, ofdmWS=%s FS=%d "
1004 "MRCcck=%s listenTime=%d CC=%d listen=%d "
1005 "ofdmErrs=%d cckErrs=%d\n",
af914a9f 1006 aniState->spurImmunityLevel,
e36b27af 1007 !aniState->ofdmWeakSigDetectOff ? "on" : "off",
af914a9f 1008 aniState->firstepLevel,
e36b27af
LR		 1009 !aniState->mrcCCKOff ? "on" : "off",
1010 aniState->listenTime,
1011 aniState->cycleCount,
1012 aniState->listenTime,
1013 aniState->ofdmPhyErrCount,
1014 aniState->cckPhyErrCount);
af914a9f 1015 return true;
c16fcb49
FF		 1016}
1017
641d9921
FF		 1018static void ar9003_hw_nf_sanitize_2g(struct ath_hw *ah, s16 *nf)
1019{
1020 struct ath_common *common = ath9k_hw_common(ah);
1021
1022 if (*nf > ah->nf_2g_max) {
1023 ath_print(common, ATH_DBG_CALIBRATE,
1024 "2 GHz NF (%d) > MAX (%d), "
1025 "correcting to MAX",
1026 *nf, ah->nf_2g_max);
1027 *nf = ah->nf_2g_max;
1028 } else if (*nf < ah->nf_2g_min) {
1029 ath_print(common, ATH_DBG_CALIBRATE,
1030 "2 GHz NF (%d) < MIN (%d), "
1031 "correcting to MIN",
1032 *nf, ah->nf_2g_min);
1033 *nf = ah->nf_2g_min;
1034 }
1035}
1036
1037static void ar9003_hw_nf_sanitize_5g(struct ath_hw *ah, s16 *nf)
1038{
1039 struct ath_common *common = ath9k_hw_common(ah);
1040
1041 if (*nf > ah->nf_5g_max) {
1042 ath_print(common, ATH_DBG_CALIBRATE,
1043 "5 GHz NF (%d) > MAX (%d), "
1044 "correcting to MAX",
1045 *nf, ah->nf_5g_max);
1046 *nf = ah->nf_5g_max;
1047 } else if (*nf < ah->nf_5g_min) {
1048 ath_print(common, ATH_DBG_CALIBRATE,
1049 "5 GHz NF (%d) < MIN (%d), "
1050 "correcting to MIN",
1051 *nf, ah->nf_5g_min);
1052 *nf = ah->nf_5g_min;
1053 }
1054}
1055
1056static void ar9003_hw_nf_sanitize(struct ath_hw *ah, s16 *nf)
1057{
1058 if (IS_CHAN_2GHZ(ah->curchan))
1059 ar9003_hw_nf_sanitize_2g(ah, nf);
1060 else
1061 ar9003_hw_nf_sanitize_5g(ah, nf);
1062}
1063
1064static void ar9003_hw_do_getnf(struct ath_hw *ah,
1065 int16_t nfarray[NUM_NF_READINGS])
1066{
1067 struct ath_common *common = ath9k_hw_common(ah);
1068 int16_t nf;
1069
1070 nf = MS(REG_READ(ah, AR_PHY_CCA_0), AR_PHY_MINCCA_PWR);
1071 if (nf & 0x100)
1072 nf = 0 - ((nf ^ 0x1ff) + 1);
1073 ar9003_hw_nf_sanitize(ah, &nf);
1074 ath_print(common, ATH_DBG_CALIBRATE,
1075 "NF calibrated [ctl] [chain 0] is %d\n", nf);
1076 nfarray[0] = nf;
1077
1078 nf = MS(REG_READ(ah, AR_PHY_CCA_1), AR_PHY_CH1_MINCCA_PWR);
1079 if (nf & 0x100)
1080 nf = 0 - ((nf ^ 0x1ff) + 1);
1081 ar9003_hw_nf_sanitize(ah, &nf);
1082 ath_print(common, ATH_DBG_CALIBRATE,
1083 "NF calibrated [ctl] [chain 1] is %d\n", nf);
1084 nfarray[1] = nf;
1085
1086 nf = MS(REG_READ(ah, AR_PHY_CCA_2), AR_PHY_CH2_MINCCA_PWR);
1087 if (nf & 0x100)
1088 nf = 0 - ((nf ^ 0x1ff) + 1);
1089 ar9003_hw_nf_sanitize(ah, &nf);
1090 ath_print(common, ATH_DBG_CALIBRATE,
1091 "NF calibrated [ctl] [chain 2] is %d\n", nf);
1092 nfarray[2] = nf;
1093
1094 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);
1095 if (nf & 0x100)
1096 nf = 0 - ((nf ^ 0x1ff) + 1);
1097 ar9003_hw_nf_sanitize(ah, &nf);
1098 ath_print(common, ATH_DBG_CALIBRATE,
1099 "NF calibrated [ext] [chain 0] is %d\n", nf);
1100 nfarray[3] = nf;
1101
1102 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA_1), AR_PHY_CH1_EXT_MINCCA_PWR);
1103 if (nf & 0x100)
1104 nf = 0 - ((nf ^ 0x1ff) + 1);
1105 ar9003_hw_nf_sanitize(ah, &nf);
1106 ath_print(common, ATH_DBG_CALIBRATE,
1107 "NF calibrated [ext] [chain 1] is %d\n", nf);
1108 nfarray[4] = nf;
1109
1110 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA_2), AR_PHY_CH2_EXT_MINCCA_PWR);
1111 if (nf & 0x100)
1112 nf = 0 - ((nf ^ 0x1ff) + 1);
1113 ar9003_hw_nf_sanitize(ah, &nf);
1114 ath_print(common, ATH_DBG_CALIBRATE,
1115 "NF calibrated [ext] [chain 2] is %d\n", nf);
1116 nfarray[5] = nf;
1117}
1118
1119void ar9003_hw_set_nf_limits(struct ath_hw *ah)
1120{
1121 ah->nf_2g_max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
1122 ah->nf_2g_min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
1123 ah->nf_5g_max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
1124 ah->nf_5g_min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
1125}
1126
df23acaa
LR		 1127/*
1128 * Find out which of the RX chains are enabled
1129 */
1130static u32 ar9003_hw_get_rx_chainmask(struct ath_hw *ah)
1131{
1132 u32 chain = REG_READ(ah, AR_PHY_RX_CHAINMASK);
1133 /*
1134 * The bits [2:0] indicate the rx chain mask and are to be
1135 * interpreted as follows:
1136 * 00x => Only chain 0 is enabled
1137 * 01x => Chain 1 and 0 enabled
1138 * 1xx => Chain 2,1 and 0 enabled
1139 */
1140 return chain & 0x7;
1141}
1142
1143static void ar9003_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
1144{
1145 struct ath9k_nfcal_hist *h;
1146 unsigned i, j;
1147 int32_t val;
1148 const u32 ar9300_cca_regs[6] = {
1149 AR_PHY_CCA_0,
1150 AR_PHY_CCA_1,
1151 AR_PHY_CCA_2,
1152 AR_PHY_EXT_CCA,
1153 AR_PHY_EXT_CCA_1,
1154 AR_PHY_EXT_CCA_2,
1155 };
1156 u8 chainmask, rx_chain_status;
1157 struct ath_common *common = ath9k_hw_common(ah);
1158
1159 rx_chain_status = ar9003_hw_get_rx_chainmask(ah);
1160
1161 chainmask = 0x3F;
1162 h = ah->nfCalHist;
1163
1164 for (i = 0; i < NUM_NF_READINGS; i++) {
1165 if (chainmask & (1 << i)) {
1166 val = REG_READ(ah, ar9300_cca_regs[i]);
1167 val &= 0xFFFFFE00;
1168 val |= (((u32) (h[i].privNF) << 1) & 0x1ff);
1169 REG_WRITE(ah, ar9300_cca_regs[i], val);
1170 }
1171 }
1172
1173 /*
1174 * Load software filtered NF value into baseband internal minCCApwr
1175 * variable.
1176 */
1177 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
1178 AR_PHY_AGC_CONTROL_ENABLE_NF);
1179 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
1180 AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
1181 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
1182
1183 /*
1184 * Wait for load to complete, should be fast, a few 10s of us.
1185 * The max delay was changed from an original 250us to 10000us
1186 * since 250us often results in NF load timeout and causes deaf
1187 * condition during stress testing 12/12/2009
1188 */
1189 for (j = 0; j < 1000; j++) {
1190 if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
1191 AR_PHY_AGC_CONTROL_NF) == 0)
1192 break;
1193 udelay(10);
1194 }
1195
1196 /*
1197 * We timed out waiting for the noisefloor to load, probably due to an
1198 * in-progress rx. Simply return here and allow the load plenty of time
1199 * to complete before the next calibration interval. We need to avoid
1200 * trying to load -50 (which happens below) while the previous load is
1201 * still in progress as this can cause rx deafness. Instead by returning
1202 * here, the baseband nf cal will just be capped by our present
1203 * noisefloor until the next calibration timer.
1204 */
1205 if (j == 1000) {
1206 ath_print(common, ATH_DBG_ANY, "Timeout while waiting for nf "
1207 "to load: AR_PHY_AGC_CONTROL=0x%x\n",
1208 REG_READ(ah, AR_PHY_AGC_CONTROL));
5d5d44d9 1209 return;
df23acaa
LR		 1210 }
1211
1212 /*
1213 * Restore maxCCAPower register parameter again so that we're not capped
1214 * by the median we just loaded. This will be initial (and max) value
1215 * of next noise floor calibration the baseband does.
1216 */
1217 for (i = 0; i < NUM_NF_READINGS; i++) {
1218 if (chainmask & (1 << i)) {
1219 val = REG_READ(ah, ar9300_cca_regs[i]);
1220 val &= 0xFFFFFE00;
1221 val |= (((u32) (-50) << 1) & 0x1ff);
1222 REG_WRITE(ah, ar9300_cca_regs[i], val);
1223 }
1224 }
1225}
1226
e36b27af
LR		 1227/*
1228 * Initialize the ANI register values with default (ini) values.
1229 * This routine is called during a (full) hardware reset after
1230 * all the registers are initialised from the INI.
1231 */
1232static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
1233{
1234 struct ar5416AniState *aniState;
1235 struct ath_common *common = ath9k_hw_common(ah);
1236 struct ath9k_channel *chan = ah->curchan;
1237 struct ath9k_ani_default *iniDef;
1238 int index;
1239 u32 val;
1240
1241 index = ath9k_hw_get_ani_channel_idx(ah, chan);
1242 aniState = &ah->ani[index];
1243 ah->curani = aniState;
1244 iniDef = &aniState->iniDef;
1245
1246 ath_print(common, ATH_DBG_ANI,
1247 "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
1248 ah->hw_version.macVersion,
1249 ah->hw_version.macRev,
1250 ah->opmode,
1251 chan->channel,
1252 chan->channelFlags);
1253
1254 val = REG_READ(ah, AR_PHY_SFCORR);
1255 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1256 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1257 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1258
1259 val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1260 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1261 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1262 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1263
1264 val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1265 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1266 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1267 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1268 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1269 iniDef->firstep = REG_READ_FIELD(ah,
1270 AR_PHY_FIND_SIG,
1271 AR_PHY_FIND_SIG_FIRSTEP);
1272 iniDef->firstepLow = REG_READ_FIELD(ah,
1273 AR_PHY_FIND_SIG_LOW,
1274 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW);
1275 iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1276 AR_PHY_TIMING5,
1277 AR_PHY_TIMING5_CYCPWR_THR1);
1278 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1279 AR_PHY_EXT_CCA,
1280 AR_PHY_EXT_CYCPWR_THR1);
1281
1282 /* these levels just got reset to defaults by the INI */
1283 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL_NEW;
1284 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW;
1285 aniState->ofdmWeakSigDetectOff = !ATH9K_ANI_USE_OFDM_WEAK_SIG;
1286 aniState->mrcCCKOff = !ATH9K_ANI_ENABLE_MRC_CCK;
1287
1288 aniState->cycleCount = 0;
1289}
1290
8525f280
LR		 1291void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
1292{
1293 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1294
1295 priv_ops->rf_set_freq = ar9003_hw_set_channel;
1296 priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
1297 priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
1298 priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
1299 priv_ops->init_bb = ar9003_hw_init_bb;
1300 priv_ops->process_ini = ar9003_hw_process_ini;
1301 priv_ops->set_rfmode = ar9003_hw_set_rfmode;
1302 priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive;
1303 priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
1304 priv_ops->rfbus_req = ar9003_hw_rfbus_req;
1305 priv_ops->rfbus_done = ar9003_hw_rfbus_done;
1306 priv_ops->enable_rfkill = ar9003_hw_enable_rfkill;
1307 priv_ops->set_diversity = ar9003_hw_set_diversity;
c16fcb49 1308 priv_ops->ani_control = ar9003_hw_ani_control;
641d9921 1309 priv_ops->do_getnf = ar9003_hw_do_getnf;
df23acaa 1310 priv_ops->loadnf = ar9003_hw_loadnf;
e36b27af 1311 priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
8525f280 1312}
aea702b7
LR		 1313
1314void ar9003_hw_bb_watchdog_config(struct ath_hw *ah)
1315{
1316 struct ath_common *common = ath9k_hw_common(ah);
1317 u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms;
1318 u32 val, idle_count;
1319
1320 if (!idle_tmo_ms) {
1321 /* disable IRQ, disable chip-reset for BB panic */
1322 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1323 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) &
1324 ~(AR_PHY_WATCHDOG_RST_ENABLE |
1325 AR_PHY_WATCHDOG_IRQ_ENABLE));
1326
1327 /* disable watchdog in non-IDLE mode, disable in IDLE mode */
1328 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1329 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) &
1330 ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1331 AR_PHY_WATCHDOG_IDLE_ENABLE));
1332
1333 ath_print(common, ATH_DBG_RESET, "Disabled BB Watchdog\n");
1334 return;
1335 }
1336
1337 /* enable IRQ, disable chip-reset for BB watchdog */
1338 val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK;
1339 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
1340 (val | AR_PHY_WATCHDOG_IRQ_ENABLE) &
1341 ~AR_PHY_WATCHDOG_RST_ENABLE);
1342
1343 /* bound limit to 10 secs */
1344 if (idle_tmo_ms > 10000)
1345 idle_tmo_ms = 10000;
1346
1347 /*
1348 * The time unit for watchdog event is 2^15 44/88MHz cycles.
1349 *
1350 * For HT20 we have a time unit of 2^15/44 MHz = .74 ms per tick
1351 * For HT40 we have a time unit of 2^15/88 MHz = .37 ms per tick
1352 *
1353 * Given we use fast clock now in 5 GHz, these time units should
1354 * be common for both 2 GHz and 5 GHz.
1355 */
1356 idle_count = (100 * idle_tmo_ms) / 74;
1357 if (ah->curchan && IS_CHAN_HT40(ah->curchan))
1358 idle_count = (100 * idle_tmo_ms) / 37;
1359
1360 /*
1361 * enable watchdog in non-IDLE mode, disable in IDLE mode,
1362 * set idle time-out.
1363 */
1364 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
1365 AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
1366 AR_PHY_WATCHDOG_IDLE_MASK |
1367 (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2)));
1368
1369 ath_print(common, ATH_DBG_RESET,
1370 "Enabled BB Watchdog timeout (%u ms)\n",
1371 idle_tmo_ms);
1372}
1373
1374void ar9003_hw_bb_watchdog_read(struct ath_hw *ah)
1375{
1376 /*
1377 * we want to avoid printing in ISR context so we save the
1378 * watchdog status to be printed later in bottom half context.
1379 */
1380 ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS);
1381
1382 /*
1383 * the watchdog timer should reset on status read but to be sure
1384 * sure we write 0 to the watchdog status bit.
1385 */
1386 REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS,
1387 ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR);
1388}
1389
1390void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah)
1391{
1392 struct ath_common *common = ath9k_hw_common(ah);
1393 u32 rxc_pcnt = 0, rxf_pcnt = 0, txf_pcnt = 0, status;
1394
1395 if (likely(!(common->debug_mask & ATH_DBG_RESET)))
1396 return;
1397
1398 status = ah->bb_watchdog_last_status;
1399 ath_print(common, ATH_DBG_RESET,
1400 "\n==== BB update: BB status=0x%08x ====\n", status);
1401 ath_print(common, ATH_DBG_RESET,
1402 "** BB state: wd=%u det=%u rdar=%u rOFDM=%d "
1403 "rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
1404 MS(status, AR_PHY_WATCHDOG_INFO),
1405 MS(status, AR_PHY_WATCHDOG_DET_HANG),
1406 MS(status, AR_PHY_WATCHDOG_RADAR_SM),
1407 MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM),
1408 MS(status, AR_PHY_WATCHDOG_RX_CCK_SM),
1409 MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM),
1410 MS(status, AR_PHY_WATCHDOG_TX_CCK_SM),
1411 MS(status, AR_PHY_WATCHDOG_AGC_SM),
1412 MS(status,AR_PHY_WATCHDOG_SRCH_SM));
1413
1414 ath_print(common, ATH_DBG_RESET,
1415 "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
1416 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1),
1417 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2));
1418 ath_print(common, ATH_DBG_RESET,
1419 "** BB mode: BB_gen_controls=0x%08x **\n",
1420 REG_READ(ah, AR_PHY_GEN_CTRL));
1421
1422 if (ath9k_hw_GetMibCycleCountsPct(ah, &rxc_pcnt, &rxf_pcnt, &txf_pcnt))
1423 ath_print(common, ATH_DBG_RESET,
1424 "** BB busy times: rx_clear=%d%%, "
1425 "rx_frame=%d%%, tx_frame=%d%% **\n",
1426 rxc_pcnt, rxf_pcnt, txf_pcnt);
1427
1428 ath_print(common, ATH_DBG_RESET,
1429 "==== BB update: done ====\n\n");
1430}
1431EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info);
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